From d122b9b58025a46da59e2929050cc208d12f19f9 Mon Sep 17 00:00:00 2001 From: tijs <67372590+TijsBellefroid@users.noreply.github.com> Date: Wed, 1 Jul 2026 14:39:21 +0200 Subject: [PATCH] Added more ARMCortexM registers --- archinfo/arch_arm.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/archinfo/arch_arm.py b/archinfo/arch_arm.py index c66a6cca..f35d7a46 100644 --- a/archinfo/arch_arm.py +++ b/archinfo/arch_arm.py @@ -446,7 +446,9 @@ class ArchARMCortexM(ArchARMEL): Register(name="msplim", size=4, general_purpose=True), Register(name="msplim_s", size=4, general_purpose=True), Register(name="msplim_ns", size=4, general_purpose=True), - Register(name="msplim_ns", size=4, general_purpose=True), + Register(name="psplim", size=4, general_purpose=True), + Register(name="psplim_s", size=4, general_purpose=True), + Register(name="psplim_ns", size=4, general_purpose=True), # additional stack pointers for secure/non_secure world Register(name="sp_process", size=4, general_purpose=True), Register(name="sp_process_s", size=4, general_purpose=True), @@ -507,6 +509,7 @@ class ArchARMCortexM(ArchARMEL): # Bit 1: Whether we use MSP (0) or PSP (1) # Bit 0: Thread mode privilege level. 0 for privileged, 1 for unprivileged. Register(name="control", size=4, default_value=(0, False, None)), + Register(name="control_ns", size=4, default_value=(0, False, None)), ] # Special handling of CM mode in *stone