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anischalianischali
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‎arch/riscv/Kconfig.socs‎

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@@ -15,6 +15,19 @@ config BOARD_ERIZO_GENERIC
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depends on SOC_ERIZO
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def_bool y
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config SOC_SPACEMIT_K1
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bool "Spacemit K1 SoC"
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depends on ARCH_RV64I
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select HAS_DEBUG_LL
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select HAS_NMON
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select USE_COMPRESSED_DTB
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select RISCV_M_MODE
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select RISCV_TIMER
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config BOARD_SPACEMIT_K1
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depends on SOC_SPACEMIT_K1
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def_bool y
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config SOC_VIRT
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bool "QEMU Virt Machine"
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select RISCV_S_MODE

‎arch/riscv/boards/Makefile‎

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@@ -5,3 +5,4 @@ obj-$(CONFIG_BOARD_HIFIVE) += hifive/
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obj-$(CONFIG_BOARD_BEAGLEV) += beaglev/
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obj-$(CONFIG_BOARD_LITEX_LINUX) += litex-linux/
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obj-$(CONFIG_BOARD_RISCVEMU) += riscvemu/
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obj-$(CONFIG_BOARD_SPACEMIT_K1) += spacemit_k1/

‎arch/riscv/boards/spacemit_k1/Makefile‎

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# SPDX-License-Identifier: GPL-2.0
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pbl-y += lowlevel.o

‎arch/riscv/boards/spacemit_k1/lowlevel.c‎

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// SPDX-License-Identifier: GPL-2.0-only
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#include <common.h>
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#include <asm/barebox-riscv.h>
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#include <debug_ll.h>
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#include <asm/riscv_nmon.h>
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ENTRY_FUNCTION(start_spacemit_k1, a0, a1, a2)
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{
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extern char __dtb_z_spacemit_k1_start[];
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void *fdt;
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/* On POR, we are running from read-only memory here. */
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fdt = __dtb_z_spacemit_k1_start + get_runtime_offset();
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barebox_riscv_supervisor_entry(0x80000000, SZ_128M, a0, fdt);
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}

‎arch/riscv/configs/rv64i_defconfig‎

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@@ -2,6 +2,7 @@ CONFIG_ARCH_RV64I=y
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CONFIG_SOC_VIRT=y
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CONFIG_SOC_SIFIVE=y
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CONFIG_BOARD_HIFIVE=y
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CONFIG_BOARD_SPACEMIT_K1=y
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CONFIG_SOC_STARFIVE=y
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CONFIG_BOARD_BEAGLEV=y
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CONFIG_BOARD_BEAGLEV_BETA=y

‎arch/riscv/dts/Makefile‎

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@@ -9,6 +9,7 @@ pbl-$(CONFIG_BOARD_HIFIVE) += hifive-unmatched-a00.dtb.o \
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hifive-unleashed-a00.dtb.o
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pbl-$(CONFIG_BOARD_BEAGLEV) += jh7100-beaglev-starlight.dtb.o
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pbl-$(CONFIG_BOARD_LITEX_LINUX) += litex-linux.dtb.o
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pbl-$(CONFIG_BOARD_SPACEMIT_K1) += spacemit_k1.dtb.o
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clean-files := *.dtb *.dtb.S .*.dtc .*.pre .*.dts *.dtb.z
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clean-files += *.dtbo *.dtbo.S .*.dtso

‎arch/riscv/dts/k1-pinctrl.dtsi‎

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// SPDX-License-Identifier: GPL-2.0 OR MIT
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/*
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* Copyright (c) 2024 Yixun Lan <dlan@gentoo.org>
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*/
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#include <dt-bindings/gpio/gpio.h>
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#define K1_PADCONF(pin, func) (((pin) << 16) | (func))
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/* Map GPIO pin to each bank's <index, offset> */
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#define K1_GPIO(x) (x / 32) (x % 32)
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&pinctrl {
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gmac0_cfg: gmac0-cfg {
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gmac0-pins {
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pinmux = <K1_PADCONF(0, 1)>, /* gmac0_rxdv */
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<K1_PADCONF(1, 1)>, /* gmac0_rx_d0 */
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<K1_PADCONF(2, 1)>, /* gmac0_rx_d1 */
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<K1_PADCONF(3, 1)>, /* gmac0_rx_clk */
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<K1_PADCONF(4, 1)>, /* gmac0_rx_d2 */
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<K1_PADCONF(5, 1)>, /* gmac0_rx_d3 */
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<K1_PADCONF(6, 1)>, /* gmac0_tx_d0 */
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<K1_PADCONF(7, 1)>, /* gmac0_tx_d1 */
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<K1_PADCONF(8, 1)>, /* gmac0_tx */
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<K1_PADCONF(9, 1)>, /* gmac0_tx_d2 */
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<K1_PADCONF(10, 1)>, /* gmac0_tx_d3 */
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<K1_PADCONF(11, 1)>, /* gmac0_tx_en */
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<K1_PADCONF(12, 1)>, /* gmac0_mdc */
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<K1_PADCONF(13, 1)>, /* gmac0_mdio */
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<K1_PADCONF(14, 1)>, /* gmac0_int_n */
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<K1_PADCONF(45, 1)>; /* gmac0_clk_ref */
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bias-pull-up = <0>;
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drive-strength = <21>;
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};
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};
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gmac1_cfg: gmac1-cfg {
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gmac1-pins {
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pinmux = <K1_PADCONF(29, 1)>, /* gmac1_rxdv */
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<K1_PADCONF(30, 1)>, /* gmac1_rx_d0 */
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<K1_PADCONF(31, 1)>, /* gmac1_rx_d1 */
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<K1_PADCONF(32, 1)>, /* gmac1_rx_clk */
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<K1_PADCONF(33, 1)>, /* gmac1_rx_d2 */
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<K1_PADCONF(34, 1)>, /* gmac1_rx_d3 */
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<K1_PADCONF(35, 1)>, /* gmac1_tx_d0 */
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<K1_PADCONF(36, 1)>, /* gmac1_tx_d1 */
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<K1_PADCONF(37, 1)>, /* gmac1_tx */
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<K1_PADCONF(38, 1)>, /* gmac1_tx_d2 */
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<K1_PADCONF(39, 1)>, /* gmac1_tx_d3 */
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<K1_PADCONF(40, 1)>, /* gmac1_tx_en */
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<K1_PADCONF(41, 1)>, /* gmac1_mdc */
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<K1_PADCONF(42, 1)>, /* gmac1_mdio */
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<K1_PADCONF(43, 1)>, /* gmac1_int_n */
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<K1_PADCONF(46, 1)>; /* gmac1_clk_ref */
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bias-pull-up = <0>;
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drive-strength = <21>;
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};
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};
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uart0_2_cfg: uart0-2-cfg {
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uart0-2-pins {
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pinmux = <K1_PADCONF(68, 2)>,
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<K1_PADCONF(69, 2)>;
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bias-pull-up = <0>;
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drive-strength = <32>;
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};
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};
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pwm14_1_cfg: pwm14-1-cfg {
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pwm14-1-pins {
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pinmux = <K1_PADCONF(44, 4)>;
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bias-pull-up = <0>;
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drive-strength = <32>;
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};
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};
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};

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