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FIX: Improve extension unit tests using ANSYS-HSD_V1 file (#6043)
Co-authored-by: pyansys-ci-bot <92810346+pyansys-ci-bot@users.noreply.github.com>
1 parent 86cff64 commit ba2bd05

7 files changed

Lines changed: 46 additions & 21 deletions

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doc/changelog.d/6043.fixed.md

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1 @@
1+
Improve extension unit tests using ANSYS-HSD_V1 file

src/ansys/aedt/core/workflows/hfss/choke_designer.py

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -494,6 +494,9 @@ def main(extension_args):
494494
if temp_dir.exists():
495495
shutil.rmtree(temp_dir, ignore_errors=True)
496496

497+
if extension_args["is_test"]:
498+
hfss.close_project()
499+
497500
if not extension_args["is_test"]: # pragma: no cover
498501
app.release_desktop(False, False)
499502
return True

src/ansys/aedt/core/workflows/hfss3dlayout/cutout.py

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -290,10 +290,8 @@ def main(extension_args):
290290
edb.nets.find_and_fix_disjoint_nets(reference)
291291
edb.close_edb()
292292

293-
# Open layout in HFSS 3D Layout
294-
Hfss3dLayout(str(new_path))
295-
296293
if not extension_args["is_test"]: # pragma: no cover
294+
Hfss3dLayout(str(new_path))
297295
app.logger.info("Project generated correctly.")
298296
app.release_desktop(False, False)
299297
return True

src/ansys/aedt/core/workflows/hfss3dlayout/post_layout_design_toolkit.py

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -98,7 +98,7 @@ def callback(self):
9898
self.selection_var.set("Please select two vias")
9999
return
100100

101-
h3d = self.master_ui.get_h3d
101+
h3d = self.master_ui.get_h3d()
102102
backend = BackendAntipad(h3d)
103103
backend.create(
104104
selected,
@@ -149,7 +149,8 @@ def create_ui(self, master):
149149

150150
def get_padstack_def(self):
151151
self.master_ui.get_selections(self.selection_var)
152-
pedb = self.master_ui.get_h3d.modeler.primitives.edb
152+
h3d = self.master_ui.get_h3d()
153+
pedb = h3d.modeler.primitives.edb
153154
temp = []
154155
selected = self.selection_var.get().split(",")
155156
for i in selected:
@@ -163,7 +164,7 @@ def get_padstack_def(self):
163164
def callback(self):
164165
selected = self.selection_var.get().split(",")
165166

166-
h3d = self.master_ui.get_h3d
167+
h3d = self.master_ui.get_h3d()
167168
backend = BackendMircoVia(h3d)
168169
new_edb_path = backend.create(
169170
selected,
@@ -188,7 +189,6 @@ def active_design(self):
188189
if odesign.GetDesignType() in ["HFSS 3D Layout Design"]:
189190
return desktop, oproject, odesign
190191

191-
@property
192192
def get_h3d(self):
193193
_, oproject, odesign = self.active_design
194194
project_name = oproject.GetName()

src/ansys/aedt/core/workflows/hfss3dlayout/via_clustering_extension.py

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -241,9 +241,10 @@ def main(extension_arguments):
241241
prim.delete()
242242
edb.save()
243243
edb.close_edb()
244-
h3d = Hfss3dLayout(new_aedb_path)
245-
h3d.logger.info("Project generated correctly.")
244+
246245
if not test_mode:
246+
h3d = Hfss3dLayout(new_aedb_path)
247+
h3d.logger.info("Project generated correctly.")
247248
h3d.release_desktop(False, False)
248249
return True
249250

src/ansys/aedt/core/workflows/project/configure_edb.py

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -338,6 +338,7 @@ def execute_export(self, file_path):
338338

339339
class ConfigureEdbBackend:
340340
def __init__(self, args, is_test=False):
341+
self.is_test = is_test
341342
if len(args["siwave_load"]): # pragma: no cover
342343
for i in args["siwave_load"]:
343344
self.execute_load_cfg_siw(**i)
@@ -381,17 +382,16 @@ def execute_load_cfg_siw(project_file, file_cfg_path, file_save_path): # pragma
381382
siw.save_project(fdir, fname)
382383
siw.quit_application()
383384

384-
@staticmethod
385-
def execute_load_cfg_aedt(project_file, file_cfg_path, file_save_path):
385+
def execute_load_cfg_aedt(self, project_file, file_cfg_path, file_save_path):
386386
fedb = Path(project_file).with_suffix(".aedb")
387387
edbapp = Edb(str(fedb), edbversion=version)
388388
edbapp.configuration.load(file_cfg_path)
389389
edbapp.configuration.run()
390390
edbapp.save_as(str(Path(file_save_path).with_suffix(".aedb")))
391391
edbapp.close()
392-
393-
h3d = Hfss3dLayout(str(Path(file_save_path).with_suffix(".aedb")))
394-
h3d.save_project()
392+
if not self.is_test:
393+
h3d = Hfss3dLayout(str(Path(file_save_path).with_suffix(".aedb")))
394+
h3d.save_project()
395395

396396
@staticmethod
397397
def execute_export_cfg_siw(project_file, file_path_save): # pragma: no cover
@@ -410,7 +410,7 @@ def execute_export_cfg_aedt(project_file, file_path_save):
410410

411411
def main(is_test=False, execute=""):
412412
if is_test:
413-
ConfigureEdbBackend(execute)
413+
ConfigureEdbBackend(execute, is_test)
414414
else: # pragma: no cover
415415

416416
app = ConfigureEdbFrontend()

tests/system/visualization/test_45_workflows.py

Lines changed: 28 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -199,6 +199,8 @@ def test_07_twinbuilder_convert_circuit(self, add_app):
199199

200200
assert main({"is_test": True})
201201

202+
aedtapp.close_project()
203+
202204
def test_08_configure_a3d(self, local_scratch):
203205
from ansys.aedt.core.workflows.project.configure_edb import main
204206

@@ -449,7 +451,7 @@ def test_10_push_excitation_3dl(self, local_scratch, desktop):
449451
# assert h3d.design_datasets
450452
h3d.close_project(h3d.project_name)
451453

452-
def test_11_cutout(self, add_app, local_scratch):
454+
def test_11_cutout(self, add_app):
453455
from ansys.aedt.core.workflows.hfss3dlayout.cutout import main
454456

455457
app = add_app("ANSYS-HSD_V1", application=ansys.aedt.core.Hfss3dLayout, subfolder=test_subfolder)
@@ -466,7 +468,7 @@ def test_11_cutout(self, add_app, local_scratch):
466468
)
467469
app.close_project()
468470

469-
def test_12_export_layout(self, add_app, local_scratch):
471+
def test_12_export_layout(self, add_app):
470472
from ansys.aedt.core.workflows.hfss3dlayout.export_layout import main
471473

472474
app = add_app("ANSYS-HSD_V1", application=ansys.aedt.core.Hfss3dLayout, subfolder=test_subfolder)
@@ -590,7 +592,7 @@ def test_18_via_merging(self, local_scratch):
590592
from ansys.aedt.core.workflows.hfss3dlayout.via_clustering_extension import main
591593

592594
file_path = os.path.join(local_scratch.path, "test_via_merging.aedb")
593-
new_file = os.path.join(local_scratch.path, "__test_via_merging.aedb")
595+
new_file = os.path.join(local_scratch.path, "new_test_via_merging.aedb")
594596
local_scratch.copyfolder(
595597
os.path.join(visualization_local_path, "example_models", "T45", "test_via_merging.aedb"), file_path
596598
)
@@ -754,7 +756,13 @@ def test_transformer_loss_distribution(self, add_app, local_scratch):
754756
def test_layout_design_toolkit_antipad_1(self, add_app, local_scratch):
755757
from ansys.aedt.core.workflows.hfss3dlayout.post_layout_design_toolkit import BackendAntipad
756758

757-
h3d = add_app("ANSYS-HSD_V1", application=ansys.aedt.core.Hfss3dLayout, subfolder=test_subfolder)
759+
file_path = os.path.join(local_scratch.path, "ANSYS-HSD_V1_antipad_1.aedb")
760+
761+
local_scratch.copyfolder(
762+
os.path.join(visualization_local_path, "example_models", "T45", "ANSYS-HSD_V1.aedb"), file_path
763+
)
764+
765+
h3d = add_app(file_path, application=ansys.aedt.core.Hfss3dLayout, just_open=True)
758766
h3d.save_project()
759767
app_antipad = BackendAntipad(h3d)
760768
app_antipad.create(selections=["Via79", "Via78"], radius="1mm", race_track=True)
@@ -764,7 +772,14 @@ def test_layout_design_toolkit_antipad_1(self, add_app, local_scratch):
764772
def test_layout_design_toolkit_antipad_2(self, add_app, local_scratch):
765773
from ansys.aedt.core.workflows.hfss3dlayout.post_layout_design_toolkit import BackendAntipad
766774

767-
h3d = add_app("ANSYS-HSD_V1", application=ansys.aedt.core.Hfss3dLayout, subfolder=test_subfolder)
775+
file_path = os.path.join(local_scratch.path, "ANSYS-HSD_V1_antipad_2.aedb")
776+
777+
local_scratch.copyfolder(
778+
os.path.join(visualization_local_path, "example_models", "T45", "ANSYS-HSD_V1.aedb"), file_path
779+
)
780+
781+
h3d = add_app(file_path, application=ansys.aedt.core.Hfss3dLayout, just_open=True)
782+
768783
h3d.save_project()
769784

770785
app_antipad = BackendAntipad(h3d)
@@ -775,7 +790,14 @@ def test_layout_design_toolkit_antipad_2(self, add_app, local_scratch):
775790
def test_layout_design_toolkit_micro_via(self, add_app, local_scratch):
776791
from ansys.aedt.core.workflows.hfss3dlayout.post_layout_design_toolkit import BackendMircoVia
777792

778-
h3d = add_app("ANSYS-HSD_V1", application=ansys.aedt.core.Hfss3dLayout, subfolder=test_subfolder)
793+
file_path = os.path.join(local_scratch.path, "ANSYS-HSD_V1_antipad_3.aedb")
794+
795+
local_scratch.copyfolder(
796+
os.path.join(visualization_local_path, "example_models", "T45", "ANSYS-HSD_V1.aedb"), file_path
797+
)
798+
799+
h3d = add_app(file_path, application=ansys.aedt.core.Hfss3dLayout, just_open=True)
800+
779801
h3d.save_project()
780802

781803
app_microvia = BackendMircoVia(h3d)

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