Can you please shed some light on this repo and othe related repos?

[udif]

Hi,

I see you have forked verilator and trying to integrate the surelog parser into the repo.
Is your repo already using the surelog SV parser instead of the Verilator original parser?
I've built your repo , but the minimal test I have ran shows no improvements in language handling over standard Verilator.

I also see this is not the only surelog related repo. I see your yosys fork also has a Surelog submodule.
Do you have a working Surelog based front end for Yosys?

What are your long term goals? Do you intend to merge your work back into the main Verilator tree?

Thanks!

[tgorochowik]

Hi

in this repository we are working towards adding a new frontend that can parse UHDM. And yes, we have a similar fork for yosys (the efforts to enable it in both goes in parallel).

UHDM (universal hardware data model) is a data model representation that Surelog can output.

So in reality, the flow goes like this:
Surelog->UHDM->Verilator
Surelog->UHDM->Yosys

You can find more details, examples and tests here: https://github.com/alainmarcel/uhdm-integration

Both tools are already somewhat working. Our first target was getting the Ibex core to work (it can be simulated with the new frontend with Verilator and synthesized with the new frontend with yosys). Currently, most of the effort is put into getting a whole EarlGrey design to work with the new frontend.

At the moment it may not necessarily be much better that the built-in parsers (in terms of language handling). But hopefully it will be in the future. As you can see the main goal here is to make those tools much more modular, we want to be able to separate the parser from the tool (fontend and backend separation). You can think of it as of LLVM of EDA tools - surelog is the first frontend we are working on, but not necessarily the only one. You may also be interested in a blog note we posted some time ago: https://antmicro.com/blog/2020/12/ibex-support-in-verilator-yosys-via-uhdm-surelog/

[udif]

Thanks,

This is more or less what I expected (I'm aware of UHDM), but I was hoping to see any README files indicating this, and a short status message.
Anyway, at the moment one of my biggest Verilator issues is not strictly the parser, but the way the parsing and elaboration is handled. More specifically, parametrized modules with an if/generate construct are always elaborated even when they shouldn't.

For example:

module a;
localparam A=1;
generate
if (A==0)
begin
b b_inst(.x(1'b0));
end
endgenerate
endmodule

module b;
endmodule

The code above fails in Verilator, passes in one of the Big3 simulators, and fails in another non-big3 commercial tool.
I have an existing code base with 3rd party IP that behaves similarly. I was hoping that the UHDM modifications also affects how and when the modules are elaborated, not only parsed.

[tgorochowik]

@udif it does affect it actually - Surelog does some initial elaboration and verilator/yosys gets uhdm with some elaboration already done.

Could you please create an issue with this code snippet in https://github.com/alainmarcel/surelog ? Please make sure to describe the exact problem and what your expectations are - I cannot promise what you want to achieve can be done, but it would be nice to have it there to start a discussion and possibly trigger some work towards this (if its needed)

[alaindargelas]

Joining this conversation a bit late, but Surelog/UHDM does exacly what you expect:

module a;
localparam A=1;
generate
if (A==0)
begin
b b_inst(.x(1'b0));
end
endgenerate
endmodule

module b;
endmodule

UHDM:

design: (work@a), id:10
|vpiName:work@a
|vpiElaborated:1
|uhdmallModules:
\_module: work@a (work@a), id:11 tests/ScratchPad.sv:1:1: , endln:9:10, parent:work@a, parID:10
  |vpiDefName:work@a
  |vpiFullName:work@a
  |vpiParamAssign:
  \_param_assign: , id:1, line:2:12, endln:2:15, parent:work@a, parID:11
    |vpiRhs:
    \_constant: , id:2, line:2:14, endln:2:15
      |vpiConstType:9
      |vpiDecompile:1
      |vpiSize:64
      |UINT:1
    |vpiLhs:
    \_parameter: (work@a.A), id:0, line:2:12, endln:2:15, parent:work@a, parID:11
      |vpiName:A
      |vpiFullName:work@a.A
      |vpiLocalParam:1
      |UINT:1
  |vpiParameter:
  \_parameter: (work@a.A), id:0, line:2:12, endln:2:15, parent:work@a, parID:11
|uhdmallModules:
\_module: work@b (work@b), id:12 tests/ScratchPad.sv:11:1: , endln:12:10, parent:work@a, parID:10
  |vpiDefName:work@b
  |vpiFullName:work@b
|uhdmtopModules:
\_module: work@a (work@a), id:13 tests/ScratchPad.sv:1:1: , endln:9:10
  |vpiDefName:work@a
  |vpiName:work@a
  |vpiParamAssign:
  \_param_assign: , id:4, line:2:12, endln:2:15, parent:work@a, parID:13
    |vpiRhs:
    \_constant: , id:5, line:2:14, endln:2:15
      |vpiConstType:9
      |vpiDecompile:1
      |vpiSize:64
      |UINT:1
    |vpiLhs:
    \_parameter: (work@a.A), id:14, line:2:12, endln:2:15, parent:work@a, parID:13
      |vpiName:A
      |vpiFullName:work@a.A
      |vpiLocalParam:1
      |UINT:1
  |vpiParameter:
  \_parameter: (work@a.A), id:14, line:2:12, endln:2:15, parent:work@a, parID:13

Change to:
parameter A=0
and UHDM will yield:

design: (work@a), id:14
|vpiName:work@a
|vpiElaborated:1
|uhdmallModules:
\_module: work@a (work@a), id:15 tests/ScratchPad.sv:1:1: , endln:9:10, parent:work@a, parID:14
  |vpiDefName:work@a
  |vpiFullName:work@a
  |vpiParamAssign:
  \_param_assign: , id:1, line:2:12, endln:2:15, parent:work@a, parID:15
    |vpiRhs:
    \_constant: , id:2, line:2:14, endln:2:15
      |vpiConstType:9
      |vpiDecompile:0
      |vpiSize:64
      |UINT:0
    |vpiLhs:
    \_parameter: (work@a.A), id:0, line:2:12, endln:2:15, parent:work@a, parID:15
      |vpiName:A
      |vpiFullName:work@a.A
      |vpiLocalParam:1
      |UINT:0
  |vpiParameter:
  \_parameter: (work@a.A), id:0, line:2:12, endln:2:15, parent:work@a, parID:15
|uhdmallModules:
\_module: work@b (work@b), id:16 tests/ScratchPad.sv:11:1: , endln:12:10, parent:work@a, parID:14
  |vpiDefName:work@b
  |vpiFullName:work@b
|uhdmtopModules:
\_module: work@a (work@a), id:17 tests/ScratchPad.sv:1:1: , endln:9:10
  |vpiDefName:work@a
  |vpiName:work@a
  |vpiGenScopeArray:
  \_gen_scope_array: (work@a.genblk1), id:22, line:4, parent:work@a, parID:17
    |vpiName:genblk1
    |vpiFullName:work@a.genblk1
    |vpiGenScope:
    \_gen_scope: (work@a.genblk1), id:23, parent:work@a.genblk1, parID:22
      |vpiFullName:work@a.genblk1
      |vpiModule:
      \_module: work@b (work@a.genblk1.b_inst), id:24 tests/ScratchPad.sv:6: , parent:work@a.genblk1, parID:23
        |vpiDefName:work@b
        |vpiName:b_inst
        |vpiFullName:work@a.genblk1.b_inst
        |vpiPort:
        \_port: (x), id:25, parent:work@a.genblk1.b_inst, parID:24
          |vpiName:x
          |vpiInstance:
          \_module: work@b (work@a.genblk1.b_inst), id:24 tests/ScratchPad.sv:6: , parent:work@a.genblk1, parID:23
          |vpiHighConn:
          \_constant: , id:12, line:6:13, endln:6:17
            |vpiConstType:3
            |vpiDecompile:1'b0
            |vpiSize:1
            |BIN:0
  |vpiParamAssign:
  \_param_assign: , id:4, line:2:12, endln:2:15, parent:work@a, parID:17
    |vpiRhs:
    \_constant: , id:5, line:2:14, endln:2:15
      |vpiConstType:9
      |vpiDecompile:0
      |vpiSize:64
      |UINT:0
    |vpiLhs:
    \_parameter: (work@a.A), id:18, line:2:12, endln:2:15, parent:work@a, parID:17
      |vpiName:A
      |vpiFullName:work@a.A
      |vpiLocalParam:1
      |UINT:0
  |vpiParameter:
  \_parameter: (work@a.A), id:18, line:2:12, endln:2:15, parent:work@a, parID:17