Address the memory limitation for running on FPGAs

[carlosedp]

I got a suggestion that one option to address the memory limitation for running Micropython on FPGAs is instantiating the ECP5 DP16KD directly similar to:

https://github.com/skristiansson/wb_sdram_ctrl/blob/master/rtl/verilog/dpram_ecp5.v

I understand that this will make the memory ECP5 bound but there are options for conditional on other platforms like here or using Chisel transformations to have multiple memory interfaces like https://chipyard.readthedocs.io/en/latest/Tools/Barstools.html#mapping-technology-srams-macrocompiler.

A bigger scope would be using the externam memory like SDRAM or DDRAM.