Any reason to have the Verilog emitter object on most modules

[carlosedp]

Is there a reason to have the object extending App on most module files like below?

import chisel3.stage.ChiselStage
...
...
object LoadStoreObj extends App {
  (new ChiselStage).emitVerilog(new LoadStoreWrapper(64, 128*1024, 50000000, "test.hex"))
}

This is only required on the main module (Core) that is used by the toplevel.

Can I submit a PR removing them?
Also can I reformat the whole code automatically using scalafmt?