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fdcavalcantiacassis
fdcavalcanti
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arch/risc-v: fix linker script manipulation on CMake for Espressif devices
This changes enables the use of the preprocessor function (nuttx_generate_preprocess_target) so it can properly process the linker scripts, instead of using the original ones (must process some `#ifdefs`). Signed-off-by: Filipe Cavalcanti <filipe.cavalcanti@espressif.com>
1 parent 19c1d86 commit 5adbddf

4 files changed

Lines changed: 86 additions & 85 deletions

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‎arch/risc-v/src/esp32c3/hal_esp32c3.cmake‎

Lines changed: 16 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -201,21 +201,22 @@ set(ESP_ROM_LD_DIR
201201
set(ESP_SOC_LD_DIR ${ESP_HAL_3RDPARTY_REPO}/components/soc/${CHIP_SERIES}/ld)
202202
set(ESP_RISCV_LD_DIR ${ESP_HAL_3RDPARTY_REPO}/components/riscv/ld)
203203

204-
target_link_options(
205-
nuttx
206-
PRIVATE
207-
-T${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.api.ld
208-
-T${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.bt_funcs.ld
209-
-T${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.eco3_bt_funcs.ld
210-
-T${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.eco3.ld
211-
-T${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.ld
212-
-T${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.libc.ld
213-
-T${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.libc-suboptimal_for_misaligned_mem.ld
214-
-T${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.libgcc.ld
215-
-T${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.newlib.ld
216-
-T${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.version.ld
217-
-T${ESP_SOC_LD_DIR}/${CHIP_SERIES}.peripherals.ld
218-
-T${ESP_RISCV_LD_DIR}/rom.api.ld)
204+
set(_esp32c3_rom_ld_files
205+
${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.api.ld
206+
${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.bt_funcs.ld
207+
${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.eco3_bt_funcs.ld
208+
${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.eco3.ld
209+
${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.ld
210+
${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.libc.ld
211+
${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.libc-suboptimal_for_misaligned_mem.ld
212+
${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.libgcc.ld
213+
${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.newlib.ld
214+
${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.version.ld
215+
${ESP_SOC_LD_DIR}/${CHIP_SERIES}.peripherals.ld
216+
${ESP_RISCV_LD_DIR}/rom.api.ld)
217+
218+
# Add these files to the GLOBAL PROPERTY LD_SCRIPT
219+
set_property(GLOBAL APPEND PROPERTY LD_SCRIPT ${_esp32c3_rom_ld_files})
219220

220221
# ##############################################################################
221222
# HAL Source Files

‎arch/risc-v/src/esp32c6/hal_esp32c6.cmake‎

Lines changed: 23 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -181,36 +181,36 @@ set(ESP_RISCV_LD_DIR ${ESP_HAL_3RDPARTY_REPO}/components/riscv/ld)
181181
set(ESP_WDT_LD_DIR
182182
${ESP_HAL_3RDPARTY_REPO}/components/esp_hal_wdt/${CHIP_SERIES})
183183

184-
target_link_options(
185-
nuttx
186-
PRIVATE
187-
-T${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.api.ld
188-
-T${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.coexist.ld
189-
-T${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.ld
190-
-T${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.libc.ld
191-
-T${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.libc-suboptimal_for_misaligned_mem.ld
192-
-T${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.libgcc.ld
193-
-T${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.net80211.ld
194-
-T${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.newlib.ld
195-
-T${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.phy.ld
196-
-T${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.pp.ld
197-
-T${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.version.ld
198-
-T${ESP_WDT_LD_DIR}/rom.wdt.ld
199-
-T${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.heap.ld
200-
-T${ESP_RISCV_LD_DIR}/rom.api.ld
201-
-T${ESP_SOC_LD_DIR}/${CHIP_SERIES}.peripherals.ld)
184+
set(_esp32c6_rom_ld_files
185+
${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.api.ld
186+
${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.coexist.ld
187+
${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.ld
188+
${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.libc.ld
189+
${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.libc-suboptimal_for_misaligned_mem.ld
190+
${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.libgcc.ld
191+
${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.net80211.ld
192+
${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.newlib.ld
193+
${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.phy.ld
194+
${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.pp.ld
195+
${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.version.ld
196+
${ESP_WDT_LD_DIR}/rom.wdt.ld
197+
${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.heap.ld
198+
${ESP_RISCV_LD_DIR}/rom.api.ld
199+
${ESP_SOC_LD_DIR}/${CHIP_SERIES}.peripherals.ld)
202200

203201
if(CONFIG_ESPRESSIF_USE_LP_CORE)
204-
target_link_options(
205-
nuttx PRIVATE
206-
-T${NUTTX_DIR}/arch/${CONFIG_ARCH}/src/board/scripts/ulp_aliases.ld)
202+
list(APPEND _esp32c6_rom_ld_files
203+
${NUTTX_DIR}/arch/${CONFIG_ARCH}/src/board/scripts/ulp_aliases.ld)
207204
endif()
208205

209206
if(CONFIG_ESPRESSIF_SPI_FLASH_USE_ROM_CODE)
210-
target_link_options(nuttx PRIVATE
211-
-T${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.spiflash.ld)
207+
list(APPEND _esp32c6_rom_ld_files
208+
${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.spiflash.ld)
212209
endif()
213210

211+
# Add these files to the GLOBAL PROPERTY LD_SCRIPT
212+
set_property(GLOBAL APPEND PROPERTY LD_SCRIPT ${_esp32c6_rom_ld_files})
213+
214214
# ##############################################################################
215215
# HAL Source Files (from hal_esp32c6.mk CHIP_CSRCS and CHIP_ASRCS)
216216
# ##############################################################################

‎arch/risc-v/src/esp32h2/hal_esp32h2.cmake‎

Lines changed: 21 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -179,32 +179,32 @@ set(ESP_RISCV_LD_DIR ${ESP_HAL_3RDPARTY_REPO}/components/riscv/ld)
179179
set(ESP_WDT_LD_DIR
180180
${ESP_HAL_3RDPARTY_REPO}/components/esp_hal_wdt/${CHIP_SERIES})
181181

182-
target_link_options(
183-
nuttx
184-
PRIVATE
185-
-T${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.api.ld
186-
-T${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.ld
187-
-T${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.libc.ld
188-
-T${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.libc-suboptimal_for_misaligned_mem.ld
189-
-T${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.libgcc.ld
190-
-T${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.newlib.ld
191-
-T${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.version.ld
192-
-T${ESP_WDT_LD_DIR}/rom.wdt.ld
193-
-T${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.heap.ld
194-
-T${ESP_RISCV_LD_DIR}/rom.api.ld
195-
-T${ESP_SOC_LD_DIR}/${CHIP_SERIES}.peripherals.ld)
182+
set(_esp32h2_rom_ld_files
183+
${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.api.ld
184+
${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.ld
185+
${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.libc.ld
186+
${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.libc-suboptimal_for_misaligned_mem.ld
187+
${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.libgcc.ld
188+
${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.newlib.ld
189+
${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.version.ld
190+
${ESP_WDT_LD_DIR}/rom.wdt.ld
191+
${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.heap.ld
192+
${ESP_RISCV_LD_DIR}/rom.api.ld
193+
${ESP_SOC_LD_DIR}/${CHIP_SERIES}.peripherals.ld)
196194

197195
if(CONFIG_ESPRESSIF_USE_LP_CORE)
198-
target_link_options(
199-
nuttx PRIVATE
200-
-T${NUTTX_DIR}/arch/${CONFIG_ARCH}/src/board/scripts/ulp_aliases.ld)
196+
list(APPEND _esp32h2_rom_ld_files
197+
${NUTTX_DIR}/arch/${CONFIG_ARCH}/src/board/scripts/ulp_aliases.ld)
201198
endif()
202199

203200
if(CONFIG_ESPRESSIF_SPI_FLASH_USE_ROM_CODE)
204-
target_link_options(nuttx PRIVATE
205-
-T${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.spiflash.ld)
201+
list(APPEND _esp32h2_rom_ld_files
202+
${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.spiflash.ld)
206203
endif()
207204

205+
# Add these files to the GLOBAL PROPERTY LD_SCRIPT
206+
set_property(GLOBAL APPEND PROPERTY LD_SCRIPT ${_esp32h2_rom_ld_files})
207+
208208
# ##############################################################################
209209
# HAL Source Files (from hal_esp32h2.mk CHIP_CSRCS and CHIP_ASRCS)
210210
# ##############################################################################
@@ -582,6 +582,7 @@ function(nuttx_generate_preprocess_target)
582582
COMMAND
583583
${PREPROCESS} -I${CMAKE_BINARY_DIR}/include -I${NUTTX_DIR}/include
584584
-I${NUTTX_CHIP_ABS_DIR} ${LD_SCRIPT_HAL_INCLUDE}
585-
${LD_SCRIPT_ADDITIONAL_INCLUDE} ${SOURCE_FILE} > ${TARGET_FILE}
585+
${LD_SCRIPT_ADDITIONAL_INCLUDE} -D__NuttX__ ${SOURCE_FILE} >
586+
${TARGET_FILE}
586587
DEPENDS ${SOURCE_FILE} ${DEPENDS})
587588
endfunction()

‎arch/risc-v/src/esp32p4/hal_esp32p4.cmake‎

Lines changed: 26 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -183,40 +183,38 @@ set(ESP_SOC_LD_DIR ${ESP_HAL_3RDPARTY_REPO}/components/soc/${CHIP_SERIES}/ld)
183183
set(ESP_RISCV_LD_DIR ${ESP_HAL_3RDPARTY_REPO}/components/riscv/ld)
184184

185185
if(CONFIG_ESP32P4_REV_MIN_300)
186-
target_link_options(
187-
nuttx
188-
PRIVATE
189-
-T${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.eco5.ld
190-
-T${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.eco5.libc.ld
191-
-T${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.eco5.libgcc.ld
192-
-T${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.eco5.newlib.ld)
186+
set(_esp32p4_rom_ld_files
187+
${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.eco5.ld
188+
${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.eco5.libc.ld
189+
${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.eco5.libgcc.ld
190+
${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.eco5.newlib.ld)
193191
else()
194-
target_link_options(
195-
nuttx
196-
PRIVATE
197-
-T${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.ld
198-
-T${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.libc.ld
199-
-T${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.libgcc.ld
200-
-T${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.newlib.ld)
192+
set(_esp32p4_rom_ld_files
193+
${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.ld
194+
${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.libc.ld
195+
${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.libgcc.ld
196+
${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.newlib.ld)
201197
endif()
202198

203-
target_link_options(
204-
nuttx
205-
PRIVATE
206-
-T${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.api.ld
207-
-T${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.version.ld
208-
-T${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.libc-suboptimal_for_misaligned_mem.ld
209-
-T${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.systimer.ld
210-
-T${ESP_SOC_LD_DIR}/${CHIP_SERIES}.peripherals.ld
211-
-T${ESP_RISCV_LD_DIR}/rom.api.ld)
199+
list(
200+
APPEND
201+
_esp32p4_rom_ld_files
202+
${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.api.ld
203+
${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.version.ld
204+
${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.libc-suboptimal_for_misaligned_mem.ld
205+
${ESP_ROM_LD_DIR}/${CHIP_SERIES}.rom.systimer.ld
206+
${ESP_SOC_LD_DIR}/${CHIP_SERIES}.peripherals.ld
207+
${ESP_RISCV_LD_DIR}/rom.api.ld)
212208

213209
# Review the path below when ULP core is implemented on CMake
214210
if(CONFIG_ESPRESSIF_USE_LP_CORE)
215-
target_link_options(
216-
nuttx PRIVATE
217-
-T${TOPDIR}/arch/${CONFIG_ARCH}/src/board/scripts/ulp_aliases.ld)
211+
list(APPEND _esp32p4_rom_ld_files
212+
${TOPDIR}/arch/${CONFIG_ARCH}/src/board/scripts/ulp_aliases.ld)
218213
endif()
219214

215+
# Add these files to the GLOBAL PROPERTY LD_SCRIPT
216+
set_property(GLOBAL APPEND PROPERTY LD_SCRIPT ${_esp32p4_rom_ld_files})
217+
220218
# ##############################################################################
221219
# HAL Source Files (from hal_esp32p4.mk CHIP_CSRCS)
222220
# ##############################################################################
@@ -505,6 +503,7 @@ function(nuttx_generate_preprocess_target)
505503
COMMAND
506504
${PREPROCESS} -I${CMAKE_BINARY_DIR}/include -I${NUTTX_DIR}/include
507505
-I${NUTTX_CHIP_ABS_DIR} ${LD_SCRIPT_HAL_INCLUDE}
508-
${LD_SCRIPT_ADDITIONAL_INCLUDE} ${SOURCE_FILE} > ${TARGET_FILE}
506+
${LD_SCRIPT_ADDITIONAL_INCLUDE} -D__NuttX__ ${SOURCE_FILE} >
507+
${TARGET_FILE}
509508
DEPENDS ${SOURCE_FILE} ${DEPENDS})
510509
endfunction()

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