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arch/stm32f0l0g0: add support for IWDG and WWDG
add IWDG and WWDG support for stm32f0l0g0. ported from arch/stm32. Signed-off-by: raiden00pl <[email protected]>
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18 files changed

+1752
-17
lines changed

18 files changed

+1752
-17
lines changed

Diff for: ‎Documentation/platforms/arm/stm32c0/index.rst

+2-2
Original file line numberDiff line numberDiff line change
@@ -35,8 +35,8 @@ CRC No
3535
ADC Yes
3636
TIM Yes
3737
IRTIM No
38-
IWDG No
39-
WWDG No
38+
IWDG Yes
39+
WWDG Yes
4040
I2C Yes
4141
USART Yes
4242
SPI Yes

Diff for: ‎Documentation/platforms/arm/stm32f0/index.rst

+2-2
Original file line numberDiff line numberDiff line change
@@ -40,8 +40,8 @@ COMP No
4040
TSC No
4141
TIM Yes
4242
IRTIM No
43-
IWDG No
44-
WWDG No
43+
IWDG Yes
44+
WWDG Yes
4545
RTC No
4646
I2C Yes
4747
USART Yes

Diff for: ‎Documentation/platforms/arm/stm32g0/index.rst

+2-2
Original file line numberDiff line numberDiff line change
@@ -39,8 +39,8 @@ AES Yes
3939
TIM Yes
4040
LPTIM No
4141
IRTIM No
42-
IWDG No
43-
WWDG No
42+
IWDG Yes
43+
WWDG Yes
4444
RTC No
4545
TAMP No
4646
I2C Yes

Diff for: ‎Documentation/platforms/arm/stm32l0/index.rst

+2-2
Original file line numberDiff line numberDiff line change
@@ -34,8 +34,8 @@ AES Yes
3434
RNG Yes
3535
TIM Yes
3636
LPTIM No
37-
IWDG No
38-
WWDG No
37+
IWDG Yes
38+
WWDG Yes
3939
RTC No
4040
I2C Yes
4141
USART Yes

Diff for: ‎arch/arm/src/stm32f0l0g0/CMakeLists.txt

+9
Original file line numberDiff line numberDiff line change
@@ -31,6 +31,7 @@ list(
3131
stm32_irq.c
3232
stm32_lowputc.c
3333
stm32_serial.c
34+
stm32_lsi.c
3435
stm32_rcc.c)
3536

3637
if(CONFIG_STM32F0L0G0_RTC_LSECLOCK OR CONFIG_LCD_LSECLOCK)
@@ -101,4 +102,12 @@ if(CONFIG_STM32F0L0G0_TIM)
101102
list(APPEND SRCS stm32_tim.c stm32_tim_lowerhalf.c)
102103
endif()
103104

105+
if(CONFIG_STM32F0L0G0_IWDG)
106+
list(APPEND SRCS stm32_iwdg.c)
107+
endif()
108+
109+
if(CONFIG_STM32F0L0G0_WWDG)
110+
list(APPEND SRCS stm32_wwdg.c)
111+
endif()
112+
104113
target_sources(arch PRIVATE ${SRCS})

Diff for: ‎arch/arm/src/stm32f0l0g0/Make.defs

+9-1
Original file line numberDiff line numberDiff line change
@@ -23,7 +23,7 @@
2323
include armv6-m/Make.defs
2424

2525
CHIP_CSRCS = stm32_start.c stm32_gpio.c stm32_exti_gpio.c stm32_irq.c
26-
CHIP_CSRCS += stm32_lowputc.c stm32_serial.c stm32_rcc.c
26+
CHIP_CSRCS += stm32_lowputc.c stm32_serial.c stm32_rcc.c stm32_lsi.c
2727

2828
ifneq ($(CONFIG_STM32F0L0G0_RTC_LSECLOCK)$(CONFIG_STM32F0L0G0_LCD_LSECLOCK),)
2929
CHIP_CSRCS += stm32_lse.c
@@ -92,3 +92,11 @@ endif
9292
ifeq ($(CONFIG_STM32F0L0G0_TIM),y)
9393
CHIP_CSRCS += stm32_tim.c stm32_tim_lowerhalf.c
9494
endif
95+
96+
ifeq ($(CONFIG_STM32F0L0G0_IWDG),y)
97+
CHIP_CSRCS += stm32_iwdg.c
98+
endif
99+
100+
ifeq ($(CONFIG_STM32F0L0G0_WWDG),y)
101+
CHIP_CSRCS += stm32_wwdg.c
102+
endif

Diff for: ‎arch/arm/src/stm32f0l0g0/hardware/stm32_dbgmcu.h

+80
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,80 @@
1+
/****************************************************************************
2+
* arch/arm/src/stm32f0l0g0/hardware/stm32_dbgmcu.h
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*
6+
* Licensed to the Apache Software Foundation (ASF) under one or more
7+
* contributor license agreements. See the NOTICE file distributed with
8+
* this work for additional information regarding copyright ownership. The
9+
* ASF licenses this file to you under the Apache License, Version 2.0 (the
10+
* "License"); you may not use this file except in compliance with the
11+
* License. You may obtain a copy of the License at
12+
*
13+
* http://www.apache.org/licenses/LICENSE-2.0
14+
*
15+
* Unless required by applicable law or agreed to in writing, software
16+
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
17+
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
18+
* License for the specific language governing permissions and limitations
19+
* under the License.
20+
*
21+
****************************************************************************/
22+
23+
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DBGMCU_H
24+
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DBGMCU_H
25+
26+
/****************************************************************************
27+
* Included Files
28+
****************************************************************************/
29+
30+
#include <nuttx/config.h>
31+
#include "chip.h"
32+
33+
/****************************************************************************
34+
* Pre-processor Definitions
35+
****************************************************************************/
36+
37+
/* Register Offsets *********************************************************/
38+
39+
#define STM32_DBGMCU_IDCODE 0x40015800 /* MCU identifier */
40+
#define STM32_DBGMCU_CR 0x40015804 /* MCU debug */
41+
#define STM32_DBGMCU_APB1_FZ 0x40015808 /* Debug MCU APB1 freeze register */
42+
#define STM32_DBGMCU_APB2_FZ 0x4001580c /* Debug MCU APB2 freeze register */
43+
44+
/* Register Bitfield Definitions ********************************************/
45+
46+
/* MCU identifier */
47+
48+
#define DBGMCU_IDCODE_DEVID_SHIFT (0) /* Bits 11-0: Device Identifier */
49+
#define DBGMCU_IDCODE_DEVID_MASK (0x0fff << DBGMCU_IDCODE_DEVID_SHIFT)
50+
#define DBGMCU_IDCODE_REVID_SHIFT (16) /* Bits 31-16: Revision Identifier */
51+
#define DBGMCU_IDCODE_REVID_MASK (0xffff << DBGMCU_IDCODE_REVID_SHIFT)
52+
53+
/* MCU debug */
54+
55+
#define DBGMCU_CR_SLEEP (1 << 0) /* Bit 0: Debug Sleep Mode */
56+
#define DBGMCU_CR_STOP (1 << 1) /* Bit 1: Debug Stop Mode */
57+
#define DBGMCU_CR_STANDBY (1 << 2) /* Bit 2: Debug Standby mode */
58+
59+
/* Debug MCU APB freeze register 1 */
60+
61+
#ifdef CONFIG_ARCH_CHIP_STM32C0
62+
# define DBGMCU_APB1_TIM2STOP (1 << 0) /* Bit 0: TIM2 stopped when core is halted */
63+
# define DBGMCU_APB1_TIM3STOP (1 << 1) /* Bit 1: TIM3 stopped when core is halted */
64+
# define DBGMCU_APB1_RTCSTOP (1 << 10) /* Bit 10: RTC stopped when core is halted */
65+
# define DBGMCU_APB1_WWDGSTOP (1 << 11) /* Bit 11: WWDG stopped when core is halted */
66+
# define DBGMCU_APB1_IWDGSTOP (1 << 12) /* Bit 12: IWDG stopped when core is halted */
67+
# define DBGMCU_APB1_I2C1STOP (1 << 21) /* Bit 21: SMBUS timeout mode stopped when Core is halted */
68+
#endif
69+
70+
/* Debug MCU APB freeze register 2 */
71+
72+
#ifdef CONFIG_ARCH_CHIP_STM32C0
73+
# define DBGMCU_APB1_TIM1STOP (1 << 11) /* Bit 1: TIM1 stopped when core is halted */
74+
# define DBGMCU_APB1_TIM14STOP (1 << 15) /* Bit 15: TIM14 stopped when core is halted */
75+
# define DBGMCU_APB1_TIM15STOP (1 << 16) /* Bit 16: TIM15 stopped when core is halted */
76+
# define DBGMCU_APB1_TIM16STOP (1 << 17) /* Bit 16: TIM16 stopped when core is halted */
77+
# define DBGMCU_APB1_TIM17STOP (1 << 18) /* Bit 16: TIM17 stopped when core is halted */
78+
#endif
79+
80+
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_DBGMCU_H */

Diff for: ‎arch/arm/src/stm32f0l0g0/hardware/stm32_wdg.h

+141
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,141 @@
1+
/****************************************************************************
2+
* arch/arm/src/stm32f0l0g0/hardware/stm32_wdg.h
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*
6+
* Licensed to the Apache Software Foundation (ASF) under one or more
7+
* contributor license agreements. See the NOTICE file distributed with
8+
* this work for additional information regarding copyright ownership. The
9+
* ASF licenses this file to you under the Apache License, Version 2.0 (the
10+
* "License"); you may not use this file except in compliance with the
11+
* License. You may obtain a copy of the License at
12+
*
13+
* http://www.apache.org/licenses/LICENSE-2.0
14+
*
15+
* Unless required by applicable law or agreed to in writing, software
16+
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
17+
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
18+
* License for the specific language governing permissions and limitations
19+
* under the License.
20+
*
21+
****************************************************************************/
22+
23+
#ifndef __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_WDG_H
24+
#define __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_WDG_H
25+
26+
/****************************************************************************
27+
* Included Files
28+
****************************************************************************/
29+
30+
#include <nuttx/config.h>
31+
32+
#include "chip.h"
33+
34+
/****************************************************************************
35+
* Pre-processor Definitions
36+
****************************************************************************/
37+
38+
/* Register Offsets *********************************************************/
39+
40+
#define STM32_IWDG_KR_OFFSET 0x0000 /* Key register (32-bit) */
41+
#define STM32_IWDG_PR_OFFSET 0x0004 /* Prescaler register (32-bit) */
42+
#define STM32_IWDG_RLR_OFFSET 0x0008 /* Reload register (32-bit) */
43+
#define STM32_IWDG_SR_OFFSET 0x000c /* Status register (32-bit) */
44+
#define STM32_IWDG_WINR_OFFSET 0x000c /* Window register (32-bit) */
45+
46+
#define STM32_WWDG_CR_OFFSET 0x0000 /* Control Register (32-bit) */
47+
#define STM32_WWDG_CFR_OFFSET 0x0004 /* Configuration register (32-bit) */
48+
#define STM32_WWDG_SR_OFFSET 0x0008 /* Status register (32-bit) */
49+
50+
/* Register Addresses *******************************************************/
51+
52+
#define STM32_IWDG_KR (STM32_IWDG_BASE+STM32_IWDG_KR_OFFSET)
53+
#define STM32_IWDG_PR (STM32_IWDG_BASE+STM32_IWDG_PR_OFFSET)
54+
#define STM32_IWDG_RLR (STM32_IWDG_BASE+STM32_IWDG_RLR_OFFSET)
55+
#define STM32_IWDG_SR (STM32_IWDG_BASE+STM32_IWDG_SR_OFFSET)
56+
#define STM32_IWDG_WINR (STM32_IWDG_BASE+STM32_IWDG_WINR_OFFSET)
57+
58+
#define STM32_WWDG_CR (STM32_WWDG_BASE+STM32_WWDG_CR_OFFSET)
59+
#define STM32_WWDG_CFR (STM32_WWDG_BASE+STM32_WWDG_CFR_OFFSET)
60+
#define STM32_WWDG_SR (STM32_WWDG_BASE+STM32_WWDG_SR_OFFSET)
61+
62+
/* Register Bitfield Definitions ********************************************/
63+
64+
/* Key register (32-bit) */
65+
66+
#define IWDG_KR_KEY_SHIFT (0) /* Bits 15-0: Key value (write only, read 0000h) */
67+
#define IWDG_KR_KEY_MASK (0xffff << IWDG_KR_KEY_SHIFT)
68+
69+
#define IWDG_KR_KEY_ENABLE (0x5555) /* Enable register access */
70+
#define IWDG_KR_KEY_DISABLE (0x0000) /* Disable register access */
71+
#define IWDG_KR_KEY_RELOAD (0xaaaa) /* Reload the counter */
72+
#define IWDG_KR_KEY_START (0xcccc) /* Start the watchdog */
73+
74+
/* Prescaler register (32-bit) */
75+
76+
#define IWDG_PR_SHIFT (0) /* Bits 2-0: Prescaler divider */
77+
#define IWDG_PR_MASK (7 << IWDG_PR_SHIFT)
78+
# define IWDG_PR_DIV4 (0 << IWDG_PR_SHIFT) /* 000: divider /4 */
79+
# define IWDG_PR_DIV8 (1 << IWDG_PR_SHIFT) /* 001: divider /8 */
80+
# define IWDG_PR_DIV16 (2 << IWDG_PR_SHIFT) /* 010: divider /16 */
81+
# define IWDG_PR_DIV32 (3 << IWDG_PR_SHIFT) /* 011: divider /32 */
82+
# define IWDG_PR_DIV64 (4 << IWDG_PR_SHIFT) /* 100: divider /64 */
83+
# define IWDG_PR_DIV128 (5 << IWDG_PR_SHIFT) /* 101: divider /128 */
84+
# define IWDG_PR_DIV256 (6 << IWDG_PR_SHIFT) /* 11x: divider /256 */
85+
86+
/* Reload register (32-bit) */
87+
88+
#define IWDG_RLR_RL_SHIFT (0) /* Bits11:0 RL[11:0]: Watchdog counter reload value */
89+
#define IWDG_RLR_RL_MASK (0x0fff << IWDG_RLR_RL_SHIFT)
90+
91+
#define IWDG_RLR_MAX (0xfff)
92+
93+
/* Status register (32-bit) */
94+
95+
#define IWDG_SR_PVU (1 << 0) /* Bit 0: Watchdog prescaler value update */
96+
#define IWDG_SR_RVU (1 << 1) /* Bit 1: Watchdog counter reload value update */
97+
#define IWDG_SR_WVU (1 << 2) /* Bit 2: */
98+
99+
/* Window register (32-bit) */
100+
101+
#define IWDG_WINR_SHIFT (0)
102+
#define IWDG_WINR_MASK (0x0fff << IWDG_WINR_SHIFT)
103+
104+
/* Control Register (32-bit) */
105+
106+
#define WWDG_CR_T_SHIFT (0) /* Bits 6:0 T[6:0]: 7-bit counter (MSB to LSB) */
107+
#define WWDG_CR_T_MASK (0x7f << WWDG_CR_T_SHIFT)
108+
# define WWDG_CR_T_MAX (0x3f << WWDG_CR_T_SHIFT)
109+
# define WWDG_CR_T_RESET (0x40 << WWDG_CR_T_SHIFT)
110+
#define WWDG_CR_WDGA (1 << 7) /* Bit 7: Activation bit */
111+
112+
/* Configuration register (32-bit) */
113+
114+
#define WWDG_CFR_W_SHIFT (0) /* Bits 6:0 W[6:0] 7-bit window value */
115+
#define WWDG_CFR_W_MASK (0x7f << WWDG_CFR_W_SHIFT)
116+
#define WWDG_CFR_WDGTB_SHIFT (7) /* Bits 8:7 [1:0]: Timer Base */
117+
#define WWDG_CFR_WDGTB_MASK (3 << WWDG_CFR_WDGTB_SHIFT)
118+
# define WWDG_CFR_PCLK1 (0 << WWDG_CFR_WDGTB_SHIFT) /* 00: CK Counter Clock (PCLK1 div 4096) div 1 */
119+
# define WWDG_CFR_PCLK1d2 (1 << WWDG_CFR_WDGTB_SHIFT) /* 01: CK Counter Clock (PCLK1 div 4096) div 2 */
120+
# define WWDG_CFR_PCLK1d4 (2 << WWDG_CFR_WDGTB_SHIFT) /* 10: CK Counter Clock (PCLK1 div 4096) div 4 */
121+
# define WWDG_CFR_PCLK1d8 (3 << WWDG_CFR_WDGTB_SHIFT) /* 11: CK Counter Clock (PCLK1 div 4096) div 8 */
122+
123+
#define WWDG_CFR_EWI (1 << 9) /* Bit 9: Early Wakeup Interrupt */
124+
125+
/* Status register (32-bit) */
126+
127+
#define WWDG_SR_EWIF (1 << 0) /* Bit 0: Early Wakeup Interrupt Flag */
128+
129+
/****************************************************************************
130+
* Public Types
131+
****************************************************************************/
132+
133+
/****************************************************************************
134+
* Public Data
135+
****************************************************************************/
136+
137+
/****************************************************************************
138+
* Public Functions Prototypes
139+
****************************************************************************/
140+
141+
#endif /* __ARCH_ARM_SRC_STM32F0L0G0_HARDWARE_STM32_WDG_H */

Diff for: ‎arch/arm/src/stm32f0l0g0/hardware/stm32c0_pwr.h

+2-8
Original file line numberDiff line numberDiff line change
@@ -34,6 +34,8 @@
3434
* Pre-processor Definitions
3535
****************************************************************************/
3636

37+
#undef HAVE_PWR_DBP /* No Disable backup write protection bit */
38+
3739
/* Register Offsets *********************************************************/
3840

3941
#define STM32_PWR_CR1_OFFSET 0x0000 /* Power control register 1 */
@@ -100,17 +102,9 @@
100102
# define PWR_CR1_LPMS_STANDBY (3 << PWR_CR1_LPMS_SHIFT) /* 011: Standby mode */
101103
# define PWR_CR1_LPMS_SHUTDOWN (4 << PWR_CR1_LPMS_SHIFT) /* 1xx: Shutdown mode */
102104

103-
#define PWR_CR1_FPDSTOP (1 << 3) /* Bit 3: Flash memory powered down during Stop mode */
104105
/* Bit 4: Reserved */
105106
#define PWR_CR1_FPDLPSLP (1 << 5) /* Bit 5: Flash memory powered down during Low-power sleep mode */
106107
/* Bits 6-31: Reserved */
107-
#define PWR_CR1_DBP (1 << 8) /* Bit 8: Disable Backup domain write protection */
108-
#define PWR_CR1_VOS_SHIFT (9) /* Bits 9-10: Voltage scaling range selection */
109-
#define PWR_CR1_VOS_MASK (3 << PWR_CR1_VOS_SHIFT)
110-
# define PWR_CR1_VOS_RANGE1 (1 << PWR_CR1_VOS_SHIFT) /* 01: Range 1 */
111-
# define PWR_CR1_VOS_RANGE2 (2 << PWR_CR1_VOS_SHIFT) /* 10: Range 2 */
112-
113-
#define PWR_CR1_LPR (1 << 14) /* Bit 14: Low-power run */
114108

115109
/* Power control register 2 */
116110

Diff for: ‎arch/arm/src/stm32f0l0g0/hardware/stm32f0_pwr.h

+1
Original file line numberDiff line numberDiff line change
@@ -34,6 +34,7 @@
3434
* Pre-processor Definitions
3535
****************************************************************************/
3636

37+
#define HAVE_PWR_DBP 1
3738
#undef HAVE_PWR_WKUP2
3839
#undef HAVE_PWR_WKUP3
3940

Diff for: ‎arch/arm/src/stm32f0l0g0/hardware/stm32g0_pwr.h

+2
Original file line numberDiff line numberDiff line change
@@ -34,6 +34,8 @@
3434
* Pre-processor Definitions
3535
****************************************************************************/
3636

37+
#define HAVE_PWR_DBP 1
38+
3739
/* Register Offsets *********************************************************/
3840

3941
#define STM32_PWR_CR1_OFFSET 0x0000 /* Power control register 1 */

Diff for: ‎arch/arm/src/stm32f0l0g0/hardware/stm32l0_pwr.h

+1
Original file line numberDiff line numberDiff line change
@@ -36,6 +36,7 @@
3636

3737
#define HAVE_PWR_WKUP2 1
3838
#define HAVE_PWR_WKUP3 1
39+
#define HAVE_PWR_DBP 1
3940

4041
/* Register Offsets *********************************************************/
4142

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