@@ -435,10 +435,17 @@ static void rts5228_init_from_cfg(struct rtsx_pcr *pcr)
435435 option -> ltr_enabled = false;
436436 }
437437 }
438+
439+ if (rtsx_check_dev_flag (pcr , ASPM_L1_1_EN | ASPM_L1_2_EN
440+ | PM_L1_1_EN | PM_L1_2_EN ))
441+ option -> force_clkreq_0 = false;
442+ else
443+ option -> force_clkreq_0 = true;
438444}
439445
440446static int rts5228_extra_init_hw (struct rtsx_pcr * pcr )
441447{
448+ struct rtsx_cr_option * option = & pcr -> option ;
442449
443450 rtsx_pci_write_register (pcr , RTS5228_AUTOLOAD_CFG1 ,
444451 CD_RESUME_EN_MASK , CD_RESUME_EN_MASK );
@@ -469,6 +476,17 @@ static int rts5228_extra_init_hw(struct rtsx_pcr *pcr)
469476 else
470477 rtsx_pci_write_register (pcr , PETXCFG , 0x30 , 0x00 );
471478
479+ /*
480+ * If u_force_clkreq_0 is enabled, CLKREQ# PIN will be forced
481+ * to drive low, and we forcibly request clock.
482+ */
483+ if (option -> force_clkreq_0 )
484+ rtsx_pci_write_register (pcr , PETXCFG ,
485+ FORCE_CLKREQ_DELINK_MASK , FORCE_CLKREQ_LOW );
486+ else
487+ rtsx_pci_write_register (pcr , PETXCFG ,
488+ FORCE_CLKREQ_DELINK_MASK , FORCE_CLKREQ_HIGH );
489+
472490 rtsx_pci_write_register (pcr , PWD_SUSPEND_EN , 0xFF , 0xFB );
473491
474492 if (pcr -> rtd3_en ) {
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