It appears the Wire library only configures the I2C SDA/SCL pins in CMOS mode when a SCI port is selected
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R_IOPORT_PinCfg(&g_ioport_ctrl, g_pin_cfg[sda_pin].pin, (uint32_t) (IOPORT_CFG_PULLUP_ENABLE | IOPORT_CFG_PERIPHERAL_PIN | ioport_sda)); |
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R_IOPORT_PinCfg(&g_ioport_ctrl, g_pin_cfg[scl_pin].pin, (uint32_t) (IOPORT_CFG_PULLUP_ENABLE | IOPORT_CFG_PERIPHERAL_PIN | ioport_scl)); |
The pin mode flags should probably read:
(uint32_t) (IOPORT_CFG_PULLUP_ENABLE | IOPORT_CFG_PERIPHERAL_PIN | IOPORT_CFG_NMOS_ENABLE | ioport_sda)
To activate the pins in open drain mode rather than CMOS mode.
I'm actually not sure if this doesn't affect the standard IIC module too, as far as I know the pin mode configuration process that would be used in the FSP is the same. I would have thought someone would have noticed a poor performing IIC port by now. For now I have identified it on my XIAO RA4M1 on the No. 2 I2C channel (D6 and D7 on that kit), after chasing erratic communications down with an oscilloscope. The nature is that the runt pulses sometimes do pass the data so it appears as though the communications is only erratic.
It appears the Wire library only configures the I2C SDA/SCL pins in CMOS mode when a SCI port is selected
ArduinoCore-renesas/libraries/Wire/Wire.cpp
Lines 255 to 256 in 99f8ee4
The pin mode flags should probably read:
(uint32_t) (IOPORT_CFG_PULLUP_ENABLE | IOPORT_CFG_PERIPHERAL_PIN | IOPORT_CFG_NMOS_ENABLE | ioport_sda)To activate the pins in open drain mode rather than CMOS mode.
I'm actually not sure if this doesn't affect the standard IIC module too, as far as I know the pin mode configuration process that would be used in the FSP is the same. I would have thought someone would have noticed a poor performing IIC port by now. For now I have identified it on my XIAO RA4M1 on the No. 2 I2C channel (D6 and D7 on that kit), after chasing erratic communications down with an oscilloscope. The nature is that the runt pulses sometimes do pass the data so it appears as though the communications is only erratic.