Automerge: [AArch64] Recombine SETCCCARRY for legalized unsigned compares (#204504)

Type legalization can turn wide unsigned compares into SETCCCARRY nodes
fed by USUBO carry results, hiding the original high/low compare shape
from the existing CCMP conjunction/disjunction lowering.

Add an AArch64 DAG combine for SETCCCARRY that recognizes these
legalized wide-compare patterns and rebuilds them as SETCC plus AND/OR,
exposing them to the existing CCMP lowering.

This is separated from llvm/llvm-project#181822.

Author: clingfei

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

@@ -1204,6 +1204,7 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
   // Try and combine setcc/select_cc with csel and bool-vector bitcasts.
   setTargetDAGCombine(ISD::SETCC);
   setTargetDAGCombine(ISD::SELECT_CC);
+  setTargetDAGCombine(ISD::SETCCCARRY);
 
   setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
 
@@ -28222,6 +28223,40 @@ static SDValue performSETCCCombine(SDNode *N,
   return SDValue();
 }
 
+static SDValue performSETCCCARRYCombine(SDNode *N, SelectionDAG &DAG) {
+  assert(N->getOpcode() == ISD::SETCCCARRY && "Unexpected opcode!");
+
+  // Rebuild narrow high/low compares from type-legalized wide unsigned compares
+  // so the existing CCMP conjunction/disjunction lowering can handle them.
+  SDValue HiLHS = N->getOperand(0);
+  SDValue HiRHS = N->getOperand(1);
+  SDValue Carry = N->getOperand(2);
+  ISD::CondCode Cond = cast<CondCodeSDNode>(N->getOperand(3))->get();
+  if (Cond != ISD::SETULT || Carry.getOpcode() != ISD::USUBO ||
+      Carry.getResNo() != 1)
+    return SDValue();
+
+  if (!isNullConstant(HiLHS) && !isNullConstant(HiRHS))
+    return SDValue();
+
+  SDValue LoLHS = Carry.getOperand(0);
+  SDValue LoRHS = Carry.getOperand(1);
+  if (!isa<ConstantSDNode>(LoLHS) && !isa<ConstantSDNode>(LoRHS))
+    return SDValue();
+
+  EVT VT = N->getValueType(0);
+  SDLoc DL(N);
+
+  SDValue LoCmp = DAG.getSetCC(DL, VT, LoLHS, LoRHS, ISD::SETULT);
+  if (isNullConstant(HiRHS)) {
+    SDValue HiEq = DAG.getSetCC(DL, VT, HiLHS, HiRHS, ISD::SETEQ);
+    return DAG.getNode(ISD::AND, DL, VT, HiEq, LoCmp);
+  }
+
+  SDValue HiNe = DAG.getSetCC(DL, VT, HiRHS, HiLHS, ISD::SETNE);
+  return DAG.getNode(ISD::OR, DL, VT, HiNe, LoCmp);
+}
+
 static SDValue performSELECT_CCCombine(SDNode *N,
                                        TargetLowering::DAGCombinerInfo &DCI,
                                        SelectionDAG &DAG) {
@@ -30154,6 +30189,8 @@ SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
     return performVSelectCombine(N, DCI, Subtarget);
   case ISD::SETCC:
     return performSETCCCombine(N, DCI, DAG);
+  case ISD::SETCCCARRY:
+    return performSETCCCARRYCombine(N, DAG);
   case ISD::LOAD:
     return performLOADCombine(N, DCI, DAG, Subtarget);
   case ISD::STORE:

llvm/test/CodeGen/AArch64/i128-cmp.ll

@@ -323,3 +323,52 @@ exit:
     ret void
 }
 
+define i1 @cmp_i128_ult_small_const(i128 %a) {
+; CHECK-LABEL: cmp_i128_ult_small_const:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    cmp x1, #0
+; CHECK-NEXT:    ccmp x0, #7, #2, eq
+; CHECK-NEXT:    cset w0, lo
+; CHECK-NEXT:    ret
+    %cmp = icmp ult i128 %a, 7
+    ret i1 %cmp
+}
+
+define i1 @cmp_i128_small_const_ult(i128 %a) {
+; CHECK-LABEL: cmp_i128_small_const_ult:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    cmp x1, #0
+; CHECK-NEXT:    ccmp x0, #7, #2, eq
+; CHECK-NEXT:    cset w0, hi
+; CHECK-NEXT:    ret
+    %cmp = icmp ult i128 7, %a
+    ret i1 %cmp
+}
+
+define i1 @cmp_i128_ult_small_const_and_i64(i128 %a, i64 %b) {
+; CHECK-LABEL: cmp_i128_ult_small_const_and_i64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    cmp x0, #7
+; CHECK-NEXT:    ccmp x2, #11, #2, lo
+; CHECK-NEXT:    ccmp x1, #0, #0, lo
+; CHECK-NEXT:    cset w0, eq
+; CHECK-NEXT:    ret
+    %wide = icmp ult i128 %a, 7
+    %narrow = icmp ult i64 %b, 11
+    %cmp = and i1 %wide, %narrow
+    ret i1 %cmp
+}
+
+define i1 @cmp_i128_small_const_ult_or_i64(i128 %a, i64 %b) {
+; CHECK-LABEL: cmp_i128_small_const_ult_or_i64:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    cmp x1, #0
+; CHECK-NEXT:    ccmp x0, #7, #2, eq
+; CHECK-NEXT:    ccmp x2, #11, #0, ls
+; CHECK-NEXT:    cset w0, lo
+; CHECK-NEXT:    ret
+    %wide = icmp ult i128 7, %a
+    %narrow = icmp ult i64 %b, 11
+    %cmp = or i1 %wide, %narrow
+    ret i1 %cmp
+}