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[RISCV] Fold 26-bit frame-index offsets into Xqcilo/Xqcilia load/store/addi (#209315)
Extend frame-index addressing such that the sp-relative offset resolved for a stack access that fits within 26-bit and not 12-bits; folds directly into the wide Xqcilo/Xqcilia instructions. This is achieved by adding the support for the following: - Adding support for stack accesses to complex pattern `SelectAddrRegImm26` for 26-bit loads and stores - Adding support for frame index operand to qc.e.addi instruction - Allowing 26-bit offsets to fold into the loads and store instructions from qcilo/qcilia extension (cherry picked from commit 79d1db7)
1 parent b9c1e15 commit 5100381

5 files changed

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‎llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp‎

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@@ -3579,6 +3579,10 @@ bool RISCVDAGToDAGISel::SelectAddrRegImm(SDValue Addr, SDValue &Base,
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/// compressible) standard load/store instructions.
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bool RISCVDAGToDAGISel::SelectAddrRegImm26(SDValue Addr, SDValue &Base,
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SDValue &Offset) {
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if (SelectAddrFrameIndex(Addr, Base, Offset))
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return true;
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SDLoc DL(Addr);
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MVT VT = Addr.getSimpleValueType();
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@@ -3588,6 +3592,8 @@ bool RISCVDAGToDAGISel::SelectAddrRegImm26(SDValue Addr, SDValue &Base,
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// load/store.
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if (isInt<26>(CVal) && !isInt<12>(CVal)) {
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Base = Addr.getOperand(0);
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if (auto *FIN = dyn_cast<FrameIndexSDNode>(Base))
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), VT);
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Offset = CurDAG->getSignedTargetConstant(CVal, DL, VT);
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return true;
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}

‎llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td‎

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@@ -1635,6 +1635,13 @@ def : PatGprNoX0Simm26NoSimm12<or, QC_E_ORI>;
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def : PatGprNoX0Simm26NoSimm12<xor, QC_E_XORI>;
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} // Predicates = [HasVendorXqcilia, IsRV32]
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/// FrameIndex calculations
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let Predicates = [HasVendorXqcilia, IsRV32] in {
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def : Pat<(riscv_add_like frameindex:$fi, simm26_nosimm12:$offset),
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(QC_E_ADDI (iPTR (to_tframeindex $fi)), simm26_nosimm12:$offset)>;
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} // Predicates = [HasVendorXqcilia, IsRV32]
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/// Load/Store operations
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let Predicates = [HasVendorXqcilo, IsRV32], AddedComplexity = 2 in {

‎llvm/lib/Target/RISCV/RISCVInstrPredicates.td‎

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@@ -242,3 +242,25 @@ def isBaseStore
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SH,
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SB,
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]>>>;
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// Xqcilo 26-bit offset Loads (qc.e.lb, qc.e.lbu, qc.e.lh, qc.e.lhu, qc.e.lw)
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def isBaseQCLoad
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: TIIPredicate<"isBaseQCLoad",
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MCReturnStatement<
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CheckOpcode<[
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QC_E_LB,
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QC_E_LBU,
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QC_E_LH,
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QC_E_LHU,
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QC_E_LW
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]>>>;
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// Xqcilo 26-bit offset Stores (qc.e.sb, qc.e.sh, qc.e.sw)
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def isBaseQCStore
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: TIIPredicate<"isBaseQCStore",
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MCReturnStatement<
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CheckOpcode<[
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QC_E_SB,
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QC_E_SH,
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QC_E_SW
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]>>>;

‎llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp‎

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@@ -588,6 +588,7 @@ bool RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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if (!IsRVVSpill) {
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int64_t Val = Offset.getFixed();
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int64_t Lo12 = SignExtend64<12>(Val);
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int64_t Lo26 = SignExtend64<26>(Val);
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unsigned Opc = MI.getOpcode();
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if (Opc == RISCV::ADDI && !isInt<12>(Val)) {
@@ -614,6 +615,11 @@ bool RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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// instruction will add 4 to the immediate. If that would overflow 12
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// bits, we can't fold the offset.
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MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0);
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} else if (Opc == RISCV::QC_E_ADDI || RISCVInstrInfo::isBaseQCLoad(MI) ||
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RISCVInstrInfo::isBaseQCStore(MI)) {
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MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Lo26);
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Offset = StackOffset::get((uint64_t)Val - (uint64_t)Lo26,
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Offset.getScalable());
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} else {
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// We can encode an add with 12 bit signed immediate in the immediate
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// operand of our user instruction. As a result, the remaining

‎llvm/test/CodeGen/RISCV/xqcilo-xqcilia-frame-index.ll‎

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@@ -0,0 +1,113 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; Frame-index addressing for the Qualcomm Xqcilo/Xqcilia large-offset
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; instructions (qc.e.lw/qc.e.sw/qc.e.addi). Stack accesses whose resolved
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; sp-relative offset is a 26-bit (but not 12-bit) signed immediate fold the
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; offset directly into the wide instruction instead of materialising a base.
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;
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; RUN: llc < %s -mtriple=riscv32 -mattr=+xqcilo,+xqcilia -riscv-no-aliases \
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; RUN: | FileCheck %s
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; Load variant: A load at a large (simm26, not simm12) offset off a stack slot
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; folds the resolved frame offset into a single qc.e.lw. The offset-0 access
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; keeps the alloca live.
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define i32 @stack_fi_load(i32 %x) nounwind {
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; CHECK-LABEL: stack_fi_load:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: qc.e.addi sp, sp, -4000016
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; CHECK-NEXT: qc.e.lw a1, 3000016(sp)
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; CHECK-NEXT: c.mv a2, a0
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; CHECK-NEXT: c.mv a0, a1
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; CHECK-NEXT: c.swsp a2, 16(sp)
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; CHECK-NEXT: qc.e.addi sp, sp, 4000016
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; CHECK-NEXT: c.jr ra
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entry:
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%arr = alloca [4000000 x i8], align 4
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%p0 = getelementptr inbounds [4000000 x i8], ptr %arr, i32 0, i32 0
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store i32 %x, ptr %p0, align 4
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%p1 = getelementptr inbounds [4000000 x i8], ptr %arr, i32 0, i32 3000000
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%v = load i32, ptr %p1, align 4
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ret i32 %v
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}
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; Store variant: a store at a large (simm26, not simm12) offset off a stack slot
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; folds into a single qc.e.sw.
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define void @stack_fi_store(i32 %x) nounwind {
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; CHECK-LABEL: stack_fi_store:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: qc.e.addi sp, sp, -4000016
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; CHECK-NEXT: qc.e.sw a0, 3000016(sp)
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; CHECK-NEXT: c.swsp a0, 16(sp)
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; CHECK-NEXT: qc.e.addi sp, sp, 4000016
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; CHECK-NEXT: c.jr ra
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entry:
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%arr = alloca [4000000 x i8], align 4
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%p1 = getelementptr inbounds [4000000 x i8], ptr %arr, i32 0, i32 3000000
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store i32 %x, ptr %p1, align 4
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%p0 = getelementptr inbounds [4000000 x i8], ptr %arr, i32 0, i32 0
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store i32 %x, ptr %p0, align 4
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ret void
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}
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; The address of a large-offset stack element escapes via a call, so it must be
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; materialised as a value. The (frameindex + simm26) computation selects
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; QC_E_ADDI and folds the resolved 26-bit frame offset into it.
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declare void @use(ptr)
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define void @fi_addr_escapes(i32 %x) nounwind {
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; CHECK-LABEL: fi_addr_escapes:
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; CHECK: # %bb.0:
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; CHECK-NEXT: c.addi16sp sp, -256
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; CHECK-NEXT: c.swsp ra, 252(sp) # 4-byte Folded Spill
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; CHECK-NEXT: qc.e.addi sp, sp, -3999760
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; CHECK-NEXT: qc.e.addi a0, sp, 3000012
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; CHECK-NEXT: call use
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; CHECK-NEXT: c.addi4spn a0, sp, 12
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; CHECK-NEXT: call use
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; CHECK-NEXT: qc.e.addi sp, sp, 3999760
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; CHECK-NEXT: c.lwsp ra, 252(sp) # 4-byte Folded Reload
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; CHECK-NEXT: c.addi16sp sp, 256
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; CHECK-NEXT: c.jr ra
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%arr = alloca [4000000 x i8], align 4
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%p1 = getelementptr inbounds [4000000 x i8], ptr %arr, i32 0, i32 3000000
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call void @use(ptr %p1)
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%p0 = getelementptr inbounds [4000000 x i8], ptr %arr, i32 0, i32 0
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call void @use(ptr %p0)
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ret void
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}
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; A bare frame index (offset 0) whose slot resolves to a large (simm26, not
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; simm12) sp-relative offset. The small alloca is placed first so the allocator
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; lays it out high in the frame (sp + ~8204).
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define i32 @bare_fi_high_frame() nounwind {
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; CHECK-LABEL: bare_fi_high_frame:
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; CHECK: # %bb.0:
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; CHECK-NEXT: qc.e.addi sp, sp, -8208
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; CHECK-NEXT: c.li a0, 1
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; CHECK-NEXT: c.swsp a0, 12(sp)
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; CHECK-NEXT: qc.e.lw a0, 8204(sp)
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; CHECK-NEXT: qc.e.addi sp, sp, 8208
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; CHECK-NEXT: c.jr ra
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%small = alloca i32
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%big = alloca [8192 x i8], align 4
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%pb = getelementptr [8192 x i8], ptr %big, i32 0, i32 0
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store volatile i32 1, ptr %pb
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%v = load i32, ptr %small
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ret i32 %v
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}
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; Store variant of the bare-frame-index case.
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define void @bare_fi_high_frame_store(i32 %x) nounwind {
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; CHECK-LABEL: bare_fi_high_frame_store:
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; CHECK: # %bb.0:
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; CHECK-NEXT: qc.e.addi sp, sp, -8208
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; CHECK-NEXT: c.li a1, 1
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; CHECK-NEXT: c.swsp a1, 12(sp)
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; CHECK-NEXT: qc.e.sw a0, 8204(sp)
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; CHECK-NEXT: qc.e.addi sp, sp, 8208
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; CHECK-NEXT: c.jr ra
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%small = alloca i32
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%big = alloca [8192 x i8], align 4
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%pb = getelementptr [8192 x i8], ptr %big, i32 0, i32 0
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store volatile i32 1, ptr %pb
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store i32 %x, ptr %small
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ret void
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}

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