diff --git a/patch/u-boot/v2024.10/board_nanopi-r3s/0001-rockchip-rk3566-add-nanopi-r3s.patch b/patch/u-boot/v2024.10/board_nanopi-r3s/0001-rockchip-rk3566-add-nanopi-r3s.patch index f90dca2e5657..b40e10129b85 100644 --- a/patch/u-boot/v2024.10/board_nanopi-r3s/0001-rockchip-rk3566-add-nanopi-r3s.patch +++ b/patch/u-boot/v2024.10/board_nanopi-r3s/0001-rockchip-rk3566-add-nanopi-r3s.patch @@ -3,125 +3,18 @@ From: Werner Date: Sun, 9 Dec 2024 07:36:02 +0200 Subject: add support for Nanopi R3S - -diff --git a/dev/null b/arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi ---- /dev/null -+++ b/arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi -@@ -0,0 +1,25 @@ -+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT -+/* -+ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd. -+ * (http://www.friendlyelec.com) -+ * -+ * Copyright (c) 2023 Tianling Shen -+ * -+ * Copyright (c) 2024 Kevin Zhang -+ */ -+ -+#include "rk356x-u-boot.dtsi" -+ -+&sdhci { -+ cap-mmc-highspeed; -+ mmc-hs200-1_8v; -+ mmc-hs400-1_8v; -+ mmc-hs400-enhanced-strobe; -+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; -+}; -+ -+&vcc5v0_usb { -+ /delete-property/ regulator-always-on; -+ /delete-property/ regulator-boot-on; -+}; -+ - -diff --git a/dev/null b/configs/nanopi-r3s-rk3566_defconfig ---- /dev/null -+++ b/configs/nanopi-r3s-rk3566_defconfig -@@ -0,0 +1,73 @@ -+CONFIG_ARM=y -+CONFIG_SKIP_LOWLEVEL_INIT=y -+CONFIG_SYS_HAS_NONCACHED_MEMORY=y -+CONFIG_COUNTER_FREQUENCY=24000000 -+CONFIG_ARCH_ROCKCHIP=y -+CONFIG_DEFAULT_DEVICE_TREE="rk3566-nanopi-r3s" -+CONFIG_ROCKCHIP_RK3568=y -+CONFIG_TARGET_NANOPI_R3S_RK3566=y -+# CONFIG_OF_UPSTREAM is not set -+CONFIG_SPL_SERIAL=y -+CONFIG_DEBUG_UART_BASE=0xFE660000 -+CONFIG_DEBUG_UART_CLOCK=24000000 -+CONFIG_SYS_LOAD_ADDR=0xc00800 -+CONFIG_PCI=y -+CONFIG_DEBUG_UART=y -+CONFIG_FIT=y -+CONFIG_FIT_VERBOSE=y -+CONFIG_SPL_FIT_SIGNATURE=y -+CONFIG_SPL_LOAD_FIT=y -+CONFIG_LEGACY_IMAGE_FORMAT=y -+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-nanopi-r3s.dtb" -+# CONFIG_DISPLAY_CPUINFO is not set -+CONFIG_DISPLAY_BOARDINFO_LATE=y -+CONFIG_SPL_MAX_SIZE=0x40000 -+CONFIG_SPL_PAD_TO=0x7f8000 -+# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set -+CONFIG_SPL_ATF=y -+CONFIG_CMD_GPIO=y -+CONFIG_CMD_GPT=y -+CONFIG_CMD_I2C=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_PCI=y -+CONFIG_CMD_USB=y -+CONFIG_CMD_PMIC=y -+CONFIG_CMD_REGULATOR=y -+# CONFIG_SPL_DOS_PARTITION is not set -+CONFIG_SPL_OF_CONTROL=y -+CONFIG_OF_LIVE=y -+CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" -+CONFIG_SPL_DM_SEQ_ALIAS=y -+CONFIG_SPL_REGMAP=y -+CONFIG_SPL_SYSCON=y -+CONFIG_SPL_CLK=y -+CONFIG_ROCKCHIP_GPIO=y -+CONFIG_SYS_I2C_ROCKCHIP=y -+CONFIG_MISC=y -+CONFIG_SUPPORT_EMMC_RPMB=y -+CONFIG_MMC_DW=y -+CONFIG_MMC_DW_ROCKCHIP=y -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_SDMA=y -+CONFIG_MMC_SDHCI_ROCKCHIP=y -+CONFIG_PHY_REALTEK=y -+CONFIG_DWC_ETH_QOS=y -+CONFIG_DWC_ETH_QOS_ROCKCHIP=y -+CONFIG_RTL8169=y -+CONFIG_PCIE_DW_ROCKCHIP=y -+CONFIG_PHY_ROCKCHIP_INNO_USB2=y -+CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y -+CONFIG_SPL_PINCTRL=y -+CONFIG_DM_PMIC=y -+CONFIG_PMIC_RK8XX=y -+CONFIG_REGULATOR_RK8XX=y -+CONFIG_PWM_ROCKCHIP=y -+CONFIG_SPL_RAM=y -+CONFIG_BAUDRATE=1500000 -+CONFIG_DEBUG_UART_SHIFT=2 -+CONFIG_SYS_NS16550_MEM32=y -+CONFIG_SYSRESET=y -+CONFIG_USB=y -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_DWC3=y -+CONFIG_USB_DWC3_GENERIC=y - -diff --git a/dev/null b/arch/arm/dts/rk3566-nanopi-r3s.dts +diff --git a/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts b/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts +new file mode 100644 +index 0000000000..a7a55d68db --- /dev/null -+++ b/arch/arm/dts/rk3566-nanopi-r3s.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts @@ -0,0 +1,554 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + * Copyright (c) 2024 FriendlyElec Computer Tech. Co., Ltd. -+ * (http://www.friendlyelec.com) ++ * (http://www.friendlyarm.com) + * + * Copyright (c) 2024 Tianling Shen + */ @@ -135,13 +28,13 @@ diff --git a/dev/null b/arch/arm/dts/rk3566-nanopi-r3s.dts +#include "rk3566.dtsi" + +/ { -+ model = "FriendlyElec NanoPi R3S"; ++ model = "FriendlyARM NanoPi R3S"; + compatible = "friendlyarm,nanopi-r3s", "rockchip,rk3566"; + + aliases { + ethernet0 = &gmac1; -+ mmc0 = &sdhci; -+ mmc1 = &sdmmc0; ++ mmc0 = &sdmmc0; ++ mmc1 = &sdhci; + }; + + chosen: chosen { @@ -267,6 +160,10 @@ diff --git a/dev/null b/arch/arm/dts/rk3566-nanopi-r3s.dts + &gmac1m0_rx_bus2 + &gmac1m0_rgmii_clk_level2 + &gmac1m0_rgmii_bus_level3>; ++ snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>; ++ snps,reset-active-low; ++ /* Reset time is 20ms, 100ms for rtl8211f */ ++ snps,reset-delays-us = <0 20000 100000>; + status = "okay"; +}; + @@ -528,9 +425,6 @@ diff --git a/dev/null b/arch/arm/dts/rk3566-nanopi-r3s.dts + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <ð_phy_reset_pin>; -+ reset-assert-us = <20000>; -+ reset-deassert-us = <100000>; -+ reset-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>; + }; +}; + @@ -594,6 +488,7 @@ diff --git a/dev/null b/arch/arm/dts/rk3566-nanopi-r3s.dts +}; + +&pmu_io_domains { ++ status = "okay"; + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; @@ -603,13 +498,11 @@ diff --git a/dev/null b/arch/arm/dts/rk3566-nanopi-r3s.dts + vccio5-supply = <&vcc_1v8>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_3v3>; -+ status = "okay"; +}; + +&sdhci { + bus-width = <8>; + max-frequency = <200000000>; -+ mmc-hs200-1_8v; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; @@ -670,3 +563,250 @@ diff --git a/dev/null b/arch/arm/dts/rk3566-nanopi-r3s.dts +&vop_mmu { + status = "okay"; +}; + + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Werner +Date: Sun, 9 Dec 2024 07:36:02 +0200 +Subject: add support for Nanopi R3S + +--- + dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts b/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts +index a7a55d68db..6bc17f755b 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts +@@ -3,7 +3,7 @@ + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * + * Copyright (c) 2024 FriendlyElec Computer Tech. Co., Ltd. +- * (http://www.friendlyarm.com) ++ * (http://www.friendlyelec.com) + * + * Copyright (c) 2024 Tianling Shen + */ +@@ -17,7 +17,7 @@ + #include "rk3566.dtsi" + + / { +- model = "FriendlyARM NanoPi R3S"; ++ model = "FriendlyElec NanoPi R3S"; + compatible = "friendlyarm,nanopi-r3s", "rockchip,rk3566"; + + aliases { + + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Werner +Date: Sun, 9 Dec 2024 07:36:02 +0200 +Subject: add support for Nanopi R3S + +--- + dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts | 7 +++---- + 1 file changed, 3 insertions(+), 4 deletions(-) + +diff --git a/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts b/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts +index 6bc17f755b..66a00cddda 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts +@@ -149,10 +149,6 @@ + &gmac1m0_rx_bus2 + &gmac1m0_rgmii_clk_level2 + &gmac1m0_rgmii_bus_level3>; +- snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>; +- snps,reset-active-low; +- /* Reset time is 20ms, 100ms for rtl8211f */ +- snps,reset-delays-us = <0 20000 100000>; + status = "okay"; + }; + +@@ -414,6 +410,9 @@ + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <ð_phy_reset_pin>; ++ reset-assert-us = <20000>; ++ reset-deassert-us = <100000>; ++ reset-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>; + }; + }; + + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Werner +Date: Sun, 9 Dec 2024 07:36:02 +0200 +Subject: add support for Nanopi R3S + +--- + dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts b/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts +index 66a00cddda..243574f8da 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts +@@ -476,7 +476,6 @@ + }; + + &pmu_io_domains { +- status = "okay"; + pmuio1-supply = <&vcc3v3_pmu>; + pmuio2-supply = <&vcc3v3_pmu>; + vccio1-supply = <&vccio_acodec>; +@@ -486,6 +485,7 @@ + vccio5-supply = <&vcc_1v8>; + vccio6-supply = <&vcc_3v3>; + vccio7-supply = <&vcc_3v3>; ++ status = "okay"; + }; + + &sdhci { + + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Werner +Date: Sun, 9 Dec 2024 07:36:02 +0200 +Subject: add support for Nanopi R3S + +--- + dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts b/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts +index 243574f8da..03a2f90f62 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts +@@ -491,6 +491,7 @@ + &sdhci { + bus-width = <8>; + max-frequency = <200000000>; ++ mmc-hs200-1_8v; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>; + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Werner +Date: Sun, 9 Dec 2024 07:36:02 +0200 +Subject: add support for Nanopi R3S + +--- + dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts b/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts +index 03a2f90f62..fb1f65c868 100644 +--- a/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts ++++ b/dts/upstream/src/arm64/rockchip/rk3566-nanopi-r3s.dts +@@ -22,8 +22,8 @@ + + aliases { + ethernet0 = &gmac1; +- mmc0 = &sdmmc0; +- mmc1 = &sdhci; ++ mmc0 = &sdhci; ++ mmc1 = &sdmmc0; + }; + + chosen: chosen { + +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Werner +Date: Sun, 9 Dec 2024 07:36:02 +0200 +Subject: add support for Nanopi R3S + +diff --git a/arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi b/arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi +new file mode 100644 +index 0000000000..b66e5015d6 +--- /dev/null ++++ b/arch/arm/dts/rk3566-nanopi-r3s-u-boot.dtsi +@@ -0,0 +1,8 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later ++ ++#include "rk356x-u-boot.dtsi" ++ ++&vcc5v0_usb { ++ /delete-property/ regulator-always-on; ++ /delete-property/ regulator-boot-on; ++}; +diff --git a/configs/nanopi-r3s-rk3566_defconfig b/configs/nanopi-r3s-rk3566_defconfig +new file mode 100644 +index 0000000000..f21c703ca7 +--- /dev/null ++++ b/configs/nanopi-r3s-rk3566_defconfig +@@ -0,0 +1,74 @@ ++CONFIG_ARM=y ++CONFIG_SKIP_LOWLEVEL_INIT=y ++CONFIG_COUNTER_FREQUENCY=24000000 ++CONFIG_ARCH_ROCKCHIP=y ++CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3566-nanopi-r3s" ++CONFIG_ROCKCHIP_RK3568=y ++CONFIG_SPL_SERIAL=y ++CONFIG_SYS_LOAD_ADDR=0xc00800 ++CONFIG_DEBUG_UART_BASE=0xFE660000 ++CONFIG_DEBUG_UART_CLOCK=24000000 ++CONFIG_PCI=y ++CONFIG_DEBUG_UART=y ++CONFIG_FIT=y ++CONFIG_FIT_VERBOSE=y ++CONFIG_SPL_FIT_SIGNATURE=y ++CONFIG_SPL_LOAD_FIT=y ++CONFIG_LEGACY_IMAGE_FORMAT=y ++CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-nanopi-r3s.dtb" ++# CONFIG_DISPLAY_CPUINFO is not set ++CONFIG_DISPLAY_BOARDINFO_LATE=y ++CONFIG_SPL_MAX_SIZE=0x40000 ++CONFIG_SPL_PAD_TO=0x7f8000 ++# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set ++CONFIG_SPL_ATF=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_I2C=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_PCI=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_PMIC=y ++CONFIG_CMD_REGULATOR=y ++# CONFIG_SPL_DOS_PARTITION is not set ++CONFIG_SPL_OF_CONTROL=y ++CONFIG_OF_LIVE=y ++CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" ++CONFIG_SPL_DM_SEQ_ALIAS=y ++CONFIG_SPL_REGMAP=y ++CONFIG_SPL_SYSCON=y ++CONFIG_SPL_CLK=y ++CONFIG_ROCKCHIP_GPIO=y ++CONFIG_SYS_I2C_ROCKCHIP=y ++CONFIG_LED=y ++CONFIG_LED_GPIO=y ++CONFIG_MISC=y ++CONFIG_SUPPORT_EMMC_RPMB=y ++CONFIG_MMC_DW=y ++CONFIG_MMC_DW_ROCKCHIP=y ++CONFIG_MMC_SDHCI=y ++CONFIG_MMC_SDHCI_SDMA=y ++CONFIG_MMC_SDHCI_ROCKCHIP=y ++CONFIG_PHY_REALTEK=y ++CONFIG_DWC_ETH_QOS=y ++CONFIG_DWC_ETH_QOS_ROCKCHIP=y ++CONFIG_RTL8169=y ++CONFIG_NVME_PCI=y ++CONFIG_PCIE_DW_ROCKCHIP=y ++CONFIG_PHY_ROCKCHIP_INNO_USB2=y ++CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y ++CONFIG_SPL_PINCTRL=y ++CONFIG_DM_PMIC=y ++CONFIG_PMIC_RK8XX=y ++CONFIG_REGULATOR_RK8XX=y ++CONFIG_PWM_ROCKCHIP=y ++CONFIG_SPL_RAM=y ++CONFIG_BAUDRATE=1500000 ++CONFIG_DEBUG_UART_SHIFT=2 ++CONFIG_SYS_NS16550_MEM32=y ++CONFIG_SYSRESET=y ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_DWC3=y ++CONFIG_USB_DWC3_GENERIC=y ++CONFIG_ERRNO_STR=y