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Feature/sunxi mainline stmmac ac300 (#9952)
* sunxi: H618: drop unused legacy vendor sunxi-gmac driver and align Orange Pi Zero 2W Remove the unused legacy vendor GMAC driver from patches. Revert syscon register range changes in the Orange Pi Zero 2W patch to align it with standard mainline stmmac bindings. The vendor GMAC was only referenced in the Orange Pi Zero 2W (where it was broken) and the Banana Pi M4 Berry board (where it was disabled), making it completely safe to remove. Signed-off-by: Alastair D'Silva <alastair@d-silva.org> Assisted-by: Antigravity <antigravity@google.com> * sunxi: EPHY: add dedicated modular AC300 EPHY driver Introduce a dedicated, mainline-quality Clause 22 PHY driver for the Allwinner AC300 Ethernet PHY. This driver matches the AC300 EPHY via a custom compatible string and communicates directly over MDIO. We compile the driver directly into the kernel (CONFIG_AC300_PHY=y) instead of building a module (CONFIG_AC300_PHY=m) for the following reasons: - The integrated AC300 EPHY starts in a powered-down state. - The MAC controller driver (dwmac-sun8i) is compiled in (y). If the AC300 PHY driver is built as a module (m), early MAC driver probing during boot will default to binding the generic C22 PHY driver because the AC300 module cannot be loaded yet. - Without the custom AC300 PHY driver's early SYSCON configuration, clock gating setup, and Bandgap calibration programming, the EPHY will fail to negotiate a stable link or establish packet transmission on boot. - Compiling the driver directly in ensures that it is immediately available to bind when the MAC probes, allowing out-of-the-box DHCP and network access. Signed-off-by: Alastair D'Silva <alastair@d-silva.org> Assisted-by: Antigravity <antigravity@google.com> * sunxi: EPHY: Support internal PHYs for H616 in the stmmac driver Introduce support for the co-packaged internal Ethernet Physical Layer (EPHY) on Allwinner H616/H618 SoCs in the mainline dwmac-sun8i driver. This adds internal PHY handling changes: - Define emac_variant_h616_internal with internal PHY, MII, RMII, and RGMII support. - Delay the MAC software reset until sun8i_dwmac_init phase. For internal PHYs, doing a MAC software reset during early probe/mux-switching fails with an EMAC reset timeout because the internal PHY's clocks are not yet active. - Skip setting H3_EPHY_SELECT for the H616 syscon MDIO mux configuration, as this bit is not applicable to H616/H618. - Add stable locally-administered MAC address generation derived from the SoC chip ID when a valid hardware address is not present. Signed-off-by: Alastair D'Silva <alastair@d-silva.org> Assisted-by: Antigravity <antigravity@google.com> * sunxi: orangepi-zero2w: Enable AC300 EPHY in device tree patches Signed-off-by: Alastair D'Silva <alastair@d-silva.org> Assisted-by: Antigravity <antigravity@google.com> --------- Signed-off-by: Alastair D'Silva <alastair@d-silva.org>
1 parent 5bfbe26 commit 21fb43e

14 files changed

Lines changed: 1179 additions & 8044 deletions

‎config/kernel/linux-sunxi64-current.config‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -760,6 +760,7 @@ CONFIG_STMMAC_PCI=m
760760
# CONFIG_NET_VENDOR_XILINX is not set
761761
CONFIG_LED_TRIGGER_PHY=y
762762
CONFIG_AC200_PHY=m
763+
CONFIG_AC300_PHY=y
763764
CONFIG_MOTORCOMM_PHY=y
764765
CONFIG_REALTEK_PHY=y
765766
CONFIG_SMSC_PHY=y

‎config/kernel/linux-sunxi64-edge.config‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -759,6 +759,7 @@ CONFIG_STMMAC_PCI=m
759759
# CONFIG_NET_VENDOR_XILINX is not set
760760
CONFIG_LED_TRIGGER_PHY=y
761761
CONFIG_AC200_PHY=m
762+
CONFIG_AC300_PHY=y
762763
CONFIG_MOTORCOMM_PHY=y
763764
CONFIG_REALTEK_PHY=y
764765
CONFIG_SMSC_PHY=y

‎patch/kernel/archive/sunxi-6.18/patches.armbian/0202-drv-net-phy-ac200-ephy-add.patch‎

Lines changed: 13 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -54,7 +54,7 @@ new file mode 100644
5454
index 000000000000..111111111111
5555
--- /dev/null
5656
+++ b/drivers/net/phy/ac200-phy.c
57-
@@ -0,0 +1,82 @@
57+
@@ -0,0 +1,94 @@
5858
+// SPDX-License-Identifier: GPL-2.0+
5959
+/**
6060
+ * Driver for AC200 Ethernet PHY
@@ -66,6 +66,7 @@ index 000000000000..111111111111
6666
+#include <linux/kernel.h>
6767
+#include <linux/module.h>
6868
+#include <linux/phy.h>
69+
+#include <linux/of.h>
6970
+
7071
+#define AC200_EPHY_ID 0x00441400
7172
+#define AC200_EPHY_ID_MASK 0x0ffffff0
@@ -114,11 +115,22 @@ index 000000000000..111111111111
114115
+ return 0;
115116
+}
116117
+
118+
+static int ac200_ephy_match_phy_device(struct phy_device *phydev,
119+
+ const struct phy_driver *phydrv)
120+
+{
121+
+ if (phydev->mdio.dev.of_node &&
122+
+ of_device_is_compatible(phydev->mdio.dev.of_node, "allwinner,sun50i-h618-ac300-ephy"))
123+
+ return 0;
124+
+
125+
+ return phy_id_compare(phydev->phy_id, phydrv->phy_id, phydrv->phy_id_mask);
126+
+}
127+
+
117128
+static struct phy_driver ac200_ephy_driver[] = {
118129
+ {
119130
+ .phy_id = AC200_EPHY_ID,
120131
+ .phy_id_mask = AC200_EPHY_ID_MASK,
121132
+ .name = "Allwinner AC200 EPHY",
133+
+ .match_phy_device = ac200_ephy_match_phy_device,
122134
+ .soft_reset = genphy_soft_reset,
123135
+ .config_init = ac200_ephy_config_init,
124136
+ .probe = ac200_ephy_probe,

‎patch/kernel/archive/sunxi-6.18/patches.armbian/0302-arm64-dts-sun50i-h618-orangepi-zero2w-add-emac-sound.patch‎

Lines changed: 32 additions & 87 deletions
Original file line numberDiff line numberDiff line change
@@ -6,59 +6,9 @@ Subject: arm64: dts: sun50i-h618-orangepi-zero2w: Add missing nodes
66
Signed-off-by: The-going <48602507+The-going@users.noreply.github.com>
77
Signed-off-by: Exodus <zjemcikolege@protonmail.com>
88
---
9-
arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 25 +-
109
arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts | 188 ++++++++++
11-
2 files changed, 205 insertions(+), 8 deletions(-)
10+
1 file changed, 188 insertions(+)
1211

13-
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
14-
index 111111111111..222222222222 100644
15-
--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
16-
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
17-
@@ -262,7 +262,7 @@ crypto: crypto@1904000 {
18-
19-
syscon: syscon@3000000 {
20-
compatible = "allwinner,sun50i-h616-system-control";
21-
- reg = <0x03000000 0x1000>;
22-
+ reg = <0x03000000 0x30>,<0x03000038 0x0fc8>;
23-
#address-cells = <1>;
24-
#size-cells = <1>;
25-
ranges;
26-
@@ -744,19 +744,28 @@ mdio0: mdio {
27-
};
28-
29-
emac1: ethernet@5030000 {
30-
- compatible = "allwinner,sun50i-h616-emac";
31-
- syscon = <&syscon 1>;
32-
- reg = <0x05030000 0x10000>;
33-
+ compatible = "allwinner,sunxi-gmac";
34-
+ reg = <0x05030000 0x10000>,
35-
+ <0x03000034 0x4>;
36-
+ reg-names = "gmac1_reg","ephy_reg";
37-
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
38-
- interrupt-names = "macirq";
39-
+ interrupt-names = "gmacirq";
40-
resets = <&ccu RST_BUS_EMAC1>;
41-
reset-names = "stmmaceth";
42-
- clocks = <&ccu CLK_BUS_EMAC1>;
43-
- clock-names = "stmmaceth";
44-
+ clocks = <&ccu CLK_BUS_EMAC1>,<&ccu CLK_EMAC_25M>;
45-
+ clock-names = "bus-emac1","emac-25m";
46-
+ pinctrl-0 = <&rmii_pins>;
47-
+ pinctrl-names = "default";
48-
+ tx-delay = <7>;
49-
+ rx-delay = <31>;
50-
+ phy-rst;
51-
+ gmac-power0;
52-
+ gmac-power1;
53-
+ gmac-power2;
54-
status = "disabled";
55-
56-
mdio1: mdio {
57-
- compatible = "snps,dwmac-mdio";
58-
+ compatible = "ethernet-phy-ieee802.3-c22";
59-
#address-cells = <1>;
60-
#size-cells = <0>;
61-
};
6212
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts
6313
index 111111111111..222222222222 100644
6414
--- a/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts
@@ -134,10 +84,10 @@ index 111111111111..222222222222 100644
13484
+ post-power-on-delay-ms = <200>;
13585
+ };
13686
+
137-
+ ac200_pwm_clk: ac200_clk {
87+
+ ac300_pwm_clk: ac300-clk {
13888
+ compatible = "pwm-clock";
13989
+ #clock-cells = <0>;
140-
+ // pwm5 period_ns = 500 > 334 for select 24M clock.
90+
+ /* 500ns period -> 2MHz */
14191
+ pwms = <&pwm 5 500 0>;
14292
+ clock-frequency = <2000000>;
14393
+ status = "okay";
@@ -204,7 +154,7 @@ index 111111111111..222222222222 100644
204154
/* USB 2 & 3 are on the FPC connector (or the exansion board) */
205155

206156
&gpu {
207-
@@ -77,14 +176,55 @@ &gpu {
157+
@@ -77,14 +176,77 @@ &gpu {
208158
&mmc0 {
209159
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
210160
bus-width = <4>;
@@ -224,21 +174,43 @@ index 111111111111..222222222222 100644
224174
};
225175

226176
+&emac1 {
177+
+ compatible = "allwinner,sun50i-h616-internal-emac";
227178
+ pinctrl-names = "default";
228179
+ pinctrl-0 = <&rmii_pins>;
229180
+ phy-mode = "rmii";
230-
+ phy-handle = <&rmii_phy>;
181+
+ phy-handle = <&ac300_ephy>;
231182
+ phy-supply = <&reg_dldo1>;
232183
+ allwinner,rx-delay-ps = <3100>;
233184
+ allwinner,tx-delay-ps = <700>;
234185
+ status = "okay";
186+
+
187+
+ mdio-mux {
188+
+ compatible = "allwinner,sun8i-h3-mdio-mux";
189+
+ #address-cells = <1>;
190+
+ #size-cells = <0>;
191+
+ mdio-parent-bus = <&mdio1>;
192+
+
193+
+ internal_mdio: mdio@1 {
194+
+ compatible = "allwinner,sun8i-h3-mdio-internal";
195+
+ reg = <1>;
196+
+ #address-cells = <1>;
197+
+ #size-cells = <0>;
198+
+
199+
+ ac300_ephy: ethernet-phy@0 {
200+
+ compatible = "ethernet-phy-id0044.1400", "allwinner,sun50i-h618-ac300-ephy", "ethernet-phy-ieee802.3-c22";
201+
+ reg = <0>;
202+
+ clocks = <&ccu CLK_EMAC_25M>, <&ac300_pwm_clk>;
203+
+ clock-names = "ephy", "pwm";
204+
+ nvmem-cells = <&ephy_calibration>;
205+
+ nvmem-cell-names = "calibration";
206+
+ status = "okay";
207+
+ };
208+
+ };
209+
+ };
235210
+};
236211
+
237212
+&mdio1 {
238-
+ rmii_phy: ethernet-phy@1 {
239-
+ compatible = "ethernet-phy-ieee802.3-c22";
240-
+ reg = <1>;
241-
+ };
213+
+ compatible = "snps,dwmac-mdio";
242214
+};
243215
+
244216
+&ohci0 {
@@ -260,34 +232,7 @@ index 111111111111..222222222222 100644
260232
&pio {
261233
vcc-pc-supply = <&reg_dldo1>;
262234
vcc-pf-supply = <&reg_dldo1>; /* internally via VCC-IO */
263-
@@ -169,6 +309,26 @@ &uart0 {
264-
status = "okay";
265-
};
266-
267-
+&i2c3 {
268-
+ status = "okay";
269-
+ pinctrl-names = "default";
270-
+ pinctrl-0 = <&i2c3_pa_pins>;
271-
+
272-
+ ac200_x: mfd@10 {
273-
+ compatible = "x-powers,ac200-sunxi";
274-
+ reg = <0x10>;
275-
+ clocks = <&ac200_pwm_clk>;
276-
+ // ephy id
277-
+ nvmem-cells = <&ephy_calibration>;
278-
+ nvmem-cell-names = "calibration";
279-
+
280-
+ ac200_ephy: phy {
281-
+ compatible = "x-powers,ac200-ephy-sunxi";
282-
+ status = "okay";
283-
+ };
284-
+ };
285-
+};
286-
+
287-
&usbotg {
288-
/*
289-
* PHY0 pins are connected to a USB-C socket, but a role switch
290-
@@ -189,3 +349,31 @@ &usbphy {
235+
@@ -189,3 +351,31 @@ &usbphy {
291236
usb1_vbus-supply = <&reg_vcc5v>;
292237
status = "okay";
293238
};

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