Feat: Add support for the Mellow Fly C5 3D Printer board (#9584)

* sunxi: mellowflyc5: add board support

This adds baseline board support for the Mellow Fly-C5 (H618), including:
- Board configurations and boot environment setup
- ATF and U-Boot patches to enable UART1 and enable eMMC in SPL
- Common family adjustments to allow overriding bootenv file
- Device tree and Ethernet controller patches (EPHY address set to 0).

Signed-off-by: Alastair D'Silva <alastair@d-silva.org>
Assisted-by: Antigravity <antigravity@google.com>

* sunxi: mellowflyc5: fix eMMC boot by backporting H616 MMC reset and limiting frequency

The H618 on-chip eMMC controller requires a reset and FIFO threshold configuration
for reliable data transfers. Backport the H616 MMC reset procedure and FIFO setup to
the U-Boot driver to enable boot functionality from the eMMC slot.

Additionally, tune the eMMC (MMC2) clock frequency limit to achieve optimal throughput
while maintaining 100% stability under 3.3V signaling (8-bit DDR mode). Sequential
reads were tested using a 200MB block read test:

| Configured Limit | Actual Clock Speed | Stability Status | Read Speed | Write Speed |
| :--- | :--- | :--- | :--- | :--- |
| 20 MHz | 20.0 MHz | Stable (0 errors) | 35.1 MB/s | — |
| 35 MHz | 33.3 MHz | Stable (0 errors) | 51.6 MB/s | — |
| 40 MHz | 37.5 MHz | Stable (0 errors) | 61.0 MB/s | 46.1 MB/s |
| 42 MHz | 37.5 MHz | Stable (0 errors) | 61.0 MB/s | 46.1 MB/s |
| 45 MHz | 42.85 MHz | Unstable (I/O errors) | 53.7 MB/s | — |
| 48 MHz | 42.85 MHz | Unstable (I/O errors) | 53.6 MB/s | — |
| 52 MHz | 50.0 MHz | Unstable (Boot fail) | Failed | — |

We set max-frequency to 40 MHz in the Linux Device Trees (configuring a stable
actual clock speed of 37.5 MHz), resulting in a 73% read throughput increase
over the initial 20 MHz limit. In U-Boot, we conservatively limit the clock
frequency to 20 MHz (f_max = 20000000) to ensure reliable early boot link-training
and initial loading.

Signed-off-by: Alastair D'Silva <alastair@d-silva.org>
Assisted-by: Antigravity <antigravity@google.com>

* arm64: dts: allwinner: Limit CPU frequency on Mellow Fly-C5 to 1.20GHz

The Device Tree configures the CPU operating performance points using the H616
common OPP table, allowing frequencies up to 1.512GHz. Frequencies above 1.20GHz
require voltages up to 1.16V to operate reliably.

However, the AXP313a PMIC vdd-cpu regulator (reg_dcdc2) is hard-capped at 1.10V
in the board configuration. When CPU load spikes and scales the frequency to
1.416GHz/1.512GHz, the voltage remains stuck at 1.10V. This severe under-volting
causes CPU instruction corruption, leading to undefined instruction oopses and
kernel panics.

We experimentally attempted to raise the regulator-max-microvolt limit to 1.30V
and set the required OPP voltages to 1.16V and 1.20V. This resulted in consistent
and immediate RCU CPU stalls and system freezes during early boot scaling. This
instability is traced to the physical limitations of the AXP313a PMIC: its DCDC2
regulator is rated for a maximum continuous current of 3.0A, which is insufficient
to sustain the transient current draw of the H618 CPU quad-cores scaling to 1.416GHz
or above at higher voltages, causing PMIC over-current protection (OCP) voltage
clipping and transient droop.

Limit the CPU maximum frequency to a stable 1.20GHz by deleting the higher OPP
nodes (opp-1320000000, opp-1416000000, and opp-1512000000) from cpu_opp_table.

Signed-off-by: Alastair D'Silva <alastair@d-silva.org>
Assisted-by: Antigravity <antigravity@google.com>

* u-boot: board: mellowflyc5: Lower DRAM clock frequency to 600MHz

The mellowflyc5 board defconfig configured the LPDDR4 DRAM clock to run
at 792MHz. Under Linux 7.0 system load, this high frequency causes signal
integrity and memory interface instability.

This DRAM clock reduction was validated through intensive testing:
1. Running static memory tests (such as memtester and stress-ng --verify)
   after U-Boot completed link training can temporarily pass on an idle,
   cool board.
2. However, under realistic system-wide load during early boot/reboot loops,
   running at 792MHz fails within 11 to 17 cycles, resulting in:
   - User-space memory corruption (e.g. __vm_enough_memory errors attempting
     to allocate 256TB of virtual memory).
   - Random SSH daemon connection resets (Connection reset by peer) due to SSL key
     corruption.
   - Complete silent kernel freezes / system bus lockups during systemd
     multi-user targets initialization.

Lowering the DRAM clock frequency from 792MHz to a stable 600MHz completely
resolves all signal integrity issues and memory corruption. With this change,
the target successfully survived 100 consecutive reboot test cycles cleanly with
working wlan0 and zero memory or connection failures.

Signed-off-by: Alastair D'Silva <alastair@d-silva.org>
Assisted-by: Antigravity <antigravity@google.com>

* sunxi: mellowflyc5: Configure LPDDR4 DRAM voltage to 1.20V in U-Boot and Linux

The Mellow Fly-C5 uses LPDDR4 memory which requires a standard 1.20V supply
voltage. The default AXP313 PMIC DCDC3 (vdd-dram) voltage in U-Boot SPL is
configured to 1.10V.

Configure DCDC3 to 1.20V in both U-Boot (CONFIG_AXP_DCDC3_VOLT=1200) and the
Linux Device Tree files (reg_dcdc3) for both sunxi-6.18 and sunxi-7.0 kernels.
This ensures the DRAM operates at its spec-compliant voltage from early boot
link-training, improving signal integrity and startup training reliability.

Signed-off-by: Alastair D'Silva <alastair@d-silva.org>
Assisted-by: Antigravity <antigravity@google.com>

---------

Signed-off-by: Alastair D'Silva <alastair@d-silva.org>

Author: deece

config/boards/mellowflyc5.csc

@@ -0,0 +1,41 @@
+# Allwinner H618 quad core 1GB RAM SoC 100M Ethernet WiFi
+BOARD_NAME="Mellow Fly-C5"
+BOOTPATCHDIR="u-boot-sunxi"
+
+BOARD_VENDOR="mellow"
+BOARDFAMILY="sun50iw9"
+BOARD_MAINTAINER="deece"
+INTRODUCED="2026"
+BOOTCONFIG="mellow_fly_c5_defconfig"
+OVERLAY_PREFIX="sun50i-h616"
+BOOT_FDT_FILE="allwinner/sun50i-h618-mellow-fly-c5.dtb"
+BOOT_LOGO="desktop"
+KERNEL_TARGET="current,edge"
+KERNEL_TEST_TARGET="current"
+FORCE_BOOTSCRIPT_UPDATE="yes"
+BOOTENV_FILE="mellowflyc5.txt"
+
+
+# WiFi RTL8821CS
+PACKAGE_LIST_BOARD="rfkill mmc-utils"
+
+# Enable eMMC (mmc2) in the SPL. Without this, CONFIG_MMC_SUNXI_SLOT_EXTRA
+# defaults to -1 and the SPL never calls sunxi_mmc_init(2), causing
+# "MMC Device 1 not found" when booting from eMMC.
+function post_config_uboot_target__mellowflyc5_emmc() {
+	display_alert "Enabling eMMC slot" "CONFIG_MMC_SUNXI_SLOT_EXTRA=2" "info"
+	run_host_command_logged scripts/config --set-val CONFIG_MMC_SUNXI_SLOT_EXTRA 2
+}
+
+function post_family_tweaks__mellowflyc5_console() {
+	display_alert "$BOARD" "Enabling serial-getty on ttyS1" "info"
+	mkdir -p "${SDCARD}/etc/systemd/system/serial-getty@ttyS1.service.d"
+	cat <<- 'EOD' > "${SDCARD}/etc/systemd/system/serial-getty@ttyS1.service.d/override.conf"
+		[Service]
+		ExecStart=
+		ExecStart=-/sbin/agetty -o '-- \u' --noreset --noclear 115200 %I $TERM
+	EOD
+	chroot_sdcard systemctl enable serial-getty@ttyS1.service
+	return 0
+}
+

config/bootenv/mellowflyc5.txt

@@ -0,0 +1,6 @@
+bootlogo=false
+console=both
+disp_mode=1920x1080p60
+extraargs=console=ttyS1,115200 console=ttyS0,115200
+
+

config/sources/families/include/sunxi64_common.inc

@@ -13,7 +13,7 @@ declare -g ATFBRANCH="tag:lts-v2.12.9"
 declare -g BOOTDELAY=1
 declare -g BOOTPATCHDIR="${BOOTPATCHDIR:-"v2026.07-sunxi64"}"
 declare -g BOOTBRANCH="${BOOTBRANCH:-"tag:v2026.07-rc4"}"
-declare -g BOOTENV_FILE='sunxi.txt'
+declare -g BOOTENV_FILE="${BOOTENV_FILE:-"sunxi.txt"}"
 declare -g UBOOT_TARGET_MAP="${UBOOT_TARGET_MAP:-BINMAN_ALLOW_MISSING=1;;u-boot-sunxi-with-spl.bin}"
 declare -g BOOTSCRIPT='boot-sun50i-next.cmd:boot.cmd'
 declare -g OVERLAY_DIR="/boot/dtb/allwinner/overlay"