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mixtile-blade3: mainline: updates to mainline DT with "working" RTL8169's
- For 6.18 + 6.19 - mixtile-blade3: add 4-pin header fan at 40c - mixtile-blade3: add gpu nodes - mixtile-blade3: add vcc5v0-host-en "usb" pinctrl - somehow results in 2 working RTL8169's behind the ASM1182e on pcie2x1l0 - which just means the _schematics lie_ - mixtile-blade3: drop rst pinctrl from pcie2x1l0 and pcie2x1l1 - this is me probably being stupid, but also required for working ASM1182e/RTL8169 - Status of this mainline port: - Initially started by Joshua Riek (2023?) - I then added some PCIe3x4 stuff, but never got around to finishing it - Specifically, the 2 FUSB302's are beyond me for now - One of them _powers_ the board. To use with mainline, power the board some other way with 12V, otherwise kaboom. - See sre's talk on this issue; Blade3 should be similar to Rock-5b in this aspect. - A challenge has been the PCI2x1 lanes to the miniPCIe and ASM1182e switch - Which by themselves seem to work, but the devices behind them (Switch + RTL8169 NICs) do not get powered - Until one day I tried to describe a (in theory) USB-related power pin, and suddenly both PCIe NICs started working! - All that said, the board is really not stable with this; end-users are much better off with vendor kernel for now. - Any and all help is appreciated. Those boards are nice, they've 2 FUSB302, and fancy PCIe Endpoint mode stuff. - Schematics we have access to are in https://damwold5pt25n.cloudfront.net/blade3/file/Schematic_Blade_3_v1.1.0.pdf - Those clearly lie.
1 parent df970b8 commit 9c4f8fa

2 files changed

Lines changed: 170 additions & 32 deletions

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‎patch/kernel/archive/rockchip64-6.18/dt/rk3588-mixtile-blade3.dts‎

Lines changed: 85 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,20 @@
11
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
22

3+
// rpardini, early 2026:
4+
// - Status of this mainline port:
5+
// - Initially started by Joshua Riek (2023?)
6+
// - I then added some PCIe3x4 stuff, but never got around to finishing it
7+
// - Specifically, the 2 FUSB302's are beyond me for now
8+
// - One of them _powers_ the board. To use with mainline, power the board some other way with 12V, otherwise kaboom.
9+
// - See sre's talk on this issue; Blade3 should be similar to Rock-5b in this aspect.
10+
// - A challenge has been the PCI2x1 lanes to the miniPCIe and ASM1182e switch
11+
// - Which by themselves seem to work, but the devices behind them (Switch + RTL8169 NICs) do not get powered
12+
// - Until one day I tried to describe a (in theory) USB-related power pin, and suddenly both PCIe NICs started working!
13+
// - All that said, the board is really not stable with this; end-users are much better off with vendor kernel for now.
14+
// - Any and all help is appreciated. Those boards are nice, they've 2 FUSB302, and fancy PCIe Endpoint mode stuff.
15+
// - Schematics we have access to are in https://damwold5pt25n.cloudfront.net/blade3/file/Schematic_Blade_3_v1.1.0.pdf
16+
// - Those clearly lie.
17+
318
/dts-v1/;
419

520
#include <dt-bindings/gpio/gpio.h>
@@ -20,6 +35,18 @@
2035
stdout-path = "serial2:1500000n8";
2136
};
2237

38+
fan: pwm-fan {
39+
compatible = "pwm-fan";
40+
#cooling-cells = <2>;
41+
cooling-levels = <0 50 100 150 200 255>;
42+
pwms = <&pwm8 0 250000 0>; /* aka GPIO3_D0 / PWM8_M2 On 4-pin fan header */
43+
fan-supply = <&vcc5v0_sys>;
44+
pulses-per-revolution = <2>;
45+
interrupt-parent = <&gpio3>; /* GPIO GPIO3_B1/PWM2_M1 */
46+
interrupts = <RK_PB1 IRQ_TYPE_EDGE_FALLING>; // On 4-pin fan header
47+
status = "okay";
48+
};
49+
2350
vcc12v_dcin: vcc12v-dcin-regulator {
2451
compatible = "regulator-fixed";
2552
regulator-name = "vcc12v_dcin";
@@ -186,6 +213,11 @@
186213
mem-supply = <&vdd_cpu_lit_mem_s0>;
187214
};
188215

216+
&gpu {
217+
mali-supply = <&vdd_gpu_s0>;
218+
status = "okay";
219+
};
220+
189221
&i2c0 {
190222
pinctrl-names = "default";
191223
pinctrl-0 = <&i2c0m2_xfer>;
@@ -270,17 +302,40 @@
270302
status = "okay";
271303
};
272304

273-
&pcie2x1l0 {
305+
/* Temperature sensor near the center of the SoC */
306+
&package_thermal {
307+
polling-delay = <1000>;
308+
309+
trips {
310+
package_hot: package_hot {
311+
hysteresis = <2000>;
312+
temperature = <40000>; /* 40 celsius */
313+
type = "active";
314+
};
315+
};
316+
317+
cooling-maps {
318+
map0 {
319+
cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
320+
trip = <&package_hot>;
321+
};
322+
};
323+
};
324+
325+
326+
&pcie2x1l0 { // combphy1, to ASM1182e
274327
reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>;
275-
pinctrl-names = "default";
276-
pinctrl-0 = <&pcie2_0_rst>;
328+
rockchip,init-delay-ms = <100>;
329+
//pinctrl-names = "default";
330+
//pinctrl-0 = <&pcie2_0_rst>;
277331
status = "okay";
278332
};
279333

280-
&pcie2x1l1 {
334+
&pcie2x1l1 { // combphy2, to miniPCIe socket
281335
reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
282-
pinctrl-names = "default";
283-
pinctrl-0 = <&pcie2_1_rst>;
336+
rockchip,init-delay-ms = <100>;
337+
//pinctrl-names = "default";
338+
//pinctrl-0 = <&pcie2_1_rst>;
284339
status = "okay";
285340
};
286341

@@ -296,22 +351,26 @@
296351
status = "okay";
297352
};
298353

354+
&pd_gpu {
355+
domain-supply = <&vdd_gpu_s0>;
356+
};
357+
299358
&pinctrl {
300359
sdmmc {
301360
sdmmc_pwr: sdmmc-pwr {
302361
rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>;
303362
};
304363
};
305364

306-
pcie2 {
307-
pcie2_0_rst: pcie2-0-rst {
308-
rockchip,pins = <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
309-
};
365+
//pcie2 {
366+
// pcie2_0_rst: pcie2-0-rst {
367+
// rockchip,pins = <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
368+
// };
310369

311-
pcie2_1_rst: pcie2-1-rst {
312-
rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
313-
};
314-
};
370+
// pcie2_1_rst: pcie2-1-rst {
371+
// rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
372+
// };
373+
//};
315374

316375
pcie3 {
317376
pcie3_rst: pcie3-rst {
@@ -320,12 +379,22 @@
320379

321380
pcie3_vcc3v3_en: pcie3-vcc3v3-en {
322381
rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
382+
// drives a ETA5050V33S2F regulator for 3.3v to VCC3V3_PI6C
383+
};
384+
};
385+
386+
usb {
387+
vcc5v0_host_en: vcc5v0-host-en {
388+
rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
389+
// Schematics say this drives a ETA6027S2F current limiter enabling VBUS5V0_TYPEC0.
390+
// But it _must_ somehow power the PCIe switch too, as both RTL8169's come up working with this!
323391
};
324392
};
393+
394+
// GPIO3_C6: 3 RK_PC6 is for power to the minipci 2.0 slot
325395
};
326396

327-
&pwm8 {
328-
pinctrl-names = "active";
397+
&pwm8 { // 4-pin FAN HEADER, PWM OUTPUT
329398
pinctrl-0 = <&pwm8m2_pins>;
330399
status = "okay";
331400
};

‎patch/kernel/archive/rockchip64-6.19/dt/rk3588-mixtile-blade3.dts‎

Lines changed: 85 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,20 @@
11
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
22

3+
// rpardini, early 2026:
4+
// - Status of this mainline port:
5+
// - Initially started by Joshua Riek (2023?)
6+
// - I then added some PCIe3x4 stuff, but never got around to finishing it
7+
// - Specifically, the 2 FUSB302's are beyond me for now
8+
// - One of them _powers_ the board. To use with mainline, power the board some other way with 12V, otherwise kaboom.
9+
// - See sre's talk on this issue; Blade3 should be similar to Rock-5b in this aspect.
10+
// - A challenge has been the PCI2x1 lanes to the miniPCIe and ASM1182e switch
11+
// - Which by themselves seem to work, but the devices behind them (Switch + RTL8169 NICs) do not get powered
12+
// - Until one day I tried to describe a (in theory) USB-related power pin, and suddenly both PCIe NICs started working!
13+
// - All that said, the board is really not stable with this; end-users are much better off with vendor kernel for now.
14+
// - Any and all help is appreciated. Those boards are nice, they've 2 FUSB302, and fancy PCIe Endpoint mode stuff.
15+
// - Schematics we have access to are in https://damwold5pt25n.cloudfront.net/blade3/file/Schematic_Blade_3_v1.1.0.pdf
16+
// - Those clearly lie.
17+
318
/dts-v1/;
419

520
#include <dt-bindings/gpio/gpio.h>
@@ -20,6 +35,18 @@
2035
stdout-path = "serial2:1500000n8";
2136
};
2237

38+
fan: pwm-fan {
39+
compatible = "pwm-fan";
40+
#cooling-cells = <2>;
41+
cooling-levels = <0 50 100 150 200 255>;
42+
pwms = <&pwm8 0 250000 0>; /* aka GPIO3_D0 / PWM8_M2 On 4-pin fan header */
43+
fan-supply = <&vcc5v0_sys>;
44+
pulses-per-revolution = <2>;
45+
interrupt-parent = <&gpio3>; /* GPIO GPIO3_B1/PWM2_M1 */
46+
interrupts = <RK_PB1 IRQ_TYPE_EDGE_FALLING>; // On 4-pin fan header
47+
status = "okay";
48+
};
49+
2350
vcc12v_dcin: vcc12v-dcin-regulator {
2451
compatible = "regulator-fixed";
2552
regulator-name = "vcc12v_dcin";
@@ -186,6 +213,11 @@
186213
mem-supply = <&vdd_cpu_lit_mem_s0>;
187214
};
188215

216+
&gpu {
217+
mali-supply = <&vdd_gpu_s0>;
218+
status = "okay";
219+
};
220+
189221
&i2c0 {
190222
pinctrl-names = "default";
191223
pinctrl-0 = <&i2c0m2_xfer>;
@@ -270,17 +302,40 @@
270302
status = "okay";
271303
};
272304

273-
&pcie2x1l0 {
305+
/* Temperature sensor near the center of the SoC */
306+
&package_thermal {
307+
polling-delay = <1000>;
308+
309+
trips {
310+
package_hot: package_hot {
311+
hysteresis = <2000>;
312+
temperature = <40000>; /* 40 celsius */
313+
type = "active";
314+
};
315+
};
316+
317+
cooling-maps {
318+
map0 {
319+
cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
320+
trip = <&package_hot>;
321+
};
322+
};
323+
};
324+
325+
326+
&pcie2x1l0 { // combphy1, to ASM1182e
274327
reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>;
275-
pinctrl-names = "default";
276-
pinctrl-0 = <&pcie2_0_rst>;
328+
rockchip,init-delay-ms = <100>;
329+
//pinctrl-names = "default";
330+
//pinctrl-0 = <&pcie2_0_rst>;
277331
status = "okay";
278332
};
279333

280-
&pcie2x1l1 {
334+
&pcie2x1l1 { // combphy2, to miniPCIe socket
281335
reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
282-
pinctrl-names = "default";
283-
pinctrl-0 = <&pcie2_1_rst>;
336+
rockchip,init-delay-ms = <100>;
337+
//pinctrl-names = "default";
338+
//pinctrl-0 = <&pcie2_1_rst>;
284339
status = "okay";
285340
};
286341

@@ -296,22 +351,26 @@
296351
status = "okay";
297352
};
298353

354+
&pd_gpu {
355+
domain-supply = <&vdd_gpu_s0>;
356+
};
357+
299358
&pinctrl {
300359
sdmmc {
301360
sdmmc_pwr: sdmmc-pwr {
302361
rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>;
303362
};
304363
};
305364

306-
pcie2 {
307-
pcie2_0_rst: pcie2-0-rst {
308-
rockchip,pins = <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
309-
};
365+
//pcie2 {
366+
// pcie2_0_rst: pcie2-0-rst {
367+
// rockchip,pins = <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
368+
// };
310369

311-
pcie2_1_rst: pcie2-1-rst {
312-
rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
313-
};
314-
};
370+
// pcie2_1_rst: pcie2-1-rst {
371+
// rockchip,pins = <4 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
372+
// };
373+
//};
315374

316375
pcie3 {
317376
pcie3_rst: pcie3-rst {
@@ -320,12 +379,22 @@
320379

321380
pcie3_vcc3v3_en: pcie3-vcc3v3-en {
322381
rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
382+
// drives a ETA5050V33S2F regulator for 3.3v to VCC3V3_PI6C
383+
};
384+
};
385+
386+
usb {
387+
vcc5v0_host_en: vcc5v0-host-en {
388+
rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
389+
// Schematics say this drives a ETA6027S2F current limiter enabling VBUS5V0_TYPEC0.
390+
// But it _must_ somehow power the PCIe switch too, as both RTL8169's come up working with this!
323391
};
324392
};
393+
394+
// GPIO3_C6: 3 RK_PC6 is for power to the minipci 2.0 slot
325395
};
326396

327-
&pwm8 {
328-
pinctrl-names = "active";
397+
&pwm8 { // 4-pin FAN HEADER, PWM OUTPUT
329398
pinctrl-0 = <&pwm8m2_pins>;
330399
status = "okay";
331400
};

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