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rockchip64-6.18: rebase rk3399 dwc3 phy-reset-quirk patch for 6.18.32 (#9847)
Kernel 6.18 stable progressed past 6.18.18 (last patch rewrite baseline, commit 2dc5b23) and refactored dwc3_readl()/dwc3_writel() to take the struct dwc3 pointer directly instead of dwc->regs. The patch context still referenced dwc->regs, causing hunks #1 (at core.c:153) and #3 (at core.c:213) to fail on builds against 6.18.32. Update the patch context to drop "->regs" (no change to the +/- payload) so it applies cleanly on 6.18.32 while remaining compatible with the prior baseline. Verified with patch -p1 --dry-run against the 6.18.32 HEAD blob from the linux-rockchip 6.18 branch: exit 0, all 16 hunks across the 3 files apply (offset -2 on core.h, harmless). Signed-off-by: SuperKali <hello@superkali.me>
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Lines changed: 5 additions & 5 deletions

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patch/kernel/archive/rockchip64-6.18/rk3399-usbc-phy-rockchip-naneng-Add-fallback-for-old-DTs.patch

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,7 @@ index 111111111111..222222222222 100644
2222
reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
2323
- reg |= DWC3_GCTL_PRTCAPDIR(mode);
2424
+ reg |= DWC3_GCTL_PRTCAPDIR(mode & DWC3_GCTL_PRTCAP_OTG);
25-
dwc3_writel(dwc->regs, DWC3_GCTL, reg);
25+
dwc3_writel(dwc, DWC3_GCTL, reg);
2626

2727
dwc->current_dr_role = mode;
2828
@@ -193,6 +193,7 @@ static void __dwc3_set_mode(struct work_struct *work)
@@ -63,9 +63,9 @@ index 111111111111..222222222222 100644
6363
+ for (int j = 0; j < dwc->num_usb3_ports; j++)
6464
+ phy_power_off(dwc->usb3_generic_phy[j]);
6565
+
66-
reg = dwc3_readl(dwc->regs, DWC3_GCTL);
66+
reg = dwc3_readl(dwc, DWC3_GCTL);
6767
reg |= DWC3_GCTL_CORESOFTRESET;
68-
dwc3_writel(dwc->regs, DWC3_GCTL, reg);
68+
dwc3_writel(dwc, DWC3_GCTL, reg);
6969

7070
+ if (dwc->usb3_phy_reset_quirk) {
7171
+ for (int j = 0; j < dwc->num_usb3_ports; j++) {
@@ -158,7 +158,7 @@ index 111111111111..222222222222 100644
158158

159159
#define DWC3_GCTL_CORESOFTRESET BIT(11)
160160
#define DWC3_GCTL_SOFITPSYNC BIT(10)
161-
@@ -1166,6 +1172,10 @@ struct dwc3_glue_ops {
161+
@@ -1164,6 +1170,10 @@ struct dwc3_glue_ops {
162162
* @sys_wakeup: set if the device may do system wakeup.
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* @wakeup_configured: set if the device is configured for remote wakeup.
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* @suspended: set to track suspend event due to U3/L2.
@@ -169,7 +169,7 @@ index 111111111111..222222222222 100644
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* @susphy_state: state of DWC3_GUSB2PHYCFG_SUSPHY + DWC3_GUSB3PIPECTL_SUSPHY
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* before PM suspend.
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* @imod_interval: set the interrupt moderation interval in 250ns
172-
@@ -1411,6 +1421,8 @@ struct dwc3 {
172+
@@ -1409,6 +1419,8 @@ struct dwc3 {
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unsigned suspended:1;
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unsigned susphy_state:1;
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