Skip to content

Commit b0a24dc

Browse files
pyavitzpyavitz
committed
SpacemiT: Add cpu scaling for K1 SoC (WIP)
https://lore.kernel.org/spacemit/20260308-shadow-deps-v1-0-0ceb5c7c07eb@mailbox.org/T/#t Signed-off-by: Patrick Yavitz <pyavitz@gmail.com>
1 parent da7ad8b commit b0a24dc

2 files changed

Lines changed: 209 additions & 0 deletions

File tree

‎patch/kernel/archive/spacemit-7.0/011-PATCH-clk-spacemit-ccu_mix-fix-inverted-condition-in-ccu_mix_trigger_fc.patch‎

Lines changed: 32 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,32 @@
1+
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
2+
From: Shuwei Wu <shuwei.wu@mailbox.org>
3+
Date: Thu, 05 Mar 2026 20:46:08 +0800
4+
Subject: [PATCH] clk: spacemit: ccu_mix: fix inverted condition in
5+
ccu_mix_trigger_fc()
6+
7+
Fix inverted condition that skips frequency change trigger,
8+
causing kernel panics during cpufreq scaling.
9+
10+
Fixes: 1b72c59db0ad ("clk: spacemit: Add clock support for SpacemiT K1 SoC")
11+
Signed-off-by: Shuwei Wu <shuwei.wu@mailbox.org>
12+
---
13+
drivers/clk/spacemit/ccu_mix.c | 2 +-
14+
1 file changed, 1 insertion(+), 1 deletion(-)
15+
16+
diff --git a/drivers/clk/spacemit/ccu_mix.c b/drivers/clk/spacemit/ccu_mix.c
17+
index 9578366e9746..a8b407049bf4 100644
18+
--- a/drivers/clk/spacemit/ccu_mix.c
19+
+++ b/drivers/clk/spacemit/ccu_mix.c
20+
@@ -73,7 +73,7 @@ static int ccu_mix_trigger_fc(struct clk_hw *hw)
21+
struct ccu_common *common = hw_to_ccu_common(hw);
22+
unsigned int val;
23+
24+
- if (common->reg_fc)
25+
+ if (!common->reg_fc)
26+
return 0;
27+
28+
ccu_update(common, fc, common->mask_fc, common->mask_fc);
29+
30+
--
31+
2.52.0
32+

‎patch/kernel/archive/spacemit-7.0/016-riscv-dts-spacemit-Add-cpu-scaling-for-K1-SoC.patch‎

Lines changed: 177 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,177 @@
1+
From af48951c69bcbadcd0b774121884d2033350616e Mon Sep 17 00:00:00 2001
2+
From: Shuwei Wu <shuwei.wu@mailbox.org>
3+
Date: Sun, 8 Mar 2026 17:43:49 -0400
4+
Subject: [PATCH] cpufreq: dt-platdev: Add SpacemiT K1 SoC to the allow list
5+
6+
Signed-off-by: Shuwei Wu <shuwei.wu@mailbox.org>
7+
---
8+
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
9+
1 file changed, 1 insertion(+)
10+
11+
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
12+
index 25fd3b191b7e..31a64739df25 100644
13+
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
14+
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
15+
@@ -81,6 +81,7 @@ static const struct of_device_id allowlist[] __initconst = {
16+
{ .have_governor_per_policy = true, },
17+
},
18+
19+
+ { .compatible = "spacemit,k1", },
20+
{ .compatible = "st-ericsson,u8500", },
21+
{ .compatible = "st-ericsson,u8540", },
22+
{ .compatible = "st-ericsson,u9500", },
23+
--
24+
2.53.0
25+
26+
27+
From 7d3e14e047fd68341fa4b8bc194e98c70ce6fef1 Mon Sep 17 00:00:00 2001
28+
From: Shuwei Wu <shuwei.wu@mailbox.org>
29+
Date: Sun, 8 Mar 2026 17:28:57 -0400
30+
Subject: [PATCH] riscv: dts: spacemit: Add cpu scaling for K1 SoC
31+
32+
Add Operating Performance Points (OPP) tables and CPU clock properties
33+
for the two clusters in the SpacemiT K1 SoC.
34+
35+
Edited-by: Patrick Yavitz <pyavitz@gmail.com>
36+
Signed-off-by: Shuwei Wu <shuwei.wu@mailbox.org>
37+
---
38+
.../boot/dts/spacemit/k1-cpu-opp-table.dtsi | 113 ++++++++++++++++++
39+
arch/riscv/boot/dts/spacemit/k1.dtsi | 2 +-
40+
2 files changed, 114 insertions(+), 1 deletion(-)
41+
create mode 100644 arch/riscv/boot/dts/spacemit/k1-cpu-opp-table.dtsi
42+
43+
diff --git a/arch/riscv/boot/dts/spacemit/k1-cpu-opp-table.dtsi b/arch/riscv/boot/dts/spacemit/k1-cpu-opp-table.dtsi
44+
new file mode 100644
45+
index 000000000000..cfe52d498b4d
46+
--- /dev/null
47+
+++ b/arch/riscv/boot/dts/spacemit/k1-cpu-opp-table.dtsi
48+
@@ -0,0 +1,113 @@
49+
+// SPDX-License-Identifier: GPL-2.0 OR MIT
50+
+
51+
+&cpus {
52+
+ cluster0_opp_table: opp-table-cluster0 {
53+
+ compatible = "operating-points-v2";
54+
+ opp-shared;
55+
+
56+
+ opp-614400000 {
57+
+ opp-hz = /bits/ 64 <614400000>;
58+
+ opp-microvolt = <950000>;
59+
+ clock-latency-ns = <200000>;
60+
+ };
61+
+
62+
+ opp-819000000 {
63+
+ opp-hz = /bits/ 64 <819000000>;
64+
+ opp-microvolt = <950000>;
65+
+ clock-latency-ns = <200000>;
66+
+ };
67+
+
68+
+ opp-1000000000 {
69+
+ opp-hz = /bits/ 64 <1000000000>;
70+
+ opp-microvolt = <950000>;
71+
+ clock-latency-ns = <200000>;
72+
+ };
73+
+
74+
+ opp-1228800000 {
75+
+ opp-hz = /bits/ 64 <1228800000>;
76+
+ opp-microvolt = <950000>;
77+
+ clock-latency-ns = <200000>;
78+
+ };
79+
+
80+
+ opp-1600000000 {
81+
+ opp-hz = /bits/ 64 <1600000000>;
82+
+ opp-microvolt = <1050000>;
83+
+ clock-latency-ns = <200000>;
84+
+ };
85+
+ };
86+
+
87+
+ cluster1_opp_table: opp-table-cluster1 {
88+
+ compatible = "operating-points-v2";
89+
+ opp-shared;
90+
+
91+
+ opp-614400000 {
92+
+ opp-hz = /bits/ 64 <614400000>;
93+
+ opp-microvolt = <950000>;
94+
+ clock-latency-ns = <200000>;
95+
+ };
96+
+
97+
+ opp-819000000 {
98+
+ opp-hz = /bits/ 64 <819000000>;
99+
+ opp-microvolt = <950000>;
100+
+ clock-latency-ns = <200000>;
101+
+ };
102+
+
103+
+ opp-1000000000 {
104+
+ opp-hz = /bits/ 64 <1000000000>;
105+
+ opp-microvolt = <950000>;
106+
+ clock-latency-ns = <200000>;
107+
+ };
108+
+
109+
+ opp-1228800000 {
110+
+ opp-hz = /bits/ 64 <1228800000>;
111+
+ opp-microvolt = <950000>;
112+
+ clock-latency-ns = <200000>;
113+
+ };
114+
+
115+
+ opp-1600000000 {
116+
+ opp-hz = /bits/ 64 <1600000000>;
117+
+ opp-microvolt = <1050000>;
118+
+ clock-latency-ns = <200000>;
119+
+ };
120+
+ };
121+
+};
122+
+
123+
+&cpu_0 {
124+
+ clocks = <&syscon_apmu CLK_CPU_C0_CORE>, <&syscon_apmu CLK_CPU_C1_CORE>;
125+
+ operating-points-v2 = <&cluster0_opp_table>, <&cluster1_opp_table>;
126+
+};
127+
+
128+
+&cpu_1 {
129+
+ clocks = <&syscon_apmu CLK_CPU_C0_CORE>, <&syscon_apmu CLK_CPU_C1_CORE>;
130+
+ operating-points-v2 = <&cluster0_opp_table>, <&cluster1_opp_table>;
131+
+};
132+
+
133+
+&cpu_2 {
134+
+ clocks = <&syscon_apmu CLK_CPU_C0_CORE>, <&syscon_apmu CLK_CPU_C1_CORE>;
135+
+ operating-points-v2 = <&cluster0_opp_table>, <&cluster1_opp_table>;
136+
+};
137+
+
138+
+&cpu_3 {
139+
+ clocks = <&syscon_apmu CLK_CPU_C0_CORE>, <&syscon_apmu CLK_CPU_C1_CORE>;
140+
+ operating-points-v2 = <&cluster0_opp_table>, <&cluster1_opp_table>;
141+
+};
142+
+
143+
+&cpu_4 {
144+
+ clocks = <&syscon_apmu CLK_CPU_C0_CORE>, <&syscon_apmu CLK_CPU_C1_CORE>;
145+
+ operating-points-v2 = <&cluster0_opp_table>, <&cluster1_opp_table>;
146+
+};
147+
+
148+
+&cpu_5 {
149+
+ clocks = <&syscon_apmu CLK_CPU_C0_CORE>, <&syscon_apmu CLK_CPU_C1_CORE>;
150+
+ operating-points-v2 = <&cluster0_opp_table>, <&cluster1_opp_table>;
151+
+};
152+
+
153+
+&cpu_6 {
154+
+ clocks = <&syscon_apmu CLK_CPU_C0_CORE>, <&syscon_apmu CLK_CPU_C1_CORE>;
155+
+ operating-points-v2 = <&cluster0_opp_table>, <&cluster1_opp_table>;
156+
+};
157+
+
158+
+&cpu_7 {
159+
+ clocks = <&syscon_apmu CLK_CPU_C0_CORE>, <&syscon_apmu CLK_CPU_C1_CORE>;
160+
+ operating-points-v2 = <&cluster0_opp_table>, <&cluster1_opp_table>;
161+
+};
162+
diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
163+
index 529ec68e9c23..5d9d32b71efa 100644
164+
--- a/arch/riscv/boot/dts/spacemit/k1.dtsi
165+
+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
166+
@@ -13,7 +13,7 @@ / {
167+
model = "SpacemiT K1";
168+
compatible = "spacemit,k1";
169+
170+
- cpus {
171+
+ cpus: cpus {
172+
#address-cells = <1>;
173+
#size-cells = <0>;
174+
timebase-frequency = <24000000>;
175+
--
176+
2.53.0
177+

0 commit comments

Comments
 (0)