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Bigtreetech CB2: bump u-boot to 2026.04
1 parent acf7f06 commit c9ce036

2 files changed

Lines changed: 115 additions & 23 deletions

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config/boards/bigtreetech-cb2.conf

Lines changed: 3 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@ KERNEL_TARGET="current,edge"
1010
KERNEL_TEST_TARGET="current"
1111
BOOT_FDT_FILE="rockchip/rk3566-bigtreetech-pi2.dtb"
1212
IMAGE_PARTITION_TABLE="gpt"
13-
BOOT_SCENARIO="spl-blobs"
13+
BOOT_SCENARIO="binman"
1414
OVERLAY_PREFIX='rk3566'
1515
FULL_DESKTOP="yes"
1616
BOOT_LOGO="desktop"
@@ -20,29 +20,9 @@ function post_family_config__bigtreetech-cb2_uboot_overrides() {
2020

2121
display_alert "$BOARD" "mainline u-boot overrides" "info"
2222

23-
DDR_BLOB="rk35/rk3566_ddr_1056MHz_v1.21.bin"
24-
BL31_BLOB="rk35/rk3568_bl31_v1.44.elf" # NOT a typo, bl31 is shared across 68 and 66
25-
2623
declare -g BOOTDELAY=1
2724
declare -g BOOTSOURCE="https://github.com/u-boot/u-boot.git"
28-
declare -g BOOTBRANCH="tag:v2024.10"
29-
declare -g BOOTPATCHDIR="v2024.10/board_bigtreetech-cb2"
25+
declare -g BOOTBRANCH="tag:v2026.04"
26+
declare -g BOOTPATCHDIR="v2026.04"
3027
declare -g UBOOT_TARGET_MAP="BL31=${RKBIN_DIR}/${BL31_BLOB} ROCKCHIP_TPL=${RKBIN_DIR}/${DDR_BLOB};;u-boot-rockchip.bin"
31-
unset uboot_custom_postprocess write_uboot_platform write_uboot_platform_mtd # disable stuff from rockchip64_common; we're using binman here which does all the work already
32-
33-
# Just use the binman-provided u-boot-rockchip.bin, which is ready-to-go
34-
function write_uboot_platform() {
35-
dd "if=${1}/u-boot-rockchip.bin" "of=${2}" bs=32k seek=1 conv=notrunc
36-
}
37-
38-
function write_uboot_platform_mtd() {
39-
declare -a extra_opts_flashcp=("--verbose")
40-
if flashcp -h | grep -q -e '--partition'; then
41-
echo "Confirmed flashcp supports --partition -- read and write only changed blocks." >&2
42-
extra_opts_flashcp+=("--partition")
43-
else
44-
echo "flashcp does not support --partition, will write full SPI flash blocks." >&2
45-
fi
46-
flashcp "${extra_opts_flashcp[@]}" "${1}/u-boot-rockchip-spi.bin" /dev/mtd0
47-
}
4828
}
Lines changed: 112 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,112 @@
1+
CONFIG_ARM=y
2+
CONFIG_ARCH_ROCKCHIP=y
3+
CONFIG_SYS_MALLOC_F_LEN=0x80000
4+
CONFIG_SF_DEFAULT_SPEED=20000000
5+
CONFIG_DEFAULT_DEVICE_TREE="rockchip/rk3566-bigtreetech-pi2"
6+
CONFIG_ROCKCHIP_RK3568=y
7+
CONFIG_SPL_SERIAL=y
8+
CONFIG_SYS_LOAD_ADDR=0xc00800
9+
CONFIG_DEBUG_UART_BASE=0xFE660000
10+
CONFIG_DEBUG_UART_CLOCK=24000000
11+
CONFIG_SPL_LIBDISK_SUPPORT=y
12+
CONFIG_SPL_SPI_FLASH_SUPPORT=y
13+
CONFIG_SPL_SPI=y
14+
CONFIG_PCI=y
15+
CONFIG_DEBUG_UART=y
16+
CONFIG_FIT=y
17+
CONFIG_FIT_VERBOSE=y
18+
CONFIG_SPL_FIT_SIGNATURE=y
19+
CONFIG_SPL_LOAD_FIT=y
20+
CONFIG_LEGACY_IMAGE_FORMAT=y
21+
CONFIG_BOOTDELAY=0
22+
# CONFIG_DISPLAY_CPUINFO is not set
23+
CONFIG_DISPLAY_BOARDINFO_LATE=y
24+
CONFIG_SPL_MAX_SIZE=0x40000
25+
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
26+
CONFIG_SPL_MMC_WRITE=y
27+
CONFIG_SPL_DM_RESET=y
28+
CONFIG_SPL_SPI_LOAD=y
29+
CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000
30+
CONFIG_SPL_ATF=y
31+
CONFIG_SYS_PROMPT="BTTPI2@uboot:~$ "
32+
CONFIG_CMD_BOOTZ=y
33+
# CONFIG_CMD_ELF is not set
34+
# CONFIG_CMD_IMI is not set
35+
# CONFIG_CMD_XIMG is not set
36+
# CONFIG_CMD_LZMADEC is not set
37+
# CONFIG_CMD_UNZIP is not set
38+
CONFIG_CMD_GPT=y
39+
# CONFIG_CMD_LOADB is not set
40+
# CONFIG_CMD_LOADS is not set
41+
CONFIG_CMD_MMC=y
42+
CONFIG_CMD_MTD=y
43+
CONFIG_CMD_PCI=y
44+
CONFIG_CMD_USB=y
45+
CONFIG_CMD_USB_MASS_STORAGE=y
46+
# CONFIG_CMD_ITEST is not set
47+
CONFIG_CMD_TFTPPUT=y
48+
# CONFIG_NET_TFTP_VARS is not set
49+
# CONFIG_SPL_DOS_PARTITION is not set
50+
# CONFIG_ISO_PARTITION is not set
51+
CONFIG_EFI_PARTITION_ENTRIES_NUMBERS=64
52+
CONFIG_SPL_OF_CONTROL=y
53+
CONFIG_OF_LIVE=y
54+
CONFIG_OF_UPSTREAM=y
55+
CONFIG_OF_SPL_REMOVE_PROPS=""
56+
CONFIG_SPL_DM_SEQ_ALIAS=y
57+
CONFIG_SPL_REGMAP=y
58+
CONFIG_SPL_SYSCON=y
59+
CONFIG_SPL_CLK=y
60+
CONFIG_FASTBOOT_BUF_ADDR=0xc00800
61+
CONFIG_FASTBOOT_BUF_SIZE=0x04000000
62+
CONFIG_ROCKCHIP_GPIO=y
63+
CONFIG_SYS_I2C_ROCKCHIP=y
64+
CONFIG_LED=y
65+
CONFIG_LED_GPIO=y
66+
CONFIG_MISC=y
67+
CONFIG_MMC_DW=y
68+
CONFIG_MMC_DW_ROCKCHIP=y
69+
CONFIG_MMC_SDHCI=y
70+
CONFIG_MMC_SDHCI_SDMA=y
71+
CONFIG_MMC_SDHCI_ROCKCHIP=y
72+
CONFIG_SPI_FLASH_EON=y
73+
CONFIG_SPI_FLASH_GIGADEVICE=y
74+
CONFIG_SPI_FLASH_MACRONIX=y
75+
CONFIG_SPI_FLASH_WINBOND=y
76+
CONFIG_SPI_FLASH_XMC=y
77+
CONFIG_SPI_FLASH_MTD=y
78+
CONFIG_PHY_MOTORCOMM=y
79+
CONFIG_DM_ETH_PHY=y
80+
CONFIG_PHY_GIGE=y
81+
CONFIG_DWC_ETH_QOS=y
82+
CONFIG_NVME=y
83+
CONFIG_DM_PCI_COMPAT=y
84+
CONFIG_PCIE_DW_ROCKCHIP=y
85+
CONFIG_PHY_ROCKCHIP_INNO_USB2=y
86+
CONFIG_PHY_ROCKCHIP_NANENG_COMBOPHY=y
87+
CONFIG_SPL_PINCTRL=y
88+
CONFIG_DM_PMIC=y
89+
CONFIG_PMIC_RK8XX=y
90+
CONFIG_SPL_PMIC_RK8XX=y
91+
CONFIG_REGULATOR_RK8XX=y
92+
CONFIG_SPL_RAM=y
93+
CONFIG_ROCKCHIP_SDRAM_COMMON=y
94+
CONFIG_BAUDRATE=1500000
95+
CONFIG_DEBUG_UART_SHIFT=2
96+
CONFIG_SYS_NS16550_MEM32=y
97+
CONFIG_ROCKCHIP_SFC=y
98+
CONFIG_SYSRESET=y
99+
CONFIG_USB=y
100+
CONFIG_USB_XHCI_HCD=y
101+
CONFIG_USB_XHCI_DWC3=y
102+
CONFIG_USB_XHCI_PCI=y
103+
CONFIG_USB_EHCI_HCD=y
104+
CONFIG_USB_EHCI_GENERIC=y
105+
CONFIG_USB_OHCI_HCD=y
106+
CONFIG_USB_OHCI_GENERIC=y
107+
CONFIG_USB_DWC3=y
108+
CONFIG_USB_DWC3_GENERIC=y
109+
CONFIG_USB_GADGET=y
110+
CONFIG_SHA512=y
111+
CONFIG_SPL_GZIP=y
112+
CONFIG_ERRNO_STR=y

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