From 0563501683d7f9e665eeb0da0c6ef443f5cf5efd Mon Sep 17 00:00:00 2001
From: The-going <48602507+The-going@users.noreply.github.com>
Date: Tue, 29 Apr 2025 16:36:16 +0300
Subject: [PATCH 1/7] sunxi-6.14: Add megous patches

---
 ...entation-and-rotation-for-PinePhone-.patch |   31 +
 .../ARM-dts-axp813-Add-charger-LED.patch      |   30 +
 ...Book-Touch-Lux-3-display-ctp-support.patch |  185 +
 .../ARM-dts-sun5i-Add-soc-handle.patch        |   26 +
 ...book-touch-lux-3-Add-RTC-clock-cells.patch |   27 +
 .../ARM-dts-sun8i-a83t-Add-MBUS-node.patch    |   39 +
 ...us-video-codec-support-to-A83T-untes.patch |   37 +
 ...M-dts-sun8i-a83t-Add-hdmi-sound-card.patch |   48 +
 ...un8i-a83t-Add-missing-GPU-trip-point.patch |   35 +
 ...-hdmi-sound-card-on-boards-with-hdmi.patch |   69 +
 ...prove-CPU-OPP-tables-go-up-to-1.8GHz.patch |  134 +
 ...s-sun8i-a83t-Set-fifo-size-for-uarts.patch |   59 +
 ...-a83t-tbs-a711-Add-PN544-NFC-support.patch |   66 +
 ...711-Add-camera-sensors-HM5065-GC2145.patch |  180 +
 ...-a83t-tbs-a711-Add-flash-led-support.patch |   32 +
 ...-Add-powerup-down-support-for-the-3G.patch |   61 +
 ...-Add-regulators-to-the-accelerometer.patch |   30 +
 ...11-Add-sound-support-via-AC100-codec.patch |  131 +
 ...1-Add-support-for-the-vibrator-motor.patch |   39 +
 ...8i-a83t-tbs-a711-Enable-charging-LED.patch |   31 +
 ...-Give-Linux-more-privileges-over-SCP.patch |   47 +
 ...711-Increase-voltage-on-the-vibrator.patch |   30 +
 ...s-bananapi-m2-zero-Enable-HDMI-audio.patch |   42 +
 ...-hdmi-sound-card-on-boards-with-hdmi.patch |  272 ++
 ...se-my-own-more-aggressive-OPPs-on-H3.patch |   72 +
 ...-pi-one-Enable-all-gpio-header-UARTs.patch |   49 +
 ...pc-Increase-max-CPUX-voltage-to-1.4V.patch |   31 +
 ...RM-dts-sun8i-r40-Add-hdmi-sound-card.patch |   48 +
 ...-bananapi-m2-ultra-Enable-HDMI-audio.patch |   42 +
 ...-bananapi-m2-berry-Enable-HDMI-audio.patch |   42 +
 .../ARM-dts-suni-a83t-Add-i2s0-pins.patch     |   29 +
 .../ARM-dts-sunxi-Add-aliases-for-MMC.patch   |   66 +
 ...ARM-dts-sunxi-a83t-Add-SCPI-protocol.patch |   52 +
 ...RM-dts-sunxi-h3-h5-Add-SCPI-protocol.patch |   81 +
 ...-dts-sunxi-h3-h5-Add-hdmi-sound-card.patch |   48 +
 ...suspend-to-memory-implementation-for.patch |   88 +
 ...-send-suspend-message-to-SCP-on-A83T.patch |   54 +
 ...g_support_set-is-not-supported-on-A8.patch |   27 +
 ...9i-hdmi-audio-Initial-implementation.patch |  233 +
 ...-New-codec-driver-for-the-EC25-modem.patch |  154 +
 ...of-playback-speed-after-system-sleep.patch |   45 +
 ...-to-define-pins-for-aux-jack-devices.patch |   67 +
 ...-Add-debug-output-for-jack-detection.patch |  129 +
 ...-jack-type-to-be-set-via-device-tree.patch |   47 +
 ...codec-Set-jack_type-from-DT-in-probe.patch |   48 +
 ...C-sun8i-codec-define-button-keycodes.patch |   31 +
 ...-with-information-and-u-boot-patches.patch |  215 +
 ...upport-for-my-private-Sapomat-device.patch |   66 +
 .../Defconfigs-for-all-my-devices.patch       | 4002 +++++++++++++++++
 ...lwinner-sram-dependency-on-h616-h618.patch |   53 +
 .../patches.megous/Fix-intptr_t-typedef.patch |   32 +
 ...INTAINERS-Add-entry-for-Himax-HM5065.patch |   30 +
 ...-Pi-PC-and-PC-2-work-as-power-off-bu.patch |   39 +
 ...async-probe-with-PROBE_PREFER_ASYNCH.patch |   40 +
 .../Move-a-node-to-avoid-merge-conflict.patch |  115 +
 .../Revert-Input-cyttsp4-remove-driver.patch  | 3232 +++++++++++++
 ...-sun4i-lvds-Invert-the-LVDS-polarity.patch |   28 +
 ...ister-existing-source-caps-before-re.patch |   39 +
 ...able-K101-IM2BYL02-panel-for-PineTab.patch |   35 +
 ...ner-Enforce-consistent-MMC-numbering.patch |   66 +
 ...ts-allwinner-a64-Add-hdmi-sound-card.patch |   48 +
 ...ble-hdmi-sound-card-on-boards-with-h.patch |  204 +
 ...s-allwinner-a64-Fix-LRADC-compatible.patch |   32 +
 ...lwinner-a64-pinetab-add-front-camera.patch |   99 +
 ...le-hdmi-sound-card-on-boards-with-hd.patch |  113 +
 ...dts-allwinner-h6-Add-hdmi-sound-card.patch |   56 +
 ...le-hdmi-sound-card-on-boards-with-hd.patch |  123 +
 ...llwinner-orange-pi-3-Enable-ethernet.patch |  105 +
 .../arm64-dts-rk3399-Add-dmc_opp_table.patch  |   62 +
 ...-dts-rockchip-rk3399-s-Add-DMC-table.patch |   62 +
 ...56x-Fix-PCIe-register-map-and-ranges.patch |   47 +
 ...a64-pinephone-Define-jack-pins-in-DT.patch |   30 +
 ...entation-and-rotation-for-PinePhone-.patch |   31 +
 ...s-sun50i-a64-Set-fifo-size-for-uarts.patch |   59 +
 ...one-Add-Type-C-support-for-all-PP-va.patch |  416 ++
 ...one-Add-detailed-OCV-to-capactiy-con.patch |  187 +
 ...a64-pinephone-Add-front-back-cameras.patch |  130 +
 ...pinephone-Add-interrupt-pin-for-WiFi.patch |   26 +
 ...64-pinephone-Add-modem-power-manager.patch |  119 +
 ...inephone-Add-power-supply-to-stk3311.patch |   27 +
 ...a64-pinephone-Add-reboot-mode-driver.patch |   80 +
 ...one-Add-supply-for-i2c-bus-to-anx768.patch |   54 +
 ...hone-Add-support-for-Bluetooth-audio.patch |   33 +
 ...one-Add-support-for-Pinephone-1.2-be.patch |   54 +
 ...one-Add-support-for-Pinephone-keyboa.patch |  170 +
 ...inephone-Add-support-for-modem-audio.patch |   71 +
 ...nephone-Bump-I2C-frequency-to-400kHz.patch |   35 +
 ...one-Don-t-make-lradc-keys-a-wakeup-s.patch |   29 +
 ...one-Enable-Pinephone-Keyboard-power-.patch |   34 +
 ...-pinephone-Enable-internal-HMIC-bias.patch |   29 +
 ...ephone-Fix-BH-modem-manager-behavior.patch |   29 +
 ...one-Power-off-the-touch-controller-i.patch |   28 +
 ...one-Set-minimum-backlight-duty-cycle.patch |   73 +
 ...one-Shorten-post-power-on-delay-on-m.patch |   43 +
 ...one-Use-newer-jack-detection-impleme.patch |   35 +
 ...one-Workaround-broken-HDMI-HPD-signa.patch |   84 +
 ...sun50i-a64-pinetab-Add-accelerometer.patch |   38 +
 ...-a64-pinetab-Name-sound-card-PineTab.patch |   28 +
 ...4-pinetab-enable-RTL8723CS-bluetooth.patch |   44 +
 ...sun50i-h5-Add-missing-GPU-trip-point.patch |   35 +
 ...se-my-own-more-aggressive-OPPs-on-H5.patch |   97 +
 ...s-without-benchmark-to-speed-up-boot.patch |   45 +
 ..._rts_on_open-true-behavior-on-bcm207.patch |   35 +
 ...-t-re-initialize-rtl8723cs-on-resume.patch |   28 +
 ...PLL-gating-and-CPUX-reparenting-to-H.patch |   55 +
 ...sunxi-ng-Export-CLK_DRAM-for-devfreq.patch |   59 +
 ...sunxi-ng-Mark-TWD-clocks-as-critical.patch |   56 +
 ...and-M-factors-to-1-for-H3-pll-cpux-c.patch |   59 +
 ...64-Increase-PLL_AUDIO-base-frequency.patch |   87 +
 ...tch-parent-of-MIPI-DSI-to-periph0-1x.patch |   48 +
 ...etected-CPU-bin-for-easier-debugging.patch |   29 +
 ...-accept-HPD-status-from-other-driver.patch |  152 +
 ...e-dw-hdmi-Report-HDMI-hotplug-events.patch |   41 +
 ...-timings-to-make-refresh-rate-exactl.patch |   37 +
 ...reboot-when-DRM-device-fails-to-bind.patch |   36 +
 ...rockchip-Fix-ISP1-PHY-initialization.patch |   35 +
 ...drm-sun4i-Implement-gamma-correction.patch |  131 +
 ...one-of-the-UI-planes-as-a-cursor-one.patch |   73 +
 ...er-display-pipeline-state-from-p-boo.patch |  547 +++
 ...ing-dclk-rate-upon-ancestor-clock-ch.patch |  179 +
 ...20x-adc-allow-to-use-TS-pin-as-GPADC.patch |   34 +
 ...-vibrator-Don-t-require-enable-gpios.patch |   35 +
 ...Add-a-binding-for-AXP813-charger-led.patch |   46 +
 ...dings-for-Himax-HM5065-camera-sensor.patch |   71 +
 ...dec-related-properties-to-AC100-PMIC.patch |   84 +
 ...ack-type-property-to-sun8i-a33-codec.patch |   36 +
 ...port-unidirectional-mailbox-channels.patch |  127 +
 ...or-sending-a-SCPI_CMD_SET_SYS_PWR_ST.patch |   87 +
 ...nd-soft-powerdown-message-on-suspend.patch |   64 +
 .../hm5065-yaml-bindings-wip.patch            |  109 +
 ...ss-when-pinctrl-recovery-state-is-no.patch |   35 +
 ...dc-allow-to-set-TS-pin-to-GPADC-mode.patch |   42 +
 ...ow-to-use-sun5i-a13-gpadc-iio-from-D.patch |   61 +
 ...-error-when-the-device-is-not-presen.patch |   39 +
 ...-Clear-the-ids-buffer-in-a-saner-way.patch |   32 +
 ...scate-MT-signals-setup-platform-data.patch |  263 ++
 ...-De-obfuscate-platform-data-for-keys.patch |   85 +
 ...-ENOSYS-error-is-ok-when-powering-up.patch |   29 +
 ...ter-recovery-from-failed-wakeup-HACK.patch |   31 +
 .../input-cyttsp4-Fix-compile-issue.patch     |   28 +
 .../input-cyttsp4-Fix-probe-oops.patch        |   29 +
 .../input-cyttsp4-Fix-warnings.patch          |   47 +
 ...river-not-hog-the-system-s-workqueue.patch |  105 +
 ...-the-driver-to-use-device-properties.patch |  590 +++
 ...t-cyttsp4-Remove-unused-enable_vkeys.patch |   27 +
 ...s-indirection-with-driver-platform-d.patch |  718 +++
 ...keup-wakeup-by-I2C-read-doesn-t-work.patch |  125 +
 ...i2c-spi-names-directly-in-the-driver.patch |   64 +
 ...se-vcc-supply-alone-to-control-the-v.patch |   76 +
 ...ort-charger-LED-on-AXP20x-like-PMICs.patch |  345 ++
 ...ilbox-while-timekeeping-is-suspended.patch |   64 +
 ...o-clean-up-hardware-on-probe-failure.patch |   35 +
 ...IXEL_RATE-HBLANK-and-VBLANK-controls.patch |  549 +++
 .../media-gc2145-Added-BGGR-bayer-mode.patch  |   30 +
 .../media-gc2145-Disable-debug-output.patch   |   37 +
 ...2145-Galaxycore-camera-module-driver.patch | 2306 ++++++++++
 ...edia-gc2145-fix-white-balance-colors.patch |  183 +
 ...edia-gc2145-implement-system-suspend.patch |   72 +
 ...river-for-Himax-HM5065-camera-sensor.patch | 2268 ++++++++++
 ...-Move-upstream-driver-out-of-the-way.patch |   52 +
 ...gc2145-Parse-and-register-properties.patch |   43 +
 ...40-Add-read-only-property-for-vblank.patch |   24 +
 ...werup-the-sensor-during-driver-probe.patch |  119 +
 ...-Try-to-disable-denoising-sharpening.patch |   50 +
 ...cus-commands-blocking-until-complete.patch |  113 +
 .../media-ov5640-Implement-autofocus.patch    |  395 ++
 ...media-ov5640-Improve-error-reporting.patch |   43 +
 ...ia-ov5640-Improve-firmware-load-time.patch |  177 +
 ...weroff-to-ensure-next-poweron-is-not.patch |   29 +
 ...a-ov5640-set-default-ae-target-lower.patch |   27 +
 ..._force_suspend-resume-for-system-sus.patch |   31 +
 ...Fix-call-to-pm_runtime_set_suspended.patch |   29 +
 ...multicamera-support-for-parallel-bus.patch |  166 +
 ...6i-csi-add-V4L2_CAP_IO_MC-capability.patch |   82 +
 ...-subdev-operation-to-access-bridge-f.patch |  128 +
 ...csi-implement-vidioc_enum_framesizes.patch |   65 +
 ..._csi_formats-and-sun6i_csi_formats_m.patch |  431 ++
 ...subdev-active-state-to-store-active-.patch |  346 ++
 ...mfd-axp20x-Add-battery-IRQ-resources.patch |  102 +
 ...modem-power-Power-manager-for-modems.patch | 2048 +++++++++
 ...dd-delay-after-power-class-selection.patch |   38 +
 ...rockchip-fix-sdmmc-after-soft-reboot.patch |   52 +
 .../mmc-sunxi-mmc-Remove-runtime-PM.patch     |  143 +
 ...-spi-nor-Add-Alliance-memory-support.patch |   85 +
 ...td-spi-nor-Add-vdd-regulator-support.patch |   33 +
 ...t-for-enabling-a-regulator-for-PHY-I.patch |   89 +
 ...-regulator-variable-to-regulator_phy.patch |   81 +
 ...devm_regulator_get-for-PHY-regulator.patch |   84 +
 ...Add-support-for-VBAT-PVDD-regulators.patch |  106 +
 ...devlink-Support-allwinner-sram-links.patch |   58 +
 ...ror-when-no-regulator-is-defined-in-.patch |   31 +
 ...-on-poweroff-reboot-on-Orange-Pi-5-P.patch |   32 +
 ...-usb-Add-support-for-usb_role_switch.patch |  146 +
 ...Allow-to-set-target-voltage-to-4.35V.patch |   31 +
 ...upts-for-low-battery-power-condition.patch |   43 +
 ...r-USB_BC_ENABLED-and-USB_DCP_INPUT_C.patch |   45 +
 ...-Add-support-for-POWER_SUPPLY_PROP_E.patch |   90 +
 ...-battery-Enable-poweron-by-RTC-alarm.patch |   35 +
 ...attery-Improve-probe-error-reporting.patch |   69 +
 ...-Support-POWER_SUPPLY_PROP_CHARGE_BE.patch |   86 +
 ...20x-usb-power-Add-missing-interrupts.patch |   59 +
 ...wer-Change-Vbus-hold-voltage-to-4.5V.patch |   38 +
 ...attery-Add-support-for-reporting-OCV.patch |   63 +
 ..._battery-Fix-charging-done-detection.patch |   40 +
 ...xp20x_battery-Monitor-battery-health.patch |  117 +
 ...tery-Send-uevents-for-status-changes.patch |  149 +
 ...-Setup-thermal-regulation-experiment.patch |   82 +
 ...-for-enabling-a-regulator-from-users.patch |  192 +
 ...support-for-vin-supply-for-drivevbus.patch |   61 +
 ...r-temperature-protection-and-16s-res.patch |   41 +
 ...SEN-to-input-on-x-powers-sense-vbus-.patch |   53 +
 ...hwmon-device-for-reading-temperature.patch |  235 +
 ...tp65185x-eInk-panel-regulator-driver.patch |  487 ++
 ...-which-error-caused-RTC-read-failure.patch |   31 +
 ...un6i-Allow-RTC-wakeup-after-shutdown.patch |   69 +
 ...rt-analog-part-of-X-Powers-AC100-cod.patch | 1074 +++++
 ...upport-for-digital-part-of-the-AC100.patch |  371 ++
 ..._probe-to-handle-EPROBE_DEFER-errors.patch |  150 +
 ...ermal-sun8i-Be-loud-when-probe-fails.patch |   88 +
 ...gling-pointer-in-netdev-private-data.patch |  307 ++
 ...ng-host-side-code-on-SoCs-where-it-s.patch |  107 +
 ...set_resume-callback-for-WWAN-devices.patch |   33 +
 ...ayport-Respect-DP_CAP_RECEPTACLE-bit.patch |   99 +
 ...driver-for-ANX7688-USB-C-HDMI-bridge.patch | 2333 ++++++++++
 ...usb-typec-anx7688-Port-to-Linux-6.10.patch |   28 +
 .../usb-typec-anx7688-Port-to-Linux-6.9.patch |  110 +
 ...-typec-fusb302-Add-OF-extcon-support.patch |   38 +
 ...-interrupts-before-we-start-toggling.patch |   40 +
 ...bugging-interface-with-driver-state-.patch |  112 +
 ...pec-fusb302-Fix-register-definitions.patch |   49 +
 ...seful-of-logging-status-on-interrupt.patch |  189 +
 ...ding-of-CC-pins-status-if-activity-i.patch |   76 +
 ...-the-current-before-enabling-pullups.patch |   50 +
 ...-increase-wait-time-for-BC1.2-result.patch |   33 +
 ...US-state-even-if-VBUS-interrupt-is-n.patch |   43 +
 ...PD-devices-capabilities-registration.patch |   95 +
 .../usb-typec-tcpm-Improve-logs.patch         |   64 +
 ...altmodes-before-registering-new-ones.patch |   52 +
 ...xtcon-Add-typec-extcon-bridge-driver.patch |  384 ++
 ...ow-to-force-reset-on-each-mux-change.patch |   48 +
 ...ypec-extcon-Enable-debugging-for-now.patch |   25 +
 ...lay-driver-for-A13-based-PocketBooks.patch | 1274 ++++++
 ...w-to-change-lth_brightness-via-sysfs.patch |  126 +
 patch/kernel/archive/sunxi-6.14/series.conf   |  249 +
 patch/kernel/archive/sunxi-6.14/series.megous |  248 +
 245 files changed, 40484 insertions(+)
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/2-arm64-dts-sun50i-Define-orientation-and-rotation-for-PinePhone-.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-axp813-Add-charger-LED.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun5i-Add-PocketBook-Touch-Lux-3-display-ctp-support.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun5i-Add-soc-handle.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun5i-a13-pocketbook-touch-lux-3-Add-RTC-clock-cells.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-Add-MBUS-node.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-Add-cedrus-video-codec-support-to-A83T-untes.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-Add-hdmi-sound-card.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-Add-missing-GPU-trip-point.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-Enable-hdmi-sound-card-on-boards-with-hdmi.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-Improve-CPU-OPP-tables-go-up-to-1.8GHz.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-Set-fifo-size-for-uarts.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-PN544-NFC-support.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-camera-sensors-HM5065-GC2145.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-flash-led-support.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-powerup-down-support-for-the-3G.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-regulators-to-the-accelerometer.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-sound-support-via-AC100-codec.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-support-for-the-vibrator-motor.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Enable-charging-LED.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Give-Linux-more-privileges-over-SCP.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Increase-voltage-on-the-vibrator.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-h2-plus-bananapi-m2-zero-Enable-HDMI-audio.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-h3-Enable-hdmi-sound-card-on-boards-with-hdmi.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-h3-Use-my-own-more-aggressive-OPPs-on-H3.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-h3-orange-pi-one-Enable-all-gpio-header-UARTs.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-h3-orange-pi-pc-Increase-max-CPUX-voltage-to-1.4V.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-r40-Add-hdmi-sound-card.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-r40-bananapi-m2-ultra-Enable-HDMI-audio.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-v40-bananapi-m2-berry-Enable-HDMI-audio.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-suni-a83t-Add-i2s0-pins.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sunxi-Add-aliases-for-MMC.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sunxi-a83t-Add-SCPI-protocol.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sunxi-h3-h5-Add-SCPI-protocol.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sunxi-h3-h5-Add-hdmi-sound-card.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/ARM-sunxi-Add-experimental-suspend-to-memory-implementation-for.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/ARM-sunxi-Use-SCPI-to-send-suspend-message-to-SCP-on-A83T.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/ARM-sunxi-sunxi_cpu0_hotplug_support_set-is-not-supported-on-A8.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/ASOC-sun9i-hdmi-audio-Initial-implementation.patch
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 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/power-supply-axp20x-usb-power-Change-Vbus-hold-voltage-to-4.5V.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/power-supply-axp20x_battery-Add-support-for-reporting-OCV.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/power-supply-axp20x_battery-Fix-charging-done-detection.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/power-supply-axp20x_battery-Monitor-battery-health.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/power-supply-axp20x_battery-Send-uevents-for-status-changes.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/power-supply-axp20x_battery-Setup-thermal-regulation-experiment.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/regulator-Add-simple-driver-for-enabling-a-regulator-from-users.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/regulator-axp20x-Add-support-for-vin-supply-for-drivevbus.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/regulator-axp20x-Enable-over-temperature-protection-and-16s-res.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/regulator-axp20x-Turn-N_VBUSEN-to-input-on-x-powers-sense-vbus-.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/regulator-tp65185-Add-hwmon-device-for-reading-temperature.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/regulator-tp65185x-Add-tp65185x-eInk-panel-regulator-driver.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/rtc-Print-which-error-caused-RTC-read-failure.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/rtc-sun6i-Allow-RTC-wakeup-after-shutdown.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/sound-soc-ac100-codec-Support-analog-part-of-X-Powers-AC100-cod.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/sound-soc-sun8i-codec-Add-support-for-digital-part-of-the-AC100.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/sunxi-Use-dev_err_probe-to-handle-EPROBE_DEFER-errors.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/thermal-sun8i-Be-loud-when-probe-fails.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/usb-gadget-Fix-dangling-pointer-in-netdev-private-data.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/usb-musb-sunxi-Avoid-enabling-host-side-code-on-SoCs-where-it-s.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/usb-serial-option-add-reset_resume-callback-for-WWAN-devices.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-altmodes-displayport-Respect-DP_CAP_RECEPTACLE-bit.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-anx7688-Add-driver-for-ANX7688-USB-C-HDMI-bridge.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-anx7688-Port-to-Linux-6.10.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-anx7688-Port-to-Linux-6.9.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-fusb302-Add-OF-extcon-support.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-fusb302-Clear-interrupts-before-we-start-toggling.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-fusb302-Extend-debugging-interface-with-driver-state-.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-fusb302-Fix-register-definitions.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-fusb302-More-useful-of-logging-status-on-interrupt.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-fusb302-Retry-reading-of-CC-pins-status-if-activity-i.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-fusb302-Set-the-current-before-enabling-pullups.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-fusb302-Slightly-increase-wait-time-for-BC1.2-result.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-fusb302-Update-VBUS-state-even-if-VBUS-interrupt-is-n.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-tcpm-Fix-PD-devices-capabilities-registration.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-tcpm-Improve-logs.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-tcpm-Unregister-altmodes-before-registering-new-ones.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-typec-extcon-Add-typec-extcon-bridge-driver.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-typec-extcon-Allow-to-force-reset-on-each-mux-change.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-typec-extcon-Enable-debugging-for-now.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/video-fbdev-eInk-display-driver-for-A13-based-PocketBooks.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.megous/video-pwm_bl-Allow-to-change-lth_brightness-via-sysfs.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/series.conf
 create mode 100644 patch/kernel/archive/sunxi-6.14/series.megous

diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/2-arm64-dts-sun50i-Define-orientation-and-rotation-for-PinePhone-.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/2-arm64-dts-sun50i-Define-orientation-and-rotation-for-PinePhone-.patch
new file mode 100644
index 000000000000..d66e2953e969
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/2-arm64-dts-sun50i-Define-orientation-and-rotation-for-PinePhone-.patch
@@ -0,0 +1,31 @@
+From 63ede72498fdb55584228f62a27c7564a9bd3289 Mon Sep 17 00:00:00 2001
+From: Arnav Singh <me@arnavion.dev>
+Date: Mon, 6 May 2024 16:36:06 -0700
+Subject: arm64: dts: sun50i: Define orientation and rotation for PinePhone
+ front camera
+
+This enables libcamera to detect the correct orientation from
+the device tree and propagate it further to e.g. Pipewire.
+
+Signed-off-by: Arnav Singh <me@arnavion.dev>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index 1a57720c25ef..f0f1367c5868 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -593,6 +593,9 @@ gc2145: front-camera@3c {
+ 		reset-gpios = <&pio 4 16 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; /* PE16 */
+ 		enable-gpios = <&pio 4 17 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; /* PE17 */
+ 
++		orientation = <0>;
++		rotation = <90>;
++
+ 		port {
+ 			gc2145_ep: endpoint {
+ 				remote-endpoint = <&csi_gc2145_ep>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-axp813-Add-charger-LED.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-axp813-Add-charger-LED.patch
new file mode 100644
index 000000000000..c86157bdd809
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-axp813-Add-charger-LED.patch
@@ -0,0 +1,30 @@
+From 6f7050f399283cdef2e0a1598a41279fb1d2ab01 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 14 Nov 2017 02:47:51 +0100
+Subject: ARM: dts: axp813: Add charger LED
+
+PMIC supports charging status indication via a LED. Add support
+for it.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/boot/dts/allwinner/axp81x.dtsi | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/axp81x.dtsi b/arch/arm/boot/dts/allwinner/axp81x.dtsi
+index ebaf1c3ce8db..a4b1be159b02 100644
+--- a/arch/arm/boot/dts/allwinner/axp81x.dtsi
++++ b/arch/arm/boot/dts/allwinner/axp81x.dtsi
+@@ -161,4 +161,9 @@ reg_drivevbus: drivevbus {
+ 	usb_power_supply: usb-power {
+ 		compatible = "x-powers,axp813-usb-power-supply";
+ 	};
++
++	charger_led: charger-led {
++		compatible = "x-powers,axp813-charger-led";
++		status = "disabled";
++	};
+ };
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun5i-Add-PocketBook-Touch-Lux-3-display-ctp-support.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun5i-Add-PocketBook-Touch-Lux-3-display-ctp-support.patch
new file mode 100644
index 000000000000..773819230a37
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun5i-Add-PocketBook-Touch-Lux-3-display-ctp-support.patch
@@ -0,0 +1,185 @@
+From 1fdeabb9597a51122d1c07678c6dd94c15e40abf Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 23 Feb 2020 01:23:10 +0100
+Subject: ARM: dts: sun5i: Add PocketBook Touch Lux 3 display/ctp support
+
+Add support for display and touchscreen via out-of-tree drivers.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../sun5i-a13-pocketbook-touch-lux-3.dts      | 105 +++++++++++++++++-
+ 1 file changed, 103 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun5i-a13-pocketbook-touch-lux-3.dts b/arch/arm/boot/dts/allwinner/sun5i-a13-pocketbook-touch-lux-3.dts
+index d60407772e5d..db28ab621804 100644
+--- a/arch/arm/boot/dts/allwinner/sun5i-a13-pocketbook-touch-lux-3.dts
++++ b/arch/arm/boot/dts/allwinner/sun5i-a13-pocketbook-touch-lux-3.dts
+@@ -62,6 +62,11 @@ key-left {
+ 		};
+ 	};
+ 
++	regulator-eink {
++		compatible = "custom,reg-userspace-consumer";
++		controlled-supply = <&tp65185x>;
++	};
++
+ 	reg_1v8: regulator-1v8 {
+ 		compatible = "regulator-fixed";
+ 		regulator-name = "vdd-1v8-nor-ctp";
+@@ -79,7 +84,6 @@ reg_1v8_nor: regulator-nor {
+ 		gpio = <&pio 2 14 GPIO_ACTIVE_HIGH>;
+ 		enable-active-high;
+ 		vin-supply = <&reg_1v8>;
+-		regulator-always-on;
+ 	};
+ 
+ 	reg_1v8_ctp: regulator-ctp {
+@@ -112,6 +116,7 @@ &ehci0 {
+ 
+ &i2c0 {
+ 	status = "okay";
++	//XXX: bsp has pullup on PB0/PB1 pins enabled, but it works without it
+ 
+ 	axp209: pmic@34 {
+ 		reg = <0x34>;
+@@ -128,12 +133,42 @@ pcf8563: rtc@51 {
+ 		compatible = "nxp,pcf8563";
+ 		reg = <0x51>;
+ 	};
++
++	// hacky PMIC driver for eInk display
++	tp65185x: regulator@68 {
++		compatible = "tp,tp65185x";
++		reg = <0x68>;
++
++		regulator-min-microvolt = <3120000>;
++		regulator-max-microvolt = <3120000>;
++		regulator-name = "eink-vcom";
++
++		//XXX: we don't use interrupts in the driver right now
++		//interrupt-parent = <&pio>;
++		//interrupts = <1 10 IRQ_TYPE_LEVEL_LOW>; /* PB10 */
++
++		wakeup-gpios = <&pio 3 18 GPIO_ACTIVE_HIGH>; /* PD18 */
++		powerup-gpios = <&pio 4 7 GPIO_ACTIVE_HIGH>; /* PE7 */
++		vcom-gpios = <&pio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */
++		//XXX: not a pullup on BSP (might have an external resistor)
++		powergood-gpios = <&pio 4 6 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PE6 */
++	};
+ };
+ 
+ &i2c2 {
+ 	status = "okay";
+ 
+-	/* Touchpanel is connected here. */
++	touchpanel@24 {
++		compatible = "cypress,cyttsp4_i2c_adapter";
++		reg = <0x24>;
++
++		interrupt-parent = <&pio>;
++		interrupts = <6 11 IRQ_TYPE_EDGE_FALLING>; /* PG11 */
++
++		vdd-supply = <&reg_1v8_ctp>;
++		power-gpios = <&pio 4 5 GPIO_ACTIVE_LOW>; /* PE5 */
++		reset-gpios = <&pio 1 3 GPIO_ACTIVE_LOW>; /* PB3 */
++	};
+ };
+ 
+ &lradc {
+@@ -179,6 +214,20 @@ &otg_sram {
+ 	status = "okay";
+ };
+ 
++&pio {
++	eink_pins_active: eink-pins-lcd {
++		pins = "PD3", "PD4", "PD5", "PD6", "PD7", "PD10", "PD11", "PD12",
++			"PD13", "PD15", "PD20", "PD21", "PD22", "PD23", "PD24";
++		function = "lcd0";
++	};
++
++	eink_pins_idle: eink-pins-gpio {
++		pins = "PD3", "PD4", "PD5", "PD6", "PD7", "PD10", "PD11", "PD12",
++			"PD13", "PD15", "PD20", "PD21", "PD22", "PD23", "PD24";
++		function = "gpio_out";
++	};
++};
++
+ &pwm {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&pwm0_pin>;
+@@ -219,6 +268,55 @@ &reg_ldo3 {
+ 	regulator-ramp-delay = <1600>;
+ };
+ 
++&soc {
++	display-controller@1c0c000 {
++		pinctrl-names = "idle", "active";
++		pinctrl-0 = <&eink_pins_idle>;
++		pinctrl-1 = <&eink_pins_active>;
++
++		all-gpios = <&pio 3 3 GPIO_ACTIVE_HIGH>,
++			<&pio 3 4 GPIO_ACTIVE_HIGH>,
++			<&pio 3 5 GPIO_ACTIVE_HIGH>,
++			<&pio 3 6 GPIO_ACTIVE_HIGH>,
++			<&pio 3 7 GPIO_ACTIVE_HIGH>,
++			<&pio 3 10 GPIO_ACTIVE_HIGH>,
++			<&pio 3 11 GPIO_ACTIVE_HIGH>,
++			<&pio 3 12 GPIO_ACTIVE_HIGH>,
++			<&pio 3 13 GPIO_ACTIVE_HIGH>,
++			<&pio 3 15 GPIO_ACTIVE_HIGH>,
++			<&pio 3 20 GPIO_ACTIVE_HIGH>,
++			<&pio 3 21 GPIO_ACTIVE_HIGH>,
++			<&pio 3 22 GPIO_ACTIVE_HIGH>,
++			<&pio 3 23 GPIO_ACTIVE_HIGH>,
++			<&pio 3 24 GPIO_ACTIVE_HIGH>;
++
++		compatible = "custom,pocketbook-touch-lux-3-tcon0-ed060xd4-display";
++		reg = <0x01c0c000 0x1000>, // TCON0 regs
++			<0x01e60000 0x10000>; // DEBE regs
++
++		interrupts = <44>; // TCON interrupt
++
++		resets = <&ccu RST_LCD>, <&ccu RST_DE_BE>;
++		reset-names = "tcon", "be";
++
++		clocks = <&ccu CLK_AHB_LCD>, <&ccu CLK_TCON_CH0>,
++			 <&ccu CLK_AHB_DE_BE>, <&ccu CLK_DE_BE>,
++			 <&ccu CLK_DRAM_DE_BE>;
++		clock-names = "tcon_bus", "tcon_mod",
++			      "be_bus", "be_mod",
++			      "be_ram";
++
++		assigned-clocks = <&ccu CLK_DE_BE>;
++		assigned-clock-rates = <300000000>;
++
++		interconnects = <&mbus 18>;
++		interconnect-names = "dma-mem";
++
++		panel-supply = <&tp65185x>;
++		control-device-name = "eink-panel";
++	};
++};
++
+ &spi2 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&spi2_pe_pins>, <&spi2_cs0_pe_pin>;
+@@ -230,6 +328,7 @@ epd_flash: flash@0 {
+ 		compatible = "macronix,mx25u4033", "jedec,spi-nor";
+ 		reg = <0>;
+ 		spi-max-frequency = <4000000>;
++		vdd-supply = <&reg_1v8_nor>;
+ 	};
+ };
+ 
+@@ -253,6 +352,8 @@ &usb_power_supply {
+ };
+ 
+ &usbphy {
++	//XXX: might not work, need to test
++	usb0_vbus_det-gpios = <&pio 6 1 GPIO_ACTIVE_HIGH>; /* PG1 */
+ 	usb1_vbus-supply = <&reg_ldo3>;
+ 	status = "okay";
+ };
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun5i-Add-soc-handle.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun5i-Add-soc-handle.patch
new file mode 100644
index 000000000000..6476558677fb
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun5i-Add-soc-handle.patch
@@ -0,0 +1,26 @@
+From 87c27d42818037b43a49d67edc1d2de68036d1af Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 5 Oct 2019 15:04:43 +0200
+Subject: ARM: dts: sun5i: Add soc handle
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/boot/dts/allwinner/sun5i.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun5i.dtsi b/arch/arm/boot/dts/allwinner/sun5i.dtsi
+index e6836fd4b8dc..126b80f3ca70 100644
+--- a/arch/arm/boot/dts/allwinner/sun5i.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun5i.dtsi
+@@ -123,7 +123,7 @@ default-pool {
+ 		};
+ 	};
+ 
+-	soc {
++	soc: soc {
+ 		compatible = "simple-bus";
+ 		#address-cells = <1>;
+ 		#size-cells = <1>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun5i-a13-pocketbook-touch-lux-3-Add-RTC-clock-cells.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun5i-a13-pocketbook-touch-lux-3-Add-RTC-clock-cells.patch
new file mode 100644
index 000000000000..8dec8d9ff3ee
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun5i-a13-pocketbook-touch-lux-3-Add-RTC-clock-cells.patch
@@ -0,0 +1,27 @@
+From 7cd038980cc2a9a28a5d908f8c66a4a2c92ad36b Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Thu, 25 Jun 2020 01:57:27 +0200
+Subject: ARM: dts: sun5i-a13-pocketbook-touch-lux-3: Add RTC clock-cells
+
+This stop the driver from complaining in dmesg.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/boot/dts/allwinner/sun5i-a13-pocketbook-touch-lux-3.dts | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun5i-a13-pocketbook-touch-lux-3.dts b/arch/arm/boot/dts/allwinner/sun5i-a13-pocketbook-touch-lux-3.dts
+index db28ab621804..ee81db68e546 100644
+--- a/arch/arm/boot/dts/allwinner/sun5i-a13-pocketbook-touch-lux-3.dts
++++ b/arch/arm/boot/dts/allwinner/sun5i-a13-pocketbook-touch-lux-3.dts
+@@ -132,6 +132,7 @@ &i2c1 {
+ 	pcf8563: rtc@51 {
+ 		compatible = "nxp,pcf8563";
+ 		reg = <0x51>;
++		#clock-cells = <0>;
+ 	};
+ 
+ 	// hacky PMIC driver for eInk display
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-Add-MBUS-node.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-Add-MBUS-node.patch
new file mode 100644
index 000000000000..c1428e08bb55
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-Add-MBUS-node.patch
@@ -0,0 +1,39 @@
+From 671a2d6f20ba155cfcadf114e6d740936ee7088a Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 3 Apr 2021 20:53:26 -0500
+Subject: ARM: dts: sun8i: a83t: Add MBUS node
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi | 15 +++++++++++++++
+ 1 file changed, 15 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+index ef62ced26684..04b33b42b414 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+@@ -1056,6 +1056,21 @@ mdio: mdio {
+ 			};
+ 		};
+ 
++		mbus: dram-controller@1c62000 {
++			compatible = "allwinner,sun8i-a83t-mbus";
++			reg = <0x01c62000 0x1000>,
++			      <0x01c63000 0x1000>;
++			reg-names = "mbus", "dram";
++			clocks = <&ccu CLK_BUS_DRAM>,
++				 <&ccu CLK_DRAM>,
++				 <&ccu CLK_MBUS>;
++			clock-names = "apb", "dram", "mbus";
++			#address-cells = <1>;
++			#size-cells = <1>;
++			dma-ranges = <0x00000000 0x40000000 0xc0000000>;
++			#interconnect-cells = <1>;
++		};
++
+ 		gic: interrupt-controller@1c81000 {
+ 			compatible = "arm,gic-400";
+ 			reg = <0x01c81000 0x1000>,
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-Add-cedrus-video-codec-support-to-A83T-untes.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-Add-cedrus-video-codec-support-to-A83T-untes.patch
new file mode 100644
index 000000000000..6c111c2f122a
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-Add-cedrus-video-codec-support-to-A83T-untes.patch
@@ -0,0 +1,37 @@
+From 01a3291530c88353c36fb80d55ce984363614c28 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 9 Sep 2019 06:02:10 +0200
+Subject: ARM: dts: sun8i-a83t: Add cedrus video codec support to A83T
+ [untested]
+
+Not tested at all.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+index addf0cb0f465..ed3d8e692d84 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+@@ -441,6 +441,16 @@ syscon: syscon@1c00000 {
+ 			reg = <0x01c00000 0x1000>;
+ 		};
+ 
++		video-codec@01c0e000 {
++			compatible = "allwinner,sun8i-a83t-video-engine";
++			reg = <0x01c0e000 0x1000>;
++			clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
++				 <&ccu CLK_DRAM_VE>;
++			clock-names = "ahb", "mod", "ram";
++			resets = <&ccu RST_BUS_VE>;
++			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
++		};
++
+ 		dma: dma-controller@1c02000 {
+ 			compatible = "allwinner,sun8i-a83t-dma";
+ 			reg = <0x01c02000 0x1000>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-Add-hdmi-sound-card.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-Add-hdmi-sound-card.patch
new file mode 100644
index 000000000000..be6abc769398
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-Add-hdmi-sound-card.patch
@@ -0,0 +1,48 @@
+From bcee56858d98fe3523d52de0f6f1dd2750ee7c77 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sun, 9 May 2021 11:32:57 +0200
+Subject: ARM: dts: sun8i: a83t: Add hdmi sound card
+
+A83t support HDMI audio. Add a sound card node for it.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi | 15 +++++++++++++++
+ 1 file changed, 15 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+index 026c9b1b2217..cc86d3755036 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+@@ -150,6 +150,20 @@ cpu103: cpu@103 {
+ 		};
+ 	};
+ 
++	sound_hdmi: sound_hdmi {
++		compatible = "allwinner,sun9i-a80-hdmi-audio",
++			     "allwinner,sun8i-a83t-hdmi-audio";
++		status = "disabled";
++
++		codec {
++			sound-dai = <&hdmi>;
++		};
++
++		cpu {
++			sound-dai = <&i2s2>;
++		};
++	};
++
+ 	timer {
+ 		compatible = "arm,armv7-timer";
+ 		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+@@ -1059,6 +1073,7 @@ csi: camera@1cb0000 {
+ 		};
+ 
+ 		hdmi: hdmi@1ee0000 {
++			#sound-dai-cells = <0>;
+ 			compatible = "allwinner,sun8i-a83t-dw-hdmi";
+ 			reg = <0x01ee0000 0x10000>;
+ 			reg-io-width = <1>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-Add-missing-GPU-trip-point.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-Add-missing-GPU-trip-point.patch
new file mode 100644
index 000000000000..16e978379055
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-Add-missing-GPU-trip-point.patch
@@ -0,0 +1,35 @@
+From 79b5366ae1cedac8596a6188275c25db406c6f1f Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Mon, 13 Mar 2023 06:02:27 +0100
+Subject: ARM: dts: sun8i-a83t: Add missing GPU trip point
+
+Without this, thermal sensor driver fails to probe.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+index 27f8e42467af..2ab73558aaca 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+@@ -1307,6 +1307,15 @@ gpu_thermal: gpu-thermal {
+ 			polling-delay-passive = <0>;
+ 			polling-delay = <0>;
+ 			thermal-sensors = <&ths 2>;
++
++			trips {
++				gpu_crit: gpu-crit {
++					/* milliCelsius */
++					temperature = <100000>;
++					hysteresis = <2000>;
++					type = "critical";
++				};
++			};
+ 		};
+ 	};
+ };
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-Enable-hdmi-sound-card-on-boards-with-hdmi.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-Enable-hdmi-sound-card-on-boards-with-hdmi.patch
new file mode 100644
index 000000000000..8ae870f641bc
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-Enable-hdmi-sound-card-on-boards-with-hdmi.patch
@@ -0,0 +1,69 @@
+From e82fb342a69f47923f2e504b7e7e2fff952dac98 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sun, 9 May 2021 11:34:43 +0200
+Subject: ARM: dts: sun8i: a83t: Enable hdmi sound card on boards with hdmi
+
+Each board that has HDMI connector can also transmit audio through it.
+Enable HDMI sound card on all A83t boards with HDMI connector.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ arch/arm/boot/dts/allwinner/sun8i-a83t-bananapi-m3.dts    | 8 ++++++++
+ .../arm/boot/dts/allwinner/sun8i-a83t-cubietruck-plus.dts | 8 ++++++++
+ 2 files changed, 16 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t-bananapi-m3.dts b/arch/arm/boot/dts/allwinner/sun8i-a83t-bananapi-m3.dts
+index 32e811fa23e2..9a7117bca70d 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t-bananapi-m3.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t-bananapi-m3.dts
+@@ -162,6 +162,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &mdio {
+ 	rgmii_phy: ethernet-phy@1 {
+ 		compatible = "ethernet-phy-ieee802.3-c22";
+@@ -380,6 +384,10 @@ &reg_sw {
+ 	regulator-name = "vcc-ephy";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_pb_pins>;
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t-cubietruck-plus.dts b/arch/arm/boot/dts/allwinner/sun8i-a83t-cubietruck-plus.dts
+index d5e6ddaffbce..d4d834084b12 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t-cubietruck-plus.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t-cubietruck-plus.dts
+@@ -197,6 +197,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &mdio {
+ 	rgmii_phy: ethernet-phy@1 {
+ 		compatible = "ethernet-phy-ieee802.3-c22";
+@@ -417,6 +421,10 @@ &reg_sw {
+ 	regulator-name = "vcc-wifi-io";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &spdif {
+ 	status = "okay";
+ };
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-Improve-CPU-OPP-tables-go-up-to-1.8GHz.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-Improve-CPU-OPP-tables-go-up-to-1.8GHz.patch
new file mode 100644
index 000000000000..aa6c75dabd61
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-Improve-CPU-OPP-tables-go-up-to-1.8GHz.patch
@@ -0,0 +1,134 @@
+From 5968a3853998a21a9c2dd8aa2e4efc3a16e7ccfb Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 1 Sep 2019 23:56:49 +0200
+Subject: ARM: dts: sun8i-a83t: Improve CPU OPP tables (go up to 1.8GHz)
+
+This table is for the worst SoC bin, so it should work on all A83T
+bins.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi | 80 ++++++---------------
+ 1 file changed, 22 insertions(+), 58 deletions(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+index 04b33b42b414..026c9b1b2217 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+@@ -210,45 +210,27 @@ opp-480000000 {
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+-		opp-600000000 {
+-			opp-hz = /bits/ 64 <600000000>;
+-			opp-microvolt = <840000>;
+-			clock-latency-ns = <244144>; /* 8 32k periods */
+-		};
+-
+-		opp-720000000 {
+-			opp-hz = /bits/ 64 <720000000>;
+-			opp-microvolt = <840000>;
+-			clock-latency-ns = <244144>; /* 8 32k periods */
+-		};
+-
+-		opp-864000000 {
+-			opp-hz = /bits/ 64 <864000000>;
+-			opp-microvolt = <840000>;
+-			clock-latency-ns = <244144>; /* 8 32k periods */
+-		};
+-
+-		opp-912000000 {
+-			opp-hz = /bits/ 64 <912000000>;
++		opp-1008000000 {
++			opp-hz = /bits/ 64 <1008000000>;
+ 			opp-microvolt = <840000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+-		opp-1008000000 {
+-			opp-hz = /bits/ 64 <1008000000>;
+-			opp-microvolt = <840000>;
++		opp-1412000000 {
++			opp-hz = /bits/ 64 <1412000000>;
++			opp-microvolt = <920000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+-		opp-1128000000 {
+-			opp-hz = /bits/ 64 <1128000000>;
+-			opp-microvolt = <840000>;
++		opp-1608000000 {
++			opp-hz = /bits/ 64 <1608000000>;
++			opp-microvolt = <1000000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+-		opp-1200000000 {
+-			opp-hz = /bits/ 64 <1200000000>;
+-			opp-microvolt = <840000>;
++		opp-1800000000 {
++			opp-hz = /bits/ 64 <1800000000>;
++			opp-microvolt = <1080000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 	};
+@@ -263,45 +245,27 @@ opp-480000000 {
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+-		opp-600000000 {
+-			opp-hz = /bits/ 64 <600000000>;
+-			opp-microvolt = <840000>;
+-			clock-latency-ns = <244144>; /* 8 32k periods */
+-		};
+-
+-		opp-720000000 {
+-			opp-hz = /bits/ 64 <720000000>;
+-			opp-microvolt = <840000>;
+-			clock-latency-ns = <244144>; /* 8 32k periods */
+-		};
+-
+-		opp-864000000 {
+-			opp-hz = /bits/ 64 <864000000>;
+-			opp-microvolt = <840000>;
+-			clock-latency-ns = <244144>; /* 8 32k periods */
+-		};
+-
+-		opp-912000000 {
+-			opp-hz = /bits/ 64 <912000000>;
++		opp-1008000000 {
++			opp-hz = /bits/ 64 <1008000000>;
+ 			opp-microvolt = <840000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+-		opp-1008000000 {
+-			opp-hz = /bits/ 64 <1008000000>;
+-			opp-microvolt = <840000>;
++		opp-1412000000 {
++			opp-hz = /bits/ 64 <1412000000>;
++			opp-microvolt = <920000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+-		opp-1128000000 {
+-			opp-hz = /bits/ 64 <1128000000>;
+-			opp-microvolt = <840000>;
++		opp-1608000000 {
++			opp-hz = /bits/ 64 <1608000000>;
++			opp-microvolt = <1000000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+-		opp-1200000000 {
+-			opp-hz = /bits/ 64 <1200000000>;
+-			opp-microvolt = <840000>;
++		opp-1800000000 {
++			opp-hz = /bits/ 64 <1800000000>;
++			opp-microvolt = <1080000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 	};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-Set-fifo-size-for-uarts.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-Set-fifo-size-for-uarts.patch
new file mode 100644
index 000000000000..425121a33481
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-Set-fifo-size-for-uarts.patch
@@ -0,0 +1,59 @@
+From 1343ffd6e889e9f9ddfe35f87c6b9bd5006a9a49 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 1 Feb 2020 23:41:47 +0100
+Subject: ARM: dts: sun8i-a83t: Set fifo-size for uarts
+
+Boot time optimization.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+index cc86d3755036..0bbf43850c95 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+@@ -926,6 +926,7 @@ uart0: serial@1c28000 {
+ 			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ 			reg-shift = <2>;
+ 			reg-io-width = <4>;
++			fifo-size = <64>;
+ 			clocks = <&ccu CLK_BUS_UART0>;
+ 			resets = <&ccu RST_BUS_UART0>;
+ 			status = "disabled";
+@@ -937,6 +938,7 @@ uart1: serial@1c28400 {
+ 			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ 			reg-shift = <2>;
+ 			reg-io-width = <4>;
++			fifo-size = <64>;
+ 			clocks = <&ccu CLK_BUS_UART1>;
+ 			resets = <&ccu RST_BUS_UART1>;
+ 			status = "disabled";
+@@ -948,6 +950,7 @@ uart2: serial@1c28800 {
+ 			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ 			reg-shift = <2>;
+ 			reg-io-width = <4>;
++			fifo-size = <64>;
+ 			clocks = <&ccu CLK_BUS_UART2>;
+ 			resets = <&ccu RST_BUS_UART2>;
+ 			status = "disabled";
+@@ -959,6 +962,7 @@ uart3: serial@1c28c00 {
+ 			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ 			reg-shift = <2>;
+ 			reg-io-width = <4>;
++			fifo-size = <64>;
+ 			clocks = <&ccu CLK_BUS_UART3>;
+ 			resets = <&ccu RST_BUS_UART3>;
+ 			status = "disabled";
+@@ -970,6 +974,7 @@ uart4: serial@1c29000 {
+ 			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ 			reg-shift = <2>;
+ 			reg-io-width = <4>;
++			fifo-size = <64>;
+ 			clocks = <&ccu CLK_BUS_UART4>;
+ 			resets = <&ccu RST_BUS_UART4>;
+ 			status = "disabled";
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-PN544-NFC-support.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-PN544-NFC-support.patch
new file mode 100644
index 000000000000..81ad7ed87b17
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-PN544-NFC-support.patch
@@ -0,0 +1,66 @@
+From af628e240ad757d9fc0258f2d64165ade363cd86 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Fri, 10 Nov 2017 14:33:28 +0100
+Subject: ARM: dts: sun8i-a83t-tbs-a711: Add PN544 NFC support
+
+Regulators on the schematic are named incorrectly. Both cameras are
+is in fact connected to the dvdd-csi-f regulator and dvdd-csi-r is
+in reality used for digital pad supply for NFC chip.
+
+At the same time vcc-mipi regulator is not used for MIPI, but for NFC
+VBAT power.
+
+Interpreting schematics is an art form! :D
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../boot/dts/allwinner/sun8i-a83t-tbs-a711.dts | 18 +++++++++++++++---
+ 1 file changed, 15 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
+index 43982b106a4d..5cedbe2455db 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
+@@ -190,6 +190,16 @@ accelerometer@18 {
+ 		interrupt-parent = <&pio>;
+ 		interrupts = <7 10 IRQ_TYPE_EDGE_RISING>; /* PH10 / EINT10 */
+ 	};
++
++	/* NFC (NPC 100) */
++	npc100: nfc@28 {
++		compatible = "nxp,nxp-nci-i2c";
++		reg = <0x28>;
++		interrupt-parent = <&r_pio>;
++		interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; /* PL6 */
++		enable-gpios = <&pio 3 2 GPIO_ACTIVE_HIGH>; /* PD2 */
++		firmware-gpios = <&pio 3 3 GPIO_ACTIVE_HIGH>; /* PD3 */
++	};
+ };
+ 
+ &mmc0 {
+@@ -368,9 +378,10 @@ &reg_dldo1 {
+ };
+ 
+ &reg_dldo2 {
+-	regulator-min-microvolt = <2800000>;
++	regulator-min-microvolt = <3300000>;
+ 	regulator-max-microvolt = <4200000>;
+-	regulator-name = "vcc-mipi";
++	regulator-name = "vbat-nfc";
++	regulator-always-on;
+ };
+ 
+ &reg_dldo3 {
+@@ -393,7 +404,8 @@ &reg_drivevbus {
+ &reg_eldo1 {
+ 	regulator-min-microvolt = <1200000>;
+ 	regulator-max-microvolt = <1800000>;
+-	regulator-name = "dvdd-csi-r";
++	regulator-name = "pvdd-nfc";
++	regulator-always-on;
+ };
+ 
+ &reg_eldo2 {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-camera-sensors-HM5065-GC2145.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-camera-sensors-HM5065-GC2145.patch
new file mode 100644
index 000000000000..c0040054f011
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-camera-sensors-HM5065-GC2145.patch
@@ -0,0 +1,180 @@
+From 6b05b5d01cedf65ba4a82cd08ad552eb26817e9e Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 23 Jun 2020 19:43:24 +0200
+Subject: ARM: dts: sun8i-a83t-tbs-a711: Add camera sensors (HM5065, GC2145)
+
+The tablet has two cameras, that can be switched between. Add
+support for the both of them.
+
+Sensor is connected via parallel bus to CSI and via I2C bus to
+PE14/PE15 pins. Enable CSI module and add the node for HM5065
+camera sensor.
+
+Camera sensors are connected via I2C to PE14/PE15 pins on A83T.
+Unfortunately while the A83T datasheet suggests TWI2 I2C controller
+can be configured to have SDA/SCL on these pins, this configuration
+doesn't work in reality. We need to either use CCI I2C controller
+that is part of the CSI module, or as is done in this patch, use GPIO
+based bitbanging I2C driver.
+
+Reduce camera IOVDD voltage.
+
+Force dvdd-csi-r/f regulators to 1.8V.
+
+This is required by camera sensors that are connected to them.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../dts/allwinner/sun8i-a83t-tbs-a711.dts     | 101 +++++++++++++++++-
+ 1 file changed, 99 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
+index ce1a8d98b548..ba3ea3199c69 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
+@@ -70,6 +70,16 @@ backlight: backlight {
+ 		default-brightness-level = <9>;
+ 	};
+ 
++	i2c_gpio: i2c-gpio {
++		compatible = "i2c-gpio";
++		/* PE15 = sda, PE14 = scl */
++		sda-gpios = <&pio 4 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
++		scl-gpios = <&pio 4 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
++		i2c-gpio,delay-us = <1>; /* ~100 kHz */
++		#address-cells = <1>;
++		#size-cells = <0>;
++	};
++
+ 	panel {
+ 		compatible = "tbs,a711-panel", "panel-lvds";
+ 		backlight = <&backlight>;
+@@ -215,6 +225,13 @@ link2_codec: codec {
+ 	};
+ };
+ 
++&ccu {
++	/* Use a stable clock source with known fixed rate for MCLK */
++	assigned-clocks = <&ccu CLK_CSI_MCLK>;
++	assigned-clock-parents = <&osc24M>;
++	assigned-clock-rates = <24000000>;
++};
++
+ &cpu0 {
+ 	cpu-supply = <&reg_dcdc2>;
+ };
+@@ -223,6 +240,37 @@ &cpu100 {
+ 	cpu-supply = <&reg_dcdc3>;
+ };
+ 
++&csi {
++	pinctrl-names = "default";
++	pinctrl-0 = <&csi_8bit_parallel_pins>, <&csi_mclk_pin>;
++	status = "okay";
++
++	port {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		csi_hm5065_ep: endpoint@0 {
++			reg = <0>;
++			remote-endpoint = <&hm5065_ep>;
++			bus-width = <8>;
++			data-active = <1>;
++			pclk-sample = <0>;
++			hsync-active = <0>;
++			vsync-active = <1>;
++		};
++
++		csi_gc2145_ep: endpoint@1 {
++			reg = <1>;
++			remote-endpoint = <&gc2145_ep>;
++			bus-width = <8>;
++			hsync-active = <1>;
++			vsync-active = <1>;
++			data-active = <1>;
++			pclk-sample = <1>;
++		};
++	};
++};
++
+ &de {
+ 	status = "okay";
+ };
+@@ -283,6 +331,55 @@ npc100: nfc@28 {
+ 	};
+ };
+ 
++&i2c_gpio {
++	hm5065: rear-camera@1f {
++		compatible = "himax,hm5065";
++		reg = <0x1f>;
++		clocks = <&ccu CLK_CSI_MCLK>;
++		clock-names = "xclk";
++		IOVDD-supply = <&reg_dldo3>;
++		AVDD-supply = <&reg_dldo4>;
++		DVDD-supply = <&reg_eldo3>;
++		AFVDD-supply = <&reg_dldo3>;
++		reset-gpios = <&pio 4 18 GPIO_ACTIVE_LOW>; /* PE18 */
++		enable-gpios = <&pio 4 19 GPIO_ACTIVE_HIGH>; /* PE19 */
++
++		port {
++			hm5065_ep: endpoint {
++				remote-endpoint = <&csi_hm5065_ep>;
++				bus-width = <8>;
++				data-active = <1>;
++				pclk-sample = <0>;
++				hsync-active = <0>;
++				vsync-active = <1>;
++			};
++		};
++	};
++
++	gc2145: front-camera@3c {
++		compatible = "galaxycore,gc2145";
++		reg = <0x3c>;
++		clocks = <&ccu CLK_CSI_MCLK>;
++		clock-names = "xclk";
++		IOVDD-supply = <&reg_dldo3>;
++		AVDD-supply = <&reg_dldo4>;
++		DVDD-supply = <&reg_eldo3>;
++		reset-gpios = <&pio 4 16 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; /* PE16 */
++		enable-gpios = <&pio 4 17 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; /* PE17 */
++
++		port {
++			gc2145_ep: endpoint {
++				remote-endpoint = <&csi_gc2145_ep>;
++				bus-width = <8>;
++				hsync-active = <1>;
++				vsync-active = <1>;
++				data-active = <1>;
++				pclk-sample = <1>;
++			};
++		};
++	};
++};
++
+ &i2s0 {
+ 	status = "okay";
+ 	pinctrl-names = "default";
+@@ -500,7 +597,7 @@ &reg_drivevbus {
+ };
+ 
+ &reg_eldo1 {
+-	regulator-min-microvolt = <1200000>;
++	regulator-min-microvolt = <1800000>;
+ 	regulator-max-microvolt = <1800000>;
+ 	regulator-name = "pvdd-nfc";
+ 	regulator-always-on;
+@@ -513,7 +610,7 @@ &reg_eldo2 {
+ };
+ 
+ &reg_eldo3 {
+-	regulator-min-microvolt = <1200000>;
++	regulator-min-microvolt = <1800000>;
+ 	regulator-max-microvolt = <1800000>;
+ 	regulator-name = "dvdd-csi-f";
+ };
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-flash-led-support.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-flash-led-support.patch
new file mode 100644
index 000000000000..a620e0bed983
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-flash-led-support.patch
@@ -0,0 +1,32 @@
+From f5ba77da4d5a3374ade9ce2c9a98697724e2f418 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Wed, 8 Nov 2017 21:57:45 +0100
+Subject: ARM: dts: sun8i-a83t-tbs-a711: Add flash led support
+
+---
+ arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
+index ba3ea3199c69..23eb11e99b98 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
+@@ -61,6 +61,15 @@ chosen {
+ 		stdout-path = "serial0:115200n8";
+ 	};
+ 
++	leds {
++		compatible = "gpio-leds";
++
++		flash_led {
++			label = "flash";
++			gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>;
++		};
++	};
++
+ 	backlight: backlight {
+ 		compatible = "pwm-backlight";
+ 		pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-powerup-down-support-for-the-3G.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-powerup-down-support-for-the-3G.patch
new file mode 100644
index 000000000000..79bd2f03690e
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-powerup-down-support-for-the-3G.patch
@@ -0,0 +1,61 @@
+From 0da088ce86e596f4d2bdff7c255cc579579be341 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Myl=C3=A8ne=20Josserand?=
+ <mylene.josserand@free-electrons.com>
+Date: Thu, 6 Jul 2017 10:57:55 +0200
+Subject: ARM: dts: sun8i-a83t-tbs-a711: Add powerup/down support for the 3G
+ modem
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The modem needs tree gpios to be powered-up:
+	- PL10 = reset
+	- PL8 = On/Off
+	- PL9 = vbat
+Because of that, the PL9 corresponds to the regulator's gpio whereas
+the PL8 (on/off) will be a power-gpio of the power sequence.
+
+Thanks to that, the modem is powered up:
+       # lsusb
+	Bus 001 Device 004: ID 19d2:ffeb
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+Signed-off-by: Mylène Josserand <mylene.josserand@free-electrons.com>
+---
+ arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts | 13 ++++++++++++-
+ 1 file changed, 12 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
+index 5cedbe2455db..f7d8e5425233 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
+@@ -118,7 +118,7 @@ reg_vmain: reg-vmain {
+ 		regulator-name = "vmain";
+ 		regulator-min-microvolt = <5000000>;
+ 		regulator-max-microvolt = <5000000>;
+-		gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>;
++		gpio = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */
+ 		enable-active-high;
+ 		vin-supply = <&reg_vbat>;
+ 	};
+@@ -134,6 +134,17 @@ wifi_pwrseq: pwrseq {
+ 		clocks = <&ac100_rtc 1>;
+ 		clock-names = "ext_clock";
+ 	};
++
++	modem {
++		compatible = "zte,mg3732";
++		char-device-name = "modem-power";
++
++		power-supply = <&reg_vmain>;
++
++		enable-gpios = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
++		reset-gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */
++		wakeup-gpios = <&r_pio 0 11 GPIO_ACTIVE_HIGH>; /* PL11 */
++	};
+ };
+ 
+ &cpu0 {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-regulators-to-the-accelerometer.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-regulators-to-the-accelerometer.patch
new file mode 100644
index 000000000000..7590fd546009
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-regulators-to-the-accelerometer.patch
@@ -0,0 +1,30 @@
+From 3388c7e4f1d60f11b0377cfe30d0bfaaa20183ba Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 23 Jun 2020 19:15:37 +0200
+Subject: ARM: dts: sun8i-a83t-tbs-a711: Add regulators to the accelerometer
+
+The bosch,bma250 driver will fail to probe if the regulators are
+not specified in DT, because it tries to set voltage on dummy
+regulators, which fails with EINVAL.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
+index 925891a1d6d9..ce1a8d98b548 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
+@@ -268,6 +268,8 @@ accelerometer@18 {
+ 		reg = <0x18>;
+ 		interrupt-parent = <&pio>;
+ 		interrupts = <7 10 IRQ_TYPE_EDGE_RISING>; /* PH10 / EINT10 */
++		vdd-supply = <&reg_dcdc1>;
++		vddio-supply = <&reg_dcdc1>;
+ 	};
+ 
+ 	/* NFC (NPC 100) */
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-sound-support-via-AC100-codec.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-sound-support-via-AC100-codec.patch
new file mode 100644
index 000000000000..4f8b75f79fcb
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-sound-support-via-AC100-codec.patch
@@ -0,0 +1,131 @@
+From 06bc6b6ae01fd5e2e9cdc570581b5795cc7cd019 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 22 Feb 2020 23:40:29 +0100
+Subject: ARM: dts: sun8i-a83t-tbs-a711: Add sound support via AC100 codec
+
+...
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../dts/allwinner/sun8i-a83t-tbs-a711.dts     | 85 +++++++++++++++++++
+ 1 file changed, 85 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
+index f7d8e5425233..925891a1d6d9 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
+@@ -145,6 +145,74 @@ modem {
+ 		reset-gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */
+ 		wakeup-gpios = <&r_pio 0 11 GPIO_ACTIVE_HIGH>; /* PL11 */
+ 	};
++
++	bt_sco_codec: bt-sco-codec {
++		#sound-dai-cells = <1>;
++		compatible = "linux,bt-sco";
++		sound-name-prefix = "Bluetooth";
++	};
++
++	speaker_amp: audio-amplifier {
++		compatible = "simple-audio-amplifier";
++		enable-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */
++		sound-name-prefix = "Speaker Amp";
++	};
++
++	sound: sound {
++		#address-cells = <1>;
++		#size-cells = <0>;
++		compatible = "simple-audio-card";
++		simple-audio-card,name = "ac100-audio";
++		simple-audio-card,aux-devs = <&ac100_codec_analog>, <&speaker_amp>;
++		simple-audio-card,widgets = "Microphone", "Headset Microphone",
++					    "Microphone", "Internal Microphone",
++					    "Headphone", "Headphone Jack",
++					    "Speaker", "Internal Speaker";
++		simple-audio-card,routing =
++				"Headphone Jack", "HP",
++				"Internal Speaker", "Speaker Amp OUTL",
++				"Speaker Amp INL", "SPKOUTL",
++				"Left DAC", "DACL",
++				"Right DAC", "DACR",
++				"ADCL", "Left ADC",
++				"ADCR", "Right ADC",
++				"Internal Microphone", "MBIAS",
++				"MIC1", "Internal Microphone",
++				"Headset Microphone", "HBIAS",
++				"MIC2", "Headset Microphone";
++
++		simple-audio-card,dai-link@0 {
++			format = "i2s";
++			frame-master = <&link0_cpu>;
++			bitclock-master = <&link0_cpu>;
++			mclk-fs = <512>;
++
++			link0_cpu: cpu {
++				sound-dai = <&i2s0>;
++			};
++
++			link0_codec: codec {
++				sound-dai = <&ac100_codec 0>;
++			};
++		};
++
++		simple-audio-card,dai-link@2 {
++			format = "dsp_a";
++			frame-master = <&link2_codec>;
++			bitclock-master = <&link2_codec>;
++			bitclock-inversion;
++
++			link2_cpu: cpu {
++				sound-dai = <&bt_sco_codec 0>;
++			};
++
++			link2_codec: codec {
++				sound-dai = <&ac100_codec 2>;
++				dai-tdm-slot-num = <2>;
++				dai-tdm-slot-width = <16>;
++			};
++		};
++	};
+ };
+ 
+ &cpu0 {
+@@ -213,6 +281,12 @@ npc100: nfc@28 {
+ 	};
+ };
+ 
++&i2s0 {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2s0_pins>;
++};
++
+ &mmc0 {
+ 	vmmc-supply = <&reg_dcdc1>;
+ 	pinctrl-names = "default";
+@@ -293,12 +367,23 @@ ac100: codec@e89 {
+ 		compatible = "x-powers,ac100";
+ 		reg = <0xe89>;
+ 
++		ac100_codec_analog: codec-analog {
++			compatible = "x-powers,ac100-codec-analog";
++			cpvdd-supply = <&reg_aldo2>;
++		};
++
+ 		ac100_codec: codec {
++			#sound-dai-cells = <1>;
+ 			compatible = "x-powers,ac100-codec";
+ 			interrupt-parent = <&r_pio>;
+ 			interrupts = <0 12 IRQ_TYPE_LEVEL_LOW>; /* PL12 */
+ 			#clock-cells = <0>;
+ 			clock-output-names = "4M_adda";
++
++			LDOIN-supply = <&reg_aldo2>;
++			AVCC-supply = <&reg_aldo3>;
++			VDDIO1-supply = <&reg_dcdc1>;
++			VDDIO2-supply = <&reg_dldo1>;
+ 		};
+ 
+ 		ac100_rtc: rtc {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-support-for-the-vibrator-motor.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-support-for-the-vibrator-motor.patch
new file mode 100644
index 000000000000..2edc3c829fba
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-support-for-the-vibrator-motor.patch
@@ -0,0 +1,39 @@
+From 9b8f0e47429380b0d58597e2581abfe86d04f1e7 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 9 Nov 2019 23:55:48 +0100
+Subject: ARM: dts: sun8i-a83t-tbs-a711: Add support for the vibrator motor
+
+The board has a vibrator mottor. Hook it to the input subsystem.
+
+According to the PMIC specification, LDO needs to be enabled (value 0b11)
+to achieve the specified max driving current of 150mA. We can't drive
+the motor with just GPIO mode.
+
+In GPIO mode the chip is probably just using the regular CMOS logic
+output circuitry (typically limited to around 20-35mA, but not specified
+in this datasheet).
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
+index 23eb11e99b98..81e1271482ed 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
+@@ -118,6 +118,11 @@ panel_input: endpoint {
+ 		};
+ 	};
+ 
++	vibrator {
++		compatible = "gpio-vibrator";
++		vcc-supply = <&reg_ldo_io1>;
++	};
++
+ 	reg_gps: reg-gps {
+ 		compatible = "regulator-fixed";
+ 		regulator-name = "gps";
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Enable-charging-LED.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Enable-charging-LED.patch
new file mode 100644
index 000000000000..b74a76cd67f4
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Enable-charging-LED.patch
@@ -0,0 +1,31 @@
+From c099653062731dfb0f13e60373a890b7ba88c149 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 23 Feb 2020 13:21:58 +0100
+Subject: ARM: dts: sun8i-a83t-tbs-a711: Enable charging LED
+
+The tablet has a LED connected to the PMIC. The LED is visible in the
+top right corner of the tablet. Enable it.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
+index 6a90763d8736..6edeaf8ed431 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
+@@ -519,6 +519,10 @@ &battery_power_supply {
+ 	status = "okay";
+ };
+ 
++&charger_led {
++	status = "okay";
++};
++
+ &reg_aldo1 {
+ 	regulator-min-microvolt = <1800000>;
+ 	regulator-max-microvolt = <1800000>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Give-Linux-more-privileges-over-SCP.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Give-Linux-more-privileges-over-SCP.patch
new file mode 100644
index 000000000000..1b9c82691405
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Give-Linux-more-privileges-over-SCP.patch
@@ -0,0 +1,47 @@
+From fd7b0ea1f64ea844570ebcb802cb2a4934414fba Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 23 Jun 2020 19:19:46 +0200
+Subject: ARM: dts: sun8i-a83t-tbs-a711: Give Linux more privileges over SCPI
+
+This is needed since on A83T there's no PSCI/ATF implementation.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi | 7 +++++--
+ 1 file changed, 5 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+index 1ef9b4a581ac..27f8e42467af 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+@@ -286,7 +286,7 @@ opp-1800000000 {
+ 
+ 	scpi_protocol: scpi {
+ 		compatible = "arm,scpi";
+-		mboxes = <&msgbox 2>, <&msgbox 3>;
++		mboxes = <&msgbox 0>, <&msgbox 1>;
+ 		mbox-names = "tx", "rx";
+ 		shmem = <&scpi_sram>;
+ 	};
+@@ -424,6 +424,9 @@ syscon: syscon@1c00000 {
+ 			compatible = "allwinner,sun8i-a83t-system-controller",
+ 				"syscon";
+ 			reg = <0x01c00000 0x1000>;
++                        #address-cells = <1>;
++                        #size-cells = <1>;
++                        ranges;
+ 
+ 			sram_a2: sram@40000 {
+ 				compatible = "mmio-sram";
+@@ -434,7 +437,7 @@ sram_a2: sram@40000 {
+ 
+ 				scpi_sram: scp-shmem@13c00 {
+ 					compatible = "arm,scp-shmem";
+-					reg = <0x13c00 0x200>;
++					reg = <0x13e00 0x200>;
+ 				};
+ 			};
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Increase-voltage-on-the-vibrator.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Increase-voltage-on-the-vibrator.patch
new file mode 100644
index 000000000000..1be57b5d0c39
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Increase-voltage-on-the-vibrator.patch
@@ -0,0 +1,30 @@
+From 7bf0e248c3dbd81edf1482bfebe5e99e0c8d30e2 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Fri, 8 Dec 2017 12:44:22 +0100
+Subject: ARM: dts: sun8i-a83t-tbs-a711: Increase voltage on the vibrator
+
+Vibrator motor is weak at the current voltage. Increase the voltage.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
+index 81e1271482ed..6a90763d8736 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t-tbs-a711.dts
+@@ -650,8 +650,8 @@ &reg_ldo_io0 {
+ };
+ 
+ &reg_ldo_io1 {
+-	regulator-min-microvolt = <3100000>;
+-	regulator-max-microvolt = <3100000>;
++	regulator-min-microvolt = <3300000>;
++	regulator-max-microvolt = <3300000>;
+ 	regulator-name = "vcc-vb";
+ 	status = "okay";
+ };
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-h2-plus-bananapi-m2-zero-Enable-HDMI-audio.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-h2-plus-bananapi-m2-zero-Enable-HDMI-audio.patch
new file mode 100644
index 000000000000..e95ddef3f19d
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-h2-plus-bananapi-m2-zero-Enable-HDMI-audio.patch
@@ -0,0 +1,42 @@
+From 4a04f862d0a85d8aac6e3bbd698c1a40bad66059 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sun, 9 May 2021 11:14:51 +0200
+Subject: ARM: dts: sun8i: h2-plus: bananapi-m2-zero: Enable HDMI audio
+
+BananaPi M2 Zero has HDMI output and thus supports HDMI audio. Enable
+it.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ .../boot/dts/allwinner/sun8i-h2-plus-bananapi-m2-zero.dts | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h2-plus-bananapi-m2-zero.dts b/arch/arm/boot/dts/allwinner/sun8i-h2-plus-bananapi-m2-zero.dts
+index d3a7c9fa23e4..f40c2d0483b5 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h2-plus-bananapi-m2-zero.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h2-plus-bananapi-m2-zero.dts
+@@ -133,6 +133,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &mmc0 {
+ 	vmmc-supply = <&reg_vcc3v3>;
+ 	bus-width = <4>;
+@@ -256,6 +260,10 @@ &r_pio {
+ 		"", "", "", "", "", "", "", "";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &usb_otg {
+ 	dr_mode = "otg";
+ 	status = "okay";
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-h3-Enable-hdmi-sound-card-on-boards-with-hdmi.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-h3-Enable-hdmi-sound-card-on-boards-with-hdmi.patch
new file mode 100644
index 000000000000..7f5c11d8ec31
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-h3-Enable-hdmi-sound-card-on-boards-with-hdmi.patch
@@ -0,0 +1,272 @@
+From e01f6a6ca5c4883ee5afbfa1eeaf9aa6c53e058b Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sun, 9 May 2021 11:06:37 +0200
+Subject: ARM: dts: sun8i: h3: Enable hdmi sound card on boards with hdmi
+
+Each board that has HDMI connector can also transmit audio through it.
+Enable HDMI sound card on all H3 boards with HDMI connector.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ arch/arm/boot/dts/allwinner/sun8i-h3-beelink-x2.dts       | 8 ++++++++
+ .../dts/allwinner/sun8i-h3-emlid-neutis-n5h3-devboard.dts | 8 ++++++++
+ arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-m1-plus.dts   | 8 ++++++++
+ arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-m1.dts        | 8 ++++++++
+ arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-2.dts       | 8 ++++++++
+ arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-lite.dts    | 8 ++++++++
+ arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts     | 8 ++++++++
+ arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc.dts      | 8 ++++++++
+ .../boot/dts/allwinner/sun8i-h3-orangepi-zero-plus2.dts   | 8 ++++++++
+ arch/arm/boot/dts/allwinner/sun8i-h3-rervision-dvk.dts    | 8 ++++++++
+ 10 files changed, 80 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-beelink-x2.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-beelink-x2.dts
+index 5b77300307de..2fa04f508216 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-beelink-x2.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-beelink-x2.dts
+@@ -159,6 +159,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &ir {
+ 	linux,rc-map-name = "rc-tanix-tx3mini";
+ 	pinctrl-names = "default";
+@@ -213,6 +217,10 @@ &reg_usb0_vbus {
+ 	status = "okay";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &spdif {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&spdif_tx_pin>;
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-emlid-neutis-n5h3-devboard.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-emlid-neutis-n5h3-devboard.dts
+index 02fbe00cde97..61d6529dcc70 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-emlid-neutis-n5h3-devboard.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-emlid-neutis-n5h3-devboard.dts
+@@ -70,3 +70,11 @@ hdmi_out_con: endpoint {
+ &i2c1 {
+ 	status = "okay";
+ };
++
++&i2s2 {
++	status = "okay";
++};
++
++&sound_hdmi {
++	status = "okay";
++};
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-m1-plus.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-m1-plus.dts
+index 59bd0746acf8..10ae138b14f0 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-m1-plus.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-m1-plus.dts
+@@ -118,6 +118,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &ir {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&r_ir_rx_pin>;
+@@ -159,6 +163,10 @@ &ohci2 {
+ 	status = "okay";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &uart3 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart3_pins>, <&uart3_rts_cts_pins>;
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-m1.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-m1.dts
+index 69243dcb30a6..9393779f33b6 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-m1.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-m1.dts
+@@ -91,6 +91,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &ir {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&r_ir_rx_pin>;
+@@ -104,3 +108,7 @@ &ohci1 {
+ &ohci2 {
+ 	status = "okay";
+ };
++
++&sound_hdmi {
++	status = "okay";
++};
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-2.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-2.dts
+index d2ae47b074bf..7fac0c8906e8 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-2.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-2.dts
+@@ -145,6 +145,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &ir {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&r_ir_rx_pin>;
+@@ -179,6 +183,10 @@ &reg_usb1_vbus {
+ 	status = "okay";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_pa_pins>;
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-lite.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-lite.dts
+index 6a4316a52469..28ec2a5b1a5c 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-lite.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-lite.dts
+@@ -120,6 +120,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &ir {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&r_ir_rx_pin>;
+@@ -156,6 +160,10 @@ &ohci2 {
+ 	status = "okay";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_pa_pins>;
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts
+index 59f6f6d5e7ca..927fd1bab07d 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts
+@@ -146,6 +146,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &mmc0 {
+ 	vmmc-supply = <&reg_vcc3v3>;
+ 	bus-width = <4>;
+@@ -166,6 +170,10 @@ &reg_usb0_vbus {
+ 	status = "okay";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_pa_pins>;
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc.dts
+index 92a58e362004..624e248e3ffc 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc.dts
+@@ -147,6 +147,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &ir {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&r_ir_rx_pin>;
+@@ -206,6 +210,10 @@ &reg_usb0_vbus {
+ 	status = "okay";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_pa_pins>;
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-zero-plus2.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-zero-plus2.dts
+index 7a6444a10e25..4073d34af23c 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-zero-plus2.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-zero-plus2.dts
+@@ -117,6 +117,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &mmc0 {
+ 	vmmc-supply = <&reg_vcc3v3>;
+ 	bus-width = <4>;
+@@ -155,6 +159,10 @@ &ohci0 {
+ 	status = "okay";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_pa_pins>;
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-rervision-dvk.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-rervision-dvk.dts
+index 4738f3a9efe4..ee645912ee39 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-rervision-dvk.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-rervision-dvk.dts
+@@ -69,6 +69,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &mmc0 {
+ 	bus-width = <4>;
+ 	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+@@ -98,6 +102,10 @@ &ohci3 {
+ 	status = "okay";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_pa_pins>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-h3-Use-my-own-more-aggressive-OPPs-on-H3.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-h3-Use-my-own-more-aggressive-OPPs-on-H3.patch
new file mode 100644
index 000000000000..99f0ac907bd8
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-h3-Use-my-own-more-aggressive-OPPs-on-H3.patch
@@ -0,0 +1,72 @@
+From 3b5ba528f3dee489d2a4d789c2e1dc83af43273e Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 17 Aug 2020 23:43:53 +0200
+Subject: ARM: dts: sun8i-h3: Use my own more aggressive OPPs on H3
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/boot/dts/allwinner/sun8i-h3.dtsi | 36 +++++++++++++++++++++++
+ 1 file changed, 36 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi b/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi
+index eac2349a2380..da1991c991cb 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi
+@@ -48,6 +48,12 @@ cpu0_opp_table: opp-table-cpu {
+ 		compatible = "operating-points-v2";
+ 		opp-shared;
+ 
++		opp-480000000 {
++			opp-hz = /bits/ 64 <480000000>;
++			opp-microvolt = <1040000 1040000 1300000>;
++			clock-latency-ns = <244144>; /* 8 32k periods */
++		};
++
+ 		opp-648000000 {
+ 			opp-hz = /bits/ 64 <648000000>;
+ 			opp-microvolt = <1040000 1040000 1300000>;
+@@ -60,11 +66,41 @@ opp-816000000 {
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
++		opp-960000000 {
++			opp-hz = /bits/ 64 <960000000>;
++			opp-microvolt = <1200000 1200000 1300000>;
++			clock-latency-ns = <244144>; /* 8 32k periods */
++		};
++
+ 		opp-1008000000 {
+ 			opp-hz = /bits/ 64 <1008000000>;
+ 			opp-microvolt = <1200000 1200000 1300000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
++
++		opp-1104000000 {
++			opp-hz = /bits/ 64 <1104000000>;
++			opp-microvolt = <1320000 1320000 1320000>;
++			clock-latency-ns = <244144>; /* 8 32k periods */
++		};
++
++		opp-1200000000 {
++			opp-hz = /bits/ 64 <1200000000>;
++			opp-microvolt = <1320000 1320000 1320000>;
++			clock-latency-ns = <244144>; /* 8 32k periods */
++		};
++
++		opp-1296000000 {
++			opp-hz = /bits/ 64 <1296000000>;
++			opp-microvolt = <1340000 1340000 1340000>;
++			clock-latency-ns = <244144>; /* 8 32k periods */
++		};
++
++		opp-1368000000 {
++			opp-hz = /bits/ 64 <1368000000>;
++			opp-microvolt = <1400000 1400000 1400000>;
++			clock-latency-ns = <244144>; /* 8 32k periods */
++		};
+ 	};
+ 
+ 	cpus {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-h3-orange-pi-one-Enable-all-gpio-header-UARTs.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-h3-orange-pi-one-Enable-all-gpio-header-UARTs.patch
new file mode 100644
index 000000000000..3aec34335507
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-h3-orange-pi-one-Enable-all-gpio-header-UARTs.patch
@@ -0,0 +1,49 @@
+From 230f694a6df3aad6214f652209d03b381999b4ac Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sat, 2 Apr 2022 02:24:26 +0200
+Subject: ARM: dts: sun8i-h3-orange-pi-one: Enable all gpio header UARTs
+
+---
+ arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts | 9 ++++++---
+ 1 file changed, 6 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts
+index f5476cdab8a4..64c489e356ce 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts
+@@ -54,6 +54,9 @@ / {
+ 	aliases {
+ 		ethernet0 = &emac;
+ 		serial0 = &uart0;
++		serial1 = &uart1;
++		serial2 = &uart2;
++		serial3 = &uart3;
+ 	};
+ 
+ 	chosen {
+@@ -183,19 +186,19 @@ &uart0 {
+ &uart1 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart1_pins>;
+-	status = "disabled";
++	status = "okay";
+ };
+ 
+ &uart2 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart2_pins>;
+-	status = "disabled";
++	status = "okay";
+ };
+ 
+ &uart3 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart3_pins>;
+-	status = "disabled";
++	status = "okay";
+ };
+ 
+ &usb_otg {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-h3-orange-pi-pc-Increase-max-CPUX-voltage-to-1.4V.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-h3-orange-pi-pc-Increase-max-CPUX-voltage-to-1.4V.patch
new file mode 100644
index 000000000000..0b8effec54c5
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-h3-orange-pi-pc-Increase-max-CPUX-voltage-to-1.4V.patch
@@ -0,0 +1,31 @@
+From 6f11d654b5650b8563abeab166342c07899d4f39 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 13 May 2018 21:00:43 +0200
+Subject: ARM: dts: sun8i-h3-orange-pi-pc: Increase max CPUX voltage to 1.4V
+
+When using thermal regulation we can afford to go higher. Also add
+regulator-ramp-delay, because regulator takes some time to change
+voltage.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc.dts | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc.dts
+index b96e015f54ee..92a58e362004 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc.dts
+@@ -194,7 +194,8 @@ reg_vdd_cpux: regulator@65 {
+ 		 * Use 1.0V as the minimum voltage instead.
+ 		 */
+ 		regulator-min-microvolt = <1000000>;
+-		regulator-max-microvolt = <1300000>;
++		regulator-max-microvolt = <1400000>;
++		regulator-ramp-delay = <200>;
+ 		regulator-boot-on;
+ 		regulator-always-on;
+ 	};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-r40-Add-hdmi-sound-card.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-r40-Add-hdmi-sound-card.patch
new file mode 100644
index 000000000000..c86ced5d8862
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-r40-Add-hdmi-sound-card.patch
@@ -0,0 +1,48 @@
+From 453f3a74fadd774b213e9e99d7512f382f5ce2ca Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sun, 9 May 2021 11:50:56 +0200
+Subject: ARM: dts: sun8i: r40: Add hdmi sound card
+
+R40 support HDMI audio. Add a sound card node for it.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ arch/arm/boot/dts/allwinner/sun8i-r40.dtsi | 15 +++++++++++++++
+ 1 file changed, 15 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-r40.dtsi b/arch/arm/boot/dts/allwinner/sun8i-r40.dtsi
+index a5b1f1e3900d..d73828d6b3c0 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-r40.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-r40.dtsi
+@@ -124,6 +124,20 @@ de: display-engine {
+ 		status = "disabled";
+ 	};
+ 
++	sound_hdmi: sound_hdmi {
++		compatible = "allwinner,sun9i-a80-hdmi-audio",
++			     "allwinner,sun8i-r40-hdmi-audio";
++		status = "disabled";
++
++		codec {
++			sound-dai = <&hdmi>;
++		};
++
++		cpu {
++			sound-dai = <&i2s2>;
++		};
++	};
++
+ 	thermal-zones {
+ 		cpu_thermal: cpu0-thermal {
+ 			/* milliseconds */
+@@ -1265,6 +1279,7 @@ gic: interrupt-controller@1c81000 {
+ 		};
+ 
+ 		hdmi: hdmi@1ee0000 {
++			#sound-dai-cells = <0>;
+ 			compatible = "allwinner,sun8i-r40-dw-hdmi",
+ 				     "allwinner,sun8i-a83t-dw-hdmi";
+ 			reg = <0x01ee0000 0x10000>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-r40-bananapi-m2-ultra-Enable-HDMI-audio.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-r40-bananapi-m2-ultra-Enable-HDMI-audio.patch
new file mode 100644
index 000000000000..c041094b176f
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-r40-bananapi-m2-ultra-Enable-HDMI-audio.patch
@@ -0,0 +1,42 @@
+From 9f7f66239ad389f9b77720ef467ba7d2225868b3 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sun, 9 May 2021 11:52:43 +0200
+Subject: ARM: dts: sun8i: r40: bananapi-m2-ultra: Enable HDMI audio
+
+BananaPi M2 Ultra has HDMI output and thus supports HDMI audio. Enable
+it.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ .../boot/dts/allwinner/sun8i-r40-bananapi-m2-ultra.dts    | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/allwinner/sun8i-r40-bananapi-m2-ultra.dts
+index cd2351acc32f..a91213e8d2c1 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-r40-bananapi-m2-ultra.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-r40-bananapi-m2-ultra.dts
+@@ -169,6 +169,10 @@ axp22x: pmic@34 {
+ 
+ #include "axp22x.dtsi"
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &ir0 {
+ 	status = "okay";
+ };
+@@ -304,6 +308,10 @@ &reg_eldo3 {
+ 	regulator-name = "vdd1v2-sata";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &tcon_tv0 {
+ 	status = "okay";
+ };
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-v40-bananapi-m2-berry-Enable-HDMI-audio.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-v40-bananapi-m2-berry-Enable-HDMI-audio.patch
new file mode 100644
index 000000000000..e7057521bb0f
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sun8i-v40-bananapi-m2-berry-Enable-HDMI-audio.patch
@@ -0,0 +1,42 @@
+From c60e834e1aae8950464e736acaa2177b3497b307 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sun, 9 May 2021 12:00:46 +0200
+Subject: ARM: dts: sun8i: v40: bananapi-m2-berry: Enable HDMI audio
+
+BananaPi M2 Berry has HDMI output and thus supports HDMI audio. Enable
+it.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ .../boot/dts/allwinner/sun8i-v40-bananapi-m2-berry.dts    | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-v40-bananapi-m2-berry.dts b/arch/arm/boot/dts/allwinner/sun8i-v40-bananapi-m2-berry.dts
+index 6575ef274453..0e1395a3d052 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-v40-bananapi-m2-berry.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-v40-bananapi-m2-berry.dts
+@@ -160,6 +160,10 @@ axp22x: pmic@34 {
+ 
+ #include "axp22x.dtsi"
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &mmc0 {
+ 	vmmc-supply = <&reg_dcdc1>;
+ 	bus-width = <4>;
+@@ -275,6 +279,10 @@ &reg_eldo3 {
+ 	regulator-name = "vdd1v2-sata";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &tcon_tv0 {
+ 	status = "okay";
+ };
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-suni-a83t-Add-i2s0-pins.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-suni-a83t-Add-i2s0-pins.patch
new file mode 100644
index 000000000000..c7b510846e4a
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-suni-a83t-Add-i2s0-pins.patch
@@ -0,0 +1,29 @@
+From 95bfb93adb3ec8a52d09dc47bb16f5b0c6d74382 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 12 Nov 2017 19:03:39 +0100
+Subject: ARM: dts: suni-a83t: Add i2s0 pins
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+index ed3d8e692d84..ef62ced26684 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+@@ -829,6 +829,11 @@ spdif_tx_pin: spdif-tx-pin {
+ 				function = "spdif";
+ 			};
+ 
++			i2s0_pins: i2s0-pins {
++				pins = "PB4", "PB5", "PB6", "PB7", "PB8";
++				function = "i2s0";
++			};
++
+ 			uart0_pb_pins: uart0-pb-pins {
+ 				pins = "PB9", "PB10";
+ 				function = "uart0";
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sunxi-Add-aliases-for-MMC.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sunxi-Add-aliases-for-MMC.patch
new file mode 100644
index 000000000000..a3c58ae695d1
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sunxi-Add-aliases-for-MMC.patch
@@ -0,0 +1,66 @@
+From 499d97a0f3f21070604d41562e7c376ccfb9c192 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 25 Jan 2021 01:15:58 +0100
+Subject: ARM: dts: sunxi: Add aliases for MMC
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/boot/dts/allwinner/sun5i.dtsi      | 6 ++++++
+ arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi | 6 ++++++
+ arch/arm/boot/dts/allwinner/sun8i-h3.dtsi   | 6 ++++++
+ 3 files changed, 18 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun5i.dtsi b/arch/arm/boot/dts/allwinner/sun5i.dtsi
+index 126b80f3ca70..a15effbbbc51 100644
+--- a/arch/arm/boot/dts/allwinner/sun5i.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun5i.dtsi
+@@ -51,6 +51,12 @@ / {
+ 	#address-cells = <1>;
+ 	#size-cells = <1>;
+ 
++	aliases {
++		mmc0 = &mmc0;
++		mmc1 = &mmc1;
++		mmc2 = &mmc2;
++	};
++
+ 	cpus {
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+index 2ab73558aaca..a1aaa99ac3c4 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+@@ -57,6 +57,12 @@ / {
+ 	#address-cells = <1>;
+ 	#size-cells = <1>;
+ 
++	aliases {
++		mmc0 = &mmc0;
++		mmc1 = &mmc1;
++		mmc2 = &mmc2;
++	};
++
+ 	cpus {
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi b/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi
+index e601317d5de2..30d72d3b670e 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi
+@@ -44,6 +44,12 @@
+ #include <dt-bindings/thermal/thermal.h>
+ 
+ / {
++	aliases {
++		mmc0 = &mmc0;
++		mmc1 = &mmc1;
++		mmc2 = &mmc2;
++	};
++
+ 	cpu0_opp_table: opp-table-cpu {
+ 		compatible = "operating-points-v2";
+ 		opp-shared;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sunxi-a83t-Add-SCPI-protocol.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sunxi-a83t-Add-SCPI-protocol.patch
new file mode 100644
index 000000000000..16e15997e159
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sunxi-a83t-Add-SCPI-protocol.patch
@@ -0,0 +1,52 @@
+From 2f243bf529a9e369b05118e64cd1553a0112f9d0 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Wed, 1 Jan 2020 16:14:29 -0600
+Subject: ARM: dts: sunxi: a83t: Add SCPI protocol
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi | 21 +++++++++++++++++++++
+ 1 file changed, 21 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+index 0bbf43850c95..1ef9b4a581ac 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+@@ -284,6 +284,13 @@ opp-1800000000 {
+ 		};
+ 	};
+ 
++	scpi_protocol: scpi {
++		compatible = "arm,scpi";
++		mboxes = <&msgbox 2>, <&msgbox 3>;
++		mbox-names = "tx", "rx";
++		shmem = <&scpi_sram>;
++	};
++
+ 	soc {
+ 		compatible = "simple-bus";
+ 		#address-cells = <1>;
+@@ -417,6 +424,20 @@ syscon: syscon@1c00000 {
+ 			compatible = "allwinner,sun8i-a83t-system-controller",
+ 				"syscon";
+ 			reg = <0x01c00000 0x1000>;
++
++			sram_a2: sram@40000 {
++				compatible = "mmio-sram";
++				reg = <0x00040000 0x14000>;
++				#address-cells = <1>;
++				#size-cells = <1>;
++				ranges = <0 0x00040000 0x14000>;
++
++				scpi_sram: scp-shmem@13c00 {
++					compatible = "arm,scp-shmem";
++					reg = <0x13c00 0x200>;
++				};
++			};
++
+ 		};
+ 
+ 		video-codec@01c0e000 {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sunxi-h3-h5-Add-SCPI-protocol.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sunxi-h3-h5-Add-SCPI-protocol.patch
new file mode 100644
index 000000000000..594b982c3e1c
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sunxi-h3-h5-Add-SCPI-protocol.patch
@@ -0,0 +1,81 @@
+From f8e5ffe17a72e7fb942255154f5c9ff6f8b4a6bc Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Wed, 1 Jan 2020 16:12:36 -0600
+Subject: ARM: dts: sunxi: h3/h5: Add SCPI protocol
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm/boot/dts/allwinner/sun8i-h3.dtsi    | 13 +++++++++++++
+ arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi |  7 +++++++
+ arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 13 +++++++++++++
+ 3 files changed, 33 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi b/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi
+index da1991c991cb..e601317d5de2 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi
+@@ -206,6 +206,19 @@ syscon: system-control@1c00000 {
+ 			#size-cells = <1>;
+ 			ranges;
+ 
++			sram_a2: sram@40000 {
++				compatible = "mmio-sram";
++				reg = <0x00040000 0xc000>;
++				#address-cells = <1>;
++				#size-cells = <1>;
++				ranges = <0 0x00040000 0xc000>;
++
++				scpi_sram: scp-shmem@bc00 {
++					compatible = "arm,scp-shmem";
++					reg = <0xbc00 0x200>;
++				};
++			};
++
+ 			sram_c: sram@1d00000 {
+ 				compatible = "mmio-sram";
+ 				reg = <0x01d00000 0x80000>;
+diff --git a/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi
+index a872fc586ab6..ebc64458084c 100644
+--- a/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi
++++ b/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi
+@@ -120,6 +120,13 @@ de: display-engine {
+ 		status = "disabled";
+ 	};
+ 
++	scpi_protocol: scpi {
++		compatible = "arm,scpi";
++		mboxes = <&msgbox 2>, <&msgbox 3>;
++		mbox-names = "tx", "rx";
++		shmem = <&scpi_sram>;
++	};
++
+ 	soc {
+ 		compatible = "simple-bus";
+ 		#address-cells = <1>;
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
+index d3caf27b6a55..e02a3848003e 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
+@@ -86,6 +86,19 @@ syscon: system-control@1c00000 {
+ 			#size-cells = <1>;
+ 			ranges;
+ 
++			sram_a2: sram@40000 {
++				compatible = "mmio-sram";
++				reg = <0x00040000 0x14000>;
++				#address-cells = <1>;
++				#size-cells = <1>;
++				ranges = <0 0x00040000 0x14000>;
++
++				scpi_sram: scp-shmem@13c00 {
++					compatible = "arm,scp-shmem";
++					reg = <0x13c00 0x200>;
++				};
++			};
++
+ 			sram_c1: sram@18000 {
+ 				compatible = "mmio-sram";
+ 				reg = <0x00018000 0x1c000>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sunxi-h3-h5-Add-hdmi-sound-card.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sunxi-h3-h5-Add-hdmi-sound-card.patch
new file mode 100644
index 000000000000..23ce3e3a83e8
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-dts-sunxi-h3-h5-Add-hdmi-sound-card.patch
@@ -0,0 +1,48 @@
+From 797e9a51924977c4a8ed90d9f4c5c2af75c97dda Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sun, 9 May 2021 11:04:58 +0200
+Subject: ARM: dts: sunxi: h3/h5: Add hdmi sound card
+
+H3 and H5 support HDMI audio. Add a sound card node for it.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi | 15 +++++++++++++++
+ 1 file changed, 15 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi
+index 7df60515a903..0f19e7c00c50 100644
+--- a/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi
++++ b/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi
+@@ -106,6 +106,20 @@ de: display-engine {
+ 		status = "disabled";
+ 	};
+ 
++	sound_hdmi: sound_hdmi {
++		compatible = "allwinner,sun9i-a80-hdmi-audio",
++			     "allwinner,sun8i-h3-hdmi-audio";
++		status = "disabled";
++
++		codec {
++			sound-dai = <&hdmi>;
++		};
++
++		cpu {
++			sound-dai = <&i2s2>;
++		};
++	};
++
+ 	soc {
+ 		compatible = "simple-bus";
+ 		#address-cells = <1>;
+@@ -818,6 +832,7 @@ csi: camera@1cb0000 {
+ 		};
+ 
+ 		hdmi: hdmi@1ee0000 {
++			#sound-dai-cells = <0>;
+ 			compatible = "allwinner,sun8i-h3-dw-hdmi",
+ 				     "allwinner,sun8i-a83t-dw-hdmi";
+ 			reg = <0x01ee0000 0x10000>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-sunxi-Add-experimental-suspend-to-memory-implementation-for.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-sunxi-Add-experimental-suspend-to-memory-implementation-for.patch
new file mode 100644
index 000000000000..f3407c758d89
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-sunxi-Add-experimental-suspend-to-memory-implementation-for.patch
@@ -0,0 +1,88 @@
+From 64d4474e732197bc47adf374dd1dcf6bb24840e2 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Wed, 23 Oct 2019 05:06:29 +0200
+Subject: ARM: sunxi: Add experimental suspend to memory implementation for
+ A83T
+
+This just ends with WFI, but all secondary CPUs will be shut down.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/mach-sunxi/sunxi.c | 46 +++++++++++++++++++++++++++++++++++++
+ 1 file changed, 46 insertions(+)
+
+diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
+index e1b7945aac99..2d6b7b4528e9 100644
+--- a/arch/arm/mach-sunxi/sunxi.c
++++ b/arch/arm/mach-sunxi/sunxi.c
+@@ -12,10 +12,13 @@
+ #include <linux/init.h>
+ #include <linux/of_clk.h>
+ #include <linux/platform_device.h>
++#include <linux/of_platform.h>
+ #include <linux/reset/sunxi.h>
++#include <linux/suspend.h>
+ 
+ #include <asm/mach/arch.h>
+ #include <asm/secure_cntvoff.h>
++#include <asm/suspend.h>
+ 
+ static const char * const sunxi_board_dt_compat[] = {
+ 	"allwinner,sun4i-a10",
+@@ -86,10 +89,53 @@ static const char * const sun8i_a83t_cntvoff_board_dt_compat[] = {
+ 	NULL,
+ };
+ 
++#ifdef CONFIG_PM_SLEEP
++static int sun8i_a83t_pm_valid(suspend_state_t state)
++{
++	return state == PM_SUSPEND_MEM;
++}
++
++static int sun8i_a83t_suspend_finish(unsigned long val)
++{
++	// don't do much
++	cpu_do_idle();
++	return 0;
++}
++
++static int sun8i_a83t_pm_enter(suspend_state_t state)
++{
++	switch (state) {
++	case PM_SUSPEND_MEM:
++		cpu_suspend(0, sun8i_a83t_suspend_finish);
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static const struct platform_suspend_ops sun8i_a83t_pm_ops = {
++	.enter = sun8i_a83t_pm_enter,
++	.valid = sun8i_a83t_pm_valid,
++};
++#define SUN8I_A83T_PM_OPS &sun8i_a83t_pm_ops
++#else
++#define SUN8I_A83T_PM_OPS NULL
++#endif
++
++static void __init sun8i_a83t_init_machine(void)
++{
++	suspend_set_ops(SUN8I_A83T_PM_OPS);
++
++	of_platform_default_populate(NULL, NULL, NULL);
++}
++
+ DT_MACHINE_START(SUN8I_A83T_CNTVOFF_DT, "Allwinner A83t board")
+ 	.init_early	= sun8i_a83t_cntvoff_init,
+ 	.init_time	= sun6i_timer_init,
+ 	.dt_compat	= sun8i_a83t_cntvoff_board_dt_compat,
++	.init_machine	= sun8i_a83t_init_machine,
+ MACHINE_END
+ 
+ static const char * const sun9i_board_dt_compat[] = {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-sunxi-Use-SCPI-to-send-suspend-message-to-SCP-on-A83T.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-sunxi-Use-SCPI-to-send-suspend-message-to-SCP-on-A83T.patch
new file mode 100644
index 000000000000..f35af20790b6
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-sunxi-Use-SCPI-to-send-suspend-message-to-SCP-on-A83T.patch
@@ -0,0 +1,54 @@
+From 2c268237b942725705a5de8365c4142d45a346b5 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 2 Nov 2019 15:21:04 +0100
+Subject: ARM: sunxi: Use SCPI to send suspend message to SCP on A83T
+
+We use undefined value of 3, to mean SUSPEND_SYSTEM. SCP should:
+
+- kill CPU0
+- kill cluster 0
+- shutdown power to both clusters (Linux MCPM doesn't do that)
+...
+- reverse all of the above on interrupt
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/mach-sunxi/sunxi.c | 15 +++++++++++++--
+ 1 file changed, 13 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
+index 2d6b7b4528e9..d4c25c33455d 100644
+--- a/arch/arm/mach-sunxi/sunxi.c
++++ b/arch/arm/mach-sunxi/sunxi.c
+@@ -14,6 +14,7 @@
+ #include <linux/platform_device.h>
+ #include <linux/of_platform.h>
+ #include <linux/reset/sunxi.h>
++#include <linux/scpi_protocol.h>
+ #include <linux/suspend.h>
+ 
+ #include <asm/mach/arch.h>
+@@ -97,8 +98,18 @@ static int sun8i_a83t_pm_valid(suspend_state_t state)
+ 
+ static int sun8i_a83t_suspend_finish(unsigned long val)
+ {
+-	// don't do much
+-	cpu_do_idle();
++	struct scpi_ops *scpi;
++
++	scpi = get_scpi_ops();
++	if (scpi && scpi->sys_set_power_state) {
++		//HACK: use invalid state to mean: suspend last CPU and the system
++		scpi->sys_set_power_state(3);
++		cpu_do_idle();
++	} else {
++		// don't do much if scpi is not available
++		cpu_do_idle();
++	}
++
+ 	return 0;
+ }
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-sunxi-sunxi_cpu0_hotplug_support_set-is-not-supported-on-A8.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-sunxi-sunxi_cpu0_hotplug_support_set-is-not-supported-on-A8.patch
new file mode 100644
index 000000000000..cd6627ce570e
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/ARM-sunxi-sunxi_cpu0_hotplug_support_set-is-not-supported-on-A8.patch
@@ -0,0 +1,27 @@
+From 6410bf1e86927b02deae0fe3ddb51d41347f555b Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Wed, 23 Oct 2019 05:08:04 +0200
+Subject: ARM: sunxi: sunxi_cpu0_hotplug_support_set is not supported on A83T
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/mach-sunxi/mc_smp.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/arch/arm/mach-sunxi/mc_smp.c b/arch/arm/mach-sunxi/mc_smp.c
+index 277f6aa8e6c2..ca237d50db4b 100644
+--- a/arch/arm/mach-sunxi/mc_smp.c
++++ b/arch/arm/mach-sunxi/mc_smp.c
+@@ -146,6 +146,9 @@ static int sunxi_cpu_power_switch_set(unsigned int cpu, unsigned int cluster,
+ 
+ static void sunxi_cpu0_hotplug_support_set(bool enable)
+ {
++	if (is_a83t)
++		return;
++
+ 	if (enable) {
+ 		writel(CPU0_SUPPORT_HOTPLUG_MAGIC0, sram_b_smp_base);
+ 		writel(CPU0_SUPPORT_HOTPLUG_MAGIC1, sram_b_smp_base + 0x4);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/ASOC-sun9i-hdmi-audio-Initial-implementation.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/ASOC-sun9i-hdmi-audio-Initial-implementation.patch
new file mode 100644
index 000000000000..d9898d8e8946
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/ASOC-sun9i-hdmi-audio-Initial-implementation.patch
@@ -0,0 +1,233 @@
+From 0ab708fedde7fb0c6a3246c34cdc4490d7ce232a Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Tue, 10 Nov 2020 20:42:44 +0100
+Subject: ASOC: sun9i-hdmi-audio: Initial implementation
+
+This implements HDMI audio sound card which is used to enable HDMI audio
+on all Allwinner SoCs with DW-HDMI core. First such SoC is A80, but it's
+been used on plenty of others, like A64, A83t, H2+, H3, H5, H6, R40 and
+V40.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ sound/soc/sunxi/Kconfig            |   8 ++
+ sound/soc/sunxi/Makefile           |   1 +
+ sound/soc/sunxi/sun9i-hdmi-audio.c | 178 +++++++++++++++++++++++++++++
+ 3 files changed, 187 insertions(+)
+ create mode 100644 sound/soc/sunxi/sun9i-hdmi-audio.c
+
+diff --git a/sound/soc/sunxi/Kconfig b/sound/soc/sunxi/Kconfig
+index f87b061f59b2..753c38c5d554 100644
+--- a/sound/soc/sunxi/Kconfig
++++ b/sound/soc/sunxi/Kconfig
+@@ -76,6 +76,14 @@ config SND_SUN50I_DMIC
+ 	  Say Y or M to add support for the DMIC audio block in the Allwinner
+ 	  H6 and affiliated SoCs.
+ 
++config SND_SUN9I_HDMI_AUDIO
++	tristate "Allwinner sun9i HDMI Audio Sound Card"
++	depends on OF
++	depends on SND_SUN4I_I2S
++	help
++	  Say Y or M to add support for the HDMI Audio sound card for Allwinner
++	  SoCs with DW-HDMI core.
++
+ config SND_SUN8I_ADDA_PR_REGMAP
+ 	tristate
+ 	select REGMAP
+diff --git a/sound/soc/sunxi/Makefile b/sound/soc/sunxi/Makefile
+index 6131aea97efa..19800277105c 100644
+--- a/sound/soc/sunxi/Makefile
++++ b/sound/soc/sunxi/Makefile
+@@ -8,3 +8,4 @@ obj-$(CONFIG_SND_SUN50I_CODEC_ANALOG) += sun50i-codec-analog.o
+ obj-$(CONFIG_SND_SUN8I_CODEC) += sun8i-codec.o
+ obj-$(CONFIG_SND_SUN8I_ADDA_PR_REGMAP) += sun8i-adda-pr-regmap.o
+ obj-$(CONFIG_SND_SUN50I_DMIC) += sun50i-dmic.o
++obj-$(CONFIG_SND_SUN9I_HDMI_AUDIO) += sun9i-hdmi-audio.o
+diff --git a/sound/soc/sunxi/sun9i-hdmi-audio.c b/sound/soc/sunxi/sun9i-hdmi-audio.c
+new file mode 100644
+index 000000000000..32eb6d9decd3
+--- /dev/null
++++ b/sound/soc/sunxi/sun9i-hdmi-audio.c
+@@ -0,0 +1,178 @@
++// SPDX-License-Identifier: GPL-2.0
++//
++// sun9i hdmi audio sound card
++//
++// Copyright (C) 2021 Jernej Skrabec <jernej.skrabec@gmail.com>
++
++#include <linux/module.h>
++#include <linux/of_platform.h>
++
++#include <sound/soc.h>
++#include <sound/soc-dai.h>
++
++static int sun9i_hdmi_audio_hw_params(struct snd_pcm_substream *substream,
++				      struct snd_pcm_hw_params *params)
++{
++	struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
++	unsigned int mclk;
++
++	mclk = params_rate(params) * 128;
++
++	return snd_soc_dai_set_sysclk(snd_soc_rtd_to_cpu(rtd, 0), 0, mclk,
++				      SND_SOC_CLOCK_OUT);
++}
++
++static const struct snd_soc_ops sun9i_hdmi_audio_ops = {
++	.hw_params = sun9i_hdmi_audio_hw_params,
++};
++
++static int sun9i_hdmi_audio_dai_init(struct snd_soc_pcm_runtime *rtd)
++{
++	int ret;
++
++	/* TODO: switch to custom api once it's implemented in sun4i-i2s */
++	ret = snd_soc_dai_set_tdm_slot(snd_soc_rtd_to_cpu(rtd, 0), 0, 0, 2, 32);
++	if (ret) {
++		dev_err(snd_soc_rtd_to_cpu(rtd, 0)->dev,
++			"setting tdm link slots failed\n");
++		return ret;
++	}
++
++	return 0;
++}
++
++static int sun9i_hdmi_audio_parse_dai(struct device_node *node,
++				      struct snd_soc_dai_link_component *dlc)
++{
++	struct of_phandle_args args;
++	int ret;
++
++	if (!node)
++		return 0;
++
++	ret = of_parse_phandle_with_args(node, "sound-dai",
++					 "#sound-dai-cells", 0, &args);
++	if (ret)
++		return ret;
++
++	ret = snd_soc_get_dai_name(&args, &dlc->dai_name);
++	if (ret < 0) {
++		of_node_put(args.np);
++
++		return ret;
++	}
++
++	dlc->of_node = args.np;
++
++	return 0;
++}
++
++static int sun9i_hdmi_audio_probe(struct platform_device *pdev)
++{
++	struct snd_soc_dai_link_component *dlc;
++	struct device *dev = &pdev->dev;
++	struct snd_soc_dai_link *link;
++	struct snd_soc_card *card;
++	struct device_node *child;
++	int ret;
++
++	card = devm_kzalloc(dev, sizeof(*card), GFP_KERNEL);
++	if (!card)
++		return -ENOMEM;
++
++	link = devm_kzalloc(dev, sizeof(*link), GFP_KERNEL);
++	if (!link)
++		return -ENOMEM;
++
++	dlc = devm_kzalloc(dev, sizeof(*dlc) * 3, GFP_KERNEL);
++	if (!dlc)
++		return -ENOMEM;
++
++	child = of_get_child_by_name(dev->of_node, "codec");
++	if (!child)
++		return -ENODEV;
++
++	ret = sun9i_hdmi_audio_parse_dai(child, &dlc[1]);
++	of_node_put(child);
++	if (ret)
++		return ret;
++
++	child = of_get_child_by_name(dev->of_node, "cpu");
++	if (!child) {
++		ret = -ENODEV;
++		goto out_err;
++	}
++
++	ret = sun9i_hdmi_audio_parse_dai(child, &dlc[0]);
++	of_node_put(child);
++	if (ret)
++		goto out_err;
++
++	dlc[2].of_node = dlc[0].of_node;
++
++	platform_set_drvdata(pdev, card);
++
++	link->cpus = &dlc[0];
++	link->codecs = &dlc[1];
++	link->platforms = &dlc[2];
++
++	link->num_cpus = 1;
++	link->num_codecs = 1;
++	link->num_platforms = 1;
++
++	link->playback_only = 1;
++
++	link->name = "SUN9I-HDMI";
++	link->stream_name = "SUN9I-HDMI PCM";
++
++	link->dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_IF | SND_SOC_DAIFMT_CBS_CFS;
++
++	link->ops = &sun9i_hdmi_audio_ops;
++	link->init = sun9i_hdmi_audio_dai_init;
++
++	card->dai_link = link;
++	card->num_links = 1;
++	card->owner = THIS_MODULE;
++	card->dev = dev;
++	card->name = "sun9i-hdmi";
++
++	ret = devm_snd_soc_register_card(dev, card);
++	if (ret)
++		goto out_err;
++
++	return 0;
++
++out_err:
++	of_node_put(dlc[0].of_node);
++	of_node_put(dlc[1].of_node);
++
++	return ret;
++}
++
++static void sun9i_hdmi_audio_remove(struct platform_device *pdev)
++{
++	struct snd_soc_card *card = platform_get_drvdata(pdev);
++
++	of_node_put(card->dai_link->cpus->of_node);
++	of_node_put(card->dai_link->codecs->of_node);
++}
++
++static const struct of_device_id sun9i_hdmi_audio_match[] = {
++	{ .compatible = "allwinner,sun9i-a80-hdmi-audio" },
++	{}
++};
++MODULE_DEVICE_TABLE(of, sun9i_hdmi_audio_match);
++
++static struct platform_driver sun9i_hdmi_audio_driver = {
++	.probe = sun9i_hdmi_audio_probe,
++	.remove = sun9i_hdmi_audio_remove,
++	.driver = {
++		.name = "sun9i-hdmi-audio",
++		.of_match_table = sun9i_hdmi_audio_match,
++	},
++};
++module_platform_driver(sun9i_hdmi_audio_driver);
++
++MODULE_DESCRIPTION("sun9i HDMI Audio Sound Card");
++MODULE_AUTHOR("Jernej Skrabec <jernej.skrabec@gmail.com>");
++MODULE_LICENSE("GPL v2");
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/ASoC-ec25-New-codec-driver-for-the-EC25-modem.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/ASoC-ec25-New-codec-driver-for-the-EC25-modem.patch
new file mode 100644
index 000000000000..f5bbec78f5e2
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/ASoC-ec25-New-codec-driver-for-the-EC25-modem.patch
@@ -0,0 +1,154 @@
+From 1fa825de245c820af4b50883f14eed193a680a5e Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Fri, 25 Sep 2020 21:42:52 -0500
+Subject: ASoC: ec25: New codec driver for the EC25 modem
+
+The EC25 LTE modem has a PCM interface, and supports 16-bit PCM audio at
+an 8 kHz or 16 kHz sameple rate.
+
+Suggested-by: Luca Weiss <luca@z3ntu.xyz>
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ sound/soc/codecs/Kconfig  |  3 ++
+ sound/soc/codecs/Makefile |  2 +
+ sound/soc/codecs/ec25.c   | 94 +++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 99 insertions(+)
+ create mode 100644 sound/soc/codecs/ec25.c
+
+diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
+index ee35f3aa5521..6d67a9fc5304 100644
+--- a/sound/soc/codecs/Kconfig
++++ b/sound/soc/codecs/Kconfig
+@@ -1148,6 +1148,9 @@ config SND_SOC_HDMI_CODEC
+ 	select SND_PCM_IEC958
+ 	select HDMI
+ 
++config SND_SOC_EC25
++	tristate "EC25 LTE module CODEC"
++
+ config SND_SOC_ES7134
+ 	tristate "Everest Semi ES7134 CODEC"
+ 
+diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
+index d7ad795603c1..7e12f3ae4f7d 100644
+--- a/sound/soc/codecs/Makefile
++++ b/sound/soc/codecs/Makefile
+@@ -122,6 +122,7 @@ snd-soc-da7219-y := da7219.o da7219-aad.o
+ snd-soc-da732x-y := da732x.o
+ snd-soc-da9055-y := da9055.o
+ snd-soc-dmic-y := dmic.o
++snd-soc-ec25-y := ec25.o
+ snd-soc-es7134-y := es7134.o
+ snd-soc-es7241-y := es7241.o
+ snd-soc-es83xx-dsm-common-y := es83xx-dsm-common.o
+@@ -539,6 +540,7 @@ obj-$(CONFIG_SND_SOC_DA7219)	+= snd-soc-da7219.o
+ obj-$(CONFIG_SND_SOC_DA732X)	+= snd-soc-da732x.o
+ obj-$(CONFIG_SND_SOC_DA9055)	+= snd-soc-da9055.o
+ obj-$(CONFIG_SND_SOC_DMIC)	+= snd-soc-dmic.o
++obj-$(CONFIG_SND_SOC_EC25)	+= snd-soc-ec25.o
+ obj-$(CONFIG_SND_SOC_ES7134)	+= snd-soc-es7134.o
+ obj-$(CONFIG_SND_SOC_ES7241)	+= snd-soc-es7241.o
+ obj-$(CONFIG_SND_SOC_ES83XX_DSM_COMMON)    += snd-soc-es83xx-dsm-common.o
+diff --git a/sound/soc/codecs/ec25.c b/sound/soc/codecs/ec25.c
+new file mode 100644
+index 000000000000..4f9b6b06cce7
+--- /dev/null
++++ b/sound/soc/codecs/ec25.c
+@@ -0,0 +1,94 @@
++// SPDX-License-Identifier: GPL-2.0-only
++
++#include <linux/module.h>
++#include <sound/soc.h>
++
++static const struct snd_soc_dapm_widget ec25_dapm_widgets[] = {
++	SND_SOC_DAPM_OUTPUT("AOUT"),
++	SND_SOC_DAPM_INPUT("AIN"),
++};
++
++static const struct snd_soc_dapm_route ec25_dapm_routes[] = {
++	{ "AOUT", NULL, "Playback" },
++	{ "AOUT", NULL, "Wideband Playback" },
++	{ "Capture", NULL, "AIN" },
++	{ "Wideband Capture", NULL, "AIN" },
++};
++
++static const struct snd_soc_component_driver ec25_component_driver = {
++	.dapm_widgets		= ec25_dapm_widgets,
++	.num_dapm_widgets	= ARRAY_SIZE(ec25_dapm_widgets),
++	.dapm_routes		= ec25_dapm_routes,
++	.num_dapm_routes	= ARRAY_SIZE(ec25_dapm_routes),
++	.endianness		= 1,
++};
++
++static struct snd_soc_dai_driver ec25_dais[] = {
++	{
++		.name = "ec25",
++		.capture = {
++			.stream_name	= "Capture",
++			.channels_min	= 1,
++			.channels_max	= 1,
++			.rates		= SNDRV_PCM_RATE_8000,
++			.formats	= SNDRV_PCM_FMTBIT_S16_LE,
++		},
++		.playback = {
++			.stream_name	= "Playback",
++			.channels_min	= 1,
++			.channels_max	= 1,
++			.rates		= SNDRV_PCM_RATE_8000,
++			.formats	= SNDRV_PCM_FMTBIT_S16_LE,
++		},
++		.symmetric_rate = 1,
++		.symmetric_channels = 1,
++		.symmetric_sample_bits = 1,
++	},
++	{
++		.name = "ec25-wb",
++		.capture = {
++			.stream_name	= "Wideband Capture",
++			.channels_min	= 1,
++			.channels_max	= 1,
++			.rates		= SNDRV_PCM_RATE_16000,
++			.formats	= SNDRV_PCM_FMTBIT_S16_LE,
++		},
++		.playback = {
++			.stream_name	= "Wideband Playback",
++			.channels_min	= 1,
++			.channels_max	= 1,
++			.rates		= SNDRV_PCM_RATE_16000,
++			.formats	= SNDRV_PCM_FMTBIT_S16_LE,
++		},
++		.symmetric_rate = 1,
++		.symmetric_channels = 1,
++		.symmetric_sample_bits = 1,
++	},
++};
++
++static int ec25_codec_probe(struct platform_device *pdev)
++{
++	return devm_snd_soc_register_component(&pdev->dev, &ec25_component_driver,
++					       ec25_dais, ARRAY_SIZE(ec25_dais));
++}
++
++static const struct of_device_id ec25_codec_of_match[] = {
++	{ .compatible = "quectel,ec25", },
++	{},
++};
++MODULE_DEVICE_TABLE(of, ec25_codec_of_match);
++
++static struct platform_driver ec25_codec_driver = {
++	.driver	= {
++		.name		= "ec25",
++		.of_match_table	= of_match_ptr(ec25_codec_of_match),
++	},
++	.probe	= ec25_codec_probe,
++};
++
++module_platform_driver(ec25_codec_driver);
++
++MODULE_DESCRIPTION("ASoC ec25 driver");
++MODULE_AUTHOR("Samuel Holland <samuel@sholland.org>");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:ec25");
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/ASoC-rockchip-Fix-doubling-of-playback-speed-after-system-sleep.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/ASoC-rockchip-Fix-doubling-of-playback-speed-after-system-sleep.patch
new file mode 100644
index 000000000000..93010e489442
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/ASoC-rockchip-Fix-doubling-of-playback-speed-after-system-sleep.patch
@@ -0,0 +1,45 @@
+From c8ae813c02fca7c7c43317e894a6516e09012bd8 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Mon, 15 Aug 2022 02:23:37 +0200
+Subject: ASoC: rockchip: Fix doubling of playback speed after system sleep
+
+There is some issue with CRU on RK3399 that can be reproduced by:
+
+- playing some audio and stopping the playback (so that runtime PM suspends I2S)
+- putting system to deep sleep and resuming it (using mainline TF-A)
+- playing some audio (audio plays at 2x the normal speed)
+
+If the audio is kept playing during system sleep cycle, the issue
+does not manifest. Relevant registers in CRU are identical in bug/
+no-bug scenarios, so this patch is just touching the CRU registers
+without actually changing anything in the end. Touching the registers
+fixes the playback speed, though.
+
+Inspired by: https://github.com/djselbeck/linux/commit/cb4be5dec3fa18c4b344c11fed3fc57aa3bea424
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ sound/soc/rockchip/rockchip_i2s.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/sound/soc/rockchip/rockchip_i2s.c b/sound/soc/rockchip/rockchip_i2s.c
+index 4315da4a47c1..b6602eaea194 100644
+--- a/sound/soc/rockchip/rockchip_i2s.c
++++ b/sound/soc/rockchip/rockchip_i2s.c
+@@ -114,6 +114,13 @@ static int i2s_runtime_resume(struct device *dev)
+ 	if (ret)
+ 		clk_disable_unprepare(i2s->mclk);
+ 
++	if (ret == 0) {
++		unsigned long rate = clk_get_rate(i2s->mclk);
++
++		clk_set_rate(i2s->mclk, rate - 1);
++		clk_set_rate(i2s->mclk, rate);
++	}
++
+ 	return ret;
+ }
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/ASoC-simple-card-Allow-to-define-pins-for-aux-jack-devices.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/ASoC-simple-card-Allow-to-define-pins-for-aux-jack-devices.patch
new file mode 100644
index 000000000000..415f1f5bb511
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/ASoC-simple-card-Allow-to-define-pins-for-aux-jack-devices.patch
@@ -0,0 +1,67 @@
+From 60f86341890692981eed6c4c538b46d41788ce56 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Tue, 14 May 2024 10:46:10 +0200
+Subject: ASoC: simple-card: Allow to define pins for aux jack devices
+
+This restores original behavior of jack pins on Pinephone, as it was
+before upstreaming jack detection to codec driver.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ sound/soc/generic/simple-card-utils.c | 40 +++++++++++++++++++++++++++
+ 1 file changed, 40 insertions(+)
+
+diff --git a/sound/soc/generic/simple-card-utils.c b/sound/soc/generic/simple-card-utils.c
+index 32efb30c55d6..7df92e045c5c 100644
+--- a/sound/soc/generic/simple-card-utils.c
++++ b/sound/soc/generic/simple-card-utils.c
+@@ -852,6 +852,46 @@ int simple_util_init_aux_jacks(struct simple_util_priv *priv, char *prefix)
+ 			continue;
+ 
+ 		(void)snd_soc_component_set_jack(component, jack, NULL);
++
++		/* add pins to the jack */
++		int count = of_property_count_strings(card->dev->of_node, "simple-audio-card,jack-pins");
++		if (count < 0) {
++			if (count != -EINVAL)
++				dev_warn(card->dev, "Invalid jack-pins property\n");
++			continue;
++		}
++		if (count % 2) {
++			dev_warn(card->dev, "jack-pins property must have even number of strings\n");
++			continue;
++		}
++
++		for (int idx = 0; idx < count; idx += 2) {
++			const char *aux_dev_name, *pin_name;
++			u32 mask;
++
++			ret = of_property_read_string_index(card->dev->of_node, "simple-audio-card,jack-pins", idx, &aux_dev_name);
++			if (ret < 0)
++				continue;
++			ret = of_property_read_string_index(card->dev->of_node, "simple-audio-card,jack-pins", idx + 1, &pin_name);
++			if (ret < 0)
++				continue;
++			ret = of_property_read_u32_index(card->dev->of_node, "simple-audio-card,jack-pins-mask", idx / 2, &mask);
++			if (ret < 0) {
++				dev_warn(card->dev, "jack-pins-mask for jack pin %s/%s can't be read\n", aux_dev_name, pin_name);
++				continue;
++			}
++
++			if (!strcmp(aux_dev_name, component->name)) {
++				struct snd_soc_jack_pin *pin = devm_kzalloc(card->dev, sizeof(*pin), GFP_KERNEL);
++
++				pin->pin = pin_name;
++				pin->mask = mask;
++
++				dev_info(card->dev, "Adding jack %s pin %s (mask %d)\n",
++					 aux_dev_name, pin_name, pin->mask);
++				snd_soc_jack_add_pins(jack, 1, pin);
++			}
++		}
+ 	}
+ 	return 0;
+ }
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/ASoC-sun8i-codec-Add-debug-output-for-jack-detection.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/ASoC-sun8i-codec-Add-debug-output-for-jack-detection.patch
new file mode 100644
index 000000000000..b5958b5863fb
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/ASoC-sun8i-codec-Add-debug-output-for-jack-detection.patch
@@ -0,0 +1,129 @@
+From 5ceac3477d9df0651a27ac60f88c8d67f516d60b Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sat, 17 Feb 2024 01:13:39 +0100
+Subject: ASoC: sun8i-codec: Add debug output for jack detection
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ sound/soc/sunxi/sun8i-codec.c | 32 +++++++++++++++++++++++++++++++-
+ 1 file changed, 31 insertions(+), 1 deletion(-)
+
+diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c
+index c5948b650777..6a9e147a6a1b 100644
+--- a/sound/soc/sunxi/sun8i-codec.c
++++ b/sound/soc/sunxi/sun8i-codec.c
+@@ -9,6 +9,8 @@
+  * Mylène Josserand <mylene.josserand@free-electrons.com>
+  */
+ 
++#define DEBUG
++
+ #include <linux/module.h>
+ #include <linux/delay.h>
+ #include <linux/clk.h>
+@@ -234,6 +236,7 @@ struct sun8i_codec {
+ 	int				jack_status;
+ 	int				jack_type;
+ 	int				jack_last_sample;
++	unsigned			jack_last_btn;
+ 	ktime_t				jack_hbias_ready;
+ 	struct mutex			jack_mutex;
+ 	int				last_hmic_irq;
+@@ -1344,6 +1347,8 @@ static void sun8i_codec_set_hmic_bias(struct sun8i_codec *scodec, bool enable)
+ 
+ 	snd_soc_dapm_sync(dapm);
+ 
++	dev_dbg(scodec->component->dev, "HMIC bias %s\n", enable ? "on" : "off");
++
+ 	regmap_update_bits(scodec->regmap, SUN8I_HMIC_CTRL1,
+ 			   irq_mask, enable ? irq_mask : 0);
+ }
+@@ -1352,6 +1357,7 @@ static void sun8i_codec_jack_work(struct work_struct *work)
+ {
+ 	struct sun8i_codec *scodec = container_of(work, struct sun8i_codec,
+ 						  jack_work.work);
++	struct device *dev = scodec->component->dev;
+ 	unsigned int mdata;
+ 	int type;
+ 
+@@ -1362,6 +1368,7 @@ static void sun8i_codec_jack_work(struct work_struct *work)
+ 			return;
+ 
+ 		scodec->jack_last_sample = -1;
++		scodec->jack_last_btn = 0;
+ 
+ 		if (scodec->jack_type & SND_JACK_MICROPHONE) {
+ 			/*
+@@ -1419,6 +1426,8 @@ static void sun8i_codec_jack_work(struct work_struct *work)
+ 
+ 		snd_soc_jack_report(scodec->jack, type, scodec->jack_type);
+ 		scodec->jack_status = SUN8I_JACK_STATUS_CONNECTED;
++
++		dev_dbg(dev, "jack: plug-in reported\n");
+ 	} else if (scodec->jack_status == SUN8I_JACK_STATUS_CONNECTED) {
+ 		if (scodec->last_hmic_irq != SUN8I_HMIC_STS_JACK_OUT_IRQ_ST)
+ 			return;
+@@ -1428,14 +1437,18 @@ static void sun8i_codec_jack_work(struct work_struct *work)
+ 			sun8i_codec_set_hmic_bias(scodec, false);
+ 
+ 		snd_soc_jack_report(scodec->jack, 0, scodec->jack_type);
++
++		dev_dbg(dev, "jack: plug-out reported\n");
+ 	}
+ }
+ 
+ static irqreturn_t sun8i_codec_jack_irq(int irq, void *dev_id)
+ {
+ 	struct sun8i_codec *scodec = dev_id;
++	struct device *dev = scodec->component->dev;
+ 	int type = SND_JACK_HEADSET;
+ 	unsigned int status, value;
++	unsigned btn_chg = 0;
+ 
+ 	guard(mutex)(&scodec->jack_mutex);
+ 
+@@ -1447,6 +1460,8 @@ static irqreturn_t sun8i_codec_jack_irq(int irq, void *dev_id)
+ 	 * 100ms after each interrupt..
+ 	 */
+ 	if (status & BIT(SUN8I_HMIC_STS_JACK_OUT_IRQ_ST)) {
++		dev_dbg(dev, "jack: irq plug-out\n");
++
+ 		/*
+ 		 * Out interrupt has priority over in interrupt so that if
+ 		 * we get both, we assume the disconnected state, which is
+@@ -1456,6 +1471,8 @@ static irqreturn_t sun8i_codec_jack_irq(int irq, void *dev_id)
+ 		mod_delayed_work(system_power_efficient_wq, &scodec->jack_work,
+ 				 msecs_to_jiffies(100));
+ 	} else if (status & BIT(SUN8I_HMIC_STS_JACK_IN_IRQ_ST)) {
++		dev_dbg(dev, "jack: irq plug-in\n");
++
+ 		scodec->last_hmic_irq = SUN8I_HMIC_STS_JACK_IN_IRQ_ST;
+ 		mod_delayed_work(system_power_efficient_wq, &scodec->jack_work,
+ 				 msecs_to_jiffies(100));
+@@ -1489,9 +1506,22 @@ static irqreturn_t sun8i_codec_jack_irq(int irq, void *dev_id)
+ 		 * samples are identical.
+ 		 */
+ 		if (scodec->jack_last_sample >= 0 &&
+-		    scodec->jack_last_sample == value)
++		    scodec->jack_last_sample == value) {
+ 			snd_soc_jack_report(scodec->jack, type,
+ 					    scodec->jack_type);
++			btn_chg = (scodec->jack_last_btn ^ type) & SUN8I_CODEC_BUTTONS;
++			scodec->jack_last_btn = type;
++		}
++
++		if (btn_chg & SND_JACK_BTN_0)
++			dev_dbg(dev, "jack: key_%spress BTN_0 (%#x)\n",
++				type & SND_JACK_BTN_0 ? "" : "de", value);
++		if (btn_chg & SND_JACK_BTN_1)
++			dev_dbg(dev, "jack: key_%spress BTN_1 (%#x)\n",
++				type & SND_JACK_BTN_1 ? "" : "de", value);
++		if (btn_chg & SND_JACK_BTN_2)
++			dev_dbg(dev, "jack: key_%spress BTN_2 (%#x)\n",
++				type & SND_JACK_BTN_2 ? "" : "de", value);
+ 
+ 		scodec->jack_last_sample = value;
+ 	}
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/ASoC-sun8i-codec-Allow-the-jack-type-to-be-set-via-device-tree.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/ASoC-sun8i-codec-Allow-the-jack-type-to-be-set-via-device-tree.patch
new file mode 100644
index 000000000000..c78992b5cd8c
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/ASoC-sun8i-codec-Allow-the-jack-type-to-be-set-via-device-tree.patch
@@ -0,0 +1,47 @@
+From 6badb648bf732dd8480424ab5ddbeb0f1c9736a8 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sat, 2 Mar 2024 14:55:31 +0100
+Subject: ASoC: sun8i-codec: Allow the jack type to be set via device tree
+
+This makes the codec's jack detection functionality usable from within
+simple-sound-card.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ sound/soc/sunxi/sun8i-codec.c | 13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+
+diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c
+index 8c645e04d571..838880cf5bd4 100644
+--- a/sound/soc/sunxi/sun8i-codec.c
++++ b/sound/soc/sunxi/sun8i-codec.c
+@@ -1563,6 +1563,18 @@ static void sun8i_codec_disable_jack_detect(struct snd_soc_component *component)
+ 	scodec->jack = NULL;
+ }
+ 
++static int sun8i_codec_component_get_jack_type(struct snd_soc_component *component)
++{
++	struct device_node *node = component->dev->of_node;
++
++	if (of_property_match_string(node, "jack-type", "headset") >= 0)
++		return SND_JACK_HEADSET | SUN8I_CODEC_BUTTONS;
++	else if (of_property_match_string(node, "jack-type", "headphone") >= 0)
++		return SND_JACK_HEADPHONE;
++
++	return 0;
++}
++
+ static int sun8i_codec_component_set_jack(struct snd_soc_component *component,
+ 					  struct snd_soc_jack *jack, void *data)
+ {
+@@ -1584,6 +1596,7 @@ static const struct snd_soc_component_driver sun8i_soc_component = {
+ 	.dapm_routes		= sun8i_codec_dapm_routes,
+ 	.num_dapm_routes	= ARRAY_SIZE(sun8i_codec_dapm_routes),
+ 	.set_jack		= sun8i_codec_component_set_jack,
++	.get_jack_type		= sun8i_codec_component_get_jack_type,
+ 	.probe			= sun8i_codec_component_probe,
+ 	.idle_bias_on		= 1,
+ 	.suspend_bias_off	= 1,
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/ASoC-sun8i-codec-Set-jack_type-from-DT-in-probe.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/ASoC-sun8i-codec-Set-jack_type-from-DT-in-probe.patch
new file mode 100644
index 000000000000..0890c58da722
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/ASoC-sun8i-codec-Set-jack_type-from-DT-in-probe.patch
@@ -0,0 +1,48 @@
+From bcd4fc8b4628893abdc7738afb815887ac8951d5 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Tue, 26 Mar 2024 17:38:38 +0100
+Subject: ASoC: sun8i-codec: Set jack_type from DT in probe
+
+Jack type needs to be set in probe so that it can be used later on.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ sound/soc/sunxi/sun8i-codec.c | 14 +++++++-------
+ 1 file changed, 7 insertions(+), 7 deletions(-)
+
+diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c
+index 6a9e147a6a1b..b195ddc5d5cf 100644
+--- a/sound/soc/sunxi/sun8i-codec.c
++++ b/sound/soc/sunxi/sun8i-codec.c
+@@ -1602,14 +1602,9 @@ static void sun8i_codec_disable_jack_detect(struct snd_soc_component *component)
+ 
+ static int sun8i_codec_component_get_jack_type(struct snd_soc_component *component)
+ {
+-	struct device_node *node = component->dev->of_node;
+-
+-	if (of_property_match_string(node, "jack-type", "headset") >= 0)
+-		return SND_JACK_HEADSET | SUN8I_CODEC_BUTTONS;
+-	else if (of_property_match_string(node, "jack-type", "headphone") >= 0)
+-		return SND_JACK_HEADPHONE;
++	struct sun8i_codec *scodec = snd_soc_component_get_drvdata(component);
+ 
+-	return 0;
++	return scodec->jack_type;
+ }
+ 
+ static int sun8i_codec_component_set_jack(struct snd_soc_component *component,
+@@ -1671,6 +1666,11 @@ static int sun8i_codec_probe(struct platform_device *pdev)
+ 
+ 	platform_set_drvdata(pdev, scodec);
+ 
++	if (of_property_match_string(pdev->dev.of_node, "jack-type", "headset") >= 0)
++		scodec->jack_type = SND_JACK_HEADSET | SUN8I_CODEC_BUTTONS;
++	else if (of_property_match_string(pdev->dev.of_node, "jack-type", "headphone") >= 0)
++		scodec->jack_type = SND_JACK_HEADPHONE;
++
+ 	if (scodec->quirks->bus_clock) {
+ 		scodec->clk_bus = devm_clk_get(&pdev->dev, "bus");
+ 		if (IS_ERR(scodec->clk_bus)) {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/ASoC-sun8i-codec-define-button-keycodes.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/ASoC-sun8i-codec-define-button-keycodes.patch
new file mode 100644
index 000000000000..0abda11785ec
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/ASoC-sun8i-codec-define-button-keycodes.patch
@@ -0,0 +1,31 @@
+From 14100a8e3e83aeb304a3f136eb5aad44b7026feb Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Fri, 23 Feb 2024 01:58:40 +0100
+Subject: ASoC: sun8i-codec: define button keycodes
+
+This is likely not upstreamable, but simple. :)
+---
+ sound/soc/sunxi/sun8i-codec.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c
+index 838880cf5bd4..c5948b650777 100644
+--- a/sound/soc/sunxi/sun8i-codec.c
++++ b/sound/soc/sunxi/sun8i-codec.c
+@@ -1541,6 +1541,13 @@ static int sun8i_codec_enable_jack_detect(struct snd_soc_component *component,
+ 	if (ret)
+ 		return ret;
+ 
++	if (jack->jack->type & SND_JACK_MICROPHONE) {
++		snd_jack_set_key(jack->jack, SND_JACK_BTN_0, KEY_PLAYPAUSE);
++		snd_jack_set_key(jack->jack, SND_JACK_BTN_1, KEY_VOLUMEUP);
++		snd_jack_set_key(jack->jack, SND_JACK_BTN_2, KEY_VOLUMEDOWN);
++		snd_jack_set_key(jack->jack, SND_JACK_BTN_3, KEY_VOICECOMMAND);
++	}
++
+ 	return 0;
+ }
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/Add-README.md-with-information-and-u-boot-patches.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/Add-README.md-with-information-and-u-boot-patches.patch
new file mode 100644
index 000000000000..cb947ec3c214
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/Add-README.md-with-information-and-u-boot-patches.patch
@@ -0,0 +1,215 @@
+From 71cc8805841a3e8e908770977756c51c555ac801 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 22 Nov 2016 01:01:49 +0100
+Subject: Add README.md with information and u-boot patches
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ ...Fix-PLL1-setup-to-never-use-dividers.patch |  33 ++++
+ README.md                                     | 154 ++++++++++++++++++
+ 2 files changed, 187 insertions(+)
+ create mode 100644 0001-sunxi-h3-Fix-PLL1-setup-to-never-use-dividers.patch
+ create mode 100644 README.md
+
+diff --git a/0001-sunxi-h3-Fix-PLL1-setup-to-never-use-dividers.patch b/0001-sunxi-h3-Fix-PLL1-setup-to-never-use-dividers.patch
+new file mode 100644
+index 000000000000..2b892e805a2b
+--- /dev/null
++++ b/0001-sunxi-h3-Fix-PLL1-setup-to-never-use-dividers.patch
+@@ -0,0 +1,33 @@
++From 7f5071f906f79bdc99d6b4b0ccf0cb280abe740b Mon Sep 17 00:00:00 2001
++From: Ondrej Jirman <megi@xff.cz>
++Date: Tue, 20 Dec 2016 11:25:12 +0100
++Subject: [PATCH] sunxi: h3: Fix PLL1 setup to never use dividers
++
++Kernel would lower the divider on first CLK change and cause the
++lock up.
++---
++ arch/arm/mach-sunxi/clock_sun6i.c | 7 +++----
++ 1 file changed, 3 insertions(+), 4 deletions(-)
++
++diff --git a/arch/arm/mach-sunxi/clock_sun6i.c b/arch/arm/mach-sunxi/clock_sun6i.c
++index 50fb302a19..91aa2a0478 100644
++--- a/arch/arm/mach-sunxi/clock_sun6i.c
+++++ b/arch/arm/mach-sunxi/clock_sun6i.c
++@@ -94,11 +94,10 @@ void clock_set_pll1(unsigned int clk)
++ 	int k = 1;
++ 	int m = 1;
++ 
++-	if (clk > 1152000000) {
++-		k = 2;
++-	} else if (clk > 768000000) {
+++	if (clk >= 1368000000) {
++ 		k = 3;
++-		m = 2;
+++	} else if (clk >= 768000000) {
+++		k = 2;
++ 	}
++ 
++ 	/* Switch to 24MHz clock while changing PLL1 */
++-- 
++2.11.0
++
+diff --git a/README.md b/README.md
+new file mode 100644
+index 000000000000..74c4c16416d3
+--- /dev/null
++++ b/README.md
+@@ -0,0 +1,154 @@
++Mainline linux kernel for Orange Pi PC/PC2/PC3/One, TBS A711, PinePhone (Pro), PocketBook Touch Lux 3
++------------------------------------------------------------------------------------------------------
++
++This kernel tree is meant for:
++
++- Orange Pi One
++- Orange Pi PC
++- Orange Pi PC 2
++- Orange Pi 3
++- PinePhone 1.0, 1.1 and 1.2(a/b)
++- TBS A711 Tablet
++- PocketBook Touch Lux 3
++- Pinebook Pro
++- Pinephone Pro
++
++Features in addition to mainline:
++
++- [Orange Pi One/PC/PC2] More aggressive OPPs for CPU
++- [All] Mark one of DRM planes as a cursor plane, speeding up Xorg based desktop with modesetting driver
++- [Orange Pi One/PC/PC2] Configure on-board micro-switches to perform system power off function
++- [Orange Pi One/PC/PC2/3] HDMI audio
++- [Orange Pi 3] Ethernet
++- [TBS A711] HM5065 (back camera) / GC2145 (front camera)
++- [PinePhone] WiFi, Bluetooth, Audio, Modem power, HDMI out over USB-C, USB-C support, cameras, PMIC improvements, power management, fixes here and there
++- [PocketBook Touch Lux 3] Display and Touchscreen support
++- [Pinephone Pro] Everything
++
++Pre-built u-boot and kernels are available at https://xff.cz/kernels/
++
++You may need some firmware files for some part of the functionality. Those are
++available at: https://megous.com/git/linux-firmware
++
++If you want to reproduce my pre-built kernels exactly, you'll need to uncomment
++CONFIG_EXTRA_FIRMWARE_DIR and CONFIG_EXTRA_FIRMWARE in the defconfigs, and
++point CONFIG_EXTRA_FIRMWARE_DIR to a directory on your computer where the
++clone of https://megous.com/git/linux-firmware resides.
++
++You can also leave those two config options commented out, and copy the contents
++of https://megous.com/git/linux-firmware to /lib/firmware/ on the target device.
++
++You can use this kernel to run a desktop environment on Orange Pi SBCs,
++Arch Linux on your Pinephone, or to have a completely opensource OS on
++a Pocketbook e-ink book reader.
++
++Have fun!
++
++
++Build instructions
++------------------
++
++These are rudimentary instructions and you need to understand what you're doing.
++These are just core steps required to build the ATF/u-boot/kernel. Downloading,
++verifying, renaming to correct directories is not described or mentioned. You
++should be able to infer missing necessary steps yourself for your particular needs.
++
++Get necessary toolchains from:
++
++- https://releases.linaro.org/components/toolchain/binaries/latest/aarch64-linux-gnu/ for 64bit Orange Pi PC2 and Orange Pi 3, PinePhone
++- https://releases.linaro.org/components/toolchain/binaries/latest/arm-linux-gnueabihf/ for 32bit Orange Pis, Pocketbook, TBS tablet
++
++Extract toolchains and prepare the environment:
++
++    CWD=`pwd`
++    OUT=$CWD/builds
++    SRC=$CWD/u-boot
++    export PATH="$PATH:$CWD/Toolchains/arm/bin:$CWD/Toolchains/aarch64/bin"
++
++For Orange Pi PC2, Orange Pi 3 or PinePhone:
++
++    export CROSS_COMPILE=aarch64-linux-gnu-
++    export KBUILD_OUTPUT=$OUT/.tmp/uboot-pc2
++    rm -rf "$KBUILD_OUTPUT"
++    mkdir -p $KBUILD_OUTPUT $OUT/pc2
++
++Get and build ATF from https://github.com/ARM-software/arm-trusted-firmware:
++
++    make -C "$CWD/arm-trusted-firmware" PLAT=sun50i_a64 DEBUG=1 bl31
++    cp "$CWD/arm-trusted-firmware/build/sun50i_a64/debug/bl31.bin" "$KBUILD_OUTPUT"
++
++Use sun50i_a64 for Orange Pi PC2 or PinePhone and sun50i_h6 for Orange Pi 3.
++
++Build u-boot from https://megous.com/git/u-boot/ (opi-v2020.04 branch) with appropriate
++defconfig (orangepi_one_defconfig, orangepi_pc2_defconfig, orangepi_pc_defconfig, orangepi_3_defconfig, tbs_a711_defconfig, pinephone_defconfig).
++
++My u-boot branch already has all the necessary patches integrated and is configured for quick u-boot/kernel startup.
++
++    make -C u-boot orangepi_pc2_defconfig
++    make -C u-boot -j5
++    
++    cp $KBUILD_OUTPUT/.config $OUT/pc2/uboot.config
++    cat $KBUILD_OUTPUT/{spl/sunxi-spl.bin,u-boot.itb} > $OUT/pc2/uboot.bin
++
++Get kernel from this repository and checkout the latest orange-pi-5.18 branch.
++
++Build the kernel for 64-bit boards:
++
++    export ARCH=arm64
++    export CROSS_COMPILE=aarch64-linux-gnu-
++    export KBUILD_OUTPUT=$OUT/.tmp/linux-arm64
++    mkdir -p $KBUILD_OUTPUT $OUT/pc2
++
++    make -C linux orangepi_defconfig
++    # or make -C linux pocketbook_touch_lux_3_defconfig
++    # or make -C linux tbs_a711_defconfig
++    make -C linux -j5 clean
++    make -C linux -j5 Image dtbs
++
++    cp -f $KBUILD_OUTPUT/arch/arm64/boot/Image $OUT/pc2/
++    cp -f $KBUILD_OUTPUT/.config $OUT/pc2/linux.config
++    cp -f $KBUILD_OUTPUT/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dtb $OUT/pc2/board.dtb
++
++Build the kernel for 32-bit boards:
++
++    export ARCH=arm
++    export CROSS_COMPILE=arm-linux-gnueabihf-
++    export KBUILD_OUTPUT=$OUT/.tmp/linux-arm
++    mkdir -p $KBUILD_OUTPUT $OUT/pc
++
++    make orangepi_defconfig
++    # or make pinephone_defconfig
++    make -C linux orangepi_defconfig
++    make -C linux -j5 clean
++    make -C linux -j5 zImage dtbs
++    
++    cp -f $KBUILD_OUTPUT/arch/arm/boot/zImage $OUT/pc/
++    cp -f $KBUILD_OUTPUT/.config $OUT/pc/linux.config
++    cp -f $KBUILD_OUTPUT/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dtb $OUT/pc/board.dtb
++    # Or use sun8i-h3-orangepi-one.dtb for Orange Pi One
++
++
++PinePhone
++---------
++
++I don't run u-boot on PinePhone, so my pre-built kernel packages don't come
++with u-boot built for PinePhone.
++
++
++Kernel lockup issues
++--------------------
++
++*If you're getting lockups on boot or later during thermal regulation,
++you're missing an u-boot patch.*
++
++This patch is necessary to run this kernel!
++
++These lockups are caused by improper NKMP clock factors selection
++in u-boot for PLL_CPUX. (M divider should not be used. P divider
++should be used only for frequencies below 240MHz.)
++
++This patch for u-boot fixes it:
++
++  0001-sunxi-h3-Fix-PLL1-setup-to-never-use-dividers.patch
++
++Kernel side is already fixed in this kernel tree.
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/Add-support-for-my-private-Sapomat-device.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/Add-support-for-my-private-Sapomat-device.patch
new file mode 100644
index 000000000000..ed1ab0785c87
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/Add-support-for-my-private-Sapomat-device.patch
@@ -0,0 +1,66 @@
+From 072caacd4e78332b3de5ed7621ded977eeb6c5e5 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Fri, 18 Aug 2017 13:56:06 +0200
+Subject: Add support for my private Sapomat device
+
+---
+ arch/arm/boot/dts/allwinner/Makefile          |  1 +
+ .../sun8i-h3-orangepi-pc-sapomat.dts          | 34 +++++++++++++++++++
+ 2 files changed, 35 insertions(+)
+ create mode 100644 arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc-sapomat.dts
+
+diff --git a/arch/arm/boot/dts/allwinner/Makefile b/arch/arm/boot/dts/allwinner/Makefile
+index 48666f73e638..1356e9553bd6 100644
+--- a/arch/arm/boot/dts/allwinner/Makefile
++++ b/arch/arm/boot/dts/allwinner/Makefile
+@@ -239,6 +239,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
+ 	sun8i-h3-orangepi-lite.dtb \
+ 	sun8i-h3-orangepi-one.dtb \
+ 	sun8i-h3-orangepi-pc.dtb \
++	sun8i-h3-orangepi-pc-sapomat.dtb \
+ 	sun8i-h3-orangepi-pc-plus.dtb \
+ 	sun8i-h3-orangepi-plus.dtb \
+ 	sun8i-h3-orangepi-plus2e.dtb \
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc-sapomat.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc-sapomat.dts
+new file mode 100644
+index 000000000000..55c82d5fb63f
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc-sapomat.dts
+@@ -0,0 +1,34 @@
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/input.h>
++#include "sun8i-h3-orangepi-pc.dts"
++
++/ {
++	model = "Xunlong Orange Pi PC Sapomat";
++
++	sapomat_gpio_keys {
++		compatible = "gpio-keys-polled";
++		poll-interval = <50>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&sapomat_btn_pins>;
++
++		red_btn {
++			label = "Red Button";
++			linux,code = <BTN_4>;
++			gpios = <&pio 2 4 GPIO_ACTIVE_LOW>; /* PC4 */
++		};
++
++		green_btn {
++			label = "Green Button";
++			linux,code = <BTN_5>;
++			gpios = <&pio 2 7 GPIO_ACTIVE_LOW>; /* PC7 */
++		};
++	};
++};
++
++&pio {
++	sapomat_btn_pins: btn_pins@0 {
++		pins = "PC4", "PC7";
++		function = "gpio_in";
++		bias-pull-up;
++	};
++};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/Defconfigs-for-all-my-devices.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/Defconfigs-for-all-my-devices.patch
new file mode 100644
index 000000000000..4701a17f799d
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/Defconfigs-for-all-my-devices.patch
@@ -0,0 +1,4002 @@
+From b5cd928a177e0a489156d5634dc9b10b6d568ab6 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 16 Sep 2019 00:35:50 +0200
+Subject: Defconfigs for all my devices
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/configs/orangepi_defconfig           |  715 ++++++++++++
+ .../configs/pocketbook_touch_lux_3_defconfig  |  416 +++++++
+ arch/arm/configs/tbs_a711_defconfig           |  524 +++++++++
+ arch/arm64/configs/orangepi_defconfig         | 1037 +++++++++++++++++
+ arch/arm64/configs/pinephone_defconfig        |  650 +++++++++++
+ .../configs/pinephone_multidist_defconfig     |  600 ++++++++++
+ 6 files changed, 3942 insertions(+)
+ create mode 100644 arch/arm/configs/orangepi_defconfig
+ create mode 100644 arch/arm/configs/pocketbook_touch_lux_3_defconfig
+ create mode 100644 arch/arm/configs/tbs_a711_defconfig
+ create mode 100644 arch/arm64/configs/orangepi_defconfig
+ create mode 100644 arch/arm64/configs/pinephone_defconfig
+ create mode 100644 arch/arm64/configs/pinephone_multidist_defconfig
+
+diff --git a/arch/arm/configs/orangepi_defconfig b/arch/arm/configs/orangepi_defconfig
+new file mode 100644
+index 000000000000..b76f1dc0eba9
+--- /dev/null
++++ b/arch/arm/configs/orangepi_defconfig
+@@ -0,0 +1,715 @@
++CONFIG_KERNEL_LZ4=y
++CONFIG_SYSVIPC=y
++CONFIG_POSIX_MQUEUE=y
++CONFIG_NO_HZ=y
++CONFIG_HIGH_RES_TIMERS=y
++CONFIG_BPF_SYSCALL=y
++# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set
++CONFIG_BSD_PROCESS_ACCT=y
++CONFIG_BSD_PROCESS_ACCT_V3=y
++CONFIG_TASKSTATS=y
++CONFIG_TASK_DELAY_ACCT=y
++CONFIG_TASK_XACCT=y
++CONFIG_TASK_IO_ACCOUNTING=y
++CONFIG_MEMCG=y
++CONFIG_BLK_CGROUP=y
++CONFIG_RT_GROUP_SCHED=y
++CONFIG_CGROUP_PIDS=y
++CONFIG_CPUSETS=y
++# CONFIG_PROC_PID_CPUSET is not set
++CONFIG_CGROUP_DEVICE=y
++CONFIG_CGROUP_BPF=y
++CONFIG_USER_NS=y
++CONFIG_SCHED_AUTOGROUP=y
++# CONFIG_RD_BZIP2 is not set
++# CONFIG_RD_LZMA is not set
++# CONFIG_RD_XZ is not set
++# CONFIG_RD_LZO is not set
++CONFIG_BOOT_CONFIG=y
++CONFIG_PERF_EVENTS=y
++CONFIG_ARCH_BCM=y
++CONFIG_ARCH_BCM2835=y
++CONFIG_ARCH_SUNXI=y
++# CONFIG_MACH_SUN9I is not set
++CONFIG_ARM_LPAE=y
++CONFIG_ARM_ERRATA_814220=y
++CONFIG_SMP=y
++CONFIG_SCHED_MC=y
++CONFIG_MCPM=y
++CONFIG_NR_CPUS=8
++CONFIG_HOTPLUG_CPU=y
++CONFIG_HZ_300=y
++CONFIG_HIGHMEM=y
++# CONFIG_ARM_MODULE_PLTS is not set
++CONFIG_ARCH_FORCE_MAX_ORDER=11
++CONFIG_ZBOOT_ROM_TEXT=0
++CONFIG_ZBOOT_ROM_BSS=0
++CONFIG_CPU_FREQ=y
++CONFIG_CPU_FREQ_STAT=y
++CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
++CONFIG_CPU_FREQ_GOV_POWERSAVE=y
++CONFIG_CPU_FREQ_GOV_USERSPACE=y
++CONFIG_CPU_FREQ_GOV_ONDEMAND=y
++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
++CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
++CONFIG_CPUFREQ_DT=y
++CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=y
++CONFIG_ARM_RASPBERRYPI_CPUFREQ=y
++CONFIG_CPU_IDLE=y
++CONFIG_CPU_IDLE_GOV_LADDER=y
++CONFIG_ARM_CPUIDLE=y
++CONFIG_ARM_PSCI_CPUIDLE=y
++CONFIG_VFP=y
++CONFIG_NEON=y
++CONFIG_KERNEL_MODE_NEON=y
++# CONFIG_SUSPEND is not set
++CONFIG_PM=y
++CONFIG_APM_EMULATION=y
++CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
++CONFIG_JUMP_LABEL=y
++# CONFIG_STACKPROTECTOR is not set
++CONFIG_MODULES=y
++CONFIG_BLK_DEV_THROTTLING=y
++CONFIG_BLK_WBT=y
++CONFIG_BLK_CGROUP_IOLATENCY=y
++CONFIG_BLK_CGROUP_IOCOST=y
++# CONFIG_MQ_IOSCHED_KYBER is not set
++CONFIG_CMA=y
++CONFIG_CMA_DEBUGFS=y
++CONFIG_CMA_AREAS=7
++CONFIG_NET=y
++CONFIG_PACKET=y
++CONFIG_PACKET_DIAG=y
++CONFIG_UNIX=y
++CONFIG_UNIX_DIAG=y
++CONFIG_NET_KEY=y
++CONFIG_INET=y
++CONFIG_IP_MULTICAST=y
++CONFIG_IP_ADVANCED_ROUTER=y
++CONFIG_IP_MULTIPLE_TABLES=y
++CONFIG_IP_ROUTE_MULTIPATH=y
++CONFIG_IP_ROUTE_VERBOSE=y
++CONFIG_IP_MROUTE=y
++CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
++CONFIG_SYN_COOKIES=y
++CONFIG_INET_UDP_DIAG=y
++CONFIG_INET_RAW_DIAG=y
++CONFIG_INET_DIAG_DESTROY=y
++CONFIG_IPV6_ROUTER_PREF=y
++CONFIG_IPV6_ROUTE_INFO=y
++CONFIG_IPV6_OPTIMISTIC_DAD=y
++CONFIG_IPV6_MIP6=y
++# CONFIG_IPV6_SIT is not set
++CONFIG_IPV6_MULTIPLE_TABLES=y
++CONFIG_IPV6_SUBTREES=y
++CONFIG_IPV6_MROUTE=y
++CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
++CONFIG_NETFILTER=y
++CONFIG_BRIDGE_NETFILTER=y
++CONFIG_NETFILTER_NETLINK_ACCT=y
++CONFIG_NETFILTER_NETLINK_QUEUE=y
++CONFIG_NETFILTER_NETLINK_LOG=y
++CONFIG_NF_CONNTRACK=y
++CONFIG_NF_CONNTRACK_MARK=y
++CONFIG_NF_CONNTRACK_FTP=y
++CONFIG_NF_CONNTRACK_H323=y
++CONFIG_NF_CONNTRACK_IRC=y
++CONFIG_NF_CONNTRACK_NETBIOS_NS=y
++CONFIG_NF_CONNTRACK_SNMP=y
++CONFIG_NF_CONNTRACK_PPTP=y
++CONFIG_NF_CONNTRACK_SIP=y
++CONFIG_NF_CONNTRACK_TFTP=y
++CONFIG_NF_CT_NETLINK=y
++CONFIG_NETFILTER_NETLINK_GLUE_CT=y
++CONFIG_NF_TABLES=y
++CONFIG_NF_TABLES_INET=y
++CONFIG_NF_TABLES_NETDEV=y
++CONFIG_NFT_NUMGEN=y
++CONFIG_NFT_CT=y
++CONFIG_NFT_CONNLIMIT=y
++CONFIG_NFT_LOG=y
++CONFIG_NFT_LIMIT=y
++CONFIG_NFT_MASQ=y
++CONFIG_NFT_REDIR=y
++CONFIG_NFT_NAT=y
++CONFIG_NFT_TUNNEL=y
++CONFIG_NFT_QUEUE=y
++CONFIG_NFT_QUOTA=y
++CONFIG_NFT_REJECT=y
++CONFIG_NFT_HASH=y
++CONFIG_NFT_FIB_INET=y
++CONFIG_NFT_SOCKET=y
++CONFIG_NFT_OSF=y
++CONFIG_NFT_TPROXY=y
++CONFIG_NFT_DUP_NETDEV=y
++CONFIG_NFT_FWD_NETDEV=y
++CONFIG_NFT_FIB_NETDEV=y
++CONFIG_NFT_REJECT_NETDEV=y
++CONFIG_NF_FLOW_TABLE_INET=y
++CONFIG_NF_FLOW_TABLE=y
++CONFIG_IP_SET=y
++CONFIG_IP_SET_BITMAP_IP=y
++CONFIG_IP_SET_BITMAP_IPMAC=y
++CONFIG_IP_SET_BITMAP_PORT=y
++CONFIG_IP_SET_HASH_IP=y
++CONFIG_IP_SET_HASH_IPMARK=y
++CONFIG_IP_SET_HASH_IPPORT=y
++CONFIG_IP_SET_HASH_IPPORTIP=y
++CONFIG_IP_SET_HASH_IPPORTNET=y
++CONFIG_IP_SET_HASH_IPMAC=y
++CONFIG_IP_SET_HASH_MAC=y
++CONFIG_IP_SET_HASH_NETPORTNET=y
++CONFIG_IP_SET_HASH_NET=y
++CONFIG_IP_SET_HASH_NETNET=y
++CONFIG_IP_SET_HASH_NETPORT=y
++CONFIG_IP_SET_HASH_NETIFACE=y
++CONFIG_IP_SET_LIST_SET=y
++CONFIG_NFT_DUP_IPV4=y
++CONFIG_NFT_FIB_IPV4=y
++CONFIG_NF_TABLES_ARP=y
++CONFIG_NF_LOG_ARP=y
++CONFIG_NF_LOG_IPV4=y
++# CONFIG_NF_NAT_SNMP_BASIC is not set
++CONFIG_NFT_DUP_IPV6=y
++CONFIG_NFT_FIB_IPV6=y
++CONFIG_NF_LOG_IPV6=y
++CONFIG_NF_TABLES_BRIDGE=y
++CONFIG_NFT_BRIDGE_REJECT=y
++CONFIG_L2TP=y
++CONFIG_L2TP_V3=y
++CONFIG_L2TP_IP=y
++CONFIG_BRIDGE=y
++CONFIG_BRIDGE_VLAN_FILTERING=y
++CONFIG_BRIDGE_MRP=y
++CONFIG_BRIDGE_CFM=y
++CONFIG_VLAN_8021Q=y
++CONFIG_VLAN_8021Q_GVRP=y
++CONFIG_VLAN_8021Q_MVRP=y
++CONFIG_NET_SCHED=y
++CONFIG_NET_SCH_HTB=y
++CONFIG_NET_SCH_PRIO=y
++CONFIG_NET_SCH_SFQ=y
++CONFIG_NET_SCH_CODEL=y
++CONFIG_NET_SCH_FQ_CODEL=y
++CONFIG_NET_CLS_BASIC=y
++CONFIG_NET_CLS_ROUTE4=y
++CONFIG_NET_CLS_FW=y
++CONFIG_NET_CLS_U32=y
++CONFIG_CLS_U32_PERF=y
++CONFIG_CLS_U32_MARK=y
++CONFIG_NET_CLS_FLOW=y
++CONFIG_NET_CLS_CGROUP=y
++CONFIG_NET_CLS_BPF=y
++CONFIG_NET_CLS_MATCHALL=y
++CONFIG_NET_CLS_ACT=y
++CONFIG_NET_ACT_POLICE=y
++CONFIG_NET_ACT_GACT=y
++CONFIG_NET_ACT_VLAN=y
++CONFIG_NET_ACT_CONNMARK=y
++CONFIG_NET_ACT_CTINFO=y
++CONFIG_NET_TC_SKB_EXT=y
++CONFIG_BT=y
++CONFIG_BT_RFCOMM=y
++CONFIG_BT_RFCOMM_TTY=y
++CONFIG_BT_BNEP=y
++CONFIG_BT_BNEP_MC_FILTER=y
++CONFIG_BT_BNEP_PROTO_FILTER=y
++CONFIG_BT_HIDP=y
++CONFIG_BT_LEDS=y
++CONFIG_BT_HCIBTSDIO=y
++CONFIG_BT_HCIUART=y
++CONFIG_BT_HCIUART_BCM=y
++CONFIG_CFG80211=y
++CONFIG_CFG80211_DEBUGFS=y
++CONFIG_MAC80211=y
++CONFIG_MAC80211_LEDS=y
++CONFIG_RFKILL=y
++CONFIG_RFKILL_GPIO=y
++CONFIG_NFC=y
++CONFIG_NFC_DIGITAL=y
++CONFIG_NFC_NCI=y
++CONFIG_NFC_NXP_NCI=y
++CONFIG_NFC_NXP_NCI_I2C=y
++CONFIG_PAGE_POOL_STATS=y
++CONFIG_UEVENT_HELPER=y
++CONFIG_DEVTMPFS=y
++CONFIG_DEVTMPFS_MOUNT=y
++#CONFIG_EXTRA_FIRMWARE="regulatory.db regulatory.db.p7s edid/asus.bin"
++#CONFIG_EXTRA_FIRMWARE_DIR="/workspace/megous.com/orangepi-pc/firmware"
++CONFIG_RASPBERRYPI_FIRMWARE=y
++CONFIG_GNSS=y
++CONFIG_GNSS_SIRF_SERIAL=y
++CONFIG_GNSS_UBX_SERIAL=y
++CONFIG_OF_OVERLAY=y
++CONFIG_ZRAM=y
++CONFIG_ZRAM_WRITEBACK=y
++CONFIG_ZRAM_MEMORY_TRACKING=y
++CONFIG_BLK_DEV_LOOP=y
++CONFIG_BLK_DEV_NBD=y
++CONFIG_SCSI=y
++CONFIG_BLK_DEV_SD=y
++# CONFIG_SCSI_LOWLEVEL is not set
++CONFIG_MD=y
++CONFIG_BLK_DEV_DM=y
++CONFIG_DM_CRYPT=y
++CONFIG_DM_INIT=y
++CONFIG_DM_INTEGRITY=y
++CONFIG_NETDEVICES=y
++CONFIG_WIREGUARD=y
++CONFIG_TUN=y
++CONFIG_VETH=y
++# CONFIG_NET_VENDOR_ALACRITECH is not set
++# CONFIG_NET_VENDOR_ALLWINNER is not set
++# CONFIG_NET_VENDOR_AMAZON is not set
++# CONFIG_NET_VENDOR_AQUANTIA is not set
++# CONFIG_NET_VENDOR_ARC is not set
++# CONFIG_NET_VENDOR_BROADCOM is not set
++# CONFIG_NET_VENDOR_CADENCE is not set
++# CONFIG_NET_VENDOR_CAVIUM is not set
++# CONFIG_NET_VENDOR_CIRRUS is not set
++# CONFIG_NET_VENDOR_CORTINA is not set
++# CONFIG_NET_VENDOR_EZCHIP is not set
++# CONFIG_NET_VENDOR_FARADAY is not set
++# CONFIG_NET_VENDOR_GOOGLE is not set
++# CONFIG_NET_VENDOR_HISILICON is not set
++# CONFIG_NET_VENDOR_HUAWEI is not set
++# CONFIG_NET_VENDOR_INTEL is not set
++# CONFIG_NET_VENDOR_MARVELL is not set
++# CONFIG_NET_VENDOR_MELLANOX is not set
++# CONFIG_NET_VENDOR_MICREL is not set
++# CONFIG_NET_VENDOR_MICROCHIP is not set
++# CONFIG_NET_VENDOR_MICROSEMI is not set
++# CONFIG_NET_VENDOR_NI is not set
++# CONFIG_NET_VENDOR_NATSEMI is not set
++# CONFIG_NET_VENDOR_NETRONOME is not set
++# CONFIG_NET_VENDOR_PENSANDO is not set
++# CONFIG_NET_VENDOR_QUALCOMM is not set
++# CONFIG_NET_VENDOR_RENESAS is not set
++# CONFIG_NET_VENDOR_ROCKER is not set
++# CONFIG_NET_VENDOR_SAMSUNG is not set
++# CONFIG_NET_VENDOR_SEEQ is not set
++# CONFIG_NET_VENDOR_SOLARFLARE is not set
++# CONFIG_NET_VENDOR_SMSC is not set
++# CONFIG_NET_VENDOR_SOCIONEXT is not set
++CONFIG_STMMAC_ETH=y
++# CONFIG_NET_VENDOR_SYNOPSYS is not set
++# CONFIG_NET_VENDOR_VIA is not set
++# CONFIG_NET_VENDOR_WIZNET is not set
++# CONFIG_NET_VENDOR_XILINX is not set
++CONFIG_LED_TRIGGER_PHY=y
++CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y
++CONFIG_PPP=y
++CONFIG_PPP_BSDCOMP=y
++CONFIG_PPP_DEFLATE=y
++CONFIG_PPP_FILTER=y
++CONFIG_PPP_MPPE=y
++CONFIG_PPPOL2TP=y
++CONFIG_PPP_ASYNC=y
++CONFIG_PPP_SYNC_TTY=y
++CONFIG_USB_RTL8152=y
++CONFIG_USB_USBNET=y
++# CONFIG_USB_NET_AX8817X is not set
++# CONFIG_USB_NET_AX88179_178A is not set
++CONFIG_USB_NET_CDC_EEM=y
++# CONFIG_USB_NET_CDC_NCM is not set
++CONFIG_USB_NET_SMSC95XX=y
++# CONFIG_USB_NET_NET1080 is not set
++# CONFIG_USB_NET_CDC_SUBSET is not set
++# CONFIG_USB_NET_ZAURUS is not set
++# CONFIG_WLAN_VENDOR_ADMTEK is not set
++# CONFIG_WLAN_VENDOR_ATH is not set
++# CONFIG_WLAN_VENDOR_ATMEL is not set
++CONFIG_BRCMFMAC=y
++# CONFIG_WLAN_VENDOR_INTEL is not set
++# CONFIG_WLAN_VENDOR_INTERSIL is not set
++# CONFIG_WLAN_VENDOR_MARVELL is not set
++# CONFIG_WLAN_VENDOR_MEDIATEK is not set
++# CONFIG_WLAN_VENDOR_MICROCHIP is not set
++CONFIG_RT2X00=y
++CONFIG_RT2800USB=y
++# CONFIG_RT2800USB_RT35XX is not set
++CONFIG_RT2800USB_RT53XX=y
++# CONFIG_WLAN_VENDOR_REALTEK is not set
++# CONFIG_WLAN_VENDOR_RSI is not set
++# CONFIG_WLAN_VENDOR_ST is not set
++# CONFIG_WLAN_VENDOR_TI is not set
++# CONFIG_WLAN_VENDOR_ZYDAS is not set
++# CONFIG_WLAN_VENDOR_QUANTENNA is not set
++CONFIG_INPUT_MOUSEDEV=y
++CONFIG_INPUT_MOUSEDEV_PSAUX=y
++CONFIG_INPUT_EVDEV=y
++CONFIG_KEYBOARD_ADC=y
++# CONFIG_KEYBOARD_ATKBD is not set
++CONFIG_KEYBOARD_GPIO=y
++CONFIG_KEYBOARD_GPIO_POLLED=y
++CONFIG_KEYBOARD_SUN4I_LRADC=y
++# CONFIG_INPUT_MOUSE is not set
++CONFIG_INPUT_TOUCHSCREEN=y
++CONFIG_TOUCHSCREEN_EDT_FT5X06=y
++CONFIG_INPUT_MISC=y
++CONFIG_INPUT_GPIO_VIBRA=y
++CONFIG_INPUT_AXP20X_PEK=y
++# CONFIG_SERIO is not set
++# CONFIG_LEGACY_PTYS is not set
++CONFIG_SERIAL_8250=y
++# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
++CONFIG_SERIAL_8250_CONSOLE=y
++CONFIG_SERIAL_8250_NR_UARTS=8
++CONFIG_SERIAL_8250_RUNTIME_UARTS=8
++CONFIG_SERIAL_8250_EXTENDED=y
++CONFIG_SERIAL_8250_SHARE_IRQ=y
++CONFIG_SERIAL_8250_BCM2835AUX=y
++CONFIG_SERIAL_8250_DW=y
++CONFIG_SERIAL_OF_PLATFORM=y
++CONFIG_SERIAL_AMBA_PL011=y
++CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
++CONFIG_SERIAL_DEV_BUS=y
++CONFIG_HW_RANDOM=y
++# CONFIG_HW_RANDOM_IPROC_RNG200 is not set
++CONFIG_I2C_CHARDEV=y
++CONFIG_I2C_MUX=y
++CONFIG_I2C_BCM2835=y
++CONFIG_I2C_GPIO=y
++CONFIG_I2C_MV64XXX=y
++CONFIG_I2C_SUN6I_P2WI=y
++CONFIG_SPI=y
++CONFIG_SPI_BCM2835=y
++CONFIG_SPI_BCM2835AUX=y
++CONFIG_SPI_SUN4I=y
++CONFIG_SPI_SUN6I=y
++CONFIG_SPI_SPIDEV=y
++CONFIG_PINCTRL_AXP209=y
++CONFIG_POWER_RESET=y
++CONFIG_POWER_RESET_GPIO=y
++CONFIG_POWER_RESET_GPIO_RESTART=y
++CONFIG_POWER_SUPPLY=y
++CONFIG_CHARGER_AXP20X=y
++CONFIG_BATTERY_AXP20X=y
++CONFIG_AXP20X_POWER=y
++CONFIG_SENSORS_RASPBERRYPI_HWMON=y
++CONFIG_THERMAL=y
++CONFIG_THERMAL_STATISTICS=y
++CONFIG_THERMAL_GOV_FAIR_SHARE=y
++CONFIG_THERMAL_GOV_BANG_BANG=y
++CONFIG_CPU_THERMAL=y
++CONFIG_SUN8I_THERMAL=y
++CONFIG_BCM2835_THERMAL=y
++CONFIG_WATCHDOG=y
++CONFIG_SUNXI_WATCHDOG=y
++CONFIG_BCM2835_WDT=y
++CONFIG_MFD_SUN4I_GPADC=y
++CONFIG_MFD_AXP20X_I2C=y
++CONFIG_MFD_AXP20X_RSB=y
++CONFIG_REGULATOR=y
++CONFIG_REGULATOR_FIXED_VOLTAGE=y
++CONFIG_REGULATOR_USERSPACE_CONSUMER=y
++CONFIG_REGULATOR_AXP20X=y
++CONFIG_REGULATOR_GPIO=y
++CONFIG_REGULATOR_PWM=y
++CONFIG_REGULATOR_SY8106A=y
++CONFIG_RC_CORE=y
++CONFIG_BPF_LIRC_MODE2=y
++CONFIG_LIRC=y
++CONFIG_RC_DECODERS=y
++CONFIG_IR_JVC_DECODER=y
++CONFIG_IR_MCE_KBD_DECODER=y
++CONFIG_IR_NEC_DECODER=y
++CONFIG_IR_RC5_DECODER=y
++CONFIG_IR_RC6_DECODER=y
++CONFIG_IR_SANYO_DECODER=y
++CONFIG_IR_SHARP_DECODER=y
++CONFIG_IR_SONY_DECODER=y
++CONFIG_IR_XMP_DECODER=y
++CONFIG_RC_DEVICES=y
++CONFIG_IR_GPIO_CIR=y
++CONFIG_IR_SUNXI=y
++CONFIG_MEDIA_CEC_RC=y
++CONFIG_MEDIA_CEC_SUPPORT=y
++CONFIG_MEDIA_SUPPORT=y
++# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
++CONFIG_MEDIA_CAMERA_SUPPORT=y
++CONFIG_MEDIA_PLATFORM_SUPPORT=y
++CONFIG_MEDIA_USB_SUPPORT=y
++CONFIG_USB_VIDEO_CLASS=y
++CONFIG_V4L_PLATFORM_DRIVERS=y
++CONFIG_V4L_MEM2MEM_DRIVERS=y
++CONFIG_VIDEO_MEM2MEM_DEINTERLACE=y
++CONFIG_VIDEO_SUN6I_CSI=y
++CONFIG_VIDEO_SUN8I_DEINTERLACE=y
++CONFIG_VIDEO_SUN8I_ROTATE=y
++# CONFIG_VIDEO_IR_I2C is not set
++CONFIG_DRM=y
++CONFIG_DRM_LOAD_EDID_FIRMWARE=y
++CONFIG_DRM_SUN4I=y
++CONFIG_DRM_SUN4I_HDMI_CEC=y
++# CONFIG_DRM_SUN6I_DSI is not set
++CONFIG_DRM_PANEL_LVDS=y
++CONFIG_DRM_DW_HDMI_AHB_AUDIO=y
++CONFIG_DRM_DW_HDMI_I2S_AUDIO=y
++CONFIG_DRM_DW_HDMI_CEC=y
++CONFIG_DRM_VC4=y
++CONFIG_DRM_VC4_HDMI_CEC=y
++CONFIG_DRM_LIMA=y
++CONFIG_FB=y
++CONFIG_LCD_CLASS_DEVICE=y
++CONFIG_BACKLIGHT_CLASS_DEVICE=y
++CONFIG_BACKLIGHT_PWM=y
++CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER=y
++CONFIG_LOGO=y
++# CONFIG_LOGO_LINUX_MONO is not set
++# CONFIG_LOGO_LINUX_VGA16 is not set
++CONFIG_SOUND=y
++CONFIG_SND=y
++CONFIG_SND_OSSEMUL=y
++CONFIG_SND_MIXER_OSS=y
++CONFIG_SND_PCM_OSS=y
++CONFIG_SND_HRTIMER=y
++CONFIG_SND_SEQUENCER=y
++CONFIG_SND_SEQUENCER_OSS=y
++CONFIG_SND_DUMMY=y
++CONFIG_SND_ALOOP=y
++# CONFIG_SND_SPI is not set
++CONFIG_SND_USB_AUDIO=y
++CONFIG_SND_SOC=y
++CONFIG_SND_BCM2835_SOC_I2S=y
++CONFIG_SND_SUN4I_CODEC=y
++CONFIG_SND_SUN8I_CODEC=y
++CONFIG_SND_SUN8I_CODEC_ANALOG=y
++CONFIG_SND_SUN4I_I2S=y
++CONFIG_SND_SUN4I_SPDIF=y
++CONFIG_SND_SOC_SPDIF=y
++CONFIG_SND_SIMPLE_CARD=y
++CONFIG_SND_AUDIO_GRAPH_CARD=y
++CONFIG_HIDRAW=y
++# CONFIG_HID_A4TECH is not set
++# CONFIG_HID_APPLE is not set
++# CONFIG_HID_BELKIN is not set
++# CONFIG_HID_CHERRY is not set
++# CONFIG_HID_CHICONY is not set
++# CONFIG_HID_CYPRESS is not set
++# CONFIG_HID_EZKEY is not set
++# CONFIG_HID_ITE is not set
++# CONFIG_HID_KENSINGTON is not set
++# CONFIG_HID_LOGITECH is not set
++# CONFIG_HID_REDRAGON is not set
++# CONFIG_HID_MICROSOFT is not set
++# CONFIG_HID_MONTEREY is not set
++CONFIG_USB_HIDDEV=y
++CONFIG_USB_LED_TRIG=y
++CONFIG_USB=y
++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
++CONFIG_USB_OTG=y
++CONFIG_USB_OTG_FSM=y
++CONFIG_USB_LEDS_TRIGGER_USBPORT=y
++CONFIG_USB_EHCI_HCD=y
++CONFIG_USB_EHCI_HCD_PLATFORM=y
++CONFIG_USB_OHCI_HCD=y
++CONFIG_USB_OHCI_HCD_PLATFORM=y
++CONFIG_USB_ACM=y
++CONFIG_USB_PRINTER=y
++CONFIG_USB_WDM=y
++CONFIG_USB_STORAGE=y
++CONFIG_USB_UAS=y
++CONFIG_USBIP_CORE=y
++CONFIG_USBIP_VHCI_HCD=y
++CONFIG_USBIP_HOST=y
++CONFIG_USBIP_VUDC=y
++CONFIG_USB_MUSB_HDRC=y
++CONFIG_USB_MUSB_SUNXI=y
++CONFIG_MUSB_PIO_ONLY=y
++CONFIG_USB_DWC2=y
++CONFIG_USB_SERIAL=y
++CONFIG_USB_SERIAL_CH341=y
++CONFIG_USB_SERIAL_CP210X=y
++CONFIG_USB_SERIAL_FTDI_SIO=y
++CONFIG_USB_SERIAL_PL2303=y
++CONFIG_USB_SERIAL_OPTION=y
++CONFIG_NOP_USB_XCEIV=y
++CONFIG_USB_GADGET=y
++CONFIG_U_SERIAL_CONSOLE=y
++CONFIG_USB_CONFIGFS=y
++CONFIG_USB_CONFIGFS_SERIAL=y
++CONFIG_USB_CONFIGFS_ACM=y
++CONFIG_USB_CONFIGFS_OBEX=y
++CONFIG_USB_CONFIGFS_NCM=y
++CONFIG_USB_CONFIGFS_ECM=y
++CONFIG_USB_CONFIGFS_ECM_SUBSET=y
++CONFIG_USB_CONFIGFS_RNDIS=y
++CONFIG_USB_CONFIGFS_EEM=y
++CONFIG_USB_CONFIGFS_MASS_STORAGE=y
++CONFIG_USB_CONFIGFS_F_LB_SS=y
++CONFIG_USB_CONFIGFS_F_FS=y
++CONFIG_USB_CONFIGFS_F_UAC1=y
++CONFIG_USB_CONFIGFS_F_UAC2=y
++CONFIG_USB_CONFIGFS_F_MIDI=y
++CONFIG_USB_CONFIGFS_F_HID=y
++CONFIG_USB_CONFIGFS_F_PRINTER=y
++CONFIG_USB_CDC_COMPOSITE=y
++CONFIG_MMC=y
++CONFIG_MMC_SUNXI=y
++CONFIG_MMC_BCM2835=y
++CONFIG_NEW_LEDS=y
++CONFIG_LEDS_CLASS=y
++CONFIG_LEDS_GPIO=y
++CONFIG_LEDS_TRIGGER_TIMER=y
++CONFIG_LEDS_TRIGGER_ONESHOT=y
++CONFIG_LEDS_TRIGGER_HEARTBEAT=y
++CONFIG_LEDS_TRIGGER_CPU=y
++CONFIG_LEDS_TRIGGER_ACTIVITY=y
++CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
++CONFIG_LEDS_TRIGGER_PANIC=y
++CONFIG_LEDS_TRIGGER_NETDEV=y
++CONFIG_LEDS_TRIGGER_PATTERN=y
++CONFIG_RTC_CLASS=y
++# CONFIG_RTC_INTF_SYSFS is not set
++# CONFIG_RTC_INTF_PROC is not set
++CONFIG_RTC_DRV_AC100=y
++CONFIG_RTC_DRV_SUNXI=y
++CONFIG_DMADEVICES=y
++CONFIG_DMA_BCM2835=y
++CONFIG_DMA_SUN6I=y
++CONFIG_DMABUF_HEAPS=y
++CONFIG_DMABUF_HEAPS_SYSTEM=y
++CONFIG_DMABUF_HEAPS_CMA=y
++# CONFIG_VIRTIO_MENU is not set
++# CONFIG_VHOST_MENU is not set
++CONFIG_STAGING=y
++CONFIG_STAGING_MEDIA=y
++CONFIG_VIDEO_SUNXI=y
++CONFIG_VIDEO_SUNXI_CEDRUS=y
++# CONFIG_BCM_VIDEOCORE is not set
++CONFIG_CLK_RASPBERRYPI=y
++# CONFIG_CLK_SUNXI_CLOCKS is not set
++# CONFIG_CLK_SUNXI_PRCM_SUN9I is not set
++# CONFIG_SUN4I_A10_CCU is not set
++# CONFIG_SUN5I_CCU is not set
++# CONFIG_SUN6I_A31_CCU is not set
++# CONFIG_SUN8I_A23_CCU is not set
++# CONFIG_SUN8I_A33_CCU is not set
++# CONFIG_SUN8I_V3S_CCU is not set
++# CONFIG_SUN8I_R40_CCU is not set
++CONFIG_MAILBOX=y
++CONFIG_BCM2835_MBOX=y
++# CONFIG_SUN6I_MSGBOX is not set
++# CONFIG_IOMMU_SUPPORT is not set
++CONFIG_RASPBERRYPI_POWER=y
++CONFIG_DEVFREQ_GOV_PERFORMANCE=y
++CONFIG_DEVFREQ_GOV_POWERSAVE=y
++CONFIG_DEVFREQ_GOV_USERSPACE=y
++CONFIG_DEVFREQ_GOV_PASSIVE=y
++CONFIG_PM_DEVFREQ_EVENT=y
++CONFIG_IIO=y
++CONFIG_IIO_CONFIGFS=y
++CONFIG_BMA180=y
++CONFIG_AXP20X_ADC=y
++CONFIG_LTR501=y
++CONFIG_AK8975=y
++CONFIG_PWM=y
++CONFIG_PWM_BCM2835=y
++CONFIG_PWM_SUN4I=y
++CONFIG_RESET_RASPBERRYPI=y
++CONFIG_PHY_SUN4I_USB=y
++CONFIG_ARM_CCI_PMU=y
++# CONFIG_ARM_CCI5xx_PMU is not set
++CONFIG_NVMEM_SUNXI_SID=y
++CONFIG_VALIDATE_FS_PARSER=y
++CONFIG_EXT4_FS=y
++CONFIG_EXT4_FS_POSIX_ACL=y
++CONFIG_XFS_FS=y
++CONFIG_XFS_POSIX_ACL=y
++CONFIG_F2FS_FS=y
++CONFIG_F2FS_FS_SECURITY=y
++CONFIG_F2FS_CHECK_FS=y
++CONFIG_F2FS_FS_COMPRESSION=y
++CONFIG_FS_ENCRYPTION=y
++CONFIG_FANOTIFY=y
++CONFIG_AUTOFS_FS=y
++CONFIG_FUSE_FS=y
++CONFIG_CUSE=y
++CONFIG_OVERLAY_FS=y
++CONFIG_OVERLAY_FS_INDEX=y
++CONFIG_OVERLAY_FS_METACOPY=y
++CONFIG_VFAT_FS=y
++CONFIG_PROC_CHILDREN=y
++CONFIG_TMPFS=y
++CONFIG_TMPFS_POSIX_ACL=y
++CONFIG_ECRYPT_FS=y
++CONFIG_ECRYPT_FS_MESSAGING=y
++CONFIG_SQUASHFS=y
++CONFIG_SQUASHFS_FILE_DIRECT=y
++CONFIG_SQUASHFS_XATTR=y
++CONFIG_SQUASHFS_LZ4=y
++CONFIG_SQUASHFS_LZO=y
++CONFIG_SQUASHFS_XZ=y
++CONFIG_SQUASHFS_ZSTD=y
++CONFIG_NFS_FS=y
++# CONFIG_NFS_V3 is not set
++CONFIG_NFS_V4=y
++CONFIG_NFS_V4_1=y
++CONFIG_NFS_V4_2=y
++CONFIG_NFS_FSCACHE=y
++# CONFIG_NFS_V4_2_READ_PLUS is not set
++CONFIG_NFSD=y
++CONFIG_NFSD_V3_ACL=y
++CONFIG_NFSD_V4=y
++# CONFIG_NFSD_LEGACY_CLIENT_TRACKING is not set
++CONFIG_CIFS=y
++# CONFIG_CIFS_STATS2 is not set
++CONFIG_CIFS_XATTR=y
++CONFIG_CIFS_POSIX=y
++# CONFIG_CIFS_DEBUG is not set
++CONFIG_NLS_CODEPAGE_437=y
++CONFIG_NLS_CODEPAGE_852=y
++CONFIG_NLS_ISO8859_1=y
++CONFIG_NLS_ISO8859_2=y
++CONFIG_NLS_UTF8=y
++CONFIG_PERSISTENT_KEYRINGS=y
++CONFIG_ENCRYPTED_KEYS=y
++CONFIG_LSM="yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor"
++CONFIG_INIT_STACK_NONE=y
++CONFIG_CRYPTO_PCRYPT=y
++CONFIG_CRYPTO_CURVE25519=y
++CONFIG_CRYPTO_AES_TI=y
++CONFIG_CRYPTO_ARC4=y
++CONFIG_CRYPTO_CHACHA20POLY1305=y
++CONFIG_CRYPTO_SEQIV=y
++CONFIG_CRYPTO_ECHAINIV=y
++CONFIG_CRYPTO_BLAKE2B=y
++CONFIG_CRYPTO_MD4=y
++CONFIG_CRYPTO_DEFLATE=y
++CONFIG_CRYPTO_LZO=y
++CONFIG_CRYPTO_LZ4=y
++CONFIG_CRYPTO_ZSTD=y
++CONFIG_CRYPTO_ANSI_CPRNG=y
++CONFIG_CRYPTO_USER_API_HASH=y
++CONFIG_CRYPTO_USER_API_SKCIPHER=y
++CONFIG_CRYPTO_USER_API_RNG=y
++CONFIG_CRYPTO_USER_API_AEAD=y
++CONFIG_CRYPTO_GHASH_ARM_CE=y
++CONFIG_CRYPTO_SHA1_ARM_NEON=y
++CONFIG_CRYPTO_SHA1_ARM_CE=y
++CONFIG_CRYPTO_SHA2_ARM_CE=y
++CONFIG_CRYPTO_SHA512_ARM=y
++CONFIG_CRYPTO_AES_ARM_BS=y
++CONFIG_CRYPTO_AES_ARM_CE=y
++CONFIG_CRYPTO_CRC32_ARM_CE=y
++CONFIG_CRYPTO_CRCT10DIF_ARM_CE=y
++CONFIG_CRYPTO_DEV_SUN4I_SS=y
++CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG=y
++CONFIG_CRYPTO_DEV_SUN8I_CE=y
++CONFIG_CRYPTO_DEV_SUN8I_SS=y
++CONFIG_PKCS8_PRIVATE_KEY_PARSER=y
++CONFIG_DMA_CMA=y
++CONFIG_CMA_SIZE_MBYTES=128
++CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15
++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
++CONFIG_DEBUG_KERNEL=y
++CONFIG_MAGIC_SYSRQ=y
++CONFIG_DEBUG_FS=y
++CONFIG_DETECT_HUNG_TASK=y
++CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y
++CONFIG_WQ_WATCHDOG=y
++# CONFIG_SCHED_DEBUG is not set
++# CONFIG_RCU_TRACE is not set
++# CONFIG_FTRACE is not set
++# CONFIG_RUNTIME_TESTING_MENU is not set
+diff --git a/arch/arm/configs/pocketbook_touch_lux_3_defconfig b/arch/arm/configs/pocketbook_touch_lux_3_defconfig
+new file mode 100644
+index 000000000000..a86ca9662199
+--- /dev/null
++++ b/arch/arm/configs/pocketbook_touch_lux_3_defconfig
+@@ -0,0 +1,416 @@
++CONFIG_KERNEL_LZ4=y
++CONFIG_SYSVIPC=y
++CONFIG_POSIX_MQUEUE=y
++CONFIG_HZ_PERIODIC=y
++CONFIG_NO_HZ=y
++CONFIG_HIGH_RES_TIMERS=y
++CONFIG_BPF_SYSCALL=y
++# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set
++CONFIG_BSD_PROCESS_ACCT=y
++CONFIG_BSD_PROCESS_ACCT_V3=y
++CONFIG_TASKSTATS=y
++CONFIG_TASK_DELAY_ACCT=y
++CONFIG_TASK_XACCT=y
++CONFIG_TASK_IO_ACCOUNTING=y
++CONFIG_MEMCG=y
++CONFIG_BLK_CGROUP=y
++CONFIG_RT_GROUP_SCHED=y
++CONFIG_CGROUP_PIDS=y
++CONFIG_CGROUP_DEVICE=y
++CONFIG_CGROUP_BPF=y
++CONFIG_USER_NS=y
++CONFIG_SCHED_AUTOGROUP=y
++# CONFIG_RD_BZIP2 is not set
++# CONFIG_RD_LZMA is not set
++# CONFIG_RD_XZ is not set
++# CONFIG_RD_LZO is not set
++CONFIG_BOOT_CONFIG=y
++CONFIG_PERF_EVENTS=y
++CONFIG_ARCH_SUNXI=y
++# CONFIG_MACH_SUN4I is not set
++# CONFIG_MACH_SUN6I is not set
++# CONFIG_MACH_SUN7I is not set
++# CONFIG_MACH_SUN8I is not set
++# CONFIG_MACH_SUN9I is not set
++CONFIG_ARM_ERRATA_430973=y
++CONFIG_ARM_ERRATA_814220=y
++CONFIG_HAVE_ARM_ARCH_TIMER=y
++CONFIG_ARM_PSCI=y
++CONFIG_HZ_1000=y
++# CONFIG_ARM_MODULE_PLTS is not set
++CONFIG_ARCH_FORCE_MAX_ORDER=11
++CONFIG_ZBOOT_ROM_TEXT=0
++CONFIG_ZBOOT_ROM_BSS=0
++CONFIG_CPU_FREQ=y
++CONFIG_CPU_FREQ_STAT=y
++CONFIG_CPU_FREQ_GOV_POWERSAVE=y
++CONFIG_CPU_FREQ_GOV_USERSPACE=y
++CONFIG_CPU_FREQ_GOV_ONDEMAND=y
++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
++CONFIG_CPUFREQ_DT=y
++CONFIG_CPU_IDLE=y
++CONFIG_CPU_IDLE_GOV_LADDER=y
++CONFIG_ARM_CPUIDLE=y
++CONFIG_VFP=y
++CONFIG_NEON=y
++CONFIG_KERNEL_MODE_NEON=y
++CONFIG_PM_WAKELOCKS=y
++CONFIG_PM_DEBUG=y
++CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
++CONFIG_JUMP_LABEL=y
++# CONFIG_STACKPROTECTOR is not set
++CONFIG_MODULES=y
++CONFIG_MODULE_FORCE_LOAD=y
++CONFIG_MODULE_UNLOAD=y
++CONFIG_MODVERSIONS=y
++CONFIG_BLK_DEV_INTEGRITY=y
++CONFIG_BLK_DEV_THROTTLING=y
++CONFIG_BLK_WBT=y
++CONFIG_BLK_CGROUP_IOLATENCY=y
++# CONFIG_MQ_IOSCHED_DEADLINE is not set
++# CONFIG_MQ_IOSCHED_KYBER is not set
++CONFIG_CMA=y
++CONFIG_CMA_DEBUGFS=y
++CONFIG_CMA_AREAS=7
++CONFIG_NET=y
++CONFIG_PACKET=y
++CONFIG_PACKET_DIAG=y
++CONFIG_UNIX=y
++CONFIG_UNIX_DIAG=y
++CONFIG_XFRM_USER=m
++CONFIG_XFRM_SUB_POLICY=y
++CONFIG_INET=y
++CONFIG_SYN_COOKIES=y
++# CONFIG_INET_DIAG is not set
++CONFIG_MPTCP=y
++CONFIG_NETFILTER=y
++CONFIG_NETFILTER_NETLINK_QUEUE=m
++CONFIG_NETFILTER_NETLINK_LOG=m
++CONFIG_NF_CONNTRACK=m
++CONFIG_NF_CONNTRACK_MARK=y
++# CONFIG_NF_CT_PROTO_DCCP is not set
++# CONFIG_NF_CT_PROTO_SCTP is not set
++# CONFIG_NF_CT_PROTO_UDPLITE is not set
++CONFIG_NF_CONNTRACK_FTP=m
++CONFIG_NF_CONNTRACK_H323=m
++CONFIG_NF_CONNTRACK_IRC=m
++CONFIG_NF_CONNTRACK_NETBIOS_NS=m
++CONFIG_NF_CONNTRACK_SNMP=m
++CONFIG_NF_CONNTRACK_PPTP=m
++CONFIG_NF_CONNTRACK_SIP=m
++CONFIG_NF_CONNTRACK_TFTP=m
++CONFIG_NF_CT_NETLINK=m
++CONFIG_NETFILTER_NETLINK_GLUE_CT=y
++CONFIG_NF_TABLES=m
++CONFIG_NF_TABLES_NETDEV=y
++CONFIG_NFT_NUMGEN=m
++CONFIG_NFT_CT=m
++CONFIG_NFT_CONNLIMIT=m
++CONFIG_NFT_LOG=m
++CONFIG_NFT_LIMIT=m
++CONFIG_NFT_MASQ=m
++CONFIG_NFT_REDIR=m
++CONFIG_NFT_NAT=m
++CONFIG_NFT_TUNNEL=m
++CONFIG_NFT_QUEUE=m
++CONFIG_NFT_QUOTA=m
++CONFIG_NFT_REJECT=m
++CONFIG_NFT_HASH=m
++CONFIG_NFT_SOCKET=m
++CONFIG_NFT_OSF=m
++CONFIG_NFT_DUP_NETDEV=m
++CONFIG_NFT_FWD_NETDEV=m
++CONFIG_NF_FLOW_TABLE_INET=m
++CONFIG_NF_FLOW_TABLE=m
++CONFIG_IP_SET=m
++CONFIG_IP_SET_BITMAP_IP=m
++CONFIG_IP_SET_BITMAP_IPMAC=m
++CONFIG_IP_SET_BITMAP_PORT=m
++CONFIG_IP_SET_HASH_IP=m
++CONFIG_IP_SET_HASH_IPMARK=m
++CONFIG_IP_SET_HASH_IPPORT=m
++CONFIG_IP_SET_HASH_IPPORTIP=m
++CONFIG_IP_SET_HASH_IPPORTNET=m
++CONFIG_IP_SET_HASH_IPMAC=m
++CONFIG_IP_SET_HASH_MAC=m
++CONFIG_IP_SET_HASH_NETPORTNET=m
++CONFIG_IP_SET_HASH_NET=m
++CONFIG_IP_SET_HASH_NETNET=m
++CONFIG_IP_SET_HASH_NETPORT=m
++CONFIG_IP_SET_HASH_NETIFACE=m
++CONFIG_IP_SET_LIST_SET=m
++CONFIG_NF_SOCKET_IPV4=y
++CONFIG_NF_TABLES_IPV4=y
++CONFIG_NFT_DUP_IPV4=m
++CONFIG_NFT_FIB_IPV4=m
++CONFIG_NF_TABLES_ARP=y
++CONFIG_NF_LOG_ARP=y
++CONFIG_NF_LOG_IPV4=y
++CONFIG_NF_REJECT_IPV4=y
++# CONFIG_NF_NAT_SNMP_BASIC is not set
++CONFIG_CFG80211=y
++CONFIG_CFG80211_DEBUGFS=y
++CONFIG_CFG80211_WEXT=y
++CONFIG_MAC80211=y
++CONFIG_MAC80211_LEDS=y
++CONFIG_MAC80211_DEBUGFS=y
++CONFIG_UEVENT_HELPER=y
++CONFIG_DEVTMPFS=y
++CONFIG_DEVTMPFS_MOUNT=y
++#CONFIG_EXTRA_FIRMWARE="regulatory.db regulatory.db.p7s rtlwifi/rtl8188eufw.bin"
++#CONFIG_EXTRA_FIRMWARE_DIR="/workspace/megous.com/orangepi-pc/firmware"
++# CONFIG_FW_CACHE is not set
++CONFIG_SUNXI_RSB=y
++CONFIG_MTD=y
++# CONFIG_MTD_OF_PARTS is not set
++CONFIG_MTD_BLOCK_RO=y
++CONFIG_MTD_SPI_NOR=m
++CONFIG_OF_OVERLAY=y
++CONFIG_ZRAM=y
++CONFIG_ZRAM_WRITEBACK=y
++CONFIG_ZRAM_MEMORY_TRACKING=y
++CONFIG_BLK_DEV_LOOP=y
++CONFIG_BLK_DEV_NBD=y
++CONFIG_SCSI=y
++CONFIG_BLK_DEV_SD=y
++# CONFIG_SCSI_LOWLEVEL is not set
++CONFIG_NETDEVICES=y
++CONFIG_WIREGUARD=m
++CONFIG_TUN=y
++# CONFIG_ETHERNET is not set
++# CONFIG_USB_NET_DRIVERS is not set
++# CONFIG_WLAN_VENDOR_ADMTEK is not set
++# CONFIG_WLAN_VENDOR_ATH is not set
++# CONFIG_WLAN_VENDOR_ATMEL is not set
++# CONFIG_WLAN_VENDOR_BROADCOM is not set
++# CONFIG_WLAN_VENDOR_INTEL is not set
++# CONFIG_WLAN_VENDOR_INTERSIL is not set
++# CONFIG_WLAN_VENDOR_MARVELL is not set
++# CONFIG_WLAN_VENDOR_MEDIATEK is not set
++# CONFIG_WLAN_VENDOR_MICROCHIP is not set
++# CONFIG_WLAN_VENDOR_PURELIFI is not set
++# CONFIG_WLAN_VENDOR_RALINK is not set
++# CONFIG_RTL_CARDS is not set
++CONFIG_RTL8XXXU=m
++# CONFIG_WLAN_VENDOR_RSI is not set
++# CONFIG_WLAN_VENDOR_SILABS is not set
++# CONFIG_WLAN_VENDOR_ST is not set
++# CONFIG_WLAN_VENDOR_TI is not set
++# CONFIG_WLAN_VENDOR_ZYDAS is not set
++# CONFIG_WLAN_VENDOR_QUANTENNA is not set
++CONFIG_INPUT_EVDEV=y
++# CONFIG_KEYBOARD_ATKBD is not set
++CONFIG_KEYBOARD_GPIO=y
++CONFIG_KEYBOARD_GPIO_POLLED=y
++CONFIG_KEYBOARD_SUN4I_LRADC=y
++# CONFIG_INPUT_MOUSE is not set
++CONFIG_INPUT_TOUCHSCREEN=y
++CONFIG_TOUCHSCREEN_CYTTSP4_CORE=m
++CONFIG_TOUCHSCREEN_CYTTSP4_I2C=m
++CONFIG_INPUT_MISC=y
++CONFIG_INPUT_AXP20X_PEK=y
++# CONFIG_SERIO is not set
++# CONFIG_LEGACY_PTYS is not set
++CONFIG_SERIAL_8250=y
++# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
++# CONFIG_SERIAL_8250_16550A_VARIANTS is not set
++CONFIG_SERIAL_8250_CONSOLE=y
++CONFIG_SERIAL_8250_NR_UARTS=8
++CONFIG_SERIAL_8250_RUNTIME_UARTS=8
++CONFIG_SERIAL_8250_DW=y
++CONFIG_SERIAL_OF_PLATFORM=y
++CONFIG_SERIAL_DEV_BUS=y
++# CONFIG_HW_RANDOM is not set
++CONFIG_I2C_CHARDEV=y
++CONFIG_I2C_MUX=y
++CONFIG_I2C_GPIO=y
++CONFIG_I2C_MV64XXX=y
++CONFIG_SPI=y
++CONFIG_SPI_SUN4I=y
++CONFIG_SPI_SPIDEV=y
++CONFIG_PINCTRL_AXP209=y
++CONFIG_POWER_SUPPLY=y
++CONFIG_CHARGER_AXP20X=y
++CONFIG_BATTERY_AXP20X=y
++CONFIG_AXP20X_POWER=y
++CONFIG_SENSORS_NTC_THERMISTOR=y
++CONFIG_THERMAL=y
++CONFIG_THERMAL_STATISTICS=y
++CONFIG_THERMAL_GOV_FAIR_SHARE=y
++CONFIG_THERMAL_GOV_BANG_BANG=y
++CONFIG_CPU_THERMAL=y
++CONFIG_WATCHDOG=y
++CONFIG_SUNXI_WATCHDOG=y
++CONFIG_MFD_SUN4I_GPADC=y
++CONFIG_MFD_AXP20X_I2C=y
++CONFIG_MFD_SUN6I_PRCM=y
++CONFIG_REGULATOR=y
++CONFIG_REGULATOR_FIXED_VOLTAGE=y
++CONFIG_REGULATOR_USERSPACE_CONSUMER_OF=y
++CONFIG_REGULATOR_AXP20X=y
++CONFIG_REGULATOR_GPIO=y
++CONFIG_REGULATOR_TP65185X=y
++CONFIG_DRM=y
++CONFIG_FB=y
++CONFIG_FB_SUN5I_EINK=m
++CONFIG_LCD_CLASS_DEVICE=y
++CONFIG_BACKLIGHT_CLASS_DEVICE=y
++CONFIG_BACKLIGHT_PWM=y
++CONFIG_FRAMEBUFFER_CONSOLE=y
++CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
++# CONFIG_HID is not set
++# CONFIG_USB_HID is not set
++CONFIG_USB_LED_TRIG=y
++CONFIG_USB=m
++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
++CONFIG_USB_OTG=y
++CONFIG_USB_OTG_FSM=m
++CONFIG_USB_LEDS_TRIGGER_USBPORT=m
++CONFIG_USB_EHCI_HCD=m
++CONFIG_USB_EHCI_HCD_PLATFORM=m
++CONFIG_USB_OHCI_HCD=m
++CONFIG_USB_OHCI_HCD_PLATFORM=m
++CONFIG_USB_WDM=m
++CONFIG_USB_MUSB_HDRC=m
++CONFIG_USB_MUSB_SUNXI=m
++CONFIG_MUSB_PIO_ONLY=y
++CONFIG_NOP_USB_XCEIV=m
++CONFIG_USB_GADGET=m
++CONFIG_U_SERIAL_CONSOLE=y
++CONFIG_USB_CONFIGFS=m
++CONFIG_USB_CONFIGFS_SERIAL=y
++CONFIG_USB_CONFIGFS_ACM=y
++CONFIG_USB_CONFIGFS_OBEX=y
++CONFIG_USB_CONFIGFS_NCM=y
++CONFIG_USB_CONFIGFS_ECM=y
++CONFIG_USB_CONFIGFS_ECM_SUBSET=y
++CONFIG_USB_CONFIGFS_RNDIS=y
++CONFIG_USB_CONFIGFS_EEM=y
++CONFIG_USB_CONFIGFS_MASS_STORAGE=y
++CONFIG_USB_CONFIGFS_F_LB_SS=y
++CONFIG_USB_CONFIGFS_F_FS=y
++CONFIG_USB_CONFIGFS_F_HID=y
++CONFIG_USB_CONFIGFS_F_PRINTER=y
++CONFIG_USB_CDC_COMPOSITE=m
++CONFIG_MMC=y
++CONFIG_MMC_SUNXI=y
++CONFIG_NEW_LEDS=y
++CONFIG_LEDS_CLASS=y
++CONFIG_LEDS_GPIO=y
++CONFIG_LEDS_TRIGGER_TIMER=y
++CONFIG_LEDS_TRIGGER_ONESHOT=y
++CONFIG_LEDS_TRIGGER_HEARTBEAT=y
++CONFIG_LEDS_TRIGGER_CPU=y
++CONFIG_LEDS_TRIGGER_ACTIVITY=y
++CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
++CONFIG_LEDS_TRIGGER_PANIC=y
++CONFIG_LEDS_TRIGGER_NETDEV=y
++CONFIG_LEDS_TRIGGER_PATTERN=y
++CONFIG_RTC_CLASS=y
++# CONFIG_RTC_INTF_SYSFS is not set
++# CONFIG_RTC_INTF_PROC is not set
++CONFIG_RTC_DRV_PCF8563=y
++CONFIG_DMADEVICES=y
++# CONFIG_VIRTIO_MENU is not set
++# CONFIG_VHOST_MENU is not set
++CONFIG_STAGING=y
++# CONFIG_CLK_SUNXI_PRCM_SUN6I is not set
++# CONFIG_CLK_SUNXI_PRCM_SUN8I is not set
++# CONFIG_CLK_SUNXI_PRCM_SUN9I is not set
++# CONFIG_IOMMU_SUPPORT is not set
++CONFIG_PM_DEVFREQ=y
++CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
++CONFIG_DEVFREQ_GOV_PERFORMANCE=y
++CONFIG_DEVFREQ_GOV_POWERSAVE=y
++CONFIG_DEVFREQ_GOV_USERSPACE=y
++CONFIG_DEVFREQ_GOV_PASSIVE=y
++CONFIG_PM_DEVFREQ_EVENT=y
++CONFIG_IIO=y
++CONFIG_IIO_CONFIGFS=y
++CONFIG_BMA180=y
++CONFIG_AXP20X_ADC=y
++CONFIG_SUN4I_GPADC=m
++CONFIG_LTR501=y
++CONFIG_AK8975=y
++CONFIG_PWM=y
++CONFIG_PWM_SUN4I=y
++CONFIG_PHY_SUN4I_USB=y
++CONFIG_ARM_CCI_PMU=y
++# CONFIG_ARM_CCI5xx_PMU is not set
++CONFIG_NVMEM_SUNXI_SID=y
++CONFIG_VALIDATE_FS_PARSER=y
++CONFIG_EXT4_FS=y
++CONFIG_EXT4_FS_POSIX_ACL=y
++CONFIG_F2FS_FS=y
++CONFIG_F2FS_FS_SECURITY=y
++CONFIG_F2FS_CHECK_FS=y
++CONFIG_F2FS_FS_COMPRESSION=y
++CONFIG_FS_ENCRYPTION=y
++CONFIG_FANOTIFY=y
++CONFIG_AUTOFS_FS=y
++CONFIG_FUSE_FS=y
++CONFIG_CUSE=y
++CONFIG_VFAT_FS=y
++CONFIG_PROC_CHILDREN=y
++CONFIG_TMPFS=y
++CONFIG_TMPFS_POSIX_ACL=y
++# CONFIG_MISC_FILESYSTEMS is not set
++# CONFIG_NETWORK_FILESYSTEMS is not set
++CONFIG_NLS_CODEPAGE_437=y
++CONFIG_NLS_CODEPAGE_852=y
++CONFIG_NLS_ISO8859_1=y
++CONFIG_NLS_ISO8859_2=y
++CONFIG_NLS_UTF8=y
++CONFIG_KEYS_REQUEST_CACHE=y
++CONFIG_PERSISTENT_KEYRINGS=y
++CONFIG_BIG_KEYS=y
++CONFIG_ENCRYPTED_KEYS=y
++CONFIG_KEY_DH_OPERATIONS=y
++CONFIG_LSM="yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor"
++CONFIG_INIT_STACK_NONE=y
++CONFIG_CRYPTO_ECDH=y
++CONFIG_CRYPTO_CURVE25519=y
++CONFIG_CRYPTO_AES_TI=y
++CONFIG_CRYPTO_DES=y
++CONFIG_CRYPTO_ARC4=y
++CONFIG_CRYPTO_CHACHA20POLY1305=y
++CONFIG_CRYPTO_SEQIV=y
++CONFIG_CRYPTO_ECHAINIV=y
++CONFIG_CRYPTO_ESSIV=y
++CONFIG_CRYPTO_BLAKE2B=y
++CONFIG_CRYPTO_MD4=y
++CONFIG_CRYPTO_DEFLATE=y
++CONFIG_CRYPTO_LZO=y
++CONFIG_CRYPTO_LZ4=y
++CONFIG_CRYPTO_ZSTD=y
++CONFIG_CRYPTO_ANSI_CPRNG=y
++CONFIG_CRYPTO_USER_API_HASH=y
++CONFIG_CRYPTO_USER_API_SKCIPHER=y
++CONFIG_CRYPTO_USER_API_RNG=y
++CONFIG_CRYPTO_USER_API_AEAD=y
++CONFIG_CRYPTO_CURVE25519_NEON=y
++CONFIG_CRYPTO_GHASH_ARM_CE=y
++CONFIG_CRYPTO_POLY1305_ARM=y
++CONFIG_CRYPTO_SHA1_ARM_NEON=y
++CONFIG_CRYPTO_SHA1_ARM_CE=y
++CONFIG_CRYPTO_SHA2_ARM_CE=y
++CONFIG_CRYPTO_SHA512_ARM=y
++CONFIG_CRYPTO_AES_ARM_BS=y
++CONFIG_CRYPTO_AES_ARM_CE=y
++CONFIG_CRYPTO_CHACHA20_NEON=y
++CONFIG_CRYPTO_CRC32_ARM_CE=y
++CONFIG_CRYPTO_CRCT10DIF_ARM_CE=y
++CONFIG_CRYPTO_DEV_SUN4I_SS=y
++CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG=y
++CONFIG_PKCS8_PRIVATE_KEY_PARSER=y
++CONFIG_CRYPTO_LIB_CURVE25519=y
++CONFIG_CRYPTO_LIB_CHACHA20POLY1305=y
++CONFIG_CRC_CCITT=y
++CONFIG_CRC_ITU_T=y
++CONFIG_LIBCRC32C=y
++CONFIG_DMA_CMA=y
++CONFIG_CMA_SIZE_MBYTES=128
++CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15
++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
++CONFIG_DEBUG_FS=y
++# CONFIG_RUNTIME_TESTING_MENU is not set
+diff --git a/arch/arm/configs/tbs_a711_defconfig b/arch/arm/configs/tbs_a711_defconfig
+new file mode 100644
+index 000000000000..e29e2c7db357
+--- /dev/null
++++ b/arch/arm/configs/tbs_a711_defconfig
+@@ -0,0 +1,524 @@
++CONFIG_KERNEL_LZ4=y
++CONFIG_SYSVIPC=y
++CONFIG_POSIX_MQUEUE=y
++CONFIG_NO_HZ=y
++CONFIG_HIGH_RES_TIMERS=y
++CONFIG_BPF_SYSCALL=y
++# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set
++CONFIG_BSD_PROCESS_ACCT=y
++CONFIG_BSD_PROCESS_ACCT_V3=y
++CONFIG_TASKSTATS=y
++CONFIG_TASK_DELAY_ACCT=y
++CONFIG_TASK_XACCT=y
++CONFIG_TASK_IO_ACCOUNTING=y
++CONFIG_LOG_BUF_SHIFT=18
++CONFIG_MEMCG=y
++CONFIG_BLK_CGROUP=y
++CONFIG_RT_GROUP_SCHED=y
++CONFIG_CGROUP_PIDS=y
++CONFIG_CPUSETS=y
++# CONFIG_PROC_PID_CPUSET is not set
++CONFIG_CGROUP_DEVICE=y
++CONFIG_CGROUP_BPF=y
++CONFIG_USER_NS=y
++CONFIG_SCHED_AUTOGROUP=y
++# CONFIG_RD_BZIP2 is not set
++# CONFIG_RD_LZMA is not set
++# CONFIG_RD_XZ is not set
++# CONFIG_RD_LZO is not set
++CONFIG_PERF_EVENTS=y
++CONFIG_ARCH_SUNXI=y
++# CONFIG_MACH_SUN9I is not set
++CONFIG_ARM_ERRATA_814220=y
++CONFIG_SMP=y
++CONFIG_SCHED_MC=y
++CONFIG_MCPM=y
++CONFIG_NR_CPUS=8
++CONFIG_HZ_1000=y
++CONFIG_HIGHMEM=y
++# CONFIG_ARM_MODULE_PLTS is not set
++CONFIG_ARCH_FORCE_MAX_ORDER=11
++CONFIG_ZBOOT_ROM_TEXT=0
++CONFIG_ZBOOT_ROM_BSS=0
++CONFIG_CPU_FREQ=y
++CONFIG_CPU_FREQ_STAT=y
++CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
++CONFIG_CPU_FREQ_GOV_POWERSAVE=y
++CONFIG_CPU_FREQ_GOV_USERSPACE=y
++CONFIG_CPU_FREQ_GOV_ONDEMAND=y
++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
++CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
++CONFIG_CPUFREQ_DT=y
++CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=y
++CONFIG_CPU_IDLE=y
++CONFIG_CPU_IDLE_GOV_LADDER=y
++CONFIG_ARM_CPUIDLE=y
++CONFIG_VFP=y
++CONFIG_NEON=y
++CONFIG_KERNEL_MODE_NEON=y
++CONFIG_PM_WAKELOCKS=y
++CONFIG_PM_DEBUG=y
++CONFIG_PM_ADVANCED_DEBUG=y
++CONFIG_APM_EMULATION=y
++CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
++CONFIG_JUMP_LABEL=y
++# CONFIG_STACKPROTECTOR is not set
++CONFIG_MODULES=y
++CONFIG_MODULE_UNLOAD=y
++CONFIG_BLK_DEV_INTEGRITY=y
++CONFIG_BLK_DEV_THROTTLING=y
++CONFIG_BLK_WBT=y
++CONFIG_BLK_CGROUP_IOLATENCY=y
++# CONFIG_MQ_IOSCHED_DEADLINE is not set
++# CONFIG_MQ_IOSCHED_KYBER is not set
++# CONFIG_BFQ_GROUP_IOSCHED is not set
++CONFIG_CMA=y
++CONFIG_CMA_DEBUGFS=y
++CONFIG_CMA_AREAS=7
++CONFIG_NET=y
++CONFIG_PACKET=y
++CONFIG_PACKET_DIAG=y
++CONFIG_UNIX=y
++CONFIG_UNIX_DIAG=y
++CONFIG_INET=y
++CONFIG_IP_ADVANCED_ROUTER=y
++CONFIG_SYN_COOKIES=y
++CONFIG_INET_DIAG=m
++CONFIG_INET_UDP_DIAG=m
++CONFIG_INET_RAW_DIAG=m
++# CONFIG_IPV6_SIT is not set
++CONFIG_MPTCP=y
++CONFIG_NETFILTER=y
++CONFIG_BRIDGE_NETFILTER=m
++CONFIG_NETFILTER_NETLINK_ACCT=m
++CONFIG_NETFILTER_NETLINK_QUEUE=m
++CONFIG_NETFILTER_NETLINK_LOG=m
++CONFIG_NF_CONNTRACK=m
++CONFIG_NF_CONNTRACK_MARK=y
++# CONFIG_NF_CT_PROTO_DCCP is not set
++# CONFIG_NF_CT_PROTO_SCTP is not set
++# CONFIG_NF_CT_PROTO_UDPLITE is not set
++CONFIG_NF_CONNTRACK_FTP=m
++CONFIG_NF_CONNTRACK_IRC=m
++CONFIG_NF_CONNTRACK_NETBIOS_NS=m
++CONFIG_NF_CONNTRACK_SIP=m
++CONFIG_NF_CT_NETLINK=m
++CONFIG_NETFILTER_NETLINK_GLUE_CT=y
++CONFIG_NF_TABLES=m
++CONFIG_NF_TABLES_INET=y
++CONFIG_NFT_NUMGEN=m
++CONFIG_NFT_CT=m
++CONFIG_NFT_CONNLIMIT=m
++CONFIG_NFT_LOG=m
++CONFIG_NFT_LIMIT=m
++CONFIG_NFT_MASQ=m
++CONFIG_NFT_REDIR=m
++CONFIG_NFT_NAT=m
++CONFIG_NFT_TUNNEL=m
++CONFIG_NFT_QUEUE=m
++CONFIG_NFT_QUOTA=m
++CONFIG_NFT_REJECT=m
++CONFIG_NFT_HASH=m
++CONFIG_NFT_FIB_INET=m
++CONFIG_NFT_SOCKET=m
++CONFIG_NFT_OSF=m
++CONFIG_NF_FLOW_TABLE_INET=m
++CONFIG_NF_FLOW_TABLE=m
++CONFIG_IP_SET=m
++CONFIG_IP_SET_BITMAP_IP=m
++CONFIG_IP_SET_BITMAP_IPMAC=m
++CONFIG_IP_SET_BITMAP_PORT=m
++CONFIG_IP_SET_HASH_IP=m
++CONFIG_IP_SET_HASH_IPMARK=m
++CONFIG_IP_SET_HASH_IPPORT=m
++CONFIG_IP_SET_HASH_IPPORTIP=m
++CONFIG_IP_SET_HASH_IPPORTNET=m
++CONFIG_IP_SET_HASH_IPMAC=m
++CONFIG_IP_SET_HASH_MAC=m
++CONFIG_IP_SET_HASH_NETPORTNET=m
++CONFIG_IP_SET_HASH_NET=m
++CONFIG_IP_SET_HASH_NETNET=m
++CONFIG_IP_SET_HASH_NETPORT=m
++CONFIG_IP_SET_HASH_NETIFACE=m
++CONFIG_IP_SET_LIST_SET=m
++CONFIG_NFT_DUP_IPV4=m
++CONFIG_NFT_FIB_IPV4=m
++CONFIG_NF_TABLES_ARP=y
++CONFIG_NF_LOG_ARP=m
++CONFIG_NF_LOG_IPV4=m
++CONFIG_NFT_DUP_IPV6=m
++CONFIG_NFT_FIB_IPV6=m
++CONFIG_NF_LOG_IPV6=m
++CONFIG_NF_TABLES_BRIDGE=m
++CONFIG_NFT_BRIDGE_REJECT=m
++CONFIG_BRIDGE=m
++CONFIG_NET_SCHED=y
++CONFIG_NET_SCH_HTB=y
++CONFIG_NET_CLS_BASIC=y
++CONFIG_NET_CLS_ROUTE4=y
++CONFIG_NET_CLS_FW=y
++CONFIG_NET_CLS_CGROUP=y
++CONFIG_NET_CLS_MATCHALL=y
++CONFIG_NET_CLS_ACT=y
++CONFIG_NET_ACT_POLICE=y
++CONFIG_NET_ACT_GACT=y
++CONFIG_BT=m
++CONFIG_BT_RFCOMM=m
++CONFIG_BT_RFCOMM_TTY=y
++CONFIG_BT_BNEP=m
++CONFIG_BT_BNEP_MC_FILTER=y
++CONFIG_BT_BNEP_PROTO_FILTER=y
++CONFIG_BT_HIDP=m
++CONFIG_BT_LEDS=y
++CONFIG_BT_HCIBTSDIO=m
++CONFIG_BT_HCIUART=m
++CONFIG_BT_HCIUART_BCM=y
++CONFIG_CFG80211=y
++# CONFIG_CFG80211_DEFAULT_PS is not set
++CONFIG_CFG80211_DEBUGFS=y
++CONFIG_MAC80211=y
++CONFIG_MAC80211_LEDS=y
++CONFIG_RFKILL=y
++CONFIG_RFKILL_GPIO=y
++CONFIG_NFC=m
++CONFIG_NFC_DIGITAL=m
++CONFIG_NFC_NCI=m
++CONFIG_NFC_NXP_NCI=m
++CONFIG_NFC_NXP_NCI_I2C=m
++CONFIG_PAGE_POOL_STATS=y
++CONFIG_UEVENT_HELPER=y
++CONFIG_DEVTMPFS=y
++CONFIG_DEVTMPFS_MOUNT=y
++#CONFIG_EXTRA_FIRMWARE="regulatory.db regulatory.db.p7s brcm/brcmfmac43362-sdio.bin brcm/brcmfmac43362-sdio.txt brcm/BCM20702A1.hcd hm5065-af.bin hm5065-init.bin brcm/brcmfmac43362-sdio.tbs-biometrics,a711.txt"
++#CONFIG_EXTRA_FIRMWARE_DIR="/workspace/megous.com/orangepi-pc/firmware"
++# CONFIG_FW_CACHE is not set
++CONFIG_ARM_SCPI_PROTOCOL=m
++CONFIG_GNSS=y
++CONFIG_GNSS_SIRF_SERIAL=y
++CONFIG_GNSS_UBX_SERIAL=y
++CONFIG_OF_OVERLAY=y
++CONFIG_ZRAM=y
++CONFIG_ZRAM_WRITEBACK=y
++CONFIG_ZRAM_MEMORY_TRACKING=y
++CONFIG_BLK_DEV_LOOP=m
++CONFIG_BLK_DEV_NBD=m
++CONFIG_MODEM_POWER=m
++CONFIG_MD=y
++CONFIG_BLK_DEV_DM=y
++CONFIG_DM_CRYPT=y
++CONFIG_DM_INIT=y
++CONFIG_NETDEVICES=y
++CONFIG_WIREGUARD=m
++CONFIG_TUN=m
++CONFIG_VETH=m
++# CONFIG_ETHERNET is not set
++CONFIG_PPP=m
++CONFIG_PPP_BSDCOMP=m
++CONFIG_PPP_DEFLATE=m
++CONFIG_PPP_FILTER=y
++CONFIG_PPP_MPPE=m
++CONFIG_PPP_ASYNC=m
++CONFIG_PPP_SYNC_TTY=m
++# CONFIG_USB_NET_DRIVERS is not set
++# CONFIG_WLAN_VENDOR_ADMTEK is not set
++# CONFIG_WLAN_VENDOR_ATH is not set
++# CONFIG_WLAN_VENDOR_ATMEL is not set
++CONFIG_BRCMFMAC=m
++# CONFIG_WLAN_VENDOR_INTEL is not set
++# CONFIG_WLAN_VENDOR_INTERSIL is not set
++# CONFIG_WLAN_VENDOR_MARVELL is not set
++# CONFIG_WLAN_VENDOR_MEDIATEK is not set
++# CONFIG_WLAN_VENDOR_RALINK is not set
++# CONFIG_WLAN_VENDOR_REALTEK is not set
++# CONFIG_WLAN_VENDOR_RSI is not set
++# CONFIG_WLAN_VENDOR_ST is not set
++# CONFIG_WLAN_VENDOR_TI is not set
++# CONFIG_WLAN_VENDOR_ZYDAS is not set
++# CONFIG_WLAN_VENDOR_QUANTENNA is not set
++CONFIG_INPUT_EVDEV=y
++# CONFIG_KEYBOARD_ATKBD is not set
++CONFIG_KEYBOARD_GPIO=y
++CONFIG_KEYBOARD_GPIO_POLLED=y
++CONFIG_KEYBOARD_SUN4I_LRADC=y
++# CONFIG_INPUT_MOUSE is not set
++CONFIG_INPUT_TOUCHSCREEN=y
++CONFIG_TOUCHSCREEN_EDT_FT5X06=m
++CONFIG_INPUT_MISC=y
++CONFIG_INPUT_GPIO_VIBRA=y
++CONFIG_INPUT_AXP20X_PEK=y
++# CONFIG_SERIO is not set
++# CONFIG_LEGACY_PTYS is not set
++CONFIG_SERIAL_8250=y
++CONFIG_SERIAL_8250_CONSOLE=y
++CONFIG_SERIAL_8250_NR_UARTS=8
++CONFIG_SERIAL_8250_RUNTIME_UARTS=8
++CONFIG_SERIAL_8250_DW=y
++CONFIG_SERIAL_OF_PLATFORM=y
++CONFIG_SERIAL_DEV_BUS=y
++# CONFIG_HW_RANDOM is not set
++CONFIG_I2C_CHARDEV=y
++CONFIG_I2C_MUX=y
++CONFIG_I2C_GPIO=y
++CONFIG_I2C_MV64XXX=y
++CONFIG_SPI=y
++CONFIG_SPI_SUN4I=y
++CONFIG_SPI_SUN6I=y
++CONFIG_SPI_SPIDEV=y
++CONFIG_PINCTRL_AXP209=y
++CONFIG_POWER_SUPPLY=y
++CONFIG_CHARGER_AXP20X=y
++CONFIG_BATTERY_AXP20X=y
++CONFIG_AXP20X_POWER=y
++# CONFIG_HWMON is not set
++CONFIG_THERMAL=y
++CONFIG_THERMAL_STATISTICS=y
++CONFIG_THERMAL_GOV_FAIR_SHARE=y
++CONFIG_THERMAL_GOV_BANG_BANG=y
++CONFIG_CPU_THERMAL=y
++CONFIG_SUN8I_THERMAL=y
++CONFIG_WATCHDOG=y
++CONFIG_SUNXI_WATCHDOG=y
++CONFIG_MFD_SUN4I_GPADC=y
++CONFIG_MFD_AC100=y
++CONFIG_MFD_AXP20X_RSB=y
++CONFIG_REGULATOR=y
++CONFIG_REGULATOR_FIXED_VOLTAGE=y
++CONFIG_REGULATOR_USERSPACE_CONSUMER=y
++CONFIG_REGULATOR_AXP20X=y
++CONFIG_REGULATOR_GPIO=y
++CONFIG_REGULATOR_PWM=y
++CONFIG_MEDIA_SUPPORT=m
++# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
++CONFIG_MEDIA_CAMERA_SUPPORT=y
++CONFIG_MEDIA_PLATFORM_SUPPORT=y
++CONFIG_VIDEO_ADV_DEBUG=y
++CONFIG_V4L_PLATFORM_DRIVERS=y
++CONFIG_V4L_MEM2MEM_DRIVERS=y
++CONFIG_VIDEO_MEM2MEM_DEINTERLACE=m
++CONFIG_VIDEO_SUN6I_CSI=m
++CONFIG_VIDEO_SUN8I_DEINTERLACE=m
++CONFIG_VIDEO_SUN8I_ROTATE=m
++CONFIG_VIDEO_HM5065=m
++CONFIG_VIDEO_GC2145=m
++CONFIG_DRM=y
++CONFIG_DRM_SUN4I=y
++# CONFIG_DRM_SUN4I_HDMI is not set
++# CONFIG_DRM_SUN4I_BACKEND is not set
++# CONFIG_DRM_SUN6I_DSI is not set
++# CONFIG_DRM_SUN8I_DW_HDMI is not set
++CONFIG_DRM_PANEL_LVDS=y
++CONFIG_FB=y
++CONFIG_BACKLIGHT_CLASS_DEVICE=y
++CONFIG_BACKLIGHT_PWM=y
++CONFIG_SOUND=m
++CONFIG_SND=m
++CONFIG_SND_HRTIMER=m
++# CONFIG_SND_SUPPORT_OLD_API is not set
++CONFIG_SND_DEBUG=y
++CONFIG_SND_DEBUG_VERBOSE=y
++# CONFIG_SND_DRIVERS is not set
++# CONFIG_SND_ARM is not set
++# CONFIG_SND_SPI is not set
++# CONFIG_SND_USB is not set
++CONFIG_SND_SOC=m
++CONFIG_SND_SUN8I_CODEC=m
++CONFIG_SND_AC100_CODEC=m
++CONFIG_SND_SUN4I_I2S=m
++CONFIG_SND_SOC_BT_SCO=m
++CONFIG_SND_SOC_EC25=m
++CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m
++CONFIG_SND_SIMPLE_CARD=m
++CONFIG_HIDRAW=y
++# CONFIG_HID_A4TECH is not set
++# CONFIG_HID_APPLE is not set
++# CONFIG_HID_BELKIN is not set
++# CONFIG_HID_CHERRY is not set
++# CONFIG_HID_CHICONY is not set
++# CONFIG_HID_CYPRESS is not set
++# CONFIG_HID_EZKEY is not set
++# CONFIG_HID_ITE is not set
++# CONFIG_HID_KENSINGTON is not set
++# CONFIG_HID_LOGITECH is not set
++# CONFIG_HID_REDRAGON is not set
++# CONFIG_HID_MICROSOFT is not set
++# CONFIG_HID_MONTEREY is not set
++CONFIG_USB_HIDDEV=y
++CONFIG_USB_LED_TRIG=y
++CONFIG_USB=m
++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
++CONFIG_USB_OTG=y
++CONFIG_USB_OTG_FSM=m
++CONFIG_USB_LEDS_TRIGGER_USBPORT=m
++CONFIG_USB_EHCI_HCD=m
++CONFIG_USB_EHCI_HCD_PLATFORM=m
++CONFIG_USB_OHCI_HCD=m
++CONFIG_USB_OHCI_HCD_PLATFORM=m
++CONFIG_USB_ACM=m
++CONFIG_USB_WDM=m
++CONFIG_USB_MUSB_HDRC=m
++CONFIG_USB_MUSB_SUNXI=m
++CONFIG_USB_SERIAL=m
++CONFIG_USB_SERIAL_GENERIC=y
++CONFIG_USB_SERIAL_OPTION=m
++CONFIG_NOP_USB_XCEIV=m
++CONFIG_USB_GADGET=m
++CONFIG_U_SERIAL_CONSOLE=y
++CONFIG_USB_CONFIGFS=m
++CONFIG_USB_CONFIGFS_SERIAL=y
++CONFIG_USB_CONFIGFS_ACM=y
++CONFIG_USB_CONFIGFS_OBEX=y
++CONFIG_USB_CONFIGFS_NCM=y
++CONFIG_USB_CONFIGFS_ECM=y
++CONFIG_USB_CONFIGFS_ECM_SUBSET=y
++CONFIG_USB_CONFIGFS_RNDIS=y
++CONFIG_USB_CONFIGFS_EEM=y
++CONFIG_USB_CONFIGFS_MASS_STORAGE=y
++CONFIG_USB_CONFIGFS_F_LB_SS=y
++CONFIG_USB_CONFIGFS_F_FS=y
++CONFIG_USB_CONFIGFS_F_UAC1=y
++CONFIG_USB_CONFIGFS_F_UAC2=y
++CONFIG_USB_CONFIGFS_F_MIDI=y
++CONFIG_USB_CONFIGFS_F_HID=y
++CONFIG_USB_CONFIGFS_F_UVC=y
++CONFIG_USB_CONFIGFS_F_PRINTER=y
++CONFIG_USB_ETH=m
++CONFIG_USB_ETH_EEM=y
++CONFIG_MMC=y
++CONFIG_MMC_SUNXI=y
++CONFIG_NEW_LEDS=y
++CONFIG_LEDS_CLASS=y
++CONFIG_LEDS_GPIO=y
++CONFIG_LEDS_AXP20X=y
++CONFIG_LEDS_TRIGGER_TIMER=y
++CONFIG_LEDS_TRIGGER_ONESHOT=y
++CONFIG_LEDS_TRIGGER_HEARTBEAT=y
++CONFIG_LEDS_TRIGGER_BACKLIGHT=y
++CONFIG_LEDS_TRIGGER_CPU=y
++CONFIG_LEDS_TRIGGER_ACTIVITY=y
++CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
++CONFIG_LEDS_TRIGGER_PANIC=y
++CONFIG_LEDS_TRIGGER_NETDEV=y
++CONFIG_LEDS_TRIGGER_PATTERN=y
++CONFIG_RTC_CLASS=y
++# CONFIG_RTC_INTF_SYSFS is not set
++# CONFIG_RTC_INTF_PROC is not set
++CONFIG_RTC_DRV_AC100=y
++# CONFIG_RTC_DRV_SUN6I is not set
++CONFIG_DMADEVICES=y
++CONFIG_DMA_SUN6I=y
++CONFIG_DMABUF_HEAPS=y
++CONFIG_DMABUF_HEAPS_SYSTEM=y
++CONFIG_DMABUF_HEAPS_CMA=y
++# CONFIG_VIRTIO_MENU is not set
++# CONFIG_VHOST_MENU is not set
++CONFIG_STAGING=y
++CONFIG_STAGING_MEDIA=y
++CONFIG_VIDEO_SUNXI=y
++CONFIG_VIDEO_SUNXI_CEDRUS=m
++# CONFIG_CLK_SUNXI_PRCM_SUN9I is not set
++# CONFIG_SUN4I_A10_CCU is not set
++# CONFIG_SUN5I_CCU is not set
++# CONFIG_SUN6I_A31_CCU is not set
++# CONFIG_SUN8I_A23_CCU is not set
++# CONFIG_SUN8I_A33_CCU is not set
++# CONFIG_SUN8I_V3S_CCU is not set
++# CONFIG_SUN8I_R40_CCU is not set
++CONFIG_MAILBOX=y
++# CONFIG_IOMMU_SUPPORT is not set
++# CONFIG_ARM_SCPI_POWER_DOMAIN is not set
++CONFIG_IIO=y
++CONFIG_IIO_KFIFO_BUF=y
++CONFIG_IIO_CONFIGFS=y
++CONFIG_BMA180=m
++CONFIG_AXP20X_ADC=y
++CONFIG_PWM=y
++CONFIG_PWM_SUN4I=y
++CONFIG_PHY_SUN4I_USB=y
++CONFIG_ARM_CCI_PMU=y
++# CONFIG_ARM_CCI5xx_PMU is not set
++CONFIG_NVMEM_SUNXI_SID=y
++CONFIG_VALIDATE_FS_PARSER=y
++CONFIG_EXT4_FS=y
++CONFIG_EXT4_FS_POSIX_ACL=y
++CONFIG_F2FS_FS=y
++CONFIG_F2FS_FS_SECURITY=y
++CONFIG_F2FS_CHECK_FS=y
++CONFIG_F2FS_FS_COMPRESSION=y
++CONFIG_FS_ENCRYPTION=y
++CONFIG_FANOTIFY=y
++CONFIG_AUTOFS_FS=y
++CONFIG_FUSE_FS=m
++CONFIG_VFAT_FS=y
++CONFIG_PROC_CHILDREN=y
++CONFIG_TMPFS=y
++CONFIG_TMPFS_POSIX_ACL=y
++# CONFIG_MISC_FILESYSTEMS is not set
++# CONFIG_NETWORK_FILESYSTEMS is not set
++CONFIG_NLS_CODEPAGE_437=y
++CONFIG_NLS_CODEPAGE_852=y
++CONFIG_NLS_ISO8859_1=y
++CONFIG_NLS_ISO8859_2=y
++CONFIG_NLS_UTF8=y
++CONFIG_KEYS_REQUEST_CACHE=y
++CONFIG_PERSISTENT_KEYRINGS=y
++CONFIG_ENCRYPTED_KEYS=y
++CONFIG_KEY_DH_OPERATIONS=y
++CONFIG_LSM="yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor"
++CONFIG_INIT_STACK_NONE=y
++CONFIG_CRYPTO_PCRYPT=y
++CONFIG_CRYPTO_ECDH=y
++CONFIG_CRYPTO_CURVE25519=y
++CONFIG_CRYPTO_AES_TI=y
++CONFIG_CRYPTO_DES=y
++CONFIG_CRYPTO_CHACHA20POLY1305=y
++CONFIG_CRYPTO_SEQIV=y
++CONFIG_CRYPTO_ECHAINIV=y
++CONFIG_CRYPTO_BLAKE2B=y
++CONFIG_CRYPTO_MD4=y
++CONFIG_CRYPTO_MD5=y
++CONFIG_CRYPTO_DEFLATE=m
++CONFIG_CRYPTO_LZO=y
++CONFIG_CRYPTO_LZ4=y
++CONFIG_CRYPTO_LZ4HC=y
++CONFIG_CRYPTO_ZSTD=y
++CONFIG_CRYPTO_ANSI_CPRNG=y
++CONFIG_CRYPTO_USER_API_HASH=m
++CONFIG_CRYPTO_USER_API_SKCIPHER=m
++CONFIG_CRYPTO_USER_API_RNG=m
++CONFIG_CRYPTO_USER_API_AEAD=m
++CONFIG_CRYPTO_CURVE25519_NEON=y
++CONFIG_CRYPTO_POLY1305_ARM=y
++CONFIG_CRYPTO_SHA1_ARM_NEON=y
++CONFIG_CRYPTO_SHA1_ARM_CE=y
++CONFIG_CRYPTO_SHA2_ARM_CE=y
++CONFIG_CRYPTO_SHA512_ARM=y
++CONFIG_CRYPTO_AES_ARM_BS=y
++CONFIG_CRYPTO_AES_ARM_CE=y
++CONFIG_CRYPTO_CRC32_ARM_CE=y
++CONFIG_CRYPTO_DEV_SUN4I_SS=m
++CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG=y
++CONFIG_CRYPTO_DEV_SUN8I_CE=m
++CONFIG_CRYPTO_DEV_SUN8I_SS=m
++CONFIG_PKCS8_PRIVATE_KEY_PARSER=y
++CONFIG_CRC_CCITT=y
++CONFIG_CRC_ITU_T=y
++CONFIG_LIBCRC32C=y
++CONFIG_DMA_CMA=y
++CONFIG_CMA_SIZE_MBYTES=64
++CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15
++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
++CONFIG_DEBUG_KERNEL=y
++CONFIG_MAGIC_SYSRQ=y
++CONFIG_DEBUG_FS=y
++CONFIG_DETECT_HUNG_TASK=y
++CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y
++CONFIG_WQ_WATCHDOG=y
++# CONFIG_SCHED_DEBUG is not set
++# CONFIG_RCU_TRACE is not set
++CONFIG_BOOTTIME_TRACING=y
++CONFIG_FUNCTION_TRACER=y
++# CONFIG_UPROBE_EVENTS is not set
++CONFIG_UNWINDER_FRAME_POINTER=y
++CONFIG_DEBUG_LL=y
++CONFIG_EARLY_PRINTK=y
++# CONFIG_RUNTIME_TESTING_MENU is not set
+diff --git a/arch/arm64/configs/orangepi_defconfig b/arch/arm64/configs/orangepi_defconfig
+new file mode 100644
+index 000000000000..19cfe9bb4c6e
+--- /dev/null
++++ b/arch/arm64/configs/orangepi_defconfig
+@@ -0,0 +1,1037 @@
++CONFIG_SYSVIPC=y
++CONFIG_POSIX_MQUEUE=y
++CONFIG_WATCH_QUEUE=y
++CONFIG_GENERIC_IRQ_DEBUGFS=y
++CONFIG_NO_HZ=y
++CONFIG_HIGH_RES_TIMERS=y
++CONFIG_BPF_SYSCALL=y
++CONFIG_BPF_JIT=y
++CONFIG_BPF_JIT_ALWAYS_ON=y
++# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set
++CONFIG_PREEMPT_VOLUNTARY=y
++CONFIG_BSD_PROCESS_ACCT=y
++CONFIG_BSD_PROCESS_ACCT_V3=y
++CONFIG_TASKSTATS=y
++CONFIG_TASK_DELAY_ACCT=y
++CONFIG_TASK_XACCT=y
++CONFIG_TASK_IO_ACCOUNTING=y
++CONFIG_PSI=y
++CONFIG_IKCONFIG=y
++CONFIG_IKCONFIG_PROC=y
++CONFIG_LOG_BUF_SHIFT=20
++CONFIG_LOG_CPU_MAX_BUF_SHIFT=14
++CONFIG_MEMCG=y
++CONFIG_BLK_CGROUP=y
++CONFIG_CFS_BANDWIDTH=y
++CONFIG_RT_GROUP_SCHED=y
++CONFIG_CGROUP_PIDS=y
++CONFIG_CGROUP_FREEZER=y
++CONFIG_CPUSETS=y
++# CONFIG_PROC_PID_CPUSET is not set
++CONFIG_CGROUP_DEVICE=y
++CONFIG_CGROUP_CPUACCT=y
++CONFIG_CGROUP_BPF=y
++CONFIG_CGROUP_MISC=y
++CONFIG_USER_NS=y
++CONFIG_SCHED_AUTOGROUP=y
++CONFIG_RELAY=y
++# CONFIG_RD_BZIP2 is not set
++# CONFIG_RD_LZMA is not set
++# CONFIG_RD_XZ is not set
++# CONFIG_RD_LZO is not set
++CONFIG_BOOT_CONFIG=y
++CONFIG_KALLSYMS_ALL=y
++CONFIG_PERF_EVENTS=y
++CONFIG_ARCH_SUNXI=y
++CONFIG_ARCH_ROCKCHIP=y
++# CONFIG_ARM64_ERRATUM_832075 is not set
++CONFIG_ARM64_ERRATUM_2441007=y
++CONFIG_ARM64_ERRATUM_1286807=y
++# CONFIG_ARM64_ERRATUM_1508412 is not set
++# CONFIG_ARM64_ERRATUM_2051678 is not set
++# CONFIG_ARM64_ERRATUM_2077057 is not set
++# CONFIG_ARM64_ERRATUM_2658417 is not set
++# CONFIG_ARM64_ERRATUM_2054223 is not set
++# CONFIG_ARM64_ERRATUM_2067961 is not set
++# CONFIG_ARM64_ERRATUM_2645198 is not set
++# CONFIG_ARM64_ERRATUM_2966298 is not set
++# CONFIG_CAVIUM_ERRATUM_22375 is not set
++# CONFIG_CAVIUM_ERRATUM_23144 is not set
++# CONFIG_CAVIUM_ERRATUM_23154 is not set
++# CONFIG_CAVIUM_ERRATUM_27456 is not set
++# CONFIG_CAVIUM_ERRATUM_30115 is not set
++# CONFIG_CAVIUM_TX2_ERRATUM_219 is not set
++# CONFIG_FUJITSU_ERRATUM_010001 is not set
++# CONFIG_HISILICON_ERRATUM_161600802 is not set
++# CONFIG_QCOM_FALKOR_ERRATUM_1003 is not set
++# CONFIG_QCOM_FALKOR_ERRATUM_1009 is not set
++# CONFIG_QCOM_QDF2400_ERRATUM_0065 is not set
++# CONFIG_QCOM_FALKOR_ERRATUM_E1041 is not set
++# CONFIG_NVIDIA_CARMEL_CNP_ERRATUM is not set
++CONFIG_ARM64_VA_BITS_48=y
++CONFIG_SCHED_MC=y
++CONFIG_SCHED_CLUSTER=y
++CONFIG_NR_CPUS=8
++CONFIG_NUMA=y
++CONFIG_NODES_SHIFT=3
++CONFIG_PARAVIRT=y
++CONFIG_COMPAT=y
++CONFIG_ARM64_PMEM=y
++# CONFIG_ARM64_PTR_AUTH is not set
++# CONFIG_ARM64_AMU_EXTN is not set
++# CONFIG_ARM64_TLB_RANGE is not set
++# CONFIG_ARM64_BTI is not set
++# CONFIG_ARM64_E0PD is not set
++# CONFIG_ARM64_MTE is not set
++# CONFIG_ARM64_EPAN is not set
++# CONFIG_ARM64_SVE is not set
++# CONFIG_EFI is not set
++CONFIG_HIBERNATION=y
++CONFIG_PM_AUTOSLEEP=y
++CONFIG_PM_WAKELOCKS=y
++CONFIG_PM_DEBUG=y
++CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
++CONFIG_ENERGY_MODEL=y
++CONFIG_CPU_IDLE=y
++CONFIG_CPU_IDLE_GOV_LADDER=y
++CONFIG_ARM_PSCI_CPUIDLE=y
++CONFIG_CPU_FREQ=y
++CONFIG_CPU_FREQ_STAT=y
++CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
++CONFIG_CPU_FREQ_GOV_POWERSAVE=y
++CONFIG_CPU_FREQ_GOV_USERSPACE=y
++CONFIG_CPU_FREQ_GOV_ONDEMAND=y
++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
++CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y
++CONFIG_CPUFREQ_DT=y
++CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=y
++CONFIG_ARM_SCPI_CPUFREQ=y
++CONFIG_ARM_SCMI_CPUFREQ=y
++CONFIG_VIRTUALIZATION=y
++CONFIG_KVM=y
++CONFIG_JUMP_LABEL=y
++# CONFIG_STACKPROTECTOR is not set
++CONFIG_MODULES=y
++CONFIG_MODULE_UNLOAD=y
++CONFIG_BLK_DEV_THROTTLING=y
++CONFIG_BLK_WBT=y
++CONFIG_BLK_CGROUP_IOLATENCY=y
++CONFIG_BLK_CGROUP_IOCOST=y
++CONFIG_BLK_CGROUP_IOPRIO=y
++CONFIG_BLK_INLINE_ENCRYPTION=y
++CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK=y
++CONFIG_PARTITION_ADVANCED=y
++CONFIG_BINFMT_MISC=y
++CONFIG_ZSWAP=y
++CONFIG_ZSWAP_DEFAULT_ON=y
++CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4=y
++CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y
++CONFIG_ZSMALLOC_STAT=y
++CONFIG_TRANSPARENT_HUGEPAGE=y
++CONFIG_CMA=y
++CONFIG_CMA_DEBUGFS=y
++CONFIG_CMA_SYSFS=y
++CONFIG_CMA_AREAS=7
++CONFIG_NET=y
++CONFIG_PACKET=y
++CONFIG_PACKET_DIAG=y
++CONFIG_UNIX=y
++CONFIG_UNIX_DIAG=y
++CONFIG_XFRM_USER=y
++CONFIG_NET_KEY=y
++CONFIG_INET=y
++CONFIG_IP_MULTICAST=y
++CONFIG_IP_ADVANCED_ROUTER=y
++CONFIG_IP_MULTIPLE_TABLES=y
++CONFIG_IP_ROUTE_MULTIPATH=y
++CONFIG_IP_ROUTE_VERBOSE=y
++CONFIG_IP_MROUTE=y
++CONFIG_IP_MROUTE_MULTIPLE_TABLES=y
++CONFIG_INET_UDP_DIAG=y
++CONFIG_INET_RAW_DIAG=y
++CONFIG_INET_DIAG_DESTROY=y
++CONFIG_IPV6_ROUTER_PREF=y
++CONFIG_IPV6_ROUTE_INFO=y
++CONFIG_IPV6_OPTIMISTIC_DAD=y
++CONFIG_IPV6_MIP6=y
++CONFIG_IPV6_TUNNEL=y
++CONFIG_IPV6_MULTIPLE_TABLES=y
++CONFIG_IPV6_SUBTREES=y
++CONFIG_IPV6_MROUTE=y
++CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
++CONFIG_NETFILTER=y
++CONFIG_BRIDGE_NETFILTER=y
++CONFIG_NETFILTER_NETLINK_HOOK=y
++CONFIG_NETFILTER_NETLINK_ACCT=y
++CONFIG_NETFILTER_NETLINK_QUEUE=y
++CONFIG_NETFILTER_NETLINK_LOG=y
++CONFIG_NF_CONNTRACK=y
++CONFIG_NF_CONNTRACK_MARK=y
++CONFIG_NF_CONNTRACK_EVENTS=y
++CONFIG_NF_CONNTRACK_TIMEOUT=y
++CONFIG_NF_CONNTRACK_TIMESTAMP=y
++CONFIG_NF_CONNTRACK_LABELS=y
++CONFIG_NF_CONNTRACK_FTP=y
++CONFIG_NF_CONNTRACK_H323=y
++CONFIG_NF_CONNTRACK_IRC=y
++CONFIG_NF_CONNTRACK_NETBIOS_NS=y
++CONFIG_NF_CONNTRACK_SNMP=y
++CONFIG_NF_CONNTRACK_PPTP=y
++CONFIG_NF_CONNTRACK_SANE=y
++CONFIG_NF_CONNTRACK_SIP=y
++CONFIG_NF_CONNTRACK_TFTP=y
++CONFIG_NF_CT_NETLINK=y
++CONFIG_NETFILTER_NETLINK_GLUE_CT=y
++CONFIG_NF_TABLES=y
++CONFIG_NF_TABLES_INET=y
++CONFIG_NF_TABLES_NETDEV=y
++CONFIG_NFT_NUMGEN=y
++CONFIG_NFT_CT=y
++CONFIG_NFT_FLOW_OFFLOAD=y
++CONFIG_NFT_CONNLIMIT=y
++CONFIG_NFT_LOG=y
++CONFIG_NFT_LIMIT=y
++CONFIG_NFT_MASQ=y
++CONFIG_NFT_REDIR=y
++CONFIG_NFT_NAT=y
++CONFIG_NFT_TUNNEL=y
++CONFIG_NFT_QUEUE=y
++CONFIG_NFT_QUOTA=y
++CONFIG_NFT_REJECT=y
++CONFIG_NFT_HASH=y
++CONFIG_NFT_FIB_INET=y
++CONFIG_NFT_SOCKET=y
++CONFIG_NFT_OSF=y
++CONFIG_NFT_TPROXY=y
++CONFIG_NFT_SYNPROXY=y
++CONFIG_NFT_DUP_NETDEV=y
++CONFIG_NFT_FWD_NETDEV=y
++CONFIG_NFT_FIB_NETDEV=y
++CONFIG_NFT_REJECT_NETDEV=y
++CONFIG_NF_FLOW_TABLE_INET=y
++CONFIG_NF_FLOW_TABLE=y
++CONFIG_IP_SET=y
++CONFIG_IP_SET_BITMAP_IP=y
++CONFIG_IP_SET_BITMAP_IPMAC=y
++CONFIG_IP_SET_BITMAP_PORT=y
++CONFIG_IP_SET_HASH_IP=y
++CONFIG_IP_SET_HASH_IPMARK=y
++CONFIG_IP_SET_HASH_IPPORT=y
++CONFIG_IP_SET_HASH_IPPORTIP=y
++CONFIG_IP_SET_HASH_IPPORTNET=y
++CONFIG_IP_SET_HASH_IPMAC=y
++CONFIG_IP_SET_HASH_MAC=y
++CONFIG_IP_SET_HASH_NETPORTNET=y
++CONFIG_IP_SET_HASH_NET=y
++CONFIG_IP_SET_HASH_NETNET=y
++CONFIG_IP_SET_HASH_NETPORT=y
++CONFIG_IP_SET_HASH_NETIFACE=y
++CONFIG_IP_SET_LIST_SET=y
++CONFIG_NFT_DUP_IPV4=y
++CONFIG_NFT_FIB_IPV4=y
++CONFIG_NF_TABLES_ARP=y
++CONFIG_NF_LOG_ARP=y
++CONFIG_NF_LOG_IPV4=y
++# CONFIG_NF_NAT_SNMP_BASIC is not set
++CONFIG_NFT_DUP_IPV6=y
++CONFIG_NFT_FIB_IPV6=y
++CONFIG_NF_LOG_IPV6=y
++CONFIG_NF_TABLES_BRIDGE=y
++CONFIG_NFT_BRIDGE_META=y
++CONFIG_NFT_BRIDGE_REJECT=y
++CONFIG_NF_CONNTRACK_BRIDGE=y
++CONFIG_L2TP=y
++CONFIG_L2TP_V3=y
++CONFIG_L2TP_IP=y
++CONFIG_BRIDGE=y
++CONFIG_BRIDGE_VLAN_FILTERING=y
++CONFIG_BRIDGE_MRP=y
++CONFIG_BRIDGE_CFM=y
++CONFIG_VLAN_8021Q=y
++CONFIG_VLAN_8021Q_GVRP=y
++CONFIG_VLAN_8021Q_MVRP=y
++CONFIG_NET_SCHED=y
++CONFIG_NET_SCH_HTB=y
++CONFIG_NET_SCH_HFSC=y
++CONFIG_NET_SCH_PRIO=y
++CONFIG_NET_SCH_MULTIQ=y
++CONFIG_NET_SCH_RED=y
++CONFIG_NET_SCH_SFB=y
++CONFIG_NET_SCH_SFQ=y
++CONFIG_NET_SCH_TEQL=y
++CONFIG_NET_SCH_TBF=y
++CONFIG_NET_SCH_CBS=y
++CONFIG_NET_SCH_ETF=y
++CONFIG_NET_SCH_TAPRIO=y
++CONFIG_NET_SCH_GRED=y
++CONFIG_NET_SCH_NETEM=y
++CONFIG_NET_SCH_DRR=y
++CONFIG_NET_SCH_MQPRIO=y
++CONFIG_NET_SCH_SKBPRIO=y
++CONFIG_NET_SCH_CHOKE=y
++CONFIG_NET_SCH_QFQ=y
++CONFIG_NET_SCH_CODEL=y
++CONFIG_NET_SCH_FQ_CODEL=y
++CONFIG_NET_SCH_CAKE=y
++CONFIG_NET_SCH_FQ=y
++CONFIG_NET_SCH_HHF=y
++CONFIG_NET_SCH_PIE=y
++CONFIG_NET_SCH_FQ_PIE=y
++CONFIG_NET_SCH_INGRESS=y
++CONFIG_NET_SCH_PLUG=y
++CONFIG_NET_SCH_ETS=y
++CONFIG_NET_CLS_BASIC=y
++CONFIG_NET_CLS_ROUTE4=y
++CONFIG_NET_CLS_FW=y
++CONFIG_NET_CLS_U32=y
++CONFIG_CLS_U32_PERF=y
++CONFIG_CLS_U32_MARK=y
++CONFIG_NET_CLS_FLOW=y
++CONFIG_NET_CLS_CGROUP=y
++CONFIG_NET_CLS_BPF=y
++CONFIG_NET_CLS_FLOWER=y
++CONFIG_NET_CLS_MATCHALL=y
++CONFIG_NET_EMATCH=y
++CONFIG_NET_EMATCH_CMP=y
++CONFIG_NET_EMATCH_NBYTE=y
++CONFIG_NET_EMATCH_U32=y
++CONFIG_NET_EMATCH_META=y
++CONFIG_NET_EMATCH_TEXT=y
++CONFIG_NET_EMATCH_IPSET=y
++CONFIG_NET_CLS_ACT=y
++CONFIG_NET_ACT_POLICE=y
++CONFIG_NET_ACT_GACT=y
++CONFIG_GACT_PROB=y
++CONFIG_NET_ACT_CONNMARK=y
++CONFIG_NET_ACT_CTINFO=y
++CONFIG_NETLINK_DIAG=y
++CONFIG_CGROUP_NET_PRIO=y
++CONFIG_BT=y
++CONFIG_BT_RFCOMM=y
++CONFIG_BT_RFCOMM_TTY=y
++CONFIG_BT_BNEP=y
++CONFIG_BT_BNEP_MC_FILTER=y
++CONFIG_BT_BNEP_PROTO_FILTER=y
++CONFIG_BT_HIDP=y
++CONFIG_BT_LEDS=y
++CONFIG_BT_HCIBTUSB=y
++CONFIG_BT_HCIBTUSB_AUTOSUSPEND=y
++CONFIG_BT_HCIUART=y
++CONFIG_BT_HCIUART_BCM=y
++CONFIG_BT_HCIUART_RTL=y
++CONFIG_CFG80211=y
++CONFIG_CFG80211_DEBUGFS=y
++CONFIG_CFG80211_WEXT=y
++CONFIG_MAC80211=y
++CONFIG_MAC80211_MESH=y
++CONFIG_MAC80211_LEDS=y
++CONFIG_MAC80211_DEBUGFS=y
++CONFIG_RFKILL=y
++CONFIG_RFKILL_GPIO=y
++CONFIG_PAGE_POOL_STATS=y
++CONFIG_PCI=y
++CONFIG_PCIEPORTBUS=y
++CONFIG_HOTPLUG_PCI_PCIE=y
++CONFIG_PCIEAER=y
++CONFIG_PCIE_DPC=y
++CONFIG_PCIE_PTM=y
++CONFIG_PCI_DEBUG=y
++CONFIG_PCI_REALLOC_ENABLE_AUTO=y
++CONFIG_PCI_STUB=y
++CONFIG_PCI_PF_STUB=y
++CONFIG_PCI_IOV=y
++CONFIG_PCI_PRI=y
++CONFIG_PCI_PASID=y
++CONFIG_HOTPLUG_PCI=y
++CONFIG_PCIE_ROCKCHIP_HOST=y
++CONFIG_PCIE_ROCKCHIP_DW_HOST=y
++CONFIG_UEVENT_HELPER=y
++CONFIG_DEVTMPFS=y
++CONFIG_DEVTMPFS_MOUNT=y
++#CONFIG_EXTRA_FIRMWARE="regulatory.db regulatory.db.p7s edid/asus.bin brcm/brcmfmac43456-sdio.bin brcm/brcmfmac43456-sdio.clm_blob brcm/brcmfmac43456-sdio.txt brcm/brcmfmac43456-sdio.pine64,pinebook-pro.txt brcm/BCM4345C5.hcd brcm/brcmfmac43456-sdio.xunlong,orangepi-3.txt anx7688-fw.bin rtl_bt/rtl8723cs_xx_config.bin rtl_bt/rtl8723cs_xx_fw.bin ov5640_af.bin brcm/brcmfmac43455-sdio.bin brcm/brcmfmac43455-sdio.pine64,pinephone-pro.txt brcm/brcmfmac43455-sdio.pine64,pinebook-pro.txt brcm/brcmfmac43455-sdio.clm_blob brcm/BCM4345C0.hcd rockchip/dptx.bin rt2870.bin rtw88/rtw8822c_fw.bin rtw88/rtw8822c_wow_fw.bin rtw89/rtw8852a_fw.bin rtl_nic/rtl8125a-3.fw rtl_nic/rtl8125b-2.fw rtl_nic/rtl8153a-4.fw rtl_nic/rtl8168h-2.fw brcm/brcmfmac43752-pcie.clm_blob brcm/brcmfmac43752-pcie.bin brcm/brcmfmac43752-pcie.txt bes2600/bes2600_factory.txt bes2600/best2002_fw_boot_sdio.bin bes2600/best2002_fw_sdio.bin bes2600/best2002_fw_sdio_btrf.bin bes2600/best2002_fw_sdio_nosignal.bin bes2600/sdd.bin bes2600/factory.bin rtl_bt/rtl8821c_fw.bin rtl_bt/rtl8821c_config.bin rtl_bt/rtl8822b_fw.bin rtl_bt/rtl8822b_config.bin rtw88/rtw8821c_fw.bin rtw88/rtw8822b_fw.bin arm/mali/arch10.8/mali_csffw.bin"
++#CONFIG_EXTRA_FIRMWARE_DIR="/workspace/megous.com/orangepi-pc/firmware"
++CONFIG_ARM_SCMI_PROTOCOL=y
++CONFIG_ARM_SCPI_PROTOCOL=y
++CONFIG_GNSS=y
++CONFIG_MTD=y
++CONFIG_MTD_BLOCK=y
++CONFIG_MTD_PARTITIONED_MASTER=y
++CONFIG_MTD_SPI_NOR=y
++# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
++CONFIG_ZRAM=y
++CONFIG_ZRAM_WRITEBACK=y
++CONFIG_ZRAM_MEMORY_TRACKING=y
++CONFIG_BLK_DEV_LOOP=y
++CONFIG_BLK_DEV_NBD=y
++CONFIG_BLK_DEV_NVME=y
++CONFIG_NVME_HWMON=y
++CONFIG_SRAM=y
++CONFIG_PPKB_POWER_MANAGER=y
++CONFIG_MODEM_POWER=y
++CONFIG_BLK_DEV_SD=y
++# CONFIG_SCSI_LOWLEVEL is not set
++CONFIG_ATA=y
++CONFIG_SATA_AHCI=y
++CONFIG_SATA_MOBILE_LPM_POLICY=0
++CONFIG_SATA_AHCI_PLATFORM=y
++CONFIG_AHCI_DWC=y
++# CONFIG_ATA_SFF is not set
++CONFIG_MD=y
++CONFIG_BLK_DEV_DM=y
++CONFIG_DM_CRYPT=y
++CONFIG_DM_INIT=y
++CONFIG_DM_UEVENT=y
++CONFIG_DM_INTEGRITY=y
++CONFIG_NETDEVICES=y
++CONFIG_WIREGUARD=y
++CONFIG_TUN=y
++CONFIG_VETH=y
++# CONFIG_NET_VENDOR_ALACRITECH is not set
++# CONFIG_NET_VENDOR_ALLWINNER is not set
++# CONFIG_NET_VENDOR_AMAZON is not set
++# CONFIG_NET_VENDOR_AMD is not set
++# CONFIG_NET_VENDOR_AQUANTIA is not set
++# CONFIG_NET_VENDOR_ARC is not set
++# CONFIG_NET_VENDOR_BROADCOM is not set
++# CONFIG_NET_VENDOR_CADENCE is not set
++# CONFIG_NET_VENDOR_CAVIUM is not set
++# CONFIG_NET_VENDOR_CORTINA is not set
++# CONFIG_NET_VENDOR_EZCHIP is not set
++# CONFIG_NET_VENDOR_GOOGLE is not set
++# CONFIG_NET_VENDOR_HISILICON is not set
++# CONFIG_NET_VENDOR_HUAWEI is not set
++CONFIG_IGB=y
++CONFIG_IGBVF=y
++# CONFIG_NET_VENDOR_MARVELL is not set
++# CONFIG_NET_VENDOR_MELLANOX is not set
++# CONFIG_NET_VENDOR_MICREL is not set
++# CONFIG_NET_VENDOR_MICROCHIP is not set
++# CONFIG_NET_VENDOR_MICROSEMI is not set
++# CONFIG_NET_VENDOR_NI is not set
++# CONFIG_NET_VENDOR_NATSEMI is not set
++# CONFIG_NET_VENDOR_NETRONOME is not set
++# CONFIG_NET_VENDOR_PENSANDO is not set
++# CONFIG_NET_VENDOR_QUALCOMM is not set
++CONFIG_R8169=y
++# CONFIG_NET_VENDOR_RENESAS is not set
++# CONFIG_NET_VENDOR_ROCKER is not set
++# CONFIG_NET_VENDOR_SAMSUNG is not set
++# CONFIG_NET_VENDOR_SEEQ is not set
++# CONFIG_NET_VENDOR_SOLARFLARE is not set
++# CONFIG_NET_VENDOR_SMSC is not set
++# CONFIG_NET_VENDOR_SOCIONEXT is not set
++CONFIG_STMMAC_ETH=y
++CONFIG_DWMAC_DWC_QOS_ETH=y
++# CONFIG_NET_VENDOR_SYNOPSYS is not set
++# CONFIG_NET_VENDOR_VIA is not set
++# CONFIG_NET_VENDOR_WIZNET is not set
++# CONFIG_NET_VENDOR_XILINX is not set
++CONFIG_LED_TRIGGER_PHY=y
++CONFIG_MOTORCOMM_PHY=y
++CONFIG_ROCKCHIP_PHY=y
++CONFIG_MDIO_SUN4I=y
++CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y
++CONFIG_PPP=y
++CONFIG_PPP_BSDCOMP=y
++CONFIG_PPP_DEFLATE=y
++CONFIG_PPP_FILTER=y
++CONFIG_PPP_MPPE=y
++CONFIG_PPPOE=y
++CONFIG_PPPOL2TP=y
++CONFIG_PPP_ASYNC=y
++CONFIG_PPP_SYNC_TTY=y
++CONFIG_USB_RTL8152=y
++CONFIG_USB_USBNET=y
++# CONFIG_USB_NET_AX8817X is not set
++# CONFIG_USB_NET_AX88179_178A is not set
++CONFIG_USB_NET_CDC_EEM=y
++CONFIG_USB_NET_CDC_MBIM=y
++# CONFIG_USB_NET_NET1080 is not set
++# CONFIG_USB_NET_CDC_SUBSET is not set
++# CONFIG_USB_NET_ZAURUS is not set
++CONFIG_USB_NET_QMI_WWAN=y
++# CONFIG_WLAN_VENDOR_ADMTEK is not set
++# CONFIG_WLAN_VENDOR_ATH is not set
++# CONFIG_WLAN_VENDOR_ATMEL is not set
++CONFIG_BRCMFMAC=y
++CONFIG_BRCMFMAC_PCIE=y
++CONFIG_BRCMDBG=y
++# CONFIG_WLAN_VENDOR_INTEL is not set
++# CONFIG_WLAN_VENDOR_INTERSIL is not set
++# CONFIG_WLAN_VENDOR_MARVELL is not set
++# CONFIG_WLAN_VENDOR_MEDIATEK is not set
++# CONFIG_WLAN_VENDOR_MICROCHIP is not set
++# CONFIG_WLAN_VENDOR_PURELIFI is not set
++CONFIG_RT2X00=y
++CONFIG_RT2800USB=y
++# CONFIG_RT2800USB_RT35XX is not set
++CONFIG_RT2800USB_RT53XX=y
++# CONFIG_RTL_CARDS is not set
++CONFIG_RTW88=y
++CONFIG_RTW88_8822BU=y
++CONFIG_RTW88_8822CE=y
++CONFIG_RTW88_8821CU=y
++CONFIG_RTW88_DEBUG=y
++CONFIG_RTW88_DEBUGFS=y
++CONFIG_RTW89=y
++CONFIG_RTW89_8852AE=y
++CONFIG_RTW89_8852CE=y
++# CONFIG_WLAN_VENDOR_RSI is not set
++CONFIG_CW1200=m
++CONFIG_CW1200_WLAN_SDIO=m
++# CONFIG_WLAN_VENDOR_TI is not set
++# CONFIG_WLAN_VENDOR_ZYDAS is not set
++# CONFIG_WLAN_VENDOR_QUANTENNA is not set
++CONFIG_INPUT_MOUSEDEV=y
++CONFIG_INPUT_MOUSEDEV_PSAUX=y
++CONFIG_INPUT_EVDEV=y
++CONFIG_KEYBOARD_ADC=y
++# CONFIG_KEYBOARD_ATKBD is not set
++CONFIG_KEYBOARD_GPIO=y
++CONFIG_KEYBOARD_GPIO_POLLED=y
++CONFIG_KEYBOARD_PINEPHONE=y
++CONFIG_KEYBOARD_SUN4I_LRADC=y
++# CONFIG_INPUT_MOUSE is not set
++CONFIG_INPUT_TOUCHSCREEN=y
++CONFIG_TOUCHSCREEN_GOODIX=y
++CONFIG_INPUT_MISC=y
++CONFIG_INPUT_GPIO_VIBRA=y
++CONFIG_INPUT_AXP20X_PEK=y
++CONFIG_INPUT_UINPUT=y
++CONFIG_INPUT_RK805_PWRKEY=y
++# CONFIG_SERIO is not set
++# CONFIG_LEGACY_PTYS is not set
++CONFIG_SERIAL_8250=y
++CONFIG_SERIAL_8250_CONSOLE=y
++CONFIG_SERIAL_8250_NR_UARTS=8
++CONFIG_SERIAL_8250_RUNTIME_UARTS=8
++CONFIG_SERIAL_8250_PCI1XXXX=y
++CONFIG_SERIAL_8250_DW=y
++CONFIG_SERIAL_OF_PLATFORM=y
++CONFIG_SERIAL_AMBA_PL011=y
++CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
++CONFIG_SERIAL_DEV_BUS=y
++CONFIG_HW_RANDOM_CN10K=y
++# CONFIG_HW_RANDOM_ROCKCHIP is not set
++CONFIG_I2C_CHARDEV=y
++CONFIG_I2C_GPIO=y
++CONFIG_I2C_MV64XXX=y
++CONFIG_I2C_RK3X=y
++CONFIG_SPI=y
++CONFIG_SPI_ROCKCHIP=y
++CONFIG_SPI_ROCKCHIP_SFC=y
++CONFIG_SPI_SUN4I=y
++CONFIG_SPI_SUN6I=y
++CONFIG_PINCTRL_AXP209=y
++CONFIG_PINCTRL_RK805=y
++CONFIG_PINCTRL_SINGLE=y
++# CONFIG_PINCTRL_SUN50I_H616 is not set
++# CONFIG_PINCTRL_SUN50I_H616_R is not set
++CONFIG_POWER_RESET_GPIO=y
++CONFIG_POWER_RESET_GPIO_RESTART=y
++CONFIG_SYSCON_REBOOT_MODE=y
++CONFIG_NVMEM_REBOOT_MODE=y
++CONFIG_IP5XXX_POWER=y
++CONFIG_BATTERY_CW2015=y
++CONFIG_CHARGER_AXP20X=y
++CONFIG_BATTERY_AXP20X=y
++CONFIG_AXP20X_POWER=y
++CONFIG_CHARGER_GPIO=y
++CONFIG_CHARGER_RK817=y
++CONFIG_CHARGER_RK818=y
++CONFIG_SENSORS_ARM_SCMI=y
++CONFIG_SENSORS_ARM_SCPI=y
++CONFIG_SENSORS_GPIO_FAN=y
++CONFIG_THERMAL=y
++CONFIG_THERMAL_STATISTICS=y
++CONFIG_THERMAL_GOV_FAIR_SHARE=y
++CONFIG_THERMAL_GOV_BANG_BANG=y
++CONFIG_CPU_THERMAL=y
++CONFIG_DEVFREQ_THERMAL=y
++CONFIG_SUN8I_THERMAL=y
++CONFIG_ROCKCHIP_THERMAL=y
++CONFIG_WATCHDOG=y
++CONFIG_DW_WATCHDOG=y
++CONFIG_SUNXI_WATCHDOG=y
++CONFIG_BCMA=y
++CONFIG_MFD_SUN4I_GPADC=y
++CONFIG_MFD_AXP20X_I2C=y
++CONFIG_MFD_AXP20X_RSB=y
++CONFIG_MFD_RK8XX_I2C=y
++CONFIG_MFD_RK8XX_SPI=y
++CONFIG_MFD_SUN6I_PRCM=y
++CONFIG_REGULATOR=y
++CONFIG_REGULATOR_FIXED_VOLTAGE=y
++CONFIG_REGULATOR_USERSPACE_CONSUMER=y
++CONFIG_REGULATOR_AXP20X=y
++CONFIG_REGULATOR_FAN53555=y
++CONFIG_REGULATOR_GPIO=y
++CONFIG_REGULATOR_PWM=y
++CONFIG_REGULATOR_RK808=y
++CONFIG_REGULATOR_SY8106A=y
++CONFIG_RC_CORE=y
++CONFIG_BPF_LIRC_MODE2=y
++CONFIG_LIRC=y
++CONFIG_RC_DECODERS=y
++CONFIG_IR_JVC_DECODER=y
++CONFIG_IR_MCE_KBD_DECODER=y
++CONFIG_IR_NEC_DECODER=y
++CONFIG_IR_RC5_DECODER=y
++CONFIG_IR_RC6_DECODER=y
++CONFIG_IR_SANYO_DECODER=y
++CONFIG_IR_SHARP_DECODER=y
++CONFIG_IR_SONY_DECODER=y
++CONFIG_IR_XMP_DECODER=y
++CONFIG_RC_DEVICES=y
++CONFIG_IR_GPIO_CIR=y
++CONFIG_IR_SUNXI=y
++CONFIG_MEDIA_CEC_RC=y
++CONFIG_MEDIA_CEC_SUPPORT=y
++CONFIG_MEDIA_SUPPORT=y
++# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
++CONFIG_MEDIA_CAMERA_SUPPORT=y
++CONFIG_MEDIA_PLATFORM_SUPPORT=y
++CONFIG_VIDEO_ADV_DEBUG=y
++CONFIG_V4L2_FLASH_LED_CLASS=y
++CONFIG_MEDIA_USB_SUPPORT=y
++CONFIG_USB_VIDEO_CLASS=y
++CONFIG_V4L_PLATFORM_DRIVERS=y
++CONFIG_V4L_MEM2MEM_DRIVERS=y
++CONFIG_VIDEO_MEM2MEM_DEINTERLACE=y
++CONFIG_VIDEO_ROCKCHIP_RGA=y
++CONFIG_VIDEO_ROCKCHIP_ISP1=y
++CONFIG_VIDEO_SUN6I_CSI=y
++CONFIG_VIDEO_SUN8I_DEINTERLACE=y
++CONFIG_VIDEO_SUN8I_ROTATE=y
++CONFIG_VIDEO_HANTRO=y
++CONFIG_VIDEO_IMX258=y
++CONFIG_VIDEO_OV5640=y
++CONFIG_VIDEO_OV5648=y
++CONFIG_VIDEO_OV8858=y
++CONFIG_VIDEO_GC2145=y
++CONFIG_VIDEO_DW9714=y
++CONFIG_DRM=y
++CONFIG_DRM_LOAD_EDID_FIRMWARE=y
++CONFIG_DRM_ROCKCHIP=y
++CONFIG_ROCKCHIP_VOP2=y
++CONFIG_ROCKCHIP_ANALOGIX_DP=y
++CONFIG_ROCKCHIP_CDN_DP=y
++CONFIG_ROCKCHIP_DW_HDMI=y
++CONFIG_ROCKCHIP_DW_HDMI_QP=y
++CONFIG_ROCKCHIP_DW_MIPI_DSI=y
++CONFIG_ROCKCHIP_INNO_HDMI=y
++CONFIG_ROCKCHIP_LVDS=y
++CONFIG_ROCKCHIP_RGB=y
++CONFIG_DRM_SUN4I=y
++CONFIG_DRM_PANEL_BOE_TH101MB31UIG002_28A=y
++CONFIG_DRM_PANEL_HIMAX_HX8394=y
++CONFIG_DRM_PANEL_ILITEK_ILI9881C=y
++CONFIG_DRM_PANEL_SITRONIX_ST7703=y
++CONFIG_DRM_PANEL_EDP=y
++CONFIG_DRM_PANEL_SIMPLE=y
++CONFIG_DRM_DISPLAY_CONNECTOR=y
++CONFIG_DRM_SIMPLE_BRIDGE=y
++CONFIG_DRM_CDNS_DSI=y
++CONFIG_DRM_DW_HDMI_AHB_AUDIO=y
++CONFIG_DRM_DW_HDMI_I2S_AUDIO=y
++CONFIG_DRM_DW_HDMI_GP_AUDIO=y
++CONFIG_DRM_DW_HDMI_CEC=y
++CONFIG_DRM_LIMA=y
++CONFIG_DRM_PANFROST=y
++CONFIG_DRM_PANTHOR=y
++CONFIG_FB=y
++CONFIG_FB_SIMPLE=y
++CONFIG_BACKLIGHT_CLASS_DEVICE=y
++CONFIG_BACKLIGHT_PWM=y
++CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
++CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER=y
++CONFIG_LOGO=y
++CONFIG_SOUND=y
++CONFIG_SND=y
++CONFIG_SND_OSSEMUL=y
++CONFIG_SND_MIXER_OSS=y
++CONFIG_SND_PCM_OSS=y
++CONFIG_SND_HRTIMER=y
++CONFIG_SND_DUMMY=y
++CONFIG_SND_ALOOP=y
++# CONFIG_SND_SPI is not set
++CONFIG_SND_USB_AUDIO=y
++CONFIG_SND_SOC=y
++CONFIG_SND_SOC_ROCKCHIP=y
++CONFIG_SND_SOC_ROCKCHIP_I2S=y
++CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=y
++CONFIG_SND_SOC_ROCKCHIP_PDM=y
++CONFIG_SND_SOC_ROCKCHIP_SPDIF=y
++CONFIG_SND_SUN4I_CODEC=y
++CONFIG_SND_SUN8I_CODEC=y
++CONFIG_SND_SUN8I_CODEC_ANALOG=y
++CONFIG_SND_SUN50I_CODEC_ANALOG=y
++CONFIG_SND_SUN4I_I2S=y
++CONFIG_SND_SUN4I_SPDIF=y
++CONFIG_SND_SUN9I_HDMI_AUDIO=y
++CONFIG_SND_SOC_BT_SCO=y
++CONFIG_SND_SOC_DMIC=y
++CONFIG_SND_SOC_EC25=y
++CONFIG_SND_SOC_ES8316=y
++CONFIG_SND_SOC_ES8328_I2C=y
++CONFIG_SND_SOC_MAX98357A=y
++CONFIG_SND_SOC_RK817=y
++CONFIG_SND_SOC_RT5640=y
++CONFIG_SND_SOC_SIMPLE_AMPLIFIER=y
++CONFIG_SND_SOC_SPDIF=y
++CONFIG_SND_SIMPLE_CARD=y
++CONFIG_SND_AUDIO_GRAPH_CARD=y
++CONFIG_HIDRAW=y
++CONFIG_UHID=y
++# CONFIG_HID_A4TECH is not set
++# CONFIG_HID_APPLE is not set
++# CONFIG_HID_BELKIN is not set
++# CONFIG_HID_CHERRY is not set
++# CONFIG_HID_CHICONY is not set
++# CONFIG_HID_CYPRESS is not set
++# CONFIG_HID_EZKEY is not set
++# CONFIG_HID_KENSINGTON is not set
++# CONFIG_HID_LOGITECH is not set
++# CONFIG_HID_REDRAGON is not set
++# CONFIG_HID_MICROSOFT is not set
++# CONFIG_HID_MONTEREY is not set
++CONFIG_HID_MULTITOUCH=y
++CONFIG_USB_HIDDEV=y
++CONFIG_USB_LED_TRIG=y
++CONFIG_USB_ULPI_BUS=y
++CONFIG_USB_CONN_GPIO=y
++CONFIG_USB=y
++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
++CONFIG_USB_OTG=y
++CONFIG_USB_OTG_FSM=y
++CONFIG_USB_LEDS_TRIGGER_USBPORT=y
++CONFIG_USB_MON=y
++CONFIG_USB_XHCI_HCD=y
++CONFIG_USB_EHCI_HCD=y
++CONFIG_USB_EHCI_HCD_PLATFORM=y
++CONFIG_USB_OHCI_HCD=y
++CONFIG_USB_OHCI_HCD_PLATFORM=y
++CONFIG_USB_ACM=y
++CONFIG_USB_PRINTER=y
++CONFIG_USB_STORAGE=y
++CONFIG_USB_UAS=y
++CONFIG_USBIP_CORE=y
++CONFIG_USBIP_VHCI_HCD=y
++CONFIG_USBIP_HOST=y
++CONFIG_USBIP_VUDC=y
++CONFIG_USB_MUSB_HDRC=y
++CONFIG_USB_MUSB_SUNXI=y
++CONFIG_MUSB_PIO_ONLY=y
++CONFIG_USB_DWC3=y
++CONFIG_USB_DWC3_ULPI=y
++CONFIG_USB_DWC2=y
++CONFIG_USB_SERIAL=y
++CONFIG_USB_SERIAL_CONSOLE=y
++CONFIG_USB_SERIAL_GENERIC=y
++CONFIG_USB_SERIAL_SIMPLE=y
++CONFIG_USB_SERIAL_CH341=y
++CONFIG_USB_SERIAL_CP210X=y
++CONFIG_USB_SERIAL_FTDI_SIO=y
++CONFIG_USB_SERIAL_PL2303=y
++CONFIG_USB_SERIAL_QCAUX=y
++CONFIG_USB_SERIAL_QUALCOMM=y
++CONFIG_USB_SERIAL_OPTION=y
++CONFIG_NOP_USB_XCEIV=y
++CONFIG_USB_GADGET=y
++CONFIG_USB_GADGET_VBUS_DRAW=500
++CONFIG_U_SERIAL_CONSOLE=y
++CONFIG_USB_CONFIGFS=y
++CONFIG_USB_CONFIGFS_SERIAL=y
++CONFIG_USB_CONFIGFS_ACM=y
++CONFIG_USB_CONFIGFS_OBEX=y
++CONFIG_USB_CONFIGFS_NCM=y
++CONFIG_USB_CONFIGFS_ECM=y
++CONFIG_USB_CONFIGFS_ECM_SUBSET=y
++CONFIG_USB_CONFIGFS_RNDIS=y
++CONFIG_USB_CONFIGFS_EEM=y
++CONFIG_USB_CONFIGFS_MASS_STORAGE=y
++CONFIG_USB_CONFIGFS_F_LB_SS=y
++CONFIG_USB_CONFIGFS_F_FS=y
++CONFIG_USB_CONFIGFS_F_UAC1=y
++CONFIG_USB_CONFIGFS_F_UAC2=y
++CONFIG_USB_CONFIGFS_F_MIDI=y
++CONFIG_USB_CONFIGFS_F_HID=y
++CONFIG_USB_CONFIGFS_F_UVC=y
++CONFIG_USB_CONFIGFS_F_PRINTER=y
++CONFIG_TYPEC=y
++CONFIG_TYPEC_TCPM=y
++CONFIG_TYPEC_TCPCI=y
++CONFIG_TYPEC_HUSB311=y
++CONFIG_TYPEC_FUSB302=y
++CONFIG_TYPEC_UCSI=y
++CONFIG_TYPEC_ANX7688=y
++CONFIG_TYPEC_EXTCON=y
++CONFIG_TYPEC_DP_ALTMODE=y
++CONFIG_MMC=y
++CONFIG_MMC_SDHCI=y
++CONFIG_MMC_SDHCI_PLTFM=y
++CONFIG_MMC_SDHCI_OF_ARASAN=y
++CONFIG_MMC_SDHCI_OF_DWCMSHC=y
++CONFIG_MMC_DW=y
++CONFIG_MMC_DW_ROCKCHIP=y
++CONFIG_MMC_SUNXI=y
++CONFIG_NEW_LEDS=y
++CONFIG_LEDS_CLASS=y
++CONFIG_LEDS_CLASS_FLASH=y
++CONFIG_LEDS_GPIO=y
++CONFIG_LEDS_PWM=y
++CONFIG_LEDS_REGULATOR=y
++CONFIG_LEDS_SGM3140=y
++CONFIG_LEDS_TRIGGER_TIMER=y
++CONFIG_LEDS_TRIGGER_ONESHOT=y
++CONFIG_LEDS_TRIGGER_HEARTBEAT=y
++CONFIG_LEDS_TRIGGER_CPU=y
++CONFIG_LEDS_TRIGGER_ACTIVITY=y
++CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
++CONFIG_LEDS_TRIGGER_TRANSIENT=y
++CONFIG_LEDS_TRIGGER_CAMERA=y
++CONFIG_LEDS_TRIGGER_PANIC=y
++CONFIG_LEDS_TRIGGER_NETDEV=y
++CONFIG_LEDS_TRIGGER_PATTERN=y
++CONFIG_RTC_CLASS=y
++# CONFIG_RTC_INTF_PROC is not set
++CONFIG_RTC_DRV_HYM8563=y
++CONFIG_RTC_DRV_RK808=y
++CONFIG_RTC_DRV_SUN6I=y
++CONFIG_DMADEVICES=y
++CONFIG_DMA_SUN6I=y
++CONFIG_PL330_DMA=y
++CONFIG_DMABUF_HEAPS=y
++CONFIG_DMABUF_HEAPS_SYSTEM=y
++CONFIG_DMABUF_HEAPS_CMA=y
++# CONFIG_VIRTIO_MENU is not set
++CONFIG_STAGING=y
++CONFIG_STAGING_MEDIA=y
++CONFIG_VIDEO_ROCKCHIP_VDEC=y
++CONFIG_VIDEO_SUNXI=y
++CONFIG_VIDEO_SUNXI_CEDRUS=y
++CONFIG_RTL8723CS=y
++CONFIG_COMMON_CLK_RK808=y
++CONFIG_COMMON_CLK_SCMI=y
++CONFIG_COMMON_CLK_SCPI=y
++CONFIG_COMMON_CLK_PWM=y
++# CONFIG_CLK_RK3308 is not set
++# CONFIG_CLK_RK3328 is not set
++# CONFIG_CLK_RK3368 is not set
++# CONFIG_SUN50I_A100_CCU is not set
++# CONFIG_SUN50I_A100_R_CCU is not set
++# CONFIG_SUN50I_H616_CCU is not set
++# CONFIG_SUN6I_RTC_CCU is not set
++# CONFIG_FSL_ERRATUM_A008585 is not set
++# CONFIG_HISILICON_ERRATUM_161010101 is not set
++CONFIG_MAILBOX=y
++CONFIG_ROCKCHIP_MBOX=y
++CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y
++CONFIG_ROCKCHIP_IOMMU=y
++CONFIG_SUN50I_IOMMU=y
++CONFIG_ARM_SMMU=y
++CONFIG_ARM_SMMU_V3=y
++CONFIG_ROCKCHIP_IODOMAIN=y
++CONFIG_ROCKCHIP_PM_DOMAINS=y
++CONFIG_DEVFREQ_GOV_PERFORMANCE=y
++CONFIG_DEVFREQ_GOV_POWERSAVE=y
++CONFIG_DEVFREQ_GOV_USERSPACE=y
++CONFIG_DEVFREQ_GOV_PASSIVE=y
++CONFIG_ARM_RK3399_DMC_DEVFREQ=y
++CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ=y
++CONFIG_EXTCON_ADC_JACK=y
++CONFIG_EXTCON_GPIO=y
++CONFIG_EXTCON_USB_GPIO=y
++CONFIG_IIO=y
++CONFIG_IIO_BUFFER_CB=y
++CONFIG_IIO_BUFFER_HW_CONSUMER=y
++CONFIG_IIO_SW_DEVICE=y
++CONFIG_IIO_SW_TRIGGER=y
++CONFIG_IIO_ST_ACCEL_3AXIS=y
++# CONFIG_IIO_ST_ACCEL_SPI_3AXIS is not set
++CONFIG_AXP20X_ADC=y
++CONFIG_ROCKCHIP_SARADC=y
++CONFIG_INV_MPU6050_I2C=y
++CONFIG_STK3310=y
++CONFIG_AF8133J=y
++CONFIG_IIO_ST_MAGN_3AXIS=y
++CONFIG_IIO_HRTIMER_TRIGGER=y
++CONFIG_IIO_INTERRUPT_TRIGGER=y
++CONFIG_IIO_SYSFS_TRIGGER=y
++CONFIG_PWM=y
++CONFIG_PWM_ROCKCHIP=y
++CONFIG_PWM_SUN4I=y
++CONFIG_PHY_SUN4I_USB=y
++CONFIG_PHY_SUN50I_USB3=y
++CONFIG_PHY_ROCKCHIP_DP=y
++CONFIG_PHY_ROCKCHIP_DPHY_RX0=y
++CONFIG_PHY_ROCKCHIP_EMMC=y
++CONFIG_PHY_ROCKCHIP_INNO_HDMI=y
++CONFIG_PHY_ROCKCHIP_INNO_USB2=y
++CONFIG_PHY_ROCKCHIP_INNO_CSIDPHY=y
++CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=y
++CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y
++CONFIG_PHY_ROCKCHIP_PCIE=y
++CONFIG_PHY_ROCKCHIP_SAMSUNG_HDPTX=y
++CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y
++CONFIG_PHY_ROCKCHIP_TYPEC=y
++CONFIG_PHY_ROCKCHIP_USB=y
++CONFIG_PHY_ROCKCHIP_USBDP=y
++CONFIG_ARM_CCI_PMU=y
++# CONFIG_ARM_CCI5xx_PMU is not set
++CONFIG_ANDROID_BINDER_IPC=y
++CONFIG_ANDROID_BINDERFS=y
++CONFIG_NVMEM_SUNXI_SID=y
++CONFIG_TEE=y
++CONFIG_OPTEE=y
++CONFIG_VALIDATE_FS_PARSER=y
++CONFIG_EXT4_FS=y
++CONFIG_EXT4_FS_POSIX_ACL=y
++CONFIG_XFS_FS=y
++CONFIG_XFS_POSIX_ACL=y
++CONFIG_BTRFS_FS=y
++CONFIG_BTRFS_FS_POSIX_ACL=y
++CONFIG_F2FS_FS=y
++CONFIG_F2FS_FS_SECURITY=y
++CONFIG_F2FS_CHECK_FS=y
++CONFIG_F2FS_FS_COMPRESSION=y
++CONFIG_FS_ENCRYPTION=y
++CONFIG_FS_ENCRYPTION_INLINE_CRYPT=y
++CONFIG_FANOTIFY=y
++CONFIG_AUTOFS_FS=y
++CONFIG_FUSE_FS=y
++CONFIG_CUSE=y
++CONFIG_OVERLAY_FS=y
++CONFIG_OVERLAY_FS_INDEX=y
++CONFIG_OVERLAY_FS_XINO_AUTO=y
++CONFIG_OVERLAY_FS_METACOPY=y
++CONFIG_ISO9660_FS=y
++CONFIG_JOLIET=y
++CONFIG_ZISOFS=y
++CONFIG_UDF_FS=y
++CONFIG_VFAT_FS=y
++CONFIG_FAT_DEFAULT_UTF8=y
++CONFIG_EXFAT_FS=y
++CONFIG_NTFS3_FS=y
++CONFIG_NTFS3_64BIT_CLUSTER=y
++CONFIG_NTFS3_FS_POSIX_ACL=y
++CONFIG_PROC_CHILDREN=y
++CONFIG_TMPFS=y
++CONFIG_TMPFS_POSIX_ACL=y
++CONFIG_TMPFS_INODE64=y
++CONFIG_HUGETLBFS=y
++CONFIG_ECRYPT_FS=y
++CONFIG_ECRYPT_FS_MESSAGING=y
++CONFIG_SQUASHFS=y
++CONFIG_SQUASHFS_FILE_DIRECT=y
++CONFIG_SQUASHFS_CHOICE_DECOMP_BY_MOUNT=y
++CONFIG_SQUASHFS_XATTR=y
++CONFIG_SQUASHFS_LZ4=y
++CONFIG_SQUASHFS_LZO=y
++CONFIG_SQUASHFS_XZ=y
++CONFIG_SQUASHFS_ZSTD=y
++CONFIG_NFS_FS=y
++# CONFIG_NFS_V3 is not set
++CONFIG_NFS_V4=y
++CONFIG_NFS_V4_1=y
++CONFIG_NFS_V4_2=y
++CONFIG_NFS_FSCACHE=y
++CONFIG_NFSD=y
++CONFIG_NFSD_V3_ACL=y
++CONFIG_NFSD_V4=y
++# CONFIG_NFSD_LEGACY_CLIENT_TRACKING is not set
++CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA2=y
++CONFIG_CIFS=y
++# CONFIG_CIFS_STATS2 is not set
++CONFIG_CIFS_XATTR=y
++CONFIG_CIFS_POSIX=y
++# CONFIG_CIFS_DEBUG is not set
++CONFIG_CIFS_DFS_UPCALL=y
++CONFIG_CIFS_SWN_UPCALL=y
++CONFIG_CIFS_FSCACHE=y
++CONFIG_NLS_CODEPAGE_437=y
++CONFIG_NLS_CODEPAGE_852=y
++CONFIG_NLS_ISO8859_1=y
++CONFIG_NLS_ISO8859_2=y
++CONFIG_NLS_UTF8=y
++CONFIG_KEYS_REQUEST_CACHE=y
++CONFIG_PERSISTENT_KEYRINGS=y
++CONFIG_BIG_KEYS=y
++CONFIG_TRUSTED_KEYS=y
++CONFIG_ENCRYPTED_KEYS=y
++CONFIG_KEY_DH_OPERATIONS=y
++CONFIG_SECURITY=y
++# CONFIG_INTEGRITY is not set
++CONFIG_LSM="yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor"
++CONFIG_INIT_STACK_NONE=y
++CONFIG_CRYPTO_USER=y
++CONFIG_CRYPTO_PCRYPT=y
++CONFIG_CRYPTO_CRYPTD=y
++CONFIG_CRYPTO_ECDSA=y
++CONFIG_CRYPTO_CURVE25519=y
++CONFIG_CRYPTO_ARC4=y
++CONFIG_CRYPTO_CHACHA20POLY1305=y
++CONFIG_CRYPTO_SEQIV=y
++CONFIG_CRYPTO_ECHAINIV=y
++CONFIG_CRYPTO_MD4=y
++CONFIG_CRYPTO_DEFLATE=y
++CONFIG_CRYPTO_ZSTD=y
++CONFIG_CRYPTO_ANSI_CPRNG=y
++CONFIG_CRYPTO_USER_API_HASH=y
++CONFIG_CRYPTO_USER_API_SKCIPHER=y
++CONFIG_CRYPTO_USER_API_RNG=y
++CONFIG_CRYPTO_USER_API_AEAD=y
++CONFIG_CRYPTO_NHPOLY1305_NEON=y
++CONFIG_CRYPTO_GHASH_ARM64_CE=y
++CONFIG_CRYPTO_SHA1_ARM64_CE=y
++CONFIG_CRYPTO_SHA2_ARM64_CE=y
++CONFIG_CRYPTO_SHA512_ARM64_CE=y
++CONFIG_CRYPTO_SHA3_ARM64=y
++CONFIG_CRYPTO_SM3_ARM64_CE=y
++CONFIG_CRYPTO_AES_ARM64=y
++CONFIG_CRYPTO_AES_ARM64_BS=y
++CONFIG_CRYPTO_SM4_ARM64_CE=y
++CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
++CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y
++CONFIG_CRYPTO_DEV_SUN4I_SS=y
++CONFIG_CRYPTO_DEV_SUN4I_SS_PRNG=y
++CONFIG_CRYPTO_DEV_SUN4I_SS_DEBUG=y
++CONFIG_CRYPTO_DEV_SUN8I_CE=y
++CONFIG_CRYPTO_DEV_SUN8I_CE_DEBUG=y
++CONFIG_CRYPTO_DEV_SUN8I_CE_HASH=y
++CONFIG_CRYPTO_DEV_SUN8I_CE_PRNG=y
++CONFIG_CRYPTO_DEV_SUN8I_CE_TRNG=y
++CONFIG_CRYPTO_DEV_SUN8I_SS=y
++CONFIG_CRYPTO_DEV_SUN8I_SS_DEBUG=y
++CONFIG_CRYPTO_DEV_SUN8I_SS_PRNG=y
++CONFIG_CRYPTO_DEV_SUN8I_SS_HASH=y
++CONFIG_CRYPTO_DEV_ROCKCHIP=y
++CONFIG_CRYPTO_DEV_ROCKCHIP_DEBUG=y
++CONFIG_PKCS8_PRIVATE_KEY_PARSER=y
++# CONFIG_RAID6_PQ_BENCHMARK is not set
++CONFIG_CORDIC=y
++CONFIG_DMA_CMA=y
++CONFIG_DMA_NUMA_CMA=y
++CONFIG_CMA_SIZE_MBYTES=64
++CONFIG_FONTS=y
++CONFIG_FONT_8x8=y
++CONFIG_FONT_8x16=y
++CONFIG_FONT_SUN12x22=y
++CONFIG_FONT_TER16x32=y
++CONFIG_CONSOLE_LOGLEVEL_DEFAULT=15
++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
++CONFIG_DYNAMIC_DEBUG=y
++CONFIG_DEBUG_KERNEL=y
++CONFIG_FRAME_WARN=1024
++CONFIG_MAGIC_SYSRQ=y
++CONFIG_PER_VMA_LOCK_STATS=y
++CONFIG_PANIC_ON_OOPS=y
++CONFIG_SOFTLOCKUP_DETECTOR=y
++CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y
++CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y
++CONFIG_WQ_WATCHDOG=y
++CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=20
++# CONFIG_RCU_TRACE is not set
++# CONFIG_FTRACE is not set
++# CONFIG_STRICT_DEVMEM is not set
++# CONFIG_RUNTIME_TESTING_MENU is not set
+diff --git a/arch/arm64/configs/pinephone_defconfig b/arch/arm64/configs/pinephone_defconfig
+new file mode 100644
+index 000000000000..51c8740d56e7
+--- /dev/null
++++ b/arch/arm64/configs/pinephone_defconfig
+@@ -0,0 +1,650 @@
++CONFIG_SYSVIPC=y
++CONFIG_POSIX_MQUEUE=y
++CONFIG_NO_HZ=y
++CONFIG_HIGH_RES_TIMERS=y
++CONFIG_BPF_SYSCALL=y
++CONFIG_BPF_JIT=y
++CONFIG_BPF_JIT_ALWAYS_ON=y
++# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set
++CONFIG_PREEMPT=y
++CONFIG_BSD_PROCESS_ACCT=y
++CONFIG_BSD_PROCESS_ACCT_V3=y
++CONFIG_TASKSTATS=y
++CONFIG_TASK_DELAY_ACCT=y
++CONFIG_TASK_XACCT=y
++CONFIG_TASK_IO_ACCOUNTING=y
++CONFIG_PSI=y
++CONFIG_LOG_BUF_SHIFT=19
++CONFIG_MEMCG=y
++CONFIG_BLK_CGROUP=y
++CONFIG_CFS_BANDWIDTH=y
++CONFIG_RT_GROUP_SCHED=y
++CONFIG_CGROUP_PIDS=y
++CONFIG_CGROUP_FREEZER=y
++CONFIG_CPUSETS=y
++# CONFIG_PROC_PID_CPUSET is not set
++CONFIG_CGROUP_DEVICE=y
++CONFIG_CGROUP_CPUACCT=y
++CONFIG_CGROUP_BPF=y
++CONFIG_USER_NS=y
++CONFIG_SCHED_AUTOGROUP=y
++# CONFIG_RD_GZIP is not set
++# CONFIG_RD_BZIP2 is not set
++# CONFIG_RD_LZMA is not set
++# CONFIG_RD_XZ is not set
++# CONFIG_RD_LZO is not set
++# CONFIG_RD_ZSTD is not set
++CONFIG_PERF_EVENTS=y
++CONFIG_ARCH_SUNXI=y
++# CONFIG_ARM64_ERRATUM_832075 is not set
++# CONFIG_ARM64_ERRATUM_1024718 is not set
++# CONFIG_ARM64_ERRATUM_1418040 is not set
++# CONFIG_ARM64_ERRATUM_1165522 is not set
++# CONFIG_ARM64_ERRATUM_1319367 is not set
++# CONFIG_ARM64_ERRATUM_1530923 is not set
++CONFIG_ARM64_ERRATUM_2441007=y
++# CONFIG_ARM64_ERRATUM_1463225 is not set
++# CONFIG_ARM64_ERRATUM_2051678 is not set
++# CONFIG_ARM64_ERRATUM_2077057 is not set
++CONFIG_ARM64_ERRATUM_2441009=y
++# CONFIG_CAVIUM_ERRATUM_22375 is not set
++# CONFIG_CAVIUM_ERRATUM_23154 is not set
++# CONFIG_CAVIUM_ERRATUM_27456 is not set
++# CONFIG_CAVIUM_ERRATUM_30115 is not set
++# CONFIG_CAVIUM_TX2_ERRATUM_219 is not set
++# CONFIG_FUJITSU_ERRATUM_010001 is not set
++# CONFIG_HISILICON_ERRATUM_161600802 is not set
++# CONFIG_QCOM_FALKOR_ERRATUM_1003 is not set
++# CONFIG_QCOM_FALKOR_ERRATUM_1009 is not set
++# CONFIG_QCOM_QDF2400_ERRATUM_0065 is not set
++# CONFIG_QCOM_FALKOR_ERRATUM_E1041 is not set
++# CONFIG_SOCIONEXT_SYNQUACER_PREITS is not set
++CONFIG_ARM64_VA_BITS_39=y
++CONFIG_SCHED_MC=y
++CONFIG_NR_CPUS=4
++CONFIG_HZ_100=y
++CONFIG_COMPAT=y
++# CONFIG_ARM64_HW_AFDBM is not set
++# CONFIG_ARM64_PAN is not set
++# CONFIG_ARM64_USE_LSE_ATOMICS is not set
++# CONFIG_ARM64_RAS_EXTN is not set
++# CONFIG_ARM64_CNP is not set
++# CONFIG_ARM64_PTR_AUTH is not set
++# CONFIG_ARM64_AMU_EXTN is not set
++# CONFIG_ARM64_TLB_RANGE is not set
++# CONFIG_ARM64_BTI is not set
++# CONFIG_ARM64_E0PD is not set
++# CONFIG_ARM64_SVE is not set
++# CONFIG_EFI is not set
++CONFIG_PM_AUTOSLEEP=y
++CONFIG_PM_WAKELOCKS=y
++CONFIG_PM_DEBUG=y
++CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
++CONFIG_ENERGY_MODEL=y
++CONFIG_CPU_IDLE=y
++CONFIG_CPU_IDLE_GOV_LADDER=y
++CONFIG_CPU_IDLE_GOV_MENU=y
++CONFIG_CPU_IDLE_GOV_TEO=y
++CONFIG_ARM_PSCI_CPUIDLE=y
++CONFIG_CPU_FREQ=y
++CONFIG_CPU_FREQ_STAT=y
++CONFIG_CPU_FREQ_GOV_POWERSAVE=y
++CONFIG_CPU_FREQ_GOV_USERSPACE=y
++CONFIG_CPU_FREQ_GOV_ONDEMAND=y
++CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
++CONFIG_CPUFREQ_DT=y
++CONFIG_JUMP_LABEL=y
++# CONFIG_STACKPROTECTOR is not set
++# CONFIG_GCC_PLUGINS is not set
++CONFIG_MODULES=y
++CONFIG_MODULE_UNLOAD=y
++CONFIG_MODVERSIONS=y
++CONFIG_BLK_DEV_THROTTLING=y
++CONFIG_BLK_WBT=y
++CONFIG_BLK_CGROUP_IOLATENCY=y
++CONFIG_BLK_CGROUP_IOCOST=y
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_MQ_IOSCHED_DEADLINE is not set
++# CONFIG_MQ_IOSCHED_KYBER is not set
++CONFIG_CMA=y
++CONFIG_CMA_DEBUGFS=y
++CONFIG_CMA_AREAS=7
++CONFIG_NET=y
++CONFIG_PACKET=y
++CONFIG_PACKET_DIAG=y
++CONFIG_UNIX=y
++CONFIG_UNIX_DIAG=y
++CONFIG_XFRM_USER=y
++CONFIG_NET_KEY=m
++CONFIG_INET=y
++CONFIG_IP_MULTICAST=y
++CONFIG_IP_ADVANCED_ROUTER=y
++CONFIG_SYN_COOKIES=y
++# CONFIG_INET_DIAG is not set
++# CONFIG_IPV6_SIT is not set
++CONFIG_MPTCP=y
++CONFIG_NETFILTER=y
++CONFIG_NETFILTER_NETLINK_QUEUE=m
++CONFIG_NETFILTER_NETLINK_LOG=m
++CONFIG_NF_CONNTRACK=m
++CONFIG_NF_CONNTRACK_MARK=y
++# CONFIG_NF_CT_PROTO_DCCP is not set
++# CONFIG_NF_CT_PROTO_SCTP is not set
++# CONFIG_NF_CT_PROTO_UDPLITE is not set
++CONFIG_NF_CONNTRACK_FTP=m
++CONFIG_NF_CONNTRACK_H323=m
++CONFIG_NF_CONNTRACK_IRC=m
++CONFIG_NF_CONNTRACK_NETBIOS_NS=m
++CONFIG_NF_CONNTRACK_SNMP=m
++CONFIG_NF_CONNTRACK_PPTP=m
++CONFIG_NF_CONNTRACK_SIP=m
++CONFIG_NF_CONNTRACK_TFTP=m
++CONFIG_NF_CT_NETLINK=m
++CONFIG_NETFILTER_NETLINK_GLUE_CT=y
++CONFIG_NF_TABLES=m
++CONFIG_NF_TABLES_INET=y
++CONFIG_NF_TABLES_NETDEV=y
++CONFIG_NFT_NUMGEN=m
++CONFIG_NFT_CT=m
++CONFIG_NFT_CONNLIMIT=m
++CONFIG_NFT_LOG=m
++CONFIG_NFT_LIMIT=m
++CONFIG_NFT_MASQ=m
++CONFIG_NFT_REDIR=m
++CONFIG_NFT_NAT=m
++CONFIG_NFT_TUNNEL=m
++CONFIG_NFT_QUEUE=m
++CONFIG_NFT_QUOTA=m
++CONFIG_NFT_REJECT=m
++CONFIG_NFT_HASH=m
++CONFIG_NFT_FIB_INET=m
++CONFIG_NFT_SOCKET=m
++CONFIG_NFT_OSF=m
++CONFIG_NFT_DUP_NETDEV=m
++CONFIG_NFT_FWD_NETDEV=m
++CONFIG_NF_FLOW_TABLE_INET=m
++CONFIG_NF_FLOW_TABLE=m
++CONFIG_IP_SET=m
++CONFIG_IP_SET_BITMAP_IP=m
++CONFIG_IP_SET_BITMAP_IPMAC=m
++CONFIG_IP_SET_BITMAP_PORT=m
++CONFIG_IP_SET_HASH_IP=m
++CONFIG_IP_SET_HASH_IPMARK=m
++CONFIG_IP_SET_HASH_IPPORT=m
++CONFIG_IP_SET_HASH_IPPORTIP=m
++CONFIG_IP_SET_HASH_IPPORTNET=m
++CONFIG_IP_SET_HASH_IPMAC=m
++CONFIG_IP_SET_HASH_MAC=m
++CONFIG_IP_SET_HASH_NETPORTNET=m
++CONFIG_IP_SET_HASH_NET=m
++CONFIG_IP_SET_HASH_NETNET=m
++CONFIG_IP_SET_HASH_NETPORT=m
++CONFIG_IP_SET_HASH_NETIFACE=m
++CONFIG_IP_SET_LIST_SET=m
++CONFIG_NFT_FIB_IPV4=m
++CONFIG_NF_TABLES_ARP=y
++CONFIG_NF_LOG_ARP=m
++CONFIG_NF_LOG_IPV4=m
++# CONFIG_NF_NAT_SNMP_BASIC is not set
++CONFIG_NFT_DUP_IPV6=m
++CONFIG_NFT_FIB_IPV6=m
++CONFIG_NF_LOG_IPV6=m
++CONFIG_BRIDGE=y
++CONFIG_NET_SCHED=y
++CONFIG_NET_SCH_HTB=m
++CONFIG_NET_CLS_BASIC=m
++CONFIG_NET_CLS_ROUTE4=m
++CONFIG_NET_CLS_FW=m
++CONFIG_NET_CLS_CGROUP=m
++CONFIG_NET_CLS_ACT=y
++CONFIG_NET_ACT_POLICE=m
++CONFIG_NET_ACT_GACT=m
++CONFIG_NET_ACT_MIRRED=m
++CONFIG_NETLINK_DIAG=m
++CONFIG_BT=m
++CONFIG_BT_RFCOMM=m
++CONFIG_BT_RFCOMM_TTY=y
++CONFIG_BT_BNEP=m
++CONFIG_BT_BNEP_MC_FILTER=y
++CONFIG_BT_BNEP_PROTO_FILTER=y
++CONFIG_BT_HIDP=m
++CONFIG_BT_LEDS=y
++CONFIG_BT_HCIUART=m
++CONFIG_BT_HCIUART_RTL=y
++CONFIG_CFG80211=m
++CONFIG_CFG80211_DEBUGFS=y
++CONFIG_CFG80211_WEXT=y
++CONFIG_MAC80211=m
++CONFIG_MAC80211_LEDS=y
++CONFIG_RFKILL=m
++CONFIG_RFKILL_GPIO=m
++CONFIG_PAGE_POOL_STATS=y
++CONFIG_UEVENT_HELPER=y
++CONFIG_DEVTMPFS=y
++CONFIG_DEVTMPFS_MOUNT=y
++#CONFIG_EXTRA_FIRMWARE="regulatory.db regulatory.db.p7s anx7688-fw.bin rtl_bt/rtl8723cs_xx_config.bin rtl_bt/rtl8723cs_xx_fw.bin ov5640_af.bin rtw88/rtw8703b_wow_fw.bin rtw88/rtw8703b_fw.bin"
++#CONFIG_EXTRA_FIRMWARE_DIR="/workspace/megous.com/orangepi-pc/firmware"
++CONFIG_ARM_SCPI_PROTOCOL=y
++# CONFIG_ARM_SMCCC_SOC_ID is not set
++CONFIG_ZRAM=m
++CONFIG_ZRAM_WRITEBACK=y
++CONFIG_ZRAM_MEMORY_TRACKING=y
++CONFIG_BLK_DEV_LOOP=m
++CONFIG_BLK_DEV_NBD=m
++CONFIG_PPKB_POWER_MANAGER=y
++CONFIG_MODEM_POWER=m
++CONFIG_SCSI=m
++CONFIG_BLK_DEV_SD=m
++# CONFIG_BLK_DEV_BSG is not set
++# CONFIG_SCSI_LOWLEVEL is not set
++CONFIG_MD=y
++CONFIG_BLK_DEV_DM=y
++CONFIG_DM_CRYPT=y
++CONFIG_DM_INIT=y
++CONFIG_DM_UEVENT=y
++CONFIG_NETDEVICES=y
++CONFIG_WIREGUARD=m
++CONFIG_TUN=m
++CONFIG_VETH=m
++# CONFIG_ETHERNET is not set
++CONFIG_PPP=m
++CONFIG_PPP_BSDCOMP=m
++CONFIG_PPP_DEFLATE=m
++CONFIG_PPP_FILTER=y
++CONFIG_PPP_MPPE=m
++CONFIG_USB_RTL8152=m
++CONFIG_USB_USBNET=m
++# CONFIG_USB_NET_AX8817X is not set
++# CONFIG_USB_NET_AX88179_178A is not set
++CONFIG_USB_NET_CDC_EEM=m
++CONFIG_USB_NET_CDC_MBIM=m
++# CONFIG_USB_NET_NET1080 is not set
++# CONFIG_USB_NET_CDC_SUBSET is not set
++# CONFIG_USB_NET_ZAURUS is not set
++CONFIG_USB_NET_QMI_WWAN=m
++# CONFIG_WLAN_VENDOR_ADMTEK is not set
++# CONFIG_WLAN_VENDOR_ATH is not set
++# CONFIG_WLAN_VENDOR_ATMEL is not set
++# CONFIG_WLAN_VENDOR_BROADCOM is not set
++# CONFIG_WLAN_VENDOR_INTEL is not set
++# CONFIG_WLAN_VENDOR_INTERSIL is not set
++# CONFIG_WLAN_VENDOR_MARVELL is not set
++# CONFIG_WLAN_VENDOR_MEDIATEK is not set
++# CONFIG_WLAN_VENDOR_MICROCHIP is not set
++# CONFIG_WLAN_VENDOR_PURELIFI is not set
++# CONFIG_WLAN_VENDOR_RALINK is not set
++# CONFIG_WLAN_VENDOR_REALTEK is not set
++# CONFIG_WLAN_VENDOR_RSI is not set
++# CONFIG_WLAN_VENDOR_SILABS is not set
++# CONFIG_WLAN_VENDOR_ST is not set
++# CONFIG_WLAN_VENDOR_TI is not set
++# CONFIG_WLAN_VENDOR_ZYDAS is not set
++# CONFIG_WLAN_VENDOR_QUANTENNA is not set
++CONFIG_INPUT_MOUSEDEV=m
++CONFIG_INPUT_MOUSEDEV_PSAUX=y
++CONFIG_INPUT_EVDEV=y
++# CONFIG_KEYBOARD_ATKBD is not set
++CONFIG_KEYBOARD_GPIO=y
++CONFIG_KEYBOARD_GPIO_POLLED=y
++CONFIG_KEYBOARD_PINEPHONE=y
++CONFIG_KEYBOARD_SUN4I_LRADC=y
++# CONFIG_INPUT_MOUSE is not set
++CONFIG_INPUT_TOUCHSCREEN=y
++CONFIG_TOUCHSCREEN_GOODIX=m
++CONFIG_INPUT_MISC=y
++CONFIG_INPUT_GPIO_VIBRA=y
++CONFIG_INPUT_AXP20X_PEK=y
++CONFIG_INPUT_UINPUT=y
++# CONFIG_SERIO is not set
++# CONFIG_LEGACY_PTYS is not set
++CONFIG_SERIAL_8250=y
++# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
++CONFIG_SERIAL_8250_CONSOLE=y
++CONFIG_SERIAL_8250_NR_UARTS=8
++CONFIG_SERIAL_8250_RUNTIME_UARTS=8
++CONFIG_SERIAL_8250_DW=y
++CONFIG_SERIAL_OF_PLATFORM=y
++CONFIG_SERIAL_DEV_BUS=y
++# CONFIG_HW_RANDOM is not set
++CONFIG_I2C_CHARDEV=y
++CONFIG_I2C_MUX=y
++CONFIG_I2C_GPIO=y
++CONFIG_I2C_MV64XXX=y
++CONFIG_PINCTRL_AXP209=y
++CONFIG_PINCTRL_SINGLE=y
++# CONFIG_PINCTRL_SUN8I_H3_R is not set
++# CONFIG_PINCTRL_SUN50I_H5 is not set
++# CONFIG_PINCTRL_SUN50I_H6 is not set
++# CONFIG_PINCTRL_SUN50I_H6_R is not set
++# CONFIG_PINCTRL_SUN50I_H616 is not set
++# CONFIG_PINCTRL_SUN50I_H616_R is not set
++CONFIG_NVMEM_REBOOT_MODE=y
++CONFIG_IP5XXX_POWER=y
++CONFIG_CHARGER_AXP20X=y
++CONFIG_BATTERY_AXP20X=y
++CONFIG_AXP20X_POWER=y
++# CONFIG_HWMON is not set
++CONFIG_THERMAL=y
++CONFIG_THERMAL_STATISTICS=y
++CONFIG_THERMAL_GOV_FAIR_SHARE=y
++CONFIG_THERMAL_GOV_BANG_BANG=y
++CONFIG_CPU_THERMAL=y
++CONFIG_SUN8I_THERMAL=y
++CONFIG_MFD_SUN4I_GPADC=y
++CONFIG_MFD_AXP20X_RSB=y
++CONFIG_MFD_SUN6I_PRCM=y
++CONFIG_REGULATOR=y
++CONFIG_REGULATOR_FIXED_VOLTAGE=y
++CONFIG_REGULATOR_AXP20X=y
++CONFIG_REGULATOR_GPIO=y
++CONFIG_MEDIA_SUPPORT=m
++# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
++CONFIG_MEDIA_CAMERA_SUPPORT=y
++CONFIG_MEDIA_PLATFORM_SUPPORT=y
++CONFIG_V4L2_FLASH_LED_CLASS=m
++CONFIG_V4L_PLATFORM_DRIVERS=y
++CONFIG_V4L_MEM2MEM_DRIVERS=y
++CONFIG_VIDEO_MEM2MEM_DEINTERLACE=m
++CONFIG_VIDEO_SUN6I_CSI=m
++CONFIG_VIDEO_SUN8I_DEINTERLACE=m
++CONFIG_VIDEO_SUN8I_ROTATE=m
++CONFIG_VIDEO_OV5640=m
++CONFIG_VIDEO_GC2145=m
++CONFIG_DRM=y
++CONFIG_DRM_LOAD_EDID_FIRMWARE=y
++CONFIG_DRM_SUN4I=y
++CONFIG_DRM_PANEL_ILITEK_ILI9881C=y
++CONFIG_DRM_PANEL_SITRONIX_ST7703=y
++CONFIG_DRM_DW_HDMI_AHB_AUDIO=m
++CONFIG_DRM_DW_HDMI_I2S_AUDIO=m
++CONFIG_DRM_DW_HDMI_CEC=y
++CONFIG_DRM_LIMA=m
++CONFIG_FB=y
++CONFIG_FB_SIMPLE=y
++CONFIG_BACKLIGHT_CLASS_DEVICE=y
++CONFIG_BACKLIGHT_PWM=y
++CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
++CONFIG_SOUND=m
++CONFIG_SND=m
++CONFIG_SND_OSSEMUL=y
++CONFIG_SND_MIXER_OSS=m
++CONFIG_SND_PCM_OSS=m
++CONFIG_SND_HRTIMER=m
++# CONFIG_SND_SUPPORT_OLD_API is not set
++CONFIG_SND_SEQUENCER=m
++CONFIG_SND_SEQ_DUMMY=m
++CONFIG_SND_SEQUENCER_OSS=m
++CONFIG_SND_ALOOP=m
++CONFIG_SND_USB_AUDIO=m
++CONFIG_SND_SOC=m
++CONFIG_SND_SUN4I_CODEC=m
++CONFIG_SND_SUN8I_CODEC=m
++CONFIG_SND_SUN8I_CODEC_ANALOG=m
++CONFIG_SND_SUN50I_CODEC_ANALOG=m
++CONFIG_SND_SUN4I_I2S=m
++CONFIG_SND_SUN4I_SPDIF=m
++CONFIG_SND_SUN9I_HDMI_AUDIO=m
++CONFIG_SND_SOC_BT_SCO=m
++CONFIG_SND_SOC_EC25=m
++CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m
++CONFIG_SND_SIMPLE_CARD=m
++CONFIG_SND_AUDIO_GRAPH_CARD=m
++CONFIG_HID=m
++# CONFIG_HID_A4TECH is not set
++# CONFIG_HID_APPLE is not set
++# CONFIG_HID_BELKIN is not set
++# CONFIG_HID_CHERRY is not set
++# CONFIG_HID_CHICONY is not set
++# CONFIG_HID_CYPRESS is not set
++# CONFIG_HID_EZKEY is not set
++# CONFIG_HID_ITE is not set
++# CONFIG_HID_KENSINGTON is not set
++# CONFIG_HID_LOGITECH is not set
++# CONFIG_HID_REDRAGON is not set
++# CONFIG_HID_MICROSOFT is not set
++# CONFIG_HID_MONTEREY is not set
++CONFIG_USB_HIDDEV=y
++CONFIG_USB_LED_TRIG=y
++CONFIG_USB=m
++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
++CONFIG_USB_OTG=y
++CONFIG_USB_OTG_FSM=m
++CONFIG_USB_LEDS_TRIGGER_USBPORT=m
++CONFIG_USB_MON=m
++CONFIG_USB_EHCI_HCD=m
++CONFIG_USB_EHCI_HCD_PLATFORM=m
++CONFIG_USB_OHCI_HCD=m
++CONFIG_USB_OHCI_HCD_PLATFORM=m
++CONFIG_USB_ACM=m
++CONFIG_USB_STORAGE=m
++CONFIG_USB_UAS=m
++CONFIG_USBIP_CORE=m
++CONFIG_USBIP_VHCI_HCD=m
++CONFIG_USBIP_HOST=m
++CONFIG_USBIP_VUDC=m
++CONFIG_USB_MUSB_HDRC=m
++CONFIG_USB_MUSB_SUNXI=m
++CONFIG_MUSB_PIO_ONLY=y
++CONFIG_USB_SERIAL=m
++CONFIG_USB_SERIAL_SIMPLE=m
++CONFIG_USB_SERIAL_CH341=m
++CONFIG_USB_SERIAL_CP210X=m
++CONFIG_USB_SERIAL_FTDI_SIO=m
++CONFIG_USB_SERIAL_QCAUX=m
++CONFIG_USB_SERIAL_QUALCOMM=m
++CONFIG_USB_SERIAL_OPTION=m
++CONFIG_NOP_USB_XCEIV=m
++CONFIG_USB_GADGET=m
++CONFIG_USB_GADGET_VBUS_DRAW=500
++CONFIG_U_SERIAL_CONSOLE=y
++CONFIG_USB_CONFIGFS=m
++CONFIG_USB_CONFIGFS_SERIAL=y
++CONFIG_USB_CONFIGFS_ACM=y
++CONFIG_USB_CONFIGFS_OBEX=y
++CONFIG_USB_CONFIGFS_NCM=y
++CONFIG_USB_CONFIGFS_ECM=y
++CONFIG_USB_CONFIGFS_ECM_SUBSET=y
++CONFIG_USB_CONFIGFS_RNDIS=y
++CONFIG_USB_CONFIGFS_EEM=y
++CONFIG_USB_CONFIGFS_MASS_STORAGE=y
++CONFIG_USB_CONFIGFS_F_LB_SS=y
++CONFIG_USB_CONFIGFS_F_FS=y
++CONFIG_USB_CONFIGFS_F_UAC1=y
++CONFIG_USB_CONFIGFS_F_UAC2=y
++CONFIG_USB_CONFIGFS_F_MIDI=y
++CONFIG_USB_CONFIGFS_F_HID=y
++CONFIG_USB_CONFIGFS_F_UVC=y
++CONFIG_USB_CONFIGFS_F_PRINTER=y
++CONFIG_USB_AUDIO=m
++CONFIG_USB_ETH=m
++CONFIG_USB_ETH_EEM=y
++CONFIG_USB_G_NCM=m
++CONFIG_USB_GADGETFS=m
++CONFIG_USB_FUNCTIONFS=m
++CONFIG_USB_FUNCTIONFS_ETH=y
++CONFIG_USB_FUNCTIONFS_RNDIS=y
++CONFIG_USB_FUNCTIONFS_GENERIC=y
++CONFIG_USB_MASS_STORAGE=m
++CONFIG_USB_G_SERIAL=m
++CONFIG_USB_MIDI_GADGET=m
++CONFIG_USB_G_PRINTER=m
++CONFIG_USB_CDC_COMPOSITE=m
++CONFIG_USB_G_ACM_MS=m
++CONFIG_USB_G_MULTI=m
++CONFIG_USB_G_MULTI_CDC=y
++CONFIG_USB_G_HID=m
++CONFIG_USB_G_WEBCAM=m
++CONFIG_USB_RAW_GADGET=m
++CONFIG_TYPEC=y
++CONFIG_TYPEC_ANX7688=y
++CONFIG_TYPEC_DP_ALTMODE=y
++CONFIG_MMC=y
++CONFIG_MMC_SUNXI=y
++CONFIG_NEW_LEDS=y
++CONFIG_LEDS_CLASS=y
++CONFIG_LEDS_CLASS_FLASH=y
++CONFIG_LEDS_CLASS_MULTICOLOR=y
++CONFIG_LEDS_GPIO=y
++CONFIG_LEDS_SGM3140=m
++CONFIG_LEDS_GROUP_MULTICOLOR=m
++CONFIG_LEDS_TRIGGER_TIMER=y
++CONFIG_LEDS_TRIGGER_ONESHOT=y
++CONFIG_LEDS_TRIGGER_HEARTBEAT=y
++CONFIG_LEDS_TRIGGER_CPU=y
++CONFIG_LEDS_TRIGGER_ACTIVITY=y
++CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
++CONFIG_LEDS_TRIGGER_TRANSIENT=m
++CONFIG_LEDS_TRIGGER_CAMERA=m
++CONFIG_LEDS_TRIGGER_PANIC=y
++CONFIG_LEDS_TRIGGER_NETDEV=y
++CONFIG_LEDS_TRIGGER_PATTERN=y
++CONFIG_RTC_CLASS=y
++# CONFIG_RTC_INTF_PROC is not set
++CONFIG_RTC_DRV_SUN6I=y
++CONFIG_DMADEVICES=y
++CONFIG_DMA_SUN6I=y
++CONFIG_DMABUF_HEAPS=y
++CONFIG_DMABUF_HEAPS_SYSTEM=y
++CONFIG_DMABUF_HEAPS_CMA=y
++# CONFIG_VIRTIO_MENU is not set
++# CONFIG_VHOST_MENU is not set
++CONFIG_STAGING=y
++CONFIG_STAGING_MEDIA=y
++CONFIG_VIDEO_SUNXI=y
++CONFIG_VIDEO_SUNXI_CEDRUS=m
++CONFIG_RTL8723CS=m
++# CONFIG_SUN50I_H6_CCU is not set
++# CONFIG_SUN50I_H616_CCU is not set
++# CONFIG_SUN50I_H6_R_CCU is not set
++# CONFIG_SUN8I_H3_CCU is not set
++# CONFIG_HISILICON_ERRATUM_161010101 is not set
++# CONFIG_ARM64_ERRATUM_858921 is not set
++CONFIG_MAILBOX=y
++CONFIG_IOMMU_IO_PGTABLE_LPAE=y
++CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
++CONFIG_DEVFREQ_GOV_PERFORMANCE=m
++CONFIG_DEVFREQ_GOV_POWERSAVE=m
++CONFIG_DEVFREQ_GOV_USERSPACE=m
++CONFIG_DEVFREQ_GOV_PASSIVE=m
++CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ=m
++CONFIG_PM_DEVFREQ_EVENT=y
++CONFIG_IIO=y
++CONFIG_IIO_BUFFER_CB=m
++CONFIG_IIO_BUFFER_HW_CONSUMER=m
++CONFIG_IIO_SW_DEVICE=m
++CONFIG_IIO_SW_TRIGGER=m
++CONFIG_AXP20X_ADC=y
++CONFIG_INV_MPU6050_I2C=m
++CONFIG_STK3310=m
++CONFIG_AF8133J=m
++CONFIG_IIO_ST_MAGN_3AXIS=m
++CONFIG_IIO_HRTIMER_TRIGGER=m
++CONFIG_IIO_INTERRUPT_TRIGGER=m
++CONFIG_IIO_SYSFS_TRIGGER=m
++CONFIG_PWM=y
++CONFIG_PWM_SUN4I=y
++CONFIG_PHY_SUN4I_USB=y
++CONFIG_ARM_CCI_PMU=y
++# CONFIG_ARM_CCI5xx_PMU is not set
++CONFIG_ANDROID_BINDER_IPC=y
++CONFIG_ANDROID_BINDERFS=y
++CONFIG_NVMEM_SUNXI_SID=y
++CONFIG_VALIDATE_FS_PARSER=y
++CONFIG_EXT4_FS=y
++CONFIG_EXT4_FS_POSIX_ACL=y
++CONFIG_XFS_FS=m
++CONFIG_XFS_POSIX_ACL=y
++CONFIG_BTRFS_FS=y
++CONFIG_BTRFS_FS_POSIX_ACL=y
++CONFIG_NILFS2_FS=m
++CONFIG_F2FS_FS=y
++CONFIG_F2FS_FS_SECURITY=y
++CONFIG_F2FS_CHECK_FS=y
++CONFIG_F2FS_FS_COMPRESSION=y
++CONFIG_FS_ENCRYPTION=y
++CONFIG_FANOTIFY=y
++CONFIG_AUTOFS_FS=m
++CONFIG_FUSE_FS=m
++CONFIG_CUSE=m
++CONFIG_OVERLAY_FS=m
++CONFIG_OVERLAY_FS_INDEX=y
++CONFIG_OVERLAY_FS_METACOPY=y
++CONFIG_VFAT_FS=y
++CONFIG_EXFAT_FS=m
++CONFIG_PROC_CHILDREN=y
++CONFIG_TMPFS=y
++CONFIG_TMPFS_POSIX_ACL=y
++CONFIG_CONFIGFS_FS=y
++CONFIG_ECRYPT_FS=m
++CONFIG_ECRYPT_FS_MESSAGING=y
++CONFIG_SQUASHFS=m
++CONFIG_SQUASHFS_FILE_DIRECT=y
++CONFIG_SQUASHFS_XATTR=y
++CONFIG_SQUASHFS_LZ4=y
++CONFIG_SQUASHFS_LZO=y
++CONFIG_SQUASHFS_XZ=y
++CONFIG_SQUASHFS_ZSTD=y
++# CONFIG_NETWORK_FILESYSTEMS is not set
++CONFIG_NLS_CODEPAGE_437=y
++CONFIG_NLS_CODEPAGE_852=y
++CONFIG_NLS_ISO8859_1=y
++CONFIG_NLS_ISO8859_2=y
++CONFIG_NLS_UTF8=y
++CONFIG_KEYS_REQUEST_CACHE=y
++CONFIG_PERSISTENT_KEYRINGS=y
++CONFIG_ENCRYPTED_KEYS=y
++CONFIG_KEY_DH_OPERATIONS=y
++CONFIG_LSM="yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor"
++CONFIG_INIT_STACK_NONE=y
++CONFIG_CRYPTO_USER=m
++CONFIG_CRYPTO_PCRYPT=m
++CONFIG_CRYPTO_CRYPTD=y
++CONFIG_CRYPTO_CURVE25519=m
++CONFIG_CRYPTO_DES=y
++CONFIG_CRYPTO_ARC4=m
++CONFIG_CRYPTO_CHACHA20POLY1305=m
++CONFIG_CRYPTO_SEQIV=m
++CONFIG_CRYPTO_ECHAINIV=m
++CONFIG_CRYPTO_MD4=m
++CONFIG_CRYPTO_SHA1=y
++CONFIG_CRYPTO_SHA3=y
++CONFIG_CRYPTO_DEFLATE=y
++CONFIG_CRYPTO_LZO=y
++CONFIG_CRYPTO_LZ4=y
++CONFIG_CRYPTO_ZSTD=y
++CONFIG_CRYPTO_ANSI_CPRNG=m
++CONFIG_CRYPTO_USER_API_HASH=m
++CONFIG_CRYPTO_USER_API_SKCIPHER=m
++CONFIG_CRYPTO_USER_API_RNG=m
++CONFIG_CRYPTO_USER_API_AEAD=m
++CONFIG_CRYPTO_GHASH_ARM64_CE=m
++CONFIG_CRYPTO_SHA1_ARM64_CE=m
++CONFIG_CRYPTO_SHA2_ARM64_CE=m
++CONFIG_CRYPTO_SHA512_ARM64_CE=m
++CONFIG_CRYPTO_SHA3_ARM64=m
++CONFIG_CRYPTO_SM3_ARM64_CE=m
++CONFIG_CRYPTO_AES_ARM64=m
++CONFIG_CRYPTO_AES_ARM64_BS=m
++CONFIG_CRYPTO_SM4_ARM64_CE=m
++CONFIG_CRYPTO_AES_ARM64_CE_CCM=m
++CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m
++CONFIG_CRYPTO_DEV_SUN8I_CE=m
++CONFIG_PKCS8_PRIVATE_KEY_PARSER=m
++# CONFIG_RAID6_PQ_BENCHMARK is not set
++CONFIG_CRC_T10DIF=y
++CONFIG_DMA_CMA=y
++CONFIG_CMA_SIZE_MBYTES=64
++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
++CONFIG_DYNAMIC_DEBUG=y
++CONFIG_FRAME_WARN=1024
++CONFIG_MAGIC_SYSRQ=y
++CONFIG_DEBUG_FS=y
++CONFIG_PER_VMA_LOCK_STATS=y
++CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=20
++CONFIG_FTRACE=y
++CONFIG_BOOTTIME_TRACING=y
++CONFIG_FUNCTION_TRACER=y
++CONFIG_FTRACE_SYSCALLS=y
++CONFIG_TRACER_SNAPSHOT=y
++# CONFIG_STRICT_DEVMEM is not set
++# CONFIG_RUNTIME_TESTING_MENU is not set
+diff --git a/arch/arm64/configs/pinephone_multidist_defconfig b/arch/arm64/configs/pinephone_multidist_defconfig
+new file mode 100644
+index 000000000000..633924e11882
+--- /dev/null
++++ b/arch/arm64/configs/pinephone_multidist_defconfig
+@@ -0,0 +1,600 @@
++CONFIG_SYSVIPC=y
++CONFIG_POSIX_MQUEUE=y
++CONFIG_NO_HZ=y
++CONFIG_HIGH_RES_TIMERS=y
++CONFIG_BPF_SYSCALL=y
++CONFIG_BPF_JIT=y
++CONFIG_BPF_JIT_ALWAYS_ON=y
++# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set
++CONFIG_BSD_PROCESS_ACCT=y
++CONFIG_BSD_PROCESS_ACCT_V3=y
++CONFIG_TASKSTATS=y
++CONFIG_TASK_DELAY_ACCT=y
++CONFIG_TASK_XACCT=y
++CONFIG_TASK_IO_ACCOUNTING=y
++CONFIG_PSI=y
++CONFIG_MEMCG=y
++CONFIG_BLK_CGROUP=y
++CONFIG_CFS_BANDWIDTH=y
++CONFIG_RT_GROUP_SCHED=y
++CONFIG_CGROUP_PIDS=y
++CONFIG_CGROUP_FREEZER=y
++CONFIG_CPUSETS=y
++# CONFIG_PROC_PID_CPUSET is not set
++CONFIG_CGROUP_DEVICE=y
++CONFIG_CGROUP_CPUACCT=y
++CONFIG_CGROUP_BPF=y
++CONFIG_NAMESPACES=y
++CONFIG_USER_NS=y
++CONFIG_SCHED_AUTOGROUP=y
++# CONFIG_RD_GZIP is not set
++# CONFIG_RD_BZIP2 is not set
++# CONFIG_RD_LZMA is not set
++# CONFIG_RD_XZ is not set
++# CONFIG_RD_LZO is not set
++# CONFIG_RD_ZSTD is not set
++CONFIG_EXPERT=y
++CONFIG_PERF_EVENTS=y
++CONFIG_ARCH_SUNXI=y
++# CONFIG_ARM64_ERRATUM_832075 is not set
++# CONFIG_ARM64_ERRATUM_1024718 is not set
++# CONFIG_ARM64_ERRATUM_1418040 is not set
++# CONFIG_ARM64_ERRATUM_1165522 is not set
++# CONFIG_ARM64_ERRATUM_1319367 is not set
++# CONFIG_ARM64_ERRATUM_1530923 is not set
++CONFIG_ARM64_ERRATUM_2441007=y
++# CONFIG_ARM64_ERRATUM_1463225 is not set
++# CONFIG_ARM64_ERRATUM_2051678 is not set
++# CONFIG_ARM64_ERRATUM_2077057 is not set
++CONFIG_ARM64_ERRATUM_2441009=y
++# CONFIG_CAVIUM_ERRATUM_22375 is not set
++# CONFIG_CAVIUM_ERRATUM_23154 is not set
++# CONFIG_CAVIUM_ERRATUM_27456 is not set
++# CONFIG_CAVIUM_ERRATUM_30115 is not set
++# CONFIG_CAVIUM_TX2_ERRATUM_219 is not set
++# CONFIG_FUJITSU_ERRATUM_010001 is not set
++# CONFIG_HISILICON_ERRATUM_161600802 is not set
++# CONFIG_QCOM_FALKOR_ERRATUM_1003 is not set
++# CONFIG_QCOM_FALKOR_ERRATUM_1009 is not set
++# CONFIG_QCOM_QDF2400_ERRATUM_0065 is not set
++# CONFIG_QCOM_FALKOR_ERRATUM_E1041 is not set
++# CONFIG_SOCIONEXT_SYNQUACER_PREITS is not set
++CONFIG_ARM64_VA_BITS_39=y
++CONFIG_SCHED_MC=y
++CONFIG_NR_CPUS=4
++CONFIG_COMPAT=y
++# CONFIG_ARM64_HW_AFDBM is not set
++# CONFIG_ARM64_PAN is not set
++# CONFIG_ARM64_USE_LSE_ATOMICS is not set
++# CONFIG_ARM64_RAS_EXTN is not set
++# CONFIG_ARM64_CNP is not set
++# CONFIG_ARM64_PTR_AUTH is not set
++# CONFIG_ARM64_AMU_EXTN is not set
++# CONFIG_ARM64_TLB_RANGE is not set
++# CONFIG_ARM64_BTI is not set
++# CONFIG_ARM64_E0PD is not set
++# CONFIG_ARM64_SVE is not set
++# CONFIG_EFI is not set
++CONFIG_PM_AUTOSLEEP=y
++CONFIG_PM_WAKELOCKS=y
++CONFIG_PM_DEBUG=y
++CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
++CONFIG_ENERGY_MODEL=y
++CONFIG_CPU_IDLE=y
++CONFIG_CPU_IDLE_GOV_LADDER=y
++CONFIG_ARM_PSCI_CPUIDLE=y
++CONFIG_CPU_FREQ=y
++CONFIG_CPU_FREQ_STAT=y
++CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y
++CONFIG_CPUFREQ_DT=y
++CONFIG_JUMP_LABEL=y
++# CONFIG_STACKPROTECTOR is not set
++# CONFIG_GCC_PLUGINS is not set
++CONFIG_MODULES=y
++CONFIG_MODULE_UNLOAD=y
++CONFIG_MODVERSIONS=y
++CONFIG_BLK_DEV_THROTTLING=y
++CONFIG_BLK_WBT=y
++CONFIG_BLK_CGROUP_IOLATENCY=y
++CONFIG_BLK_CGROUP_IOCOST=y
++CONFIG_PARTITION_ADVANCED=y
++# CONFIG_MQ_IOSCHED_DEADLINE is not set
++# CONFIG_MQ_IOSCHED_KYBER is not set
++CONFIG_CMA=y
++CONFIG_CMA_DEBUGFS=y
++CONFIG_CMA_AREAS=7
++CONFIG_NET=y
++CONFIG_PACKET=y
++CONFIG_PACKET_DIAG=y
++CONFIG_UNIX=y
++CONFIG_UNIX_DIAG=y
++CONFIG_XFRM_USER=y
++CONFIG_NET_KEY=y
++CONFIG_INET=y
++CONFIG_IP_MULTICAST=y
++CONFIG_IP_ADVANCED_ROUTER=y
++CONFIG_SYN_COOKIES=y
++# CONFIG_INET_DIAG is not set
++# CONFIG_IPV6_SIT is not set
++CONFIG_MPTCP=y
++CONFIG_NETFILTER=y
++CONFIG_NETFILTER_NETLINK_QUEUE=y
++CONFIG_NETFILTER_NETLINK_LOG=y
++CONFIG_NF_CONNTRACK=y
++CONFIG_NF_CONNTRACK_MARK=y
++# CONFIG_NF_CT_PROTO_DCCP is not set
++# CONFIG_NF_CT_PROTO_SCTP is not set
++# CONFIG_NF_CT_PROTO_UDPLITE is not set
++CONFIG_NF_CONNTRACK_FTP=y
++CONFIG_NF_CONNTRACK_H323=y
++CONFIG_NF_CONNTRACK_IRC=y
++CONFIG_NF_CONNTRACK_NETBIOS_NS=y
++CONFIG_NF_CONNTRACK_SNMP=y
++CONFIG_NF_CONNTRACK_PPTP=y
++CONFIG_NF_CONNTRACK_SIP=y
++CONFIG_NF_CONNTRACK_TFTP=y
++CONFIG_NF_CT_NETLINK=y
++CONFIG_NETFILTER_NETLINK_GLUE_CT=y
++CONFIG_NF_TABLES=y
++CONFIG_NF_TABLES_INET=y
++CONFIG_NF_TABLES_NETDEV=y
++CONFIG_NFT_NUMGEN=y
++CONFIG_NFT_CT=y
++CONFIG_NFT_CONNLIMIT=y
++CONFIG_NFT_LOG=y
++CONFIG_NFT_LIMIT=y
++CONFIG_NFT_MASQ=y
++CONFIG_NFT_REDIR=y
++CONFIG_NFT_NAT=y
++CONFIG_NFT_TUNNEL=y
++CONFIG_NFT_QUEUE=y
++CONFIG_NFT_QUOTA=y
++CONFIG_NFT_REJECT=y
++CONFIG_NFT_HASH=y
++CONFIG_NFT_FIB_INET=y
++CONFIG_NFT_SOCKET=y
++CONFIG_NFT_OSF=y
++CONFIG_NFT_DUP_NETDEV=y
++CONFIG_NFT_FWD_NETDEV=y
++CONFIG_NF_FLOW_TABLE_INET=y
++CONFIG_NF_FLOW_TABLE=y
++CONFIG_IP_SET=y
++CONFIG_IP_SET_BITMAP_IP=y
++CONFIG_IP_SET_BITMAP_IPMAC=y
++CONFIG_IP_SET_BITMAP_PORT=y
++CONFIG_IP_SET_HASH_IP=y
++CONFIG_IP_SET_HASH_IPMARK=y
++CONFIG_IP_SET_HASH_IPPORT=y
++CONFIG_IP_SET_HASH_IPPORTIP=y
++CONFIG_IP_SET_HASH_IPPORTNET=y
++CONFIG_IP_SET_HASH_IPMAC=y
++CONFIG_IP_SET_HASH_MAC=y
++CONFIG_IP_SET_HASH_NETPORTNET=y
++CONFIG_IP_SET_HASH_NET=y
++CONFIG_IP_SET_HASH_NETNET=y
++CONFIG_IP_SET_HASH_NETPORT=y
++CONFIG_IP_SET_HASH_NETIFACE=y
++CONFIG_IP_SET_LIST_SET=y
++CONFIG_NFT_FIB_IPV4=y
++CONFIG_NF_TABLES_ARP=y
++CONFIG_NF_LOG_ARP=y
++CONFIG_NF_LOG_IPV4=y
++# CONFIG_NF_NAT_SNMP_BASIC is not set
++CONFIG_NFT_DUP_IPV6=y
++CONFIG_NFT_FIB_IPV6=y
++CONFIG_NF_LOG_IPV6=y
++CONFIG_BRIDGE=y
++CONFIG_NET_SCHED=y
++CONFIG_NET_SCH_HTB=y
++CONFIG_NET_CLS_BASIC=y
++CONFIG_NET_CLS_ROUTE4=y
++CONFIG_NET_CLS_FW=y
++CONFIG_NET_CLS_CGROUP=y
++CONFIG_NET_CLS_ACT=y
++CONFIG_NET_ACT_POLICE=y
++CONFIG_NET_ACT_GACT=y
++CONFIG_NET_ACT_MIRRED=y
++CONFIG_NETLINK_DIAG=y
++CONFIG_BT=y
++CONFIG_BT_RFCOMM=y
++CONFIG_BT_RFCOMM_TTY=y
++CONFIG_BT_BNEP=y
++CONFIG_BT_BNEP_MC_FILTER=y
++CONFIG_BT_BNEP_PROTO_FILTER=y
++CONFIG_BT_HIDP=y
++CONFIG_BT_LEDS=y
++CONFIG_BT_HCIUART=y
++CONFIG_BT_HCIUART_RTL=y
++CONFIG_CFG80211=y
++CONFIG_CFG80211_DEBUGFS=y
++CONFIG_CFG80211_WEXT=y
++CONFIG_MAC80211=y
++CONFIG_MAC80211_LEDS=y
++CONFIG_RFKILL=y
++CONFIG_RFKILL_GPIO=y
++CONFIG_PAGE_POOL_STATS=y
++CONFIG_UEVENT_HELPER=y
++CONFIG_DEVTMPFS=y
++CONFIG_DEVTMPFS_MOUNT=y
++CONFIG_EXTRA_FIRMWARE="regulatory.db regulatory.db.p7s anx7688-fw.bin rtl_bt/rtl8723cs_xx_config.bin rtl_bt/rtl8723cs_xx_fw.bin ov5640_af.bin rtw88/rtw8703b_wow_fw.bin rtw88/rtw8703b_fw.bin"
++CONFIG_EXTRA_FIRMWARE_DIR="/workspace/megous.com/orangepi-pc/firmware"
++CONFIG_ARM_SCPI_PROTOCOL=y
++# CONFIG_ARM_SMCCC_SOC_ID is not set
++CONFIG_ZRAM=y
++CONFIG_ZRAM_WRITEBACK=y
++CONFIG_ZRAM_MEMORY_TRACKING=y
++CONFIG_BLK_DEV_LOOP=y
++CONFIG_BLK_DEV_NBD=y
++CONFIG_PPKB_POWER_MANAGER=y
++CONFIG_MODEM_POWER=y
++CONFIG_SCSI=y
++CONFIG_BLK_DEV_SD=y
++# CONFIG_BLK_DEV_BSG is not set
++# CONFIG_SCSI_LOWLEVEL is not set
++CONFIG_MD=y
++CONFIG_BLK_DEV_DM=y
++CONFIG_DM_CRYPT=y
++CONFIG_DM_INIT=y
++CONFIG_DM_UEVENT=y
++CONFIG_NETDEVICES=y
++CONFIG_WIREGUARD=y
++CONFIG_TUN=y
++CONFIG_VETH=y
++# CONFIG_ETHERNET is not set
++CONFIG_PPP=y
++CONFIG_PPP_BSDCOMP=y
++CONFIG_PPP_DEFLATE=y
++CONFIG_PPP_FILTER=y
++CONFIG_PPP_MPPE=y
++CONFIG_USB_RTL8152=y
++CONFIG_USB_USBNET=y
++# CONFIG_USB_NET_AX8817X is not set
++# CONFIG_USB_NET_AX88179_178A is not set
++CONFIG_USB_NET_CDC_EEM=y
++CONFIG_USB_NET_CDC_MBIM=y
++# CONFIG_USB_NET_NET1080 is not set
++# CONFIG_USB_NET_CDC_SUBSET is not set
++# CONFIG_USB_NET_ZAURUS is not set
++CONFIG_USB_NET_QMI_WWAN=y
++# CONFIG_WLAN_VENDOR_ADMTEK is not set
++# CONFIG_WLAN_VENDOR_ATH is not set
++# CONFIG_WLAN_VENDOR_ATMEL is not set
++# CONFIG_WLAN_VENDOR_BROADCOM is not set
++# CONFIG_WLAN_VENDOR_INTEL is not set
++# CONFIG_WLAN_VENDOR_INTERSIL is not set
++# CONFIG_WLAN_VENDOR_MARVELL is not set
++# CONFIG_WLAN_VENDOR_MEDIATEK is not set
++# CONFIG_WLAN_VENDOR_MICROCHIP is not set
++# CONFIG_WLAN_VENDOR_PURELIFI is not set
++# CONFIG_WLAN_VENDOR_RALINK is not set
++# CONFIG_RTL_CARDS is not set
++CONFIG_RTW88=m
++# CONFIG_WLAN_VENDOR_RSI is not set
++# CONFIG_WLAN_VENDOR_SILABS is not set
++# CONFIG_WLAN_VENDOR_ST is not set
++# CONFIG_WLAN_VENDOR_TI is not set
++# CONFIG_WLAN_VENDOR_ZYDAS is not set
++# CONFIG_WLAN_VENDOR_QUANTENNA is not set
++CONFIG_INPUT_MOUSEDEV=y
++CONFIG_INPUT_MOUSEDEV_PSAUX=y
++CONFIG_INPUT_EVDEV=y
++# CONFIG_KEYBOARD_ATKBD is not set
++CONFIG_KEYBOARD_GPIO=y
++CONFIG_KEYBOARD_GPIO_POLLED=y
++CONFIG_KEYBOARD_PINEPHONE=y
++CONFIG_KEYBOARD_SUN4I_LRADC=y
++# CONFIG_INPUT_MOUSE is not set
++CONFIG_INPUT_TOUCHSCREEN=y
++CONFIG_TOUCHSCREEN_GOODIX=y
++CONFIG_INPUT_MISC=y
++CONFIG_INPUT_GPIO_VIBRA=y
++CONFIG_INPUT_AXP20X_PEK=y
++CONFIG_INPUT_UINPUT=y
++# CONFIG_SERIO is not set
++# CONFIG_LEGACY_PTYS is not set
++CONFIG_SERIAL_8250=y
++# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
++CONFIG_SERIAL_8250_CONSOLE=y
++CONFIG_SERIAL_8250_NR_UARTS=8
++CONFIG_SERIAL_8250_RUNTIME_UARTS=8
++CONFIG_SERIAL_8250_DW=y
++CONFIG_SERIAL_OF_PLATFORM=y
++CONFIG_SERIAL_DEV_BUS=y
++# CONFIG_HW_RANDOM is not set
++CONFIG_I2C_CHARDEV=y
++CONFIG_I2C_GPIO=y
++CONFIG_I2C_MV64XXX=y
++CONFIG_PINCTRL_AXP209=y
++CONFIG_PINCTRL_SINGLE=y
++# CONFIG_PINCTRL_SUN8I_H3_R is not set
++# CONFIG_PINCTRL_SUN50I_H5 is not set
++# CONFIG_PINCTRL_SUN50I_H6 is not set
++# CONFIG_PINCTRL_SUN50I_H6_R is not set
++# CONFIG_PINCTRL_SUN50I_H616 is not set
++# CONFIG_PINCTRL_SUN50I_H616_R is not set
++CONFIG_GPIO_SYSFS=y
++CONFIG_NVMEM_REBOOT_MODE=y
++CONFIG_IP5XXX_POWER=y
++CONFIG_CHARGER_AXP20X=y
++CONFIG_BATTERY_AXP20X=y
++CONFIG_AXP20X_POWER=y
++# CONFIG_HWMON is not set
++CONFIG_THERMAL=y
++CONFIG_THERMAL_STATISTICS=y
++CONFIG_THERMAL_GOV_FAIR_SHARE=y
++CONFIG_THERMAL_GOV_BANG_BANG=y
++CONFIG_CPU_THERMAL=y
++CONFIG_SUN8I_THERMAL=y
++CONFIG_WATCHDOG=y
++CONFIG_SUNXI_WATCHDOG=y
++CONFIG_MFD_SUN4I_GPADC=y
++CONFIG_MFD_AXP20X_RSB=y
++CONFIG_MFD_SUN6I_PRCM=y
++CONFIG_REGULATOR=y
++CONFIG_REGULATOR_FIXED_VOLTAGE=y
++CONFIG_REGULATOR_AXP20X=y
++CONFIG_REGULATOR_GPIO=y
++CONFIG_MEDIA_SUPPORT=y
++CONFIG_MEDIA_SUPPORT_FILTER=y
++# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
++CONFIG_MEDIA_CAMERA_SUPPORT=y
++CONFIG_MEDIA_PLATFORM_SUPPORT=y
++CONFIG_V4L2_FLASH_LED_CLASS=y
++CONFIG_V4L_PLATFORM_DRIVERS=y
++CONFIG_V4L_MEM2MEM_DRIVERS=y
++CONFIG_VIDEO_MEM2MEM_DEINTERLACE=y
++CONFIG_VIDEO_SUN6I_CSI=y
++CONFIG_VIDEO_SUN8I_DEINTERLACE=y
++CONFIG_VIDEO_SUN8I_ROTATE=y
++CONFIG_VIDEO_OV5640=y
++CONFIG_VIDEO_GC2145=y
++CONFIG_DRM=y
++CONFIG_DRM_LOAD_EDID_FIRMWARE=y
++CONFIG_DRM_SUN4I=y
++CONFIG_DRM_PANEL_ILITEK_ILI9881C=y
++CONFIG_DRM_PANEL_SITRONIX_ST7703=y
++CONFIG_DRM_DW_HDMI_AHB_AUDIO=y
++CONFIG_DRM_DW_HDMI_I2S_AUDIO=y
++CONFIG_DRM_DW_HDMI_CEC=y
++CONFIG_DRM_LIMA=y
++CONFIG_FB=y
++CONFIG_FB_SIMPLE=y
++CONFIG_BACKLIGHT_CLASS_DEVICE=y
++CONFIG_BACKLIGHT_PWM=y
++CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
++CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER=y
++CONFIG_SOUND=y
++CONFIG_SND=y
++CONFIG_SND_OSSEMUL=y
++CONFIG_SND_MIXER_OSS=y
++CONFIG_SND_PCM_OSS=y
++CONFIG_SND_HRTIMER=y
++# CONFIG_SND_SUPPORT_OLD_API is not set
++# CONFIG_SND_DRIVERS is not set
++CONFIG_SND_USB_AUDIO=y
++CONFIG_SND_SOC=y
++CONFIG_SND_SUN4I_CODEC=y
++CONFIG_SND_SUN8I_CODEC=y
++CONFIG_SND_SUN8I_CODEC_ANALOG=y
++CONFIG_SND_SUN50I_CODEC_ANALOG=y
++CONFIG_SND_SUN4I_I2S=y
++CONFIG_SND_SUN4I_SPDIF=y
++CONFIG_SND_SUN9I_HDMI_AUDIO=y
++CONFIG_SND_SOC_BT_SCO=y
++CONFIG_SND_SOC_EC25=y
++CONFIG_SND_SOC_SIMPLE_AMPLIFIER=y
++CONFIG_SND_SIMPLE_CARD=y
++CONFIG_USB_HIDDEV=y
++CONFIG_USB_LED_TRIG=y
++CONFIG_USB=y
++CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
++CONFIG_USB_OTG=y
++CONFIG_USB_OTG_FSM=y
++CONFIG_USB_LEDS_TRIGGER_USBPORT=y
++CONFIG_USB_MON=y
++CONFIG_USB_EHCI_HCD=y
++CONFIG_USB_EHCI_HCD_PLATFORM=y
++CONFIG_USB_OHCI_HCD=y
++CONFIG_USB_OHCI_HCD_PLATFORM=y
++CONFIG_USB_ACM=y
++CONFIG_USB_STORAGE=y
++CONFIG_USB_UAS=y
++CONFIG_USB_MUSB_HDRC=y
++CONFIG_USB_MUSB_SUNXI=y
++CONFIG_MUSB_PIO_ONLY=y
++CONFIG_USB_SERIAL=y
++CONFIG_USB_SERIAL_CONSOLE=y
++CONFIG_USB_SERIAL_GENERIC=y
++CONFIG_USB_SERIAL_SIMPLE=y
++CONFIG_USB_SERIAL_CH341=y
++CONFIG_USB_SERIAL_CP210X=y
++CONFIG_USB_SERIAL_FTDI_SIO=y
++CONFIG_USB_SERIAL_QCAUX=y
++CONFIG_USB_SERIAL_OPTION=y
++CONFIG_NOP_USB_XCEIV=y
++CONFIG_USB_GADGET=y
++CONFIG_USB_GADGET_VBUS_DRAW=500
++CONFIG_U_SERIAL_CONSOLE=y
++CONFIG_USB_CONFIGFS=y
++CONFIG_USB_CONFIGFS_SERIAL=y
++CONFIG_USB_CONFIGFS_ACM=y
++CONFIG_USB_CONFIGFS_OBEX=y
++CONFIG_USB_CONFIGFS_NCM=y
++CONFIG_USB_CONFIGFS_ECM=y
++CONFIG_USB_CONFIGFS_ECM_SUBSET=y
++CONFIG_USB_CONFIGFS_RNDIS=y
++CONFIG_USB_CONFIGFS_EEM=y
++CONFIG_USB_CONFIGFS_MASS_STORAGE=y
++CONFIG_USB_CONFIGFS_F_FS=y
++CONFIG_USB_CONFIGFS_F_UAC1=y
++CONFIG_USB_CONFIGFS_F_UAC2=y
++CONFIG_USB_CONFIGFS_F_HID=y
++CONFIG_USB_CONFIGFS_F_UVC=y
++CONFIG_USB_CONFIGFS_F_PRINTER=y
++CONFIG_TYPEC=y
++CONFIG_TYPEC_TCPM=y
++CONFIG_TYPEC_TCPCI=y
++CONFIG_TYPEC_UCSI=y
++CONFIG_TYPEC_ANX7688=y
++CONFIG_TYPEC_DP_ALTMODE=y
++CONFIG_MMC=y
++CONFIG_MMC_SUNXI=y
++CONFIG_NEW_LEDS=y
++CONFIG_LEDS_CLASS=y
++CONFIG_LEDS_CLASS_FLASH=y
++CONFIG_LEDS_GPIO=y
++CONFIG_LEDS_SGM3140=y
++CONFIG_LEDS_TRIGGER_TIMER=y
++CONFIG_LEDS_TRIGGER_ONESHOT=y
++CONFIG_LEDS_TRIGGER_HEARTBEAT=y
++CONFIG_LEDS_TRIGGER_CPU=y
++CONFIG_LEDS_TRIGGER_ACTIVITY=y
++CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
++CONFIG_LEDS_TRIGGER_TRANSIENT=y
++CONFIG_LEDS_TRIGGER_CAMERA=y
++CONFIG_LEDS_TRIGGER_PANIC=y
++CONFIG_LEDS_TRIGGER_NETDEV=y
++CONFIG_LEDS_TRIGGER_PATTERN=y
++CONFIG_RTC_CLASS=y
++# CONFIG_RTC_INTF_PROC is not set
++CONFIG_RTC_DRV_SUN6I=y
++CONFIG_DMADEVICES=y
++CONFIG_DMA_SUN6I=y
++CONFIG_DMABUF_HEAPS=y
++CONFIG_DMABUF_HEAPS_SYSTEM=y
++CONFIG_DMABUF_HEAPS_CMA=y
++# CONFIG_VIRTIO_MENU is not set
++# CONFIG_VHOST_MENU is not set
++CONFIG_STAGING=y
++CONFIG_STAGING_MEDIA=y
++CONFIG_VIDEO_SUNXI=y
++CONFIG_VIDEO_SUNXI_CEDRUS=y
++CONFIG_RTL8723CS=m
++# CONFIG_SUN50I_H6_CCU is not set
++# CONFIG_SUN50I_H616_CCU is not set
++# CONFIG_SUN50I_H6_R_CCU is not set
++# CONFIG_SUN8I_H3_CCU is not set
++# CONFIG_HISILICON_ERRATUM_161010101 is not set
++# CONFIG_ARM64_ERRATUM_858921 is not set
++CONFIG_MAILBOX=y
++CONFIG_IOMMU_IO_PGTABLE_LPAE=y
++CONFIG_DEVFREQ_GOV_PERFORMANCE=y
++CONFIG_DEVFREQ_GOV_POWERSAVE=y
++CONFIG_DEVFREQ_GOV_USERSPACE=y
++CONFIG_DEVFREQ_GOV_PASSIVE=y
++CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ=y
++CONFIG_PM_DEVFREQ_EVENT=y
++CONFIG_IIO=y
++CONFIG_IIO_BUFFER_CB=y
++CONFIG_IIO_BUFFER_HW_CONSUMER=y
++CONFIG_IIO_SW_DEVICE=y
++CONFIG_IIO_SW_TRIGGER=y
++CONFIG_AXP20X_ADC=y
++CONFIG_INV_MPU6050_I2C=y
++CONFIG_STK3310=y
++CONFIG_AF8133J=y
++CONFIG_IIO_ST_MAGN_3AXIS=y
++CONFIG_IIO_HRTIMER_TRIGGER=y
++CONFIG_IIO_INTERRUPT_TRIGGER=y
++CONFIG_IIO_SYSFS_TRIGGER=y
++CONFIG_PWM=y
++CONFIG_PWM_SUN4I=y
++CONFIG_PHY_SUN4I_USB=y
++CONFIG_ARM_CCI_PMU=y
++# CONFIG_ARM_CCI5xx_PMU is not set
++CONFIG_ANDROID_BINDER_IPC=y
++CONFIG_ANDROID_BINDERFS=y
++CONFIG_NVMEM_SUNXI_SID=y
++CONFIG_VALIDATE_FS_PARSER=y
++CONFIG_EXT4_FS=y
++CONFIG_EXT4_FS_POSIX_ACL=y
++CONFIG_BTRFS_FS=y
++CONFIG_BTRFS_FS_POSIX_ACL=y
++CONFIG_F2FS_FS=y
++CONFIG_F2FS_FS_SECURITY=y
++CONFIG_F2FS_CHECK_FS=y
++CONFIG_F2FS_FS_COMPRESSION=y
++CONFIG_FS_ENCRYPTION=y
++CONFIG_FANOTIFY=y
++CONFIG_AUTOFS_FS=y
++CONFIG_FUSE_FS=y
++CONFIG_CUSE=y
++CONFIG_OVERLAY_FS=y
++CONFIG_OVERLAY_FS_INDEX=y
++CONFIG_OVERLAY_FS_METACOPY=y
++CONFIG_VFAT_FS=y
++CONFIG_EXFAT_FS=y
++CONFIG_PROC_CHILDREN=y
++CONFIG_TMPFS=y
++CONFIG_TMPFS_POSIX_ACL=y
++CONFIG_ECRYPT_FS=y
++CONFIG_ECRYPT_FS_MESSAGING=y
++CONFIG_SQUASHFS=y
++CONFIG_SQUASHFS_FILE_DIRECT=y
++CONFIG_SQUASHFS_XATTR=y
++CONFIG_SQUASHFS_LZ4=y
++CONFIG_SQUASHFS_LZO=y
++CONFIG_SQUASHFS_XZ=y
++CONFIG_SQUASHFS_ZSTD=y
++# CONFIG_NETWORK_FILESYSTEMS is not set
++CONFIG_NLS_CODEPAGE_437=y
++CONFIG_NLS_CODEPAGE_852=y
++CONFIG_NLS_ISO8859_1=y
++CONFIG_NLS_ISO8859_2=y
++CONFIG_NLS_UTF8=y
++CONFIG_KEYS_REQUEST_CACHE=y
++CONFIG_PERSISTENT_KEYRINGS=y
++CONFIG_BIG_KEYS=y
++CONFIG_ENCRYPTED_KEYS=y
++CONFIG_KEY_DH_OPERATIONS=y
++CONFIG_LSM="yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor"
++CONFIG_INIT_STACK_NONE=y
++CONFIG_CRYPTO_USER=y
++CONFIG_CRYPTO_PCRYPT=y
++CONFIG_CRYPTO_CRYPTD=y
++CONFIG_CRYPTO_CURVE25519=y
++CONFIG_CRYPTO_ARC4=y
++CONFIG_CRYPTO_CHACHA20POLY1305=y
++CONFIG_CRYPTO_SEQIV=y
++CONFIG_CRYPTO_ECHAINIV=y
++CONFIG_CRYPTO_MD4=y
++CONFIG_CRYPTO_DEFLATE=y
++CONFIG_CRYPTO_LZO=y
++CONFIG_CRYPTO_LZ4=y
++CONFIG_CRYPTO_ZSTD=y
++CONFIG_CRYPTO_ANSI_CPRNG=y
++CONFIG_CRYPTO_USER_API_HASH=y
++CONFIG_CRYPTO_USER_API_SKCIPHER=y
++CONFIG_CRYPTO_USER_API_RNG=y
++CONFIG_CRYPTO_USER_API_AEAD=y
++CONFIG_CRYPTO_GHASH_ARM64_CE=y
++CONFIG_CRYPTO_SHA1_ARM64_CE=y
++CONFIG_CRYPTO_SHA2_ARM64_CE=y
++CONFIG_CRYPTO_SHA512_ARM64_CE=y
++CONFIG_CRYPTO_SHA3_ARM64=y
++CONFIG_CRYPTO_SM3_ARM64_CE=y
++CONFIG_CRYPTO_AES_ARM64=y
++CONFIG_CRYPTO_AES_ARM64_BS=y
++CONFIG_CRYPTO_SM4_ARM64_CE=y
++CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
++CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y
++CONFIG_CRYPTO_DEV_SUN8I_CE=y
++CONFIG_PKCS8_PRIVATE_KEY_PARSER=y
++# CONFIG_RAID6_PQ_BENCHMARK is not set
++CONFIG_CRC_T10DIF=y
++CONFIG_DMA_CMA=y
++CONFIG_CMA_SIZE_MBYTES=64
++CONFIG_MESSAGE_LOGLEVEL_DEFAULT=7
++CONFIG_DYNAMIC_DEBUG=y
++CONFIG_FRAME_WARN=1024
++CONFIG_MAGIC_SYSRQ=y
++CONFIG_DEBUG_FS=y
++# CONFIG_SLUB_DEBUG is not set
++CONFIG_PER_VMA_LOCK_STATS=y
++CONFIG_RCU_EXP_CPU_STALL_TIMEOUT=20
++CONFIG_BOOTTIME_TRACING=y
++CONFIG_FUNCTION_TRACER=y
++CONFIG_FTRACE_SYSCALLS=y
++CONFIG_TRACER_SNAPSHOT=y
++# CONFIG_STRICT_DEVMEM is not set
++# CONFIG_RUNTIME_TESTING_MENU is not set
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/Fix-broken-allwinner-sram-dependency-on-h616-h618.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/Fix-broken-allwinner-sram-dependency-on-h616-h618.patch
new file mode 100644
index 000000000000..02c47fe97a7c
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/Fix-broken-allwinner-sram-dependency-on-h616-h618.patch
@@ -0,0 +1,53 @@
+From c9248297e040af7071212003c78140c1e383535d Mon Sep 17 00:00:00 2001
+From: "Steinar H. Gunderson" <steinar+kernel@gunderson.no>
+Date: Mon, 4 Nov 2024 15:35:38 +0000
+Subject: Fix broken allwinner,sram dependency on h616, h618
+
+On BigTreeTech CB1, the thermal sensor has an allwinner,sram
+property pointing to <&syscon>. However, Armbian has an out-of-tree
+kernel patch that creates dependencies based on allwinner,sram
+properties, which assumes that they point to sram nodes exactly
+two levels below the syscon node (instead of the syscon itself).
+This manifests itself as the thermal sensor refusing to load with
+a nonsensical error message:
+
+  [   23.775976] platform 5070400.thermal-sensor: deferred probe pending: platform: wait for supplier
+
+Note that it does not say _which_ supplier it is waiting for
+(the message ends in a space and then no supplier). The patch
+was unproblematic in the 5.6 megous patch set, where it was
+introduced, and in 6.6, which is current for Armbian, but in
+6.8, the sun8i-thermal driver got mainlined, with this extra
+property compared to the out-of-tree version we used before
+(since it wants to clear a special bit at 0x300000 instead of
+relying on the firmware to do so before kernel boot).
+
+Fix by being a bit more flexible when we walk up the tree,
+so that we always stop at the syscon node.
+
+Tested on a Sovol SV08, which is CB1-based.
+
+Signed-off-by: Steinar H. Gunderson <steinar+kernel@gunderson.no>
+---
+ drivers/of/property.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/of/property.c b/drivers/of/property.c
+index 8c9f3ea663a6..074fbf9d27f8 100644
+--- a/drivers/of/property.c
++++ b/drivers/of/property.c
+@@ -1470,8 +1470,9 @@ static struct device_node *parse_allwinner_sram(struct device_node *np,
+ 		return NULL;
+ 
+ 	sram_node = of_parse_phandle(np, prop_name, 0);
+-	sram_node = of_get_parent(sram_node);
+-	sram_node = of_get_parent(sram_node);
++	while (sram_node && !of_node_is_type(sram_node, "syscon")) {
++		sram_node = of_get_parent(sram_node);
++	}
+ 
+ 	return sram_node;
+ }
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/Fix-intptr_t-typedef.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/Fix-intptr_t-typedef.patch
new file mode 100644
index 000000000000..e17baeb09b22
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/Fix-intptr_t-typedef.patch
@@ -0,0 +1,32 @@
+From fb28d52e3bbfa61ae3a900d5a42972628c2e9ea2 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sat, 26 Aug 2023 10:55:24 +0200
+Subject: Fix intptr_t typedef
+
+GCC includes the same typedef, but on some 32bit platforms it's defined
+as int, leading to conflicts.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ include/linux/types.h | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/include/linux/types.h b/include/linux/types.h
+index 1c509ce8f7f6..46f7b982a7ec 100644
+--- a/include/linux/types.h
++++ b/include/linux/types.h
+@@ -40,7 +40,11 @@ typedef __kernel_uid16_t        uid16_t;
+ typedef __kernel_gid16_t        gid16_t;
+ 
+ typedef unsigned long		uintptr_t;
++#if __SIZEOF_POINTER__ == __SIZEOF_INT__
++typedef int			intptr_t;
++#else
+ typedef long			intptr_t;
++#endif
+ 
+ #ifdef CONFIG_HAVE_UID16
+ /* This is defined by arch/{arch}/include/asm/posix_types.h */
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/MAINTAINERS-Add-entry-for-Himax-HM5065.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/MAINTAINERS-Add-entry-for-Himax-HM5065.patch
new file mode 100644
index 000000000000..8b378ab73241
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/MAINTAINERS-Add-entry-for-Himax-HM5065.patch
@@ -0,0 +1,30 @@
+From 8b84ffb671ccc349736193252b38ecedb32503dd Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 30 Sep 2017 21:31:35 +0200
+Subject: MAINTAINERS: Add entry for Himax HM5065
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ MAINTAINERS | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/MAINTAINERS b/MAINTAINERS
+index 00e94bec401e..7d07a2608cb2 100644
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -10375,6 +10375,12 @@ L:	linux-kernel@vger.kernel.org
+ S:	Maintained
+ F:	drivers/misc/hisi_hikey_usb.c
+ 
++HIMAX HM5065 SENSOR DRIVER
++M:	Ondrej Jirman <kernel@xff.cz>
++L:	linux-media@vger.kernel.org
++S:	Supported
++F:	drivers/media/i2c/hm5065.c
++
+ HIMAX HX83112B TOUCHSCREEN SUPPORT
+ M:	Job Noorman <job@noorman.info>
+ L:	linux-input@vger.kernel.org
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/Make-microbuttons-on-Orange-Pi-PC-and-PC-2-work-as-power-off-bu.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/Make-microbuttons-on-Orange-Pi-PC-and-PC-2-work-as-power-off-bu.patch
new file mode 100644
index 000000000000..14982acd1091
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/Make-microbuttons-on-Orange-Pi-PC-and-PC-2-work-as-power-off-bu.patch
@@ -0,0 +1,39 @@
+From 6d2930ee9c0b2c64a42d5559a91858b9b8e6926c Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Fri, 18 Aug 2017 13:55:48 +0200
+Subject: Make microbuttons on Orange Pi PC and PC 2 work as power off buttons
+
+---
+ arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts    | 2 +-
+ arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts
+index 927fd1bab07d..f5476cdab8a4 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-one.dts
+@@ -91,7 +91,7 @@ gpio-keys {
+ 
+ 		switch-4 {
+ 			label = "sw4";
+-			linux,code = <BTN_0>;
++			linux,code = <KEY_POWER>;
+ 			gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
+ 		};
+ 	};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
+index f420acc6f49f..3d16a6efa2a7 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
+@@ -60,7 +60,7 @@ gpio-keys {
+ 
+ 		key-sw4 {
+ 			label = "sw4";
+-			linux,code = <BTN_0>;
++			linux,code = <KEY_POWER>;
+ 			gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
+ 			wakeup-source;
+ 		};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/Mark-some-slow-drivers-for-async-probe-with-PROBE_PREFER_ASYNCH.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/Mark-some-slow-drivers-for-async-probe-with-PROBE_PREFER_ASYNCH.patch
new file mode 100644
index 000000000000..95bc4a97592c
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/Mark-some-slow-drivers-for-async-probe-with-PROBE_PREFER_ASYNCH.patch
@@ -0,0 +1,40 @@
+From 3bcea65acc9d9f6227d539e7db848caa149e8ed6 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 10 Feb 2020 01:00:12 +0100
+Subject: Mark some slow drivers for async probe with PROBE_PREFER_ASYNCHRONOUS
+
+This makes it faster to boot TBS A711 tablet.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/iio/accel/bma180.c | 1 +
+ drivers/nfc/nxp-nci/i2c.c  | 1 +
+ 2 files changed, 2 insertions(+)
+
+diff --git a/drivers/iio/accel/bma180.c b/drivers/iio/accel/bma180.c
+index 128db14ba726..9881cb1de9ef 100644
+--- a/drivers/iio/accel/bma180.c
++++ b/drivers/iio/accel/bma180.c
+@@ -1127,6 +1127,7 @@ static struct i2c_driver bma180_driver = {
+ 		.name	= "bma180",
+ 		.pm	= pm_sleep_ptr(&bma180_pm_ops),
+ 		.of_match_table = bma180_of_match,
++		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
+ 	},
+ 	.probe		= bma180_probe,
+ 	.remove		= bma180_remove,
+diff --git a/drivers/nfc/nxp-nci/i2c.c b/drivers/nfc/nxp-nci/i2c.c
+index 049662ffdf97..35986be81ee3 100644
+--- a/drivers/nfc/nxp-nci/i2c.c
++++ b/drivers/nfc/nxp-nci/i2c.c
+@@ -348,6 +348,7 @@ static struct i2c_driver nxp_nci_i2c_driver = {
+ 		   .name = NXP_NCI_I2C_DRIVER_NAME,
+ 		   .acpi_match_table = ACPI_PTR(acpi_id),
+ 		   .of_match_table = of_nxp_nci_i2c_match,
++		   .probe_type = PROBE_PREFER_ASYNCHRONOUS,
+ 		  },
+ 	.probe = nxp_nci_i2c_probe,
+ 	.id_table = nxp_nci_i2c_id_table,
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/Move-a-node-to-avoid-merge-conflict.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/Move-a-node-to-avoid-merge-conflict.patch
new file mode 100644
index 000000000000..02cab02c5ec3
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/Move-a-node-to-avoid-merge-conflict.patch
@@ -0,0 +1,115 @@
+From 275a68cd0bf4414c886f9f4a5e39f7f166fe4286 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 9 May 2021 23:43:21 +0200
+Subject: Move a node to avoid merge conflict
+
+---
+ arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi  | 12 ++++-----
+ .../dts/allwinner/sun50i-h6-orangepi-3.dts    |  8 +++---
+ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi  | 27 +++++++++----------
+ 3 files changed, 23 insertions(+), 24 deletions(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi
+index 0f19e7c00c50..a872fc586ab6 100644
+--- a/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi
++++ b/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi
+@@ -100,12 +100,6 @@ osc32k: osc32k-clk {
+ 		};
+ 	};
+ 
+-	de: display-engine {
+-		compatible = "allwinner,sun8i-h3-display-engine";
+-		allwinner,pipelines = <&mixer0>;
+-		status = "disabled";
+-	};
+-
+ 	sound_hdmi: sound_hdmi {
+ 		compatible = "allwinner,sun9i-a80-hdmi-audio",
+ 			     "allwinner,sun8i-h3-hdmi-audio";
+@@ -120,6 +114,12 @@ cpu {
+ 		};
+ 	};
+ 
++	de: display-engine {
++		compatible = "allwinner,sun8i-h3-display-engine";
++		allwinner,pipelines = <&mixer0>;
++		status = "disabled";
++	};
++
+ 	soc {
+ 		compatible = "simple-bus";
+ 		#address-cells = <1>;
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
+index 7e11286bf6d1..d1f5daf63484 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
+@@ -128,6 +128,10 @@ &gpu {
+ 	status = "okay";
+ };
+ 
++&i2s1 {
++	status = "okay";
++};
++
+ &hdmi {
+ 	status = "okay";
+ };
+@@ -167,10 +171,6 @@ ext_rgmii_phy: ethernet-phy@1 {
+ 	};
+ };
+ 
+-&i2s1 {
+-	status = "okay";
+-};
+-
+ &mmc0 {
+ 	vmmc-supply = <&reg_cldo1>;
+ 	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+index 13fe21b00711..c4e35a255643 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+@@ -126,20 +126,6 @@ psci {
+ 		method = "smc";
+ 	};
+ 
+-	sound_hdmi: sound_hdmi {
+-		compatible = "allwinner,sun9i-a80-hdmi-audio",
+-			     "allwinner,sun50i-h6-hdmi-audio";
+-		status = "disabled";
+-
+-		codec {
+-			sound-dai = <&hdmi>;
+-		};
+-
+-		cpu {
+-			sound-dai = <&i2s1>;
+-		};
+-	};
+-
+ 	timer {
+ 		compatible = "arm,armv8-timer";
+ 		arm,no-tick-in-suspend;
+@@ -153,6 +139,19 @@ timer {
+ 			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ 	};
+ 
++	sound_hdmi: sound_hdmi {
++		compatible = "allwinner,sun9i-a80-hdmi-audio",
++			     "allwinner,sun50i-h6-hdmi-audio";
++		status = "disabled";
++
++		codec {
++			sound-dai = <&hdmi>;
++		};
++
++		cpu {
++			sound-dai = <&i2s1>;
++		};
++	};
+ 
+ 	soc {
+ 		compatible = "simple-bus";
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/Revert-Input-cyttsp4-remove-driver.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/Revert-Input-cyttsp4-remove-driver.patch
new file mode 100644
index 000000000000..40050fc15bc4
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/Revert-Input-cyttsp4-remove-driver.patch
@@ -0,0 +1,3232 @@
+From afe7cc88dc1c603d849bfac407867231ce8ccdff Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Thu, 26 Sep 2024 23:00:02 +0200
+Subject: Revert "Input: cyttsp4 - remove driver"
+
+This reverts commit 25162a4f64f8ba0065f300977589fe1f6af332f0.
+---
+ drivers/input/touchscreen/Kconfig             |   30 +
+ drivers/input/touchscreen/Makefile            |    5 +-
+ drivers/input/touchscreen/cyttsp4_core.c      | 2174 +++++++++++++++++
+ drivers/input/touchscreen/cyttsp4_core.h      |  448 ++++
+ drivers/input/touchscreen/cyttsp4_i2c.c       |   72 +
+ drivers/input/touchscreen/cyttsp4_spi.c       |  187 ++
+ drivers/input/touchscreen/cyttsp_core.h       |    4 +
+ drivers/input/touchscreen/cyttsp_i2c.c        |   55 -
+ drivers/input/touchscreen/cyttsp_i2c_common.c |   86 +
+ include/linux/platform_data/cyttsp4.h         |   62 +
+ 10 files changed, 3067 insertions(+), 56 deletions(-)
+ create mode 100644 drivers/input/touchscreen/cyttsp4_core.c
+ create mode 100644 drivers/input/touchscreen/cyttsp4_core.h
+ create mode 100644 drivers/input/touchscreen/cyttsp4_i2c.c
+ create mode 100644 drivers/input/touchscreen/cyttsp4_spi.c
+ create mode 100644 drivers/input/touchscreen/cyttsp_i2c_common.c
+ create mode 100644 include/linux/platform_data/cyttsp4.h
+
+diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig
+index 1a03de7fcfa6..3a8a3ad64cdc 100644
+--- a/drivers/input/touchscreen/Kconfig
++++ b/drivers/input/touchscreen/Kconfig
+@@ -254,6 +254,36 @@ config TOUCHSCREEN_CYTTSP_SPI
+ 	  To compile this driver as a module, choose M here: the
+ 	  module will be called cyttsp_spi.
+ 
++config TOUCHSCREEN_CYTTSP4_CORE
++	tristate "Cypress TrueTouch Gen4 Touchscreen Driver"
++	help
++	  Core driver for Cypress TrueTouch(tm) Standard Product
++	  Generation4 touchscreen controllers.
++
++	  Say Y here if you have a Cypress Gen4 touchscreen.
++
++	  If unsure, say N.
++
++	  To compile this driver as a module, choose M here.
++
++config TOUCHSCREEN_CYTTSP4_I2C
++	tristate "support I2C bus connection"
++	depends on TOUCHSCREEN_CYTTSP4_CORE && I2C
++	help
++	  Say Y here if the touchscreen is connected via I2C bus.
++
++	  To compile this driver as a module, choose M here: the
++	  module will be called cyttsp4_i2c.
++
++config TOUCHSCREEN_CYTTSP4_SPI
++	tristate "support SPI bus connection"
++	depends on TOUCHSCREEN_CYTTSP4_CORE && SPI_MASTER
++	help
++	  Say Y here if the touchscreen is connected via SPI bus.
++
++	  To compile this driver as a module, choose M here: the
++	  module will be called cyttsp4_spi.
++
+ config TOUCHSCREEN_CYTTSP5
+ 	tristate "Cypress TrueTouch Gen5 Touchscreen Driver"
+ 	depends on I2C
+diff --git a/drivers/input/touchscreen/Makefile b/drivers/input/touchscreen/Makefile
+index 82bc837ca01e..04dc8039341b 100644
+--- a/drivers/input/touchscreen/Makefile
++++ b/drivers/input/touchscreen/Makefile
+@@ -25,8 +25,11 @@ obj-$(CONFIG_TOUCHSCREEN_CHIPONE_ICN8505)	+= chipone_icn8505.o
+ obj-$(CONFIG_TOUCHSCREEN_CY8CTMA140)	+= cy8ctma140.o
+ obj-$(CONFIG_TOUCHSCREEN_CY8CTMG110)	+= cy8ctmg110_ts.o
+ obj-$(CONFIG_TOUCHSCREEN_CYTTSP_CORE)	+= cyttsp_core.o
+-obj-$(CONFIG_TOUCHSCREEN_CYTTSP_I2C)	+= cyttsp_i2c.o
++obj-$(CONFIG_TOUCHSCREEN_CYTTSP_I2C)	+= cyttsp_i2c.o cyttsp_i2c_common.o
+ obj-$(CONFIG_TOUCHSCREEN_CYTTSP_SPI)	+= cyttsp_spi.o
++obj-$(CONFIG_TOUCHSCREEN_CYTTSP4_CORE)	+= cyttsp4_core.o
++obj-$(CONFIG_TOUCHSCREEN_CYTTSP4_I2C)	+= cyttsp4_i2c.o cyttsp_i2c_common.o
++obj-$(CONFIG_TOUCHSCREEN_CYTTSP4_SPI)	+= cyttsp4_spi.o
+ obj-$(CONFIG_TOUCHSCREEN_CYTTSP5)	+= cyttsp5.o
+ obj-$(CONFIG_TOUCHSCREEN_DA9034)	+= da9034-ts.o
+ obj-$(CONFIG_TOUCHSCREEN_DA9052)	+= da9052_tsi.o
+diff --git a/drivers/input/touchscreen/cyttsp4_core.c b/drivers/input/touchscreen/cyttsp4_core.c
+new file mode 100644
+index 000000000000..7cb26929dc73
+--- /dev/null
++++ b/drivers/input/touchscreen/cyttsp4_core.c
+@@ -0,0 +1,2174 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * cyttsp4_core.c
++ * Cypress TrueTouch(TM) Standard Product V4 Core driver module.
++ * For use with Cypress Txx4xx parts.
++ * Supported parts include:
++ * TMA4XX
++ * TMA1036
++ *
++ * Copyright (C) 2012 Cypress Semiconductor
++ *
++ * Contact Cypress Semiconductor at www.cypress.com <ttdrivers@cypress.com>
++ */
++
++#include "cyttsp4_core.h"
++#include <linux/delay.h>
++#include <linux/gpio.h>
++#include <linux/input/mt.h>
++#include <linux/interrupt.h>
++#include <linux/pm_runtime.h>
++#include <linux/sched.h>
++#include <linux/slab.h>
++
++/* Timeout in ms. */
++#define CY_CORE_REQUEST_EXCLUSIVE_TIMEOUT	500
++#define CY_CORE_SLEEP_REQUEST_EXCLUSIVE_TIMEOUT	5000
++#define CY_CORE_MODE_CHANGE_TIMEOUT		1000
++#define CY_CORE_RESET_AND_WAIT_TIMEOUT		500
++#define CY_CORE_WAKEUP_TIMEOUT			500
++
++#define CY_CORE_STARTUP_RETRY_COUNT		3
++
++static const char * const cyttsp4_tch_abs_string[] = {
++	[CY_TCH_X]	= "X",
++	[CY_TCH_Y]	= "Y",
++	[CY_TCH_P]	= "P",
++	[CY_TCH_T]	= "T",
++	[CY_TCH_E]	= "E",
++	[CY_TCH_O]	= "O",
++	[CY_TCH_W]	= "W",
++	[CY_TCH_MAJ]	= "MAJ",
++	[CY_TCH_MIN]	= "MIN",
++	[CY_TCH_OR]	= "OR",
++	[CY_TCH_NUM_ABS] = "INVALID"
++};
++
++static const u8 ldr_exit[] = {
++	0xFF, 0x01, 0x3B, 0x00, 0x00, 0x4F, 0x6D, 0x17
++};
++
++static const u8 ldr_err_app[] = {
++	0x01, 0x02, 0x00, 0x00, 0x55, 0xDD, 0x17
++};
++
++static inline size_t merge_bytes(u8 high, u8 low)
++{
++	return (high << 8) + low;
++}
++
++#ifdef VERBOSE_DEBUG
++static void cyttsp4_pr_buf(struct device *dev, u8 *pr_buf, u8 *dptr, int size,
++		const char *data_name)
++{
++	int i, k;
++	const char fmt[] = "%02X ";
++	int max;
++
++	if (!size)
++		return;
++
++	max = (CY_MAX_PRBUF_SIZE - 1) - sizeof(CY_PR_TRUNCATED);
++
++	pr_buf[0] = 0;
++	for (i = k = 0; i < size && k < max; i++, k += 3)
++		scnprintf(pr_buf + k, CY_MAX_PRBUF_SIZE, fmt, dptr[i]);
++
++	dev_vdbg(dev, "%s:  %s[0..%d]=%s%s\n", __func__, data_name, size - 1,
++			pr_buf, size <= max ? "" : CY_PR_TRUNCATED);
++}
++#else
++#define cyttsp4_pr_buf(dev, pr_buf, dptr, size, data_name) do { } while (0)
++#endif
++
++static int cyttsp4_load_status_regs(struct cyttsp4 *cd)
++{
++	struct cyttsp4_sysinfo *si = &cd->sysinfo;
++	struct device *dev = cd->dev;
++	int rc;
++
++	rc = cyttsp4_adap_read(cd, CY_REG_BASE, si->si_ofs.mode_size,
++			si->xy_mode);
++	if (rc < 0)
++		dev_err(dev, "%s: fail read mode regs r=%d\n",
++			__func__, rc);
++	else
++		cyttsp4_pr_buf(dev, cd->pr_buf, si->xy_mode,
++			si->si_ofs.mode_size, "xy_mode");
++
++	return rc;
++}
++
++static int cyttsp4_handshake(struct cyttsp4 *cd, u8 mode)
++{
++	u8 cmd = mode ^ CY_HST_TOGGLE;
++	int rc;
++
++	/*
++	 * Mode change issued, handshaking now will cause endless mode change
++	 * requests, for sync mode modechange will do same with handshake
++	 * */
++	if (mode & CY_HST_MODE_CHANGE)
++		return 0;
++
++	rc = cyttsp4_adap_write(cd, CY_REG_BASE, sizeof(cmd), &cmd);
++	if (rc < 0)
++		dev_err(cd->dev, "%s: bus write fail on handshake (ret=%d)\n",
++				__func__, rc);
++
++	return rc;
++}
++
++static int cyttsp4_hw_soft_reset(struct cyttsp4 *cd)
++{
++	u8 cmd = CY_HST_RESET;
++	int rc = cyttsp4_adap_write(cd, CY_REG_BASE, sizeof(cmd), &cmd);
++	if (rc < 0) {
++		dev_err(cd->dev, "%s: FAILED to execute SOFT reset\n",
++				__func__);
++		return rc;
++	}
++	return 0;
++}
++
++static int cyttsp4_hw_hard_reset(struct cyttsp4 *cd)
++{
++	if (cd->cpdata->xres) {
++		cd->cpdata->xres(cd->cpdata, cd->dev);
++		dev_dbg(cd->dev, "%s: execute HARD reset\n", __func__);
++		return 0;
++	}
++	dev_err(cd->dev, "%s: FAILED to execute HARD reset\n", __func__);
++	return -ENOSYS;
++}
++
++static int cyttsp4_hw_reset(struct cyttsp4 *cd)
++{
++	int rc = cyttsp4_hw_hard_reset(cd);
++	if (rc == -ENOSYS)
++		rc = cyttsp4_hw_soft_reset(cd);
++	return rc;
++}
++
++/*
++ * Gets number of bits for a touch filed as parameter,
++ * sets maximum value for field which is used as bit mask
++ * and returns number of bytes required for that field
++ */
++static int cyttsp4_bits_2_bytes(unsigned int nbits, size_t *max)
++{
++	*max = 1UL << nbits;
++	return (nbits + 7) / 8;
++}
++
++static int cyttsp4_si_data_offsets(struct cyttsp4 *cd)
++{
++	struct cyttsp4_sysinfo *si = &cd->sysinfo;
++	int rc = cyttsp4_adap_read(cd, CY_REG_BASE, sizeof(si->si_data),
++			&si->si_data);
++	if (rc < 0) {
++		dev_err(cd->dev, "%s: fail read sysinfo data offsets r=%d\n",
++			__func__, rc);
++		return rc;
++	}
++
++	/* Print sysinfo data offsets */
++	cyttsp4_pr_buf(cd->dev, cd->pr_buf, (u8 *)&si->si_data,
++		       sizeof(si->si_data), "sysinfo_data_offsets");
++
++	/* convert sysinfo data offset bytes into integers */
++
++	si->si_ofs.map_sz = merge_bytes(si->si_data.map_szh,
++			si->si_data.map_szl);
++	si->si_ofs.map_sz = merge_bytes(si->si_data.map_szh,
++			si->si_data.map_szl);
++	si->si_ofs.cydata_ofs = merge_bytes(si->si_data.cydata_ofsh,
++			si->si_data.cydata_ofsl);
++	si->si_ofs.test_ofs = merge_bytes(si->si_data.test_ofsh,
++			si->si_data.test_ofsl);
++	si->si_ofs.pcfg_ofs = merge_bytes(si->si_data.pcfg_ofsh,
++			si->si_data.pcfg_ofsl);
++	si->si_ofs.opcfg_ofs = merge_bytes(si->si_data.opcfg_ofsh,
++			si->si_data.opcfg_ofsl);
++	si->si_ofs.ddata_ofs = merge_bytes(si->si_data.ddata_ofsh,
++			si->si_data.ddata_ofsl);
++	si->si_ofs.mdata_ofs = merge_bytes(si->si_data.mdata_ofsh,
++			si->si_data.mdata_ofsl);
++	return rc;
++}
++
++static int cyttsp4_si_get_cydata(struct cyttsp4 *cd)
++{
++	struct cyttsp4_sysinfo *si = &cd->sysinfo;
++	int read_offset;
++	int mfgid_sz, calc_mfgid_sz;
++	void *p;
++	int rc;
++
++	if (si->si_ofs.test_ofs <= si->si_ofs.cydata_ofs) {
++		dev_err(cd->dev,
++			"%s: invalid offset test_ofs: %zu, cydata_ofs: %zu\n",
++			__func__, si->si_ofs.test_ofs, si->si_ofs.cydata_ofs);
++		return -EINVAL;
++	}
++
++	si->si_ofs.cydata_size = si->si_ofs.test_ofs - si->si_ofs.cydata_ofs;
++	dev_dbg(cd->dev, "%s: cydata size: %zd\n", __func__,
++			si->si_ofs.cydata_size);
++
++	p = krealloc(si->si_ptrs.cydata, si->si_ofs.cydata_size, GFP_KERNEL);
++	if (p == NULL) {
++		dev_err(cd->dev, "%s: failed to allocate cydata memory\n",
++			__func__);
++		return -ENOMEM;
++	}
++	si->si_ptrs.cydata = p;
++
++	read_offset = si->si_ofs.cydata_ofs;
++
++	/* Read the CYDA registers up to MFGID field */
++	rc = cyttsp4_adap_read(cd, read_offset,
++			offsetof(struct cyttsp4_cydata, mfgid_sz)
++				+ sizeof(si->si_ptrs.cydata->mfgid_sz),
++			si->si_ptrs.cydata);
++	if (rc < 0) {
++		dev_err(cd->dev, "%s: fail read cydata r=%d\n",
++			__func__, rc);
++		return rc;
++	}
++
++	/* Check MFGID size */
++	mfgid_sz = si->si_ptrs.cydata->mfgid_sz;
++	calc_mfgid_sz = si->si_ofs.cydata_size - sizeof(struct cyttsp4_cydata);
++	if (mfgid_sz != calc_mfgid_sz) {
++		dev_err(cd->dev, "%s: mismatch in MFGID size, reported:%d calculated:%d\n",
++			__func__, mfgid_sz, calc_mfgid_sz);
++		return -EINVAL;
++	}
++
++	read_offset += offsetof(struct cyttsp4_cydata, mfgid_sz)
++			+ sizeof(si->si_ptrs.cydata->mfgid_sz);
++
++	/* Read the CYDA registers for MFGID field */
++	rc = cyttsp4_adap_read(cd, read_offset, si->si_ptrs.cydata->mfgid_sz,
++			si->si_ptrs.cydata->mfg_id);
++	if (rc < 0) {
++		dev_err(cd->dev, "%s: fail read cydata r=%d\n",
++			__func__, rc);
++		return rc;
++	}
++
++	read_offset += si->si_ptrs.cydata->mfgid_sz;
++
++	/* Read the rest of the CYDA registers */
++	rc = cyttsp4_adap_read(cd, read_offset,
++			sizeof(struct cyttsp4_cydata)
++				- offsetof(struct cyttsp4_cydata, cyito_idh),
++			&si->si_ptrs.cydata->cyito_idh);
++	if (rc < 0) {
++		dev_err(cd->dev, "%s: fail read cydata r=%d\n",
++			__func__, rc);
++		return rc;
++	}
++
++	cyttsp4_pr_buf(cd->dev, cd->pr_buf, (u8 *)si->si_ptrs.cydata,
++		si->si_ofs.cydata_size, "sysinfo_cydata");
++	return rc;
++}
++
++static int cyttsp4_si_get_test_data(struct cyttsp4 *cd)
++{
++	struct cyttsp4_sysinfo *si = &cd->sysinfo;
++	void *p;
++	int rc;
++
++	if (si->si_ofs.pcfg_ofs <= si->si_ofs.test_ofs) {
++		dev_err(cd->dev,
++			"%s: invalid offset pcfg_ofs: %zu, test_ofs: %zu\n",
++			__func__, si->si_ofs.pcfg_ofs, si->si_ofs.test_ofs);
++		return -EINVAL;
++	}
++
++	si->si_ofs.test_size = si->si_ofs.pcfg_ofs - si->si_ofs.test_ofs;
++
++	p = krealloc(si->si_ptrs.test, si->si_ofs.test_size, GFP_KERNEL);
++	if (p == NULL) {
++		dev_err(cd->dev, "%s: failed to allocate test memory\n",
++			__func__);
++		return -ENOMEM;
++	}
++	si->si_ptrs.test = p;
++
++	rc = cyttsp4_adap_read(cd, si->si_ofs.test_ofs, si->si_ofs.test_size,
++			si->si_ptrs.test);
++	if (rc < 0) {
++		dev_err(cd->dev, "%s: fail read test data r=%d\n",
++			__func__, rc);
++		return rc;
++	}
++
++	cyttsp4_pr_buf(cd->dev, cd->pr_buf,
++		       (u8 *)si->si_ptrs.test, si->si_ofs.test_size,
++		       "sysinfo_test_data");
++	if (si->si_ptrs.test->post_codel &
++	    CY_POST_CODEL_WDG_RST)
++		dev_info(cd->dev, "%s: %s codel=%02X\n",
++			 __func__, "Reset was a WATCHDOG RESET",
++			 si->si_ptrs.test->post_codel);
++
++	if (!(si->si_ptrs.test->post_codel &
++	      CY_POST_CODEL_CFG_DATA_CRC_FAIL))
++		dev_info(cd->dev, "%s: %s codel=%02X\n", __func__,
++			 "Config Data CRC FAIL",
++			 si->si_ptrs.test->post_codel);
++
++	if (!(si->si_ptrs.test->post_codel &
++	      CY_POST_CODEL_PANEL_TEST_FAIL))
++		dev_info(cd->dev, "%s: %s codel=%02X\n",
++			 __func__, "PANEL TEST FAIL",
++			 si->si_ptrs.test->post_codel);
++
++	dev_info(cd->dev, "%s: SCANNING is %s codel=%02X\n",
++		 __func__, si->si_ptrs.test->post_codel & 0x08 ?
++		 "ENABLED" : "DISABLED",
++		 si->si_ptrs.test->post_codel);
++	return rc;
++}
++
++static int cyttsp4_si_get_pcfg_data(struct cyttsp4 *cd)
++{
++	struct cyttsp4_sysinfo *si = &cd->sysinfo;
++	void *p;
++	int rc;
++
++	if (si->si_ofs.opcfg_ofs <= si->si_ofs.pcfg_ofs) {
++		dev_err(cd->dev,
++			"%s: invalid offset opcfg_ofs: %zu, pcfg_ofs: %zu\n",
++			__func__, si->si_ofs.opcfg_ofs, si->si_ofs.pcfg_ofs);
++		return -EINVAL;
++	}
++
++	si->si_ofs.pcfg_size = si->si_ofs.opcfg_ofs - si->si_ofs.pcfg_ofs;
++
++	p = krealloc(si->si_ptrs.pcfg, si->si_ofs.pcfg_size, GFP_KERNEL);
++	if (p == NULL) {
++		dev_err(cd->dev, "%s: failed to allocate pcfg memory\n",
++			__func__);
++		return -ENOMEM;
++	}
++	si->si_ptrs.pcfg = p;
++
++	rc = cyttsp4_adap_read(cd, si->si_ofs.pcfg_ofs, si->si_ofs.pcfg_size,
++			si->si_ptrs.pcfg);
++	if (rc < 0) {
++		dev_err(cd->dev, "%s: fail read pcfg data r=%d\n",
++			__func__, rc);
++		return rc;
++	}
++
++	si->si_ofs.max_x = merge_bytes((si->si_ptrs.pcfg->res_xh
++			& CY_PCFG_RESOLUTION_X_MASK), si->si_ptrs.pcfg->res_xl);
++	si->si_ofs.x_origin = !!(si->si_ptrs.pcfg->res_xh
++			& CY_PCFG_ORIGIN_X_MASK);
++	si->si_ofs.max_y = merge_bytes((si->si_ptrs.pcfg->res_yh
++			& CY_PCFG_RESOLUTION_Y_MASK), si->si_ptrs.pcfg->res_yl);
++	si->si_ofs.y_origin = !!(si->si_ptrs.pcfg->res_yh
++			& CY_PCFG_ORIGIN_Y_MASK);
++	si->si_ofs.max_p = merge_bytes(si->si_ptrs.pcfg->max_zh,
++			si->si_ptrs.pcfg->max_zl);
++
++	cyttsp4_pr_buf(cd->dev, cd->pr_buf,
++		       (u8 *)si->si_ptrs.pcfg,
++		       si->si_ofs.pcfg_size, "sysinfo_pcfg_data");
++	return rc;
++}
++
++static int cyttsp4_si_get_opcfg_data(struct cyttsp4 *cd)
++{
++	struct cyttsp4_sysinfo *si = &cd->sysinfo;
++	struct cyttsp4_tch_abs_params *tch;
++	struct cyttsp4_tch_rec_params *tch_old, *tch_new;
++	enum cyttsp4_tch_abs abs;
++	int i;
++	void *p;
++	int rc;
++
++	if (si->si_ofs.ddata_ofs <= si->si_ofs.opcfg_ofs) {
++		dev_err(cd->dev,
++			"%s: invalid offset ddata_ofs: %zu, opcfg_ofs: %zu\n",
++			__func__, si->si_ofs.ddata_ofs, si->si_ofs.opcfg_ofs);
++		return -EINVAL;
++	}
++
++	si->si_ofs.opcfg_size = si->si_ofs.ddata_ofs - si->si_ofs.opcfg_ofs;
++
++	p = krealloc(si->si_ptrs.opcfg, si->si_ofs.opcfg_size, GFP_KERNEL);
++	if (p == NULL) {
++		dev_err(cd->dev, "%s: failed to allocate opcfg memory\n",
++			__func__);
++		return -ENOMEM;
++	}
++	si->si_ptrs.opcfg = p;
++
++	rc = cyttsp4_adap_read(cd, si->si_ofs.opcfg_ofs, si->si_ofs.opcfg_size,
++			si->si_ptrs.opcfg);
++	if (rc < 0) {
++		dev_err(cd->dev, "%s: fail read opcfg data r=%d\n",
++			__func__, rc);
++		return rc;
++	}
++	si->si_ofs.cmd_ofs = si->si_ptrs.opcfg->cmd_ofs;
++	si->si_ofs.rep_ofs = si->si_ptrs.opcfg->rep_ofs;
++	si->si_ofs.rep_sz = (si->si_ptrs.opcfg->rep_szh * 256) +
++		si->si_ptrs.opcfg->rep_szl;
++	si->si_ofs.num_btns = si->si_ptrs.opcfg->num_btns;
++	si->si_ofs.num_btn_regs = (si->si_ofs.num_btns +
++		CY_NUM_BTN_PER_REG - 1) / CY_NUM_BTN_PER_REG;
++	si->si_ofs.tt_stat_ofs = si->si_ptrs.opcfg->tt_stat_ofs;
++	si->si_ofs.obj_cfg0 = si->si_ptrs.opcfg->obj_cfg0;
++	si->si_ofs.max_tchs = si->si_ptrs.opcfg->max_tchs &
++		CY_BYTE_OFS_MASK;
++	si->si_ofs.tch_rec_size = si->si_ptrs.opcfg->tch_rec_size &
++		CY_BYTE_OFS_MASK;
++
++	/* Get the old touch fields */
++	for (abs = CY_TCH_X; abs < CY_NUM_TCH_FIELDS; abs++) {
++		tch = &si->si_ofs.tch_abs[abs];
++		tch_old = &si->si_ptrs.opcfg->tch_rec_old[abs];
++
++		tch->ofs = tch_old->loc & CY_BYTE_OFS_MASK;
++		tch->size = cyttsp4_bits_2_bytes(tch_old->size,
++						 &tch->max);
++		tch->bofs = (tch_old->loc & CY_BOFS_MASK) >> CY_BOFS_SHIFT;
++	}
++
++	/* button fields */
++	si->si_ofs.btn_rec_size = si->si_ptrs.opcfg->btn_rec_size;
++	si->si_ofs.btn_diff_ofs = si->si_ptrs.opcfg->btn_diff_ofs;
++	si->si_ofs.btn_diff_size = si->si_ptrs.opcfg->btn_diff_size;
++
++	if (si->si_ofs.tch_rec_size > CY_TMA1036_TCH_REC_SIZE) {
++		/* Get the extended touch fields */
++		for (i = 0; i < CY_NUM_EXT_TCH_FIELDS; abs++, i++) {
++			tch = &si->si_ofs.tch_abs[abs];
++			tch_new = &si->si_ptrs.opcfg->tch_rec_new[i];
++
++			tch->ofs = tch_new->loc & CY_BYTE_OFS_MASK;
++			tch->size = cyttsp4_bits_2_bytes(tch_new->size,
++							 &tch->max);
++			tch->bofs = (tch_new->loc & CY_BOFS_MASK) >> CY_BOFS_SHIFT;
++		}
++	}
++
++	for (abs = 0; abs < CY_TCH_NUM_ABS; abs++) {
++		dev_dbg(cd->dev, "%s: tch_rec_%s\n", __func__,
++			cyttsp4_tch_abs_string[abs]);
++		dev_dbg(cd->dev, "%s:     ofs =%2zd\n", __func__,
++			si->si_ofs.tch_abs[abs].ofs);
++		dev_dbg(cd->dev, "%s:     siz =%2zd\n", __func__,
++			si->si_ofs.tch_abs[abs].size);
++		dev_dbg(cd->dev, "%s:     max =%2zd\n", __func__,
++			si->si_ofs.tch_abs[abs].max);
++		dev_dbg(cd->dev, "%s:     bofs=%2zd\n", __func__,
++			si->si_ofs.tch_abs[abs].bofs);
++	}
++
++	si->si_ofs.mode_size = si->si_ofs.tt_stat_ofs + 1;
++	si->si_ofs.data_size = si->si_ofs.max_tchs *
++		si->si_ptrs.opcfg->tch_rec_size;
++
++	cyttsp4_pr_buf(cd->dev, cd->pr_buf, (u8 *)si->si_ptrs.opcfg,
++		si->si_ofs.opcfg_size, "sysinfo_opcfg_data");
++
++	return 0;
++}
++
++static int cyttsp4_si_get_ddata(struct cyttsp4 *cd)
++{
++	struct cyttsp4_sysinfo *si = &cd->sysinfo;
++	void *p;
++	int rc;
++
++	si->si_ofs.ddata_size = si->si_ofs.mdata_ofs - si->si_ofs.ddata_ofs;
++
++	p = krealloc(si->si_ptrs.ddata, si->si_ofs.ddata_size, GFP_KERNEL);
++	if (p == NULL) {
++		dev_err(cd->dev, "%s: fail alloc ddata memory\n", __func__);
++		return -ENOMEM;
++	}
++	si->si_ptrs.ddata = p;
++
++	rc = cyttsp4_adap_read(cd, si->si_ofs.ddata_ofs, si->si_ofs.ddata_size,
++			si->si_ptrs.ddata);
++	if (rc < 0)
++		dev_err(cd->dev, "%s: fail read ddata data r=%d\n",
++			__func__, rc);
++	else
++		cyttsp4_pr_buf(cd->dev, cd->pr_buf,
++			       (u8 *)si->si_ptrs.ddata,
++			       si->si_ofs.ddata_size, "sysinfo_ddata");
++	return rc;
++}
++
++static int cyttsp4_si_get_mdata(struct cyttsp4 *cd)
++{
++	struct cyttsp4_sysinfo *si = &cd->sysinfo;
++	void *p;
++	int rc;
++
++	si->si_ofs.mdata_size = si->si_ofs.map_sz - si->si_ofs.mdata_ofs;
++
++	p = krealloc(si->si_ptrs.mdata, si->si_ofs.mdata_size, GFP_KERNEL);
++	if (p == NULL) {
++		dev_err(cd->dev, "%s: fail alloc mdata memory\n", __func__);
++		return -ENOMEM;
++	}
++	si->si_ptrs.mdata = p;
++
++	rc = cyttsp4_adap_read(cd, si->si_ofs.mdata_ofs, si->si_ofs.mdata_size,
++			si->si_ptrs.mdata);
++	if (rc < 0)
++		dev_err(cd->dev, "%s: fail read mdata data r=%d\n",
++			__func__, rc);
++	else
++		cyttsp4_pr_buf(cd->dev, cd->pr_buf,
++			       (u8 *)si->si_ptrs.mdata,
++			       si->si_ofs.mdata_size, "sysinfo_mdata");
++	return rc;
++}
++
++static int cyttsp4_si_get_btn_data(struct cyttsp4 *cd)
++{
++	struct cyttsp4_sysinfo *si = &cd->sysinfo;
++	int btn;
++	int num_defined_keys;
++	u16 *key_table;
++	void *p;
++	int rc = 0;
++
++	if (si->si_ofs.num_btns) {
++		si->si_ofs.btn_keys_size = si->si_ofs.num_btns *
++			sizeof(struct cyttsp4_btn);
++
++		p = krealloc(si->btn, si->si_ofs.btn_keys_size,
++				GFP_KERNEL|__GFP_ZERO);
++		if (p == NULL) {
++			dev_err(cd->dev, "%s: %s\n", __func__,
++				"fail alloc btn_keys memory");
++			return -ENOMEM;
++		}
++		si->btn = p;
++
++		if (cd->cpdata->sett[CY_IC_GRPNUM_BTN_KEYS] == NULL)
++			num_defined_keys = 0;
++		else if (cd->cpdata->sett[CY_IC_GRPNUM_BTN_KEYS]->data == NULL)
++			num_defined_keys = 0;
++		else
++			num_defined_keys = cd->cpdata->sett
++				[CY_IC_GRPNUM_BTN_KEYS]->size;
++
++		for (btn = 0; btn < si->si_ofs.num_btns &&
++			btn < num_defined_keys; btn++) {
++			key_table = (u16 *)cd->cpdata->sett
++				[CY_IC_GRPNUM_BTN_KEYS]->data;
++			si->btn[btn].key_code = key_table[btn];
++			si->btn[btn].state = CY_BTN_RELEASED;
++			si->btn[btn].enabled = true;
++		}
++		for (; btn < si->si_ofs.num_btns; btn++) {
++			si->btn[btn].key_code = KEY_RESERVED;
++			si->btn[btn].state = CY_BTN_RELEASED;
++			si->btn[btn].enabled = true;
++		}
++
++		return rc;
++	}
++
++	si->si_ofs.btn_keys_size = 0;
++	kfree(si->btn);
++	si->btn = NULL;
++	return rc;
++}
++
++static int cyttsp4_si_get_op_data_ptrs(struct cyttsp4 *cd)
++{
++	struct cyttsp4_sysinfo *si = &cd->sysinfo;
++	void *p;
++
++	p = krealloc(si->xy_mode, si->si_ofs.mode_size, GFP_KERNEL|__GFP_ZERO);
++	if (p == NULL)
++		return -ENOMEM;
++	si->xy_mode = p;
++
++	p = krealloc(si->xy_data, si->si_ofs.data_size, GFP_KERNEL|__GFP_ZERO);
++	if (p == NULL)
++		return -ENOMEM;
++	si->xy_data = p;
++
++	p = krealloc(si->btn_rec_data,
++			si->si_ofs.btn_rec_size * si->si_ofs.num_btns,
++			GFP_KERNEL|__GFP_ZERO);
++	if (p == NULL)
++		return -ENOMEM;
++	si->btn_rec_data = p;
++
++	return 0;
++}
++
++static void cyttsp4_si_put_log_data(struct cyttsp4 *cd)
++{
++	struct cyttsp4_sysinfo *si = &cd->sysinfo;
++	dev_dbg(cd->dev, "%s: cydata_ofs =%4zd siz=%4zd\n", __func__,
++		si->si_ofs.cydata_ofs, si->si_ofs.cydata_size);
++	dev_dbg(cd->dev, "%s: test_ofs   =%4zd siz=%4zd\n", __func__,
++		si->si_ofs.test_ofs, si->si_ofs.test_size);
++	dev_dbg(cd->dev, "%s: pcfg_ofs   =%4zd siz=%4zd\n", __func__,
++		si->si_ofs.pcfg_ofs, si->si_ofs.pcfg_size);
++	dev_dbg(cd->dev, "%s: opcfg_ofs  =%4zd siz=%4zd\n", __func__,
++		si->si_ofs.opcfg_ofs, si->si_ofs.opcfg_size);
++	dev_dbg(cd->dev, "%s: ddata_ofs  =%4zd siz=%4zd\n", __func__,
++		si->si_ofs.ddata_ofs, si->si_ofs.ddata_size);
++	dev_dbg(cd->dev, "%s: mdata_ofs  =%4zd siz=%4zd\n", __func__,
++		si->si_ofs.mdata_ofs, si->si_ofs.mdata_size);
++
++	dev_dbg(cd->dev, "%s: cmd_ofs       =%4zd\n", __func__,
++		si->si_ofs.cmd_ofs);
++	dev_dbg(cd->dev, "%s: rep_ofs       =%4zd\n", __func__,
++		si->si_ofs.rep_ofs);
++	dev_dbg(cd->dev, "%s: rep_sz        =%4zd\n", __func__,
++		si->si_ofs.rep_sz);
++	dev_dbg(cd->dev, "%s: num_btns      =%4zd\n", __func__,
++		si->si_ofs.num_btns);
++	dev_dbg(cd->dev, "%s: num_btn_regs  =%4zd\n", __func__,
++		si->si_ofs.num_btn_regs);
++	dev_dbg(cd->dev, "%s: tt_stat_ofs   =%4zd\n", __func__,
++		si->si_ofs.tt_stat_ofs);
++	dev_dbg(cd->dev, "%s: tch_rec_size  =%4zd\n", __func__,
++		si->si_ofs.tch_rec_size);
++	dev_dbg(cd->dev, "%s: max_tchs      =%4zd\n", __func__,
++		si->si_ofs.max_tchs);
++	dev_dbg(cd->dev, "%s: mode_size     =%4zd\n", __func__,
++		si->si_ofs.mode_size);
++	dev_dbg(cd->dev, "%s: data_size     =%4zd\n", __func__,
++		si->si_ofs.data_size);
++	dev_dbg(cd->dev, "%s: map_sz        =%4zd\n", __func__,
++		si->si_ofs.map_sz);
++
++	dev_dbg(cd->dev, "%s: btn_rec_size   =%2zd\n", __func__,
++		si->si_ofs.btn_rec_size);
++	dev_dbg(cd->dev, "%s: btn_diff_ofs   =%2zd\n", __func__,
++		si->si_ofs.btn_diff_ofs);
++	dev_dbg(cd->dev, "%s: btn_diff_size  =%2zd\n", __func__,
++		si->si_ofs.btn_diff_size);
++
++	dev_dbg(cd->dev, "%s: max_x    = 0x%04zX (%zd)\n", __func__,
++		si->si_ofs.max_x, si->si_ofs.max_x);
++	dev_dbg(cd->dev, "%s: x_origin = %zd (%s)\n", __func__,
++		si->si_ofs.x_origin,
++		si->si_ofs.x_origin == CY_NORMAL_ORIGIN ?
++		"left corner" : "right corner");
++	dev_dbg(cd->dev, "%s: max_y    = 0x%04zX (%zd)\n", __func__,
++		si->si_ofs.max_y, si->si_ofs.max_y);
++	dev_dbg(cd->dev, "%s: y_origin = %zd (%s)\n", __func__,
++		si->si_ofs.y_origin,
++		si->si_ofs.y_origin == CY_NORMAL_ORIGIN ?
++		"upper corner" : "lower corner");
++	dev_dbg(cd->dev, "%s: max_p    = 0x%04zX (%zd)\n", __func__,
++		si->si_ofs.max_p, si->si_ofs.max_p);
++
++	dev_dbg(cd->dev, "%s: xy_mode=%p xy_data=%p\n", __func__,
++		si->xy_mode, si->xy_data);
++}
++
++static int cyttsp4_get_sysinfo_regs(struct cyttsp4 *cd)
++{
++	struct cyttsp4_sysinfo *si = &cd->sysinfo;
++	int rc;
++
++	rc = cyttsp4_si_data_offsets(cd);
++	if (rc < 0)
++		return rc;
++
++	rc = cyttsp4_si_get_cydata(cd);
++	if (rc < 0)
++		return rc;
++
++	rc = cyttsp4_si_get_test_data(cd);
++	if (rc < 0)
++		return rc;
++
++	rc = cyttsp4_si_get_pcfg_data(cd);
++	if (rc < 0)
++		return rc;
++
++	rc = cyttsp4_si_get_opcfg_data(cd);
++	if (rc < 0)
++		return rc;
++
++	rc = cyttsp4_si_get_ddata(cd);
++	if (rc < 0)
++		return rc;
++
++	rc = cyttsp4_si_get_mdata(cd);
++	if (rc < 0)
++		return rc;
++
++	rc = cyttsp4_si_get_btn_data(cd);
++	if (rc < 0)
++		return rc;
++
++	rc = cyttsp4_si_get_op_data_ptrs(cd);
++	if (rc < 0) {
++		dev_err(cd->dev, "%s: failed to get_op_data\n",
++			__func__);
++		return rc;
++	}
++
++	cyttsp4_si_put_log_data(cd);
++
++	/* provide flow control handshake */
++	rc = cyttsp4_handshake(cd, si->si_data.hst_mode);
++	if (rc < 0)
++		dev_err(cd->dev, "%s: handshake fail on sysinfo reg\n",
++			__func__);
++
++	si->ready = true;
++	return rc;
++}
++
++static void cyttsp4_queue_startup_(struct cyttsp4 *cd)
++{
++	if (cd->startup_state == STARTUP_NONE) {
++		cd->startup_state = STARTUP_QUEUED;
++		schedule_work(&cd->startup_work);
++		dev_dbg(cd->dev, "%s: cyttsp4_startup queued\n", __func__);
++	} else {
++		dev_dbg(cd->dev, "%s: startup_state = %d\n", __func__,
++			cd->startup_state);
++	}
++}
++
++static void cyttsp4_report_slot_liftoff(struct cyttsp4_mt_data *md,
++		int max_slots)
++{
++	int t;
++
++	if (md->num_prv_tch == 0)
++		return;
++
++	for (t = 0; t < max_slots; t++) {
++		input_mt_slot(md->input, t);
++		input_mt_report_slot_inactive(md->input);
++	}
++}
++
++static void cyttsp4_lift_all(struct cyttsp4_mt_data *md)
++{
++	if (!md->si)
++		return;
++
++	if (md->num_prv_tch != 0) {
++		cyttsp4_report_slot_liftoff(md,
++				md->si->si_ofs.tch_abs[CY_TCH_T].max);
++		input_sync(md->input);
++		md->num_prv_tch = 0;
++	}
++}
++
++static void cyttsp4_get_touch_axis(struct cyttsp4_mt_data *md,
++	int *axis, int size, int max, u8 *xy_data, int bofs)
++{
++	int nbyte;
++	int next;
++
++	for (nbyte = 0, *axis = 0, next = 0; nbyte < size; nbyte++) {
++		dev_vdbg(&md->input->dev,
++			"%s: *axis=%02X(%d) size=%d max=%08X xy_data=%p"
++			" xy_data[%d]=%02X(%d) bofs=%d\n",
++			__func__, *axis, *axis, size, max, xy_data, next,
++			xy_data[next], xy_data[next], bofs);
++		*axis = (*axis * 256) + (xy_data[next] >> bofs);
++		next++;
++	}
++
++	*axis &= max - 1;
++
++	dev_vdbg(&md->input->dev,
++		"%s: *axis=%02X(%d) size=%d max=%08X xy_data=%p"
++		" xy_data[%d]=%02X(%d)\n",
++		__func__, *axis, *axis, size, max, xy_data, next,
++		xy_data[next], xy_data[next]);
++}
++
++static void cyttsp4_get_touch(struct cyttsp4_mt_data *md,
++	struct cyttsp4_touch *touch, u8 *xy_data)
++{
++	struct device *dev = &md->input->dev;
++	struct cyttsp4_sysinfo *si = md->si;
++	enum cyttsp4_tch_abs abs;
++	bool flipped;
++
++	for (abs = CY_TCH_X; abs < CY_TCH_NUM_ABS; abs++) {
++		cyttsp4_get_touch_axis(md, &touch->abs[abs],
++			si->si_ofs.tch_abs[abs].size,
++			si->si_ofs.tch_abs[abs].max,
++			xy_data + si->si_ofs.tch_abs[abs].ofs,
++			si->si_ofs.tch_abs[abs].bofs);
++		dev_vdbg(dev, "%s: get %s=%04X(%d)\n", __func__,
++			cyttsp4_tch_abs_string[abs],
++			touch->abs[abs], touch->abs[abs]);
++	}
++
++	if (md->pdata->flags & CY_FLAG_FLIP) {
++		swap(touch->abs[CY_TCH_X], touch->abs[CY_TCH_Y]);
++		flipped = true;
++	} else
++		flipped = false;
++
++	if (md->pdata->flags & CY_FLAG_INV_X) {
++		if (flipped)
++			touch->abs[CY_TCH_X] = md->si->si_ofs.max_y -
++				touch->abs[CY_TCH_X];
++		else
++			touch->abs[CY_TCH_X] = md->si->si_ofs.max_x -
++				touch->abs[CY_TCH_X];
++	}
++	if (md->pdata->flags & CY_FLAG_INV_Y) {
++		if (flipped)
++			touch->abs[CY_TCH_Y] = md->si->si_ofs.max_x -
++				touch->abs[CY_TCH_Y];
++		else
++			touch->abs[CY_TCH_Y] = md->si->si_ofs.max_y -
++				touch->abs[CY_TCH_Y];
++	}
++
++	dev_vdbg(dev, "%s: flip=%s inv-x=%s inv-y=%s x=%04X(%d) y=%04X(%d)\n",
++		__func__, flipped ? "true" : "false",
++		md->pdata->flags & CY_FLAG_INV_X ? "true" : "false",
++		md->pdata->flags & CY_FLAG_INV_Y ? "true" : "false",
++		touch->abs[CY_TCH_X], touch->abs[CY_TCH_X],
++		touch->abs[CY_TCH_Y], touch->abs[CY_TCH_Y]);
++}
++
++static void cyttsp4_final_sync(struct input_dev *input, int max_slots, int *ids)
++{
++	int t;
++
++	for (t = 0; t < max_slots; t++) {
++		if (ids[t])
++			continue;
++		input_mt_slot(input, t);
++		input_mt_report_slot_inactive(input);
++	}
++
++	input_sync(input);
++}
++
++static void cyttsp4_get_mt_touches(struct cyttsp4_mt_data *md, int num_cur_tch)
++{
++	struct device *dev = &md->input->dev;
++	struct cyttsp4_sysinfo *si = md->si;
++	struct cyttsp4_touch tch;
++	int sig;
++	int i, j, t = 0;
++	int ids[max(CY_TMA1036_MAX_TCH, CY_TMA4XX_MAX_TCH)];
++
++	memset(ids, 0, si->si_ofs.tch_abs[CY_TCH_T].max * sizeof(int));
++	for (i = 0; i < num_cur_tch; i++) {
++		cyttsp4_get_touch(md, &tch, si->xy_data +
++			(i * si->si_ofs.tch_rec_size));
++		if ((tch.abs[CY_TCH_T] < md->pdata->frmwrk->abs
++			[(CY_ABS_ID_OST * CY_NUM_ABS_SET) + CY_MIN_OST]) ||
++			(tch.abs[CY_TCH_T] > md->pdata->frmwrk->abs
++			[(CY_ABS_ID_OST * CY_NUM_ABS_SET) + CY_MAX_OST])) {
++			dev_err(dev, "%s: tch=%d -> bad trk_id=%d max_id=%d\n",
++				__func__, i, tch.abs[CY_TCH_T],
++				md->pdata->frmwrk->abs[(CY_ABS_ID_OST *
++				CY_NUM_ABS_SET) + CY_MAX_OST]);
++			continue;
++		}
++
++		/* use 0 based track id's */
++		sig = md->pdata->frmwrk->abs
++			[(CY_ABS_ID_OST * CY_NUM_ABS_SET) + 0];
++		if (sig != CY_IGNORE_VALUE) {
++			t = tch.abs[CY_TCH_T] - md->pdata->frmwrk->abs
++				[(CY_ABS_ID_OST * CY_NUM_ABS_SET) + CY_MIN_OST];
++			if (tch.abs[CY_TCH_E] == CY_EV_LIFTOFF) {
++				dev_dbg(dev, "%s: t=%d e=%d lift-off\n",
++					__func__, t, tch.abs[CY_TCH_E]);
++				goto cyttsp4_get_mt_touches_pr_tch;
++			}
++			input_mt_slot(md->input, t);
++			input_mt_report_slot_state(md->input, MT_TOOL_FINGER,
++					true);
++			ids[t] = true;
++		}
++
++		/* all devices: position and pressure fields */
++		for (j = 0; j <= CY_ABS_W_OST; j++) {
++			sig = md->pdata->frmwrk->abs[((CY_ABS_X_OST + j) *
++				CY_NUM_ABS_SET) + 0];
++			if (sig != CY_IGNORE_VALUE)
++				input_report_abs(md->input, sig,
++					tch.abs[CY_TCH_X + j]);
++		}
++		if (si->si_ofs.tch_rec_size > CY_TMA1036_TCH_REC_SIZE) {
++			/*
++			 * TMA400 size and orientation fields:
++			 * if pressure is non-zero and major touch
++			 * signal is zero, then set major and minor touch
++			 * signals to minimum non-zero value
++			 */
++			if (tch.abs[CY_TCH_P] > 0 && tch.abs[CY_TCH_MAJ] == 0)
++				tch.abs[CY_TCH_MAJ] = tch.abs[CY_TCH_MIN] = 1;
++
++			/* Get the extended touch fields */
++			for (j = 0; j < CY_NUM_EXT_TCH_FIELDS; j++) {
++				sig = md->pdata->frmwrk->abs
++					[((CY_ABS_MAJ_OST + j) *
++					CY_NUM_ABS_SET) + 0];
++				if (sig != CY_IGNORE_VALUE)
++					input_report_abs(md->input, sig,
++						tch.abs[CY_TCH_MAJ + j]);
++			}
++		}
++
++cyttsp4_get_mt_touches_pr_tch:
++		if (si->si_ofs.tch_rec_size > CY_TMA1036_TCH_REC_SIZE)
++			dev_dbg(dev,
++				"%s: t=%d x=%d y=%d z=%d M=%d m=%d o=%d e=%d\n",
++				__func__, t,
++				tch.abs[CY_TCH_X],
++				tch.abs[CY_TCH_Y],
++				tch.abs[CY_TCH_P],
++				tch.abs[CY_TCH_MAJ],
++				tch.abs[CY_TCH_MIN],
++				tch.abs[CY_TCH_OR],
++				tch.abs[CY_TCH_E]);
++		else
++			dev_dbg(dev,
++				"%s: t=%d x=%d y=%d z=%d e=%d\n", __func__,
++				t,
++				tch.abs[CY_TCH_X],
++				tch.abs[CY_TCH_Y],
++				tch.abs[CY_TCH_P],
++				tch.abs[CY_TCH_E]);
++	}
++
++	cyttsp4_final_sync(md->input, si->si_ofs.tch_abs[CY_TCH_T].max, ids);
++
++	md->num_prv_tch = num_cur_tch;
++
++	return;
++}
++
++/* read xy_data for all current touches */
++static int cyttsp4_xy_worker(struct cyttsp4 *cd)
++{
++	struct cyttsp4_mt_data *md = &cd->md;
++	struct device *dev = &md->input->dev;
++	struct cyttsp4_sysinfo *si = md->si;
++	u8 num_cur_tch;
++	u8 hst_mode;
++	u8 rep_len;
++	u8 rep_stat;
++	u8 tt_stat;
++	int rc = 0;
++
++	/*
++	 * Get event data from cyttsp4 device.
++	 * The event data includes all data
++	 * for all active touches.
++	 * Event data also includes button data
++	 */
++	/*
++	 * Use 2 reads:
++	 * 1st read to get mode + button bytes + touch count (core)
++	 * 2nd read (optional) to get touch 1 - touch n data
++	 */
++	hst_mode = si->xy_mode[CY_REG_BASE];
++	rep_len = si->xy_mode[si->si_ofs.rep_ofs];
++	rep_stat = si->xy_mode[si->si_ofs.rep_ofs + 1];
++	tt_stat = si->xy_mode[si->si_ofs.tt_stat_ofs];
++	dev_vdbg(dev, "%s: %s%02X %s%d %s%02X %s%02X\n", __func__,
++		"hst_mode=", hst_mode, "rep_len=", rep_len,
++		"rep_stat=", rep_stat, "tt_stat=", tt_stat);
++
++	num_cur_tch = GET_NUM_TOUCHES(tt_stat);
++	dev_vdbg(dev, "%s: num_cur_tch=%d\n", __func__, num_cur_tch);
++
++	if (rep_len == 0 && num_cur_tch > 0) {
++		dev_err(dev, "%s: report length error rep_len=%d num_tch=%d\n",
++			__func__, rep_len, num_cur_tch);
++		goto cyttsp4_xy_worker_exit;
++	}
++
++	/* read touches */
++	if (num_cur_tch > 0) {
++		rc = cyttsp4_adap_read(cd, si->si_ofs.tt_stat_ofs + 1,
++				num_cur_tch * si->si_ofs.tch_rec_size,
++				si->xy_data);
++		if (rc < 0) {
++			dev_err(dev, "%s: read fail on touch regs r=%d\n",
++				__func__, rc);
++			goto cyttsp4_xy_worker_exit;
++		}
++	}
++
++	/* print xy data */
++	cyttsp4_pr_buf(dev, cd->pr_buf, si->xy_data, num_cur_tch *
++		si->si_ofs.tch_rec_size, "xy_data");
++
++	/* check any error conditions */
++	if (IS_BAD_PKT(rep_stat)) {
++		dev_dbg(dev, "%s: Invalid buffer detected\n", __func__);
++		rc = 0;
++		goto cyttsp4_xy_worker_exit;
++	}
++
++	if (IS_LARGE_AREA(tt_stat))
++		dev_dbg(dev, "%s: Large area detected\n", __func__);
++
++	if (num_cur_tch > si->si_ofs.max_tchs) {
++		dev_err(dev, "%s: too many tch; set to max tch (n=%d c=%zd)\n",
++				__func__, num_cur_tch, si->si_ofs.max_tchs);
++		num_cur_tch = si->si_ofs.max_tchs;
++	}
++
++	/* extract xy_data for all currently reported touches */
++	dev_vdbg(dev, "%s: extract data num_cur_tch=%d\n", __func__,
++		num_cur_tch);
++	if (num_cur_tch)
++		cyttsp4_get_mt_touches(md, num_cur_tch);
++	else
++		cyttsp4_lift_all(md);
++
++	rc = 0;
++
++cyttsp4_xy_worker_exit:
++	return rc;
++}
++
++static int cyttsp4_mt_attention(struct cyttsp4 *cd)
++{
++	struct device *dev = cd->dev;
++	struct cyttsp4_mt_data *md = &cd->md;
++	int rc = 0;
++
++	if (!md->si)
++		return 0;
++
++	mutex_lock(&md->report_lock);
++	if (!md->is_suspended) {
++		/* core handles handshake */
++		rc = cyttsp4_xy_worker(cd);
++	} else {
++		dev_vdbg(dev, "%s: Ignoring report while suspended\n",
++			__func__);
++	}
++	mutex_unlock(&md->report_lock);
++	if (rc < 0)
++		dev_err(dev, "%s: xy_worker error r=%d\n", __func__, rc);
++
++	return rc;
++}
++
++static irqreturn_t cyttsp4_irq(int irq, void *handle)
++{
++	struct cyttsp4 *cd = handle;
++	struct device *dev = cd->dev;
++	enum cyttsp4_mode cur_mode;
++	u8 cmd_ofs = cd->sysinfo.si_ofs.cmd_ofs;
++	u8 mode[3];
++	int rc;
++
++	/*
++	 * Check whether this IRQ should be ignored (external)
++	 * This should be the very first thing to check since
++	 * ignore_irq may be set for a very short period of time
++	 */
++	if (atomic_read(&cd->ignore_irq)) {
++		dev_vdbg(dev, "%s: Ignoring IRQ\n", __func__);
++		return IRQ_HANDLED;
++	}
++
++	dev_dbg(dev, "%s int:0x%x\n", __func__, cd->int_status);
++
++	mutex_lock(&cd->system_lock);
++
++	/* Just to debug */
++	if (cd->sleep_state == SS_SLEEP_ON || cd->sleep_state == SS_SLEEPING)
++		dev_vdbg(dev, "%s: Received IRQ while in sleep\n", __func__);
++
++	rc = cyttsp4_adap_read(cd, CY_REG_BASE, sizeof(mode), mode);
++	if (rc) {
++		dev_err(cd->dev, "%s: Fail read adapter r=%d\n", __func__, rc);
++		goto cyttsp4_irq_exit;
++	}
++	dev_vdbg(dev, "%s mode[0-2]:0x%X 0x%X 0x%X\n", __func__,
++			mode[0], mode[1], mode[2]);
++
++	if (IS_BOOTLOADER(mode[0], mode[1])) {
++		cur_mode = CY_MODE_BOOTLOADER;
++		dev_vdbg(dev, "%s: bl running\n", __func__);
++		if (cd->mode == CY_MODE_BOOTLOADER) {
++			/* Signal bootloader heartbeat heard */
++			wake_up(&cd->wait_q);
++			goto cyttsp4_irq_exit;
++		}
++
++		/* switch to bootloader */
++		dev_dbg(dev, "%s: restart switch to bl m=%d -> m=%d\n",
++			__func__, cd->mode, cur_mode);
++
++		/* catch operation->bl glitch */
++		if (cd->mode != CY_MODE_UNKNOWN) {
++			/* Incase startup_state do not let startup_() */
++			cd->mode = CY_MODE_UNKNOWN;
++			cyttsp4_queue_startup_(cd);
++			goto cyttsp4_irq_exit;
++		}
++
++		/*
++		 * do not wake thread on this switch since
++		 * it is possible to get an early heartbeat
++		 * prior to performing the reset
++		 */
++		cd->mode = cur_mode;
++
++		goto cyttsp4_irq_exit;
++	}
++
++	switch (mode[0] & CY_HST_MODE) {
++	case CY_HST_OPERATE:
++		cur_mode = CY_MODE_OPERATIONAL;
++		dev_vdbg(dev, "%s: operational\n", __func__);
++		break;
++	case CY_HST_CAT:
++		cur_mode = CY_MODE_CAT;
++		dev_vdbg(dev, "%s: CaT\n", __func__);
++		break;
++	case CY_HST_SYSINFO:
++		cur_mode = CY_MODE_SYSINFO;
++		dev_vdbg(dev, "%s: sysinfo\n", __func__);
++		break;
++	default:
++		cur_mode = CY_MODE_UNKNOWN;
++		dev_err(dev, "%s: unknown HST mode 0x%02X\n", __func__,
++			mode[0]);
++		break;
++	}
++
++	/* Check whether this IRQ should be ignored (internal) */
++	if (cd->int_status & CY_INT_IGNORE) {
++		dev_vdbg(dev, "%s: Ignoring IRQ\n", __func__);
++		goto cyttsp4_irq_exit;
++	}
++
++	/* Check for wake up interrupt */
++	if (cd->int_status & CY_INT_AWAKE) {
++		cd->int_status &= ~CY_INT_AWAKE;
++		wake_up(&cd->wait_q);
++		dev_vdbg(dev, "%s: Received wake up interrupt\n", __func__);
++		goto cyttsp4_irq_handshake;
++	}
++
++	/* Expecting mode change interrupt */
++	if ((cd->int_status & CY_INT_MODE_CHANGE)
++			&& (mode[0] & CY_HST_MODE_CHANGE) == 0) {
++		cd->int_status &= ~CY_INT_MODE_CHANGE;
++		dev_dbg(dev, "%s: finish mode switch m=%d -> m=%d\n",
++				__func__, cd->mode, cur_mode);
++		cd->mode = cur_mode;
++		wake_up(&cd->wait_q);
++		goto cyttsp4_irq_handshake;
++	}
++
++	/* compare current core mode to current device mode */
++	dev_vdbg(dev, "%s: cd->mode=%d cur_mode=%d\n",
++			__func__, cd->mode, cur_mode);
++	if ((mode[0] & CY_HST_MODE_CHANGE) == 0 && cd->mode != cur_mode) {
++		/* Unexpected mode change occurred */
++		dev_err(dev, "%s %d->%d 0x%x\n", __func__, cd->mode,
++				cur_mode, cd->int_status);
++		dev_dbg(dev, "%s: Unexpected mode change, startup\n",
++				__func__);
++		cyttsp4_queue_startup_(cd);
++		goto cyttsp4_irq_exit;
++	}
++
++	/* Expecting command complete interrupt */
++	dev_vdbg(dev, "%s: command byte:0x%x\n", __func__, mode[cmd_ofs]);
++	if ((cd->int_status & CY_INT_EXEC_CMD)
++			&& mode[cmd_ofs] & CY_CMD_COMPLETE) {
++		cd->int_status &= ~CY_INT_EXEC_CMD;
++		dev_vdbg(dev, "%s: Received command complete interrupt\n",
++				__func__);
++		wake_up(&cd->wait_q);
++		/*
++		 * It is possible to receive a single interrupt for
++		 * command complete and touch/button status report.
++		 * Continue processing for a possible status report.
++		 */
++	}
++
++	/* This should be status report, read status regs */
++	if (cd->mode == CY_MODE_OPERATIONAL) {
++		dev_vdbg(dev, "%s: Read status registers\n", __func__);
++		rc = cyttsp4_load_status_regs(cd);
++		if (rc < 0)
++			dev_err(dev, "%s: fail read mode regs r=%d\n",
++				__func__, rc);
++	}
++
++	cyttsp4_mt_attention(cd);
++
++cyttsp4_irq_handshake:
++	/* handshake the event */
++	dev_vdbg(dev, "%s: Handshake mode=0x%02X r=%d\n",
++			__func__, mode[0], rc);
++	rc = cyttsp4_handshake(cd, mode[0]);
++	if (rc < 0)
++		dev_err(dev, "%s: Fail handshake mode=0x%02X r=%d\n",
++				__func__, mode[0], rc);
++
++	/*
++	 * a non-zero udelay period is required for using
++	 * IRQF_TRIGGER_LOW in order to delay until the
++	 * device completes isr deassert
++	 */
++	udelay(cd->cpdata->level_irq_udelay);
++
++cyttsp4_irq_exit:
++	mutex_unlock(&cd->system_lock);
++	return IRQ_HANDLED;
++}
++
++static void cyttsp4_start_wd_timer(struct cyttsp4 *cd)
++{
++	if (!CY_WATCHDOG_TIMEOUT)
++		return;
++
++	mod_timer(&cd->watchdog_timer, jiffies +
++			msecs_to_jiffies(CY_WATCHDOG_TIMEOUT));
++}
++
++static void cyttsp4_stop_wd_timer(struct cyttsp4 *cd)
++{
++	if (!CY_WATCHDOG_TIMEOUT)
++		return;
++
++	/*
++	 * Ensure we wait until the watchdog timer
++	 * running on a different CPU finishes
++	 */
++	timer_shutdown_sync(&cd->watchdog_timer);
++	cancel_work_sync(&cd->watchdog_work);
++}
++
++static void cyttsp4_watchdog_timer(struct timer_list *t)
++{
++	struct cyttsp4 *cd = from_timer(cd, t, watchdog_timer);
++
++	dev_vdbg(cd->dev, "%s: Watchdog timer triggered\n", __func__);
++
++	schedule_work(&cd->watchdog_work);
++
++	return;
++}
++
++static int cyttsp4_request_exclusive(struct cyttsp4 *cd, void *ownptr,
++		int timeout_ms)
++{
++	int t = msecs_to_jiffies(timeout_ms);
++	bool with_timeout = (timeout_ms != 0);
++
++	mutex_lock(&cd->system_lock);
++	if (!cd->exclusive_dev && cd->exclusive_waits == 0) {
++		cd->exclusive_dev = ownptr;
++		goto exit;
++	}
++
++	cd->exclusive_waits++;
++wait:
++	mutex_unlock(&cd->system_lock);
++	if (with_timeout) {
++		t = wait_event_timeout(cd->wait_q, !cd->exclusive_dev, t);
++		if (IS_TMO(t)) {
++			dev_err(cd->dev, "%s: tmo waiting exclusive access\n",
++				__func__);
++			mutex_lock(&cd->system_lock);
++			cd->exclusive_waits--;
++			mutex_unlock(&cd->system_lock);
++			return -ETIME;
++		}
++	} else {
++		wait_event(cd->wait_q, !cd->exclusive_dev);
++	}
++	mutex_lock(&cd->system_lock);
++	if (cd->exclusive_dev)
++		goto wait;
++	cd->exclusive_dev = ownptr;
++	cd->exclusive_waits--;
++exit:
++	mutex_unlock(&cd->system_lock);
++
++	return 0;
++}
++
++/*
++ * returns error if was not owned
++ */
++static int cyttsp4_release_exclusive(struct cyttsp4 *cd, void *ownptr)
++{
++	mutex_lock(&cd->system_lock);
++	if (cd->exclusive_dev != ownptr) {
++		mutex_unlock(&cd->system_lock);
++		return -EINVAL;
++	}
++
++	dev_vdbg(cd->dev, "%s: exclusive_dev %p freed\n",
++		__func__, cd->exclusive_dev);
++	cd->exclusive_dev = NULL;
++	wake_up(&cd->wait_q);
++	mutex_unlock(&cd->system_lock);
++	return 0;
++}
++
++static int cyttsp4_wait_bl_heartbeat(struct cyttsp4 *cd)
++{
++	long t;
++	int rc = 0;
++
++	/* wait heartbeat */
++	dev_vdbg(cd->dev, "%s: wait heartbeat...\n", __func__);
++	t = wait_event_timeout(cd->wait_q, cd->mode == CY_MODE_BOOTLOADER,
++			msecs_to_jiffies(CY_CORE_RESET_AND_WAIT_TIMEOUT));
++	if (IS_TMO(t)) {
++		dev_err(cd->dev, "%s: tmo waiting bl heartbeat cd->mode=%d\n",
++			__func__, cd->mode);
++		rc = -ETIME;
++	}
++
++	return rc;
++}
++
++static int cyttsp4_wait_sysinfo_mode(struct cyttsp4 *cd)
++{
++	long t;
++
++	dev_vdbg(cd->dev, "%s: wait sysinfo...\n", __func__);
++
++	t = wait_event_timeout(cd->wait_q, cd->mode == CY_MODE_SYSINFO,
++			msecs_to_jiffies(CY_CORE_MODE_CHANGE_TIMEOUT));
++	if (IS_TMO(t)) {
++		dev_err(cd->dev, "%s: tmo waiting exit bl cd->mode=%d\n",
++			__func__, cd->mode);
++		mutex_lock(&cd->system_lock);
++		cd->int_status &= ~CY_INT_MODE_CHANGE;
++		mutex_unlock(&cd->system_lock);
++		return -ETIME;
++	}
++
++	return 0;
++}
++
++static int cyttsp4_reset_and_wait(struct cyttsp4 *cd)
++{
++	int rc;
++
++	/* reset hardware */
++	mutex_lock(&cd->system_lock);
++	dev_dbg(cd->dev, "%s: reset hw...\n", __func__);
++	rc = cyttsp4_hw_reset(cd);
++	cd->mode = CY_MODE_UNKNOWN;
++	mutex_unlock(&cd->system_lock);
++	if (rc < 0) {
++		dev_err(cd->dev, "%s:Fail hw reset r=%d\n", __func__, rc);
++		return rc;
++	}
++
++	return cyttsp4_wait_bl_heartbeat(cd);
++}
++
++/*
++ * returns err if refused or timeout; block until mode change complete
++ * bit is set (mode change interrupt)
++ */
++static int cyttsp4_set_mode(struct cyttsp4 *cd, int new_mode)
++{
++	u8 new_dev_mode;
++	u8 mode;
++	long t;
++	int rc;
++
++	switch (new_mode) {
++	case CY_MODE_OPERATIONAL:
++		new_dev_mode = CY_HST_OPERATE;
++		break;
++	case CY_MODE_SYSINFO:
++		new_dev_mode = CY_HST_SYSINFO;
++		break;
++	case CY_MODE_CAT:
++		new_dev_mode = CY_HST_CAT;
++		break;
++	default:
++		dev_err(cd->dev, "%s: invalid mode: %02X(%d)\n",
++			__func__, new_mode, new_mode);
++		return -EINVAL;
++	}
++
++	/* change mode */
++	dev_dbg(cd->dev, "%s: %s=%p new_dev_mode=%02X new_mode=%d\n",
++			__func__, "have exclusive", cd->exclusive_dev,
++			new_dev_mode, new_mode);
++
++	mutex_lock(&cd->system_lock);
++	rc = cyttsp4_adap_read(cd, CY_REG_BASE, sizeof(mode), &mode);
++	if (rc < 0) {
++		mutex_unlock(&cd->system_lock);
++		dev_err(cd->dev, "%s: Fail read mode r=%d\n",
++			__func__, rc);
++		goto exit;
++	}
++
++	/* Clear device mode bits and set to new mode */
++	mode &= ~CY_HST_MODE;
++	mode |= new_dev_mode | CY_HST_MODE_CHANGE;
++
++	cd->int_status |= CY_INT_MODE_CHANGE;
++	rc = cyttsp4_adap_write(cd, CY_REG_BASE, sizeof(mode), &mode);
++	mutex_unlock(&cd->system_lock);
++	if (rc < 0) {
++		dev_err(cd->dev, "%s: Fail write mode change r=%d\n",
++				__func__, rc);
++		goto exit;
++	}
++
++	/* wait for mode change done interrupt */
++	t = wait_event_timeout(cd->wait_q,
++			(cd->int_status & CY_INT_MODE_CHANGE) == 0,
++			msecs_to_jiffies(CY_CORE_MODE_CHANGE_TIMEOUT));
++	dev_dbg(cd->dev, "%s: back from wait t=%ld cd->mode=%d\n",
++			__func__, t, cd->mode);
++
++	if (IS_TMO(t)) {
++		dev_err(cd->dev, "%s: %s\n", __func__,
++				"tmo waiting mode change");
++		mutex_lock(&cd->system_lock);
++		cd->int_status &= ~CY_INT_MODE_CHANGE;
++		mutex_unlock(&cd->system_lock);
++		rc = -EINVAL;
++	}
++
++exit:
++	return rc;
++}
++
++static void cyttsp4_watchdog_work(struct work_struct *work)
++{
++	struct cyttsp4 *cd =
++		container_of(work, struct cyttsp4, watchdog_work);
++	u8 *mode;
++	int retval;
++
++	mutex_lock(&cd->system_lock);
++	retval = cyttsp4_load_status_regs(cd);
++	if (retval < 0) {
++		dev_err(cd->dev,
++			"%s: failed to access device in watchdog timer r=%d\n",
++			__func__, retval);
++		cyttsp4_queue_startup_(cd);
++		goto cyttsp4_timer_watchdog_exit_error;
++	}
++	mode = &cd->sysinfo.xy_mode[CY_REG_BASE];
++	if (IS_BOOTLOADER(mode[0], mode[1])) {
++		dev_err(cd->dev,
++			"%s: device found in bootloader mode when operational mode\n",
++			__func__);
++		cyttsp4_queue_startup_(cd);
++		goto cyttsp4_timer_watchdog_exit_error;
++	}
++
++	cyttsp4_start_wd_timer(cd);
++cyttsp4_timer_watchdog_exit_error:
++	mutex_unlock(&cd->system_lock);
++	return;
++}
++
++static int cyttsp4_core_sleep_(struct cyttsp4 *cd)
++{
++	enum cyttsp4_sleep_state ss = SS_SLEEP_ON;
++	enum cyttsp4_int_state int_status = CY_INT_IGNORE;
++	int rc = 0;
++	u8 mode[2];
++
++	/* Already in sleep mode? */
++	mutex_lock(&cd->system_lock);
++	if (cd->sleep_state == SS_SLEEP_ON) {
++		mutex_unlock(&cd->system_lock);
++		return 0;
++	}
++	cd->sleep_state = SS_SLEEPING;
++	mutex_unlock(&cd->system_lock);
++
++	cyttsp4_stop_wd_timer(cd);
++
++	/* Wait until currently running IRQ handler exits and disable IRQ */
++	disable_irq(cd->irq);
++
++	dev_vdbg(cd->dev, "%s: write DEEP SLEEP...\n", __func__);
++	mutex_lock(&cd->system_lock);
++	rc = cyttsp4_adap_read(cd, CY_REG_BASE, sizeof(mode), &mode);
++	if (rc) {
++		mutex_unlock(&cd->system_lock);
++		dev_err(cd->dev, "%s: Fail read adapter r=%d\n", __func__, rc);
++		goto error;
++	}
++
++	if (IS_BOOTLOADER(mode[0], mode[1])) {
++		mutex_unlock(&cd->system_lock);
++		dev_err(cd->dev, "%s: Device in BOOTLOADER mode.\n", __func__);
++		rc = -EINVAL;
++		goto error;
++	}
++
++	mode[0] |= CY_HST_SLEEP;
++	rc = cyttsp4_adap_write(cd, CY_REG_BASE, sizeof(mode[0]), &mode[0]);
++	mutex_unlock(&cd->system_lock);
++	if (rc) {
++		dev_err(cd->dev, "%s: Fail write adapter r=%d\n", __func__, rc);
++		goto error;
++	}
++	dev_vdbg(cd->dev, "%s: write DEEP SLEEP succeeded\n", __func__);
++
++	if (cd->cpdata->power) {
++		dev_dbg(cd->dev, "%s: Power down HW\n", __func__);
++		rc = cd->cpdata->power(cd->cpdata, 0, cd->dev, &cd->ignore_irq);
++	} else {
++		dev_dbg(cd->dev, "%s: No power function\n", __func__);
++		rc = 0;
++	}
++	if (rc < 0) {
++		dev_err(cd->dev, "%s: HW Power down fails r=%d\n",
++				__func__, rc);
++		goto error;
++	}
++
++	/* Give time to FW to sleep */
++	msleep(50);
++
++	goto exit;
++
++error:
++	ss = SS_SLEEP_OFF;
++	int_status = CY_INT_NONE;
++	cyttsp4_start_wd_timer(cd);
++
++exit:
++	mutex_lock(&cd->system_lock);
++	cd->sleep_state = ss;
++	cd->int_status |= int_status;
++	mutex_unlock(&cd->system_lock);
++	enable_irq(cd->irq);
++	return rc;
++}
++
++static int cyttsp4_startup_(struct cyttsp4 *cd)
++{
++	int retry = CY_CORE_STARTUP_RETRY_COUNT;
++	int rc;
++
++	cyttsp4_stop_wd_timer(cd);
++
++reset:
++	if (retry != CY_CORE_STARTUP_RETRY_COUNT)
++		dev_dbg(cd->dev, "%s: Retry %d\n", __func__,
++			CY_CORE_STARTUP_RETRY_COUNT - retry);
++
++	/* reset hardware and wait for heartbeat */
++	rc = cyttsp4_reset_and_wait(cd);
++	if (rc < 0) {
++		dev_err(cd->dev, "%s: Error on h/w reset r=%d\n", __func__, rc);
++		if (retry--)
++			goto reset;
++		goto exit;
++	}
++
++	/* exit bl into sysinfo mode */
++	dev_vdbg(cd->dev, "%s: write exit ldr...\n", __func__);
++	mutex_lock(&cd->system_lock);
++	cd->int_status &= ~CY_INT_IGNORE;
++	cd->int_status |= CY_INT_MODE_CHANGE;
++
++	rc = cyttsp4_adap_write(cd, CY_REG_BASE, sizeof(ldr_exit),
++			(u8 *)ldr_exit);
++	mutex_unlock(&cd->system_lock);
++	if (rc < 0) {
++		dev_err(cd->dev, "%s: Fail write r=%d\n", __func__, rc);
++		if (retry--)
++			goto reset;
++		goto exit;
++	}
++
++	rc = cyttsp4_wait_sysinfo_mode(cd);
++	if (rc < 0) {
++		u8 buf[sizeof(ldr_err_app)];
++		int rc1;
++
++		/* Check for invalid/corrupted touch application */
++		rc1 = cyttsp4_adap_read(cd, CY_REG_BASE, sizeof(ldr_err_app),
++				buf);
++		if (rc1) {
++			dev_err(cd->dev, "%s: Fail read r=%d\n", __func__, rc1);
++		} else if (!memcmp(buf, ldr_err_app, sizeof(ldr_err_app))) {
++			dev_err(cd->dev, "%s: Error launching touch application\n",
++				__func__);
++			mutex_lock(&cd->system_lock);
++			cd->invalid_touch_app = true;
++			mutex_unlock(&cd->system_lock);
++			goto exit_no_wd;
++		}
++
++		if (retry--)
++			goto reset;
++		goto exit;
++	}
++
++	mutex_lock(&cd->system_lock);
++	cd->invalid_touch_app = false;
++	mutex_unlock(&cd->system_lock);
++
++	/* read sysinfo data */
++	dev_vdbg(cd->dev, "%s: get sysinfo regs..\n", __func__);
++	rc = cyttsp4_get_sysinfo_regs(cd);
++	if (rc < 0) {
++		dev_err(cd->dev, "%s: failed to get sysinfo regs rc=%d\n",
++			__func__, rc);
++		if (retry--)
++			goto reset;
++		goto exit;
++	}
++
++	rc = cyttsp4_set_mode(cd, CY_MODE_OPERATIONAL);
++	if (rc < 0) {
++		dev_err(cd->dev, "%s: failed to set mode to operational rc=%d\n",
++			__func__, rc);
++		if (retry--)
++			goto reset;
++		goto exit;
++	}
++
++	cyttsp4_lift_all(&cd->md);
++
++	/* restore to sleep if was suspended */
++	mutex_lock(&cd->system_lock);
++	if (cd->sleep_state == SS_SLEEP_ON) {
++		cd->sleep_state = SS_SLEEP_OFF;
++		mutex_unlock(&cd->system_lock);
++		cyttsp4_core_sleep_(cd);
++		goto exit_no_wd;
++	}
++	mutex_unlock(&cd->system_lock);
++
++exit:
++	cyttsp4_start_wd_timer(cd);
++exit_no_wd:
++	return rc;
++}
++
++static int cyttsp4_startup(struct cyttsp4 *cd)
++{
++	int rc;
++
++	mutex_lock(&cd->system_lock);
++	cd->startup_state = STARTUP_RUNNING;
++	mutex_unlock(&cd->system_lock);
++
++	rc = cyttsp4_request_exclusive(cd, cd->dev,
++			CY_CORE_REQUEST_EXCLUSIVE_TIMEOUT);
++	if (rc < 0) {
++		dev_err(cd->dev, "%s: fail get exclusive ex=%p own=%p\n",
++				__func__, cd->exclusive_dev, cd->dev);
++		goto exit;
++	}
++
++	rc = cyttsp4_startup_(cd);
++
++	if (cyttsp4_release_exclusive(cd, cd->dev) < 0)
++		/* Don't return fail code, mode is already changed. */
++		dev_err(cd->dev, "%s: fail to release exclusive\n", __func__);
++	else
++		dev_vdbg(cd->dev, "%s: pass release exclusive\n", __func__);
++
++exit:
++	mutex_lock(&cd->system_lock);
++	cd->startup_state = STARTUP_NONE;
++	mutex_unlock(&cd->system_lock);
++
++	/* Wake the waiters for end of startup */
++	wake_up(&cd->wait_q);
++
++	return rc;
++}
++
++static void cyttsp4_startup_work_function(struct work_struct *work)
++{
++	struct cyttsp4 *cd =  container_of(work, struct cyttsp4, startup_work);
++	int rc;
++
++	rc = cyttsp4_startup(cd);
++	if (rc < 0)
++		dev_err(cd->dev, "%s: Fail queued startup r=%d\n",
++			__func__, rc);
++}
++
++static void cyttsp4_free_si_ptrs(struct cyttsp4 *cd)
++{
++	struct cyttsp4_sysinfo *si = &cd->sysinfo;
++
++	if (!si)
++		return;
++
++	kfree(si->si_ptrs.cydata);
++	kfree(si->si_ptrs.test);
++	kfree(si->si_ptrs.pcfg);
++	kfree(si->si_ptrs.opcfg);
++	kfree(si->si_ptrs.ddata);
++	kfree(si->si_ptrs.mdata);
++	kfree(si->btn);
++	kfree(si->xy_mode);
++	kfree(si->xy_data);
++	kfree(si->btn_rec_data);
++}
++
++static int cyttsp4_core_sleep(struct cyttsp4 *cd)
++{
++	int rc;
++
++	rc = cyttsp4_request_exclusive(cd, cd->dev,
++			CY_CORE_SLEEP_REQUEST_EXCLUSIVE_TIMEOUT);
++	if (rc < 0) {
++		dev_err(cd->dev, "%s: fail get exclusive ex=%p own=%p\n",
++				__func__, cd->exclusive_dev, cd->dev);
++		return 0;
++	}
++
++	rc = cyttsp4_core_sleep_(cd);
++
++	if (cyttsp4_release_exclusive(cd, cd->dev) < 0)
++		dev_err(cd->dev, "%s: fail to release exclusive\n", __func__);
++	else
++		dev_vdbg(cd->dev, "%s: pass release exclusive\n", __func__);
++
++	return rc;
++}
++
++static int cyttsp4_core_wake_(struct cyttsp4 *cd)
++{
++	struct device *dev = cd->dev;
++	int rc;
++	u8 mode;
++	int t;
++
++	/* Already woken? */
++	mutex_lock(&cd->system_lock);
++	if (cd->sleep_state == SS_SLEEP_OFF) {
++		mutex_unlock(&cd->system_lock);
++		return 0;
++	}
++	cd->int_status &= ~CY_INT_IGNORE;
++	cd->int_status |= CY_INT_AWAKE;
++	cd->sleep_state = SS_WAKING;
++
++	if (cd->cpdata->power) {
++		dev_dbg(dev, "%s: Power up HW\n", __func__);
++		rc = cd->cpdata->power(cd->cpdata, 1, dev, &cd->ignore_irq);
++	} else {
++		dev_dbg(dev, "%s: No power function\n", __func__);
++		rc = -ENOSYS;
++	}
++	if (rc < 0) {
++		dev_err(dev, "%s: HW Power up fails r=%d\n",
++				__func__, rc);
++
++		/* Initiate a read transaction to wake up */
++		cyttsp4_adap_read(cd, CY_REG_BASE, sizeof(mode), &mode);
++	} else
++		dev_vdbg(cd->dev, "%s: HW power up succeeds\n",
++			__func__);
++	mutex_unlock(&cd->system_lock);
++
++	t = wait_event_timeout(cd->wait_q,
++			(cd->int_status & CY_INT_AWAKE) == 0,
++			msecs_to_jiffies(CY_CORE_WAKEUP_TIMEOUT));
++	if (IS_TMO(t)) {
++		dev_err(dev, "%s: TMO waiting for wakeup\n", __func__);
++		mutex_lock(&cd->system_lock);
++		cd->int_status &= ~CY_INT_AWAKE;
++		/* Try starting up */
++		cyttsp4_queue_startup_(cd);
++		mutex_unlock(&cd->system_lock);
++	}
++
++	mutex_lock(&cd->system_lock);
++	cd->sleep_state = SS_SLEEP_OFF;
++	mutex_unlock(&cd->system_lock);
++
++	cyttsp4_start_wd_timer(cd);
++
++	return 0;
++}
++
++static int cyttsp4_core_wake(struct cyttsp4 *cd)
++{
++	int rc;
++
++	rc = cyttsp4_request_exclusive(cd, cd->dev,
++			CY_CORE_REQUEST_EXCLUSIVE_TIMEOUT);
++	if (rc < 0) {
++		dev_err(cd->dev, "%s: fail get exclusive ex=%p own=%p\n",
++				__func__, cd->exclusive_dev, cd->dev);
++		return 0;
++	}
++
++	rc = cyttsp4_core_wake_(cd);
++
++	if (cyttsp4_release_exclusive(cd, cd->dev) < 0)
++		dev_err(cd->dev, "%s: fail to release exclusive\n", __func__);
++	else
++		dev_vdbg(cd->dev, "%s: pass release exclusive\n", __func__);
++
++	return rc;
++}
++
++static int cyttsp4_core_suspend(struct device *dev)
++{
++	struct cyttsp4 *cd = dev_get_drvdata(dev);
++	struct cyttsp4_mt_data *md = &cd->md;
++	int rc;
++
++	md->is_suspended = true;
++
++	rc = cyttsp4_core_sleep(cd);
++	if (rc < 0) {
++		dev_err(dev, "%s: Error on sleep\n", __func__);
++		return -EAGAIN;
++	}
++	return 0;
++}
++
++static int cyttsp4_core_resume(struct device *dev)
++{
++	struct cyttsp4 *cd = dev_get_drvdata(dev);
++	struct cyttsp4_mt_data *md = &cd->md;
++	int rc;
++
++	md->is_suspended = false;
++
++	rc = cyttsp4_core_wake(cd);
++	if (rc < 0) {
++		dev_err(dev, "%s: Error on wake\n", __func__);
++		return -EAGAIN;
++	}
++
++	return 0;
++}
++
++EXPORT_GPL_RUNTIME_DEV_PM_OPS(cyttsp4_pm_ops,
++			      cyttsp4_core_suspend, cyttsp4_core_resume, NULL);
++
++static int cyttsp4_mt_open(struct input_dev *input)
++{
++	pm_runtime_get(input->dev.parent);
++	return 0;
++}
++
++static void cyttsp4_mt_close(struct input_dev *input)
++{
++	struct cyttsp4_mt_data *md = input_get_drvdata(input);
++	mutex_lock(&md->report_lock);
++	if (!md->is_suspended)
++		pm_runtime_put(input->dev.parent);
++	mutex_unlock(&md->report_lock);
++}
++
++
++static int cyttsp4_setup_input_device(struct cyttsp4 *cd)
++{
++	struct device *dev = cd->dev;
++	struct cyttsp4_mt_data *md = &cd->md;
++	int signal = CY_IGNORE_VALUE;
++	int max_x, max_y, max_p, min, max;
++	int max_x_tmp, max_y_tmp;
++	int i;
++	int rc;
++
++	dev_vdbg(dev, "%s: Initialize event signals\n", __func__);
++	__set_bit(EV_ABS, md->input->evbit);
++	__set_bit(EV_REL, md->input->evbit);
++	__set_bit(EV_KEY, md->input->evbit);
++
++	max_x_tmp = md->si->si_ofs.max_x;
++	max_y_tmp = md->si->si_ofs.max_y;
++
++	/* get maximum values from the sysinfo data */
++	if (md->pdata->flags & CY_FLAG_FLIP) {
++		max_x = max_y_tmp - 1;
++		max_y = max_x_tmp - 1;
++	} else {
++		max_x = max_x_tmp - 1;
++		max_y = max_y_tmp - 1;
++	}
++	max_p = md->si->si_ofs.max_p;
++
++	/* set event signal capabilities */
++	for (i = 0; i < (md->pdata->frmwrk->size / CY_NUM_ABS_SET); i++) {
++		signal = md->pdata->frmwrk->abs
++			[(i * CY_NUM_ABS_SET) + CY_SIGNAL_OST];
++		if (signal != CY_IGNORE_VALUE) {
++			__set_bit(signal, md->input->absbit);
++			min = md->pdata->frmwrk->abs
++				[(i * CY_NUM_ABS_SET) + CY_MIN_OST];
++			max = md->pdata->frmwrk->abs
++				[(i * CY_NUM_ABS_SET) + CY_MAX_OST];
++			if (i == CY_ABS_ID_OST) {
++				/* shift track ids down to start at 0 */
++				max = max - min;
++				min = min - min;
++			} else if (i == CY_ABS_X_OST)
++				max = max_x;
++			else if (i == CY_ABS_Y_OST)
++				max = max_y;
++			else if (i == CY_ABS_P_OST)
++				max = max_p;
++			input_set_abs_params(md->input, signal, min, max,
++				md->pdata->frmwrk->abs
++				[(i * CY_NUM_ABS_SET) + CY_FUZZ_OST],
++				md->pdata->frmwrk->abs
++				[(i * CY_NUM_ABS_SET) + CY_FLAT_OST]);
++			dev_dbg(dev, "%s: register signal=%02X min=%d max=%d\n",
++				__func__, signal, min, max);
++			if ((i == CY_ABS_ID_OST) &&
++				(md->si->si_ofs.tch_rec_size <
++				CY_TMA4XX_TCH_REC_SIZE))
++				break;
++		}
++	}
++
++	input_mt_init_slots(md->input, md->si->si_ofs.tch_abs[CY_TCH_T].max,
++			INPUT_MT_DIRECT);
++	rc = input_register_device(md->input);
++	if (rc < 0)
++		dev_err(dev, "%s: Error, failed register input device r=%d\n",
++			__func__, rc);
++	return rc;
++}
++
++static int cyttsp4_mt_probe(struct cyttsp4 *cd)
++{
++	struct device *dev = cd->dev;
++	struct cyttsp4_mt_data *md = &cd->md;
++	struct cyttsp4_mt_platform_data *pdata = cd->pdata->mt_pdata;
++	int rc = 0;
++
++	mutex_init(&md->report_lock);
++	md->pdata = pdata;
++	/* Create the input device and register it. */
++	dev_vdbg(dev, "%s: Create the input device and register it\n",
++		__func__);
++	md->input = input_allocate_device();
++	if (md->input == NULL) {
++		dev_err(dev, "%s: Error, failed to allocate input device\n",
++			__func__);
++		rc = -ENOSYS;
++		goto error_alloc_failed;
++	}
++
++	md->input->name = pdata->inp_dev_name;
++	scnprintf(md->phys, sizeof(md->phys)-1, "%s", dev_name(dev));
++	md->input->phys = md->phys;
++	md->input->id.bustype = cd->bus_ops->bustype;
++	md->input->dev.parent = dev;
++	md->input->open = cyttsp4_mt_open;
++	md->input->close = cyttsp4_mt_close;
++	input_set_drvdata(md->input, md);
++
++	/* get sysinfo */
++	md->si = &cd->sysinfo;
++
++	rc = cyttsp4_setup_input_device(cd);
++	if (rc)
++		goto error_init_input;
++
++	return 0;
++
++error_init_input:
++	input_free_device(md->input);
++error_alloc_failed:
++	dev_err(dev, "%s failed.\n", __func__);
++	return rc;
++}
++
++struct cyttsp4 *cyttsp4_probe(const struct cyttsp4_bus_ops *ops,
++		struct device *dev, u16 irq, size_t xfer_buf_size)
++{
++	struct cyttsp4 *cd;
++	struct cyttsp4_platform_data *pdata = dev_get_platdata(dev);
++	unsigned long irq_flags;
++	int rc = 0;
++
++	if (!pdata || !pdata->core_pdata || !pdata->mt_pdata) {
++		dev_err(dev, "%s: Missing platform data\n", __func__);
++		rc = -ENODEV;
++		goto error_no_pdata;
++	}
++
++	cd = kzalloc(sizeof(*cd), GFP_KERNEL);
++	if (!cd) {
++		dev_err(dev, "%s: Error, kzalloc\n", __func__);
++		rc = -ENOMEM;
++		goto error_alloc_data;
++	}
++
++	cd->xfer_buf = kzalloc(xfer_buf_size, GFP_KERNEL);
++	if (!cd->xfer_buf) {
++		dev_err(dev, "%s: Error, kzalloc\n", __func__);
++		rc = -ENOMEM;
++		goto error_free_cd;
++	}
++
++	/* Initialize device info */
++	cd->dev = dev;
++	cd->pdata = pdata;
++	cd->cpdata = pdata->core_pdata;
++	cd->bus_ops = ops;
++
++	/* Initialize mutexes and spinlocks */
++	mutex_init(&cd->system_lock);
++	mutex_init(&cd->adap_lock);
++
++	/* Initialize wait queue */
++	init_waitqueue_head(&cd->wait_q);
++
++	/* Initialize works */
++	INIT_WORK(&cd->startup_work, cyttsp4_startup_work_function);
++	INIT_WORK(&cd->watchdog_work, cyttsp4_watchdog_work);
++
++	/* Initialize IRQ */
++	cd->irq = gpio_to_irq(cd->cpdata->irq_gpio);
++	if (cd->irq < 0) {
++		rc = -EINVAL;
++		goto error_free_xfer;
++	}
++
++	dev_set_drvdata(dev, cd);
++
++	/* Call platform init function */
++	if (cd->cpdata->init) {
++		dev_dbg(cd->dev, "%s: Init HW\n", __func__);
++		rc = cd->cpdata->init(cd->cpdata, 1, cd->dev);
++	} else {
++		dev_dbg(cd->dev, "%s: No HW INIT function\n", __func__);
++		rc = 0;
++	}
++	if (rc < 0)
++		dev_err(cd->dev, "%s: HW Init fail r=%d\n", __func__, rc);
++
++	dev_dbg(dev, "%s: initialize threaded irq=%d\n", __func__, cd->irq);
++	if (cd->cpdata->level_irq_udelay > 0)
++		/* use level triggered interrupts */
++		irq_flags = IRQF_TRIGGER_LOW | IRQF_ONESHOT;
++	else
++		/* use edge triggered interrupts */
++		irq_flags = IRQF_TRIGGER_FALLING | IRQF_ONESHOT;
++
++	rc = request_threaded_irq(cd->irq, NULL, cyttsp4_irq, irq_flags,
++		dev_name(dev), cd);
++	if (rc < 0) {
++		dev_err(dev, "%s: Error, could not request irq\n", __func__);
++		goto error_request_irq;
++	}
++
++	/* Setup watchdog timer */
++	timer_setup(&cd->watchdog_timer, cyttsp4_watchdog_timer, 0);
++
++	/*
++	 * call startup directly to ensure that the device
++	 * is tested before leaving the probe
++	 */
++	rc = cyttsp4_startup(cd);
++
++	/* Do not fail probe if startup fails but the device is detected */
++	if (rc < 0 && cd->mode == CY_MODE_UNKNOWN) {
++		dev_err(cd->dev, "%s: Fail initial startup r=%d\n",
++			__func__, rc);
++		goto error_startup;
++	}
++
++	rc = cyttsp4_mt_probe(cd);
++	if (rc < 0) {
++		dev_err(dev, "%s: Error, fail mt probe\n", __func__);
++		goto error_startup;
++	}
++
++	pm_runtime_enable(dev);
++
++	return cd;
++
++error_startup:
++	cancel_work_sync(&cd->startup_work);
++	cyttsp4_stop_wd_timer(cd);
++	pm_runtime_disable(dev);
++	cyttsp4_free_si_ptrs(cd);
++	free_irq(cd->irq, cd);
++error_request_irq:
++	if (cd->cpdata->init)
++		cd->cpdata->init(cd->cpdata, 0, dev);
++error_free_xfer:
++	kfree(cd->xfer_buf);
++error_free_cd:
++	kfree(cd);
++error_alloc_data:
++error_no_pdata:
++	dev_err(dev, "%s failed.\n", __func__);
++	return ERR_PTR(rc);
++}
++EXPORT_SYMBOL_GPL(cyttsp4_probe);
++
++static void cyttsp4_mt_release(struct cyttsp4_mt_data *md)
++{
++	input_unregister_device(md->input);
++	input_set_drvdata(md->input, NULL);
++}
++
++int cyttsp4_remove(struct cyttsp4 *cd)
++{
++	struct device *dev = cd->dev;
++
++	cyttsp4_mt_release(&cd->md);
++
++	/*
++	 * Suspend the device before freeing the startup_work and stopping
++	 * the watchdog since sleep function restarts watchdog on failure
++	 */
++	pm_runtime_suspend(dev);
++	pm_runtime_disable(dev);
++
++	cancel_work_sync(&cd->startup_work);
++
++	cyttsp4_stop_wd_timer(cd);
++
++	free_irq(cd->irq, cd);
++	if (cd->cpdata->init)
++		cd->cpdata->init(cd->cpdata, 0, dev);
++	cyttsp4_free_si_ptrs(cd);
++	kfree(cd);
++	return 0;
++}
++EXPORT_SYMBOL_GPL(cyttsp4_remove);
++
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("Cypress TrueTouch(R) Standard touchscreen core driver");
++MODULE_AUTHOR("Cypress");
+diff --git a/drivers/input/touchscreen/cyttsp4_core.h b/drivers/input/touchscreen/cyttsp4_core.h
+new file mode 100644
+index 000000000000..6262f6e45075
+--- /dev/null
++++ b/drivers/input/touchscreen/cyttsp4_core.h
+@@ -0,0 +1,448 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++/*
++ * cyttsp4_core.h
++ * Cypress TrueTouch(TM) Standard Product V4 Core driver module.
++ * For use with Cypress Txx4xx parts.
++ * Supported parts include:
++ * TMA4XX
++ * TMA1036
++ *
++ * Copyright (C) 2012 Cypress Semiconductor
++ *
++ * Contact Cypress Semiconductor at www.cypress.com <ttdrivers@cypress.com>
++ */
++
++#ifndef _LINUX_CYTTSP4_CORE_H
++#define _LINUX_CYTTSP4_CORE_H
++
++#include <linux/device.h>
++#include <linux/err.h>
++#include <linux/input.h>
++#include <linux/kernel.h>
++#include <linux/limits.h>
++#include <linux/module.h>
++#include <linux/stringify.h>
++#include <linux/types.h>
++#include <linux/platform_data/cyttsp4.h>
++
++#define CY_REG_BASE			0x00
++
++#define CY_POST_CODEL_WDG_RST		0x01
++#define CY_POST_CODEL_CFG_DATA_CRC_FAIL	0x02
++#define CY_POST_CODEL_PANEL_TEST_FAIL	0x04
++
++#define CY_NUM_BTN_PER_REG		4
++
++/* touch record system information offset masks and shifts */
++#define CY_BYTE_OFS_MASK		0x1F
++#define CY_BOFS_MASK			0xE0
++#define CY_BOFS_SHIFT			5
++
++#define CY_TMA1036_TCH_REC_SIZE		6
++#define CY_TMA4XX_TCH_REC_SIZE		9
++#define CY_TMA1036_MAX_TCH		0x0E
++#define CY_TMA4XX_MAX_TCH		0x1E
++
++#define CY_NORMAL_ORIGIN		0	/* upper, left corner */
++#define CY_INVERT_ORIGIN		1	/* lower, right corner */
++
++/* helpers */
++#define GET_NUM_TOUCHES(x)		((x) & 0x1F)
++#define IS_LARGE_AREA(x)		((x) & 0x20)
++#define IS_BAD_PKT(x)			((x) & 0x20)
++#define IS_BOOTLOADER(hst_mode, reset_detect)	\
++		((hst_mode) & 0x01 || (reset_detect) != 0)
++#define IS_TMO(t)			((t) == 0)
++
++
++enum cyttsp_cmd_bits {
++	CY_CMD_COMPLETE = (1 << 6),
++};
++
++/* Timeout in ms. */
++#define CY_WATCHDOG_TIMEOUT		1000
++
++#define CY_MAX_PRINT_SIZE		512
++#ifdef VERBOSE_DEBUG
++#define CY_MAX_PRBUF_SIZE		PIPE_BUF
++#define CY_PR_TRUNCATED			" truncated..."
++#endif
++
++enum cyttsp4_ic_grpnum {
++	CY_IC_GRPNUM_RESERVED,
++	CY_IC_GRPNUM_CMD_REGS,
++	CY_IC_GRPNUM_TCH_REP,
++	CY_IC_GRPNUM_DATA_REC,
++	CY_IC_GRPNUM_TEST_REC,
++	CY_IC_GRPNUM_PCFG_REC,
++	CY_IC_GRPNUM_TCH_PARM_VAL,
++	CY_IC_GRPNUM_TCH_PARM_SIZE,
++	CY_IC_GRPNUM_RESERVED1,
++	CY_IC_GRPNUM_RESERVED2,
++	CY_IC_GRPNUM_OPCFG_REC,
++	CY_IC_GRPNUM_DDATA_REC,
++	CY_IC_GRPNUM_MDATA_REC,
++	CY_IC_GRPNUM_TEST_REGS,
++	CY_IC_GRPNUM_BTN_KEYS,
++	CY_IC_GRPNUM_TTHE_REGS,
++	CY_IC_GRPNUM_NUM
++};
++
++enum cyttsp4_int_state {
++	CY_INT_NONE,
++	CY_INT_IGNORE      = (1 << 0),
++	CY_INT_MODE_CHANGE = (1 << 1),
++	CY_INT_EXEC_CMD    = (1 << 2),
++	CY_INT_AWAKE       = (1 << 3),
++};
++
++enum cyttsp4_mode {
++	CY_MODE_UNKNOWN,
++	CY_MODE_BOOTLOADER   = (1 << 1),
++	CY_MODE_OPERATIONAL  = (1 << 2),
++	CY_MODE_SYSINFO      = (1 << 3),
++	CY_MODE_CAT          = (1 << 4),
++	CY_MODE_STARTUP      = (1 << 5),
++	CY_MODE_LOADER       = (1 << 6),
++	CY_MODE_CHANGE_MODE  = (1 << 7),
++	CY_MODE_CHANGED      = (1 << 8),
++	CY_MODE_CMD_COMPLETE = (1 << 9),
++};
++
++enum cyttsp4_sleep_state {
++	SS_SLEEP_OFF,
++	SS_SLEEP_ON,
++	SS_SLEEPING,
++	SS_WAKING,
++};
++
++enum cyttsp4_startup_state {
++	STARTUP_NONE,
++	STARTUP_QUEUED,
++	STARTUP_RUNNING,
++};
++
++#define CY_NUM_REVCTRL			8
++struct cyttsp4_cydata {
++	u8 ttpidh;
++	u8 ttpidl;
++	u8 fw_ver_major;
++	u8 fw_ver_minor;
++	u8 revctrl[CY_NUM_REVCTRL];
++	u8 blver_major;
++	u8 blver_minor;
++	u8 jtag_si_id3;
++	u8 jtag_si_id2;
++	u8 jtag_si_id1;
++	u8 jtag_si_id0;
++	u8 mfgid_sz;
++	u8 cyito_idh;
++	u8 cyito_idl;
++	u8 cyito_verh;
++	u8 cyito_verl;
++	u8 ttsp_ver_major;
++	u8 ttsp_ver_minor;
++	u8 device_info;
++	u8 mfg_id[];
++} __packed;
++
++struct cyttsp4_test {
++	u8 post_codeh;
++	u8 post_codel;
++} __packed;
++
++struct cyttsp4_pcfg {
++	u8 electrodes_x;
++	u8 electrodes_y;
++	u8 len_xh;
++	u8 len_xl;
++	u8 len_yh;
++	u8 len_yl;
++	u8 res_xh;
++	u8 res_xl;
++	u8 res_yh;
++	u8 res_yl;
++	u8 max_zh;
++	u8 max_zl;
++	u8 panel_info0;
++} __packed;
++
++struct cyttsp4_tch_rec_params {
++	u8 loc;
++	u8 size;
++} __packed;
++
++#define CY_NUM_TCH_FIELDS		7
++#define CY_NUM_EXT_TCH_FIELDS		3
++struct cyttsp4_opcfg {
++	u8 cmd_ofs;
++	u8 rep_ofs;
++	u8 rep_szh;
++	u8 rep_szl;
++	u8 num_btns;
++	u8 tt_stat_ofs;
++	u8 obj_cfg0;
++	u8 max_tchs;
++	u8 tch_rec_size;
++	struct cyttsp4_tch_rec_params tch_rec_old[CY_NUM_TCH_FIELDS];
++	u8 btn_rec_size;	/* btn record size (in bytes) */
++	u8 btn_diff_ofs;	/* btn data loc, diff counts  */
++	u8 btn_diff_size;	/* btn size of diff counts (in bits) */
++	struct cyttsp4_tch_rec_params tch_rec_new[CY_NUM_EXT_TCH_FIELDS];
++} __packed;
++
++struct cyttsp4_sysinfo_ptr {
++	struct cyttsp4_cydata *cydata;
++	struct cyttsp4_test *test;
++	struct cyttsp4_pcfg *pcfg;
++	struct cyttsp4_opcfg *opcfg;
++	struct cyttsp4_ddata *ddata;
++	struct cyttsp4_mdata *mdata;
++} __packed;
++
++struct cyttsp4_sysinfo_data {
++	u8 hst_mode;
++	u8 reserved;
++	u8 map_szh;
++	u8 map_szl;
++	u8 cydata_ofsh;
++	u8 cydata_ofsl;
++	u8 test_ofsh;
++	u8 test_ofsl;
++	u8 pcfg_ofsh;
++	u8 pcfg_ofsl;
++	u8 opcfg_ofsh;
++	u8 opcfg_ofsl;
++	u8 ddata_ofsh;
++	u8 ddata_ofsl;
++	u8 mdata_ofsh;
++	u8 mdata_ofsl;
++} __packed;
++
++enum cyttsp4_tch_abs {	/* for ordering within the extracted touch data array */
++	CY_TCH_X,	/* X */
++	CY_TCH_Y,	/* Y */
++	CY_TCH_P,	/* P (Z) */
++	CY_TCH_T,	/* TOUCH ID */
++	CY_TCH_E,	/* EVENT ID */
++	CY_TCH_O,	/* OBJECT ID */
++	CY_TCH_W,	/* SIZE */
++	CY_TCH_MAJ,	/* TOUCH_MAJOR */
++	CY_TCH_MIN,	/* TOUCH_MINOR */
++	CY_TCH_OR,	/* ORIENTATION */
++	CY_TCH_NUM_ABS
++};
++
++struct cyttsp4_touch {
++	int abs[CY_TCH_NUM_ABS];
++};
++
++struct cyttsp4_tch_abs_params {
++	size_t ofs;	/* abs byte offset */
++	size_t size;	/* size in bits */
++	size_t max;	/* max value */
++	size_t bofs;	/* bit offset */
++};
++
++struct cyttsp4_sysinfo_ofs {
++	size_t chip_type;
++	size_t cmd_ofs;
++	size_t rep_ofs;
++	size_t rep_sz;
++	size_t num_btns;
++	size_t num_btn_regs;	/* ceil(num_btns/4) */
++	size_t tt_stat_ofs;
++	size_t tch_rec_size;
++	size_t obj_cfg0;
++	size_t max_tchs;
++	size_t mode_size;
++	size_t data_size;
++	size_t map_sz;
++	size_t max_x;
++	size_t x_origin;	/* left or right corner */
++	size_t max_y;
++	size_t y_origin;	/* upper or lower corner */
++	size_t max_p;
++	size_t cydata_ofs;
++	size_t test_ofs;
++	size_t pcfg_ofs;
++	size_t opcfg_ofs;
++	size_t ddata_ofs;
++	size_t mdata_ofs;
++	size_t cydata_size;
++	size_t test_size;
++	size_t pcfg_size;
++	size_t opcfg_size;
++	size_t ddata_size;
++	size_t mdata_size;
++	size_t btn_keys_size;
++	struct cyttsp4_tch_abs_params tch_abs[CY_TCH_NUM_ABS];
++	size_t btn_rec_size; /* btn record size (in bytes) */
++	size_t btn_diff_ofs;/* btn data loc ,diff counts, (Op-Mode byte ofs) */
++	size_t btn_diff_size;/* btn size of diff counts (in bits) */
++};
++
++enum cyttsp4_btn_state {
++	CY_BTN_RELEASED,
++	CY_BTN_PRESSED,
++	CY_BTN_NUM_STATE
++};
++
++struct cyttsp4_btn {
++	bool enabled;
++	int state;	/* CY_BTN_PRESSED, CY_BTN_RELEASED */
++	int key_code;
++};
++
++struct cyttsp4_sysinfo {
++	bool ready;
++	struct cyttsp4_sysinfo_data si_data;
++	struct cyttsp4_sysinfo_ptr si_ptrs;
++	struct cyttsp4_sysinfo_ofs si_ofs;
++	struct cyttsp4_btn *btn;	/* button states */
++	u8 *btn_rec_data;		/* button diff count data */
++	u8 *xy_mode;			/* operational mode and status regs */
++	u8 *xy_data;			/* operational touch regs */
++};
++
++struct cyttsp4_mt_data {
++	struct cyttsp4_mt_platform_data *pdata;
++	struct cyttsp4_sysinfo *si;
++	struct input_dev *input;
++	struct mutex report_lock;
++	bool is_suspended;
++	char phys[NAME_MAX];
++	int num_prv_tch;
++};
++
++struct cyttsp4 {
++	struct device *dev;
++	struct mutex system_lock;
++	struct mutex adap_lock;
++	enum cyttsp4_mode mode;
++	enum cyttsp4_sleep_state sleep_state;
++	enum cyttsp4_startup_state startup_state;
++	int int_status;
++	wait_queue_head_t wait_q;
++	int irq;
++	struct work_struct startup_work;
++	struct work_struct watchdog_work;
++	struct timer_list watchdog_timer;
++	struct cyttsp4_sysinfo sysinfo;
++	void *exclusive_dev;
++	int exclusive_waits;
++	atomic_t ignore_irq;
++	bool invalid_touch_app;
++	struct cyttsp4_mt_data md;
++	struct cyttsp4_platform_data *pdata;
++	struct cyttsp4_core_platform_data *cpdata;
++	const struct cyttsp4_bus_ops *bus_ops;
++	u8 *xfer_buf;
++#ifdef VERBOSE_DEBUG
++	u8 pr_buf[CY_MAX_PRBUF_SIZE];
++#endif
++};
++
++struct cyttsp4_bus_ops {
++	u16 bustype;
++	int (*write)(struct device *dev, u8 *xfer_buf, u16 addr, u8 length,
++			const void *values);
++	int (*read)(struct device *dev, u8 *xfer_buf, u16 addr, u8 length,
++			void *values);
++};
++
++enum cyttsp4_hst_mode_bits {
++	CY_HST_TOGGLE      = (1 << 7),
++	CY_HST_MODE_CHANGE = (1 << 3),
++	CY_HST_MODE        = (7 << 4),
++	CY_HST_OPERATE     = (0 << 4),
++	CY_HST_SYSINFO     = (1 << 4),
++	CY_HST_CAT         = (2 << 4),
++	CY_HST_LOWPOW      = (1 << 2),
++	CY_HST_SLEEP       = (1 << 1),
++	CY_HST_RESET       = (1 << 0),
++};
++
++/* abs settings */
++#define CY_IGNORE_VALUE			0xFFFF
++
++/* abs signal capabilities offsets in the frameworks array */
++enum cyttsp4_sig_caps {
++	CY_SIGNAL_OST,
++	CY_MIN_OST,
++	CY_MAX_OST,
++	CY_FUZZ_OST,
++	CY_FLAT_OST,
++	CY_NUM_ABS_SET	/* number of signal capability fields */
++};
++
++/* abs axis signal offsets in the framworks array  */
++enum cyttsp4_sig_ost {
++	CY_ABS_X_OST,
++	CY_ABS_Y_OST,
++	CY_ABS_P_OST,
++	CY_ABS_W_OST,
++	CY_ABS_ID_OST,
++	CY_ABS_MAJ_OST,
++	CY_ABS_MIN_OST,
++	CY_ABS_OR_OST,
++	CY_NUM_ABS_OST	/* number of abs signals */
++};
++
++enum cyttsp4_flags {
++	CY_FLAG_NONE = 0x00,
++	CY_FLAG_HOVER = 0x04,
++	CY_FLAG_FLIP = 0x08,
++	CY_FLAG_INV_X = 0x10,
++	CY_FLAG_INV_Y = 0x20,
++	CY_FLAG_VKEYS = 0x40,
++};
++
++enum cyttsp4_object_id {
++	CY_OBJ_STANDARD_FINGER,
++	CY_OBJ_LARGE_OBJECT,
++	CY_OBJ_STYLUS,
++	CY_OBJ_HOVER,
++};
++
++enum cyttsp4_event_id {
++	CY_EV_NO_EVENT,
++	CY_EV_TOUCHDOWN,
++	CY_EV_MOVE,		/* significant displacement (> act dist) */
++	CY_EV_LIFTOFF,		/* record reports last position */
++};
++
++/* x-axis resolution of panel in pixels */
++#define CY_PCFG_RESOLUTION_X_MASK	0x7F
++
++/* y-axis resolution of panel in pixels */
++#define CY_PCFG_RESOLUTION_Y_MASK	0x7F
++
++/* x-axis, 0:origin is on left side of panel, 1: right */
++#define CY_PCFG_ORIGIN_X_MASK		0x80
++
++/* y-axis, 0:origin is on top side of panel, 1: bottom */
++#define CY_PCFG_ORIGIN_Y_MASK		0x80
++
++static inline int cyttsp4_adap_read(struct cyttsp4 *ts, u16 addr, int size,
++		void *buf)
++{
++	return ts->bus_ops->read(ts->dev, ts->xfer_buf, addr, size, buf);
++}
++
++static inline int cyttsp4_adap_write(struct cyttsp4 *ts, u16 addr, int size,
++		const void *buf)
++{
++	return ts->bus_ops->write(ts->dev, ts->xfer_buf, addr, size, buf);
++}
++
++extern struct cyttsp4 *cyttsp4_probe(const struct cyttsp4_bus_ops *ops,
++		struct device *dev, u16 irq, size_t xfer_buf_size);
++extern int cyttsp4_remove(struct cyttsp4 *ts);
++int cyttsp_i2c_write_block_data(struct device *dev, u8 *xfer_buf, u16 addr,
++		u8 length, const void *values);
++int cyttsp_i2c_read_block_data(struct device *dev, u8 *xfer_buf, u16 addr,
++		u8 length, void *values);
++extern const struct dev_pm_ops cyttsp4_pm_ops;
++
++#endif /* _LINUX_CYTTSP4_CORE_H */
+diff --git a/drivers/input/touchscreen/cyttsp4_i2c.c b/drivers/input/touchscreen/cyttsp4_i2c.c
+new file mode 100644
+index 000000000000..da32c151def5
+--- /dev/null
++++ b/drivers/input/touchscreen/cyttsp4_i2c.c
+@@ -0,0 +1,72 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * cyttsp_i2c.c
++ * Cypress TrueTouch(TM) Standard Product (TTSP) I2C touchscreen driver.
++ * For use with Cypress  Txx4xx parts.
++ * Supported parts include:
++ * TMA4XX
++ * TMA1036
++ *
++ * Copyright (C) 2009, 2010, 2011 Cypress Semiconductor, Inc.
++ * Copyright (C) 2012 Javier Martinez Canillas <javier@dowhile0.org>
++ * Copyright (C) 2013 Cypress Semiconductor
++ *
++ * Contact Cypress Semiconductor at www.cypress.com <ttdrivers@cypress.com>
++ */
++
++#include "cyttsp4_core.h"
++
++#include <linux/i2c.h>
++#include <linux/input.h>
++
++#define CYTTSP4_I2C_DATA_SIZE	(3 * 256)
++
++static const struct cyttsp4_bus_ops cyttsp4_i2c_bus_ops = {
++	.bustype	= BUS_I2C,
++	.write		= cyttsp_i2c_write_block_data,
++	.read           = cyttsp_i2c_read_block_data,
++};
++
++static int cyttsp4_i2c_probe(struct i2c_client *client)
++{
++	struct cyttsp4 *ts;
++
++	if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
++		dev_err(&client->dev, "I2C functionality not Supported\n");
++		return -EIO;
++	}
++
++	ts = cyttsp4_probe(&cyttsp4_i2c_bus_ops, &client->dev, client->irq,
++			  CYTTSP4_I2C_DATA_SIZE);
++
++	return PTR_ERR_OR_ZERO(ts);
++}
++
++static void cyttsp4_i2c_remove(struct i2c_client *client)
++{
++	struct cyttsp4 *ts = i2c_get_clientdata(client);
++
++	cyttsp4_remove(ts);
++}
++
++static const struct i2c_device_id cyttsp4_i2c_id[] = {
++	{ CYTTSP4_I2C_NAME },
++	{ }
++};
++MODULE_DEVICE_TABLE(i2c, cyttsp4_i2c_id);
++
++static struct i2c_driver cyttsp4_i2c_driver = {
++	.driver = {
++		.name	= CYTTSP4_I2C_NAME,
++		.pm	= pm_ptr(&cyttsp4_pm_ops),
++	},
++	.probe		= cyttsp4_i2c_probe,
++	.remove		= cyttsp4_i2c_remove,
++	.id_table	= cyttsp4_i2c_id,
++};
++
++module_i2c_driver(cyttsp4_i2c_driver);
++
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("Cypress TrueTouch(R) Standard Product (TTSP) I2C driver");
++MODULE_AUTHOR("Cypress");
+diff --git a/drivers/input/touchscreen/cyttsp4_spi.c b/drivers/input/touchscreen/cyttsp4_spi.c
+new file mode 100644
+index 000000000000..944fbbe9113e
+--- /dev/null
++++ b/drivers/input/touchscreen/cyttsp4_spi.c
+@@ -0,0 +1,187 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * Source for:
++ * Cypress TrueTouch(TM) Standard Product (TTSP) SPI touchscreen driver.
++ * For use with Cypress Txx4xx parts.
++ * Supported parts include:
++ * TMA4XX
++ * TMA1036
++ *
++ * Copyright (C) 2009, 2010, 2011 Cypress Semiconductor, Inc.
++ * Copyright (C) 2012 Javier Martinez Canillas <javier@dowhile0.org>
++ * Copyright (C) 2013 Cypress Semiconductor
++ *
++ * Contact Cypress Semiconductor at www.cypress.com <ttdrivers@cypress.com>
++ */
++
++#include "cyttsp4_core.h"
++
++#include <linux/delay.h>
++#include <linux/input.h>
++#include <linux/spi/spi.h>
++
++#define CY_SPI_WR_OP		0x00 /* r/~w */
++#define CY_SPI_RD_OP		0x01
++#define CY_SPI_BITS_PER_WORD	8
++#define CY_SPI_A8_BIT		0x02
++#define CY_SPI_WR_HEADER_BYTES	2
++#define CY_SPI_RD_HEADER_BYTES	1
++#define CY_SPI_CMD_BYTES	2
++#define CY_SPI_SYNC_BYTE	0
++#define CY_SPI_SYNC_ACK		0x62 /* from TRM *A protocol */
++#define CY_SPI_DATA_SIZE	(2 * 256)
++
++#define CY_SPI_DATA_BUF_SIZE	(CY_SPI_CMD_BYTES + CY_SPI_DATA_SIZE)
++
++static int cyttsp_spi_xfer(struct device *dev, u8 *xfer_buf,
++			   u8 op, u16 reg, u8 *buf, int length)
++{
++	struct spi_device *spi = to_spi_device(dev);
++	struct spi_message msg;
++	struct spi_transfer xfer[2];
++	u8 *wr_buf = &xfer_buf[0];
++	u8 rd_buf[CY_SPI_CMD_BYTES];
++	int retval;
++	int i;
++
++	if (length > CY_SPI_DATA_SIZE) {
++		dev_err(dev, "%s: length %d is too big.\n",
++			__func__, length);
++		return -EINVAL;
++	}
++
++	memset(wr_buf, 0, CY_SPI_DATA_BUF_SIZE);
++	memset(rd_buf, 0, CY_SPI_CMD_BYTES);
++
++	wr_buf[0] = op + (((reg >> 8) & 0x1) ? CY_SPI_A8_BIT : 0);
++	if (op == CY_SPI_WR_OP) {
++		wr_buf[1] = reg & 0xFF;
++		if (length > 0)
++			memcpy(wr_buf + CY_SPI_CMD_BYTES, buf, length);
++	}
++
++	memset(xfer, 0, sizeof(xfer));
++	spi_message_init(&msg);
++
++	/*
++	  We set both TX and RX buffers because Cypress TTSP
++	  requires full duplex operation.
++	*/
++	xfer[0].tx_buf = wr_buf;
++	xfer[0].rx_buf = rd_buf;
++	switch (op) {
++	case CY_SPI_WR_OP:
++		xfer[0].len = length + CY_SPI_CMD_BYTES;
++		spi_message_add_tail(&xfer[0], &msg);
++		break;
++
++	case CY_SPI_RD_OP:
++		xfer[0].len = CY_SPI_RD_HEADER_BYTES;
++		spi_message_add_tail(&xfer[0], &msg);
++
++		xfer[1].rx_buf = buf;
++		xfer[1].len = length;
++		spi_message_add_tail(&xfer[1], &msg);
++		break;
++
++	default:
++		dev_err(dev, "%s: bad operation code=%d\n", __func__, op);
++		return -EINVAL;
++	}
++
++	retval = spi_sync(spi, &msg);
++	if (retval < 0) {
++		dev_dbg(dev, "%s: spi_sync() error %d, len=%d, op=%d\n",
++			__func__, retval, xfer[1].len, op);
++
++		/*
++		 * do not return here since was a bad ACK sequence
++		 * let the following ACK check handle any errors and
++		 * allow silent retries
++		 */
++	}
++
++	if (rd_buf[CY_SPI_SYNC_BYTE] != CY_SPI_SYNC_ACK) {
++		dev_dbg(dev, "%s: operation %d failed\n", __func__, op);
++
++		for (i = 0; i < CY_SPI_CMD_BYTES; i++)
++			dev_dbg(dev, "%s: test rd_buf[%d]:0x%02x\n",
++				__func__, i, rd_buf[i]);
++		for (i = 0; i < length; i++)
++			dev_dbg(dev, "%s: test buf[%d]:0x%02x\n",
++				__func__, i, buf[i]);
++
++		return -EIO;
++	}
++
++	return 0;
++}
++
++static int cyttsp_spi_read_block_data(struct device *dev, u8 *xfer_buf,
++				      u16 addr, u8 length, void *data)
++{
++	int rc;
++
++	rc = cyttsp_spi_xfer(dev, xfer_buf, CY_SPI_WR_OP, addr, NULL, 0);
++	if (rc)
++		return rc;
++	else
++		return cyttsp_spi_xfer(dev, xfer_buf, CY_SPI_RD_OP, addr, data,
++				length);
++}
++
++static int cyttsp_spi_write_block_data(struct device *dev, u8 *xfer_buf,
++				       u16 addr, u8 length, const void *data)
++{
++	return cyttsp_spi_xfer(dev, xfer_buf, CY_SPI_WR_OP, addr, (void *)data,
++			length);
++}
++
++static const struct cyttsp4_bus_ops cyttsp_spi_bus_ops = {
++	.bustype	= BUS_SPI,
++	.write		= cyttsp_spi_write_block_data,
++	.read		= cyttsp_spi_read_block_data,
++};
++
++static int cyttsp4_spi_probe(struct spi_device *spi)
++{
++	struct cyttsp4 *ts;
++	int error;
++
++	/* Set up SPI*/
++	spi->bits_per_word = CY_SPI_BITS_PER_WORD;
++	spi->mode = SPI_MODE_0;
++	error = spi_setup(spi);
++	if (error < 0) {
++		dev_err(&spi->dev, "%s: SPI setup error %d\n",
++			__func__, error);
++		return error;
++	}
++
++	ts = cyttsp4_probe(&cyttsp_spi_bus_ops, &spi->dev, spi->irq,
++			  CY_SPI_DATA_BUF_SIZE);
++
++	return PTR_ERR_OR_ZERO(ts);
++}
++
++static void cyttsp4_spi_remove(struct spi_device *spi)
++{
++	struct cyttsp4 *ts = spi_get_drvdata(spi);
++	cyttsp4_remove(ts);
++}
++
++static struct spi_driver cyttsp4_spi_driver = {
++	.driver = {
++		.name	= CYTTSP4_SPI_NAME,
++		.pm	= pm_ptr(&cyttsp4_pm_ops),
++	},
++	.probe  = cyttsp4_spi_probe,
++	.remove = cyttsp4_spi_remove,
++};
++
++module_spi_driver(cyttsp4_spi_driver);
++
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("Cypress TrueTouch(R) Standard Product (TTSP) SPI driver");
++MODULE_AUTHOR("Cypress");
++MODULE_ALIAS("spi:cyttsp4");
+diff --git a/drivers/input/touchscreen/cyttsp_core.h b/drivers/input/touchscreen/cyttsp_core.h
+index 40a605d20285..cd3b80401970 100644
+--- a/drivers/input/touchscreen/cyttsp_core.h
++++ b/drivers/input/touchscreen/cyttsp_core.h
+@@ -136,6 +136,10 @@ struct cyttsp {
+ struct cyttsp *cyttsp_probe(const struct cyttsp_bus_ops *bus_ops,
+ 			    struct device *dev, int irq, size_t xfer_buf_size);
+ 
++int cyttsp_i2c_write_block_data(struct device *dev, u8 *xfer_buf, u16 addr,
++		u8 length, const void *values);
++int cyttsp_i2c_read_block_data(struct device *dev, u8 *xfer_buf, u16 addr,
++		u8 length, void *values);
+ extern const struct dev_pm_ops cyttsp_pm_ops;
+ 
+ #endif /* __CYTTSP_CORE_H__ */
+diff --git a/drivers/input/touchscreen/cyttsp_i2c.c b/drivers/input/touchscreen/cyttsp_i2c.c
+index cb15600549cd..bf13b3448a6b 100644
+--- a/drivers/input/touchscreen/cyttsp_i2c.c
++++ b/drivers/input/touchscreen/cyttsp_i2c.c
+@@ -22,61 +22,6 @@
+ 
+ #define CY_I2C_DATA_SIZE	128
+ 
+-static int cyttsp_i2c_read_block_data(struct device *dev, u8 *xfer_buf,
+-				      u16 addr, u8 length, void *values)
+-{
+-	struct i2c_client *client = to_i2c_client(dev);
+-	u8 client_addr = client->addr | ((addr >> 8) & 0x1);
+-	u8 addr_lo = addr & 0xFF;
+-	struct i2c_msg msgs[] = {
+-		{
+-			.addr = client_addr,
+-			.flags = 0,
+-			.len = 1,
+-			.buf = &addr_lo,
+-		},
+-		{
+-			.addr = client_addr,
+-			.flags = I2C_M_RD,
+-			.len = length,
+-			.buf = values,
+-		},
+-	};
+-	int retval;
+-
+-	retval = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
+-	if (retval < 0)
+-		return retval;
+-
+-	return retval != ARRAY_SIZE(msgs) ? -EIO : 0;
+-}
+-
+-static int cyttsp_i2c_write_block_data(struct device *dev, u8 *xfer_buf,
+-				       u16 addr, u8 length, const void *values)
+-{
+-	struct i2c_client *client = to_i2c_client(dev);
+-	u8 client_addr = client->addr | ((addr >> 8) & 0x1);
+-	u8 addr_lo = addr & 0xFF;
+-	struct i2c_msg msgs[] = {
+-		{
+-			.addr = client_addr,
+-			.flags = 0,
+-			.len = length + 1,
+-			.buf = xfer_buf,
+-		},
+-	};
+-	int retval;
+-
+-	xfer_buf[0] = addr_lo;
+-	memcpy(&xfer_buf[1], values, length);
+-
+-	retval = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
+-	if (retval < 0)
+-		return retval;
+-
+-	return retval != ARRAY_SIZE(msgs) ? -EIO : 0;
+-}
+-
+ static const struct cyttsp_bus_ops cyttsp_i2c_bus_ops = {
+ 	.bustype	= BUS_I2C,
+ 	.write		= cyttsp_i2c_write_block_data,
+diff --git a/drivers/input/touchscreen/cyttsp_i2c_common.c b/drivers/input/touchscreen/cyttsp_i2c_common.c
+new file mode 100644
+index 000000000000..7e752fb9fad7
+--- /dev/null
++++ b/drivers/input/touchscreen/cyttsp_i2c_common.c
+@@ -0,0 +1,86 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * cyttsp_i2c_common.c
++ * Cypress TrueTouch(TM) Standard Product (TTSP) I2C touchscreen driver.
++ * For use with Cypress Txx3xx and Txx4xx parts.
++ * Supported parts include:
++ * CY8CTST341
++ * CY8CTMA340
++ * TMA4XX
++ * TMA1036
++ *
++ * Copyright (C) 2009, 2010, 2011 Cypress Semiconductor, Inc.
++ * Copyright (C) 2012 Javier Martinez Canillas <javier@dowhile0.org>
++ *
++ * Contact Cypress Semiconductor at www.cypress.com <ttdrivers@cypress.com>
++ */
++
++#include <linux/device.h>
++#include <linux/export.h>
++#include <linux/i2c.h>
++#include <linux/module.h>
++#include <linux/types.h>
++
++#include "cyttsp4_core.h"
++
++int cyttsp_i2c_read_block_data(struct device *dev, u8 *xfer_buf,
++				      u16 addr, u8 length, void *values)
++{
++	struct i2c_client *client = to_i2c_client(dev);
++	u8 client_addr = client->addr | ((addr >> 8) & 0x1);
++	u8 addr_lo = addr & 0xFF;
++	struct i2c_msg msgs[] = {
++		{
++			.addr = client_addr,
++			.flags = 0,
++			.len = 1,
++			.buf = &addr_lo,
++		},
++		{
++			.addr = client_addr,
++			.flags = I2C_M_RD,
++			.len = length,
++			.buf = values,
++		},
++	};
++	int retval;
++
++	retval = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
++	if (retval < 0)
++		return retval;
++
++	return retval != ARRAY_SIZE(msgs) ? -EIO : 0;
++}
++EXPORT_SYMBOL_GPL(cyttsp_i2c_read_block_data);
++
++int cyttsp_i2c_write_block_data(struct device *dev, u8 *xfer_buf,
++				       u16 addr, u8 length, const void *values)
++{
++	struct i2c_client *client = to_i2c_client(dev);
++	u8 client_addr = client->addr | ((addr >> 8) & 0x1);
++	u8 addr_lo = addr & 0xFF;
++	struct i2c_msg msgs[] = {
++		{
++			.addr = client_addr,
++			.flags = 0,
++			.len = length + 1,
++			.buf = xfer_buf,
++		},
++	};
++	int retval;
++
++	xfer_buf[0] = addr_lo;
++	memcpy(&xfer_buf[1], values, length);
++
++	retval = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
++	if (retval < 0)
++		return retval;
++
++	return retval != ARRAY_SIZE(msgs) ? -EIO : 0;
++}
++EXPORT_SYMBOL_GPL(cyttsp_i2c_write_block_data);
++
++
++MODULE_DESCRIPTION("Cypress TrueTouch(TM) Standard Product (TTSP) I2C touchscreen driver");
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Cypress");
+diff --git a/include/linux/platform_data/cyttsp4.h b/include/linux/platform_data/cyttsp4.h
+new file mode 100644
+index 000000000000..5dc9d2be384b
+--- /dev/null
++++ b/include/linux/platform_data/cyttsp4.h
+@@ -0,0 +1,62 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++/*
++ * Header file for:
++ * Cypress TrueTouch(TM) Standard Product (TTSP) touchscreen drivers.
++ * For use with Cypress Txx3xx parts.
++ * Supported parts include:
++ * CY8CTST341
++ * CY8CTMA340
++ *
++ * Copyright (C) 2009, 2010, 2011 Cypress Semiconductor, Inc.
++ * Copyright (C) 2012 Javier Martinez Canillas <javier@dowhile0.org>
++ *
++ * Contact Cypress Semiconductor at www.cypress.com (kev@cypress.com)
++ */
++#ifndef _CYTTSP4_H_
++#define _CYTTSP4_H_
++
++#define CYTTSP4_MT_NAME "cyttsp4_mt"
++#define CYTTSP4_I2C_NAME "cyttsp4_i2c_adapter"
++#define CYTTSP4_SPI_NAME "cyttsp4_spi_adapter"
++
++#define CY_TOUCH_SETTINGS_MAX 32
++
++struct touch_framework {
++	const uint16_t  *abs;
++	uint8_t         size;
++	uint8_t         enable_vkeys;
++} __packed;
++
++struct cyttsp4_mt_platform_data {
++	struct touch_framework *frmwrk;
++	unsigned short flags;
++	char const *inp_dev_name;
++};
++
++struct touch_settings {
++	const uint8_t *data;
++	uint32_t size;
++	uint8_t tag;
++} __packed;
++
++struct cyttsp4_core_platform_data {
++	int irq_gpio;
++	int rst_gpio;
++	int level_irq_udelay;
++	int (*xres)(struct cyttsp4_core_platform_data *pdata,
++		struct device *dev);
++	int (*init)(struct cyttsp4_core_platform_data *pdata,
++		int on, struct device *dev);
++	int (*power)(struct cyttsp4_core_platform_data *pdata,
++		int on, struct device *dev, atomic_t *ignore_irq);
++	int (*irq_stat)(struct cyttsp4_core_platform_data *pdata,
++		struct device *dev);
++	struct touch_settings *sett[CY_TOUCH_SETTINGS_MAX];
++};
++
++struct cyttsp4_platform_data {
++	struct cyttsp4_core_platform_data *core_pdata;
++	struct cyttsp4_mt_platform_data *mt_pdata;
++};
++
++#endif /* _CYTTSP4_H_ */
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/Revert-drm-sun4i-lvds-Invert-the-LVDS-polarity.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/Revert-drm-sun4i-lvds-Invert-the-LVDS-polarity.patch
new file mode 100644
index 000000000000..4c49a1575cec
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/Revert-drm-sun4i-lvds-Invert-the-LVDS-polarity.patch
@@ -0,0 +1,28 @@
+From 150ddcb209012261b0a63d80ae9481134105e04a Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 1 Nov 2020 02:57:38 +0100
+Subject: Revert "drm/sun4i: lvds: Invert the LVDS polarity"
+
+This reverts commit 3bc46a083fa9f475dd2e0ab8717d9839b070b8d9.
+---
+ drivers/gpu/drm/sun4i/sun4i_tcon.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
+index 960e83c8291d..fca95b76e258 100644
+--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
++++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
+@@ -476,7 +476,9 @@ static void sun4i_tcon0_mode_set_lvds(struct sun4i_tcon *tcon,
+ 		     SUN4I_TCON0_BASIC2_V_TOTAL(mode->crtc_vtotal * 2) |
+ 		     SUN4I_TCON0_BASIC2_V_BACKPORCH(bp));
+ 
+-	reg = SUN4I_TCON0_LVDS_IF_CLK_SEL_TCON0;
++	reg = SUN4I_TCON0_LVDS_IF_CLK_SEL_TCON0 |
++		SUN4I_TCON0_LVDS_IF_DATA_POL_NORMAL |
++		SUN4I_TCON0_LVDS_IF_CLK_POL_NORMAL;
+ 	if (sun4i_tcon_get_pixel_depth(encoder) == 24)
+ 		reg |= SUN4I_TCON0_LVDS_IF_BITWIDTH_24BITS;
+ 	else
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/Revert-usb-typec-tcpm-unregister-existing-source-caps-before-re.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/Revert-usb-typec-tcpm-unregister-existing-source-caps-before-re.patch
new file mode 100644
index 000000000000..cfbff1c58939
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/Revert-usb-typec-tcpm-unregister-existing-source-caps-before-re.patch
@@ -0,0 +1,39 @@
+From 4328071664e452dc5ceff356343a04b4f399c118 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Tue, 7 May 2024 18:39:12 +0200
+Subject: Revert "usb: typec: tcpm: unregister existing source caps before
+ re-registration"
+
+This reverts commit 230ecdf71a644c9c73e0e6735b33173074ae3f94.
+---
+ drivers/usb/typec/tcpm/tcpm.c | 7 +------
+ 1 file changed, 1 insertion(+), 6 deletions(-)
+
+diff --git a/drivers/usb/typec/tcpm/tcpm.c b/drivers/usb/typec/tcpm/tcpm.c
+index 62ca4a0ec55b..2c92996954b2 100644
+--- a/drivers/usb/typec/tcpm/tcpm.c
++++ b/drivers/usb/typec/tcpm/tcpm.c
+@@ -3053,7 +3053,7 @@ static int tcpm_register_source_caps(struct tcpm_port *port)
+ {
+ 	struct usb_power_delivery_desc desc = { port->negotiated_rev };
+ 	struct usb_power_delivery_capabilities_desc caps = { };
+-	struct usb_power_delivery_capabilities *cap = port->partner_source_caps;
++	struct usb_power_delivery_capabilities *cap;
+ 
+ 	if (!port->partner_pd)
+ 		port->partner_pd = usb_power_delivery_register(NULL, &desc);
+@@ -3063,11 +3063,6 @@ static int tcpm_register_source_caps(struct tcpm_port *port)
+ 	memcpy(caps.pdo, port->source_caps, sizeof(u32) * port->nr_source_caps);
+ 	caps.role = TYPEC_SOURCE;
+ 
+-	if (cap) {
+-		usb_power_delivery_unregister_capabilities(cap);
+-		port->partner_source_caps = NULL;
+-	}
+-
+ 	cap = usb_power_delivery_register_capabilities(port->partner_pd, &caps);
+ 	if (IS_ERR(cap))
+ 		return PTR_ERR(cap);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-allwinner-dts-a64-enable-K101-IM2BYL02-panel-for-PineTab.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-allwinner-dts-a64-enable-K101-IM2BYL02-panel-for-PineTab.patch
new file mode 100644
index 000000000000..7c22387b4693
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-allwinner-dts-a64-enable-K101-IM2BYL02-panel-for-PineTab.patch
@@ -0,0 +1,35 @@
+From eff7988fc46688c551cb1d18bef171cf3243905d Mon Sep 17 00:00:00 2001
+From: Icenowy Zheng <icenowy@aosc.io>
+Date: Mon, 20 Jul 2020 01:11:34 +0800
+Subject: arm64: allwinner: dts: a64: enable K101-IM2BYL02 panel for PineTab
+
+Newer PineTab may switch to K101-IM2BYL02.
+
+Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts | 8 +++-----
+ 1 file changed, 3 insertions(+), 5 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
+index 50a0e1916743..6056c965baf6 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
+@@ -200,12 +200,10 @@ &dsi {
+ 	status = "okay";
+ 
+ 	panel@0 {
+-		compatible = "feixin,k101-im2ba02";
++		compatible = "feixin,k101-im2byl02";
+ 		reg = <0>;
+-		avdd-supply = <&reg_dc1sw>;
+-		dvdd-supply = <&reg_dc1sw>;
+-		cvdd-supply = <&reg_ldo_io1>;
+-		reset-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */
++		power-supply = <&reg_dc1sw>;
++		reset-gpios = <&pio 3 24 GPIO_ACTIVE_LOW>; /* PD24 */
+ 		backlight = <&backlight>;
+ 	};
+ };
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-allwinner-Enforce-consistent-MMC-numbering.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-allwinner-Enforce-consistent-MMC-numbering.patch
new file mode 100644
index 000000000000..e15c1e45cda1
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-allwinner-Enforce-consistent-MMC-numbering.patch
@@ -0,0 +1,66 @@
+From add1775ff68e073feb7cc5e3ada49826633c256c Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 6 Dec 2020 11:15:34 -0600
+Subject: arm64: dts: allwinner: Enforce consistent MMC numbering
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 6 ++++++
+ arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi  | 6 ++++++
+ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi  | 6 ++++++
+ 3 files changed, 18 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+index c061387abe41..c4272550580c 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+@@ -18,6 +18,12 @@ / {
+ 	#address-cells = <1>;
+ 	#size-cells = <1>;
+ 
++	aliases {
++		mmc0 = &mmc0;
++		mmc1 = &mmc1;
++		mmc2 = &mmc2;
++	};
++
+ 	chosen {
+ 		#address-cells = <1>;
+ 		#size-cells = <1>;
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
+index a6a2e2a19e75..080c3d10fdfa 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
+@@ -6,6 +6,12 @@
+ #include <dt-bindings/thermal/thermal.h>
+ 
+ / {
++	aliases {
++		mmc0 = &mmc0;
++		mmc1 = &mmc1;
++		mmc2 = &mmc2;
++	};
++
+ 	cpus {
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+index c4e35a255643..1596ff1edce4 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+@@ -17,6 +17,12 @@ / {
+ 	#address-cells = <1>;
+ 	#size-cells = <1>;
+ 
++	aliases {
++		mmc0 = &mmc0;
++		mmc1 = &mmc1;
++		mmc2 = &mmc2;
++	};
++
+ 	cpus {
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-allwinner-a64-Add-hdmi-sound-card.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-allwinner-a64-Add-hdmi-sound-card.patch
new file mode 100644
index 000000000000..a26e4b20dbd0
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-allwinner-a64-Add-hdmi-sound-card.patch
@@ -0,0 +1,48 @@
+From 6129debfdc7530a3ac08ad6486d4008b7aa7c3ab Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sun, 9 May 2021 10:39:56 +0200
+Subject: arm64: dts: allwinner: a64: Add hdmi sound card
+
+A64 supports HDMI audio. Add a sound card node for it.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 15 +++++++++++++++
+ 1 file changed, 15 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+index 0fecf0abb204..9a43bcc2f489 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+@@ -196,6 +196,20 @@ link0_codec: codec {
+ 		};
+ 	};
+ 
++	sound_hdmi: sound_hdmi {
++		compatible = "allwinner,sun9i-a80-hdmi-audio",
++			     "allwinner,sun50i-a64-hdmi-audio";
++		status = "disabled";
++
++		codec {
++			sound-dai = <&hdmi>;
++		};
++
++		cpu {
++			sound-dai = <&i2s2>;
++		};
++	};
++
+ 	timer {
+ 		compatible = "arm,armv8-timer";
+ 		allwinner,erratum-unknown1;
+@@ -1261,6 +1275,7 @@ deinterlace: deinterlace@1e00000 {
+ 		};
+ 
+ 		hdmi: hdmi@1ee0000 {
++			#sound-dai-cells = <0>;
+ 			compatible = "allwinner,sun50i-a64-dw-hdmi",
+ 				     "allwinner,sun8i-a83t-dw-hdmi";
+ 			reg = <0x01ee0000 0x10000>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-allwinner-a64-Enable-hdmi-sound-card-on-boards-with-h.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-allwinner-a64-Enable-hdmi-sound-card-on-boards-with-h.patch
new file mode 100644
index 000000000000..3cd1913aa740
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-allwinner-a64-Enable-hdmi-sound-card-on-boards-with-h.patch
@@ -0,0 +1,204 @@
+From 12b313d4d8ec2709665fd56a97d28fee9dbd5207 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sun, 9 May 2021 10:42:16 +0200
+Subject: arm64: dts: allwinner: a64: Enable hdmi sound card on boards with
+ hdmi
+
+Each board that has HDMI connector can also transmit audio through it.
+Enable HDMI sound card on all A64 boards with HDMI connector.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 8 ++++++++
+ arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts   | 8 ++++++++
+ arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts    | 7 +++++++
+ arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts | 8 ++++++++
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts       | 8 ++++++++
+ .../boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts    | 8 ++++++++
+ arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts      | 8 ++++++++
+ 7 files changed, 55 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
+index d1f415acd7b5..0b68888c9eef 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
+@@ -130,6 +130,10 @@ &i2c1_pins {
+ 	bias-pull-up;
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &mdio {
+ 	ext_rgmii_phy: ethernet-phy@1 {
+ 		compatible = "ethernet-phy-ieee802.3-c22";
+@@ -341,6 +345,10 @@ &sound {
+ 			"MIC1", "Onboard Microphone";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_pb_pins>;
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts
+index dec9960a7440..b6142224c329 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts
+@@ -102,6 +102,10 @@ &i2c1_pins {
+ 	bias-pull-up;
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &mdio {
+ 	ext_rgmii_phy: ethernet-phy@1 {
+ 		compatible = "ethernet-phy-ieee802.3-c22";
+@@ -252,6 +256,10 @@ &simplefb_hdmi {
+ 	vcc-hdmi-supply = <&reg_dldo1>;
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_pb_pins>;
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
+index fd3794678c33..0cc2e11dcb92 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
+@@ -120,6 +120,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &mdio {
+ 	ext_rgmii_phy: ethernet-phy@1 {
+ 		compatible = "ethernet-phy-ieee802.3-c22";
+@@ -355,6 +359,9 @@ &sound {
+ 		    "MIC1", "Microphone Jack Left",
+ 		    "Microphone Jack Right", "MBIAS",
+ 		    "MIC2", "Microphone Jack Right";
++};
++
++&sound_hdmi {
+ 	status = "okay";
+ };
+ 
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
+index c8303a66438d..9194ca4b1e19 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
+@@ -137,6 +137,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &mdio {
+ 	ext_rgmii_phy: ethernet-phy@1 {
+ 		compatible = "ethernet-phy-ieee802.3-c22";
+@@ -340,6 +344,10 @@ &sound {
+ 			"MIC1", "Onboard Microphone";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &spi0 {
+ 	status = "okay";
+ 
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+index 09e71fd60785..51bedd34fc25 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+@@ -107,6 +107,10 @@ &i2c1_pins {
+ 	bias-pull-up;
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &mdio {
+ 	ext_rmii_phy1: ethernet-phy@1 {
+ 		compatible = "ethernet-phy-ieee802.3-c22";
+@@ -270,6 +274,10 @@ &sound {
+ 	status = "okay";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ /* On Euler connector */
+ &spdif {
+ 	status = "disabled";
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
+index be2347c8f267..70c7f8ff49ad 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
+@@ -96,6 +96,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &mdio {
+ 	ext_rgmii_phy: ethernet-phy@1 {
+ 		compatible = "ethernet-phy-ieee802.3-c22";
+@@ -169,6 +173,10 @@ &sound {
+ 	status = "okay";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_pb_pins>;
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts
+index ec055510af8b..992dc947551d 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-teres-i.dts
+@@ -150,6 +150,10 @@ anx6345_in: endpoint {
+ 	};
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &mixer0 {
+ 	status = "okay";
+ };
+@@ -366,6 +370,10 @@ &sound {
+ 	status = "okay";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &tcon0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&lcd_rgb666_pins>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-allwinner-a64-Fix-LRADC-compatible.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-allwinner-a64-Fix-LRADC-compatible.patch
new file mode 100644
index 000000000000..dbc1ee3adebe
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-allwinner-a64-Fix-LRADC-compatible.patch
@@ -0,0 +1,32 @@
+From c675093587794fbf1de91fa2de45aea0c117b901 Mon Sep 17 00:00:00 2001
+From: Icenowy Zheng <icenowy@aosc.io>
+Date: Sun, 30 Jun 2019 22:45:34 +0800
+Subject: arm64: dts: allwinner: a64: Fix LRADC compatible
+
+The LRADC reference voltage of A64 is 2.0V, and AVCC is 3.0V. So the
+internal voltage divider is 2/3 (the A10 value), not 3/4 (the A83T
+value).
+
+Fix the compatible string of the A64 LRADC.
+
+Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+index d53a6f7e086a..c061387abe41 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+@@ -921,7 +921,7 @@ spdif: spdif@1c21000 {
+ 
+ 		lradc: lradc@1c21800 {
+ 			compatible = "allwinner,sun50i-a64-lradc",
+-				     "allwinner,sun8i-a83t-r-lradc";
++				     "allwinner,sun4i-a10-lradc-keys";
+ 			reg = <0x01c21800 0x400>;
+ 			interrupt-parent = <&r_intc>;
+ 			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-allwinner-a64-pinetab-add-front-camera.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-allwinner-a64-pinetab-add-front-camera.patch
new file mode 100644
index 000000000000..fc01a5a392fd
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-allwinner-a64-pinetab-add-front-camera.patch
@@ -0,0 +1,99 @@
+From 572548e1235cc21b5be242b267fdc66984d6d3f8 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 17 Nov 2020 01:06:30 +0100
+Subject: arm64: dts: allwinner: a64: pinetab: add front camera
+
+---
+ .../boot/dts/allwinner/sun50i-a64-pinetab.dts | 50 ++++++++++++++++---
+ 1 file changed, 44 insertions(+), 6 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
+index f5fb1ee32dad..50a0e1916743 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
+@@ -55,12 +55,35 @@ i2c-csi {
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+ 
++		/* Front camera */
++		gc2145: front-camera@3c {
++			compatible = "galaxycore,gc2145";
++			reg = <0x3c>;
++			clocks = <&ccu CLK_CSI_MCLK>;
++			clock-names = "xclk";
++
++			AVDD-supply = <&reg_dldo3>;
++			DVDD-supply = <&reg_aldo1>;
++			IOVDD-supply = <&reg_eldo3>;
++			reset-gpios = <&pio 4 16 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; /* PE16 */
++			enable-gpios = <&pio 4 17 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; /* PE17 */
++
++			port {
++				gc2145_ep: endpoint {
++					remote-endpoint = <&csi_gc2145_ep>;
++					bus-width = <8>;
++					hsync-active = <1>;
++					vsync-active = <1>;
++					data-active = <1>;
++					pclk-sample = <1>;
++				};
++			};
++		};
++
+ 		/* Rear camera */
+-		ov5640: camera@3c {
++		ov5640: rear-camera@4c {
+ 			compatible = "ovti,ov5640";
+-			reg = <0x3c>;
+-			pinctrl-names = "default";
+-			pinctrl-0 = <&csi_mclk_pin>;
++			reg = <0x4c>;
+ 			clocks = <&ccu CLK_CSI_MCLK>;
+ 			clock-names = "xclk";
+ 
+@@ -72,7 +95,7 @@ ov5640: camera@3c {
+ 
+ 			port {
+ 				ov5640_ep: endpoint {
+-					remote-endpoint = <&csi_ep>;
++					remote-endpoint = <&csi_ov5640_ep>;
+ 					bus-width = <8>;
+ 					hsync-active = <1>; /* Active high */
+ 					vsync-active = <0>; /* Active low */
+@@ -131,10 +154,15 @@ &cpu3 {
+ };
+ 
+ &csi {
++	pinctrl-0 = <&csi_pins>, <&csi_mclk_pin>;
+ 	status = "okay";
+ 
+ 	port {
+-		csi_ep: endpoint {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		csi_ov5640_ep: endpoint@0 {
++			reg = <0>;
+ 			remote-endpoint = <&ov5640_ep>;
+ 			bus-width = <8>;
+ 			hsync-active = <1>; /* Active high */
+@@ -142,6 +170,16 @@ csi_ep: endpoint {
+ 			data-active = <1>;  /* Active high */
+ 			pclk-sample = <1>;  /* Rising */
+ 		};
++
++		csi_gc2145_ep: endpoint@1 {
++			reg = <1>;
++			remote-endpoint = <&gc2145_ep>;
++			bus-width=<8>;
++			hsync-active = <1>; /* Active high */
++			vsync-active = <1>; /* Active high */
++			data-active = <1>;  /* Active high */
++			pclk-sample = <1>;  /* Rising */
++		};
+ 	};
+ };
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-allwinner-h5-Enable-hdmi-sound-card-on-boards-with-hd.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-allwinner-h5-Enable-hdmi-sound-card-on-boards-with-hd.patch
new file mode 100644
index 000000000000..b085458fe29f
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-allwinner-h5-Enable-hdmi-sound-card-on-boards-with-hd.patch
@@ -0,0 +1,113 @@
+From 7835fbd016daedfa548cdb6b9c4b9d663bc67c73 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sun, 9 May 2021 12:40:31 +0200
+Subject: arm64: dts: allwinner: h5: Enable hdmi sound card on boards with hdmi
+
+Each board that has HDMI connector can also transmit audio through it.
+Enable HDMI sound card on all H5 boards with HDMI connector.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ .../dts/allwinner/sun50i-h5-emlid-neutis-n5-devboard.dts  | 8 ++++++++
+ arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts  | 8 ++++++++
+ .../arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts | 8 ++++++++
+ .../boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts  | 8 ++++++++
+ 4 files changed, 32 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5-devboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5-devboard.dts
+index 076a0b983101..5882b62097a9 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5-devboard.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-emlid-neutis-n5-devboard.dts
+@@ -69,3 +69,11 @@ hdmi_out_con: endpoint {
+ &i2c1 {
+ 	status = "okay";
+ };
++
++&i2s2 {
++	status = "okay";
++};
++
++&sound_hdmi {
++	status = "okay";
++};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
+index 0f29da7d51e6..f420acc6f49f 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
+@@ -145,6 +145,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &ir {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&r_ir_rx_pin>;
+@@ -191,6 +195,10 @@ reg_vdd_cpux: regulator@65 {
+ 	};
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &spi0  {
+ 	status = "okay";
+ 
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
+index d4fc4e60e4e7..42d0ffa4a864 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
+@@ -145,6 +145,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &ir {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&r_ir_rx_pin>;
+@@ -183,6 +187,10 @@ &ohci3 {
+ 	status = "okay";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_pa_pins>;
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts
+index 3eb986c354a9..281d37d46d43 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus2.dts
+@@ -77,6 +77,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &mmc0 {
+ 	vmmc-supply = <&reg_vcc3v3>;
+ 	disable-wp;
+@@ -116,6 +120,10 @@ &ohci0 {
+ 	status = "okay";
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_pa_pins>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-allwinner-h6-Add-hdmi-sound-card.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-allwinner-h6-Add-hdmi-sound-card.patch
new file mode 100644
index 000000000000..2589bd609691
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-allwinner-h6-Add-hdmi-sound-card.patch
@@ -0,0 +1,56 @@
+From eedcdc30e7c22e62ce01296f6fefc63b1143e810 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Tue, 10 Nov 2020 20:43:28 +0100
+Subject: arm64: dts: allwinner: h6: Add hdmi sound card
+
+H6 supports HDMI audio. Add a sound card node for it.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 16 ++++++++++++++++
+ 1 file changed, 16 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+index 2301c59b41b1..13fe21b00711 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+@@ -126,6 +126,20 @@ psci {
+ 		method = "smc";
+ 	};
+ 
++	sound_hdmi: sound_hdmi {
++		compatible = "allwinner,sun9i-a80-hdmi-audio",
++			     "allwinner,sun50i-h6-hdmi-audio";
++		status = "disabled";
++
++		codec {
++			sound-dai = <&hdmi>;
++		};
++
++		cpu {
++			sound-dai = <&i2s1>;
++		};
++	};
++
+ 	timer {
+ 		compatible = "arm,armv8-timer";
+ 		arm,no-tick-in-suspend;
+@@ -139,6 +153,7 @@ timer {
+ 			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ 	};
+ 
++
+ 	soc {
+ 		compatible = "simple-bus";
+ 		#address-cells = <1>;
+@@ -817,6 +832,7 @@ ohci3: usb@5311400 {
+ 		};
+ 
+ 		hdmi: hdmi@6000000 {
++			#sound-dai-cells = <0>;
+ 			compatible = "allwinner,sun50i-h6-dw-hdmi";
+ 			reg = <0x06000000 0x10000>;
+ 			reg-io-width = <1>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-allwinner-h6-Enable-hdmi-sound-card-on-boards-with-hd.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-allwinner-h6-Enable-hdmi-sound-card-on-boards-with-hd.patch
new file mode 100644
index 000000000000..109c6a2cd839
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-allwinner-h6-Enable-hdmi-sound-card-on-boards-with-hd.patch
@@ -0,0 +1,123 @@
+From dead2c32ebf5c0c69df98a4b72e35e11753991b2 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 11 Jan 2022 13:08:47 +0100
+Subject: arm64: dts: allwinner: h6: Enable hdmi sound card on boards with hdmi
+
+Each board that has HDMI connector can also transmit audio through it.
+Enable HDMI sound card on all H6 boards with HDMI connector.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 8 ++++++++
+ arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts  | 8 ++++++++
+ arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi   | 8 ++++++++
+ arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts    | 8 ++++++++
+ 4 files changed, 32 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
+index 13a0e63afeaf..4044c33c92f2 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
+@@ -119,6 +119,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s1 {
++	status = "okay";
++};
++
+ &mdio {
+ 	ext_rgmii_phy: ethernet-phy@1 {
+ 		compatible = "ethernet-phy-ieee802.3-c22";
+@@ -291,6 +295,10 @@ sw {
+ 	};
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &spdif {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&spdif_tx_pin>;
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
+index 48d720e20334..7e11286bf6d1 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
+@@ -167,6 +167,10 @@ ext_rgmii_phy: ethernet-phy@1 {
+ 	};
+ };
+ 
++&i2s1 {
++	status = "okay";
++};
++
+ &mmc0 {
+ 	vmmc-supply = <&reg_cldo1>;
+ 	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+@@ -340,6 +344,10 @@ &rtc {
+ 	clocks = <&ext_osc32k>;
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_ph_pins>;
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
+index d05dc5d6e6b9..ed4d4672f4c9 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
+@@ -91,6 +91,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s1 {
++	status = "okay";
++};
++
+ &mmc0 {
+ 	vmmc-supply = <&reg_cldo1>;
+ 	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
+@@ -245,6 +249,10 @@ &rtc {
+ 	clocks = <&ext_osc32k>;
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_ph_pins>;
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
+index fa7a765ee828..95aea02bce40 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
+@@ -123,6 +123,10 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2s1 {
++	status = "okay";
++};
++
+ &mdio {
+ 	ext_rgmii_phy: ethernet-phy@1 {
+ 		compatible = "ethernet-phy-ieee802.3-c22";
+@@ -299,6 +303,10 @@ &rtc {
+ 	clocks = <&ext_osc32k>;
+ };
+ 
++&sound_hdmi {
++	status = "okay";
++};
++
+ /*
+  * The CS pin is shared with the MMC2 CMD pin, so we cannot have the SPI
+  * flash and eMMC at the same time, as one of them would fail probing.
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-allwinner-orange-pi-3-Enable-ethernet.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-allwinner-orange-pi-3-Enable-ethernet.patch
new file mode 100644
index 000000000000..89e454ee1ff7
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-allwinner-orange-pi-3-Enable-ethernet.patch
@@ -0,0 +1,105 @@
+From 4e0844ed190a4de7091fac2fcb3f1cfb7b6893dd Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 20 Aug 2019 14:54:48 +0200
+Subject: arm64: dts: allwinner: orange-pi-3: Enable ethernet
+
+Orange Pi 3 has two regulators that power the Realtek RTL8211E
+PHY. According to the datasheet, both regulators need to be enabled
+at the same time, or that "phy-io" should be enabled slightly earlier
+than "phy" regulator.
+
+RTL8211E/RTL8211EG datasheet says:
+
+  Note 4: 2.5V (or 1.8/1.5V) RGMII power should be risen simultaneously
+  or slightly earlier than 3.3V power. Rising 2.5V (or 1.8/1.5V) power
+  later than 3.3V power may lead to errors.
+
+The driver ensures the regulator enable ordering. The timing is set
+in DT via startup-delay-us.
+
+We also need to wait at least 30ms after power-up/reset, before
+accessing the PHY registers.
+
+All values of RX/TX delay were tested exhaustively and a middle one
+of the range of working values was chosen.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../dts/allwinner/sun50i-h6-orangepi-3.dts    | 40 +++++++++++++++++++
+ 1 file changed, 40 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
+index ab87c3447cd7..48d720e20334 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
+@@ -15,6 +15,7 @@ / {
+ 	aliases {
+ 		serial0 = &uart0;
+ 		serial1 = &uart1;
++		ethernet0 = &emac;
+ 	};
+ 
+ 	chosen {
+@@ -64,6 +65,15 @@ reg_vcc5v: vcc5v {
+ 		regulator-always-on;
+ 	};
+ 
++	reg_gmac_2v5: gmac-2v5 {
++		compatible = "regulator-fixed";
++		regulator-name = "gmac-2v5";
++		regulator-min-microvolt = <2500000>;
++		regulator-max-microvolt = <2500000>;
++		enable-active-high;
++		gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
++	};
++
+ 	reg_vcc33_wifi: vcc33-wifi {
+ 		/* Always on 3.3V regulator for WiFi and BT */
+ 		compatible = "regulator-fixed";
+@@ -128,6 +138,35 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&emac {
++	pinctrl-names = "default";
++	pinctrl-0 = <&ext_rgmii_pins>;
++	phy-mode = "rgmii-id";
++	phy-handle = <&ext_rgmii_phy>;
++	/*
++	 * The board uses 2.5V RGMII signalling. Power sequence to enable
++	 * the phy is to enable GMAC-2V5 and GMAC-3V (aldo2) power rails
++	 * at the same time and to wait 100ms. The driver enables phy-io
++	 * first. Delay is achieved with enable-ramp-delay on reg_aldo2.
++	 */
++	phy-supply = <&reg_aldo2>;
++	phy-io-supply = <&reg_gmac_2v5>;
++	allwinner,rx-delay-ps = <200>;
++	allwinner,tx-delay-ps = <200>;
++	status = "okay";
++};
++
++&mdio {
++	ext_rgmii_phy: ethernet-phy@1 {
++		compatible = "ethernet-phy-ieee802.3-c22";
++		reg = <1>;
++
++		reset-gpios = <&pio 3 14 GPIO_ACTIVE_LOW>; /* PD14 */
++		reset-assert-us = <15000>;
++		reset-deassert-us = <40000>;
++	};
++};
++
+ &mmc0 {
+ 	vmmc-supply = <&reg_cldo1>;
+ 	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+@@ -212,6 +251,7 @@ reg_aldo2: aldo2 {
+ 				regulator-min-microvolt = <3300000>;
+ 				regulator-max-microvolt = <3300000>;
+ 				regulator-name = "vcc33-audio-tv-ephy-mac";
++				regulator-enable-ramp-delay = <100000>;
+ 			};
+ 
+ 			/* ALDO3 is shorted to CLDO1 */
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-rk3399-Add-dmc_opp_table.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-rk3399-Add-dmc_opp_table.patch
new file mode 100644
index 000000000000..686684e5868f
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-rk3399-Add-dmc_opp_table.patch
@@ -0,0 +1,62 @@
+From 90c0c047de85bdde3752b7556d4abf735df72242 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Fri, 22 Nov 2024 23:41:48 +0100
+Subject: arm64: dts: rk3399: Add dmc_opp_table
+
+This was removed in v6.12. Re-add it with original values.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/boot/dts/rockchip/rk3399.dtsi | 29 ++++++++++++++++++++++++
+ 1 file changed, 29 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+index 6bc1249d99e6..bb9205bebf9f 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+@@ -104,6 +104,31 @@ opp05 {
+ 			opp-microvolt = <1100000 1100000 1150000>;
+ 		};
+ 	};
++
++	dmc_opp_table: opp-table-3 {
++		compatible = "operating-points-v2";
++
++		opp00 {
++			opp-hz = /bits/ 64 <328000000>;
++			opp-microvolt = <900000>;
++		};
++		opp01 {
++			opp-hz = /bits/ 64 <416000000>;
++			opp-microvolt = <900000>;
++		};
++		opp02 {
++			opp-hz = /bits/ 64 <666000000>;
++			opp-microvolt = <900000>;
++		};
++		opp03 {
++			opp-hz = /bits/ 64 <856000000>;
++			opp-microvolt = <900000>;
++		};
++		opp04 {
++			opp-hz = /bits/ 64 <928000000>;
++			opp-microvolt = <925000>;
++		};
++	};
+ };
+ 
+ &cpu_l0 {
+@@ -130,6 +155,10 @@ &cpu_b1 {
+ 	operating-points-v2 = <&cluster1_opp>;
+ };
+ 
++&dmc {
++	operating-points-v2 = <&dmc_opp_table>;
++};
++
+ &gpu {
+ 	operating-points-v2 = <&gpu_opp_table>;
+ };
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-rockchip-rk3399-s-Add-DMC-table.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-rockchip-rk3399-s-Add-DMC-table.patch
new file mode 100644
index 000000000000..8bcf9982009d
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-rockchip-rk3399-s-Add-DMC-table.patch
@@ -0,0 +1,62 @@
+From ea6833fd7294f14e4e84d6dde5fa11f82243f1a8 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Thu, 28 Nov 2024 11:16:31 +0100
+Subject: arm64: dts: rockchip: rk3399-s: Add DMC table
+
+This is used by Pinephone Pro.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/boot/dts/rockchip/rk3399-s.dtsi | 29 ++++++++++++++++++++++
+ 1 file changed, 29 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk3399-s.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-s.dtsi
+index e54f451af9f3..82b941720294 100644
+--- a/arch/arm64/boot/dts/rockchip/rk3399-s.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399-s.dtsi
+@@ -92,6 +92,31 @@ opp05 {
+ 			opp-microvolt = <1100000 1100000 1150000>;
+ 		};
+ 	};
++
++	dmc_opp_table: opp-table-3 {
++		compatible = "operating-points-v2";
++
++		opp00 {
++			opp-hz = /bits/ 64 <328000000>;
++			opp-microvolt = <900000>;
++		};
++		opp01 {
++			opp-hz = /bits/ 64 <416000000>;
++			opp-microvolt = <900000>;
++		};
++		opp02 {
++			opp-hz = /bits/ 64 <666000000>;
++			opp-microvolt = <900000>;
++		};
++		opp03 {
++			opp-hz = /bits/ 64 <856000000>;
++			opp-microvolt = <900000>;
++		};
++		opp04 {
++			opp-hz = /bits/ 64 <928000000>;
++			opp-microvolt = <925000>;
++		};
++	};
+ };
+ 
+ &cpu_l0 {
+@@ -118,6 +143,10 @@ &cpu_b1 {
+ 	operating-points-v2 = <&cluster1_opp>;
+ };
+ 
++&dmc {
++	operating-points-v2 = <&dmc_opp_table>;
++};
++
+ &gpu {
+ 	operating-points-v2 = <&gpu_opp_table>;
+ };
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-rockchip-rk356x-Fix-PCIe-register-map-and-ranges.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-rockchip-rk356x-Fix-PCIe-register-map-and-ranges.patch
new file mode 100644
index 000000000000..4ba8d341bbe6
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-rockchip-rk356x-Fix-PCIe-register-map-and-ranges.patch
@@ -0,0 +1,47 @@
+From e35cba7b314073d85e8229ce603d291c0f720a68 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sat, 24 Sep 2022 21:59:07 +0200
+Subject: arm64: dts: rockchip: rk356x: Fix PCIe register map and ranges
+
+I have two Realtek PCIe wifi cards connected over the 4 port PCIe bridge
+to Quartz64-A. The cards fail to work, when nvme SSD is connected at the
+same time to the bridge. Without nvme connected, cards work fine. The
+issue seems to be related to mixed use of devices which make use of I/O
+ranges and memory ranges.
+
+This patch changes I/O, MEM and config mappings so that config and I/O
+mappings use the 0xf4000000 outbound address space, and MEM range uses
+the whole 0x300000000 outbound space.
+
+These values were suggested by pgwipeout:
+
+  https://lore.kernel.org/lkml/875ygbsrf3.fsf@bloch.sibelius.xs4all.nl/T/#m84b5f6992cc26dffe0d3783c0d8c9c86e5e10c10
+
+This is identical to how BSP does the mappings.
+
+This change to the regs/ranges makes the issue go away and both nvme and
+wifi cards work when connected at the same time to the bridge. I tested
+the nvme with large amount of reads/writes, both behind the PCIe bridge
+and when directly connected to Quartz64-A board.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi
+index 8421d4b8c771..3dd63161bbf1 100644
+--- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi
+@@ -954,7 +954,7 @@ pcie2x1: pcie@fe260000 {
+ 				<0 0 0 4 &pcie_intc 3>;
+ 		linux,pci-domain = <0>;
+ 		num-ib-windows = <6>;
+-		num-ob-windows = <2>;
++		num-ob-windows = <8>;
+ 		max-link-speed = <2>;
+ 		msi-map = <0x0 &gic 0x0 0x1000>;
+ 		num-lanes = <1>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50-a64-pinephone-Define-jack-pins-in-DT.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50-a64-pinephone-Define-jack-pins-in-DT.patch
new file mode 100644
index 000000000000..48a2b34a1280
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50-a64-pinephone-Define-jack-pins-in-DT.patch
@@ -0,0 +1,30 @@
+From ed8e79073bb141a1f5a5b5f2b891e3c9be8079c8 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Tue, 14 May 2024 10:47:05 +0200
+Subject: arm64: dts: sun50-a64-pinephone: Define jack pins in DT
+
+To restore pre v6.8 behavior of the sound card.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index f0f1367c5868..d502c1392b8e 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -999,6 +999,10 @@ &sound {
+ 			"MIC1", "Internal Microphone",
+ 			"Headset Microphone", "HBIAS",
+ 			"MIC2", "Headset Microphone";
++	simple-audio-card,jack-pins =
++			"1c22e00.codec", "Headphone Jack",
++			"1c22e00.codec", "Headset Microphone";
++	simple-audio-card,jack-pins-mask = <1>, <2>;
+ 
+ 	simple-audio-card,dai-link@1 {
+ 		format = "dsp_a";
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-Define-orientation-and-rotation-for-PinePhone-.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-Define-orientation-and-rotation-for-PinePhone-.patch
new file mode 100644
index 000000000000..2e608e06d9d9
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-Define-orientation-and-rotation-for-PinePhone-.patch
@@ -0,0 +1,31 @@
+From b0ce326666eaf6803bcc5723af14c513eff895d5 Mon Sep 17 00:00:00 2001
+From: Arnav Singh <me@arnavion.dev>
+Date: Mon, 6 May 2024 16:36:04 -0700
+Subject: arm64: dts: sun50i: Define orientation and rotation for PinePhone
+ rear camera
+
+This enables libcamera to detect the correct orientation from
+the device tree and propagate it further to e.g. Pipewire.
+
+Signed-off-by: Arnav Singh <me@arnavion.dev>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index e7e90e5baff4..1a57720c25ef 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -617,6 +617,9 @@ ov5640: rear-camera@4c {
+ 		reset-gpios = <&pio 3 3 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; /* PD3 */
+ 		powerdown-gpios = <&pio 2 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; /* PC0 */
+ 
++		orientation = <1>;
++		rotation = <270>;
++
+ 		port {
+ 			ov5640_ep: endpoint {
+ 				remote-endpoint = <&csi_ov5640_ep>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-Set-fifo-size-for-uarts.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-Set-fifo-size-for-uarts.patch
new file mode 100644
index 000000000000..5c5658df204d
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-Set-fifo-size-for-uarts.patch
@@ -0,0 +1,59 @@
+From d742191977aca3b6ba39e760ff7c307728e10eb2 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 1 Feb 2020 23:41:18 +0100
+Subject: arm64: dts: sun50i-a64: Set fifo-size for uarts
+
+Boot time optimization.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+index 9a43bcc2f489..d53a6f7e086a 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+@@ -1012,6 +1012,7 @@ uart0: serial@1c28000 {
+ 			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ 			reg-shift = <2>;
+ 			reg-io-width = <4>;
++			fifo-size = <64>;
+ 			clocks = <&ccu CLK_BUS_UART0>;
+ 			resets = <&ccu RST_BUS_UART0>;
+ 			status = "disabled";
+@@ -1023,6 +1024,7 @@ uart1: serial@1c28400 {
+ 			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+ 			reg-shift = <2>;
+ 			reg-io-width = <4>;
++			fifo-size = <64>;
+ 			clocks = <&ccu CLK_BUS_UART1>;
+ 			resets = <&ccu RST_BUS_UART1>;
+ 			status = "disabled";
+@@ -1034,6 +1036,7 @@ uart2: serial@1c28800 {
+ 			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ 			reg-shift = <2>;
+ 			reg-io-width = <4>;
++			fifo-size = <64>;
+ 			clocks = <&ccu CLK_BUS_UART2>;
+ 			resets = <&ccu RST_BUS_UART2>;
+ 			status = "disabled";
+@@ -1045,6 +1048,7 @@ uart3: serial@1c28c00 {
+ 			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ 			reg-shift = <2>;
+ 			reg-io-width = <4>;
++			fifo-size = <64>;
+ 			clocks = <&ccu CLK_BUS_UART3>;
+ 			resets = <&ccu RST_BUS_UART3>;
+ 			status = "disabled";
+@@ -1056,6 +1060,7 @@ uart4: serial@1c29000 {
+ 			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ 			reg-shift = <2>;
+ 			reg-io-width = <4>;
++			fifo-size = <64>;
+ 			clocks = <&ccu CLK_BUS_UART4>;
+ 			resets = <&ccu RST_BUS_UART4>;
+ 			status = "disabled";
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-Type-C-support-for-all-PP-va.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-Type-C-support-for-all-PP-va.patch
new file mode 100644
index 000000000000..54ebfbfc6e2a
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-Type-C-support-for-all-PP-va.patch
@@ -0,0 +1,416 @@
+From dbf95776199d6ae835f22bcb28af833821d3e2b2 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Wed, 8 Jul 2020 00:58:16 +0200
+Subject: arm64: dts: sun50i-a64-pinephone: Add Type-C support for all PP
+ variants 1.0-1.2
+
+There are differences in GPIO and how VBUS is handled. Describe them
+in DTS. Thankfully we can support both unmodded and modded variants
+of 1.0 and 1.1 boards with one DTS. No need for more subvariants.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../allwinner/sun50i-a64-pinephone-1.0.dts    | 86 +++++++++++++++++++
+ .../allwinner/sun50i-a64-pinephone-1.1.dts    | 86 +++++++++++++++++++
+ .../allwinner/sun50i-a64-pinephone-1.2.dts    | 60 +++++++++++++
+ .../dts/allwinner/sun50i-a64-pinephone.dtsi   | 68 ++++++++++++++-
+ 4 files changed, 299 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts
+index 219f720b8b7d..498ae493d176 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts
+@@ -8,6 +8,92 @@
+ / {
+ 	model = "Pine64 PinePhone Developer Batch (1.0)";
+ 	compatible = "pine64,pinephone-1.0", "pine64,pinephone", "allwinner,sun50i-a64";
++
++	reg_vbus: usb0-vbus {
++		compatible = "regulator-fixed";
++		regulator-name = "usb0-vbus";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
++		enable-active-high;
++		vin-supply = <&reg_drivevbus>;
++	};
++};
++
++&axp803 {
++	x-powers,drive-vbus-en;
++};
++
++&i2c0 {
++	hdmi-bridge@28 {
++		compatible = "analogix,anx7688";
++		reg = <0x28>;
++
++		interrupt-parent = <&r_pio>;
++		interrupts = <0 11 IRQ_TYPE_EDGE_FALLING>; /* PL11 */
++
++		enable-gpios = <&pio 3 10 GPIO_ACTIVE_LOW>; /* PD10 */
++		reset-gpios = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */
++
++		cabledet-gpios = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
++
++		avdd10-supply = <&reg_anx1v0>;
++		dvdd10-supply = <&reg_anx1v0>;
++		/* This is for the HW hack variant, but will also work for non-modified version. */
++		avdd18-supply = <&reg_ldo_io1>;
++		dvdd18-supply = <&reg_ldo_io1>;
++		avdd33-supply = <&reg_dldo1>;
++		vconn-supply = <&reg_vconn5v0>;
++		hdmi_vt-supply = <&reg_dldo1>;
++
++		source-caps = <
++			PDO_FIXED(5000, 500, PDO_FIXED_DATA_SWAP | PDO_FIXED_USB_COMM | PDO_FIXED_DUAL_ROLE)
++		>;
++
++		sink-caps = <
++			PDO_FIXED(5000, 3000, PDO_FIXED_DATA_SWAP | PDO_FIXED_USB_COMM | PDO_FIXED_DUAL_ROLE)
++		>;
++
++		/*
++		 * ANX7688 can't enable/disable USB-5V <-> DCIN switch by
++		 * itself, and PMIC's N_VBUSEN is not connected anywhere either,
++		 * so we need to configure everything in software:
++		 *
++		 * - get the VBUS status from ANX7688 via I2C
++		 * - configure PMIC to let it know vbus drive status (via
++		 *   reg_drivevbus)
++		 * - enable VBUS switch and USB-5V regulator (via reg_vbus
++		 *   and reg_usb_5v)
++		 */
++		vbus-supply = <&reg_vbus>;
++		vbus_in-supply = <&usb_power_supply>;
++
++		port {
++			typec0_dr_sw: endpoint {
++				remote-endpoint = <&usb0_drd_sw>;
++			};
++		};
++	};
++};
++
++/*
++ * The N_VBUSEN pin is disconnected, but we need to inform the PMIC about
++ * the VBUS status anyway. To avoid the pin from floating and to inform
++ * the PMIC, about VBUS status, we couple reg_drivevbus with reg_vbus.
++ */
++&reg_drivevbus {
++	vin-supply = <&reg_usb_5v>;
++	status = "okay";
++};
++
++&usbphy {
++	usb-role-switch;
++
++	port {
++		usb0_drd_sw: endpoint {
++			remote-endpoint = <&typec0_dr_sw>;
++		};
++	};
+ };
+ 
+ &codec_analog {
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
+index 723af64a9cee..73275308f484 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
+@@ -8,6 +8,20 @@
+ / {
+ 	model = "Pine64 PinePhone Braveheart (1.1)";
+ 	compatible = "pine64,pinephone-1.1", "pine64,pinephone", "allwinner,sun50i-a64";
++
++	reg_vbus: usb0-vbus {
++		compatible = "regulator-fixed";
++		regulator-name = "usb0-vbus";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
++		enable-active-high;
++		vin-supply = <&reg_drivevbus>;
++	};
++};
++
++&axp803 {
++	x-powers,drive-vbus-en;
+ };
+ 
+ &backlight {
+@@ -33,7 +47,79 @@ &codec_analog {
+ 	allwinner,internal-bias-resistor;
+ };
+ 
++&i2c0 {
++	hdmi-bridge@28 {
++		compatible = "analogix,anx7688";
++		reg = <0x28>;
++
++		interrupt-parent = <&r_pio>;
++		interrupts = <0 11 IRQ_TYPE_EDGE_FALLING>; /* PL11 */
++
++		enable-gpios = <&pio 3 10 GPIO_ACTIVE_LOW>; /* PD10 */
++		reset-gpios = <&r_pio 0 9 GPIO_ACTIVE_HIGH>; /* PL9 */
++
++		cabledet-gpios = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
++
++		avdd10-supply = <&reg_anx1v0>;
++		dvdd10-supply = <&reg_anx1v0>;
++		/* This is for the HW hack variant, but will also work for non-modified version. */
++		avdd18-supply = <&reg_ldo_io1>;
++		dvdd18-supply = <&reg_ldo_io1>;
++		avdd33-supply = <&reg_dldo1>;
++		vconn-supply = <&reg_vconn5v0>;
++		hdmi_vt-supply = <&reg_dldo1>;
++
++		source-caps = <
++			PDO_FIXED(5000, 500, PDO_FIXED_DATA_SWAP | PDO_FIXED_USB_COMM | PDO_FIXED_DUAL_ROLE)
++		>;
++
++		sink-caps = <
++			PDO_FIXED(5000, 3000, PDO_FIXED_DATA_SWAP | PDO_FIXED_USB_COMM | PDO_FIXED_DUAL_ROLE)
++		>;
++
++		/*
++		 * ANX7688 can't enable/disable USB-5V <-> DCIN switch by
++		 * itself, and PMIC's N_VBUSEN is not connected anywhere either,
++		 * so we need to configure everything in software:
++		 *
++		 * - get the VBUS status from ANX7688 via I2C
++		 * - configure PMIC to let it know vbus drive status (via
++		 *   reg_drivevbus)
++		 * - enable VBUS switch and USB-5V regulator (via reg_vbus
++		 *   and reg_usb_5v)
++		 */
++		vbus-supply = <&reg_vbus>;
++		vbus_in-supply = <&usb_power_supply>;
++
++		port {
++			typec0_dr_sw: endpoint {
++				remote-endpoint = <&usb0_drd_sw>;
++			};
++		};
++	};
++};
++
++/*
++ * The N_VBUSEN pin is disconnected, but we need to inform the PMIC about
++ * the VBUS status anyway. To avoid the pin from floating and to inform
++ * the PMIC, about VBUS status, we couple reg_drivevbus with reg_vbus.
++ */
++&reg_drivevbus {
++	vin-supply = <&reg_usb_5v>;
++	status = "okay";
++};
++
+ &sgm3140 {
+ 	enable-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */
+ 	flash-gpios = <&pio 2 3 GPIO_ACTIVE_HIGH>; /* PC3 */
+ };
++
++&usbphy {
++	usb-role-switch;
++
++	port {
++		usb0_drd_sw: endpoint {
++			remote-endpoint = <&typec0_dr_sw>;
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
+index 4e7e237cb46a..40127186606f 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
+@@ -48,7 +48,67 @@ &mmc1 {
+ 	mmc-pwrseq = <&wifi_pwrseq>;
+ };
+ 
++&i2c0 {
++	hdmi-bridge@28 {
++		compatible = "analogix,anx7688";
++		reg = <0x28>;
++
++		interrupt-parent = <&r_pio>;
++		interrupts = <0 11 IRQ_TYPE_EDGE_FALLING>; /* PL11 */
++
++		enable-gpios = <&pio 3 10 GPIO_ACTIVE_LOW>; /* PD10 */
++		reset-gpios = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
++
++		cabledet-gpios = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */
++
++		avdd10-supply = <&reg_anx1v0>;
++		dvdd10-supply = <&reg_anx1v0>;
++		avdd18-supply = <&reg_ldo_io1>;
++		dvdd18-supply = <&reg_ldo_io1>;
++		avdd33-supply = <&reg_dcdc1>;
++		vconn-supply = <&reg_vconn5v0>;
++		hdmi_vt-supply = <&reg_dldo1>;
++
++		source-caps = <
++			PDO_FIXED(5000, 500, PDO_FIXED_DATA_SWAP | PDO_FIXED_USB_COMM | PDO_FIXED_DUAL_ROLE)
++		>;
++
++		sink-caps = <
++			PDO_FIXED(5000, 3000, PDO_FIXED_DATA_SWAP | PDO_FIXED_USB_COMM | PDO_FIXED_DUAL_ROLE)
++		>;
++
++		/*
++		 * ANX7688 will enable/disable USB-5V <-> DCIN switch by itself
++		 * via VBUS_CTRL pin. The driver just has to enable the USB-5V
++		 * so that the switch has power.
++		 */
++		vbus-supply = <&reg_usb_5v>;
++		vbus_in-supply = <&usb_power_supply>;
++
++		port {
++			typec0_dr_sw: endpoint {
++				remote-endpoint = <&usb0_drd_sw>;
++			};
++		};
++	};
++};
++
++&reg_anx1v0 {
++	gpio = <&pio 3 11 GPIO_ACTIVE_HIGH>; /* PD11 */
++	enable-active-high;
++};
++
+ &sgm3140 {
+ 	enable-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */
+ 	flash-gpios = <&pio 2 3 GPIO_ACTIVE_HIGH>; /* PC3 */
+ };
++
++&usbphy {
++	usb-role-switch;
++
++	port {
++		usb0_drd_sw: endpoint {
++			remote-endpoint = <&typec0_dr_sw>;
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index 5d55c6f82352..e8f6c016e1b3 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -10,6 +10,7 @@
+ #include <dt-bindings/input/input.h>
+ #include <dt-bindings/leds/common.h>
+ #include <dt-bindings/pwm/pwm.h>
++#include <dt-bindings/usb/pd.h>
+ 
+ / {
+ 	chassis-type = "handset";
+@@ -70,6 +71,24 @@ led2: led-2 {
+ 		};
+ 	};
+ 
++	hdmi-connector {
++		compatible = "hdmi-connector";
++		type = "a";
++
++		port {
++			hdmi_con_in: endpoint {
++				remote-endpoint = <&hdmi_out_con>;
++			};
++		};
++	};
++
++	reg_anx1v0: anx1v0 {
++		compatible = "regulator-fixed";
++		regulator-name = "anx1v0";
++		regulator-min-microvolt = <1000000>;
++		regulator-max-microvolt = <1000000>;
++	};
++
+ 	multi-led {
+ 		compatible = "leds-group-multicolor";
+ 		color = <LED_COLOR_ID_RGB>;
+@@ -85,6 +104,24 @@ reg_ps: ps-regulator {
+ 		regulator-boot-on;
+ 	};
+ 
++	reg_usb_5v: usb-5v {
++		compatible = "regulator-fixed";
++		regulator-name = "usb-5v";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		gpio = <&pio 3 8 GPIO_ACTIVE_HIGH>; /* PD8 */
++		enable-active-high;
++	};
++
++	reg_vbat_bb: vbat-bb {
++		compatible = "regulator-fixed";
++		regulator-name = "vbat-bb";
++		regulator-min-microvolt = <3500000>;
++		regulator-max-microvolt = <3500000>;
++		gpio = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */
++		enable-active-high;
++	};
++
+ 	reg_vbat_wifi: vbat-wifi {
+ 		compatible = "regulator-fixed";
+ 		regulator-min-microvolt = <3300000>;
+@@ -92,6 +129,16 @@ reg_vbat_wifi: vbat-wifi {
+ 		regulator-name = "vbat-wifi";
+ 	};
+ 
++	/* This is a charge pump for CC1 and CC2 pins on USB-C connector. */
++	reg_vconn5v0: vconn5v0 {
++		compatible = "regulator-fixed";
++		regulator-name = "vconn5v0";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		gpio = <&pio 3 9 GPIO_ACTIVE_HIGH>; /* PD9 */
++		enable-active-high;
++	};
++
+ 	sgm3140: led-controller {
+ 		compatible = "sgmicro,sgm3140";
+ 		vin-supply = <&reg_dcdc1>;
+@@ -207,6 +254,21 @@ &ehci1 {
+ 	status = "okay";
+ };
+ 
++&hdmi {
++	hvcc-supply = <&reg_dldo1>;
++	status = "okay";
++};
++
++&hdmi_out {
++	hdmi_out_con: endpoint {
++		remote-endpoint = <&hdmi_con_in>;
++	};
++};
++
++&sound_hdmi {
++	status = "okay";
++};
++
+ &i2c_csi {
+ 	gc2145: front-camera@3c {
+ 		compatible = "galaxycore,gc2145";
+@@ -330,6 +392,10 @@ &i2c2 {
+ 	status = "okay";
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &lradc {
+ 	vref-supply = <&reg_aldo3>;
+ 	wakeup-source;
+@@ -623,7 +689,7 @@ &uart3 {
+ };
+ 
+ &usb_otg {
+-	dr_mode = "peripheral";
++	dr_mode = "otg";
+ 	status = "okay";
+ };
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-detailed-OCV-to-capactiy-con.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-detailed-OCV-to-capactiy-con.patch
new file mode 100644
index 000000000000..69258e24228e
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-detailed-OCV-to-capactiy-con.patch
@@ -0,0 +1,187 @@
+From 382fca153620b6d38d36f13d093e524d301f8c44 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 28 Sep 2020 04:35:13 +0200
+Subject: arm64: dts: sun50i-a64-pinephone: Add detailed OCV to capactiy
+ conversion table
+
+This ensures that discharging stops at 3V, and that charging current
+limits are enforced. It also allows for more precise capacity reporting
+(on my device at the very least, at room temperature).
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../dts/allwinner/sun50i-a64-pinephone.dtsi   | 151 ++++++++++++++++++
+ 1 file changed, 151 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index e8f6c016e1b3..13213a3704a1 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -28,6 +28,156 @@ backlight: backlight {
+ 		/* Backlight configuration differs per PinePhone revision. */
+ 	};
+ 
++        bat: battery {
++                compatible = "simple-battery";
++                voltage-min-design-microvolt = <3000000>;
++                voltage-max-design-microvolt = <4350000>;
++                energy-full-design-microwatt-hours = <12000000>;
++                charge-full-design-microamp-hours = <2750000>;
++                precharge-current-microamp = <130000>;
++                charge-term-current-microamp = <50000>;
++                constant-charge-current-max-microamp = <1300000>;
++                constant-charge-voltage-max-microvolt = <4350000>;
++                factory-internal-resistance-micro-ohms = <150000>;
++                resistance-temp-table = <20 150>;
++                ocv-capacity-celsius = <20>;
++                ocv-capacity-table-0 =
++                	<4334000 100>,
++			<4319700 99>,
++			<4304300 98>,
++			<4292200 97>,
++			<4280100 96>,
++			<4269100 95>,
++			<4253700 94>,
++			<4242700 93>,
++			<4232800 92>,
++			<4222900 91>,
++			<4211900 90>,
++			<4203100 89>,
++			<4192100 88>,
++			<4177800 87>,
++			<4167900 86>,
++			<4155800 85>,
++			<4147000 84>,
++			<4136000 83>,
++			<4126100 82>,
++			<4111800 81>,
++			<4102999 80>,
++			<4093100 79>,
++			<4084300 78>,
++			<4075500 77>,
++			<4064500 76>,
++			<4054600 75>,
++			<4042500 74>,
++			<4035900 73>,
++			<4029300 72>,
++			<4018300 71>,
++			<4006200 70>,
++			<3993000 69>,
++			<3974300 68>,
++			<3964400 67>,
++			<3956700 66>,
++			<3949000 65>,
++			<3943500 64>,
++			<3938000 63>,
++			<3931400 62>,
++			<3923700 61>,
++			<3917100 60>,
++			<3903900 59>,
++			<3895100 58>,
++			<3887400 57>,
++			<3878600 56>,
++			<3870900 55>,
++			<3863200 54>,
++			<3855500 53>,
++			<3848900 52>,
++			<3837900 51>,
++			<3830200 50>,
++			<3825800 49>,
++			<3821400 48>,
++			<3815900 47>,
++			<3810400 46>,
++			<3806000 45>,
++			<3801600 44>,
++			<3797200 43>,
++			<3792800 42>,
++			<3789500 41>,
++			<3786200 40>,
++			<3781800 39>,
++			<3778500 38>,
++			<3775200 37>,
++			<3770800 36>,
++			<3764200 35>,
++			<3760900 34>,
++			<3758700 33>,
++			<3755400 32>,
++			<3754300 31>,
++			<3752100 30>,
++			<3748800 29>,
++			<3749900 28>,
++			<3745500 27>,
++			<3742200 26>,
++			<3741100 25>,
++			<3737800 24>,
++			<3734500 23>,
++			<3731200 22>,
++			<3730100 21>,
++			<3724600 20>,
++			<3722400 19>,
++			<3718000 18>,
++			<3713600 17>,
++			<3708100 16>,
++			<3701500 15>,
++			<3689400 14>,
++			<3682800 13>,
++			<3674000 12>,
++			<3666300 11>,
++			<3659700 10>,
++			<3653100 9>,
++			<3647600 8>,
++			<3641000 7>,
++			<3625600 6>,
++			<3613500 5>,
++			<3591500 4>,
++			<3554100 3>,
++			<3489200 2>,
++			<3393500 1>,
++			<3256000 0>;
++                x-powers,ocv-capacity-table =
++                	<0xc0 0>,
++			<0xc1 1>,
++			<0xc2 1>,
++			<0xc3 2>,
++			<0xc4 2>,
++			<0xc5 4>,
++			<0xc6 4>,
++			<0xc7 5>,
++			<0xc8 6>,
++			<0xc9 8>,
++			<0xca 11>,
++			<0xcb 15>,
++			<0xcc 22>,
++			<0xcd 36>,
++			<0xce 44>,
++			<0xcf 48>,
++			<0xd0 51>,
++			<0xd1 53>,
++			<0xd2 56>,
++			<0xd3 60>,
++			<0xd4 64>,
++			<0xd5 69>,
++			<0xd6 71>,
++			<0xd7 75>,
++			<0xd8 78>,
++			<0xd9 82>,
++			<0xda 84>,
++			<0xdb 85>,
++			<0xdc 88>,
++			<0xdd 92>,
++			<0xde 95>,
++			<0xdf 98>;
++        };
++
+ 	bt_sco_codec: bt-sco-codec {
+ 		#sound-dai-cells = <1>;
+ 		compatible = "linux,bt-sco";
+@@ -499,6 +649,7 @@ axp803: pmic@3a3 {
+ 
+ &battery_power_supply {
+ 	status = "okay";
++	monitored-battery = <&bat>;
+ };
+ 
+ &reg_aldo1 {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-front-back-cameras.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-front-back-cameras.patch
new file mode 100644
index 000000000000..b03ae63cddda
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-front-back-cameras.patch
@@ -0,0 +1,130 @@
+From 46c60d4ce1900101897221b32794922bee23855f Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Wed, 8 Apr 2020 14:13:08 +0200
+Subject: arm64: dts: sun50i-a64-pinephone: Add front/back cameras
+
+Pinephone has OV5640 back camera and GC2145 front camera. Add support
+for both.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../dts/allwinner/sun50i-a64-pinephone.dtsi   | 89 +++++++++++++++++++
+ 1 file changed, 89 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index 4bc6c1ef2cde..5d55c6f82352 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -36,6 +36,15 @@ chosen {
+ 		stdout-path = "serial0:115200n8";
+ 	};
+ 
++	i2c_csi: i2c-csi {
++		compatible = "i2c-gpio";
++		sda-gpios = <&pio 4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; /* PE13 */
++		scl-gpios = <&pio 4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; /* PE12 */
++		i2c-gpio,delay-us = <3>;
++		#address-cells = <1>;
++		#size-cells = <0>;
++	};
++
+ 	leds {
+ 		compatible = "gpio-leds";
+ 
+@@ -134,6 +143,36 @@ &cpu3 {
+ 	cpu-supply = <&reg_dcdc2>;
+ };
+ 
++&csi {
++	pinctrl-0 = <&csi_pins>, <&csi_mclk_pin>;
++	status = "okay";
++
++	port {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		csi_ov5640_ep: endpoint@0 {
++			reg = <0>;
++			remote-endpoint = <&ov5640_ep>;
++			bus-width = <8>;
++			hsync-active = <1>; /* Active high */
++			vsync-active = <0>; /* Active low */
++			data-active = <1>;  /* Active high */
++			pclk-sample = <1>;  /* Rising */
++		};
++
++		csi_gc2145_ep: endpoint@1 {
++			reg = <1>;
++			remote-endpoint = <&gc2145_ep>;
++			bus-width = <8>;
++			hsync-active = <1>;
++			vsync-active = <1>;
++			data-active = <1>;
++			pclk-sample = <1>;
++		};
++	};
++};
++
+ &dai {
+ 	status = "okay";
+ };
+@@ -168,6 +207,56 @@ &ehci1 {
+ 	status = "okay";
+ };
+ 
++&i2c_csi {
++	gc2145: front-camera@3c {
++		compatible = "galaxycore,gc2145";
++		reg = <0x3c>;
++		clocks = <&ccu CLK_CSI_MCLK>;
++		clock-names = "xclk";
++
++		AVDD-supply = <&reg_dldo3>;
++		DVDD-supply = <&reg_aldo1>;
++		IOVDD-supply = <&reg_eldo3>;
++		reset-gpios = <&pio 4 16 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; /* PE16 */
++		enable-gpios = <&pio 4 17 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; /* PE17 */
++
++		port {
++			gc2145_ep: endpoint {
++				remote-endpoint = <&csi_gc2145_ep>;
++				bus-width = <8>;
++				hsync-active = <1>;
++				vsync-active = <1>;
++				data-active = <1>;
++				pclk-sample = <1>;
++			};
++		};
++	};
++
++	ov5640: rear-camera@4c {
++		compatible = "ovti,ov5640";
++		reg = <0x4c>;
++		clocks = <&ccu CLK_CSI_MCLK>;
++		clock-names = "xclk";
++
++		AVDD-supply = <&reg_dldo3>;
++		DOVDD-supply = <&reg_aldo1>; /* shared with AFVCC */
++		DVDD-supply = <&reg_eldo3>;
++		reset-gpios = <&pio 3 3 (GPIO_ACTIVE_LOW | GPIO_OPEN_DRAIN)>; /* PD3 */
++		powerdown-gpios = <&pio 2 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; /* PC0 */
++
++		port {
++			ov5640_ep: endpoint {
++				remote-endpoint = <&csi_ov5640_ep>;
++				bus-width = <8>;
++				hsync-active = <1>; /* Active high */
++				vsync-active = <0>; /* Active low */
++				data-active = <1>;  /* Active high */
++				pclk-sample = <1>;  /* Rising */
++			};
++		};
++	};
++};
++
+ &i2c0 {
+ 	status = "okay";
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-interrupt-pin-for-WiFi.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-interrupt-pin-for-WiFi.patch
new file mode 100644
index 000000000000..df18e76de5a8
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-interrupt-pin-for-WiFi.patch
@@ -0,0 +1,26 @@
+From dd36dd39913b0dcbcd99b4d41492a5c436a056e3 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 17 Jan 2021 23:06:03 +0100
+Subject: arm64: dts: sun50i-a64-pinephone: Add interrupt pin for WiFi
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index c2746a21b021..3885a1fd3916 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -599,6 +599,8 @@ &mmc1 {
+ 
+ 	rtl8723cs: wifi@1 {
+ 		reg = <1>;
++		interrupt-parent = <&r_pio>;
++		interrupts = <0 3 IRQ_TYPE_EDGE_FALLING>; /* PL3 */
+ 	};
+ };
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-modem-power-manager.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-modem-power-manager.patch
new file mode 100644
index 000000000000..d188548db7a5
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-modem-power-manager.patch
@@ -0,0 +1,119 @@
+From 079113ffb649556d044400aa3d4ab176948c461a Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Wed, 8 Jul 2020 01:00:48 +0200
+Subject: arm64: dts: sun50i-a64-pinephone: Add modem power manager
+
+Pinephone has a EG25-G modem that needs a special powerup/powerdown
+sequence. Add a power manager to manage the modem power.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../allwinner/sun50i-a64-pinephone-1.0.dts    | 22 ++++++++++++++++++
+ .../allwinner/sun50i-a64-pinephone-1.1.dts    | 23 +++++++++++++++++++
+ .../allwinner/sun50i-a64-pinephone-1.2.dts    | 23 +++++++++++++++++++
+ 3 files changed, 68 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts
+index 498ae493d176..ff01e2be26e7 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts
+@@ -86,6 +86,28 @@ &reg_drivevbus {
+ 	status = "okay";
+ };
+ 
++&uart3 {
++	modem {
++		compatible = "quectel,eg25";
++		char-device-name = "modem-power";
++
++		power-supply = <&reg_vbat_bb>; /* PL7 */
++
++		enable-gpios = <&pio 7 8 GPIO_ACTIVE_LOW>; /* PH8 */
++		reset-gpios = <&pio 2 4 GPIO_ACTIVE_HIGH>; /* PC4 */
++		pwrkey-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
++
++		sleep-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
++		wakeup-gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2-RI */
++
++		cts-gpios = <&pio 3 5 GPIO_ACTIVE_HIGH>; /* PD5-CTS */
++		dtr-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6-DTR */
++		rts-gpios = <&pio 3 4 GPIO_ACTIVE_HIGH>; /* PD4-RTS */
++
++		quectel,qdai = "1,1,0,1,0,0,1,1";
++	};
++};
++
+ &usbphy {
+ 	usb-role-switch;
+ 
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
+index 73275308f484..93dc8512fe45 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
+@@ -114,6 +114,29 @@ &sgm3140 {
+ 	flash-gpios = <&pio 2 3 GPIO_ACTIVE_HIGH>; /* PC3 */
+ };
+ 
++&uart3 {
++	modem {
++		compatible = "quectel,eg25";
++		char-device-name = "modem-power";
++
++		power-supply = <&reg_vbat_bb>; /* PL7 */
++
++		enable-gpios = <&pio 7 8 GPIO_ACTIVE_LOW>; /* PH8 */
++		reset-gpios = <&pio 2 4 GPIO_ACTIVE_HIGH>; /* PC4 */
++		status-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
++		status-pwrkey-multiplexed; /* status acts as pwrkey */
++
++		sleep-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
++		wakeup-gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2-RI */
++
++		dtr-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6-DTR */
++		cts-gpios = <&pio 3 5 GPIO_ACTIVE_HIGH>; /* PD5-CTS */
++		rts-gpios = <&pio 3 4 GPIO_ACTIVE_HIGH>; /* PD4-RTS */
++
++		quectel,qdai = "1,1,0,1,0,0,1,1";
++	};
++};
++
+ &usbphy {
+ 	usb-role-switch;
+ 
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
+index 40127186606f..5e988230e6e4 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
+@@ -103,6 +103,29 @@ &sgm3140 {
+ 	flash-gpios = <&pio 2 3 GPIO_ACTIVE_HIGH>; /* PC3 */
+ };
+ 
++&uart3 {
++	modem {
++		compatible = "quectel,eg25";
++		char-device-name = "modem-power";
++
++		power-supply = <&reg_vbat_bb>; /* PL7 */
++
++		enable-gpios = <&pio 7 8 GPIO_ACTIVE_LOW>; /* PH8 */
++		reset-gpios = <&pio 2 4 GPIO_ACTIVE_HIGH>; /* PC4 */
++		status-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */
++		pwrkey-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
++
++		host-ready-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
++		wakeup-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6-RI */
++
++		dtr-gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2-DTR */
++		cts-gpios = <&pio 3 5 GPIO_ACTIVE_HIGH>; /* PD5-CTS */
++		rts-gpios = <&pio 3 4 GPIO_ACTIVE_HIGH>; /* PD4-RTS */
++
++		quectel,qdai = "1,1,0,1,0,0,1,1";
++	};
++};
++
+ &usbphy {
+ 	usb-role-switch;
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-power-supply-to-stk3311.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-power-supply-to-stk3311.patch
new file mode 100644
index 000000000000..cdf579e244c5
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-power-supply-to-stk3311.patch
@@ -0,0 +1,27 @@
+From 3aa8258da2bda4c6e5b18e223c6025fc77fd4bc5 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sat, 20 May 2023 16:58:11 +0200
+Subject: arm64: dts: sun50i-a64-pinephone: Add power supply to stk3311
+
+This makes the driver disable the supply during sleep.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index 7de884adadb1..7d02c43cef05 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -656,6 +656,7 @@ light-sensor@48 {
+ 		reg = <0x48>;
+ 		interrupt-parent = <&pio>;
+ 		interrupts = <1 0 IRQ_TYPE_EDGE_FALLING>; /* PB0 */
++		vdd-supply = <&reg_ldo_io0>;
+ 	};
+ 
+ 	/* Accelerometer/gyroscope */
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-reboot-mode-driver.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-reboot-mode-driver.patch
new file mode 100644
index 000000000000..a4763224e5cc
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-reboot-mode-driver.patch
@@ -0,0 +1,80 @@
+From 8cedae67577d6f1d1350e65571d6bfc6a5be9ffa Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 15 Feb 2021 17:45:13 +0100
+Subject: arm64: dts: sun50i-a64-pinephone: Add reboot mode driver
+
+With the latest p-boot (released 2021-02-15), you can reboot to
+a particular boot option or to the menu, to FEL, to eMMC bootloader,
+regardless of the user defined p-boot defaults.
+
+Call reboot with cmd of LINUX_REBOOT_CMD_RESTART2 and arg:
+
+- fel          Reboot to FEL
+- emmc-egon    Reboot with chainload of bootloader from eMMC
+- sd1-8        Reboot to SD bootfs option
+- emmc1-8      Reboot to eMMC bootfs option
+- menu         Reboot to p-boot menu
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../dts/allwinner/sun50i-a64-pinephone.dtsi   | 37 +++++++++++++++++++
+ 1 file changed, 37 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index 7d02c43cef05..aeb282eba4b5 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -423,6 +423,34 @@ sgm3140_flash: led {
+ 		};
+ 	};
+ 
++	/* PinePhone specific reboot modes for p-boot. */
++	reboot-mode {
++		compatible = "nvmem-reboot-mode";
++		nvmem-cells = <&reboot_mode>;
++		nvmem-cell-names = "reboot-mode";
++
++		mode-normal     = <0x0>;
++		mode-fel        = <0xb0010fe1>;
++		mode-emmc-egon  = <0xb001e33c>;
++		mode-sd1        = <0xb0010020>;
++		mode-sd2        = <0xb0010021>;
++		mode-sd3        = <0xb0010022>;
++		mode-sd4        = <0xb0010023>;
++		mode-sd5        = <0xb0010024>;
++		mode-sd6        = <0xb0010025>;
++		mode-sd7        = <0xb0010026>;
++		mode-sd8        = <0xb0010027>;
++		mode-emmc1      = <0xb0010000>;
++		mode-emmc2      = <0xb0010001>;
++		mode-emmc3      = <0xb0010002>;
++		mode-emmc4      = <0xb0010003>;
++		mode-emmc5      = <0xb0010004>;
++		mode-emmc6      = <0xb0010005>;
++		mode-emmc7      = <0xb0010006>;
++		mode-emmc8      = <0xb0010007>;
++		mode-menu       = <0xb00100ff>;
++	};
++
+ 	speaker_amp: audio-amplifier {
+ 		compatible = "simple-audio-amplifier";
+ 		enable-gpios = <&pio 2 7 GPIO_ACTIVE_HIGH>; /* PC7 */
+@@ -931,6 +959,15 @@ &reg_rtc_ldo {
+ 	regulator-name = "vcc-rtc";
+ };
+ 
++&rtc {
++	#address-cells = <1>;
++	#size-cells = <1>;
++
++	reboot_mode: reboot-mode@4 {
++		reg = <0x4 0x4>;
++	};
++};
++
+ &sound {
+ 	status = "okay";
+ 	simple-audio-card,name = "PinePhone";
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-supply-for-i2c-bus-to-anx768.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-supply-for-i2c-bus-to-anx768.patch
new file mode 100644
index 000000000000..040b4b6ec394
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-supply-for-i2c-bus-to-anx768.patch
@@ -0,0 +1,54 @@
+From 1e444bc655527644b0420e0da7a3b2b41b460f6e Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 18 Oct 2021 17:41:25 +0200
+Subject: arm64: dts: sun50i-a64-pinephone: Add supply for i2c bus to anx7688
+
+The bus power needs to be enabled for anx7688 to be able to communicate
+with the master.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts | 1 +
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts | 1 +
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts | 1 +
+ 3 files changed, 3 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts
+index 8f6ea6b06aa9..cfb9518e057f 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts
+@@ -43,6 +43,7 @@ hdmi-bridge@28 {
+ 		avdd18-supply = <&reg_ldo_io1>;
+ 		dvdd18-supply = <&reg_ldo_io1>;
+ 		avdd33-supply = <&reg_dldo1>;
++		i2c-supply = <&reg_ldo_io0>;
+ 		vconn-supply = <&reg_vconn5v0>;
+ 		hdmi_vt-supply = <&reg_dldo1>;
+ 
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
+index 63ceae07a0e0..35cb92e3b5f1 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
+@@ -52,6 +52,7 @@ hdmi-bridge@28 {
+ 		avdd18-supply = <&reg_ldo_io1>;
+ 		dvdd18-supply = <&reg_ldo_io1>;
+ 		avdd33-supply = <&reg_dldo1>;
++		i2c-supply = <&reg_ldo_io0>;
+ 		vconn-supply = <&reg_vconn5v0>;
+ 		hdmi_vt-supply = <&reg_dldo1>;
+ 
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
+index d28a23e98232..aeb5c69fe51d 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
+@@ -51,6 +51,7 @@ hdmi-bridge@28 {
+ 		avdd18-supply = <&reg_ldo_io1>;
+ 		dvdd18-supply = <&reg_ldo_io1>;
+ 		avdd33-supply = <&reg_dcdc1>;
++		i2c-supply = <&reg_ldo_io0>;
+ 		vconn-supply = <&reg_vconn5v0>;
+ 		hdmi_vt-supply = <&reg_dldo1>;
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Bluetooth-audio.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Bluetooth-audio.patch
new file mode 100644
index 000000000000..609274bd8cc8
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Bluetooth-audio.patch
@@ -0,0 +1,33 @@
+From 34e327e91d7aafc189e2be3c701ceeb9b2dbaacd Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Thu, 6 Feb 2020 23:49:27 -0600
+Subject: arm64: dts: sun50i-a64-pinephone: Add support for Bluetooth audio
+
+The PinePhone has a Bluetooth chip with its PCM interface connected to
+AIF3. Add the DAI link so headeset audio can be routed in hardware.
+
+Even though the link is mono, configuring the link for 2 slots is
+required for compatibility with AIF2, which uses a single 32-bit slot,
+and which shares its clock dividers with AIF3. Using equal clock
+frequencies allows the modem and headset to be used at the same time.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index 91312b0ab896..4f471e80dcd8 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -181,6 +181,7 @@ bat: battery {
+ 	bt_sco_codec: bt-sco-codec {
+ 		#sound-dai-cells = <1>;
+ 		compatible = "linux,bt-sco";
++		sound-name-prefix = "Bluetooth";
+ 	};
+ 
+ 	chosen {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Pinephone-1.2-be.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Pinephone-1.2-be.patch
new file mode 100644
index 000000000000..15cdb6639dcb
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Pinephone-1.2-be.patch
@@ -0,0 +1,54 @@
+From c2c2f67a5e65027ed1f142ad564fa0e170df47ca Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Thu, 10 Nov 2022 20:11:10 +0100
+Subject: arm64: dts: sun50i-a64-pinephone: Add support for Pinephone 1.2 beta
+
+Beta versions uses a different magnetometer chip.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/boot/dts/allwinner/Makefile        |  1 +
+ .../allwinner/sun50i-a64-pinephone-1.2b.dts   | 19 +++++++++++++++++++
+ 2 files changed, 20 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2b.dts
+
+diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
+index 00bed412ee31..9fd6b08ea528 100644
+--- a/arch/arm64/boot/dts/allwinner/Makefile
++++ b/arch/arm64/boot/dts/allwinner/Makefile
+@@ -12,6 +12,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinebook.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinephone-1.0.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinephone-1.1.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinephone-1.2.dtb
++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinephone-1.2b.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinetab.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pinetab-early-adopter.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-sopine-baseboard.dtb
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2b.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2b.dts
+new file mode 100644
+index 000000000000..f5ac2e9ca836
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2b.dts
+@@ -0,0 +1,19 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++// Copyright (C) 2020 Ondrej Jirman <megous@megous.com>
++
++/dts-v1/;
++
++#include "sun50i-a64-pinephone-1.2.dts"
++
++/ {
++	model = "Pine64 PinePhone (1.2b)";
++	compatible = "pine64,pinephone-1.2b", "pine64,pinephone", "allwinner,sun50i-a64";
++};
++
++&lis3mdl {
++	status = "disabled";
++};
++
++&af8133j {
++	status = "okay";
++};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Pinephone-keyboa.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Pinephone-keyboa.patch
new file mode 100644
index 000000000000..de5ffb1f7085
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Pinephone-keyboa.patch
@@ -0,0 +1,170 @@
+From 671ab9b320585350524ef5f6fdf3e1d3a47b2b15 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Fri, 21 Jan 2022 23:28:48 +0100
+Subject: arm64: dts: sun50i-a64-pinephone: Add support for Pinephone keyboard
+
+Pinephone keyboard can be used with Pinephone. Describe it in
+the device tree.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../dts/allwinner/sun50i-a64-pinephone.dtsi   | 136 ++++++++++++++++++
+ 1 file changed, 136 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index 97c2f5956ef5..0124635431d5 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -178,6 +178,122 @@ bat: battery {
+ 			<0xdf 98>;
+         };
+ 
++        ppkb_battery: keyboard-battery {
++                compatible = "simple-battery";
++                voltage-min-design-microvolt = <3000000>;
++                voltage-max-design-microvolt = <4200000>;
++                energy-full-design-microwatt-hours = <21000000>;
++                charge-full-design-microamp-hours = <6000000>;
++                precharge-current-microamp = <100000>;
++                charge-term-current-microamp = <50000>;
++                constant-charge-current-max-microamp = <2000000>;
++                constant-charge-voltage-max-microvolt = <4200000>;
++                factory-internal-resistance-micro-ohms = <120000>;
++                ocv-capacity-celsius = <20>;
++                ocv-capacity-table-0 =
++                	<4147328 100>,
++			<4132636 99>,
++			<4121720 98>,
++			<4110905 97>,
++			<4102063 96>,
++			<4092428 95>,
++			<4082371 94>,
++			<4074137 93>,
++			<4064172 92>,
++			<4056387 91>,
++			<4047198 90>,
++			<4038599 89>,
++			<4030933 88>,
++			<4021831 87>,
++			<4012613 86>,
++			<4003863 85>,
++			<3995132 84>,
++			<3986108 83>,
++			<3977434 82>,
++			<3967977 81>,
++			<3960286 80>,
++			<3951737 79>,
++			<3943518 78>,
++			<3935723 77>,
++			<3928692 76>,
++			<3920093 75>,
++			<3912676 74>,
++			<3905481 73>,
++			<3899881 72>,
++			<3892341 71>,
++			<3887140 70>,
++			<3880005 69>,
++			<3876060 68>,
++			<3869195 67>,
++			<3863234 66>,
++			<3857808 65>,
++			<3851464 64>,
++			<3846976 63>,
++			<3840724 62>,
++			<3835254 61>,
++			<3830946 60>,
++			<3826564 59>,
++			<3821275 58>,
++			<3817413 57>,
++			<3811941 56>,
++			<3808947 55>,
++			<3804959 54>,
++			<3800958 53>,
++			<3797447 52>,
++			<3794303 51>,
++			<3790341 50>,
++			<3787022 49>,
++			<3783436 48>,
++			<3779936 47>,
++			<3776176 46>,
++			<3772160 45>,
++			<3769348 44>,
++			<3766705 43>,
++			<3762481 42>,
++			<3760894 41>,
++			<3758396 40>,
++			<3755803 39>,
++			<3753543 38>,
++			<3749691 37>,
++			<3747026 36>,
++			<3743937 35>,
++			<3741872 34>,
++			<3738529 33>,
++			<3737528 32>,
++			<3734059 31>,
++			<3731586 30>,
++			<3728576 29>,
++			<3725939 28>,
++			<3721208 27>,
++			<3718239 26>,
++			<3713032 25>,
++			<3709785 24>,
++			<3704045 23>,
++			<3701203 22>,
++			<3695965 21>,
++			<3691074 20>,
++			<3684562 19>,
++			<3679140 18>,
++			<3670993 17>,
++			<3664243 16>,
++			<3655383 15>,
++			<3647666 14>,
++			<3642747 13>,
++			<3637775 12>,
++			<3632593 11>,
++			<3627120 10>,
++			<3620923 9>,
++			<3611465 8>,
++			<3597536 7>,
++			<3577366 6>,
++			<3545253 5>,
++			<3497377 4>,
++			<3430377 3>,
++			<3337780 2>,
++			<3183953 1>,
++			<3064061 0>;
++        };
++
+ 	bt_sco_codec: bt-sco-codec {
+ 		#sound-dai-cells = <1>;
+ 		compatible = "linux,bt-sco";
+@@ -550,6 +666,26 @@ accelerometer@68 {
+ /* Connected to pogo pins (external spring based pinheader for user addons) */
+ &i2c2 {
+ 	status = "okay";
++
++	ppkb: keyboard@15 {
++		compatible = "pine64,pinephone-keyboard";
++		reg = <0x15>;
++		interrupt-parent = <&r_pio>;
++		interrupts = <0 12 IRQ_TYPE_EDGE_FALLING>; /* PL12 */
++		vbat-supply = <&reg_usb_5v>;
++		wakeup-source;
++
++		i2c {
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			charger@75 {
++				compatible = "injoinic,ip5209";
++				reg = <0x75>;
++				monitored-battery = <&ppkb_battery>;
++			};
++		};
++	};
+ };
+ 
+ &i2s2 {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-modem-audio.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-modem-audio.patch
new file mode 100644
index 000000000000..dd64937752d1
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-modem-audio.patch
@@ -0,0 +1,71 @@
+From 2cf576727cd3f9434c1a9921d69ca2eb04273f3c Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Wed, 5 Feb 2020 23:14:27 -0600
+Subject: arm64: dts: sun50i-a64-pinephone: Add support for modem audio
+
+The PinePhone has a Quectel EG25-G modem (a variant of the EC25) with
+its PCM interface connected to AIF2. Add the DAI link so call audio can
+be routed in hardware.
+
+The modem supports two fixed sample rates, and one fixed word size, with
+a variable BCLK frequency. Use the minimum supported BCLK frequency,
+which corresponds to a slot width of 32 bits.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ .../dts/allwinner/sun50i-a64-pinephone.dtsi   | 25 ++++++++++++++++++-
+ 1 file changed, 24 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index 4f471e80dcd8..76e55a0e415a 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -188,6 +188,12 @@ chosen {
+ 		stdout-path = "serial0:115200n8";
+ 	};
+ 
++	ec25_codec: ec25-codec {
++		#sound-dai-cells = <1>;
++		compatible = "quectel,ec25";
++		sound-name-prefix = "Modem";
++	};
++
+ 	i2c_csi: i2c-csi {
+ 		compatible = "i2c-gpio";
+ 		sda-gpios = <&pio 4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; /* PE13 */
+@@ -316,7 +322,7 @@ vibrator {
+ 
+ &codec {
+ 	pinctrl-names = "default";
+-	pinctrl-0 = <&aif3_pins>;
++	pinctrl-0 = <&aif2_pins>, <&aif3_pins>;
+ 	status = "okay";
+ };
+ 
+@@ -799,6 +805,23 @@ &sound {
+ 			"Headset Microphone", "HBIAS",
+ 			"MIC2", "Headset Microphone";
+ 
++	simple-audio-card,dai-link@1 {
++		format = "dsp_a";
++		frame-master = <&link1_codec>;
++		bitclock-master = <&link1_codec>;
++		bitclock-inversion;
++
++		link1_cpu: cpu {
++			sound-dai = <&ec25_codec 0>;
++		};
++
++		link1_codec: codec {
++			sound-dai = <&codec 1>;
++			dai-tdm-slot-num = <1>;
++			dai-tdm-slot-width = <32>;
++		};
++	};
++
+ 	simple-audio-card,dai-link@2 {
+ 		format = "dsp_a";
+ 		frame-master = <&link2_codec>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Bump-I2C-frequency-to-400kHz.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Bump-I2C-frequency-to-400kHz.patch
new file mode 100644
index 000000000000..99992b00b3de
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Bump-I2C-frequency-to-400kHz.patch
@@ -0,0 +1,35 @@
+From 429717d518e8ab162336302782b040755e6f3d9f Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 30 Nov 2020 06:14:07 +0100
+Subject: arm64: dts: sun50i-a64-pinephone: Bump I2C frequency to 400kHz
+
+High speed. :)
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index 76e55a0e415a..c2746a21b021 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -478,6 +478,7 @@ ov5640_ep: endpoint {
+ 
+ &i2c0 {
+ 	status = "okay";
++	clock-frequency = <400000>;
+ 
+ 	touchscreen@5d {
+ 		compatible = "goodix,gt917s";
+@@ -495,6 +496,7 @@ touchscreen@5d {
+ 
+ &i2c1 {
+ 	status = "okay";
++	clock-frequency = <400000>;
+ 
+ 	/* Alternative magnetometer */
+ 	af8133j: magnetometer@1c {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Don-t-make-lradc-keys-a-wakeup-s.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Don-t-make-lradc-keys-a-wakeup-s.patch
new file mode 100644
index 000000000000..e9171c2d4cf2
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Don-t-make-lradc-keys-a-wakeup-s.patch
@@ -0,0 +1,29 @@
+From c5f3ddccace279a6885d01b7919e7dd5cdf21b3c Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 26 Apr 2021 01:31:27 +0200
+Subject: arm64: dts: sun50i-a64-pinephone: Don't make lradc keys a wakeup
+ source
+
+This allow the crust to reach lower suspend state.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index f3b1c0e5493f..97c2f5956ef5 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -558,7 +558,7 @@ &i2s2 {
+ 
+ &lradc {
+ 	vref-supply = <&reg_aldo3>;
+-	wakeup-source;
++//	wakeup-source;
+ 	status = "okay";
+ 
+ 	button-200 {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Enable-Pinephone-Keyboard-power-.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Enable-Pinephone-Keyboard-power-.patch
new file mode 100644
index 000000000000..ab4aab7719bf
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Enable-Pinephone-Keyboard-power-.patch
@@ -0,0 +1,34 @@
+From 88b3c983bfedc0ccceede32e6055320772a8c146 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sat, 16 Apr 2022 02:12:06 +0200
+Subject: arm64: dts: sun50i-a64-pinephone: Enable Pinephone Keyboard power
+ manager
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index 0124635431d5..7de884adadb1 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -434,6 +434,15 @@ vibrator {
+ 		enable-gpios = <&pio 3 2 GPIO_ACTIVE_HIGH>; /* PD2 */
+ 		vcc-supply = <&reg_dcdc1>;
+ 	};
++
++	keyboard-power {
++		compatible = "megi,pinephone-keyboard-power-manager";
++		phone-battery = "axp20x-battery";
++		phone-usb = "axp20x-usb";
++		kb-battery = "ip5xxx-battery";
++		kb-boost = "ip5xxx-boost";
++		kb-usb = "ip5xxx-usb";
++	};
+ };
+ 
+ &codec {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Enable-internal-HMIC-bias.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Enable-internal-HMIC-bias.patch
new file mode 100644
index 000000000000..3892e491d638
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Enable-internal-HMIC-bias.patch
@@ -0,0 +1,29 @@
+From b4a237d25b94da596769bf1669e8e8017a0d2145 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Wed, 23 Sep 2020 00:13:54 -0500
+Subject: arm64: dts: sun50i-a64-pinephone: Enable internal HMIC bias
+
+Revisions 1.0 and 1.1 of the PinePhone mainboard do not have an external
+resistor connecting HBIAS to MIC2. Enable the internal resistor to
+provide the appropriate mic bias.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts
+index ff01e2be26e7..8f6ea6b06aa9 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts
+@@ -126,3 +126,7 @@ &sgm3140 {
+ 	enable-gpios = <&pio 2 3 GPIO_ACTIVE_HIGH>; /* PC3 */
+ 	flash-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */
+ };
++
++&codec_analog {
++	allwinner,internal-bias-resistor;
++};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Fix-BH-modem-manager-behavior.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Fix-BH-modem-manager-behavior.patch
new file mode 100644
index 000000000000..5be69fc53c78
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Fix-BH-modem-manager-behavior.patch
@@ -0,0 +1,29 @@
+From 60ededfd0381c8c76a587daff8ca5dfe47195149 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Wed, 5 Aug 2020 11:19:01 +0200
+Subject: arm64: dts: sun50i-a64-pinephone: Fix BH modem manager behavior
+
+PP 1.1 has STATUS line multiplexed with POWER KEY, but reading it doesn't
+work reliably. Just treat 1.1 as if it was 1.0, and ignore the STATUS.
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
+index 93dc8512fe45..d67f31ef529e 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
+@@ -123,8 +123,8 @@ modem {
+ 
+ 		enable-gpios = <&pio 7 8 GPIO_ACTIVE_LOW>; /* PH8 */
+ 		reset-gpios = <&pio 2 4 GPIO_ACTIVE_HIGH>; /* PC4 */
+-		status-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
+-		status-pwrkey-multiplexed; /* status acts as pwrkey */
++		pwrkey-gpios = <&pio 1 3 GPIO_ACTIVE_HIGH>; /* PB3 */
++		//status-pwrkey-multiplexed; /* status acts as pwrkey */
+ 
+ 		sleep-gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
+ 		wakeup-gpios = <&pio 1 2 GPIO_ACTIVE_HIGH>; /* PB2-RI */
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Power-off-the-touch-controller-i.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Power-off-the-touch-controller-i.patch
new file mode 100644
index 000000000000..230dd5c3a569
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Power-off-the-touch-controller-i.patch
@@ -0,0 +1,28 @@
+From f495e5bfb6f5967b34cf61a8e9a0dfb91c0c726d Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 25 Apr 2021 03:17:39 +0200
+Subject: arm64: dts: sun50i-a64-pinephone: Power off the touch controller in
+ sleep
+
+Otherwise it stays on and consumes quite a bit of power.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index 3885a1fd3916..f3b1c0e5493f 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -491,6 +491,7 @@ touchscreen@5d {
+ 		VDDIO-supply = <&reg_ldo_io0>;
+ 		touchscreen-size-x = <720>;
+ 		touchscreen-size-y = <1440>;
++		poweroff-in-suspend;
+ 	};
+ };
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Set-minimum-backlight-duty-cycle.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Set-minimum-backlight-duty-cycle.patch
new file mode 100644
index 000000000000..cfcbee717a95
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Set-minimum-backlight-duty-cycle.patch
@@ -0,0 +1,73 @@
+From d7c78e25c6b1f65cbf3fdef64401a804f62392e1 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 7 Jun 2021 20:23:52 +0200
+Subject: arm64: dts: sun50i-a64-pinephone: Set minimum backlight duty cycle to
+ 10%
+
+Instead of creating our own table, use existing lth_brightness
+functionality in the pwm_bl driver.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../dts/allwinner/sun50i-a64-pinephone-1.1.dts  | 16 +---------------
+ .../dts/allwinner/sun50i-a64-pinephone-1.2.dts  | 17 +----------------
+ 2 files changed, 2 insertions(+), 31 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
+index d67f31ef529e..63ceae07a0e0 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
+@@ -26,21 +26,7 @@ &axp803 {
+ 
+ &backlight {
+ 	power-supply = <&reg_ldo_io0>;
+-	/*
+-	 * PWM backlight circuit on this PinePhone revision was changed since
+-	 * 1.0, and the lowest PWM duty cycle that doesn't lead to backlight
+-	 * being off is around 20%. Duty cycle for the lowest brightness level
+-	 * also varries quite a bit between individual boards, so the lowest
+-	 * value here was chosen as a safe default.
+-	 */
+-	brightness-levels = <
+-		774  793  814  842
+-		882  935  1003 1088
+-		1192 1316 1462 1633
+-		1830 2054 2309 2596
+-		2916 3271 3664 4096>;
+-	num-interpolated-steps = <50>;
+-	default-brightness-level = <400>;
++	lth-brightness = <10>;
+ };
+ 
+ &codec_analog {
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
+index 5e988230e6e4..d28a23e98232 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
+@@ -17,22 +17,7 @@ wifi_pwrseq: wifi-pwrseq {
+ 
+ &backlight {
+ 	power-supply = <&reg_ldo_io0>;
+-	/*
+-	 * PWM backlight circuit on this PinePhone revision was changed since 1.0,
+-	 * and the lowest PWM duty cycle that doesn't lead to backlight being off
+-	 * is around 10%. Duty cycle for the lowest brightness level also varries
+-	 * quite a bit between individual boards, so the lowest value here was
+-	 * chosen as a safe default.
+-	 */
+-	brightness-levels = <
+-		5000 5248 5506 5858 6345
+-		6987 7805 8823 10062 11543
+-		13287 15317 17654 20319 23336
+-		26724 30505 34702 39335 44427
+-		50000
+-	>;
+-	num-interpolated-steps = <50>;
+-	default-brightness-level = <500>;
++	lth-brightness = <10>;
+ };
+ 
+ &lis3mdl {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Shorten-post-power-on-delay-on-m.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Shorten-post-power-on-delay-on-m.patch
new file mode 100644
index 000000000000..59e3d658940b
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Shorten-post-power-on-delay-on-m.patch
@@ -0,0 +1,43 @@
+From 02f9ee2c698d1d2debe17d60569ebb7366280942 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Thu, 6 Feb 2020 04:58:32 +0100
+Subject: arm64: dts: sun50i-a64-pinephone: Shorten post-power-on-delay on mmcs
+
+These are not needed.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index 13213a3704a1..91312b0ab896 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -574,6 +574,7 @@ &mmc0 {
+ 	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ 	disable-wp;
+ 	bus-width = <4>;
++	post-power-on-delay-ms = <1>; /* power is already turned on by the bootloader */
+ 	status = "okay";
+ };
+ 
+@@ -584,6 +585,7 @@ &mmc1 {
+ 	vqmmc-supply = <&reg_dldo4>;
+ 	bus-width = <4>;
+ 	non-removable;
++	post-power-on-delay-ms = <1>; /* wifi power is always on */
+ 	status = "okay";
+ 
+ 	rtl8723cs: wifi@1 {
+@@ -599,6 +601,7 @@ &mmc2 {
+ 	bus-width = <8>;
+ 	non-removable;
+ 	cap-mmc-hw-reset;
++	post-power-on-delay-ms = <1>; /* power is already turned on by the bootloader */
+ 	status = "okay";
+ };
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Use-newer-jack-detection-impleme.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Use-newer-jack-detection-impleme.patch
new file mode 100644
index 000000000000..3a9127fe9ff0
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Use-newer-jack-detection-impleme.patch
@@ -0,0 +1,35 @@
+From 3eaa6aabbb8758f9309a73287cfaaf9005a6979e Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Fri, 23 Feb 2024 01:53:14 +0100
+Subject: arm64: dts: sun50i-a64-pinephone: Use newer jack detection
+ implementaion
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index aeb282eba4b5..e7e90e5baff4 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -476,6 +476,7 @@ keyboard-power {
+ &codec {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&aif2_pins>, <&aif3_pins>;
++	jack-type = "headset";
+ 	status = "okay";
+ };
+ 
+@@ -971,7 +972,7 @@ reboot_mode: reboot-mode@4 {
+ &sound {
+ 	status = "okay";
+ 	simple-audio-card,name = "PinePhone";
+-	simple-audio-card,aux-devs = <&codec_analog>, <&speaker_amp>;
++	simple-audio-card,aux-devs = <&codec_analog>, <&codec>, <&speaker_amp>;
+ 	simple-audio-card,widgets = "Microphone", "Headset Microphone",
+ 				    "Microphone", "Internal Microphone",
+ 				    "Headphone", "Headphone Jack",
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Workaround-broken-HDMI-HPD-signa.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Workaround-broken-HDMI-HPD-signa.patch
new file mode 100644
index 000000000000..bd2467741a5b
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinephone-Workaround-broken-HDMI-HPD-signa.patch
@@ -0,0 +1,84 @@
+From 5547207e11f604491659e71791488f00b010d3c9 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 26 Oct 2021 01:25:46 +0200
+Subject: arm64: dts: sun50i-a64-pinephone: Workaround broken HDMI HPD signal
+
+HDMI HPD signal from ANX7688 to SoC's HDMI PHY is wrongly level
+shifted and does not register most of the time at the SoC's input.
+
+We need to do the signalling in software. Link anx7688 to hdmi
+driver via extcon interface.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts | 6 +++++-
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts | 6 +++++-
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts | 6 +++++-
+ 3 files changed, 15 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts
+index cfb9518e057f..0530881d8401 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.0.dts
+@@ -25,7 +25,7 @@ &axp803 {
+ };
+ 
+ &i2c0 {
+-	hdmi-bridge@28 {
++	anx7688: hdmi-bridge@28 {
+ 		compatible = "analogix,anx7688";
+ 		reg = <0x28>;
+ 
+@@ -131,3 +131,7 @@ &sgm3140 {
+ &codec_analog {
+ 	allwinner,internal-bias-resistor;
+ };
++
++&hdmi {
++	extcon = <&anx7688 0>;
++};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
+index 35cb92e3b5f1..053e4add9973 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.1.dts
+@@ -34,7 +34,7 @@ &codec_analog {
+ };
+ 
+ &i2c0 {
+-	hdmi-bridge@28 {
++	anx7688: hdmi-bridge@28 {
+ 		compatible = "analogix,anx7688";
+ 		reg = <0x28>;
+ 
+@@ -133,3 +133,7 @@ usb0_drd_sw: endpoint {
+ 		};
+ 	};
+ };
++
++&hdmi {
++	extcon = <&anx7688 0>;
++};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
+index aeb5c69fe51d..c4e3547e02e9 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
+@@ -34,7 +34,7 @@ &mmc1 {
+ };
+ 
+ &i2c0 {
+-	hdmi-bridge@28 {
++	anx7688: hdmi-bridge@28 {
+ 		compatible = "analogix,anx7688";
+ 		reg = <0x28>;
+ 
+@@ -121,3 +121,7 @@ usb0_drd_sw: endpoint {
+ 		};
+ 	};
+ };
++
++&hdmi {
++	extcon = <&anx7688 0>;
++};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinetab-Add-accelerometer.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinetab-Add-accelerometer.patch
new file mode 100644
index 000000000000..910f70705df7
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinetab-Add-accelerometer.patch
@@ -0,0 +1,38 @@
+From b76c601b4f0f85265c2d33adf1c4642c6e050e2a Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sun, 18 Feb 2024 17:39:58 +0100
+Subject: arm64: dts: sun50i-a64-pinetab: Add accelerometer
+
+Add accelerometer. Patch picked up from here:
+
+https://github.com/dreemurrs-embedded/Pine64-Arch/blob/master/PKGBUILDS/pine64/linux-megi/pinetab-accelerometer.patch
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts | 10 +++++++++-
+ 1 file changed, 9 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
+index b7ab7d28914e..8c91ed7083d7 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
+@@ -237,7 +237,15 @@ &i2c0_pins {
+ &i2c1 {
+ 	status = "okay";
+ 
+-	/* TODO: add Bochs BMA223 accelerometer here */
++	bma223@18 {
++		compatible = "bosch,bma223", "bosch,bma222e";
++		reg = <0x18>;
++		interrupt-parent = <&pio>;
++		interrupts = <7 5 IRQ_TYPE_LEVEL_HIGH>; /* PH5 */
++		mount-matrix = "0", "-1", "0",
++			       "-1", "0", "0",
++			       "0", "0", "-1";
++	};
+ };
+ 
+ &lradc {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinetab-Name-sound-card-PineTab.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinetab-Name-sound-card-PineTab.patch
new file mode 100644
index 000000000000..4d98add63360
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinetab-Name-sound-card-PineTab.patch
@@ -0,0 +1,28 @@
+From c530886e537d311c5c8833f1c685ca457155e5fb Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sun, 18 Feb 2024 17:38:00 +0100
+Subject: arm64: dts: sun50i-a64-pinetab: Name sound card PineTab
+
+There's no upstream UCM for PineTab, yet. So I guess we can safely
+rename it. Pine64-Arch is using this name.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
+index 6056c965baf6..b7ab7d28914e 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
+@@ -475,6 +475,7 @@ hdmi_out_con: endpoint {
+ 
+ &sound {
+ 	status = "okay";
++	simple-audio-card,name = "PineTab";
+ 	simple-audio-card,aux-devs = <&codec_analog>, <&speaker_amp>;
+ 	simple-audio-card,widgets = "Microphone", "Internal Microphone Left",
+ 				    "Microphone", "Internal Microphone Right",
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinetab-enable-RTL8723CS-bluetooth.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinetab-enable-RTL8723CS-bluetooth.patch
new file mode 100644
index 000000000000..80701925b80d
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-a64-pinetab-enable-RTL8723CS-bluetooth.patch
@@ -0,0 +1,44 @@
+From ad81b4fe119c8d10e47fc7aa721f5505103176ea Mon Sep 17 00:00:00 2001
+From: Icenowy Zheng <icenowy@aosc.io>
+Date: Sun, 14 Apr 2019 23:46:47 +0800
+Subject: arm64: dts: sun50i-a64-pinetab: enable RTL8723CS bluetooth
+
+PineTab has a RTL8723CS Wi-Fi/BT combo chip on board, the bluetooth part
+of it communicates with A64 via UART, and the power of it is controlled
+with some GPIO at PL bank.
+
+Enable the bluetooth in the device tree.
+
+Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
+---
+ .../boot/dts/allwinner/sun50i-a64-pinetab.dts      | 14 ++++++++++++++
+ 1 file changed, 14 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
+index 8c91ed7083d7..419fe19b4a6f 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinetab.dts
+@@ -511,6 +511,20 @@ &uart0 {
+ 	status = "okay";
+ };
+ 
++&uart1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
++	status = "okay";
++
++	bluetooth {
++		compatible = "realtek,rtl8723cs-bt";
++		reset-gpios = <&r_pio 0 4 GPIO_ACTIVE_LOW>; /* PL4 */
++		device-wake-gpios = <&r_pio 0 5 GPIO_ACTIVE_LOW>; /* PL5 */
++		host-wake-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
++		firmware-postfix = "pinebook";
++	};
++};
++
+ &usb_otg {
+ 	dr_mode = "otg";
+ 	status = "okay";
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-h5-Add-missing-GPU-trip-point.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-h5-Add-missing-GPU-trip-point.patch
new file mode 100644
index 000000000000..a362ef8d9f1e
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-h5-Add-missing-GPU-trip-point.patch
@@ -0,0 +1,35 @@
+From c83ffe6aa547f78dc811a570dd78baf0c482a41f Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Mon, 13 Mar 2023 06:02:46 +0100
+Subject: arm64: dts: sun50i-h5: Add missing GPU trip point
+
+Without this, thermal sensor driver fails to probe.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
+index e02a3848003e..a6a2e2a19e75 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
+@@ -234,6 +234,15 @@ gpu-thermal {
+ 			polling-delay-passive = <0>;
+ 			polling-delay = <0>;
+ 			thermal-sensors = <&ths 1>;
++
++			trips {
++				gpu_crit: gpu-crit {
++					/* milliCelsius */
++					temperature = <110000>;
++					hysteresis = <2000>;
++					type = "critical";
++				};
++			};
+ 		};
+ 	};
+ };
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-h5-Use-my-own-more-aggressive-OPPs-on-H5.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-h5-Use-my-own-more-aggressive-OPPs-on-H5.patch
new file mode 100644
index 000000000000..5a85dedab8ff
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-dts-sun50i-h5-Use-my-own-more-aggressive-OPPs-on-H5.patch
@@ -0,0 +1,97 @@
+From a926b916c845808bcbfc976427be67d28c980a4c Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 17 Aug 2020 23:43:53 +0200
+Subject: arm64: dts: sun50i-h5: Use my own more aggressive OPPs on H5
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi | 44 +++++++++----------
+ 1 file changed, 22 insertions(+), 22 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi
+index 1afad8b437d7..a74463c8cc52 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-cpu-opp.dtsi
+@@ -6,57 +6,57 @@ cpu_opp_table: opp-table-cpu {
+ 		compatible = "operating-points-v2";
+ 		opp-shared;
+ 
+-		opp-408000000 {
+-			opp-hz = /bits/ 64 <408000000>;
+-			opp-microvolt = <1000000 1000000 1310000>;
++		opp-480000000 {
++			opp-hz = /bits/ 64 <480000000>;
++			opp-microvolt = <1040000 1040000 1300000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+ 		opp-648000000 {
+ 			opp-hz = /bits/ 64 <648000000>;
+-			opp-microvolt = <1040000 1040000 1310000>;
++			opp-microvolt = <1040000 1040000 1300000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+ 		opp-816000000 {
+ 			opp-hz = /bits/ 64 <816000000>;
+-			opp-microvolt = <1080000 1080000 1310000>;
+-			clock-latency-ns = <244144>; /* 8 32k periods */
+-		};
+-
+-		opp-912000000 {
+-			opp-hz = /bits/ 64 <912000000>;
+-			opp-microvolt = <1120000 1120000 1310000>;
++			opp-microvolt = <1100000 1100000 1300000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+ 		opp-960000000 {
+ 			opp-hz = /bits/ 64 <960000000>;
+-			opp-microvolt = <1160000 1160000 1310000>;
++			opp-microvolt = <1200000 1200000 1300000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+ 		opp-1008000000 {
+ 			opp-hz = /bits/ 64 <1008000000>;
+-			opp-microvolt = <1200000 1200000 1310000>;
++			opp-microvolt = <1200000 1200000 1300000>;
++			clock-latency-ns = <244144>; /* 8 32k periods */
++		};
++
++		opp-1104000000 {
++			opp-hz = /bits/ 64 <1104000000>;
++			opp-microvolt = <1320000 1320000 1320000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+-		opp-1056000000 {
+-			opp-hz = /bits/ 64 <1056000000>;
+-			opp-microvolt = <1240000 1240000 1310000>;
++		opp-1200000000 {
++			opp-hz = /bits/ 64 <1200000000>;
++			opp-microvolt = <1320000 1320000 1320000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+-		opp-1104000000 {
+-			opp-hz = /bits/ 64 <1104000000>;
+-			opp-microvolt = <1260000 1260000 1310000>;
++		opp-1296000000 {
++			opp-hz = /bits/ 64 <1296000000>;
++			opp-microvolt = <1340000 1340000 1340000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+-		opp-1152000000 {
+-			opp-hz = /bits/ 64 <1152000000>;
+-			opp-microvolt = <1300000 1300000 1310000>;
++		opp-1368000000 {
++			opp-hz = /bits/ 64 <1368000000>;
++			opp-microvolt = <1400000 1400000 1400000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 	};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-xor-Select-32regs-without-benchmark-to-speed-up-boot.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-xor-Select-32regs-without-benchmark-to-speed-up-boot.patch
new file mode 100644
index 000000000000..463464f782e4
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/arm64-xor-Select-32regs-without-benchmark-to-speed-up-boot.patch
@@ -0,0 +1,45 @@
+From b8f9f4c5427c44cc2c23c51687424d2dc5c25fcf Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Thu, 10 Sep 2020 21:38:28 +0200
+Subject: arm64: xor: Select 32regs without benchmark to speed up boot
+
+32regs is fastest on Cortex-A53.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm64/include/asm/xor.h | 14 ++++----------
+ 1 file changed, 4 insertions(+), 10 deletions(-)
+
+diff --git a/arch/arm64/include/asm/xor.h b/arch/arm64/include/asm/xor.h
+index befcd8a7abc9..e4487ddc76e1 100644
+--- a/arch/arm64/include/asm/xor.h
++++ b/arch/arm64/include/asm/xor.h
+@@ -57,21 +57,15 @@ xor_neon_5(unsigned long bytes, unsigned long * __restrict p1,
+ 	kernel_neon_end();
+ }
+ 
+-static struct xor_block_template xor_block_arm64 = {
++static struct xor_block_template xor_block_arm64 __maybe_unused = {
+ 	.name   = "arm64_neon",
+ 	.do_2   = xor_neon_2,
+ 	.do_3   = xor_neon_3,
+ 	.do_4   = xor_neon_4,
+ 	.do_5	= xor_neon_5
+ };
+-#undef XOR_TRY_TEMPLATES
+-#define XOR_TRY_TEMPLATES           \
+-	do {        \
+-		xor_speed(&xor_block_8regs);    \
+-		xor_speed(&xor_block_32regs);    \
+-		if (cpu_has_neon()) { \
+-			xor_speed(&xor_block_arm64);\
+-		} \
+-	} while (0)
++
++#define XOR_SELECT_TEMPLATE(x)	\
++	(&xor_block_32regs)
+ 
+ #endif /* ! CONFIG_KERNEL_MODE_NEON */
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/bluetooth-bcm-Restore-drive_rts_on_open-true-behavior-on-bcm207.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/bluetooth-bcm-Restore-drive_rts_on_open-true-behavior-on-bcm207.patch
new file mode 100644
index 000000000000..b458c52f426e
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/bluetooth-bcm-Restore-drive_rts_on_open-true-behavior-on-bcm207.patch
@@ -0,0 +1,35 @@
+From 23fcf552af5ba182cd53d5af326a73c86a351eae Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sun, 7 Aug 2022 14:28:16 +0200
+Subject: bluetooth: bcm: Restore drive_rts_on_open = true behavior on
+ bcm20702a1
+
+This is what it was on v5.5. It doesn't fix the UART issues though.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/bluetooth/hci_bcm.c | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/bluetooth/hci_bcm.c b/drivers/bluetooth/hci_bcm.c
+index 9684eb16059b..5447f409a701 100644
+--- a/drivers/bluetooth/hci_bcm.c
++++ b/drivers/bluetooth/hci_bcm.c
+@@ -1584,8 +1584,13 @@ static struct bcm_device_data cyw55572_device_data = {
+ 	.max_autobaud_speed = 921600,
+ };
+ 
++static struct bcm_device_data bcm20702a1_device_data = {
++	.drive_rts_on_open = true,
++	.no_early_set_baudrate = true,
++};
++
+ static const struct of_device_id bcm_bluetooth_of_match[] = {
+-	{ .compatible = "brcm,bcm20702a1" },
++	{ .compatible = "brcm,bcm20702a1", .data = &bcm20702a1_device_data },
+ 	{ .compatible = "brcm,bcm4329-bt" },
+ 	{ .compatible = "brcm,bcm4330-bt" },
+ 	{ .compatible = "brcm,bcm4334-bt" },
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/bluetooth-h5-Don-t-re-initialize-rtl8723cs-on-resume.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/bluetooth-h5-Don-t-re-initialize-rtl8723cs-on-resume.patch
new file mode 100644
index 000000000000..b880bf8ec8ea
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/bluetooth-h5-Don-t-re-initialize-rtl8723cs-on-resume.patch
@@ -0,0 +1,28 @@
+From dcd320fc4e24521978144b482cb01814b4f80c5e Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sun, 30 Apr 2023 18:12:17 +0200
+Subject: bluetooth: h5: Don't re-initialize rtl8723cs on resume
+
+The power is kept across during sleep, and this is not necessary.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/bluetooth/hci_h5.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/bluetooth/hci_h5.c b/drivers/bluetooth/hci_h5.c
+index c0436881a533..3f6955ce9b7c 100644
+--- a/drivers/bluetooth/hci_h5.c
++++ b/drivers/bluetooth/hci_h5.c
+@@ -1108,7 +1108,7 @@ static const struct of_device_id rtl_bluetooth_of_match[] = {
+ 	{ .compatible = "realtek,rtl8723bs-bt",
+ 	  .data = (const void *)&h5_data_rtl8723bs },
+ 	{ .compatible = "realtek,rtl8723cs-bt",
+-	  .data = (const void *)&h5_data_rtl8723bs },
++	  .data = (const void *)&h5_data_rtl8822cs },
+ 	{ .compatible = "realtek,rtl8723ds-bt",
+ 	  .data = (const void *)&h5_data_rtl8723bs },
+ #endif
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/clk-sunxi-ng-Don-t-use-CPU-PLL-gating-and-CPUX-reparenting-to-H.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/clk-sunxi-ng-Don-t-use-CPU-PLL-gating-and-CPUX-reparenting-to-H.patch
new file mode 100644
index 000000000000..03174314773a
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/clk-sunxi-ng-Don-t-use-CPU-PLL-gating-and-CPUX-reparenting-to-H.patch
@@ -0,0 +1,55 @@
+From c654921edfdbeca309621420e64ee5b014fc306b Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 10 Mar 2020 06:04:32 +0100
+Subject: clk: sunxi-ng: Don't use CPU PLL gating and CPUX reparenting to HOSC
+
+It's not necessary when not using dividers on CPU PLL, and it's
+causing cntvct jump backs on H3.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 21 ---------------------
+ 1 file changed, 21 deletions(-)
+
+diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+index 33254d63ecb5..9bd05a0488ff 100644
+--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
++++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+@@ -1029,20 +1029,6 @@ static const struct sunxi_ccu_desc sun50i_h5_ccu_desc = {
+ 	.num_resets	= ARRAY_SIZE(sun50i_h5_ccu_resets),
+ };
+ 
+-static struct ccu_pll_nb sun8i_h3_pll_cpu_nb = {
+-	.common	= &pll_cpux_clk.common,
+-	/* copy from pll_cpux_clk */
+-	.enable	= BIT(31),
+-	.lock	= BIT(28),
+-};
+-
+-static struct ccu_mux_nb sun8i_h3_cpu_nb = {
+-	.common		= &cpux_clk.common,
+-	.cm		= &cpux_clk.mux,
+-	.delay_us	= 1, /* > 8 clock cycles at 24 MHz */
+-	.bypass_index	= 1, /* index of 24 MHz oscillator */
+-};
+-
+ static int sun8i_h3_ccu_probe(struct platform_device *pdev)
+ {
+ 	const struct sunxi_ccu_desc *desc;
+@@ -1067,13 +1053,6 @@ static int sun8i_h3_ccu_probe(struct platform_device *pdev)
+ 	if (ret)
+ 		return ret;
+ 
+-	/* Gate then ungate PLL CPU after any rate changes */
+-	ccu_pll_notifier_register(&sun8i_h3_pll_cpu_nb);
+-
+-	/* Reparent CPU during PLL CPU rate changes */
+-	ccu_mux_notifier_register(pll_cpux_clk.common.hw.clk,
+-				  &sun8i_h3_cpu_nb);
+-
+ 	return 0;
+ }
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/clk-sunxi-ng-Export-CLK_DRAM-for-devfreq.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/clk-sunxi-ng-Export-CLK_DRAM-for-devfreq.patch
new file mode 100644
index 000000000000..434a324cca48
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/clk-sunxi-ng-Export-CLK_DRAM-for-devfreq.patch
@@ -0,0 +1,59 @@
+From c55cb745c5ad2b343487227c24d2961cc2aa7ec2 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 3 Apr 2021 17:14:49 -0500
+Subject: clk: sunxi-ng: Export CLK_DRAM for devfreq
+
+MBUS needs to reference the CLK_DRAM clock, as it is responsible for
+DRAM frequency scaling.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/clk/sunxi-ng/ccu-sun8i-a83t.h      | 4 ----
+ include/dt-bindings/clock/sun8i-a83t-ccu.h | 5 ++---
+ 2 files changed, 2 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.h b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.h
+index 40e575ba51d2..6c927bc75224 100644
+--- a/drivers/clk/sunxi-ng/ccu-sun8i-a83t.h
++++ b/drivers/clk/sunxi-ng/ccu-sun8i-a83t.h
+@@ -42,12 +42,8 @@
+ 
+ /* module and usb clocks exported */
+ 
+-#define CLK_DRAM		82
+-
+ /* dram gates and more module clocks exported */
+ 
+-#define CLK_MBUS		95
+-
+ /* more module clocks exported */
+ 
+ #define CLK_NUMBER		(CLK_GPU_HYD + 1)
+diff --git a/include/dt-bindings/clock/sun8i-a83t-ccu.h b/include/dt-bindings/clock/sun8i-a83t-ccu.h
+index 78af5085f630..affe1857eb54 100644
+--- a/include/dt-bindings/clock/sun8i-a83t-ccu.h
++++ b/include/dt-bindings/clock/sun8i-a83t-ccu.h
+@@ -116,10 +116,9 @@
+ #define CLK_USB_HSIC		79
+ #define CLK_USB_HSIC_12M	80
+ #define CLK_USB_OHCI0		81
+-
++#define CLK_DRAM		82
+ #define CLK_DRAM_VE		83
+ #define CLK_DRAM_CSI		84
+-
+ #define CLK_TCON0		85
+ #define CLK_TCON1		86
+ #define CLK_CSI_MISC		87
+@@ -130,7 +129,7 @@
+ #define CLK_AVS			92
+ #define CLK_HDMI		93
+ #define CLK_HDMI_SLOW		94
+-
++#define CLK_MBUS		95
+ #define CLK_MIPI_DSI0		96
+ #define CLK_MIPI_DSI1		97
+ #define CLK_GPU_CORE		98
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/clk-sunxi-ng-Mark-TWD-clocks-as-critical.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/clk-sunxi-ng-Mark-TWD-clocks-as-critical.patch
new file mode 100644
index 000000000000..460c13321565
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/clk-sunxi-ng-Mark-TWD-clocks-as-critical.patch
@@ -0,0 +1,56 @@
+From 9ba880cc4a8d1fcd989cb000c1679e9e596dba9b Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 28 May 2022 18:01:42 -0500
+Subject: clk: sunxi-ng: Mark TWD clocks as critical
+
+Secure world firmware depends on this clock, so it cannot be disabled.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c | 2 +-
+ drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c   | 2 +-
+ drivers/clk/sunxi-ng/ccu-sun8i-r.c       | 2 +-
+ 3 files changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c b/drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c
+index cb0f8d110c32..ed17dd627b8b 100644
+--- a/drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c
++++ b/drivers/clk/sunxi-ng/ccu-sun50i-a100-r.c
+@@ -91,7 +91,7 @@ static SUNXI_CCU_GATE_DATA(r_apb1_timer_clk, "r-apb1-timer", clk_parent_r_apb1,
+ 			   0x11c, BIT(0), 0);
+ 
+ static SUNXI_CCU_GATE_DATA(r_apb1_twd_clk, "r-apb1-twd", clk_parent_r_apb1,
+-			   0x12c, BIT(0), 0);
++			   0x12c, BIT(0), CLK_IS_CRITICAL);
+ 
+ static const char * const r_apb1_pwm_clk_parents[] = { "dcxo24M", "osc32k",
+ 						       "iosc" };
+diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
+index acb4e8b9b1ba..3d08d7f6642a 100644
+--- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
++++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
+@@ -85,7 +85,7 @@ static struct ccu_div r_apb2_clk = {
+ static SUNXI_CCU_GATE(r_apb1_timer_clk,	"r-apb1-timer",	"r-apb1",
+ 		      0x11c, BIT(0), 0);
+ static SUNXI_CCU_GATE(r_apb1_twd_clk,	"r-apb1-twd",	"r-apb1",
+-		      0x12c, BIT(0), 0);
++		      0x12c, BIT(0), CLK_IS_CRITICAL);
+ static SUNXI_CCU_GATE(r_apb1_pwm_clk,	"r-apb1-pwm",	"r-apb1",
+ 		      0x13c, BIT(0), 0);
+ static SUNXI_CCU_GATE(r_apb2_uart_clk,	"r-apb2-uart",	"r-apb2",
+diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-r.c b/drivers/clk/sunxi-ng/ccu-sun8i-r.c
+index 0e324344673b..98e7d98e6685 100644
+--- a/drivers/clk/sunxi-ng/ccu-sun8i-r.c
++++ b/drivers/clk/sunxi-ng/ccu-sun8i-r.c
+@@ -73,7 +73,7 @@ static SUNXI_CCU_GATE_HWS(apb0_uart_clk,	"apb0-uart",
+ static SUNXI_CCU_GATE_HWS(apb0_i2c_clk,		"apb0-i2c",
+ 			  apb0_gate_parent, 0x28, BIT(6), 0);
+ static SUNXI_CCU_GATE_HWS(apb0_twd_clk,		"apb0-twd",
+-			  apb0_gate_parent, 0x28, BIT(7), 0);
++			  apb0_gate_parent, 0x28, BIT(7), CLK_IS_CRITICAL);
+ 
+ static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M" };
+ static SUNXI_CCU_MP_WITH_MUX_GATE(ir_clk, "ir",
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/clk-sunxi-ng-Set-maximum-P-and-M-factors-to-1-for-H3-pll-cpux-c.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/clk-sunxi-ng-Set-maximum-P-and-M-factors-to-1-for-H3-pll-cpux-c.patch
new file mode 100644
index 000000000000..babc35eb87fa
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/clk-sunxi-ng-Set-maximum-P-and-M-factors-to-1-for-H3-pll-cpux-c.patch
@@ -0,0 +1,59 @@
+From 68e7e97e96211e3df8cc02638fcfe7081166ebbf Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Thu, 12 Jan 2017 16:34:57 +0100
+Subject: clk: sunxi-ng: Set maximum P and M factors to 1 for H3 pll-cpux clock
+
+When using M factor greater than 1 system is experiencing
+occasional lockups. P factor should only be used for clock
+speeds below 288MHz. We don't use such speeds in the mainline
+kernel.
+
+This change was verified to fix lockups with PLL stress
+tester available at https://xff.cz/git/arisc-firmware/.
+
+Note that M factor must not be used outside the kernel either,
+so for example u-boot needs a similar patch.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 24 +++++++++++++++---------
+ 1 file changed, 15 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+index 740c4c97331c..33254d63ecb5 100644
+--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
++++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+@@ -25,15 +25,21 @@
+ 
+ #include "ccu-sun8i-h3.h"
+ 
+-static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpux_clk, "pll-cpux",
+-				     "osc24M", 0x000,
+-				     8, 5,	/* N */
+-				     4, 2,	/* K */
+-				     0, 2,	/* M */
+-				     16, 2,	/* P */
+-				     BIT(31),	/* gate */
+-				     BIT(28),	/* lock */
+-				     CLK_SET_RATE_UNGATE);
++static struct ccu_nkmp pll_cpux_clk = {
++	.enable		= BIT(31),
++	.lock		= BIT(28),
++	.n		= _SUNXI_CCU_MULT(8, 5),
++	.k		= _SUNXI_CCU_MULT(4, 2),
++	.m		= _SUNXI_CCU_DIV_MAX(0, 2, 1),
++	.p		= _SUNXI_CCU_DIV_MAX(16, 2, 1),
++	.common		= {
++		.reg		= 0x000,
++		.hw.init	= CLK_HW_INIT("pll-cpux",
++					      "osc24M",
++					      &ccu_nkmp_ops,
++					      CLK_SET_RATE_UNGATE),
++	},
++};
+ 
+ /*
+  * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/clk-sunxi-ng-a64-Increase-PLL_AUDIO-base-frequency.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/clk-sunxi-ng-a64-Increase-PLL_AUDIO-base-frequency.patch
new file mode 100644
index 000000000000..917d49a293ae
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/clk-sunxi-ng-a64-Increase-PLL_AUDIO-base-frequency.patch
@@ -0,0 +1,87 @@
+From 6817daf7af44eaf118c68c12b617b62b9ecc510f Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 19 Jul 2020 17:10:15 -0500
+Subject: clk: sunxi-ng: a64: Increase PLL_AUDIO base frequency
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 41 +++++++++++++++++++++------
+ 1 file changed, 32 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+index ba1ad267f123..4b3068bdfdf2 100644
+--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
++++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+@@ -47,15 +47,35 @@ static struct ccu_nkmp pll_cpux_clk = {
+  * With sigma-delta modulation for fractional-N on the audio PLL,
+  * we have to use specific dividers. This means the variable divider
+  * can no longer be used, as the audio codec requests the exact clock
+- * rates we support through this mechanism. So we now hard code the
+- * variable divider to 1. This means the clock rates will no longer
+- * match the clock names.
++ * rates we support through this mechanism.
++ *
++ * For the audio codec to work correctly, pll-audio must be exactly
++ * 22579200 Hz or 24576000 Hz, and pll-audio-4x (1x the base) must be
++ * between 3x and 8x that frequency. For the SRC to work at 96 kHz,
++ * pll-audio-4x must be at least 6x pll-audio.
++ *
++ * For now, hard code the variable divider to 3.
+  */
+ #define SUN50I_A64_PLL_AUDIO_REG	0x008
++#define SUN50I_A64_PLL_AUDIO_BIAS_REG	0x224
+ 
+ static struct ccu_sdm_setting pll_audio_sdm_table[] = {
+-	{ .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
+-	{ .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
++	/* 24000000 * (  7 + 0x10d84 / 131072 ) /  8 / 1 - 22579200 == -6.9Hz */
++	{ .rate =  22579200, .pattern = 0xc0010d84, .m =  8, .n =  7 },
++	/* 24000000 * ( 14 + 0x0ac02 / 131072 ) / 14 / 1 - 24576000 == -2.5Hz */
++	{ .rate =  24576000, .pattern = 0xc000ac08, .m = 14, .n = 14 },
++	/* 24000000 * (  8 + 0x0ef35 / 131072 ) /  3 / 3 - 22579200 ==  3.3Hz */
++	{ .rate =  67737600, .pattern = 0xc000ef35, .m =  3, .n =  8 },
++	/* 24000000 * ( 15 + 0x0b852 / 131072 ) /  5 / 3 - 24576000 ==  1.0Hz */
++	{ .rate =  73728000, .pattern = 0xc000b852, .m =  5, .n = 15 },
++	/* 24000000 * (  7 + 0x10d84 / 131072 ) /  2 / 4 - 22579200 == -6.9Hz */
++	{ .rate =  90316800, .pattern = 0xc0010d84, .m =  2, .n =  7 },
++	/* 24000000 * ( 16 + 0x0c49c / 131072 ) /  4 / 4 - 24576000 ==  4.0Hz */
++	{ .rate =  98304000, .pattern = 0xc000c49c, .m =  4, .n = 16 },
++	/* 24000000 * (  5 + 0x14a23 / 131072 ) /  1 / 6 - 22579200 == -6.9Hz */
++	{ .rate = 135475200, .pattern = 0xc0014a23, .m =  1, .n =  5 },
++	/* 24000000 * ( 12 + 0x09375 / 131072 ) /  2 / 6 - 24576000 ==  4.0Hz */
++	{ .rate = 147456000, .pattern = 0xc0009375, .m =  2, .n = 12 },
+ };
+ 
+ static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
+@@ -610,10 +630,10 @@ static const struct clk_hw *clk_parent_pll_audio[] = {
+ 	&pll_audio_base_clk.common.hw
+ };
+ 
+-/* We hardcode the divider to 1 for now */
++/* We hardcode the divider to 3 for now */
+ static CLK_FIXED_FACTOR_HWS(pll_audio_clk, "pll-audio",
+ 			    clk_parent_pll_audio,
+-			    1, 1, CLK_SET_RATE_PARENT);
++			    3, 1, CLK_SET_RATE_PARENT);
+ static CLK_FIXED_FACTOR_HWS(pll_audio_2x_clk, "pll-audio-2x",
+ 			    clk_parent_pll_audio,
+ 			    2, 1, CLK_SET_RATE_PARENT);
+@@ -952,10 +972,13 @@ static int sun50i_a64_ccu_probe(struct platform_device *pdev)
+ 	if (IS_ERR(reg))
+ 		return PTR_ERR(reg);
+ 
+-	/* Force the PLL-Audio-1x divider to 1 */
++	/* Force the pll-audio variable divider to 3 */
+ 	val = readl(reg + SUN50I_A64_PLL_AUDIO_REG);
+ 	val &= ~GENMASK(19, 16);
+-	writel(val | (0 << 16), reg + SUN50I_A64_PLL_AUDIO_REG);
++	writel(val | (2 << 16), reg + SUN50I_A64_PLL_AUDIO_REG);
++
++	/* Decrease the PLL AUDIO bias current to reduce noise. */
++	writel(0x10040000, reg + SUN50I_A64_PLL_AUDIO_BIAS_REG);
+ 
+ 	writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/clk-sunxi-ng-sun50i-a64-Switch-parent-of-MIPI-DSI-to-periph0-1x.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/clk-sunxi-ng-sun50i-a64-Switch-parent-of-MIPI-DSI-to-periph0-1x.patch
new file mode 100644
index 000000000000..b7876a623520
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/clk-sunxi-ng-sun50i-a64-Switch-parent-of-MIPI-DSI-to-periph0-1x.patch
@@ -0,0 +1,48 @@
+From 99e1ff82c84ee35099cd1dade28df0c963fdbf20 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 14 Aug 2023 07:28:11 +0200
+Subject: clk: sunxi-ng: sun50i-a64: Switch parent of MIPI-DSI to periph0(1x)
+
+This makes video0(1x) clock less constrained, and improves compatibility
+with external monitors on Pinephone when using both internal display
+and HDMI output at once.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 11 ++++++++++-
+ 1 file changed, 10 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+index c8cdb342b1a0..e76a1c10f390 100644
+--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
++++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+@@ -962,6 +962,8 @@ static struct ccu_mux_nb sun50i_a64_cpu_nb = {
+ 	.bypass_index	= 1, /* index of 24 MHz oscillator */
+ };
+ 
++#define CCU_MIPI_DSI_CLK 0x168
++
+ static int sun50i_a64_ccu_probe(struct platform_device *pdev)
+ {
+ 	void __iomem *reg;
+@@ -981,9 +983,16 @@ static int sun50i_a64_ccu_probe(struct platform_device *pdev)
+ 	writel(0x10040000, reg + SUN50I_A64_PLL_AUDIO_BIAS_REG);
+ 
+ 	ret = of_property_read_u32_index(of_chosen, "p-boot,framebuffer-start", 0, &val);
+-	if (ret)
++	if (ret) {
+ 		writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);
+ 
++		/* Set MIPI-DSI clock parent to periph0(1x), so that video0(1x) is free to change. */
++		val = readl(reg + CCU_MIPI_DSI_CLK);
++		val &= 0x30f;
++		val |= (2 << 8) | ((4 - 1) << 0); /* M-1 */
++		writel(val, reg + CCU_MIPI_DSI_CLK);
++	}
++
+ 	ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun50i_a64_ccu_desc);
+ 	if (ret)
+ 		return ret;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/cpufreq-sun50i-Show-detected-CPU-bin-for-easier-debugging.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/cpufreq-sun50i-Show-detected-CPU-bin-for-easier-debugging.patch
new file mode 100644
index 000000000000..208baf6df17f
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/cpufreq-sun50i-Show-detected-CPU-bin-for-easier-debugging.patch
@@ -0,0 +1,29 @@
+From 2489a1cedce4d285ac0f18f5ff39ecb07e178f4a Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Thu, 31 Oct 2019 18:31:32 +0100
+Subject: cpufreq: sun50i: Show detected CPU bin, for easier debugging
+
+Useful for people running into crashes during boot, due to issues
+with OPP voltages.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/cpufreq/sun50i-cpufreq-nvmem.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/cpufreq/sun50i-cpufreq-nvmem.c b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
+index 47d6840b3489..8992d281a818 100644
+--- a/drivers/cpufreq/sun50i-cpufreq-nvmem.c
++++ b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
+@@ -262,6 +262,8 @@ static int sun50i_cpufreq_nvmem_probe(struct platform_device *pdev)
+ 	snprintf(name, sizeof(name), "speed%d", speed);
+ 	config.prop_name = name;
+ 
++	pr_info("Using CPU speed bin %s\n", name);
++
+ 	for_each_present_cpu(cpu) {
+ 		struct device *cpu_dev = get_cpu_device(cpu);
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/drm-bridge-dw-hdmi-Allow-to-accept-HPD-status-from-other-driver.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/drm-bridge-dw-hdmi-Allow-to-accept-HPD-status-from-other-driver.patch
new file mode 100644
index 000000000000..9296558e2357
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/drm-bridge-dw-hdmi-Allow-to-accept-HPD-status-from-other-driver.patch
@@ -0,0 +1,152 @@
+From 023860ddb7a0feb4e634ebcbdd53a1721663f512 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Fri, 1 Sep 2023 00:57:04 +0200
+Subject: drm: bridge: dw-hdmi: Allow to accept HPD status from other drivers
+
+This change allows other drivers to provide HPD status.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 63 +++++++++++++++++++++--
+ 1 file changed, 59 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+index 996733ed2c00..57b2ea9225ca 100644
+--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+@@ -9,6 +9,7 @@
+ #include <linux/clk.h>
+ #include <linux/delay.h>
+ #include <linux/err.h>
++#include <linux/extcon.h>
+ #include <linux/hdmi.h>
+ #include <linux/i2c.h>
+ #include <linux/irq.h>
+@@ -195,6 +196,8 @@ struct dw_hdmi {
+ 	hdmi_codec_plugged_cb plugged_cb;
+ 	struct device *codec_dev;
+ 	enum drm_connector_status last_connector_result;
++	struct extcon_dev *extcon;
++	struct notifier_block extcon_nb;
+ };
+ 
+ #define HDMI_IH_PHY_STAT0_RX_SENSE \
+@@ -1686,6 +1689,12 @@ static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data)
+ enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi,
+ 					       void *data)
+ {
++	if (hdmi->extcon) {
++		return extcon_get_state(hdmi->extcon, EXTCON_DISP_HDMI) > 0
++			? connector_status_connected
++			: connector_status_disconnected;
++	}
++
+ 	return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ?
+ 		connector_status_connected : connector_status_disconnected;
+ }
+@@ -1696,7 +1705,7 @@ void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data,
+ {
+ 	u8 old_mask = hdmi->phy_mask;
+ 
+-	if (force || disabled || !rxsense)
++	if (force || disabled || !rxsense || hdmi->extcon)
+ 		hdmi->phy_mask |= HDMI_PHY_RX_SENSE;
+ 	else
+ 		hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE;
+@@ -3128,7 +3137,7 @@ static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
+ 			status = connector_status_disconnected;
+ 	}
+ 
+-	if (status != connector_status_unknown) {
++	if (status != connector_status_unknown && !hdmi->extcon) {
+ 		dev_dbg(hdmi->dev, "EVENT=%s\n",
+ 			status == connector_status_connected ?
+ 			"plugin" : "plugout");
+@@ -3314,6 +3323,25 @@ bool dw_hdmi_bus_fmt_is_420(struct dw_hdmi *hdmi)
+ }
+ EXPORT_SYMBOL_GPL(dw_hdmi_bus_fmt_is_420);
+ 
++static int dw_hdmi_extcon_notifier(struct notifier_block *nb,
++				   unsigned long event, void *ptr)
++{
++	struct dw_hdmi *hdmi = container_of(nb, struct dw_hdmi, extcon_nb);
++
++	enum drm_connector_status status = dw_hdmi_phy_read_hpd(hdmi, NULL);
++
++	dev_info(hdmi->dev, "EVENT=%s\n",
++		 status == connector_status_connected ? "plugin" : "plugout");
++
++	if (hdmi->bridge.dev) {
++		//XXX: ???
++		drm_helper_hpd_irq_event(hdmi->bridge.dev);
++		drm_bridge_hpd_notify(&hdmi->bridge, status);
++	}
++
++	return NOTIFY_DONE;
++}
++
+ struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
+ 			      const struct dw_hdmi_plat_data *plat_data)
+ {
+@@ -3356,15 +3384,38 @@ struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
+ 	if (ret < 0)
+ 		return ERR_PTR(ret);
+ 
++	hdmi->extcon = extcon_get_edev_by_phandle(dev, 0);
++	if (IS_ERR(hdmi->extcon)) {
++		if (PTR_ERR(hdmi->extcon) == -ENODEV) {
++			hdmi->extcon = NULL;
++		} else {
++			if (PTR_ERR(hdmi->extcon) != -EPROBE_DEFER)
++				dev_err(dev, "Invalid or missing extcon\n");
++			return ERR_CAST(hdmi->extcon);
++		}
++	}
++
++	if (hdmi->extcon) {
++		/* don't register IRQ for native HPD */
++		hdmi->phy_mask = (u8)~(HDMI_PHY_RX_SENSE);
++
++		hdmi->extcon_nb.notifier_call = dw_hdmi_extcon_notifier;
++		ret = extcon_register_notifier_all(hdmi->extcon, &hdmi->extcon_nb);
++		if (ret < 0) {
++			dev_err(dev, "failed to register extcon notifier\n");
++			return ERR_PTR(ret);
++		}
++	}
++
+ 	ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0);
+ 	if (ddc_node) {
+ 		hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node);
+ 		of_node_put(ddc_node);
+ 		if (!hdmi->ddc) {
+ 			dev_dbg(hdmi->dev, "failed to read ddc node\n");
+-			return ERR_PTR(-EPROBE_DEFER);
++			ret = -EPROBE_DEFER;
++			goto err_extcon;
+ 		}
+-
+ 	} else {
+ 		dev_dbg(hdmi->dev, "no ddc property found\n");
+ 	}
+@@ -3583,6 +3634,8 @@ struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev,
+ 
+ err_res:
+ 	i2c_put_adapter(hdmi->ddc);
++err_extcon:
++	extcon_unregister_notifier_all(hdmi->extcon, &hdmi->extcon_nb);
+ 
+ 	return ERR_PTR(ret);
+ }
+@@ -3590,6 +3643,8 @@ EXPORT_SYMBOL_GPL(dw_hdmi_probe);
+ 
+ void dw_hdmi_remove(struct dw_hdmi *hdmi)
+ {
++	extcon_unregister_notifier_all(hdmi->extcon, &hdmi->extcon_nb);
++
+ 	drm_bridge_remove(&hdmi->bridge);
+ 
+ 	if (hdmi->audio && !IS_ERR(hdmi->audio))
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/drm-bridge-dw-hdmi-Report-HDMI-hotplug-events.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/drm-bridge-dw-hdmi-Report-HDMI-hotplug-events.patch
new file mode 100644
index 000000000000..1726442cb2f6
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/drm-bridge-dw-hdmi-Report-HDMI-hotplug-events.patch
@@ -0,0 +1,41 @@
+From d21528bf852f57845123c8d64bbd5dd5eba17e32 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Fri, 1 Sep 2023 00:59:08 +0200
+Subject: drm: bridge: dw-hdmi: Report HDMI hotplug events
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 10 ++++++++--
+ 1 file changed, 8 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+index 57b2ea9225ca..0f1582318119 100644
+--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
++++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+@@ -2455,7 +2455,13 @@ static enum drm_connector_status dw_hdmi_detect(struct dw_hdmi *hdmi)
+ 	enum drm_connector_status result;
+ 
+ 	result = hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data);
+-	hdmi->last_connector_result = result;
++
++	if (result != hdmi->last_connector_result) {
++		dev_info(hdmi->dev, "read_hpd result: %d", result);
++		handle_plugged_change(hdmi,
++				      result == connector_status_connected);
++		hdmi->last_connector_result = result;
++	}
+ 
+ 	return result;
+ }
+@@ -3138,7 +3144,7 @@ static irqreturn_t dw_hdmi_irq(int irq, void *dev_id)
+ 	}
+ 
+ 	if (status != connector_status_unknown && !hdmi->extcon) {
+-		dev_dbg(hdmi->dev, "EVENT=%s\n",
++		dev_info(hdmi->dev, "EVENT=%s\n",
+ 			status == connector_status_connected ?
+ 			"plugin" : "plugout");
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/drm-panel-st7703-Fix-xbd599-timings-to-make-refresh-rate-exactl.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/drm-panel-st7703-Fix-xbd599-timings-to-make-refresh-rate-exactl.patch
new file mode 100644
index 000000000000..19f4533d0705
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/drm-panel-st7703-Fix-xbd599-timings-to-make-refresh-rate-exactl.patch
@@ -0,0 +1,37 @@
+From 82f1ded9bc2c9cf4f9f3b541cdc8f2d6d42a6775 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Thu, 29 Oct 2020 04:55:40 +0100
+Subject: drm/panel: st7703: Fix xbd599 timings to make refresh rate exactly
+ 60.006Hz
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/gpu/drm/panel/panel-sitronix-st7703.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/panel/panel-sitronix-st7703.c b/drivers/gpu/drm/panel/panel-sitronix-st7703.c
+index 67e8e45498cb..6d3ad83be141 100644
+--- a/drivers/gpu/drm/panel/panel-sitronix-st7703.c
++++ b/drivers/gpu/drm/panel/panel-sitronix-st7703.c
+@@ -312,14 +312,14 @@ static void xbd599_init_sequence(struct mipi_dsi_multi_context *dsi_ctx)
+ 
+ static const struct drm_display_mode xbd599_mode = {
+ 	.hdisplay    = 720,
+-	.hsync_start = 720 + 40,
+-	.hsync_end   = 720 + 40 + 40,
+-	.htotal	     = 720 + 40 + 40 + 40,
++	.hsync_start = 720 + 30,
++	.hsync_end   = 720 + 30 + 28,
++	.htotal	     = 720 + 30 + 28 + 30,
+ 	.vdisplay    = 1440,
+ 	.vsync_start = 1440 + 18,
+ 	.vsync_end   = 1440 + 18 + 10,
+ 	.vtotal	     = 1440 + 18 + 10 + 17,
+-	.clock	     = 69000,
++	.clock	     = 72000,
+ 	.flags	     = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
+ 	.width_mm    = 68,
+ 	.height_mm   = 136,
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/drm-rockchip-Fix-panic-on-reboot-when-DRM-device-fails-to-bind.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/drm-rockchip-Fix-panic-on-reboot-when-DRM-device-fails-to-bind.patch
new file mode 100644
index 000000000000..8d819d939aee
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/drm-rockchip-Fix-panic-on-reboot-when-DRM-device-fails-to-bind.patch
@@ -0,0 +1,36 @@
+From 38f3ba49d792cecd9b89602c16a74caa99d2eded Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sat, 24 Sep 2022 21:54:23 +0200
+Subject: drm: rockchip: Fix panic on reboot when DRM device fails to bind
+
+When DRM device is freed, we need to clear the drvdata pointer, because
+it now points to invalid memory.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
+index 439edc165ff6..44ba21037f50 100644
+--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
++++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
+@@ -206,6 +206,7 @@ static int rockchip_drm_bind(struct device *dev)
+ 	component_unbind_all(dev, drm_dev);
+ err_free:
+ 	drm_dev_put(drm_dev);
++	dev_set_drvdata(dev, NULL);
+ 	return ret;
+ }
+ 
+@@ -222,6 +223,7 @@ static void rockchip_drm_unbind(struct device *dev)
+ 	rockchip_iommu_cleanup(drm_dev);
+ 
+ 	drm_dev_put(drm_dev);
++	dev_set_drvdata(dev, NULL);
+ }
+ 
+ DEFINE_DRM_GEM_FOPS(rockchip_drm_driver_fops);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/drm-rockchip-dw-mipi-dsi-rockchip-Fix-ISP1-PHY-initialization.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/drm-rockchip-dw-mipi-dsi-rockchip-Fix-ISP1-PHY-initialization.patch
new file mode 100644
index 000000000000..36690c04e34b
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/drm-rockchip-dw-mipi-dsi-rockchip-Fix-ISP1-PHY-initialization.patch
@@ -0,0 +1,35 @@
+From 7b4684d211e12e8afabc94d545078e3ad070d1be Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sun, 9 Jun 2024 14:30:12 +0200
+Subject: drm: rockchip: dw-mipi-dsi-rockchip: Fix ISP1 PHY initialization
+
+After suspend/resume cycle, ISP1 would stop receiving data.
+Re-initializing DPHY during PHY power on fixes the issue.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
+index 3398160ad75e..471851879947 100644
+--- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
++++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
+@@ -1245,6 +1245,14 @@ static int dw_mipi_dsi_dphy_power_on(struct phy *phy)
+ 		goto err_phy_cfg_clk;
+ 	}
+ 
++	if (dsi->cdata->dphy_rx_init) {
++		ret = dsi->cdata->dphy_rx_init(phy);
++		if (ret < 0) {
++			DRM_DEV_ERROR(dsi->dev, "hardware-specific phy init failed: %d\n", ret);
++			goto err_pwr_on;
++		}
++	}
++
+ 	/* do soc-variant specific init */
+ 	if (dsi->cdata->dphy_rx_power_on) {
+ 		ret = dsi->cdata->dphy_rx_power_on(phy);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/drm-sun4i-Implement-gamma-correction.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/drm-sun4i-Implement-gamma-correction.patch
new file mode 100644
index 000000000000..7dd2c2644fee
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/drm-sun4i-Implement-gamma-correction.patch
@@ -0,0 +1,131 @@
+From 8521d1baa2940c22c9eede1517ee7ff85738f751 Mon Sep 17 00:00:00 2001
+From: Vasily Khoruzhick <anarsoul@gmail.com>
+Date: Wed, 13 Mar 2019 19:50:17 -0700
+Subject: drm/sun4i: Implement gamma correction
+
+Add support for gamma corretion to sun4i TCON driver. Its LUT has 256
+entries and can be updated only when gamma correction is disabled.
+
+Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
+---
+ drivers/gpu/drm/sun4i/sun4i_crtc.c | 14 +++++++++++++
+ drivers/gpu/drm/sun4i/sun4i_tcon.c | 33 ++++++++++++++++++++++++++++++
+ drivers/gpu/drm/sun4i/sun4i_tcon.h | 12 ++++++++++-
+ 3 files changed, 58 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/sun4i/sun4i_crtc.c b/drivers/gpu/drm/sun4i/sun4i_crtc.c
+index 18e74047b0f5..a09944a49e89 100644
+--- a/drivers/gpu/drm/sun4i/sun4i_crtc.c
++++ b/drivers/gpu/drm/sun4i/sun4i_crtc.c
+@@ -103,6 +103,20 @@ static void sun4i_crtc_atomic_flush(struct drm_crtc *crtc,
+ 			drm_crtc_send_vblank_event(crtc, event);
+ 		spin_unlock_irq(&crtc->dev->event_lock);
+ 	}
++
++	if (crtc->state->color_mgmt_changed) {
++		if (crtc->state->gamma_lut) {
++			/* LUT can be only updated when gamma correction is
++			 * disabled
++			 */
++			sun4i_tcon_enable_gamma(scrtc->tcon, false);
++			sun4i_tcon_load_gamma_lut(scrtc->tcon,
++						  crtc->state->gamma_lut->data);
++			sun4i_tcon_enable_gamma(scrtc->tcon, true);
++		} else
++			sun4i_tcon_enable_gamma(scrtc->tcon, false);
++	}
++
+ }
+ 
+ static void sun4i_crtc_atomic_disable(struct drm_crtc *crtc,
+diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
+index fca95b76e258..ac6ad2ed1cc0 100644
+--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
++++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
+@@ -240,6 +240,34 @@ void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, bool enable)
+ }
+ EXPORT_SYMBOL(sun4i_tcon_enable_vblank);
+ 
++void sun4i_tcon_load_gamma_lut(struct sun4i_tcon *tcon,
++			       struct drm_color_lut *lut)
++{
++	int i;
++
++	for (i = 0; i < SUN4I_TCON_GAMMA_LUT_SIZE; i++) {
++		u32 r, g, b;
++
++		r = drm_color_lut_extract(lut[i].red, 8);
++		g = drm_color_lut_extract(lut[i].green, 8);
++		b = drm_color_lut_extract(lut[i].blue, 8);
++
++		regmap_write(tcon->regs, SUN4I_TCON_GAMMA_TABLE_REG + 4 * i,
++			     SUN4I_TCON_GAMMA_TABLE_R(r) |
++			     SUN4I_TCON_GAMMA_TABLE_G(g) |
++			     SUN4I_TCON_GAMMA_TABLE_B(b));
++	}
++}
++EXPORT_SYMBOL(sun4i_tcon_load_gamma_lut);
++
++void sun4i_tcon_enable_gamma(struct sun4i_tcon *tcon, bool enable)
++{
++	regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
++			   SUN4I_TCON_GCTL_GAMMA_ENABLE,
++			   enable ? SUN4I_TCON_GCTL_GAMMA_ENABLE : 0);
++}
++EXPORT_SYMBOL(sun4i_tcon_enable_gamma);
++
+ /*
+  * This function is a helper for TCON output muxing. The TCON output
+  * muxing control register in earlier SoCs (without the TCON TOP block)
+@@ -1288,6 +1316,11 @@ static int sun4i_tcon_bind(struct device *dev, struct device *master,
+ 
+ 	list_add_tail(&tcon->list, &drv->tcon_list);
+ 
++	drm_mode_crtc_set_gamma_size(&tcon->crtc->crtc,
++				     SUN4I_TCON_GAMMA_LUT_SIZE);
++	drm_crtc_enable_color_mgmt(&tcon->crtc->crtc, 0, false,
++				   tcon->crtc->crtc.gamma_size);
++
+ 	return 0;
+ 
+ err_free_dclk:
+diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/sun4i_tcon.h
+index fa23aa23fe4a..97df39db2a31 100644
+--- a/drivers/gpu/drm/sun4i/sun4i_tcon.h
++++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h
+@@ -19,6 +19,7 @@
+ 
+ #define SUN4I_TCON_GCTL_REG			0x0
+ #define SUN4I_TCON_GCTL_TCON_ENABLE			BIT(31)
++#define SUN4I_TCON_GCTL_GAMMA_ENABLE			BIT(30)
+ #define SUN4I_TCON_GCTL_IOMAP_MASK			BIT(0)
+ #define SUN4I_TCON_GCTL_IOMAP_TCON1			(1 << 0)
+ #define SUN4I_TCON_GCTL_IOMAP_TCON0			(0 << 0)
+@@ -229,7 +230,13 @@
+ #define SUN4I_TCON1_FILL_BEG2_REG		0x31c
+ #define SUN4I_TCON1_FILL_END2_REG		0x320
+ #define SUN4I_TCON1_FILL_DATA2_REG		0x324
+-#define SUN4I_TCON1_GAMMA_TABLE_REG		0x400
++
++#define SUN4I_TCON_GAMMA_TABLE_REG		0x400
++#define SUN4I_TCON_GAMMA_TABLE_B(x)		((x) & 0xff)
++#define SUN4I_TCON_GAMMA_TABLE_G(x)		(((x) & 0xff) << 8)
++#define SUN4I_TCON_GAMMA_TABLE_R(x)		(((x) & 0xff) << 16)
++
++#define SUN4I_TCON_GAMMA_LUT_SIZE		256
+ 
+ #define SUN4I_TCON_MAX_CHANNELS		2
+ 
+@@ -297,6 +304,9 @@ void sun4i_tcon_mode_set(struct sun4i_tcon *tcon,
+ 			 const struct drm_display_mode *mode);
+ void sun4i_tcon_set_status(struct sun4i_tcon *crtc,
+ 			   const struct drm_encoder *encoder, bool enable);
++void sun4i_tcon_load_gamma_lut(struct sun4i_tcon *tcon,
++			       struct drm_color_lut *lut);
++void sun4i_tcon_enable_gamma(struct sun4i_tcon *tcon, bool enable);
+ 
+ extern const struct of_device_id sun4i_tcon_of_table[];
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/drm-sun4i-Mark-one-of-the-UI-planes-as-a-cursor-one.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/drm-sun4i-Mark-one-of-the-UI-planes-as-a-cursor-one.patch
new file mode 100644
index 000000000000..e62940fcb452
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/drm-sun4i-Mark-one-of-the-UI-planes-as-a-cursor-one.patch
@@ -0,0 +1,73 @@
+From 44014e4f2d9fa752d0b04d8322582aad7dcbf249 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Mon, 31 Oct 2022 03:23:11 +0100
+Subject: drm/sun4i: Mark one of the UI planes as a cursor one
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/gpu/drm/sun4i/sun8i_mixer.c    | 7 ++++++-
+ drivers/gpu/drm/sun4i/sun8i_ui_layer.c | 7 ++-----
+ drivers/gpu/drm/sun4i/sun8i_ui_layer.h | 4 +++-
+ 3 files changed, 11 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
+index 8b41d33baa30..03dd180a4c31 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
++++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
+@@ -349,8 +349,13 @@ static struct drm_plane **sun8i_layers_init(struct drm_device *drm,
+ 
+ 	for (i = 0; i < mixer->cfg->ui_num; i++) {
+ 		struct sun8i_layer *layer;
++		enum drm_plane_type type = DRM_PLANE_TYPE_OVERLAY;
++		if (i == 0)
++			type = DRM_PLANE_TYPE_PRIMARY;
++		else if (i == (mixer->cfg->ui_num - 1))
++			type = DRM_PLANE_TYPE_CURSOR;
+ 
+-		layer = sun8i_ui_layer_init_one(drm, mixer, i);
++		layer = sun8i_ui_layer_init_one(drm, mixer, i, type);
+ 		if (IS_ERR(layer)) {
+ 			dev_err(drm->dev, "Couldn't initialize %s plane\n",
+ 				i ? "overlay" : "primary");
+diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
+index b90e5edef4e8..0349e8bdffd6 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
++++ b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
+@@ -277,9 +277,9 @@ static const uint64_t sun8i_layer_modifiers[] = {
+ 
+ struct sun8i_layer *sun8i_ui_layer_init_one(struct drm_device *drm,
+ 					    struct sun8i_mixer *mixer,
+-					    int index)
++					    int index,
++					    enum drm_plane_type type)
+ {
+-	enum drm_plane_type type = DRM_PLANE_TYPE_OVERLAY;
+ 	int channel = mixer->cfg->vi_num + index;
+ 	struct sun8i_layer *layer;
+ 	unsigned int plane_cnt;
+@@ -289,9 +289,6 @@ struct sun8i_layer *sun8i_ui_layer_init_one(struct drm_device *drm,
+ 	if (!layer)
+ 		return ERR_PTR(-ENOMEM);
+ 
+-	if (index == 0)
+-		type = DRM_PLANE_TYPE_PRIMARY;
+-
+ 	/* possible crtcs are set later */
+ 	ret = drm_universal_plane_init(drm, &layer->plane, 0,
+ 				       &sun8i_ui_layer_funcs,
+diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_layer.h b/drivers/gpu/drm/sun4i/sun8i_ui_layer.h
+index 83892f6ff211..d4530e9f64e0 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_ui_layer.h
++++ b/drivers/gpu/drm/sun4i/sun8i_ui_layer.h
+@@ -51,5 +51,7 @@ struct sun8i_layer;
+ 
+ struct sun8i_layer *sun8i_ui_layer_init_one(struct drm_device *drm,
+ 					    struct sun8i_mixer *mixer,
+-					    int index);
++					    int index,
++					    enum drm_plane_type type);
++
+ #endif /* _SUN8I_UI_LAYER_H_ */
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/drm-sun4i-Support-taking-over-display-pipeline-state-from-p-boo.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/drm-sun4i-Support-taking-over-display-pipeline-state-from-p-boo.patch
new file mode 100644
index 000000000000..54b9a2f969d1
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/drm-sun4i-Support-taking-over-display-pipeline-state-from-p-boo.patch
@@ -0,0 +1,547 @@
+From 0fcf6084c0e1482b81d3ee60db39b478fcd48798 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sun, 30 Apr 2023 18:19:16 +0200
+Subject: drm/sun4i: Support taking over display pipeline state from p-boot
+
+For perfect, flickerless and fast boot.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/clk/sunxi-ng/ccu-sun50i-a64.c         |  4 +-
+ drivers/gpu/drm/drm_fbdev_ttm.c               | 14 +++++
+ drivers/gpu/drm/panel/panel-sitronix-st7703.c | 17 ++++++
+ drivers/gpu/drm/sun4i/sun4i_tcon.c            | 23 ++++++++
+ drivers/gpu/drm/sun4i/sun4i_tcon.h            |  2 +
+ drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c        | 13 +++++
+ drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h        |  2 +
+ drivers/gpu/drm/sun4i/sun8i_mixer.c           | 52 +++++++++++++++++++
+ drivers/gpu/drm/sun4i/sun8i_mixer.h           |  3 ++
+ drivers/phy/allwinner/phy-sun6i-mipi-dphy.c   | 14 +++++
+ drivers/video/backlight/pwm_bl.c              | 25 ++++++++-
+ 11 files changed, 167 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+index 4b3068bdfdf2..c8cdb342b1a0 100644
+--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
++++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+@@ -980,7 +980,9 @@ static int sun50i_a64_ccu_probe(struct platform_device *pdev)
+ 	/* Decrease the PLL AUDIO bias current to reduce noise. */
+ 	writel(0x10040000, reg + SUN50I_A64_PLL_AUDIO_BIAS_REG);
+ 
+-	writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);
++	ret = of_property_read_u32_index(of_chosen, "p-boot,framebuffer-start", 0, &val);
++	if (ret)
++		writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);
+ 
+ 	ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun50i_a64_ccu_desc);
+ 	if (ret)
+diff --git a/drivers/gpu/drm/drm_fbdev_ttm.c b/drivers/gpu/drm/drm_fbdev_ttm.c
+index 73d35d59590c..f9d71d285e2f 100644
+--- a/drivers/gpu/drm/drm_fbdev_ttm.c
++++ b/drivers/gpu/drm/drm_fbdev_ttm.c
+@@ -179,6 +179,7 @@ int drm_fbdev_ttm_driver_fbdev_probe(struct drm_fb_helper *fb_helper,
+ 	struct fb_info *info;
+ 	size_t screen_size;
+ 	void *screen_buffer;
++	u32 fb_start;
+ 	u32 format;
+ 	int ret;
+ 
+@@ -228,6 +229,19 @@ int drm_fbdev_ttm_driver_fbdev_probe(struct drm_fb_helper *fb_helper,
+ 	if (ret)
+ 		goto err_drm_fb_helper_release_info;
+ 
++	ret = of_property_read_u32_index(of_chosen, "p-boot,framebuffer-start", 0, &fb_start);
++	if (ret == 0) {
++		// copy framebuffer contents from p-boot if reasonable
++		if (screen_size != 720 * 1440 * 4) {
++			drm_err(dev, "surface width(%d), height(%d) and bpp(%d) does not match p-boot requirements\n",
++				    sizes->surface_width, sizes->surface_height,
++				    sizes->surface_bpp);
++			return 0;
++		}
++
++		memcpy(screen_buffer, __va(fb_start), screen_size);
++	}
++
+ 	return 0;
+ 
+ err_drm_fb_helper_release_info:
+diff --git a/drivers/gpu/drm/panel/panel-sitronix-st7703.c b/drivers/gpu/drm/panel/panel-sitronix-st7703.c
+index 6d3ad83be141..8e359c9e0a09 100644
+--- a/drivers/gpu/drm/panel/panel-sitronix-st7703.c
++++ b/drivers/gpu/drm/panel/panel-sitronix-st7703.c
+@@ -62,6 +62,7 @@ struct st7703 {
+ 	struct dentry *debugfs;
+ 	const struct st7703_panel_desc *desc;
+ 	enum drm_panel_orientation orientation;
++	bool hw_preenabled;
+ };
+ 
+ struct st7703_panel_desc {
+@@ -679,6 +680,11 @@ static int st7703_enable(struct drm_panel *panel)
+ 	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
+ 	struct mipi_dsi_multi_context dsi_ctx = {.dsi = dsi};
+ 
++	if (ctx->hw_preenabled) {
++		ctx->hw_preenabled = false;
++		return 0;
++	}
++
+ 	ctx->desc->init_sequence(&dsi_ctx);
+ 
+ 	mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);
+@@ -726,8 +732,10 @@ static int st7703_prepare(struct drm_panel *panel)
+ 	struct st7703 *ctx = panel_to_st7703(panel);
+ 	int ret;
+ 
++	if (!ctx->hw_preenabled) {
+ 	dev_dbg(ctx->dev, "Resetting the panel\n");
+ 	gpiod_set_value_cansleep(ctx->reset_gpio, 1);
++	}
+ 
+ 	ret = regulator_enable(ctx->iovcc);
+ 	if (ret < 0) {
+@@ -743,10 +751,12 @@ static int st7703_prepare(struct drm_panel *panel)
+ 	}
+ 
+ 	/* Give power supplies time to stabilize before deasserting reset. */
++	if (!ctx->hw_preenabled) {
+ 	usleep_range(10000, 20000);
+ 
+ 	gpiod_set_value_cansleep(ctx->reset_gpio, 0);
+ 	usleep_range(15000, 20000);
++	}
+ 
+ 	return 0;
+ }
+@@ -844,12 +854,19 @@ static int st7703_probe(struct mipi_dsi_device *dsi)
+ {
+ 	struct device *dev = &dsi->dev;
+ 	struct st7703 *ctx;
++	u32 fb_start;
+ 	int ret;
+ 
+ 	ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
+ 	if (!ctx)
+ 		return -ENOMEM;
+ 
++	ret = of_property_read_u32_index(of_chosen, "p-boot,framebuffer-start", 0, &fb_start);
++	if (ret == 0) {
++		/* the display pipeline is already initialized by p-boot */
++		ctx->hw_preenabled = true;
++	}
++
+ 	ctx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
+ 	if (IS_ERR(ctx->reset_gpio))
+ 		return dev_err_probe(dev, PTR_ERR(ctx->reset_gpio), "Failed to get reset gpio\n");
+diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
+index ac6ad2ed1cc0..b36c1ea0948c 100644
+--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
++++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
+@@ -40,6 +40,8 @@
+ #include "sun8i_tcon_top.h"
+ #include "sunxi_engine.h"
+ 
++static bool hw_preconfigured;
++
+ static struct drm_connector *sun4i_tcon_get_connector(const struct drm_encoder *encoder)
+ {
+ 	struct drm_connector *connector;
+@@ -743,6 +745,13 @@ void sun4i_tcon_mode_set(struct sun4i_tcon *tcon,
+ 			 const struct drm_encoder *encoder,
+ 			 const struct drm_display_mode *mode)
+ {
++	if (tcon->hw_preconfigured) {
++		// avoid the first modeset
++		tcon->hw_preconfigured = false;
++		hw_preconfigured = false;
++		return;
++	}
++
+ 	switch (encoder->encoder_type) {
+ 	case DRM_MODE_ENCODER_DSI:
+ 		/* DSI is tied to special case of CPU interface */
+@@ -883,6 +892,7 @@ static int sun4i_tcon_init_regmap(struct device *dev,
+ 		return PTR_ERR(tcon->regs);
+ 	}
+ 
++	if (!tcon->hw_preconfigured) {
+ 	/* Make sure the TCON is disabled and all IRQs are off */
+ 	regmap_write(tcon->regs, SUN4I_TCON_GCTL_REG, 0);
+ 	regmap_write(tcon->regs, SUN4I_TCON_GINT0_REG, 0);
+@@ -891,6 +901,7 @@ static int sun4i_tcon_init_regmap(struct device *dev,
+ 	/* Disable IO lines and set them to tristate */
+ 	regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, ~0);
+ 	regmap_write(tcon->regs, SUN4I_TCON1_IO_TRI_REG, ~0);
++	}
+ 
+ 	return 0;
+ }
+@@ -1162,6 +1173,9 @@ static int sun4i_tcon_bind(struct device *dev, struct device *master,
+ 	tcon->dev = dev;
+ 	tcon->id = engine->id;
+ 	tcon->quirks = of_device_get_match_data(dev);
++	
++	if (tcon->id == 0)
++		tcon->hw_preconfigured = hw_preconfigured;
+ 
+ 	tcon->lcd_rst = devm_reset_control_get(dev, "lcd");
+ 	if (IS_ERR(tcon->lcd_rst)) {
+@@ -1183,12 +1197,14 @@ static int sun4i_tcon_bind(struct device *dev, struct device *master,
+ 		}
+ 	}
+ 
++	if (!tcon->hw_preconfigured) {
+ 	/* Make sure our TCON is reset */
+ 	ret = reset_control_reset(tcon->lcd_rst);
+ 	if (ret) {
+ 		dev_err(dev, "Couldn't deassert our reset line\n");
+ 		return ret;
+ 	}
++	}
+ 
+ 	if (tcon->quirks->supports_lvds) {
+ 		/*
+@@ -1352,8 +1368,15 @@ static int sun4i_tcon_probe(struct platform_device *pdev)
+ 	const struct sun4i_tcon_quirks *quirks;
+ 	struct drm_bridge *bridge;
+ 	struct drm_panel *panel;
++	u32 fb_start;
+ 	int ret;
+ 
++	ret = of_property_read_u32_index(of_chosen, "p-boot,framebuffer-start", 0, &fb_start);
++	if (ret == 0) {
++		/* the display pipeline is already initialized by p-boot */
++		hw_preconfigured = true;
++	}
++
+ 	quirks = of_device_get_match_data(&pdev->dev);
+ 
+ 	/* panels and bridges are present only on TCONs with channel 0 */
+diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/sun4i_tcon.h
+index 97df39db2a31..864d70b9d242 100644
+--- a/drivers/gpu/drm/sun4i/sun4i_tcon.h
++++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h
+@@ -293,6 +293,8 @@ struct sun4i_tcon {
+ 
+ 	/* TCON list management */
+ 	struct list_head		list;
++
++	bool hw_preconfigured;
+ };
+ 
+ struct drm_bridge *sun4i_tcon_find_bridge(struct device_node *node);
+diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
+index c35b70d83e53..3644db360a30 100644
+--- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
++++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c
+@@ -732,6 +732,7 @@ static void sun6i_dsi_encoder_enable(struct drm_encoder *encoder)
+ 	reset_control_deassert(dsi->reset);
+ 	clk_prepare_enable(dsi->mod_clk);
+ 
++	if (!dsi->hw_preconfigured) {
+ 	/*
+ 	 * Enable the DSI block.
+ 	 */
+@@ -758,6 +759,7 @@ static void sun6i_dsi_encoder_enable(struct drm_encoder *encoder)
+ 	sun6i_dsi_setup_inst_loop(dsi, mode);
+ 	sun6i_dsi_setup_format(dsi, mode);
+ 	sun6i_dsi_setup_timings(dsi, mode);
++	}
+ 
+ 	phy_init(dsi->dphy);
+ 
+@@ -787,11 +789,15 @@ static void sun6i_dsi_encoder_enable(struct drm_encoder *encoder)
+ 	if (dsi->panel)
+ 		drm_panel_enable(dsi->panel);
+ 
++	if (!dsi->hw_preconfigured) {
+ 	sun6i_dsi_start(dsi, DSI_START_HSC);
+ 
+ 	udelay(1000);
+ 
+ 	sun6i_dsi_start(dsi, DSI_START_HSD);
++	}
++
++	dsi->hw_preconfigured = false;
+ }
+ 
+ static void sun6i_dsi_encoder_disable(struct drm_encoder *encoder)
+@@ -1105,6 +1111,7 @@ static int sun6i_dsi_probe(struct platform_device *pdev)
+ 	struct device *dev = &pdev->dev;
+ 	struct sun6i_dsi *dsi;
+ 	void __iomem *base;
++	u32 fb_start;
+ 	int ret;
+ 
+ 	variant = device_get_match_data(dev);
+@@ -1120,6 +1127,12 @@ static int sun6i_dsi_probe(struct platform_device *pdev)
+ 	dsi->host.dev = dev;
+ 	dsi->variant = variant;
+ 
++	ret = of_property_read_u32_index(of_chosen, "p-boot,framebuffer-start", 0, &fb_start);
++	if (ret == 0) {
++		/* the display pipeline is already initialized by p-boot */
++		dsi->hw_preconfigured = true;
++	}
++
+ 	base = devm_platform_ioremap_resource(pdev, 0);
+ 	if (IS_ERR(base)) {
+ 		dev_err(dev, "Couldn't map the DSI encoder registers\n");
+diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h
+index f1ddefe0f554..958c2997ab43 100644
+--- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h
++++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.h
+@@ -38,6 +38,8 @@ struct sun6i_dsi {
+ 	struct drm_panel	*panel;
+ 
+ 	const struct sun6i_dsi_variant *variant;
++	
++	bool hw_preconfigured;
+ };
+ 
+ static inline struct sun6i_dsi *host_to_sun6i_dsi(struct mipi_dsi_host *host)
+diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
+index 03dd180a4c31..913490acee53 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
++++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
+@@ -24,6 +24,7 @@
+ #include <drm/drm_probe_helper.h>
+ 
+ #include "sun4i_drv.h"
++#include "sun4i_tcon.h"
+ #include "sun8i_mixer.h"
+ #include "sun8i_ui_layer.h"
+ #include "sun8i_vi_layer.h"
+@@ -34,6 +35,8 @@ struct de2_fmt_info {
+ 	u32	de2_fmt;
+ };
+ 
++static bool hw_preconfigured;
++
+ static const struct de2_fmt_info de2_formats[] = {
+ 	{
+ 		.drm_fmt = DRM_FORMAT_ARGB8888,
+@@ -278,6 +281,33 @@ static void sun8i_mixer_commit(struct sunxi_engine *engine,
+ 	struct drm_plane *plane;
+ 	u32 route = 0, pipe_en = 0;
+ 
++	if (mixer->hw_preconfigured && engine->id == 0) {
++		struct sun4i_tcon* tcon;
++		u32 val, saved, ret;
++
++		/*
++		 * This is the first commit, wait for vblank on tcon0 before continuing.
++		 */
++		list_for_each_entry(tcon, &mixer->drv->tcon_list, list) {
++			if (tcon->id == 0) {
++				regmap_read(tcon->regs, SUN4I_TCON_GINT0_REG, &saved);
++				saved &= 0xffff0000;
++
++				regmap_write(tcon->regs, SUN4I_TCON_GINT0_REG, 0);
++
++				ret = regmap_read_poll_timeout(tcon->regs, SUN4I_TCON_GINT0_REG, val,
++							 val & (SUN4I_TCON_GINT0_VBLANK_INT(0) |
++								SUN4I_TCON_GINT0_VBLANK_INT(1) |
++								SUN4I_TCON_GINT0_TCON0_TRI_FINISH_INT),
++							 100, 40000);
++
++				regmap_write(tcon->regs, SUN4I_TCON_GINT0_REG, saved);
++			}
++		}
++
++		mixer->hw_preconfigured = false;
++	}
++
+ 	DRM_DEBUG_DRIVER("Committing changes\n");
+ 
+ 	drm_for_each_plane(plane, state->dev) {
+@@ -461,6 +491,7 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,
+ 	dev_set_drvdata(dev, mixer);
+ 	mixer->engine.ops = &sun8i_engine_ops;
+ 	mixer->engine.node = dev->of_node;
++	mixer->drv = drv;
+ 
+ 	if (of_property_present(dev->of_node, "iommus")) {
+ 		/*
+@@ -485,6 +516,11 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,
+ 	 */
+ 	mixer->engine.id = sun8i_mixer_of_get_id(dev->of_node);
+ 
++	if (mixer->engine.id == 0) {
++		mixer->hw_preconfigured = hw_preconfigured;
++		hw_preconfigured = false;
++	}
++
+ 	mixer->cfg = of_device_get_match_data(dev);
+ 	if (!mixer->cfg)
+ 		return -EINVAL;
+@@ -532,8 +568,11 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,
+ 	 * reason for the mixer to be functional. Make sure it's the
+ 	 * case.
+ 	 */
++
++	if (!mixer->hw_preconfigured) {
+ 	if (mixer->cfg->mod_rate)
+ 		clk_set_rate(mixer->mod_clk, mixer->cfg->mod_rate);
++	}
+ 
+ 	clk_prepare_enable(mixer->mod_clk);
+ 
+@@ -541,6 +580,7 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,
+ 
+ 	base = sun8i_blender_base(mixer);
+ 
++	if (!mixer->hw_preconfigured) {
+ 	/* Reset registers and disable unused sub-engines */
+ 	if (mixer->cfg->is_de3) {
+ 		for (i = 0; i < DE3_MIXER_UNIT_SIZE; i += 4)
+@@ -572,6 +612,7 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,
+ 	/* Enable the mixer */
+ 	regmap_write(mixer->engine.regs, SUN8I_MIXER_GLOBAL_CTL,
+ 		     SUN8I_MIXER_GLOBAL_CTL_RT_EN);
++	} /* hw_preconfigured */
+ 
+ 	/* Set background color to black */
+ 	regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_BKCOLOR(base),
+@@ -592,8 +633,10 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,
+ 			     SUN8I_MIXER_BLEND_MODE(base, i),
+ 			     SUN8I_MIXER_BLEND_MODE_DEF);
+ 
++	if (!mixer->hw_preconfigured) {
+ 	regmap_update_bits(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base),
+ 			   SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK, 0);
++	}
+ 
+ 	return 0;
+ 
+@@ -623,6 +666,15 @@ static const struct component_ops sun8i_mixer_ops = {
+ 
+ static int sun8i_mixer_probe(struct platform_device *pdev)
+ {
++	int ret;
++	u32 fb_start;
++
++	ret = of_property_read_u32_index(of_chosen, "p-boot,framebuffer-start", 0, &fb_start);
++	if (ret == 0) {
++		/* the display pipeline is already initialized by p-boot */
++		hw_preconfigured = true;
++	}
++
+ 	return component_add(&pdev->dev, &sun8i_mixer_ops);
+ }
+ 
+diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h
+index d7898c9c9cc0..68e2741b0962 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_mixer.h
++++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h
+@@ -184,6 +184,9 @@ struct sun8i_mixer {
+ 
+ 	struct clk			*bus_clk;
+ 	struct clk			*mod_clk;
++
++	struct sun4i_drv		*drv;
++	bool				hw_preconfigured;
+ };
+ 
+ enum {
+diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
+index 36eab95271b2..a19a27cea860 100644
+--- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
++++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
+@@ -195,6 +195,8 @@ struct sun6i_dphy {
+ 
+ 	const struct sun6i_dphy_variant		*variant;
+ 	enum sun6i_dphy_direction		direction;
++
++	bool hw_preconfigured;
+ };
+ 
+ static int sun6i_dphy_init(struct phy *phy)
+@@ -226,6 +228,11 @@ static void sun6i_a31_mipi_dphy_tx_power_on(struct sun6i_dphy *dphy)
+ {
+ 	u8 lanes_mask = GENMASK(dphy->config.lanes - 1, 0);
+ 
++	if (dphy->hw_preconfigured) {
++		dphy->hw_preconfigured = false;
++		return;
++	}
++
+ 	regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG,
+ 		     SUN6I_DPHY_ANA0_REG_PWS |
+ 		     SUN6I_DPHY_ANA0_REG_DMPC |
+@@ -551,6 +558,7 @@ static int sun6i_dphy_probe(struct platform_device *pdev)
+ 	struct sun6i_dphy *dphy;
+ 	const char *direction;
+ 	void __iomem *regs;
++	u32 fb_start;
+ 	int ret;
+ 
+ 	dphy = devm_kzalloc(&pdev->dev, sizeof(*dphy), GFP_KERNEL);
+@@ -561,6 +569,12 @@ static int sun6i_dphy_probe(struct platform_device *pdev)
+ 	if (!dphy->variant)
+ 		return -EINVAL;
+ 
++	ret = of_property_read_u32_index(of_chosen, "p-boot,framebuffer-start", 0, &fb_start);
++	if (ret == 0) {
++		/* the display pipeline is already initialized by p-boot */
++		dphy->hw_preconfigured = true;
++	}
++
+ 	regs = devm_platform_ioremap_resource(pdev, 0);
+ 	if (IS_ERR(regs)) {
+ 		dev_err(&pdev->dev, "Couldn't map the DPHY encoder registers\n");
+diff --git a/drivers/video/backlight/pwm_bl.c b/drivers/video/backlight/pwm_bl.c
+index 237d3d3f3bb1..f7d9d8813d92 100644
+--- a/drivers/video/backlight/pwm_bl.c
++++ b/drivers/video/backlight/pwm_bl.c
+@@ -444,7 +444,7 @@ static int pwm_backlight_probe(struct platform_device *pdev)
+ 	struct backlight_properties props;
+ 	struct backlight_device *bl;
+ 	struct pwm_bl_data *pb;
+-	struct pwm_state state;
++	struct pwm_state state, state_real;
+ 	unsigned int i;
+ 	int ret;
+ 
+@@ -509,6 +509,11 @@ static int pwm_backlight_probe(struct platform_device *pdev)
+ 	/* Sync up PWM state. */
+ 	pwm_init_state(pb->pwm, &state);
+ 
++	/* Read real state, but only if the PWM is enabled. */
++	pwm_get_state(pb->pwm, &state_real);
++	if (state_real.enabled)
++		state = state_real;
++
+ 	/*
+ 	 * The DT case will set the pwm_period_ns field to 0 and store the
+ 	 * period, parsed from the DT, in the PWM device. For the non-DT case,
+@@ -601,6 +606,24 @@ static int pwm_backlight_probe(struct platform_device *pdev)
+ 
+ 	bl->props.brightness = data->dft_brightness;
+ 	bl->props.power = pwm_backlight_initial_power_state(pb);
++	if (bl->props.power == FB_BLANK_UNBLANK && pb->levels) {
++		u64 level;
++
++		/* If the backlight is already on, determine the default
++		 * brightness from PWM duty cycle instead of forcing
++		 * the brightness determined by the driver 
++		 */
++		pwm_get_state(pb->pwm, &state);
++		level = (u64)state.duty_cycle * pb->scale;
++		do_div(level, (u64)state.period);
++
++		for (i = 0; i <= data->max_brightness; i++) {
++			if (data->levels[i] > level) {
++				bl->props.brightness = i;
++				break;
++			}
++		}
++	}
+ 	backlight_update_status(bl);
+ 
+ 	platform_set_drvdata(pdev, bl);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/drm-sun4i-tcon-Support-keeping-dclk-rate-upon-ancestor-clock-ch.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/drm-sun4i-tcon-Support-keeping-dclk-rate-upon-ancestor-clock-ch.patch
new file mode 100644
index 000000000000..cbfa0952d5fa
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/drm-sun4i-tcon-Support-keeping-dclk-rate-upon-ancestor-clock-ch.patch
@@ -0,0 +1,179 @@
+From 47d49fbc4a674b45279c3dbc20ab911e3ea470fe Mon Sep 17 00:00:00 2001
+From: Frank Oltmanns <frank@oltmanns.dev>
+Date: Sun, 10 Mar 2024 14:32:29 +0100
+Subject: drm/sun4i: tcon: Support keeping dclk rate upon ancestor clock
+ changes
+
+Allow the dclk to reset its rate when a rate change is initiated from an
+ancestor clock. This makes it possible to no longer to get an exclusive
+lock. As a consequence, it is now possible to set new rates if
+necessary, e.g. when an external display is connected.
+
+The first user of this functionality is the A64 because PLL-VIDEO0 is an
+ancestor for both HDMI and TCON0. This allows to select an optimal rate
+for TCON0 as long as there is no external HDMI connection. Once a change
+in PLL-VIDEO0 is performed when an HDMI connection is established, TCON0
+can react gracefully and select an optimal rate based on this the new
+constraint.
+
+Signed-off-by: Frank Oltmanns <frank@oltmanns.dev>
+---
+ drivers/gpu/drm/sun4i/sun4i_tcon.c | 70 +++++++++++++++++++++++++++---
+ drivers/gpu/drm/sun4i/sun4i_tcon.h | 12 +++++
+ 2 files changed, 76 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
+index b36c1ea0948c..221df37406d8 100644
+--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
++++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
+@@ -110,9 +110,11 @@ static void sun4i_tcon_channel_set_status(struct sun4i_tcon *tcon, int channel,
+ 
+ 	if (enabled) {
+ 		clk_prepare_enable(clk);
+-		clk_rate_exclusive_get(clk);
++		if (!tcon->quirks->restores_rate)
++			clk_rate_exclusive_get(clk);
+ 	} else {
+-		clk_rate_exclusive_put(clk);
++		if (!tcon->quirks->restores_rate)
++			clk_rate_exclusive_put(clk);
+ 		clk_disable_unprepare(clk);
+ 	}
+ }
+@@ -373,6 +375,53 @@ static void sun4i_tcon0_mode_set_dithering(struct sun4i_tcon *tcon,
+ 	regmap_write(tcon->regs, SUN4I_TCON_FRM_CTL_REG, val);
+ }
+ 
++static void sun4i_rate_reset_notifier_delayed_update(struct work_struct *work)
++{
++	struct sun4i_rate_reset_nb *rate_reset = container_of(work, struct sun4i_rate_reset_nb,
++							    reset_rate_work.work);
++
++	clk_set_rate(rate_reset->target_clk, rate_reset->saved_rate);
++}
++
++static int sun4i_rate_reset_notifier_cb(struct notifier_block *nb,
++				      unsigned long event, void *data)
++{
++	struct sun4i_rate_reset_nb *rate_reset = to_sun4i_rate_reset_nb(nb);
++
++	if (event == POST_RATE_CHANGE)
++		mod_delayed_work(system_wq, &rate_reset->reset_rate_work, msecs_to_jiffies(100));
++
++	return NOTIFY_DONE;
++}
++
++static void sun4i_rate_reset_notifier_register(struct sun4i_rate_reset_nb *rate_reset_nb)
++{
++	if (rate_reset_nb->is_registered)
++		return;
++
++	rate_reset_nb->clk_nb.notifier_call = sun4i_rate_reset_notifier_cb;
++
++	INIT_DELAYED_WORK(&rate_reset_nb->reset_rate_work,
++			  sun4i_rate_reset_notifier_delayed_update);
++
++	if (!clk_notifier_register(rate_reset_nb->target_clk,
++				   &rate_reset_nb->clk_nb))
++		rate_reset_nb->is_registered = true;
++}
++
++static struct sun4i_rate_reset_nb tcon_rate_reset_tcon0_nb;
++
++static void sun4i_tcon0_set_dclk_rate(struct sun4i_tcon *tcon, unsigned long rate)
++{
++	clk_set_rate(tcon->dclk, rate);
++
++	if (tcon->quirks->restores_rate) {
++		tcon_rate_reset_tcon0_nb.target_clk = tcon->dclk;
++		tcon_rate_reset_tcon0_nb.saved_rate = rate;
++		sun4i_rate_reset_notifier_register(&tcon_rate_reset_tcon0_nb);
++	}
++}
++
+ static void sun4i_tcon0_mode_set_cpu(struct sun4i_tcon *tcon,
+ 				     const struct drm_encoder *encoder,
+ 				     const struct drm_display_mode *mode)
+@@ -390,8 +439,8 @@ static void sun4i_tcon0_mode_set_cpu(struct sun4i_tcon *tcon,
+ 	 */
+ 	tcon->dclk_min_div = SUN6I_DSI_TCON_DIV;
+ 	tcon->dclk_max_div = SUN6I_DSI_TCON_DIV;
+-	clk_set_rate(tcon->dclk, mode->crtc_clock * 1000 * (bpp / lanes)
+-						  / SUN6I_DSI_TCON_DIV);
++	sun4i_tcon0_set_dclk_rate(tcon, mode->crtc_clock * 1000 * (bpp / lanes)
++				  / SUN6I_DSI_TCON_DIV);
+ 
+ 	/* Set the resolution */
+ 	regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
+@@ -464,7 +513,7 @@ static void sun4i_tcon0_mode_set_lvds(struct sun4i_tcon *tcon,
+ 
+ 	tcon->dclk_min_div = 7;
+ 	tcon->dclk_max_div = 7;
+-	clk_set_rate(tcon->dclk, mode->crtc_clock * 1000);
++	sun4i_tcon0_set_dclk_rate(tcon, mode->crtc_clock * 1000);
+ 
+ 	/* Set the resolution */
+ 	regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
+@@ -548,7 +597,7 @@ static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon,
+ 
+ 	tcon->dclk_min_div = tcon->quirks->dclk_min_div;
+ 	tcon->dclk_max_div = 127;
+-	clk_set_rate(tcon->dclk, mode->crtc_clock * 1000);
++	sun4i_tcon0_set_dclk_rate(tcon, mode->crtc_clock * 1000);
+ 
+ 	/* Set the resolution */
+ 	regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
+@@ -1561,6 +1610,14 @@ static const struct sun4i_tcon_quirks sun8i_a33_quirks = {
+ 	.supports_lvds		= true,
+ };
+ 
++static const struct sun4i_tcon_quirks sun50i_a64_lcd_quirks = {
++	.supports_lvds		= true,
++	.has_channel_0		= true,
++	.restores_rate		= true,
++	.dclk_min_div		= 1,
++	.setup_lvds_phy		= sun6i_tcon_setup_lvds_phy,
++};
++
+ static const struct sun4i_tcon_quirks sun8i_a83t_lcd_quirks = {
+ 	.supports_lvds		= true,
+ 	.has_channel_0		= true,
+@@ -1619,6 +1676,7 @@ const struct of_device_id sun4i_tcon_of_table[] = {
+ 	{ .compatible = "allwinner,sun9i-a80-tcon-tv", .data = &sun9i_a80_tcon_tv_quirks },
+ 	{ .compatible = "allwinner,sun20i-d1-tcon-lcd", .data = &sun20i_d1_lcd_quirks },
+ 	{ .compatible = "allwinner,sun20i-d1-tcon-tv", .data = &sun8i_r40_tv_quirks },
++	{ .compatible = "allwinner,sun50i-a64-tcon-lcd", .data = &sun50i_a64_lcd_quirks },
+ 	{ }
+ };
+ MODULE_DEVICE_TABLE(of, sun4i_tcon_of_table);
+diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/sun4i_tcon.h
+index 864d70b9d242..729d64b78846 100644
+--- a/drivers/gpu/drm/sun4i/sun4i_tcon.h
++++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h
+@@ -250,6 +250,7 @@ struct sun4i_tcon_quirks {
+ 	bool    needs_edp_reset; /* a80 edp reset needed for tcon0 access */
+ 	bool	supports_lvds;   /* Does the TCON support an LVDS output? */
+ 	bool	polarity_in_ch0; /* some tcon1 channels have polarity bits in tcon0 pol register */
++	bool	restores_rate;   /* restores the initial rate when rate changes */
+ 	u8	dclk_min_div;	/* minimum divider for TCON0 DCLK */
+ 
+ 	/* callback to handle tcon muxing options */
+@@ -312,4 +313,15 @@ void sun4i_tcon_enable_gamma(struct sun4i_tcon *tcon, bool enable);
+ 
+ extern const struct of_device_id sun4i_tcon_of_table[];
+ 
++struct sun4i_rate_reset_nb {
++	struct notifier_block	clk_nb;
++	struct delayed_work	reset_rate_work;
++
++	struct clk		*target_clk;
++	unsigned long		saved_rate;
++	bool			is_registered;
++};
++
++#define to_sun4i_rate_reset_nb(_nb) container_of(_nb, struct sun4i_rate_reset_nb, clk_nb)
++
+ #endif /* __SUN4I_TCON_H__ */
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/dt-bindings-axp20x-adc-allow-to-use-TS-pin-as-GPADC.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/dt-bindings-axp20x-adc-allow-to-use-TS-pin-as-GPADC.patch
new file mode 100644
index 000000000000..d46437891848
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/dt-bindings-axp20x-adc-allow-to-use-TS-pin-as-GPADC.patch
@@ -0,0 +1,34 @@
+From 9d267992ddf49ed7c35fec49416bea500dd7efdf Mon Sep 17 00:00:00 2001
+From: Icenowy Zheng <icenowy@aosc.io>
+Date: Tue, 10 Sep 2019 12:02:23 +0800
+Subject: dt-bindings: axp20x-adc: allow to use TS pin as GPADC
+
+The AXP series PMICs allow to use the TS pin as GPADC rather than the
+battery temperature sensor.
+
+Add the property to enable this mode.
+
+Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
+---
+ .../devicetree/bindings/iio/adc/x-powers,axp209-adc.yaml     | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/iio/adc/x-powers,axp209-adc.yaml b/Documentation/devicetree/bindings/iio/adc/x-powers,axp209-adc.yaml
+index 1caa896fce82..46ed0cdd925e 100644
+--- a/Documentation/devicetree/bindings/iio/adc/x-powers,axp209-adc.yaml
++++ b/Documentation/devicetree/bindings/iio/adc/x-powers,axp209-adc.yaml
+@@ -73,6 +73,11 @@ properties:
+   "#io-channel-cells":
+     const: 1
+ 
++  x-powers,ts-as-gpadc:
++    description: |
++      Boolean. Defines whether the TS pin should be used
++      as GPADC rather than battery temperature sensor pin.
++
+ additionalProperties: false
+ 
+ examples:
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/dt-bindings-input-gpio-vibrator-Don-t-require-enable-gpios.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/dt-bindings-input-gpio-vibrator-Don-t-require-enable-gpios.patch
new file mode 100644
index 000000000000..f66383cc4291
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/dt-bindings-input-gpio-vibrator-Don-t-require-enable-gpios.patch
@@ -0,0 +1,35 @@
+From 02cd44cdcb83d7b3b4adb5908fa184cfb60a67e1 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 23 Feb 2020 00:00:00 +0100
+Subject: dt-bindings: input: gpio-vibrator: Don't require enable-gpios
+
+It is possible to turn the motor on/off just by enabling/disabling
+the vcc-supply. Change the binding to require either enable-gpios
+or vcc-supply or both.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ Documentation/devicetree/bindings/input/gpio-vibrator.yaml | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+diff --git a/Documentation/devicetree/bindings/input/gpio-vibrator.yaml b/Documentation/devicetree/bindings/input/gpio-vibrator.yaml
+index 2384465eaa19..082ac06471db 100644
+--- a/Documentation/devicetree/bindings/input/gpio-vibrator.yaml
++++ b/Documentation/devicetree/bindings/input/gpio-vibrator.yaml
+@@ -24,7 +24,12 @@ properties:
+ 
+ required:
+   - compatible
+-  - enable-gpios
++
++anyOf:
++  - required:
++    - enable-gpios
++  - required:
++    - vcc-supply
+ 
+ additionalProperties: false
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/dt-bindings-leds-Add-a-binding-for-AXP813-charger-led.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/dt-bindings-leds-Add-a-binding-for-AXP813-charger-led.patch
new file mode 100644
index 000000000000..6e92a412bedc
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/dt-bindings-leds-Add-a-binding-for-AXP813-charger-led.patch
@@ -0,0 +1,46 @@
+From 881c70e2d4624f2af93a7464c0b7471896b2cb9a Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 23 Feb 2020 13:40:15 +0100
+Subject: dt-bindings: leds: Add a binding for AXP813 charger led
+
+The AXP813 PMIC can control one LED. Add binding to represent the LED.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../devicetree/bindings/leds/leds-axp20x.yaml | 24 +++++++++++++++++++
+ 1 file changed, 24 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/leds/leds-axp20x.yaml
+
+diff --git a/Documentation/devicetree/bindings/leds/leds-axp20x.yaml b/Documentation/devicetree/bindings/leds/leds-axp20x.yaml
+new file mode 100644
+index 000000000000..110edae82204
+--- /dev/null
++++ b/Documentation/devicetree/bindings/leds/leds-axp20x.yaml
+@@ -0,0 +1,24 @@
++# SPDX-License-Identifier: GPL-2.0
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/leds/leds-axp20x.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: LED driver for AXP813 PMIC from X-Powers.
++
++maintainers:
++  - Ondrej Jirman <megi@xff.cz>
++
++description: |
++  This module is part of the AXP20x MFD device. For more details
++  see Documentation/devicetree/bindings/mfd/axp20x.txt.
++
++  The LED controller is represented as a sub-node of the PMIC node on
++  the device tree.
++
++properties:
++  compatible:
++    const: x-powers,axp813-charger-led
++
++required:
++  - compatible
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/dt-bindings-media-Add-bindings-for-Himax-HM5065-camera-sensor.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/dt-bindings-media-Add-bindings-for-Himax-HM5065-camera-sensor.patch
new file mode 100644
index 000000000000..3062996ef08c
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/dt-bindings-media-Add-bindings-for-Himax-HM5065-camera-sensor.patch
@@ -0,0 +1,71 @@
+From 3680411d51a3657965cf6226c91dca9e7b0140fc Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 30 Sep 2017 02:30:39 +0200
+Subject: dt-bindings: media: Add bindings for Himax HM5065 camera sensor
+
+HM5065 is 5MP CMOS sensor...
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../devicetree/bindings/media/i2c/hm5065.txt  | 49 +++++++++++++++++++
+ 1 file changed, 49 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/media/i2c/hm5065.txt
+
+diff --git a/Documentation/devicetree/bindings/media/i2c/hm5065.txt b/Documentation/devicetree/bindings/media/i2c/hm5065.txt
+new file mode 100644
+index 000000000000..92ba6cac0d2f
+--- /dev/null
++++ b/Documentation/devicetree/bindings/media/i2c/hm5065.txt
+@@ -0,0 +1,49 @@
++* Himax HM5065 CSI camera sensor
++
++Required Properties:
++- compatible: should be "himax,hm5065"
++- reg: I2C device address (0x1f)
++- clocks: reference to the external input clock for the sensor.
++- clock-names: should be "xclk".
++- IOVDD-supply: Digital I/O voltage supply, 2.8 volts
++- AVDD-supply: Analog voltage supply, 2.8 volts
++- DVDD-supply: Digital core voltage supply, 1.8 volts
++- AFVDD-supply: Auto focus voltage supply, 2.8 volts
++
++Optional Properties (one or both must be configured):
++- reset-gpios: reference to the GPIO connected to the reset pin, if any.
++	       This is an active low signal to the HM5065.
++- enable-gpios: reference to the GPIO connected to the CE pin,
++		if any. This is an active high signal to the HM5065.
++
++The device node must contain one 'port' child node for its digital output
++video port, in accordance with the video interface bindings defined in
++Documentation/devicetree/bindings/media/video-interfaces.txt.
++
++Example:
++
++&i2c1 {
++	hm5065: camera@1f {
++		compatible = "himax,hm5065";
++		reg = <0x1f>;
++		clocks = <&ccu CLK_CSI_MCLK>;
++		clock-names = "xclk";
++		IOVDD-supply = <&reg_dldo3>;
++		AVDD-supply = <&reg_dldo4>;
++		DVDD-supply = <&reg_eldo3>;
++		AFVDD-supply = <&reg_dldo3>;
++		reset-gpios = <&pio 4 18 GPIO_ACTIVE_LOW>; /* PE18 */
++		enable-gpios = <&pio 4 19 GPIO_ACTIVE_HIGH>; /* PE19 */
++
++		port {
++			hm5065_ep: endpoint {
++				remote-endpoint = <&csi0_hm5065_ep>;
++				bus-width = <8>;
++				hsync-active = <1>;
++				vsync-active = <1>;
++				data-active = <1>;
++				pclk-sample = <1>;
++			};
++		};
++	};
++};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/dt-bindings-mfd-Add-codec-related-properties-to-AC100-PMIC.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/dt-bindings-mfd-Add-codec-related-properties-to-AC100-PMIC.patch
new file mode 100644
index 000000000000..9c7b9fbfc62c
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/dt-bindings-mfd-Add-codec-related-properties-to-AC100-PMIC.patch
@@ -0,0 +1,84 @@
+From b1949039cf1e2d3d460e0ae3da77e6f51e3df3f0 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sat, 17 Feb 2024 02:01:49 +0100
+Subject: dt: bindings: mfd: Add codec related properties to AC100 PMIC
+
+This PMIC includes a co-packaged audio codec with analog and digital
+parts. Add additional properties that describe power supplies to
+the codec, and the node for analog part of the codec.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../bindings/mfd/x-powers,ac100.yaml          | 38 +++++++++++++++++++
+ 1 file changed, 38 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/mfd/x-powers,ac100.yaml b/Documentation/devicetree/bindings/mfd/x-powers,ac100.yaml
+index f3d8394b27e7..59ad898fbf85 100644
+--- a/Documentation/devicetree/bindings/mfd/x-powers,ac100.yaml
++++ b/Documentation/devicetree/bindings/mfd/x-powers,ac100.yaml
+@@ -34,11 +34,39 @@ properties:
+         description: >
+           Name of the 4M_adda clock exposed by the codec
+ 
++      "#sound-dai-cells":
++        const: 1
++
++      LDOIN-supply: true
++      AVCC-supply: true
++      VDDIO1-supply: true
++      VDDIO2-supply: true
++
+     required:
+       - "#clock-cells"
+       - compatible
+       - interrupts
+       - clock-output-names
++      - "#sound-dai-cells"
++      - LDOIN-supply
++      - AVCC-supply
++      - VDDIO1-supply
++      - VDDIO2-supply
++
++    additionalProperties: false
++
++  codec-analog:
++    type: object
++
++    properties:
++      compatible:
++        const: x-powers,ac100-codec-analog
++
++      CPVDD-supply: true
++
++    required:
++      - compatible
++      - CPVDD-supply
+ 
+     additionalProperties: false
+ 
+@@ -94,12 +122,22 @@ examples:
+             compatible = "x-powers,ac100";
+             reg = <0xe89>;
+ 
++            ac100_codec_analog: codec-analog {
++                compatible = "x-powers,ac100-codec-analog";
++                CPVDD-supply = <&reg_aldo2>;
++            };
++
+             ac100_codec: codec {
++                #sound-dai-cells = <1>;
+                 compatible = "x-powers,ac100-codec";
+                 interrupt-parent = <&r_pio>;
+                 interrupts = <0 9 IRQ_TYPE_LEVEL_LOW>; /* PL9 */
+                 #clock-cells = <0>;
+                 clock-output-names = "4M_adda";
++                LDOIN-supply = <&reg_aldo2>;
++                AVCC-supply = <&reg_aldo3>;
++                VDDIO1-supply = <&reg_dcdc1>;
++                VDDIO2-supply = <&reg_dldo1>;
+             };
+ 
+             ac100_rtc: rtc {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/dt-bindings-sound-Add-jack-type-property-to-sun8i-a33-codec.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/dt-bindings-sound-Add-jack-type-property-to-sun8i-a33-codec.patch
new file mode 100644
index 000000000000..62246f6e3fdd
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/dt-bindings-sound-Add-jack-type-property-to-sun8i-a33-codec.patch
@@ -0,0 +1,36 @@
+From f20f5106e8f16311a5a99f9de7ef1049d9e8bbd7 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Fri, 23 Feb 2024 00:47:12 +0100
+Subject: dt-bindings: sound: Add jack-type property to sun8i-a33-codec
+
+The codec driver needs to know what jack connector is connected to
+on the board. Add proprty to describe the type of connector.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../bindings/sound/allwinner,sun8i-a33-codec.yaml        | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/Documentation/devicetree/bindings/sound/allwinner,sun8i-a33-codec.yaml b/Documentation/devicetree/bindings/sound/allwinner,sun8i-a33-codec.yaml
+index 63eadc4200ac..399fc00ad3f4 100644
+--- a/Documentation/devicetree/bindings/sound/allwinner,sun8i-a33-codec.yaml
++++ b/Documentation/devicetree/bindings/sound/allwinner,sun8i-a33-codec.yaml
+@@ -44,6 +44,15 @@ properties:
+       - const: bus
+       - const: mod
+ 
++  jack-type:
++    enum:
++      - headset
++      - headphone
++    description:
++      Type of jack connector connected to the codec. This can be either
++      a 3-pin headphone connector or 4-pin headset connector. If not
++      specified, jack detection is disabled.
++
+ required:
+   - "#sound-dai-cells"
+   - compatible
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/firmware-arm_scpi-Support-unidirectional-mailbox-channels.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/firmware-arm_scpi-Support-unidirectional-mailbox-channels.patch
new file mode 100644
index 000000000000..e6ccb925b762
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/firmware-arm_scpi-Support-unidirectional-mailbox-channels.patch
@@ -0,0 +1,127 @@
+From 7ccfcf014f1793ab9388a98cdabe65e0a336259a Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Tue, 5 Mar 2019 22:02:41 -0600
+Subject: firmware: arm_scpi: Support unidirectional mailbox channels
+
+Some mailbox controllers have only unidirectional channels, so we need a
+pair of them for each SCPI channel. If a mbox-names property is present,
+look for "rx" and "tx" mbox channels; otherwise, the existing behavior
+is preserved, and a single mbox channel is used for each SCPI channel.
+
+Note that since the mailbox framework only supports a single phandle
+with each name (mbox_request_channel_byname always returns the first
+one), this new mode only supports a single SCPI channel.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/firmware/arm_scpi.c | 58 +++++++++++++++++++++++++++++--------
+ 1 file changed, 46 insertions(+), 12 deletions(-)
+
+diff --git a/drivers/firmware/arm_scpi.c b/drivers/firmware/arm_scpi.c
+index 0967c9212653..46c541bd9447 100644
+--- a/drivers/firmware/arm_scpi.c
++++ b/drivers/firmware/arm_scpi.c
+@@ -237,7 +237,8 @@ struct scpi_xfer {
+ 
+ struct scpi_chan {
+ 	struct mbox_client cl;
+-	struct mbox_chan *chan;
++	struct mbox_chan *rx_chan;
++	struct mbox_chan *tx_chan;
+ 	void __iomem *tx_payload;
+ 	void __iomem *rx_payload;
+ 	struct list_head rx_pending;
+@@ -511,7 +512,7 @@ static int scpi_send_message(u8 idx, void *tx_buf, unsigned int tx_len,
+ 	msg->rx_len = rx_len;
+ 	reinit_completion(&msg->done);
+ 
+-	ret = mbox_send_message(scpi_chan->chan, msg);
++	ret = mbox_send_message(scpi_chan->tx_chan, msg);
+ 	if (ret < 0 || !rx_buf)
+ 		goto out;
+ 
+@@ -872,8 +873,13 @@ static void scpi_free_channels(void *data)
+ 	struct scpi_drvinfo *info = data;
+ 	int i;
+ 
+-	for (i = 0; i < info->num_chans; i++)
+-		mbox_free_channel(info->channels[i].chan);
++	for (i = 0; i < info->num_chans; i++) {
++		struct scpi_chan *pchan = &info->channels[i];
++
++		if (pchan->tx_chan != pchan->rx_chan)
++			mbox_free_channel(pchan->tx_chan);
++		mbox_free_channel(pchan->rx_chan);
++	}
+ }
+ 
+ static void scpi_remove(struct platform_device *pdev)
+@@ -923,6 +929,7 @@ static int scpi_probe(struct platform_device *pdev)
+ 	struct device *dev = &pdev->dev;
+ 	struct device_node *np = dev->of_node;
+ 	struct scpi_drvinfo *scpi_drvinfo;
++	bool use_mbox_names = false;
+ 
+ 	scpi_drvinfo = devm_kzalloc(dev, sizeof(*scpi_drvinfo), GFP_KERNEL);
+ 	if (!scpi_drvinfo)
+@@ -935,6 +942,14 @@ static int scpi_probe(struct platform_device *pdev)
+ 		dev_err(dev, "no mboxes property in '%pOF'\n", np);
+ 		return -ENODEV;
+ 	}
++	if (of_get_property(dev->of_node, "mbox-names", NULL)) {
++		use_mbox_names = true;
++		if (count != 2) {
++			dev_err(dev, "need exactly 2 mboxes with mbox-names\n");
++			return -ENODEV;
++		}
++		count /= 2;
++	}
+ 
+ 	scpi_drvinfo->channels =
+ 		devm_kcalloc(dev, count, sizeof(struct scpi_chan), GFP_KERNEL);
+@@ -983,15 +998,34 @@ static int scpi_probe(struct platform_device *pdev)
+ 		mutex_init(&pchan->xfers_lock);
+ 
+ 		ret = scpi_alloc_xfer_list(dev, pchan);
+-		if (!ret) {
+-			pchan->chan = mbox_request_channel(cl, idx);
+-			if (!IS_ERR(pchan->chan))
+-				continue;
+-			ret = PTR_ERR(pchan->chan);
+-			if (ret != -EPROBE_DEFER)
+-				dev_err(dev, "failed to get channel%d err %d\n",
+-					idx, ret);
++		if (ret)
++			return ret;
++
++		if (use_mbox_names) {
++			pchan->rx_chan = mbox_request_channel_byname(cl, "rx");
++			if (IS_ERR(pchan->rx_chan)) {
++				ret = PTR_ERR(pchan->rx_chan);
++				goto fail;
++			}
++			pchan->tx_chan = mbox_request_channel_byname(cl, "tx");
++			if (IS_ERR(pchan->rx_chan)) {
++				ret = PTR_ERR(pchan->tx_chan);
++				goto fail;
++			}
++		} else {
++			pchan->rx_chan = mbox_request_channel(cl, idx);
++			if (IS_ERR(pchan->rx_chan)) {
++				ret = PTR_ERR(pchan->rx_chan);
++				goto fail;
++			}
++			pchan->tx_chan = pchan->rx_chan;
+ 		}
++		continue;
++
++fail:
++		if (ret != -EPROBE_DEFER)
++			dev_err(dev, "failed to get channel%d err %d\n",
++				idx, ret);
+ 		return ret;
+ 	}
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/firmware-scpi-Add-support-for-sending-a-SCPI_CMD_SET_SYS_PWR_ST.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/firmware-scpi-Add-support-for-sending-a-SCPI_CMD_SET_SYS_PWR_ST.patch
new file mode 100644
index 000000000000..6b0932fe185a
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/firmware-scpi-Add-support-for-sending-a-SCPI_CMD_SET_SYS_PWR_ST.patch
@@ -0,0 +1,87 @@
+From 0cfb0b5ca768b2516a5aa7b0f88be0daeea31692 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 2 Nov 2019 15:14:10 +0100
+Subject: firmware: scpi: Add support for sending a SCPI_CMD_SET_SYS_PWR_STATE
+ msg
+
+This is NOT the right message to signal SCP we want to suspend the
+system, but we use it anyway, because we simply want to do a fixed
+function suspend sequence, instead of more complicated and granular
+cluster/cpu/system power management.
+
+Normally we'd signal system suspend by sending a CSS power state
+message. I guess that can be done later, if wanted.
+
+For now, Linux will kill all secondary CPU cores via MCPM, and SCP
+will kill the last CPU, and suspend the system.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/firmware/arm_scpi.c   | 10 ++++++++++
+ include/linux/scpi_protocol.h |  1 +
+ 2 files changed, 11 insertions(+)
+
+diff --git a/drivers/firmware/arm_scpi.c b/drivers/firmware/arm_scpi.c
+index 87c323de17b9..0967c9212653 100644
+--- a/drivers/firmware/arm_scpi.c
++++ b/drivers/firmware/arm_scpi.c
+@@ -187,6 +187,7 @@ enum scpi_drv_cmds {
+ 	CMD_SENSOR_VALUE,
+ 	CMD_SET_DEVICE_PWR_STATE,
+ 	CMD_GET_DEVICE_PWR_STATE,
++	CMD_SET_SYS_PWR_STATE,
+ 	CMD_MAX_COUNT,
+ };
+ 
+@@ -203,6 +204,7 @@ static int scpi_std_commands[CMD_MAX_COUNT] = {
+ 	SCPI_CMD_SENSOR_VALUE,
+ 	SCPI_CMD_SET_DEVICE_PWR_STATE,
+ 	SCPI_CMD_GET_DEVICE_PWR_STATE,
++	SCPI_CMD_SET_SYS_PWR_STATE,
+ };
+ 
+ static int scpi_legacy_commands[CMD_MAX_COUNT] = {
+@@ -218,6 +220,7 @@ static int scpi_legacy_commands[CMD_MAX_COUNT] = {
+ 	LEGACY_SCPI_CMD_SENSOR_VALUE,
+ 	-1, /* SET_DEVICE_PWR_STATE */
+ 	-1, /* GET_DEVICE_PWR_STATE */
++	LEGACY_SCPI_CMD_SYS_PWR_STATE,
+ };
+ 
+ struct scpi_xfer {
+@@ -785,6 +788,12 @@ static int scpi_device_set_power_state(u16 dev_id, u8 pstate)
+ 				 sizeof(dev_set), &stat, sizeof(stat));
+ }
+ 
++static int scpi_sys_set_power_state(u8 pstate)
++{
++	return scpi_send_message(CMD_SET_SYS_PWR_STATE, &pstate,
++				 sizeof(pstate), NULL, 0);
++}
++
+ static struct scpi_ops scpi_ops = {
+ 	.get_version = scpi_get_version,
+ 	.clk_get_range = scpi_clk_get_range,
+@@ -801,6 +810,7 @@ static struct scpi_ops scpi_ops = {
+ 	.sensor_get_value = scpi_sensor_get_value,
+ 	.device_get_power_state = scpi_device_get_power_state,
+ 	.device_set_power_state = scpi_device_set_power_state,
++	.sys_set_power_state = scpi_sys_set_power_state,
+ };
+ 
+ struct scpi_ops *get_scpi_ops(void)
+diff --git a/include/linux/scpi_protocol.h b/include/linux/scpi_protocol.h
+index d2176a56828a..6169348c3b72 100644
+--- a/include/linux/scpi_protocol.h
++++ b/include/linux/scpi_protocol.h
+@@ -76,6 +76,7 @@ struct scpi_ops {
+ 	int (*sensor_get_value)(u16, u64 *);
+ 	int (*device_get_power_state)(u16);
+ 	int (*device_set_power_state)(u16, u8);
++	int (*sys_set_power_state)(u8);
+ };
+ 
+ #if IS_REACHABLE(CONFIG_ARM_SCPI_PROTOCOL)
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/gnss-ubx-Send-soft-powerdown-message-on-suspend.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/gnss-ubx-Send-soft-powerdown-message-on-suspend.patch
new file mode 100644
index 000000000000..ed98593c0a73
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/gnss-ubx-Send-soft-powerdown-message-on-suspend.patch
@@ -0,0 +1,64 @@
+From 21307662463898619177f8290f24007d38d3810e Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Wed, 23 Oct 2019 05:08:35 +0200
+Subject: gnss: ubx: Send soft powerdown message on suspend
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/gnss/ubx.c | 35 +++++++++++++++++++++++++++++++++++
+ 1 file changed, 35 insertions(+)
+
+diff --git a/drivers/gnss/ubx.c b/drivers/gnss/ubx.c
+index 92402f6082c4..fd0ccb054477 100644
+--- a/drivers/gnss/ubx.c
++++ b/drivers/gnss/ubx.c
+@@ -33,11 +33,46 @@ static int ubx_set_active(struct gnss_serial *gserial)
+ 	return 0;
+ }
+ 
++// RXM-PMREQ
++static const u8 ubx_suspend_packet[] = {
++	0xb5, 0x62, // 'ub'
++	0x02, 0x41, // message class and id
++	0x08, 0x00, // message length
++	0x00, 0x00, 0x00, 0x00, // duration (0 == infinite)
++	0x02, 0x00, 0x00, 0x00, // flags (backup)
++	0x4d, 0x3b, // checksum
++};
++
+ static int ubx_set_standby(struct gnss_serial *gserial)
+ {
+ 	struct ubx_data *data = gnss_serial_get_drvdata(gserial);
+ 	int ret;
+ 
++#if 0
++	struct serdev_device *serdev = gserial->serdev;
++
++	// we can't know what state the device is in, so first make sure
++	// it's woken up by writing a zero byte to it and then suspend it
++	// for sure
++
++	ret = serdev_device_write(serdev, "", 1, MAX_SCHEDULE_TIMEOUT);
++	if (ret < 0)
++		return ret;
++
++	serdev_device_wait_until_sent(serdev, 0);
++
++	// wait for wakeup
++	mdelay(100);
++
++	ret = serdev_device_write(serdev, ubx_suspend_packet,
++				  sizeof(ubx_suspend_packet),
++				  MAX_SCHEDULE_TIMEOUT);
++	if (ret < 0 || ret < sizeof(ubx_suspend_packet))
++		return ret;
++
++	serdev_device_wait_until_sent(serdev, 0);
++#endif
++
+ 	ret = regulator_disable(data->vcc);
+ 	if (ret)
+ 		return ret;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/hm5065-yaml-bindings-wip.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/hm5065-yaml-bindings-wip.patch
new file mode 100644
index 000000000000..95462e00ccfb
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/hm5065-yaml-bindings-wip.patch
@@ -0,0 +1,109 @@
+From 95c2f6cf0f9b2c0f358946ebd92947e817bb2ba1 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 20 May 2019 17:58:05 +0200
+Subject: hm5065: yaml bindings (wip)
+
+---
+ .../devicetree/bindings/media/i2c/hm5065.yaml | 90 +++++++++++++++++++
+ 1 file changed, 90 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/media/i2c/hm5065.yaml
+
+diff --git a/Documentation/devicetree/bindings/media/i2c/hm5065.yaml b/Documentation/devicetree/bindings/media/i2c/hm5065.yaml
+new file mode 100644
+index 000000000000..df7a4f514b3f
+--- /dev/null
++++ b/Documentation/devicetree/bindings/media/i2c/hm5065.yaml
+@@ -0,0 +1,90 @@
++# SPDX-License-Identifier: GPL-2.0
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/media/i2c/hm5065.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Himax HM5065 CSI camera sensor
++
++description: |+
++  At least one of reset-gpios and enable-gpios must be configured.
++
++  The device node must contain one 'port' child node for its digital output
++  video port, in accordance with the video interface bindings defined in
++  
++  Documentation/devicetree/bindings/media/video-interfaces.txt.
++
++maintainers:
++  - Ondrej Jirman <megi@xff.cz>
++
++properties:
++  compatible:
++    const: himax,hm5065
++
++  reg:
++    maxItems: 1
++
++  reset-gpios:
++    maxItems: 1
++    description: reference to the GPIO connected to the reset pin, if any. This is an active low signal to the HM5065.
++
++  enable-gpios:
++    maxItems: 1
++    description: reference to the GPIO connected to the CE pin, if any. This is an active high signal to the HM5065.
++
++  IOVDD-supply:
++    description: Digital I/O voltage supply, 2.8 volts
++
++  AVDD-supply:
++    description: Analog voltage supply, 2.8 volts
++
++  DVDD-supply:
++    description: Digital core voltage supply, 1.8 volts
++
++  AFVDD-supply:
++    description: Auto focus voltage supply, 2.8 volts
++
++  clocks:
++    minItems: 1
++    maxItems: 1
++    description: reference to the external input clock for the sensor.
++
++- clock-names: should be "xclk".
++
++required:
++  - compatible
++  - reg
++  - clocks
++  - clock-names
++  - IOVDD-supply
++  - AVDD-supply
++  - DVDD-supply
++  - AFVDD-supply
++
++Example:
++
++&i2c1 {
++	hm5065: camera@1f {
++		compatible = "himax,hm5065";
++		reg = <0x1f>;
++		clocks = <&ccu CLK_CSI_MCLK>;
++		clock-names = "xclk";
++		IOVDD-supply = <&reg_dldo3>;
++		AVDD-supply = <&reg_dldo4>;
++		DVDD-supply = <&reg_eldo3>;
++		AFVDD-supply = <&reg_dldo3>;
++		reset-gpios = <&pio 4 18 GPIO_ACTIVE_LOW>; /* PE18 */
++		enable-gpios = <&pio 4 19 GPIO_ACTIVE_HIGH>; /* PE19 */
++
++		port {
++			hm5065_ep: endpoint {
++				remote-endpoint = <&csi0_hm5065_ep>;
++				bus-width = <8>;
++				hsync-active = <1>;
++				vsync-active = <1>;
++				data-active = <1>;
++				pclk-sample = <1>;
++			};
++		};
++	};
++};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/i2c-mv64xxx-Don-t-make-a-fuss-when-pinctrl-recovery-state-is-no.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/i2c-mv64xxx-Don-t-make-a-fuss-when-pinctrl-recovery-state-is-no.patch
new file mode 100644
index 000000000000..b8f1eabba728
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/i2c-mv64xxx-Don-t-make-a-fuss-when-pinctrl-recovery-state-is-no.patch
@@ -0,0 +1,35 @@
+From 329092d43e60dd4c8f1308330231a77c7cb00bd9 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 17 Jan 2021 23:19:52 +0100
+Subject: i2c: mv64xxx: Don't make a fuss when pinctrl recovery state is not
+ present
+
+Otherwise dmesg log presents a useless error.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/i2c/busses/i2c-mv64xxx.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/drivers/i2c/busses/i2c-mv64xxx.c b/drivers/i2c/busses/i2c-mv64xxx.c
+index 874309580c33..d7cac1434126 100644
+--- a/drivers/i2c/busses/i2c-mv64xxx.c
++++ b/drivers/i2c/busses/i2c-mv64xxx.c
+@@ -950,6 +950,14 @@ static int mv64xxx_i2c_init_recovery_info(struct mv64xxx_i2c_data *drv_data,
+ 		return -ENODEV;
+ 	}
+ 
++	if (IS_ERR(pinctrl_lookup_state(rinfo->pinctrl, "gpio")) &&
++		IS_ERR(pinctrl_lookup_state(rinfo->pinctrl, "recovery"))) {
++		/* No recovery state is vailable in pinctrl. */
++		devm_pinctrl_put(rinfo->pinctrl);
++		rinfo->pinctrl = NULL;
++		return 0;
++	}
++
+ 	drv_data->adapter.bus_recovery_info = rinfo;
+ 	return 0;
+ }
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/iio-adc-axp20x_adc-allow-to-set-TS-pin-to-GPADC-mode.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/iio-adc-axp20x_adc-allow-to-set-TS-pin-to-GPADC-mode.patch
new file mode 100644
index 000000000000..ba33f252ca4a
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/iio-adc-axp20x_adc-allow-to-set-TS-pin-to-GPADC-mode.patch
@@ -0,0 +1,42 @@
+From 5617049aa26b140a13a7eb7c3e38ab940c6cbca0 Mon Sep 17 00:00:00 2001
+From: Icenowy Zheng <icenowy@aosc.io>
+Date: Tue, 10 Sep 2019 12:03:32 +0800
+Subject: iio: adc: axp20x_adc: allow to set TS pin to GPADC mode
+
+The TS pin of AXP PMICs can be set to GPADC mode. In this situation, it
+doesn't affect battery charging.
+
+Add the code to do the mode setting.
+
+Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
+---
+ drivers/iio/adc/axp20x_adc.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/drivers/iio/adc/axp20x_adc.c b/drivers/iio/adc/axp20x_adc.c
+index 9fd7027623d0..50eef565df2c 100644
+--- a/drivers/iio/adc/axp20x_adc.c
++++ b/drivers/iio/adc/axp20x_adc.c
+@@ -58,6 +58,7 @@
+ #define AXP813_TS_GPIO0_ADC_RATE_HZ(x)		AXP20X_ADC_RATE_HZ(x)
+ #define AXP813_V_I_ADC_RATE_HZ(x)		((ilog2((x) / 100) << 4) & AXP813_V_I_ADC_RATE_MASK)
+ #define AXP813_ADC_RATE_HZ(x)			(AXP20X_ADC_RATE_HZ(x) | AXP813_V_I_ADC_RATE_HZ(x))
++#define AXP20X_TS_FUNCTION_GPADC		BIT(2)
+ 
+ #define AXP20X_ADC_CHANNEL(_channel, _name, _type, _reg)	\
+ 	{							\
+@@ -1131,6 +1132,11 @@ static int axp20x_probe(struct platform_device *pdev)
+ 		regmap_set_bits(info->regmap, info->data->adc_en2,
+ 				info->data->adc_en2_mask);
+ 
++	if (of_property_read_bool(pdev->dev.of_node, "x-powers,ts-as-gpadc"))
++		regmap_update_bits(info->regmap, AXP20X_ADC_RATE,
++				   AXP20X_TS_FUNCTION_GPADC,
++				   AXP20X_TS_FUNCTION_GPADC);
++
+ 	/* Configure ADCs rate */
+ 	if (info->data->adc_rate)
+ 		info->data->adc_rate(info, 100);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/iio-adc-sun4i-gpadc-iio-Allow-to-use-sun5i-a13-gpadc-iio-from-D.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/iio-adc-sun4i-gpadc-iio-Allow-to-use-sun5i-a13-gpadc-iio-from-D.patch
new file mode 100644
index 000000000000..0bfb8408a0fe
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/iio-adc-sun4i-gpadc-iio-Allow-to-use-sun5i-a13-gpadc-iio-from-D.patch
@@ -0,0 +1,61 @@
+From 0ff022dc3b2674f575bcf30a2a988002845eb698 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 7 Oct 2019 02:12:34 +0200
+Subject: iio: adc: sun4i-gpadc-iio: Allow to use sun5i-a13-gpadc-iio from DT
+
+We can now use allwinner,sun5i-a13-gpadc-iio to create a sub-node of
+allwinner,sun5i-a13-ts, that can be referenced by other drivers
+via IIO framework.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/boot/dts/allwinner/sun5i.dtsi | 5 +++++
+ drivers/iio/adc/sun4i-gpadc-iio.c      | 3 ++-
+ drivers/mfd/sun4i-gpadc.c              | 1 +
+ 3 files changed, 8 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun5i.dtsi b/arch/arm/boot/dts/allwinner/sun5i.dtsi
+index d7c7b454a11a..e6836fd4b8dc 100644
+--- a/arch/arm/boot/dts/allwinner/sun5i.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun5i.dtsi
+@@ -657,6 +657,11 @@ rtp: rtp@1c25000 {
+ 			reg = <0x01c25000 0x100>;
+ 			interrupts = <29>;
+ 			#thermal-sensor-cells = <0>;
++
++			rtp_adc: adc {
++				compatible = "allwinner,sun5i-a13-gpadc-iio";
++				#io-channel-cells = <1>;
++			};
+ 		};
+ 
+ 		uart0: serial@1c28000 {
+diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c b/drivers/iio/adc/sun4i-gpadc-iio.c
+index 8b27458dcd66..3c673c35629f 100644
+--- a/drivers/iio/adc/sun4i-gpadc-iio.c
++++ b/drivers/iio/adc/sun4i-gpadc-iio.c
+@@ -618,7 +618,8 @@ static int sun4i_gpadc_probe(struct platform_device *pdev)
+ 	indio_dev->info = &sun4i_gpadc_iio_info;
+ 	indio_dev->modes = INDIO_DIRECT_MODE;
+ 
+-	if (pdev->dev.of_node)
++	if (pdev->dev.of_node && of_match_node(sun4i_gpadc_of_id,
++					       pdev->dev.of_node))
+ 		ret = sun4i_gpadc_probe_dt(pdev, indio_dev);
+ 	else
+ 		ret = sun4i_gpadc_probe_mfd(pdev, indio_dev);
+diff --git a/drivers/mfd/sun4i-gpadc.c b/drivers/mfd/sun4i-gpadc.c
+index 3029d48e982c..51da961cffd5 100644
+--- a/drivers/mfd/sun4i-gpadc.c
++++ b/drivers/mfd/sun4i-gpadc.c
+@@ -53,6 +53,7 @@ static struct mfd_cell sun4i_gpadc_cells[] = {
+ static struct mfd_cell sun5i_gpadc_cells[] = {
+ 	{
+ 		.name	= "sun5i-a13-gpadc-iio",
++		.of_compatible	= "allwinner,sun5i-a13-gpadc-iio",
+ 		.resources = adc_resources,
+ 		.num_resources = ARRAY_SIZE(adc_resources),
+ 	},
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/iio-st_sensors-Don-t-report-error-when-the-device-is-not-presen.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/iio-st_sensors-Don-t-report-error-when-the-device-is-not-presen.patch
new file mode 100644
index 000000000000..e24bffabe61e
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/iio-st_sensors-Don-t-report-error-when-the-device-is-not-presen.patch
@@ -0,0 +1,39 @@
+From db9ba37a021ab7935acc6d7b7ff4e40756314229 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sat, 29 Oct 2022 23:12:49 +0200
+Subject: iio: st_sensors: Don't report error when the device is not present on
+ I2C bus
+
+On Pinephone, this is not an error, because there are two alternate
+magentometer configurations.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/iio/common/st_sensors/st_sensors_core.c | 10 +++++++++-
+ 1 file changed, 9 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/iio/common/st_sensors/st_sensors_core.c b/drivers/iio/common/st_sensors/st_sensors_core.c
+index e4f5a7ff7e74..5ee2ab1fc619 100644
+--- a/drivers/iio/common/st_sensors/st_sensors_core.c
++++ b/drivers/iio/common/st_sensors/st_sensors_core.c
+@@ -600,8 +600,16 @@ int st_sensors_verify_id(struct iio_dev *indio_dev)
+ 		err = regmap_read(sdata->regmap,
+ 				  sdata->sensor_settings->wai_addr, &wai);
+ 		if (err < 0) {
++			if (err == -ENXIO) {
++				dev_info(&indio_dev->dev,
++					 "%s is not present on the bus\n",
++					 indio_dev->name);
++				return err;
++			}
++
+ 			dev_err(&indio_dev->dev,
+-				"failed to read Who-Am-I register.\n");
++				"%s: failed to read Who-Am-I register (%d).\n",
++				indio_dev->name, err);
+ 			return err;
+ 		}
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/input-cyttsp4-Clear-the-ids-buffer-in-a-saner-way.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/input-cyttsp4-Clear-the-ids-buffer-in-a-saner-way.patch
new file mode 100644
index 000000000000..e6a8c25757a1
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/input-cyttsp4-Clear-the-ids-buffer-in-a-saner-way.patch
@@ -0,0 +1,32 @@
+From eeddb82ccb6cc3d77349fc5eb465b3636383017f Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 28 Sep 2019 18:00:33 +0200
+Subject: input: cyttsp4: Clear the ids buffer in a saner way
+
+Fixes memory corruption / NPE failures during touch data
+acquisition.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/input/touchscreen/cyttsp4_core.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/drivers/input/touchscreen/cyttsp4_core.c b/drivers/input/touchscreen/cyttsp4_core.c
+index 31fd75477322..1205fc6658ad 100644
+--- a/drivers/input/touchscreen/cyttsp4_core.c
++++ b/drivers/input/touchscreen/cyttsp4_core.c
+@@ -854,10 +854,9 @@ static void cyttsp4_get_mt_touches(struct cyttsp4 *cd, int num_cur_tch)
+ 	struct cyttsp4_sysinfo *si = cd->si;
+ 	struct cyttsp4_touch tch;
+ 	int i, j, t = 0;
+-	int ids[max(CY_TMA1036_MAX_TCH, CY_TMA4XX_MAX_TCH)];
++	int ids[max(CY_TMA1036_MAX_TCH, CY_TMA4XX_MAX_TCH)] = {0};
+ 	struct cyttsp4_signal_def* sig;
+ 
+-	memset(ids, 0, si->si_ofs.tch_abs[CY_TCH_T].max * sizeof(int));
+ 	for (i = 0; i < num_cur_tch; i++) {
+ 		cyttsp4_get_touch(cd, &tch, si->xy_data +
+ 				  (i * si->si_ofs.tch_rec_size));
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/input-cyttsp4-De-obfuscate-MT-signals-setup-platform-data.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/input-cyttsp4-De-obfuscate-MT-signals-setup-platform-data.patch
new file mode 100644
index 000000000000..e202ca0b1e91
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/input-cyttsp4-De-obfuscate-MT-signals-setup-platform-data.patch
@@ -0,0 +1,263 @@
+From 3b73c055dddefa34abf2bc744b607c23411e3099 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 28 Sep 2019 16:01:06 +0200
+Subject: input: cyttsp4: De-obfuscate MT signals setup/platform data
+
+Original code does a lot of array math, and is needlessly complicated.
+Make it easier to use and clean it up.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/input/touchscreen/cyttsp4_core.c | 102 ++++++++++-------------
+ drivers/input/touchscreen/cyttsp4_core.h |  26 ------
+ include/linux/platform_data/cyttsp4.h    |  27 ++++--
+ 3 files changed, 66 insertions(+), 89 deletions(-)
+
+diff --git a/drivers/input/touchscreen/cyttsp4_core.c b/drivers/input/touchscreen/cyttsp4_core.c
+index 867c18abc89b..31fd75477322 100644
+--- a/drivers/input/touchscreen/cyttsp4_core.c
++++ b/drivers/input/touchscreen/cyttsp4_core.c
+@@ -853,31 +853,26 @@ static void cyttsp4_get_mt_touches(struct cyttsp4 *cd, int num_cur_tch)
+ 	struct device *dev = &cd->input->dev;
+ 	struct cyttsp4_sysinfo *si = cd->si;
+ 	struct cyttsp4_touch tch;
+-	int sig;
+ 	int i, j, t = 0;
+ 	int ids[max(CY_TMA1036_MAX_TCH, CY_TMA4XX_MAX_TCH)];
++	struct cyttsp4_signal_def* sig;
+ 
+ 	memset(ids, 0, si->si_ofs.tch_abs[CY_TCH_T].max * sizeof(int));
+ 	for (i = 0; i < num_cur_tch; i++) {
+ 		cyttsp4_get_touch(cd, &tch, si->xy_data +
+-			(i * si->si_ofs.tch_rec_size));
+-		if ((tch.abs[CY_TCH_T] < cd->pdata->frmwrk->abs
+-			[(CY_ABS_ID_OST * CY_NUM_ABS_SET) + CY_MIN_OST]) ||
+-			(tch.abs[CY_TCH_T] > cd->pdata->frmwrk->abs
+-			[(CY_ABS_ID_OST * CY_NUM_ABS_SET) + CY_MAX_OST])) {
++				  (i * si->si_ofs.tch_rec_size));
++
++		sig = &cd->pdata->signals[CY_ABS_ID_OST];
++		if (tch.abs[CY_TCH_T] < sig->min ||
++			tch.abs[CY_TCH_T] > sig->max) {
+ 			dev_err(dev, "%s: tch=%d -> bad trk_id=%d max_id=%d\n",
+-				__func__, i, tch.abs[CY_TCH_T],
+-				cd->pdata->frmwrk->abs[(CY_ABS_ID_OST *
+-				CY_NUM_ABS_SET) + CY_MAX_OST]);
++				__func__, i, tch.abs[CY_TCH_T], sig->max);
+ 			continue;
+ 		}
+ 
+ 		/* use 0 based track id's */
+-		sig = cd->pdata->frmwrk->abs
+-			[(CY_ABS_ID_OST * CY_NUM_ABS_SET) + 0];
+-		if (sig != CY_IGNORE_VALUE) {
+-			t = tch.abs[CY_TCH_T] - cd->pdata->frmwrk->abs
+-				[(CY_ABS_ID_OST * CY_NUM_ABS_SET) + CY_MIN_OST];
++		if (sig->signal >= 0) {
++			t = tch.abs[CY_TCH_T] - sig->min;
+ 			if (tch.abs[CY_TCH_E] == CY_EV_LIFTOFF) {
+ 				dev_dbg(dev, "%s: t=%d e=%d lift-off\n",
+ 					__func__, t, tch.abs[CY_TCH_E]);
+@@ -885,18 +880,18 @@ static void cyttsp4_get_mt_touches(struct cyttsp4 *cd, int num_cur_tch)
+ 			}
+ 			input_mt_slot(cd->input, t);
+ 			input_mt_report_slot_state(cd->input, MT_TOOL_FINGER,
+-					true);
++						   true);
+ 			ids[t] = true;
+ 		}
+ 
+ 		/* all devices: position and pressure fields */
+ 		for (j = 0; j <= CY_ABS_W_OST; j++) {
+-			sig = cd->pdata->frmwrk->abs[((CY_ABS_X_OST + j) *
+-				CY_NUM_ABS_SET) + 0];
+-			if (sig != CY_IGNORE_VALUE)
+-				input_report_abs(cd->input, sig,
+-					tch.abs[CY_TCH_X + j]);
++			sig = &cd->pdata->signals[j];
++			if (sig->signal >= 0)
++				input_report_abs(cd->input, sig->signal,
++						 tch.abs[CY_TCH_X + j]);
+ 		}
++
+ 		if (si->si_ofs.tch_rec_size > CY_TMA1036_TCH_REC_SIZE) {
+ 			/*
+ 			 * TMA400 size and orientation fields:
+@@ -909,12 +904,10 @@ static void cyttsp4_get_mt_touches(struct cyttsp4 *cd, int num_cur_tch)
+ 
+ 			/* Get the extended touch fields */
+ 			for (j = 0; j < CY_NUM_EXT_TCH_FIELDS; j++) {
+-				sig = cd->pdata->frmwrk->abs
+-					[((CY_ABS_MAJ_OST + j) *
+-					CY_NUM_ABS_SET) + 0];
+-				if (sig != CY_IGNORE_VALUE)
+-					input_report_abs(cd->input, sig,
+-						tch.abs[CY_TCH_MAJ + j]);
++				sig = &cd->pdata->signals[CY_ABS_MAJ_OST + j];
++				if (sig->signal >= 0)
++					input_report_abs(cd->input, sig->signal,
++							 tch.abs[CY_TCH_MAJ + j]);
+ 			}
+ 		}
+ 
+@@ -1878,7 +1871,7 @@ static void cyttsp4_mt_close(struct input_dev *input)
+ static int cyttsp4_setup_input_device(struct cyttsp4 *cd)
+ {
+ 	struct device *dev = cd->dev;
+-	int signal = CY_IGNORE_VALUE;
++	struct cyttsp4_signal_def *signal;
+ 	int max_x, max_y, max_p, min, max;
+ 	int max_x_tmp, max_y_tmp;
+ 	int i;
+@@ -1903,37 +1896,30 @@ static int cyttsp4_setup_input_device(struct cyttsp4 *cd)
+ 	max_p = cd->si->si_ofs.max_p;
+ 
+ 	/* set event signal capabilities */
+-	for (i = 0; i < (cd->pdata->frmwrk->size / CY_NUM_ABS_SET); i++) {
+-		signal = cd->pdata->frmwrk->abs
+-			[(i * CY_NUM_ABS_SET) + CY_SIGNAL_OST];
+-		if (signal != CY_IGNORE_VALUE) {
+-			__set_bit(signal, cd->input->absbit);
+-			min = cd->pdata->frmwrk->abs
+-				[(i * CY_NUM_ABS_SET) + CY_MIN_OST];
+-			max = cd->pdata->frmwrk->abs
+-				[(i * CY_NUM_ABS_SET) + CY_MAX_OST];
+-			if (i == CY_ABS_ID_OST) {
+-				/* shift track ids down to start at 0 */
+-				max = max - min;
+-				min = min - min;
+-			} else if (i == CY_ABS_X_OST)
+-				max = max_x;
+-			else if (i == CY_ABS_Y_OST)
+-				max = max_y;
+-			else if (i == CY_ABS_P_OST)
+-				max = max_p;
+-			input_set_abs_params(cd->input, signal, min, max,
+-				cd->pdata->frmwrk->abs
+-				[(i * CY_NUM_ABS_SET) + CY_FUZZ_OST],
+-				cd->pdata->frmwrk->abs
+-				[(i * CY_NUM_ABS_SET) + CY_FLAT_OST]);
+-			dev_dbg(dev, "%s: register signal=%02X min=%d max=%d\n",
+-				__func__, signal, min, max);
+-			if ((i == CY_ABS_ID_OST) &&
+-				(cd->si->si_ofs.tch_rec_size <
+-				CY_TMA4XX_TCH_REC_SIZE))
+-				break;
+-		}
++	for (i = 0; i < cd->pdata->n_signals; i++) {
++		signal = &cd->pdata->signals[i];
++
++		__set_bit(signal->signal, cd->input->absbit);
++
++		max = signal->max;
++		min = signal->min;
++
++		if (signal->signal == ABS_MT_POSITION_X)
++			max = max_x;
++		else if (signal->signal == ABS_MT_POSITION_Y)
++			max = max_y;
++		else if (signal->signal == ABS_MT_PRESSURE)
++			max = max_p;
++
++		input_set_abs_params(cd->input, signal->signal, min, max,
++				     signal->fuzz, signal->flat);
++		dev_dbg(dev, "%s: register signal=%02X min=%d max=%d\n",
++			__func__, signal->signal, min, max);
++
++		if ((i == CY_ABS_ID_OST) &&
++			(cd->si->si_ofs.tch_rec_size <
++			CY_TMA4XX_TCH_REC_SIZE))
++			break;
+ 	}
+ 
+ 	input_mt_init_slots(cd->input, cd->si->si_ofs.tch_abs[CY_TCH_T].max,
+diff --git a/drivers/input/touchscreen/cyttsp4_core.h b/drivers/input/touchscreen/cyttsp4_core.h
+index 05fb30058d87..995bfd0a54d0 100644
+--- a/drivers/input/touchscreen/cyttsp4_core.h
++++ b/drivers/input/touchscreen/cyttsp4_core.h
+@@ -357,32 +357,6 @@ enum cyttsp4_hst_mode_bits {
+ 	CY_HST_RESET       = (1 << 0),
+ };
+ 
+-/* abs settings */
+-#define CY_IGNORE_VALUE			0xFFFF
+-
+-/* abs signal capabilities offsets in the frameworks array */
+-enum cyttsp4_sig_caps {
+-	CY_SIGNAL_OST,
+-	CY_MIN_OST,
+-	CY_MAX_OST,
+-	CY_FUZZ_OST,
+-	CY_FLAT_OST,
+-	CY_NUM_ABS_SET	/* number of signal capability fields */
+-};
+-
+-/* abs axis signal offsets in the framworks array  */
+-enum cyttsp4_sig_ost {
+-	CY_ABS_X_OST,
+-	CY_ABS_Y_OST,
+-	CY_ABS_P_OST,
+-	CY_ABS_W_OST,
+-	CY_ABS_ID_OST,
+-	CY_ABS_MAJ_OST,
+-	CY_ABS_MIN_OST,
+-	CY_ABS_OR_OST,
+-	CY_NUM_ABS_OST	/* number of abs signals */
+-};
+-
+ enum cyttsp4_flags {
+ 	CY_FLAG_NONE = 0x00,
+ 	CY_FLAG_HOVER = 0x04,
+diff --git a/include/linux/platform_data/cyttsp4.h b/include/linux/platform_data/cyttsp4.h
+index 362fa181ac04..1b5b30796e43 100644
+--- a/include/linux/platform_data/cyttsp4.h
++++ b/include/linux/platform_data/cyttsp4.h
+@@ -21,15 +21,31 @@
+ 
+ #define CY_TOUCH_SETTINGS_MAX 32
+ 
+-struct touch_framework {
+-	const uint16_t  *abs;
+-	uint8_t         size;
+-} __packed;
++/* abs axis signal offsets in the signals array  */
++enum cyttsp4_sig_ost {
++	CY_ABS_X_OST,
++	CY_ABS_Y_OST,
++	CY_ABS_P_OST,
++	CY_ABS_W_OST,
++	CY_ABS_ID_OST,
++	CY_ABS_MAJ_OST,
++	CY_ABS_MIN_OST,
++	CY_ABS_OR_OST,
++	CY_NUM_ABS_OST	/* number of abs signals */
++};
+ 
+ struct cyttsp4_virtual_key {
+ 	int code;
+ };
+ 
++struct cyttsp4_signal_def {
++	int signal;
++	int min;
++	int max;
++	int fuzz;
++	int flat;
++};
++
+ struct cyttsp4_platform_data {
+ 	char const *inp_dev_name;
+ 	unsigned short flags;
+@@ -46,7 +62,8 @@ struct cyttsp4_platform_data {
+ 	int (*irq_stat)(struct cyttsp4_platform_data *pdata,
+ 		struct device *dev);
+ 
+-	struct touch_framework *frmwrk;
++	int n_signals;
++	struct cyttsp4_signal_def *signals;
+ 
+ 	int n_keys;
+ 	struct cyttsp4_virtual_key* keys;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/input-cyttsp4-De-obfuscate-platform-data-for-keys.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/input-cyttsp4-De-obfuscate-platform-data-for-keys.patch
new file mode 100644
index 000000000000..3f201fb28072
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/input-cyttsp4-De-obfuscate-platform-data-for-keys.patch
@@ -0,0 +1,85 @@
+From 942e10d26c88fc22ffb1a520d4441b31912cc5fd Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 28 Sep 2019 14:46:11 +0200
+Subject: input: cyttsp4: De-obfuscate platform data for keys
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/input/touchscreen/cyttsp4_core.c | 22 +++-------------------
+ include/linux/platform_data/cyttsp4.h    | 12 ++++++------
+ 2 files changed, 9 insertions(+), 25 deletions(-)
+
+diff --git a/drivers/input/touchscreen/cyttsp4_core.c b/drivers/input/touchscreen/cyttsp4_core.c
+index 7cb26929dc73..f2dd87cdeb8f 100644
+--- a/drivers/input/touchscreen/cyttsp4_core.c
++++ b/drivers/input/touchscreen/cyttsp4_core.c
+@@ -541,8 +541,6 @@ static int cyttsp4_si_get_btn_data(struct cyttsp4 *cd)
+ {
+ 	struct cyttsp4_sysinfo *si = &cd->sysinfo;
+ 	int btn;
+-	int num_defined_keys;
+-	u16 *key_table;
+ 	void *p;
+ 	int rc = 0;
+ 
+@@ -559,24 +557,10 @@ static int cyttsp4_si_get_btn_data(struct cyttsp4 *cd)
+ 		}
+ 		si->btn = p;
+ 
+-		if (cd->cpdata->sett[CY_IC_GRPNUM_BTN_KEYS] == NULL)
+-			num_defined_keys = 0;
+-		else if (cd->cpdata->sett[CY_IC_GRPNUM_BTN_KEYS]->data == NULL)
+-			num_defined_keys = 0;
+-		else
+-			num_defined_keys = cd->cpdata->sett
+-				[CY_IC_GRPNUM_BTN_KEYS]->size;
+-
+-		for (btn = 0; btn < si->si_ofs.num_btns &&
+-			btn < num_defined_keys; btn++) {
+-			key_table = (u16 *)cd->cpdata->sett
+-				[CY_IC_GRPNUM_BTN_KEYS]->data;
+-			si->btn[btn].key_code = key_table[btn];
+-			si->btn[btn].state = CY_BTN_RELEASED;
+-			si->btn[btn].enabled = true;
+-		}
+-		for (; btn < si->si_ofs.num_btns; btn++) {
++		for (btn = 0; btn < si->si_ofs.num_btns; btn++) {
+ 			si->btn[btn].key_code = KEY_RESERVED;
++			if (btn < cd->cpdata->n_keys)
++				si->btn[btn].key_code = cd->cpdata->keys[btn].code;
+ 			si->btn[btn].state = CY_BTN_RELEASED;
+ 			si->btn[btn].enabled = true;
+ 		}
+diff --git a/include/linux/platform_data/cyttsp4.h b/include/linux/platform_data/cyttsp4.h
+index 5dc9d2be384b..c54160c17b0b 100644
+--- a/include/linux/platform_data/cyttsp4.h
++++ b/include/linux/platform_data/cyttsp4.h
+@@ -33,11 +33,9 @@ struct cyttsp4_mt_platform_data {
+ 	char const *inp_dev_name;
+ };
+ 
+-struct touch_settings {
+-	const uint8_t *data;
+-	uint32_t size;
+-	uint8_t tag;
+-} __packed;
++struct cyttsp4_virtual_key {
++	int code;
++};
+ 
+ struct cyttsp4_core_platform_data {
+ 	int irq_gpio;
+@@ -51,7 +49,9 @@ struct cyttsp4_core_platform_data {
+ 		int on, struct device *dev, atomic_t *ignore_irq);
+ 	int (*irq_stat)(struct cyttsp4_core_platform_data *pdata,
+ 		struct device *dev);
+-	struct touch_settings *sett[CY_TOUCH_SETTINGS_MAX];
++
++	int n_keys;
++	struct cyttsp4_virtual_key* keys;
+ };
+ 
+ struct cyttsp4_platform_data {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/input-cyttsp4-ENOSYS-error-is-ok-when-powering-up.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/input-cyttsp4-ENOSYS-error-is-ok-when-powering-up.patch
new file mode 100644
index 000000000000..23785caa6db5
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/input-cyttsp4-ENOSYS-error-is-ok-when-powering-up.patch
@@ -0,0 +1,29 @@
+From fc58479f81ed2a3d2eaf37030addf1534fcf10d0 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 28 Sep 2019 18:01:49 +0200
+Subject: input: cyttsp4: ENOSYS error is ok when powering up
+
+This error is handled gracefully, don't report it.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/input/touchscreen/cyttsp4_core.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/input/touchscreen/cyttsp4_core.c b/drivers/input/touchscreen/cyttsp4_core.c
+index 1205fc6658ad..1e277ceca20f 100644
+--- a/drivers/input/touchscreen/cyttsp4_core.c
++++ b/drivers/input/touchscreen/cyttsp4_core.c
+@@ -1764,7 +1764,8 @@ static int cyttsp4_core_wake_(struct cyttsp4 *cd)
+ 		rc = -ENOSYS;
+ 	}
+ 	if (rc < 0) {
+-		dev_err(dev, "%s: HW Power up fails r=%d\n",
++		if (rc != -ENOSYS)
++			dev_err(dev, "%s: HW Power up fails r=%d\n",
+ 				__func__, rc);
+ 
+ 		/* Initiate a read transaction to wake up */
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/input-cyttsp4-Faster-recovery-from-failed-wakeup-HACK.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/input-cyttsp4-Faster-recovery-from-failed-wakeup-HACK.patch
new file mode 100644
index 000000000000..7ff27992b2c4
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/input-cyttsp4-Faster-recovery-from-failed-wakeup-HACK.patch
@@ -0,0 +1,31 @@
+From d360ec7955abbb6da5b01a392a0192cb561a54c3 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 28 Sep 2019 18:03:41 +0200
+Subject: input: cyttsp4: Faster recovery from failed wakeup (HACK)
+
+For some reason on Pocket Book Touch Lux 3, sending and I2C
+data, doesn't wake up the device, and it always times out.
+
+Lower the timeout, so that reset is done ASAP after wakeup.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/input/touchscreen/cyttsp4_core.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/input/touchscreen/cyttsp4_core.c b/drivers/input/touchscreen/cyttsp4_core.c
+index 1e277ceca20f..c30e2088c732 100644
+--- a/drivers/input/touchscreen/cyttsp4_core.c
++++ b/drivers/input/touchscreen/cyttsp4_core.c
+@@ -26,7 +26,7 @@
+ #define CY_CORE_SLEEP_REQUEST_EXCLUSIVE_TIMEOUT	5000
+ #define CY_CORE_MODE_CHANGE_TIMEOUT		1000
+ #define CY_CORE_RESET_AND_WAIT_TIMEOUT		500
+-#define CY_CORE_WAKEUP_TIMEOUT			500
++#define CY_CORE_WAKEUP_TIMEOUT			50
+ 
+ #define CY_CORE_STARTUP_RETRY_COUNT		3
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/input-cyttsp4-Fix-compile-issue.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/input-cyttsp4-Fix-compile-issue.patch
new file mode 100644
index 000000000000..dde944276549
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/input-cyttsp4-Fix-compile-issue.patch
@@ -0,0 +1,28 @@
+From 224d61a728afdbd5131719f99e33b6be432ea25c Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Fri, 22 Nov 2024 23:42:03 +0100
+Subject: input: cyttsp4: Fix compile issue
+
+We can't use {0} initializer with v6.12+
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/input/touchscreen/cyttsp4_core.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/input/touchscreen/cyttsp4_core.c b/drivers/input/touchscreen/cyttsp4_core.c
+index 67cb72ad6620..97264bfbfca4 100644
+--- a/drivers/input/touchscreen/cyttsp4_core.c
++++ b/drivers/input/touchscreen/cyttsp4_core.c
+@@ -851,7 +851,7 @@ static void cyttsp4_get_mt_touches(struct cyttsp4 *cd, int num_cur_tch)
+ 	struct cyttsp4_sysinfo *si = cd->si;
+ 	struct cyttsp4_touch tch;
+ 	int i, j, t = 0;
+-	int ids[max(CY_TMA1036_MAX_TCH, CY_TMA4XX_MAX_TCH)] = {0};
++	int ids[max(CY_TMA1036_MAX_TCH, CY_TMA4XX_MAX_TCH)] = {};
+ 	struct cyttsp4_signal_def* sig;
+ 
+ 	for (i = 0; i < num_cur_tch; i++) {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/input-cyttsp4-Fix-probe-oops.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/input-cyttsp4-Fix-probe-oops.patch
new file mode 100644
index 000000000000..aef98e65ef70
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/input-cyttsp4-Fix-probe-oops.patch
@@ -0,0 +1,29 @@
+From 4909c2986e0c930ce9ee49e30f53eae3a1fd5abd Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Fri, 11 Mar 2022 22:01:10 +0100
+Subject: input: cyttsp4: Fix probe oops
+
+__set_bit is called with bit offset -1 which causes oops.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/input/touchscreen/cyttsp4_core.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/input/touchscreen/cyttsp4_core.c b/drivers/input/touchscreen/cyttsp4_core.c
+index c353ac73c106..67cb72ad6620 100644
+--- a/drivers/input/touchscreen/cyttsp4_core.c
++++ b/drivers/input/touchscreen/cyttsp4_core.c
+@@ -1903,6 +1903,9 @@ static int cyttsp4_setup_input_device(struct cyttsp4 *cd)
+ 	for (i = 0; i < cd->n_signals; i++) {
+ 		signal = &cd->signals[i];
+ 
++		if (signal->signal < 0)
++			continue;
++
+ 		__set_bit(signal->signal, cd->input->absbit);
+ 
+ 		max = signal->max;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/input-cyttsp4-Fix-warnings.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/input-cyttsp4-Fix-warnings.patch
new file mode 100644
index 000000000000..d32a0d29921e
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/input-cyttsp4-Fix-warnings.patch
@@ -0,0 +1,47 @@
+From 46db61d367d9b20e72bb4660be54a418672262ec Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 7 Oct 2019 06:22:56 +0200
+Subject: input: cyttsp4: Fix warnings
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/input/touchscreen/cyttsp4_core.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/input/touchscreen/cyttsp4_core.c b/drivers/input/touchscreen/cyttsp4_core.c
+index 1ddb0b466a46..d9243c9db69a 100644
+--- a/drivers/input/touchscreen/cyttsp4_core.c
++++ b/drivers/input/touchscreen/cyttsp4_core.c
+@@ -1461,6 +1461,7 @@ static void cyttsp4_watchdog_work(struct work_struct *work)
+ 	return;
+ }
+ 
++#if 0
+ static int cyttsp4_set_power(struct cyttsp4* cd, int on)
+ {
+ 	dev_dbg(cd->dev, "Power %s\n", on ? "up" : "down");
+@@ -1476,6 +1477,7 @@ static int cyttsp4_set_power(struct cyttsp4* cd, int on)
+ 
+ 	return -ENOSYS;
+ }
++#endif
+ 
+ static int cyttsp4_core_sleep_(struct cyttsp4 *cd)
+ {
+@@ -1743,12 +1745,12 @@ static int cyttsp4_core_sleep(struct cyttsp4 *cd)
+ 
+ static int cyttsp4_core_wake_(struct cyttsp4 *cd)
+ {
++#if 0
+ 	struct device *dev = cd->dev;
+ 	int rc;
+ 	u8 mode;
+ 	int t;
+ 
+-#if 0
+ 	/* Already woken? */
+ 	mutex_lock(&cd->system_lock);
+ 	if (cd->sleep_state == SS_SLEEP_OFF) {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/input-cyttsp4-Make-the-driver-not-hog-the-system-s-workqueue.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/input-cyttsp4-Make-the-driver-not-hog-the-system-s-workqueue.patch
new file mode 100644
index 000000000000..919a6049cd55
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/input-cyttsp4-Make-the-driver-not-hog-the-system-s-workqueue.patch
@@ -0,0 +1,105 @@
+From 1445518f66b5f3d00bee5a10cf66fda0d0adae18 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 14 Oct 2019 18:00:32 +0200
+Subject: input: cyttsp4: Make the driver not hog the system's workqueue
+
+The driver's work items can take 100's of ms, use a separate
+thread for this.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/input/touchscreen/cyttsp4_core.c | 20 ++++++++++++++------
+ drivers/input/touchscreen/cyttsp4_core.h |  3 ++-
+ 2 files changed, 16 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/input/touchscreen/cyttsp4_core.c b/drivers/input/touchscreen/cyttsp4_core.c
+index d9243c9db69a..c353ac73c106 100644
+--- a/drivers/input/touchscreen/cyttsp4_core.c
++++ b/drivers/input/touchscreen/cyttsp4_core.c
+@@ -721,7 +721,7 @@ static void cyttsp4_queue_startup_(struct cyttsp4 *cd)
+ {
+ 	if (cd->startup_state == STARTUP_NONE) {
+ 		cd->startup_state = STARTUP_QUEUED;
+-		schedule_work(&cd->startup_work);
++		queue_work(cd->wq, &cd->startup_work);
+ 		dev_dbg(cd->dev, "%s: cyttsp4_startup queued\n", __func__);
+ 	} else {
+ 		dev_dbg(cd->dev, "%s: startup_state = %d\n", __func__,
+@@ -1237,9 +1237,7 @@ static void cyttsp4_watchdog_timer(struct timer_list *t)
+ 
+ 	dev_vdbg(cd->dev, "%s: Watchdog timer triggered\n", __func__);
+ 
+-	schedule_work(&cd->watchdog_work);
+-
+-	return;
++	queue_work(cd->wq, &cd->watchdog_work);
+ }
+ 
+ static int cyttsp4_request_exclusive(struct cyttsp4 *cd, void *ownptr,
+@@ -2048,6 +2046,13 @@ struct cyttsp4 *cyttsp4_probe(const struct cyttsp4_bus_ops *ops,
+ 		goto error_disable_vdd;
+ 	}
+ 
++	cd->wq = alloc_workqueue("cyttsp4", WQ_SYSFS, 0);
++	if (!cd->wq) {
++		rc = -ENOMEM;
++		dev_err(dev, "failed to allocate workqueue\n");
++		goto error_disable_vdd;
++	}
++
+ 	/* Initialize device info */
+ 	cd->dev = dev;
+ 	cd->bus_ops = ops;
+@@ -2071,7 +2076,7 @@ struct cyttsp4 *cyttsp4_probe(const struct cyttsp4_bus_ops *ops,
+ 	if (rc) {
+ 		dev_err(cd->dev, "failed to request IRQ %d, err: %d\n",
+ 			cd->irq, rc);
+-		goto error_disable_vdd;
++		goto error_free_wq;
+ 	}
+ 
+ 	/* Setup watchdog timer */
+@@ -2105,6 +2110,8 @@ struct cyttsp4 *cyttsp4_probe(const struct cyttsp4_bus_ops *ops,
+ 	cyttsp4_stop_wd_timer(cd);
+ 	pm_runtime_disable(dev);
+ 	cyttsp4_free_si_ptrs(cd);
++error_free_wq:
++	destroy_workqueue(cd->wq);
+ error_disable_vdd:
+ 	gpiod_set_value_cansleep(cd->reset_gpio, 1);
+ 	gpiod_set_value_cansleep(cd->power_gpio, 0);
+@@ -2132,8 +2139,9 @@ int cyttsp4_remove(struct cyttsp4 *cd)
+ 	pm_runtime_suspend(dev);
+ 	pm_runtime_disable(dev);
+ 
+-	cancel_work_sync(&cd->startup_work);
+ 	cyttsp4_stop_wd_timer(cd);
++	cancel_work_sync(&cd->startup_work);
++	destroy_workqueue(cd->wq);
+ 	cyttsp4_free_si_ptrs(cd);
+ 	return 0;
+ }
+diff --git a/drivers/input/touchscreen/cyttsp4_core.h b/drivers/input/touchscreen/cyttsp4_core.h
+index cff547979b28..ac2d7b303f39 100644
+--- a/drivers/input/touchscreen/cyttsp4_core.h
++++ b/drivers/input/touchscreen/cyttsp4_core.h
+@@ -62,7 +62,7 @@ enum cyttsp_cmd_bits {
+ };
+ 
+ /* Timeout in ms. */
+-#define CY_WATCHDOG_TIMEOUT		1000
++#define CY_WATCHDOG_TIMEOUT		10000
+ 
+ #define CY_MAX_PRINT_SIZE		512
+ #ifdef VERBOSE_DEBUG
+@@ -316,6 +316,7 @@ struct cyttsp4 {
+ 	enum cyttsp4_startup_state startup_state;
+ 	int int_status;
+ 	wait_queue_head_t wait_q;
++	struct workqueue_struct *wq;
+ 	int irq;
+ 	struct work_struct startup_work;
+ 	struct work_struct watchdog_work;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/input-cyttsp4-Port-the-driver-to-use-device-properties.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/input-cyttsp4-Port-the-driver-to-use-device-properties.patch
new file mode 100644
index 000000000000..da130be0533f
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/input-cyttsp4-Port-the-driver-to-use-device-properties.patch
@@ -0,0 +1,590 @@
+From 7fd7b9301fa4d426d48cc017cd1920cec28be8a0 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 1 Oct 2019 00:31:06 +0200
+Subject: input: cyttsp4: Port the driver to use device properties
+
+The driver has several unimplemented features, that are nevertheless
+expressed in its platform data. Drop this.
+
+If needed, interested parties can implement them properly in the
+future.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/input/touchscreen/cyttsp4_core.c | 234 +++++++++++------------
+ drivers/input/touchscreen/cyttsp4_core.h |  36 +++-
+ include/linux/platform_data/cyttsp4.h    |  70 -------
+ 3 files changed, 151 insertions(+), 189 deletions(-)
+
+diff --git a/drivers/input/touchscreen/cyttsp4_core.c b/drivers/input/touchscreen/cyttsp4_core.c
+index c30e2088c732..58eb9586a46f 100644
+--- a/drivers/input/touchscreen/cyttsp4_core.c
++++ b/drivers/input/touchscreen/cyttsp4_core.c
+@@ -17,7 +17,9 @@
+ #include <linux/gpio.h>
+ #include <linux/input/mt.h>
+ #include <linux/interrupt.h>
++#include <linux/of_device.h>
+ #include <linux/pm_runtime.h>
++#include <linux/property.h>
+ #include <linux/sched.h>
+ #include <linux/slab.h>
+ 
+@@ -131,23 +133,20 @@ static int cyttsp4_hw_soft_reset(struct cyttsp4 *cd)
+ 	return 0;
+ }
+ 
+-static int cyttsp4_hw_hard_reset(struct cyttsp4 *cd)
+-{
+-	if (cd->pdata->xres) {
+-		cd->pdata->xres(cd->pdata, cd->dev);
+-		dev_dbg(cd->dev, "%s: execute HARD reset\n", __func__);
+-		return 0;
+-	}
+-	dev_err(cd->dev, "%s: FAILED to execute HARD reset\n", __func__);
+-	return -ENOSYS;
+-}
+-
+ static int cyttsp4_hw_reset(struct cyttsp4 *cd)
+ {
+-	int rc = cyttsp4_hw_hard_reset(cd);
+-	if (rc == -ENOSYS)
+-		rc = cyttsp4_hw_soft_reset(cd);
+-	return rc;
++	if (!cd->reset_gpio)
++		return cyttsp4_hw_soft_reset(cd);
++
++	gpiod_set_value_cansleep(cd->reset_gpio, 1);
++	msleep(20);
++
++	gpiod_set_value_cansleep(cd->reset_gpio, 0);
++	msleep(40);
++
++	gpiod_set_value_cansleep(cd->reset_gpio, 1);
++	msleep(20);
++	return 0;
+ }
+ 
+ /*
+@@ -559,8 +558,8 @@ static int cyttsp4_si_get_btn_data(struct cyttsp4 *cd)
+ 
+ 		for (btn = 0; btn < si->si_ofs.num_btns; btn++) {
+ 			si->btn[btn].key_code = KEY_RESERVED;
+-			if (btn < cd->pdata->n_keys)
+-				si->btn[btn].key_code = cd->pdata->keys[btn].code;
++			if (btn < cd->n_keys)
++				si->btn[btn].key_code = cd->keys[btn].code;
+ 			si->btn[btn].state = CY_BTN_RELEASED;
+ 			si->btn[btn].enabled = true;
+ 		}
+@@ -803,13 +802,13 @@ static void cyttsp4_get_touch(struct cyttsp4 *cd,
+ 			touch->abs[abs], touch->abs[abs]);
+ 	}
+ 
+-	if (cd->pdata->flags & CY_FLAG_FLIP) {
++	if (cd->flags & CY_FLAG_FLIP) {
+ 		swap(touch->abs[CY_TCH_X], touch->abs[CY_TCH_Y]);
+ 		flipped = true;
+ 	} else
+ 		flipped = false;
+ 
+-	if (cd->pdata->flags & CY_FLAG_INV_X) {
++	if (cd->flags & CY_FLAG_INV_X) {
+ 		if (flipped)
+ 			touch->abs[CY_TCH_X] = cd->si->si_ofs.max_y -
+ 				touch->abs[CY_TCH_X];
+@@ -817,7 +816,7 @@ static void cyttsp4_get_touch(struct cyttsp4 *cd,
+ 			touch->abs[CY_TCH_X] = cd->si->si_ofs.max_x -
+ 				touch->abs[CY_TCH_X];
+ 	}
+-	if (cd->pdata->flags & CY_FLAG_INV_Y) {
++	if (cd->flags & CY_FLAG_INV_Y) {
+ 		if (flipped)
+ 			touch->abs[CY_TCH_Y] = cd->si->si_ofs.max_x -
+ 				touch->abs[CY_TCH_Y];
+@@ -828,8 +827,8 @@ static void cyttsp4_get_touch(struct cyttsp4 *cd,
+ 
+ 	dev_vdbg(dev, "%s: flip=%s inv-x=%s inv-y=%s x=%04X(%d) y=%04X(%d)\n",
+ 		__func__, flipped ? "true" : "false",
+-		cd->pdata->flags & CY_FLAG_INV_X ? "true" : "false",
+-		cd->pdata->flags & CY_FLAG_INV_Y ? "true" : "false",
++		cd->flags & CY_FLAG_INV_X ? "true" : "false",
++		cd->flags & CY_FLAG_INV_Y ? "true" : "false",
+ 		touch->abs[CY_TCH_X], touch->abs[CY_TCH_X],
+ 		touch->abs[CY_TCH_Y], touch->abs[CY_TCH_Y]);
+ }
+@@ -861,7 +860,7 @@ static void cyttsp4_get_mt_touches(struct cyttsp4 *cd, int num_cur_tch)
+ 		cyttsp4_get_touch(cd, &tch, si->xy_data +
+ 				  (i * si->si_ofs.tch_rec_size));
+ 
+-		sig = &cd->pdata->signals[CY_ABS_ID_OST];
++		sig = &cd->signals[CY_ABS_ID_OST];
+ 		if (tch.abs[CY_TCH_T] < sig->min ||
+ 			tch.abs[CY_TCH_T] > sig->max) {
+ 			dev_err(dev, "%s: tch=%d -> bad trk_id=%d max_id=%d\n",
+@@ -885,7 +884,7 @@ static void cyttsp4_get_mt_touches(struct cyttsp4 *cd, int num_cur_tch)
+ 
+ 		/* all devices: position and pressure fields */
+ 		for (j = 0; j <= CY_ABS_W_OST; j++) {
+-			sig = &cd->pdata->signals[j];
++			sig = &cd->signals[j];
+ 			if (sig->signal >= 0)
+ 				input_report_abs(cd->input, sig->signal,
+ 						 tch.abs[CY_TCH_X + j]);
+@@ -903,7 +902,7 @@ static void cyttsp4_get_mt_touches(struct cyttsp4 *cd, int num_cur_tch)
+ 
+ 			/* Get the extended touch fields */
+ 			for (j = 0; j < CY_NUM_EXT_TCH_FIELDS; j++) {
+-				sig = &cd->pdata->signals[CY_ABS_MAJ_OST + j];
++				sig = &cd->signals[CY_ABS_MAJ_OST + j];
+ 				if (sig->signal >= 0)
+ 					input_report_abs(cd->input, sig->signal,
+ 							 tch.abs[CY_TCH_MAJ + j]);
+@@ -1207,13 +1206,6 @@ static irqreturn_t cyttsp4_irq(int irq, void *handle)
+ 		dev_err(dev, "%s: Fail handshake mode=0x%02X r=%d\n",
+ 				__func__, mode[0], rc);
+ 
+-	/*
+-	 * a non-zero udelay period is required for using
+-	 * IRQF_TRIGGER_LOW in order to delay until the
+-	 * device completes isr deassert
+-	 */
+-	udelay(cd->pdata->level_irq_udelay);
+-
+ cyttsp4_irq_exit:
+ 	mutex_unlock(&cd->system_lock);
+ 	return IRQ_HANDLED;
+@@ -1471,6 +1463,22 @@ static void cyttsp4_watchdog_work(struct work_struct *work)
+ 	return;
+ }
+ 
++static int cyttsp4_set_power(struct cyttsp4* cd, int on)
++{
++	dev_dbg(cd->dev, "Power %s\n", on ? "up" : "down");
++
++	if (!cd->power_gpio)
++		return -ENOSYS;
++
++	//atomic_set(&cd->ignore_irq, 1);
++
++	//gpiod_set_value_cansleep(cd->power_gpio, on);
++
++	//atomic_set(&cd->ignore_irq, 0);
++
++	return -ENOSYS;
++}
++
+ static int cyttsp4_core_sleep_(struct cyttsp4 *cd)
+ {
+ 	enum cyttsp4_sleep_state ss = SS_SLEEP_ON;
+@@ -1517,13 +1525,7 @@ static int cyttsp4_core_sleep_(struct cyttsp4 *cd)
+ 	}
+ 	dev_vdbg(cd->dev, "%s: write DEEP SLEEP succeeded\n", __func__);
+ 
+-	if (cd->pdata->power) {
+-		dev_dbg(cd->dev, "%s: Power down HW\n", __func__);
+-		rc = cd->pdata->power(cd->pdata, 0, cd->dev, &cd->ignore_irq);
+-	} else {
+-		dev_dbg(cd->dev, "%s: No power function\n", __func__);
+-		rc = 0;
+-	}
++	rc = cyttsp4_set_power(cd, 0);
+ 	if (rc < 0) {
+ 		dev_err(cd->dev, "%s: HW Power down fails r=%d\n",
+ 				__func__, rc);
+@@ -1756,13 +1758,7 @@ static int cyttsp4_core_wake_(struct cyttsp4 *cd)
+ 	cd->int_status |= CY_INT_AWAKE;
+ 	cd->sleep_state = SS_WAKING;
+ 
+-	if (cd->pdata->power) {
+-		dev_dbg(dev, "%s: Power up HW\n", __func__);
+-		rc = cd->pdata->power(cd->pdata, 1, dev, &cd->ignore_irq);
+-	} else {
+-		dev_dbg(dev, "%s: No power function\n", __func__);
+-		rc = -ENOSYS;
+-	}
++	rc = cyttsp4_set_power(cd, 1);
+ 	if (rc < 0) {
+ 		if (rc != -ENOSYS)
+ 			dev_err(dev, "%s: HW Power up fails r=%d\n",
+@@ -1886,7 +1882,7 @@ static int cyttsp4_setup_input_device(struct cyttsp4 *cd)
+ 	max_y_tmp = cd->si->si_ofs.max_y;
+ 
+ 	/* get maximum values from the sysinfo data */
+-	if (cd->pdata->flags & CY_FLAG_FLIP) {
++	if (cd->flags & CY_FLAG_FLIP) {
+ 		max_x = max_y_tmp - 1;
+ 		max_y = max_x_tmp - 1;
+ 	} else {
+@@ -1896,8 +1892,8 @@ static int cyttsp4_setup_input_device(struct cyttsp4 *cd)
+ 	max_p = cd->si->si_ofs.max_p;
+ 
+ 	/* set event signal capabilities */
+-	for (i = 0; i < cd->pdata->n_signals; i++) {
+-		signal = &cd->pdata->signals[i];
++	for (i = 0; i < cd->n_signals; i++) {
++		signal = &cd->signals[i];
+ 
+ 		__set_bit(signal->signal, cd->input->absbit);
+ 
+@@ -1948,7 +1944,7 @@ static int cyttsp4_mt_probe(struct cyttsp4 *cd)
+ 		goto error_alloc_failed;
+ 	}
+ 
+-	cd->input->name = cd->pdata->inp_dev_name;
++	cd->input->name = "mt_ctp";
+ 	scnprintf(cd->phys, sizeof(cd->phys)-1, "%s", dev_name(dev));
+ 	cd->input->phys = cd->phys;
+ 	cd->input->id.bustype = cd->bus_ops->bustype;
+@@ -1973,38 +1969,77 @@ static int cyttsp4_mt_probe(struct cyttsp4 *cd)
+ 	return rc;
+ }
+ 
++static struct cyttsp4_signal_def cyttsp4_default_signals[CY_NUM_ABS_OST] = {
++	[CY_ABS_X_OST]   = { ABS_MT_POSITION_X, 0, 758, },
++	[CY_ABS_Y_OST]   = { ABS_MT_POSITION_Y, 0, 1024, },
++	[CY_ABS_P_OST]   = { ABS_MT_PRESSURE, 0, 255, },
++	[CY_ABS_W_OST]   = { -1 },
++	[CY_ABS_ID_OST]  = { ABS_MT_TRACKING_ID, 0, 15, },
++	[CY_ABS_MAJ_OST] = { ABS_MT_TOUCH_MAJOR, 0, 255, },
++	[CY_ABS_MIN_OST] = { ABS_MT_TOUCH_MINOR, 0, 255, },
++	[CY_ABS_OR_OST]  = { ABS_MT_ORIENTATION, -127, 127, },
++};
++
+ struct cyttsp4 *cyttsp4_probe(const struct cyttsp4_bus_ops *ops,
+ 		struct device *dev, u16 irq, size_t xfer_buf_size)
+ {
+ 	struct cyttsp4 *cd;
+-	struct cyttsp4_platform_data *pdata = dev_get_platdata(dev);
+-	unsigned long irq_flags;
+ 	int rc = 0;
+ 
+-	if (!pdata) {
+-		dev_err(dev, "%s: Missing platform data\n", __func__);
+-		rc = -ENODEV;
+-		goto error_no_pdata;
+-	}
+-
+-	cd = kzalloc(sizeof(*cd), GFP_KERNEL);
++	cd = devm_kzalloc(dev, sizeof(*cd), GFP_KERNEL);
+ 	if (!cd) {
+ 		dev_err(dev, "%s: Error, kzalloc\n", __func__);
+-		rc = -ENOMEM;
+-		goto error_alloc_data;
++		return ERR_PTR(-ENOMEM);
+ 	}
+ 
+-	cd->xfer_buf = kzalloc(xfer_buf_size, GFP_KERNEL);
++	cd->signals = cyttsp4_default_signals;
++	cd->n_signals = ARRAY_SIZE(cyttsp4_default_signals);
++
++	if (device_property_read_bool(dev, "flip"))
++		cd->flags |= CY_FLAG_FLIP;
++	if (device_property_read_bool(dev, "invert-x"))
++		cd->flags |= CY_FLAG_INV_X;
++	if (device_property_read_bool(dev, "invert-y"))
++		cd->flags |= CY_FLAG_INV_Y;
++
++	cd->vdd_supply = devm_regulator_get(dev, "vdd");
++	if (IS_ERR(cd->vdd_supply)) {
++		rc = PTR_ERR(cd->vdd_supply);
++		dev_err(dev, "can't get vdd power (%d)\n", rc);
++		return ERR_PTR(rc);
++	}
++
++	rc = regulator_enable(cd->vdd_supply);
++	if (rc) {
++		dev_err(dev, "can't enable vdd power (%d)\n", rc);
++		return ERR_PTR(rc);
++	}
++
++	cd->power_gpio = devm_gpiod_get(dev, "power", GPIOD_OUT_HIGH);
++	if (IS_ERR(cd->reset_gpio)) {
++		rc = PTR_ERR(cd->reset_gpio);
++		dev_err(dev, "can't get reset gpio (%d)\n", rc);
++		return ERR_PTR(rc);
++	}
++
++	cd->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
++	if (IS_ERR(cd->reset_gpio)) {
++		rc = PTR_ERR(cd->reset_gpio);
++		dev_err(dev, "can't get reset gpio (%d)\n", rc);
++		return ERR_PTR(rc);
++	}
++
++	cd->xfer_buf = devm_kzalloc(dev, xfer_buf_size, GFP_KERNEL);
+ 	if (!cd->xfer_buf) {
+ 		dev_err(dev, "%s: Error, kzalloc\n", __func__);
+ 		rc = -ENOMEM;
+-		goto error_free_cd;
++		goto error_disable_vdd;
+ 	}
+ 
+ 	/* Initialize device info */
+ 	cd->dev = dev;
+-	cd->pdata = pdata;
+ 	cd->bus_ops = ops;
++	dev_set_drvdata(dev, cd);
+ 
+ 	/* Initialize mutexes and spinlocks */
+ 	mutex_init(&cd->system_lock);
+@@ -2018,43 +2053,20 @@ struct cyttsp4 *cyttsp4_probe(const struct cyttsp4_bus_ops *ops,
+ 	INIT_WORK(&cd->watchdog_work, cyttsp4_watchdog_work);
+ 
+ 	/* Initialize IRQ */
+-	cd->irq = gpio_to_irq(cd->pdata->irq_gpio);
+-	if (cd->irq < 0) {
+-		rc = -EINVAL;
+-		goto error_free_xfer;
+-	}
+-
+-	dev_set_drvdata(dev, cd);
+-
+-	/* Call platform init function */
+-	if (cd->pdata->init) {
+-		dev_dbg(cd->dev, "%s: Init HW\n", __func__);
+-		rc = cd->pdata->init(cd->pdata, 1, cd->dev);
+-	} else {
+-		dev_dbg(cd->dev, "%s: No HW INIT function\n", __func__);
+-		rc = 0;
+-	}
+-	if (rc < 0)
+-		dev_err(cd->dev, "%s: HW Init fail r=%d\n", __func__, rc);
+-
+-	dev_dbg(dev, "%s: initialize threaded irq=%d\n", __func__, cd->irq);
+-	if (cd->pdata->level_irq_udelay > 0)
+-		/* use level triggered interrupts */
+-		irq_flags = IRQF_TRIGGER_LOW | IRQF_ONESHOT;
+-	else
+-		/* use edge triggered interrupts */
+-		irq_flags = IRQF_TRIGGER_FALLING | IRQF_ONESHOT;
+-
+-	rc = request_threaded_irq(cd->irq, NULL, cyttsp4_irq, irq_flags,
+-		dev_name(dev), cd);
+-	if (rc < 0) {
+-		dev_err(dev, "%s: Error, could not request irq\n", __func__);
+-		goto error_request_irq;
++	rc = devm_request_threaded_irq(dev, cd->irq, NULL, cyttsp4_irq,
++				       IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
++				       dev_name(dev), cd);
++	if (rc) {
++		dev_err(cd->dev, "failed to request IRQ %d, err: %d\n",
++			cd->irq, rc);
++		goto error_disable_vdd;
+ 	}
+ 
+ 	/* Setup watchdog timer */
+ 	timer_setup(&cd->watchdog_timer, cyttsp4_watchdog_timer, 0);
+ 
++	//XXX: msleep(300);
++
+ 	/*
+ 	 * call startup directly to ensure that the device
+ 	 * is tested before leaving the probe
+@@ -2062,17 +2074,15 @@ struct cyttsp4 *cyttsp4_probe(const struct cyttsp4_bus_ops *ops,
+ 	rc = cyttsp4_startup(cd);
+ 
+ 	/* Do not fail probe if startup fails but the device is detected */
+-	if (rc < 0 && cd->mode == CY_MODE_UNKNOWN) {
+-		dev_err(cd->dev, "%s: Fail initial startup r=%d\n",
++	if (rc && cd->mode == CY_MODE_UNKNOWN) {
++		dev_err(cd->dev, "%s: Fail initial startup rc=%d\n",
+ 			__func__, rc);
+ 		goto error_startup;
+ 	}
+ 
+ 	rc = cyttsp4_mt_probe(cd);
+-	if (rc < 0) {
+-		dev_err(dev, "%s: Error, fail mt probe\n", __func__);
++	if (rc)
+ 		goto error_startup;
+-	}
+ 
+ 	pm_runtime_enable(dev);
+ 
+@@ -2083,17 +2093,10 @@ struct cyttsp4 *cyttsp4_probe(const struct cyttsp4_bus_ops *ops,
+ 	cyttsp4_stop_wd_timer(cd);
+ 	pm_runtime_disable(dev);
+ 	cyttsp4_free_si_ptrs(cd);
+-	free_irq(cd->irq, cd);
+-error_request_irq:
+-	if (cd->pdata->init)
+-		cd->pdata->init(cd->pdata, 0, dev);
+-error_free_xfer:
+-	kfree(cd->xfer_buf);
+-error_free_cd:
+-	kfree(cd);
+-error_alloc_data:
+-error_no_pdata:
+-	dev_err(dev, "%s failed.\n", __func__);
++error_disable_vdd:
++	gpiod_set_value_cansleep(cd->reset_gpio, 1);
++	gpiod_set_value_cansleep(cd->power_gpio, 0);
++	regulator_disable(cd->vdd_supply);
+ 	return ERR_PTR(rc);
+ }
+ EXPORT_SYMBOL_GPL(cyttsp4_probe);
+@@ -2118,14 +2121,8 @@ int cyttsp4_remove(struct cyttsp4 *cd)
+ 	pm_runtime_disable(dev);
+ 
+ 	cancel_work_sync(&cd->startup_work);
+-
+ 	cyttsp4_stop_wd_timer(cd);
+-
+-	free_irq(cd->irq, cd);
+-	if (cd->pdata->init)
+-		cd->pdata->init(cd->pdata, 0, dev);
+ 	cyttsp4_free_si_ptrs(cd);
+-	kfree(cd);
+ 	return 0;
+ }
+ EXPORT_SYMBOL_GPL(cyttsp4_remove);
+@@ -2133,3 +2130,4 @@ EXPORT_SYMBOL_GPL(cyttsp4_remove);
+ MODULE_LICENSE("GPL");
+ MODULE_DESCRIPTION("Cypress TrueTouch(R) Standard touchscreen core driver");
+ MODULE_AUTHOR("Cypress");
++MODULE_AUTHOR("Ondrej Jirman <megi@xff.cz>");
+diff --git a/drivers/input/touchscreen/cyttsp4_core.h b/drivers/input/touchscreen/cyttsp4_core.h
+index 995bfd0a54d0..cff547979b28 100644
+--- a/drivers/input/touchscreen/cyttsp4_core.h
++++ b/drivers/input/touchscreen/cyttsp4_core.h
+@@ -24,6 +24,8 @@
+ #include <linux/stringify.h>
+ #include <linux/types.h>
+ #include <linux/platform_data/cyttsp4.h>
++#include <linux/regulator/consumer.h>
++#include <linux/gpio.h>
+ 
+ #define CY_REG_BASE			0x00
+ 
+@@ -329,12 +331,19 @@ struct cyttsp4 {
+ 	bool is_suspended;
+ 	char phys[NAME_MAX];
+ 	int num_prv_tch;
+-	struct cyttsp4_platform_data *pdata;
+ 	const struct cyttsp4_bus_ops *bus_ops;
+ 	u8 *xfer_buf;
+ #ifdef VERBOSE_DEBUG
+ 	u8 pr_buf[CY_MAX_PRBUF_SIZE];
+ #endif
++	int flags;
++	int n_signals;
++	struct cyttsp4_signal_def *signals;
++	int n_keys;
++	struct cyttsp4_virtual_key* keys;
++	struct gpio_desc *reset_gpio;
++	struct gpio_desc *power_gpio;
++	struct regulator *vdd_supply;
+ };
+ 
+ struct cyttsp4_bus_ops {
+@@ -392,6 +401,31 @@ enum cyttsp4_event_id {
+ /* y-axis, 0:origin is on top side of panel, 1: bottom */
+ #define CY_PCFG_ORIGIN_Y_MASK		0x80
+ 
++/* abs axis signal offsets in the signals array  */
++enum cyttsp4_sig_ost {
++	CY_ABS_X_OST,
++	CY_ABS_Y_OST,
++	CY_ABS_P_OST,
++	CY_ABS_W_OST,
++	CY_ABS_ID_OST,
++	CY_ABS_MAJ_OST,
++	CY_ABS_MIN_OST,
++	CY_ABS_OR_OST,
++	CY_NUM_ABS_OST	/* number of abs signals */
++};
++
++struct cyttsp4_virtual_key {
++	int code;
++};
++
++struct cyttsp4_signal_def {
++	int signal;
++	int min;
++	int max;
++	int fuzz;
++	int flat;
++};
++
+ static inline int cyttsp4_adap_read(struct cyttsp4 *ts, u16 addr, int size,
+ 		void *buf)
+ {
+diff --git a/include/linux/platform_data/cyttsp4.h b/include/linux/platform_data/cyttsp4.h
+index e718d2204ce7..e69de29bb2d1 100644
+--- a/include/linux/platform_data/cyttsp4.h
++++ b/include/linux/platform_data/cyttsp4.h
+@@ -1,70 +0,0 @@
+-/* SPDX-License-Identifier: GPL-2.0-only */
+-/*
+- * Header file for:
+- * Cypress TrueTouch(TM) Standard Product (TTSP) touchscreen drivers.
+- * For use with Cypress Txx3xx parts.
+- * Supported parts include:
+- * CY8CTST341
+- * CY8CTMA340
+- *
+- * Copyright (C) 2009, 2010, 2011 Cypress Semiconductor, Inc.
+- * Copyright (C) 2012 Javier Martinez Canillas <javier@dowhile0.org>
+- *
+- * Contact Cypress Semiconductor at www.cypress.com (kev@cypress.com)
+- */
+-#ifndef _CYTTSP4_H_
+-#define _CYTTSP4_H_
+-
+-#define CYTTSP4_MT_NAME "cyttsp4_mt"
+-
+-#define CY_TOUCH_SETTINGS_MAX 32
+-
+-/* abs axis signal offsets in the signals array  */
+-enum cyttsp4_sig_ost {
+-	CY_ABS_X_OST,
+-	CY_ABS_Y_OST,
+-	CY_ABS_P_OST,
+-	CY_ABS_W_OST,
+-	CY_ABS_ID_OST,
+-	CY_ABS_MAJ_OST,
+-	CY_ABS_MIN_OST,
+-	CY_ABS_OR_OST,
+-	CY_NUM_ABS_OST	/* number of abs signals */
+-};
+-
+-struct cyttsp4_virtual_key {
+-	int code;
+-};
+-
+-struct cyttsp4_signal_def {
+-	int signal;
+-	int min;
+-	int max;
+-	int fuzz;
+-	int flat;
+-};
+-
+-struct cyttsp4_platform_data {
+-	char const *inp_dev_name;
+-	unsigned short flags;
+-
+-	int irq_gpio;
+-	int rst_gpio;
+-	int level_irq_udelay;
+-	int (*xres)(struct cyttsp4_platform_data *pdata,
+-		struct device *dev);
+-	int (*init)(struct cyttsp4_platform_data *pdata,
+-		int on, struct device *dev);
+-	int (*power)(struct cyttsp4_platform_data *pdata,
+-		int on, struct device *dev, atomic_t *ignore_irq);
+-	int (*irq_stat)(struct cyttsp4_platform_data *pdata,
+-		struct device *dev);
+-
+-	int n_signals;
+-	struct cyttsp4_signal_def *signals;
+-
+-	int n_keys;
+-	struct cyttsp4_virtual_key* keys;
+-};
+-
+-#endif /* _CYTTSP4_H_ */
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/input-cyttsp4-Remove-unused-enable_vkeys.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/input-cyttsp4-Remove-unused-enable_vkeys.patch
new file mode 100644
index 000000000000..bd63188556a9
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/input-cyttsp4-Remove-unused-enable_vkeys.patch
@@ -0,0 +1,27 @@
+From 20f3eaeeca3ca518b9f5d566ea206afc70569569 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 28 Sep 2019 15:06:16 +0200
+Subject: input: cyttsp4: Remove unused enable_vkeys
+
+It doesn't seem to be used anywhere.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ include/linux/platform_data/cyttsp4.h | 1 -
+ 1 file changed, 1 deletion(-)
+
+diff --git a/include/linux/platform_data/cyttsp4.h b/include/linux/platform_data/cyttsp4.h
+index 1f945aa2466e..362fa181ac04 100644
+--- a/include/linux/platform_data/cyttsp4.h
++++ b/include/linux/platform_data/cyttsp4.h
+@@ -24,7 +24,6 @@
+ struct touch_framework {
+ 	const uint16_t  *abs;
+ 	uint8_t         size;
+-	uint8_t         enable_vkeys;
+ } __packed;
+ 
+ struct cyttsp4_virtual_key {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/input-cyttsp4-Remove-useless-indirection-with-driver-platform-d.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/input-cyttsp4-Remove-useless-indirection-with-driver-platform-d.patch
new file mode 100644
index 000000000000..30fc8a645f29
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/input-cyttsp4-Remove-useless-indirection-with-driver-platform-d.patch
@@ -0,0 +1,718 @@
+From c384e31b371b8cd94b47ed60fc35c0f72247b71a Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 28 Sep 2019 15:05:39 +0200
+Subject: input: cyttsp4: Remove useless indirection with driver/platform data
+
+It is not necessary to have struct cyttsp4_mt_data fields separate
+from struct cyttsp4, as cyttsp4_mt_data was embedded as 'md' field
+anyway.
+
+The same goes for struct cyttsp4_mt_platform_data.
+
+Remove all this indirection.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/input/touchscreen/cyttsp4_core.c | 233 +++++++++++------------
+ drivers/input/touchscreen/cyttsp4_core.h |  18 +-
+ include/linux/platform_data/cyttsp4.h    |  26 +--
+ 3 files changed, 128 insertions(+), 149 deletions(-)
+
+diff --git a/drivers/input/touchscreen/cyttsp4_core.c b/drivers/input/touchscreen/cyttsp4_core.c
+index f2dd87cdeb8f..867c18abc89b 100644
+--- a/drivers/input/touchscreen/cyttsp4_core.c
++++ b/drivers/input/touchscreen/cyttsp4_core.c
+@@ -133,8 +133,8 @@ static int cyttsp4_hw_soft_reset(struct cyttsp4 *cd)
+ 
+ static int cyttsp4_hw_hard_reset(struct cyttsp4 *cd)
+ {
+-	if (cd->cpdata->xres) {
+-		cd->cpdata->xres(cd->cpdata, cd->dev);
++	if (cd->pdata->xres) {
++		cd->pdata->xres(cd->pdata, cd->dev);
+ 		dev_dbg(cd->dev, "%s: execute HARD reset\n", __func__);
+ 		return 0;
+ 	}
+@@ -559,8 +559,8 @@ static int cyttsp4_si_get_btn_data(struct cyttsp4 *cd)
+ 
+ 		for (btn = 0; btn < si->si_ofs.num_btns; btn++) {
+ 			si->btn[btn].key_code = KEY_RESERVED;
+-			if (btn < cd->cpdata->n_keys)
+-				si->btn[btn].key_code = cd->cpdata->keys[btn].code;
++			if (btn < cd->pdata->n_keys)
++				si->btn[btn].key_code = cd->pdata->keys[btn].code;
+ 			si->btn[btn].state = CY_BTN_RELEASED;
+ 			si->btn[btn].enabled = true;
+ 		}
+@@ -732,41 +732,41 @@ static void cyttsp4_queue_startup_(struct cyttsp4 *cd)
+ 	}
+ }
+ 
+-static void cyttsp4_report_slot_liftoff(struct cyttsp4_mt_data *md,
++static void cyttsp4_report_slot_liftoff(struct cyttsp4 *cd,
+ 		int max_slots)
+ {
+ 	int t;
+ 
+-	if (md->num_prv_tch == 0)
++	if (cd->num_prv_tch == 0)
+ 		return;
+ 
+ 	for (t = 0; t < max_slots; t++) {
+-		input_mt_slot(md->input, t);
+-		input_mt_report_slot_inactive(md->input);
++		input_mt_slot(cd->input, t);
++		input_mt_report_slot_inactive(cd->input);
+ 	}
+ }
+ 
+-static void cyttsp4_lift_all(struct cyttsp4_mt_data *md)
++static void cyttsp4_lift_all(struct cyttsp4 *cd)
+ {
+-	if (!md->si)
++	if (!cd->si)
+ 		return;
+ 
+-	if (md->num_prv_tch != 0) {
+-		cyttsp4_report_slot_liftoff(md,
+-				md->si->si_ofs.tch_abs[CY_TCH_T].max);
+-		input_sync(md->input);
+-		md->num_prv_tch = 0;
++	if (cd->num_prv_tch != 0) {
++		cyttsp4_report_slot_liftoff(cd,
++				cd->si->si_ofs.tch_abs[CY_TCH_T].max);
++		input_sync(cd->input);
++		cd->num_prv_tch = 0;
+ 	}
+ }
+ 
+-static void cyttsp4_get_touch_axis(struct cyttsp4_mt_data *md,
++static void cyttsp4_get_touch_axis(struct cyttsp4 *cd,
+ 	int *axis, int size, int max, u8 *xy_data, int bofs)
+ {
+ 	int nbyte;
+ 	int next;
+ 
+ 	for (nbyte = 0, *axis = 0, next = 0; nbyte < size; nbyte++) {
+-		dev_vdbg(&md->input->dev,
++		dev_vdbg(&cd->input->dev,
+ 			"%s: *axis=%02X(%d) size=%d max=%08X xy_data=%p"
+ 			" xy_data[%d]=%02X(%d) bofs=%d\n",
+ 			__func__, *axis, *axis, size, max, xy_data, next,
+@@ -777,23 +777,23 @@ static void cyttsp4_get_touch_axis(struct cyttsp4_mt_data *md,
+ 
+ 	*axis &= max - 1;
+ 
+-	dev_vdbg(&md->input->dev,
++	dev_vdbg(&cd->input->dev,
+ 		"%s: *axis=%02X(%d) size=%d max=%08X xy_data=%p"
+ 		" xy_data[%d]=%02X(%d)\n",
+ 		__func__, *axis, *axis, size, max, xy_data, next,
+ 		xy_data[next], xy_data[next]);
+ }
+ 
+-static void cyttsp4_get_touch(struct cyttsp4_mt_data *md,
++static void cyttsp4_get_touch(struct cyttsp4 *cd,
+ 	struct cyttsp4_touch *touch, u8 *xy_data)
+ {
+-	struct device *dev = &md->input->dev;
+-	struct cyttsp4_sysinfo *si = md->si;
++	struct device *dev = &cd->input->dev;
++	struct cyttsp4_sysinfo *si = cd->si;
+ 	enum cyttsp4_tch_abs abs;
+ 	bool flipped;
+ 
+ 	for (abs = CY_TCH_X; abs < CY_TCH_NUM_ABS; abs++) {
+-		cyttsp4_get_touch_axis(md, &touch->abs[abs],
++		cyttsp4_get_touch_axis(cd, &touch->abs[abs],
+ 			si->si_ofs.tch_abs[abs].size,
+ 			si->si_ofs.tch_abs[abs].max,
+ 			xy_data + si->si_ofs.tch_abs[abs].ofs,
+@@ -803,33 +803,33 @@ static void cyttsp4_get_touch(struct cyttsp4_mt_data *md,
+ 			touch->abs[abs], touch->abs[abs]);
+ 	}
+ 
+-	if (md->pdata->flags & CY_FLAG_FLIP) {
++	if (cd->pdata->flags & CY_FLAG_FLIP) {
+ 		swap(touch->abs[CY_TCH_X], touch->abs[CY_TCH_Y]);
+ 		flipped = true;
+ 	} else
+ 		flipped = false;
+ 
+-	if (md->pdata->flags & CY_FLAG_INV_X) {
++	if (cd->pdata->flags & CY_FLAG_INV_X) {
+ 		if (flipped)
+-			touch->abs[CY_TCH_X] = md->si->si_ofs.max_y -
++			touch->abs[CY_TCH_X] = cd->si->si_ofs.max_y -
+ 				touch->abs[CY_TCH_X];
+ 		else
+-			touch->abs[CY_TCH_X] = md->si->si_ofs.max_x -
++			touch->abs[CY_TCH_X] = cd->si->si_ofs.max_x -
+ 				touch->abs[CY_TCH_X];
+ 	}
+-	if (md->pdata->flags & CY_FLAG_INV_Y) {
++	if (cd->pdata->flags & CY_FLAG_INV_Y) {
+ 		if (flipped)
+-			touch->abs[CY_TCH_Y] = md->si->si_ofs.max_x -
++			touch->abs[CY_TCH_Y] = cd->si->si_ofs.max_x -
+ 				touch->abs[CY_TCH_Y];
+ 		else
+-			touch->abs[CY_TCH_Y] = md->si->si_ofs.max_y -
++			touch->abs[CY_TCH_Y] = cd->si->si_ofs.max_y -
+ 				touch->abs[CY_TCH_Y];
+ 	}
+ 
+ 	dev_vdbg(dev, "%s: flip=%s inv-x=%s inv-y=%s x=%04X(%d) y=%04X(%d)\n",
+ 		__func__, flipped ? "true" : "false",
+-		md->pdata->flags & CY_FLAG_INV_X ? "true" : "false",
+-		md->pdata->flags & CY_FLAG_INV_Y ? "true" : "false",
++		cd->pdata->flags & CY_FLAG_INV_X ? "true" : "false",
++		cd->pdata->flags & CY_FLAG_INV_Y ? "true" : "false",
+ 		touch->abs[CY_TCH_X], touch->abs[CY_TCH_X],
+ 		touch->abs[CY_TCH_Y], touch->abs[CY_TCH_Y]);
+ }
+@@ -848,10 +848,10 @@ static void cyttsp4_final_sync(struct input_dev *input, int max_slots, int *ids)
+ 	input_sync(input);
+ }
+ 
+-static void cyttsp4_get_mt_touches(struct cyttsp4_mt_data *md, int num_cur_tch)
++static void cyttsp4_get_mt_touches(struct cyttsp4 *cd, int num_cur_tch)
+ {
+-	struct device *dev = &md->input->dev;
+-	struct cyttsp4_sysinfo *si = md->si;
++	struct device *dev = &cd->input->dev;
++	struct cyttsp4_sysinfo *si = cd->si;
+ 	struct cyttsp4_touch tch;
+ 	int sig;
+ 	int i, j, t = 0;
+@@ -859,42 +859,42 @@ static void cyttsp4_get_mt_touches(struct cyttsp4_mt_data *md, int num_cur_tch)
+ 
+ 	memset(ids, 0, si->si_ofs.tch_abs[CY_TCH_T].max * sizeof(int));
+ 	for (i = 0; i < num_cur_tch; i++) {
+-		cyttsp4_get_touch(md, &tch, si->xy_data +
++		cyttsp4_get_touch(cd, &tch, si->xy_data +
+ 			(i * si->si_ofs.tch_rec_size));
+-		if ((tch.abs[CY_TCH_T] < md->pdata->frmwrk->abs
++		if ((tch.abs[CY_TCH_T] < cd->pdata->frmwrk->abs
+ 			[(CY_ABS_ID_OST * CY_NUM_ABS_SET) + CY_MIN_OST]) ||
+-			(tch.abs[CY_TCH_T] > md->pdata->frmwrk->abs
++			(tch.abs[CY_TCH_T] > cd->pdata->frmwrk->abs
+ 			[(CY_ABS_ID_OST * CY_NUM_ABS_SET) + CY_MAX_OST])) {
+ 			dev_err(dev, "%s: tch=%d -> bad trk_id=%d max_id=%d\n",
+ 				__func__, i, tch.abs[CY_TCH_T],
+-				md->pdata->frmwrk->abs[(CY_ABS_ID_OST *
++				cd->pdata->frmwrk->abs[(CY_ABS_ID_OST *
+ 				CY_NUM_ABS_SET) + CY_MAX_OST]);
+ 			continue;
+ 		}
+ 
+ 		/* use 0 based track id's */
+-		sig = md->pdata->frmwrk->abs
++		sig = cd->pdata->frmwrk->abs
+ 			[(CY_ABS_ID_OST * CY_NUM_ABS_SET) + 0];
+ 		if (sig != CY_IGNORE_VALUE) {
+-			t = tch.abs[CY_TCH_T] - md->pdata->frmwrk->abs
++			t = tch.abs[CY_TCH_T] - cd->pdata->frmwrk->abs
+ 				[(CY_ABS_ID_OST * CY_NUM_ABS_SET) + CY_MIN_OST];
+ 			if (tch.abs[CY_TCH_E] == CY_EV_LIFTOFF) {
+ 				dev_dbg(dev, "%s: t=%d e=%d lift-off\n",
+ 					__func__, t, tch.abs[CY_TCH_E]);
+ 				goto cyttsp4_get_mt_touches_pr_tch;
+ 			}
+-			input_mt_slot(md->input, t);
+-			input_mt_report_slot_state(md->input, MT_TOOL_FINGER,
++			input_mt_slot(cd->input, t);
++			input_mt_report_slot_state(cd->input, MT_TOOL_FINGER,
+ 					true);
+ 			ids[t] = true;
+ 		}
+ 
+ 		/* all devices: position and pressure fields */
+ 		for (j = 0; j <= CY_ABS_W_OST; j++) {
+-			sig = md->pdata->frmwrk->abs[((CY_ABS_X_OST + j) *
++			sig = cd->pdata->frmwrk->abs[((CY_ABS_X_OST + j) *
+ 				CY_NUM_ABS_SET) + 0];
+ 			if (sig != CY_IGNORE_VALUE)
+-				input_report_abs(md->input, sig,
++				input_report_abs(cd->input, sig,
+ 					tch.abs[CY_TCH_X + j]);
+ 		}
+ 		if (si->si_ofs.tch_rec_size > CY_TMA1036_TCH_REC_SIZE) {
+@@ -909,11 +909,11 @@ static void cyttsp4_get_mt_touches(struct cyttsp4_mt_data *md, int num_cur_tch)
+ 
+ 			/* Get the extended touch fields */
+ 			for (j = 0; j < CY_NUM_EXT_TCH_FIELDS; j++) {
+-				sig = md->pdata->frmwrk->abs
++				sig = cd->pdata->frmwrk->abs
+ 					[((CY_ABS_MAJ_OST + j) *
+ 					CY_NUM_ABS_SET) + 0];
+ 				if (sig != CY_IGNORE_VALUE)
+-					input_report_abs(md->input, sig,
++					input_report_abs(cd->input, sig,
+ 						tch.abs[CY_TCH_MAJ + j]);
+ 			}
+ 		}
+@@ -940,9 +940,9 @@ static void cyttsp4_get_mt_touches(struct cyttsp4_mt_data *md, int num_cur_tch)
+ 				tch.abs[CY_TCH_E]);
+ 	}
+ 
+-	cyttsp4_final_sync(md->input, si->si_ofs.tch_abs[CY_TCH_T].max, ids);
++	cyttsp4_final_sync(cd->input, si->si_ofs.tch_abs[CY_TCH_T].max, ids);
+ 
+-	md->num_prv_tch = num_cur_tch;
++	cd->num_prv_tch = num_cur_tch;
+ 
+ 	return;
+ }
+@@ -950,9 +950,8 @@ static void cyttsp4_get_mt_touches(struct cyttsp4_mt_data *md, int num_cur_tch)
+ /* read xy_data for all current touches */
+ static int cyttsp4_xy_worker(struct cyttsp4 *cd)
+ {
+-	struct cyttsp4_mt_data *md = &cd->md;
+-	struct device *dev = &md->input->dev;
+-	struct cyttsp4_sysinfo *si = md->si;
++	struct device *dev = &cd->input->dev;
++	struct cyttsp4_sysinfo *si = cd->si;
+ 	u8 num_cur_tch;
+ 	u8 hst_mode;
+ 	u8 rep_len;
+@@ -1024,9 +1023,9 @@ static int cyttsp4_xy_worker(struct cyttsp4 *cd)
+ 	dev_vdbg(dev, "%s: extract data num_cur_tch=%d\n", __func__,
+ 		num_cur_tch);
+ 	if (num_cur_tch)
+-		cyttsp4_get_mt_touches(md, num_cur_tch);
++		cyttsp4_get_mt_touches(cd, num_cur_tch);
+ 	else
+-		cyttsp4_lift_all(md);
++		cyttsp4_lift_all(cd);
+ 
+ 	rc = 0;
+ 
+@@ -1037,21 +1036,20 @@ static int cyttsp4_xy_worker(struct cyttsp4 *cd)
+ static int cyttsp4_mt_attention(struct cyttsp4 *cd)
+ {
+ 	struct device *dev = cd->dev;
+-	struct cyttsp4_mt_data *md = &cd->md;
+ 	int rc = 0;
+ 
+-	if (!md->si)
++	if (!cd->si)
+ 		return 0;
+ 
+-	mutex_lock(&md->report_lock);
+-	if (!md->is_suspended) {
++	mutex_lock(&cd->report_lock);
++	if (!cd->is_suspended) {
+ 		/* core handles handshake */
+ 		rc = cyttsp4_xy_worker(cd);
+ 	} else {
+ 		dev_vdbg(dev, "%s: Ignoring report while suspended\n",
+ 			__func__);
+ 	}
+-	mutex_unlock(&md->report_lock);
++	mutex_unlock(&cd->report_lock);
+ 	if (rc < 0)
+ 		dev_err(dev, "%s: xy_worker error r=%d\n", __func__, rc);
+ 
+@@ -1222,7 +1220,7 @@ static irqreturn_t cyttsp4_irq(int irq, void *handle)
+ 	 * IRQF_TRIGGER_LOW in order to delay until the
+ 	 * device completes isr deassert
+ 	 */
+-	udelay(cd->cpdata->level_irq_udelay);
++	udelay(cd->pdata->level_irq_udelay);
+ 
+ cyttsp4_irq_exit:
+ 	mutex_unlock(&cd->system_lock);
+@@ -1527,9 +1525,9 @@ static int cyttsp4_core_sleep_(struct cyttsp4 *cd)
+ 	}
+ 	dev_vdbg(cd->dev, "%s: write DEEP SLEEP succeeded\n", __func__);
+ 
+-	if (cd->cpdata->power) {
++	if (cd->pdata->power) {
+ 		dev_dbg(cd->dev, "%s: Power down HW\n", __func__);
+-		rc = cd->cpdata->power(cd->cpdata, 0, cd->dev, &cd->ignore_irq);
++		rc = cd->pdata->power(cd->pdata, 0, cd->dev, &cd->ignore_irq);
+ 	} else {
+ 		dev_dbg(cd->dev, "%s: No power function\n", __func__);
+ 		rc = 0;
+@@ -1644,7 +1642,7 @@ static int cyttsp4_startup_(struct cyttsp4 *cd)
+ 		goto exit;
+ 	}
+ 
+-	cyttsp4_lift_all(&cd->md);
++	cyttsp4_lift_all(cd);
+ 
+ 	/* restore to sleep if was suspended */
+ 	mutex_lock(&cd->system_lock);
+@@ -1766,9 +1764,9 @@ static int cyttsp4_core_wake_(struct cyttsp4 *cd)
+ 	cd->int_status |= CY_INT_AWAKE;
+ 	cd->sleep_state = SS_WAKING;
+ 
+-	if (cd->cpdata->power) {
++	if (cd->pdata->power) {
+ 		dev_dbg(dev, "%s: Power up HW\n", __func__);
+-		rc = cd->cpdata->power(cd->cpdata, 1, dev, &cd->ignore_irq);
++		rc = cd->pdata->power(cd->pdata, 1, dev, &cd->ignore_irq);
+ 	} else {
+ 		dev_dbg(dev, "%s: No power function\n", __func__);
+ 		rc = -ENOSYS;
+@@ -1830,10 +1828,9 @@ static int cyttsp4_core_wake(struct cyttsp4 *cd)
+ static int cyttsp4_core_suspend(struct device *dev)
+ {
+ 	struct cyttsp4 *cd = dev_get_drvdata(dev);
+-	struct cyttsp4_mt_data *md = &cd->md;
+ 	int rc;
+ 
+-	md->is_suspended = true;
++	cd->is_suspended = true;
+ 
+ 	rc = cyttsp4_core_sleep(cd);
+ 	if (rc < 0) {
+@@ -1846,10 +1843,9 @@ static int cyttsp4_core_suspend(struct device *dev)
+ static int cyttsp4_core_resume(struct device *dev)
+ {
+ 	struct cyttsp4 *cd = dev_get_drvdata(dev);
+-	struct cyttsp4_mt_data *md = &cd->md;
+ 	int rc;
+ 
+-	md->is_suspended = false;
++	cd->is_suspended = false;
+ 
+ 	rc = cyttsp4_core_wake(cd);
+ 	if (rc < 0) {
+@@ -1871,18 +1867,17 @@ static int cyttsp4_mt_open(struct input_dev *input)
+ 
+ static void cyttsp4_mt_close(struct input_dev *input)
+ {
+-	struct cyttsp4_mt_data *md = input_get_drvdata(input);
+-	mutex_lock(&md->report_lock);
+-	if (!md->is_suspended)
++	struct cyttsp4 *cd = input_get_drvdata(input);
++	mutex_lock(&cd->report_lock);
++	if (!cd->is_suspended)
+ 		pm_runtime_put(input->dev.parent);
+-	mutex_unlock(&md->report_lock);
++	mutex_unlock(&cd->report_lock);
+ }
+ 
+ 
+ static int cyttsp4_setup_input_device(struct cyttsp4 *cd)
+ {
+ 	struct device *dev = cd->dev;
+-	struct cyttsp4_mt_data *md = &cd->md;
+ 	int signal = CY_IGNORE_VALUE;
+ 	int max_x, max_y, max_p, min, max;
+ 	int max_x_tmp, max_y_tmp;
+@@ -1890,32 +1885,32 @@ static int cyttsp4_setup_input_device(struct cyttsp4 *cd)
+ 	int rc;
+ 
+ 	dev_vdbg(dev, "%s: Initialize event signals\n", __func__);
+-	__set_bit(EV_ABS, md->input->evbit);
+-	__set_bit(EV_REL, md->input->evbit);
+-	__set_bit(EV_KEY, md->input->evbit);
++	__set_bit(EV_ABS, cd->input->evbit);
++	__set_bit(EV_REL, cd->input->evbit);
++	__set_bit(EV_KEY, cd->input->evbit);
+ 
+-	max_x_tmp = md->si->si_ofs.max_x;
+-	max_y_tmp = md->si->si_ofs.max_y;
++	max_x_tmp = cd->si->si_ofs.max_x;
++	max_y_tmp = cd->si->si_ofs.max_y;
+ 
+ 	/* get maximum values from the sysinfo data */
+-	if (md->pdata->flags & CY_FLAG_FLIP) {
++	if (cd->pdata->flags & CY_FLAG_FLIP) {
+ 		max_x = max_y_tmp - 1;
+ 		max_y = max_x_tmp - 1;
+ 	} else {
+ 		max_x = max_x_tmp - 1;
+ 		max_y = max_y_tmp - 1;
+ 	}
+-	max_p = md->si->si_ofs.max_p;
++	max_p = cd->si->si_ofs.max_p;
+ 
+ 	/* set event signal capabilities */
+-	for (i = 0; i < (md->pdata->frmwrk->size / CY_NUM_ABS_SET); i++) {
+-		signal = md->pdata->frmwrk->abs
++	for (i = 0; i < (cd->pdata->frmwrk->size / CY_NUM_ABS_SET); i++) {
++		signal = cd->pdata->frmwrk->abs
+ 			[(i * CY_NUM_ABS_SET) + CY_SIGNAL_OST];
+ 		if (signal != CY_IGNORE_VALUE) {
+-			__set_bit(signal, md->input->absbit);
+-			min = md->pdata->frmwrk->abs
++			__set_bit(signal, cd->input->absbit);
++			min = cd->pdata->frmwrk->abs
+ 				[(i * CY_NUM_ABS_SET) + CY_MIN_OST];
+-			max = md->pdata->frmwrk->abs
++			max = cd->pdata->frmwrk->abs
+ 				[(i * CY_NUM_ABS_SET) + CY_MAX_OST];
+ 			if (i == CY_ABS_ID_OST) {
+ 				/* shift track ids down to start at 0 */
+@@ -1927,23 +1922,23 @@ static int cyttsp4_setup_input_device(struct cyttsp4 *cd)
+ 				max = max_y;
+ 			else if (i == CY_ABS_P_OST)
+ 				max = max_p;
+-			input_set_abs_params(md->input, signal, min, max,
+-				md->pdata->frmwrk->abs
++			input_set_abs_params(cd->input, signal, min, max,
++				cd->pdata->frmwrk->abs
+ 				[(i * CY_NUM_ABS_SET) + CY_FUZZ_OST],
+-				md->pdata->frmwrk->abs
++				cd->pdata->frmwrk->abs
+ 				[(i * CY_NUM_ABS_SET) + CY_FLAT_OST]);
+ 			dev_dbg(dev, "%s: register signal=%02X min=%d max=%d\n",
+ 				__func__, signal, min, max);
+ 			if ((i == CY_ABS_ID_OST) &&
+-				(md->si->si_ofs.tch_rec_size <
++				(cd->si->si_ofs.tch_rec_size <
+ 				CY_TMA4XX_TCH_REC_SIZE))
+ 				break;
+ 		}
+ 	}
+ 
+-	input_mt_init_slots(md->input, md->si->si_ofs.tch_abs[CY_TCH_T].max,
++	input_mt_init_slots(cd->input, cd->si->si_ofs.tch_abs[CY_TCH_T].max,
+ 			INPUT_MT_DIRECT);
+-	rc = input_register_device(md->input);
++	rc = input_register_device(cd->input);
+ 	if (rc < 0)
+ 		dev_err(dev, "%s: Error, failed register input device r=%d\n",
+ 			__func__, rc);
+@@ -1953,34 +1948,31 @@ static int cyttsp4_setup_input_device(struct cyttsp4 *cd)
+ static int cyttsp4_mt_probe(struct cyttsp4 *cd)
+ {
+ 	struct device *dev = cd->dev;
+-	struct cyttsp4_mt_data *md = &cd->md;
+-	struct cyttsp4_mt_platform_data *pdata = cd->pdata->mt_pdata;
+ 	int rc = 0;
+ 
+-	mutex_init(&md->report_lock);
+-	md->pdata = pdata;
++	mutex_init(&cd->report_lock);
+ 	/* Create the input device and register it. */
+ 	dev_vdbg(dev, "%s: Create the input device and register it\n",
+ 		__func__);
+-	md->input = input_allocate_device();
+-	if (md->input == NULL) {
++	cd->input = input_allocate_device();
++	if (cd->input == NULL) {
+ 		dev_err(dev, "%s: Error, failed to allocate input device\n",
+ 			__func__);
+ 		rc = -ENOSYS;
+ 		goto error_alloc_failed;
+ 	}
+ 
+-	md->input->name = pdata->inp_dev_name;
+-	scnprintf(md->phys, sizeof(md->phys)-1, "%s", dev_name(dev));
+-	md->input->phys = md->phys;
+-	md->input->id.bustype = cd->bus_ops->bustype;
+-	md->input->dev.parent = dev;
+-	md->input->open = cyttsp4_mt_open;
+-	md->input->close = cyttsp4_mt_close;
+-	input_set_drvdata(md->input, md);
++	cd->input->name = cd->pdata->inp_dev_name;
++	scnprintf(cd->phys, sizeof(cd->phys)-1, "%s", dev_name(dev));
++	cd->input->phys = cd->phys;
++	cd->input->id.bustype = cd->bus_ops->bustype;
++	cd->input->dev.parent = dev;
++	cd->input->open = cyttsp4_mt_open;
++	cd->input->close = cyttsp4_mt_close;
++	input_set_drvdata(cd->input, cd);
+ 
+ 	/* get sysinfo */
+-	md->si = &cd->sysinfo;
++	cd->si = &cd->sysinfo;
+ 
+ 	rc = cyttsp4_setup_input_device(cd);
+ 	if (rc)
+@@ -1989,7 +1981,7 @@ static int cyttsp4_mt_probe(struct cyttsp4 *cd)
+ 	return 0;
+ 
+ error_init_input:
+-	input_free_device(md->input);
++	input_free_device(cd->input);
+ error_alloc_failed:
+ 	dev_err(dev, "%s failed.\n", __func__);
+ 	return rc;
+@@ -2003,7 +1995,7 @@ struct cyttsp4 *cyttsp4_probe(const struct cyttsp4_bus_ops *ops,
+ 	unsigned long irq_flags;
+ 	int rc = 0;
+ 
+-	if (!pdata || !pdata->core_pdata || !pdata->mt_pdata) {
++	if (!pdata) {
+ 		dev_err(dev, "%s: Missing platform data\n", __func__);
+ 		rc = -ENODEV;
+ 		goto error_no_pdata;
+@@ -2026,7 +2018,6 @@ struct cyttsp4 *cyttsp4_probe(const struct cyttsp4_bus_ops *ops,
+ 	/* Initialize device info */
+ 	cd->dev = dev;
+ 	cd->pdata = pdata;
+-	cd->cpdata = pdata->core_pdata;
+ 	cd->bus_ops = ops;
+ 
+ 	/* Initialize mutexes and spinlocks */
+@@ -2041,7 +2032,7 @@ struct cyttsp4 *cyttsp4_probe(const struct cyttsp4_bus_ops *ops,
+ 	INIT_WORK(&cd->watchdog_work, cyttsp4_watchdog_work);
+ 
+ 	/* Initialize IRQ */
+-	cd->irq = gpio_to_irq(cd->cpdata->irq_gpio);
++	cd->irq = gpio_to_irq(cd->pdata->irq_gpio);
+ 	if (cd->irq < 0) {
+ 		rc = -EINVAL;
+ 		goto error_free_xfer;
+@@ -2050,9 +2041,9 @@ struct cyttsp4 *cyttsp4_probe(const struct cyttsp4_bus_ops *ops,
+ 	dev_set_drvdata(dev, cd);
+ 
+ 	/* Call platform init function */
+-	if (cd->cpdata->init) {
++	if (cd->pdata->init) {
+ 		dev_dbg(cd->dev, "%s: Init HW\n", __func__);
+-		rc = cd->cpdata->init(cd->cpdata, 1, cd->dev);
++		rc = cd->pdata->init(cd->pdata, 1, cd->dev);
+ 	} else {
+ 		dev_dbg(cd->dev, "%s: No HW INIT function\n", __func__);
+ 		rc = 0;
+@@ -2061,7 +2052,7 @@ struct cyttsp4 *cyttsp4_probe(const struct cyttsp4_bus_ops *ops,
+ 		dev_err(cd->dev, "%s: HW Init fail r=%d\n", __func__, rc);
+ 
+ 	dev_dbg(dev, "%s: initialize threaded irq=%d\n", __func__, cd->irq);
+-	if (cd->cpdata->level_irq_udelay > 0)
++	if (cd->pdata->level_irq_udelay > 0)
+ 		/* use level triggered interrupts */
+ 		irq_flags = IRQF_TRIGGER_LOW | IRQF_ONESHOT;
+ 	else
+@@ -2108,8 +2099,8 @@ struct cyttsp4 *cyttsp4_probe(const struct cyttsp4_bus_ops *ops,
+ 	cyttsp4_free_si_ptrs(cd);
+ 	free_irq(cd->irq, cd);
+ error_request_irq:
+-	if (cd->cpdata->init)
+-		cd->cpdata->init(cd->cpdata, 0, dev);
++	if (cd->pdata->init)
++		cd->pdata->init(cd->pdata, 0, dev);
+ error_free_xfer:
+ 	kfree(cd->xfer_buf);
+ error_free_cd:
+@@ -2121,17 +2112,17 @@ struct cyttsp4 *cyttsp4_probe(const struct cyttsp4_bus_ops *ops,
+ }
+ EXPORT_SYMBOL_GPL(cyttsp4_probe);
+ 
+-static void cyttsp4_mt_release(struct cyttsp4_mt_data *md)
++static void cyttsp4_mt_release(struct cyttsp4 *cd)
+ {
+-	input_unregister_device(md->input);
+-	input_set_drvdata(md->input, NULL);
++	input_unregister_device(cd->input);
++	input_set_drvdata(cd->input, NULL);
+ }
+ 
+ int cyttsp4_remove(struct cyttsp4 *cd)
+ {
+ 	struct device *dev = cd->dev;
+ 
+-	cyttsp4_mt_release(&cd->md);
++	cyttsp4_mt_release(cd);
+ 
+ 	/*
+ 	 * Suspend the device before freeing the startup_work and stopping
+@@ -2145,8 +2136,8 @@ int cyttsp4_remove(struct cyttsp4 *cd)
+ 	cyttsp4_stop_wd_timer(cd);
+ 
+ 	free_irq(cd->irq, cd);
+-	if (cd->cpdata->init)
+-		cd->cpdata->init(cd->cpdata, 0, dev);
++	if (cd->pdata->init)
++		cd->pdata->init(cd->pdata, 0, dev);
+ 	cyttsp4_free_si_ptrs(cd);
+ 	kfree(cd);
+ 	return 0;
+diff --git a/drivers/input/touchscreen/cyttsp4_core.h b/drivers/input/touchscreen/cyttsp4_core.h
+index 6262f6e45075..05fb30058d87 100644
+--- a/drivers/input/touchscreen/cyttsp4_core.h
++++ b/drivers/input/touchscreen/cyttsp4_core.h
+@@ -305,16 +305,6 @@ struct cyttsp4_sysinfo {
+ 	u8 *xy_data;			/* operational touch regs */
+ };
+ 
+-struct cyttsp4_mt_data {
+-	struct cyttsp4_mt_platform_data *pdata;
+-	struct cyttsp4_sysinfo *si;
+-	struct input_dev *input;
+-	struct mutex report_lock;
+-	bool is_suspended;
+-	char phys[NAME_MAX];
+-	int num_prv_tch;
+-};
+-
+ struct cyttsp4 {
+ 	struct device *dev;
+ 	struct mutex system_lock;
+@@ -333,9 +323,13 @@ struct cyttsp4 {
+ 	int exclusive_waits;
+ 	atomic_t ignore_irq;
+ 	bool invalid_touch_app;
+-	struct cyttsp4_mt_data md;
++	struct cyttsp4_sysinfo *si;
++	struct input_dev *input;
++	struct mutex report_lock;
++	bool is_suspended;
++	char phys[NAME_MAX];
++	int num_prv_tch;
+ 	struct cyttsp4_platform_data *pdata;
+-	struct cyttsp4_core_platform_data *cpdata;
+ 	const struct cyttsp4_bus_ops *bus_ops;
+ 	u8 *xfer_buf;
+ #ifdef VERBOSE_DEBUG
+diff --git a/include/linux/platform_data/cyttsp4.h b/include/linux/platform_data/cyttsp4.h
+index c54160c17b0b..1f945aa2466e 100644
+--- a/include/linux/platform_data/cyttsp4.h
++++ b/include/linux/platform_data/cyttsp4.h
+@@ -27,36 +27,30 @@ struct touch_framework {
+ 	uint8_t         enable_vkeys;
+ } __packed;
+ 
+-struct cyttsp4_mt_platform_data {
+-	struct touch_framework *frmwrk;
+-	unsigned short flags;
+-	char const *inp_dev_name;
+-};
+-
+ struct cyttsp4_virtual_key {
+ 	int code;
+ };
+ 
+-struct cyttsp4_core_platform_data {
++struct cyttsp4_platform_data {
++	char const *inp_dev_name;
++	unsigned short flags;
++
+ 	int irq_gpio;
+ 	int rst_gpio;
+ 	int level_irq_udelay;
+-	int (*xres)(struct cyttsp4_core_platform_data *pdata,
++	int (*xres)(struct cyttsp4_platform_data *pdata,
+ 		struct device *dev);
+-	int (*init)(struct cyttsp4_core_platform_data *pdata,
++	int (*init)(struct cyttsp4_platform_data *pdata,
+ 		int on, struct device *dev);
+-	int (*power)(struct cyttsp4_core_platform_data *pdata,
++	int (*power)(struct cyttsp4_platform_data *pdata,
+ 		int on, struct device *dev, atomic_t *ignore_irq);
+-	int (*irq_stat)(struct cyttsp4_core_platform_data *pdata,
++	int (*irq_stat)(struct cyttsp4_platform_data *pdata,
+ 		struct device *dev);
+ 
++	struct touch_framework *frmwrk;
++
+ 	int n_keys;
+ 	struct cyttsp4_virtual_key* keys;
+ };
+ 
+-struct cyttsp4_platform_data {
+-	struct cyttsp4_core_platform_data *core_pdata;
+-	struct cyttsp4_mt_platform_data *mt_pdata;
+-};
+-
+ #endif /* _CYTTSP4_H_ */
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/input-cyttsp4-Restart-on-wakeup-wakeup-by-I2C-read-doesn-t-work.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/input-cyttsp4-Restart-on-wakeup-wakeup-by-I2C-read-doesn-t-work.patch
new file mode 100644
index 000000000000..5c8550d3edbd
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/input-cyttsp4-Restart-on-wakeup-wakeup-by-I2C-read-doesn-t-work.patch
@@ -0,0 +1,125 @@
+From 722dc128c2cfef58b8ed8737f6c76224be25cd28 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 1 Oct 2019 02:21:43 +0200
+Subject: input: cyttsp4: Restart on wakeup (wakeup by I2C read doesn't work)
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/input/touchscreen/cyttsp4_core.c | 30 ++++++++++++++++--------
+ 1 file changed, 20 insertions(+), 10 deletions(-)
+
+diff --git a/drivers/input/touchscreen/cyttsp4_core.c b/drivers/input/touchscreen/cyttsp4_core.c
+index 58eb9586a46f..1ddb0b466a46 100644
+--- a/drivers/input/touchscreen/cyttsp4_core.c
++++ b/drivers/input/touchscreen/cyttsp4_core.c
+@@ -28,7 +28,7 @@
+ #define CY_CORE_SLEEP_REQUEST_EXCLUSIVE_TIMEOUT	5000
+ #define CY_CORE_MODE_CHANGE_TIMEOUT		1000
+ #define CY_CORE_RESET_AND_WAIT_TIMEOUT		500
+-#define CY_CORE_WAKEUP_TIMEOUT			50
++#define CY_CORE_WAKEUP_TIMEOUT			250
+ 
+ #define CY_CORE_STARTUP_RETRY_COUNT		3
+ 
+@@ -139,13 +139,11 @@ static int cyttsp4_hw_reset(struct cyttsp4 *cd)
+ 		return cyttsp4_hw_soft_reset(cd);
+ 
+ 	gpiod_set_value_cansleep(cd->reset_gpio, 1);
+-	msleep(20);
+-
+-	gpiod_set_value_cansleep(cd->reset_gpio, 0);
+ 	msleep(40);
+ 
+-	gpiod_set_value_cansleep(cd->reset_gpio, 1);
++	gpiod_set_value_cansleep(cd->reset_gpio, 0);
+ 	msleep(20);
++
+ 	return 0;
+ }
+ 
+@@ -1525,12 +1523,14 @@ static int cyttsp4_core_sleep_(struct cyttsp4 *cd)
+ 	}
+ 	dev_vdbg(cd->dev, "%s: write DEEP SLEEP succeeded\n", __func__);
+ 
++	/*
+ 	rc = cyttsp4_set_power(cd, 0);
+ 	if (rc < 0) {
+ 		dev_err(cd->dev, "%s: HW Power down fails r=%d\n",
+ 				__func__, rc);
+ 		goto error;
+ 	}
++          */
+ 
+ 	/* Give time to FW to sleep */
+ 	msleep(50);
+@@ -1748,6 +1748,7 @@ static int cyttsp4_core_wake_(struct cyttsp4 *cd)
+ 	u8 mode;
+ 	int t;
+ 
++#if 0
+ 	/* Already woken? */
+ 	mutex_lock(&cd->system_lock);
+ 	if (cd->sleep_state == SS_SLEEP_OFF) {
+@@ -1765,7 +1766,8 @@ static int cyttsp4_core_wake_(struct cyttsp4 *cd)
+ 				__func__, rc);
+ 
+ 		/* Initiate a read transaction to wake up */
+-		cyttsp4_adap_read(cd, CY_REG_BASE, sizeof(mode), &mode);
++		rc = cyttsp4_adap_read(cd, CY_REG_BASE, sizeof(mode), &mode);
++		dev_err(dev, "Waking up by read rc=%d\n", rc);
+ 	} else
+ 		dev_vdbg(cd->dev, "%s: HW power up succeeds\n",
+ 			__func__);
+@@ -1782,7 +1784,13 @@ static int cyttsp4_core_wake_(struct cyttsp4 *cd)
+ 		cyttsp4_queue_startup_(cd);
+ 		mutex_unlock(&cd->system_lock);
+ 	}
+-
++#else
++	mutex_lock(&cd->system_lock);
++	cd->int_status &= ~CY_INT_AWAKE;
++	/* Try starting up */
++	cyttsp4_queue_startup_(cd);
++	mutex_unlock(&cd->system_lock);
++#endif
+ 	mutex_lock(&cd->system_lock);
+ 	cd->sleep_state = SS_SLEEP_OFF;
+ 	mutex_unlock(&cd->system_lock);
+@@ -1992,6 +2000,7 @@ struct cyttsp4 *cyttsp4_probe(const struct cyttsp4_bus_ops *ops,
+ 		return ERR_PTR(-ENOMEM);
+ 	}
+ 
++	cd->irq = irq;
+ 	cd->signals = cyttsp4_default_signals;
+ 	cd->n_signals = ARRAY_SIZE(cyttsp4_default_signals);
+ 
+@@ -2005,7 +2014,8 @@ struct cyttsp4 *cyttsp4_probe(const struct cyttsp4_bus_ops *ops,
+ 	cd->vdd_supply = devm_regulator_get(dev, "vdd");
+ 	if (IS_ERR(cd->vdd_supply)) {
+ 		rc = PTR_ERR(cd->vdd_supply);
+-		dev_err(dev, "can't get vdd power (%d)\n", rc);
++		if (rc != -EPROBE_DEFER)
++			dev_err(dev, "can't get vdd power (%d)\n", rc);
+ 		return ERR_PTR(rc);
+ 	}
+ 
+@@ -2019,14 +2029,14 @@ struct cyttsp4 *cyttsp4_probe(const struct cyttsp4_bus_ops *ops,
+ 	if (IS_ERR(cd->reset_gpio)) {
+ 		rc = PTR_ERR(cd->reset_gpio);
+ 		dev_err(dev, "can't get reset gpio (%d)\n", rc);
+-		return ERR_PTR(rc);
++		goto error_disable_vdd;
+ 	}
+ 
+ 	cd->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
+ 	if (IS_ERR(cd->reset_gpio)) {
+ 		rc = PTR_ERR(cd->reset_gpio);
+ 		dev_err(dev, "can't get reset gpio (%d)\n", rc);
+-		return ERR_PTR(rc);
++		goto error_disable_vdd;
+ 	}
+ 
+ 	cd->xfer_buf = devm_kzalloc(dev, xfer_buf_size, GFP_KERNEL);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/input-cyttsp4-Use-i2c-spi-names-directly-in-the-driver.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/input-cyttsp4-Use-i2c-spi-names-directly-in-the-driver.patch
new file mode 100644
index 000000000000..b6f968ebb1aa
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/input-cyttsp4-Use-i2c-spi-names-directly-in-the-driver.patch
@@ -0,0 +1,64 @@
+From 08cc518ba716985004d51794be20d684e18bdd45 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Mon, 6 Mar 2023 01:17:09 +0100
+Subject: input: cyttsp4: Use i2c/spi names directly in the driver
+
+Platform data is going to be removed.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/input/touchscreen/cyttsp4_i2c.c | 4 ++--
+ drivers/input/touchscreen/cyttsp4_spi.c | 2 +-
+ include/linux/platform_data/cyttsp4.h   | 2 --
+ 3 files changed, 3 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/input/touchscreen/cyttsp4_i2c.c b/drivers/input/touchscreen/cyttsp4_i2c.c
+index da32c151def5..5b38a4f34209 100644
+--- a/drivers/input/touchscreen/cyttsp4_i2c.c
++++ b/drivers/input/touchscreen/cyttsp4_i2c.c
+@@ -50,14 +50,14 @@ static void cyttsp4_i2c_remove(struct i2c_client *client)
+ }
+ 
+ static const struct i2c_device_id cyttsp4_i2c_id[] = {
+-	{ CYTTSP4_I2C_NAME },
++	{ "cyttsp4_i2c_adapter" },
+ 	{ }
+ };
+ MODULE_DEVICE_TABLE(i2c, cyttsp4_i2c_id);
+ 
+ static struct i2c_driver cyttsp4_i2c_driver = {
+ 	.driver = {
+-		.name	= CYTTSP4_I2C_NAME,
++		.name	= "cyttsp4_i2c_adapter",
+ 		.pm	= pm_ptr(&cyttsp4_pm_ops),
+ 	},
+ 	.probe		= cyttsp4_i2c_probe,
+diff --git a/drivers/input/touchscreen/cyttsp4_spi.c b/drivers/input/touchscreen/cyttsp4_spi.c
+index 944fbbe9113e..f3cca8c9c119 100644
+--- a/drivers/input/touchscreen/cyttsp4_spi.c
++++ b/drivers/input/touchscreen/cyttsp4_spi.c
+@@ -172,7 +172,7 @@ static void cyttsp4_spi_remove(struct spi_device *spi)
+ 
+ static struct spi_driver cyttsp4_spi_driver = {
+ 	.driver = {
+-		.name	= CYTTSP4_SPI_NAME,
++		.name	= "cyttsp4_spi_adapter",
+ 		.pm	= pm_ptr(&cyttsp4_pm_ops),
+ 	},
+ 	.probe  = cyttsp4_spi_probe,
+diff --git a/include/linux/platform_data/cyttsp4.h b/include/linux/platform_data/cyttsp4.h
+index 1b5b30796e43..e718d2204ce7 100644
+--- a/include/linux/platform_data/cyttsp4.h
++++ b/include/linux/platform_data/cyttsp4.h
+@@ -16,8 +16,6 @@
+ #define _CYTTSP4_H_
+ 
+ #define CYTTSP4_MT_NAME "cyttsp4_mt"
+-#define CYTTSP4_I2C_NAME "cyttsp4_i2c_adapter"
+-#define CYTTSP4_SPI_NAME "cyttsp4_spi_adapter"
+ 
+ #define CY_TOUCH_SETTINGS_MAX 32
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/input-gpio-vibra-Allow-to-use-vcc-supply-alone-to-control-the-v.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/input-gpio-vibra-Allow-to-use-vcc-supply-alone-to-control-the-v.patch
new file mode 100644
index 000000000000..8abb01a6990e
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/input-gpio-vibra-Allow-to-use-vcc-supply-alone-to-control-the-v.patch
@@ -0,0 +1,76 @@
+From 2ff865418f446773e58aacf75a2af9a9327abedb Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Fri, 8 Sep 2023 01:07:30 +0200
+Subject: input: gpio-vibra: Allow to use vcc-supply alone to control the
+ vibrator
+
+Make enable-gpio optional to allow using this driver with boards that
+have vibrator connected to a power supply without intermediate gpio
+based enable circuitry.
+
+Also avoid a case where neither regulator nor enable gpio is specified,
+and bail out in probe in such a case.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/input/misc/gpio-vibra.c | 25 ++++++++++++++++++-------
+ 1 file changed, 18 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/input/misc/gpio-vibra.c b/drivers/input/misc/gpio-vibra.c
+index ad44b4d18a2a..de24e28458b0 100644
+--- a/drivers/input/misc/gpio-vibra.c
++++ b/drivers/input/misc/gpio-vibra.c
+@@ -39,7 +39,7 @@ static int gpio_vibrator_start(struct gpio_vibrator *vibrator)
+ 	struct device *pdev = vibrator->input->dev.parent;
+ 	int err;
+ 
+-	if (!vibrator->vcc_on) {
++	if (vibrator->vcc && !vibrator->vcc_on) {
+ 		err = regulator_enable(vibrator->vcc);
+ 		if (err) {
+ 			dev_err(pdev, "failed to enable regulator: %d\n", err);
+@@ -57,7 +57,7 @@ static void gpio_vibrator_stop(struct gpio_vibrator *vibrator)
+ {
+ 	gpiod_set_value_cansleep(vibrator->gpio, 0);
+ 
+-	if (vibrator->vcc_on) {
++	if (vibrator->vcc && vibrator->vcc_on) {
+ 		regulator_disable(vibrator->vcc);
+ 		vibrator->vcc_on = false;
+ 	}
+@@ -112,16 +112,27 @@ static int gpio_vibrator_probe(struct platform_device *pdev)
+ 	if (!vibrator->input)
+ 		return -ENOMEM;
+ 
+-	vibrator->vcc = devm_regulator_get(&pdev->dev, "vcc");
+-	if (IS_ERR(vibrator->vcc))
+-		return dev_err_probe(&pdev->dev, PTR_ERR(vibrator->vcc),
++	vibrator->vcc = devm_regulator_get_optional(&pdev->dev, "vcc");
++	err = PTR_ERR_OR_ZERO(vibrator->vcc);
++	if (err == -ENODEV) {
++		vibrator->vcc = NULL;
++	} else if (err) {
++		return dev_err_probe(&pdev->dev, err,
+ 				     "Failed to request regulator\n");
++	}
+ 
+-	vibrator->gpio = devm_gpiod_get(&pdev->dev, "enable", GPIOD_OUT_LOW);
+-	if (IS_ERR(vibrator->gpio))
++	vibrator->gpio = devm_gpiod_get_optional(&pdev->dev, "enable",
++						 GPIOD_OUT_LOW);
++	err = PTR_ERR_OR_ZERO(vibrator->gpio);
++	if (err)
+ 		return dev_err_probe(&pdev->dev, PTR_ERR(vibrator->gpio),
+ 				     "Failed to request main gpio\n");
+ 
++	if (!vibrator->vcc && !vibrator->gpio) {
++		dev_err(&pdev->dev, "Neither gpio nor regulator provided\n");
++		return -EINVAL;
++	}
++
+ 	INIT_WORK(&vibrator->play_work, gpio_vibrator_play_work);
+ 
+ 	vibrator->input->name = "gpio-vibrator";
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/leds-axp20x-Support-charger-LED-on-AXP20x-like-PMICs.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/leds-axp20x-Support-charger-LED-on-AXP20x-like-PMICs.patch
new file mode 100644
index 000000000000..0311559d59ac
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/leds-axp20x-Support-charger-LED-on-AXP20x-like-PMICs.patch
@@ -0,0 +1,345 @@
+From aa883f0bc0aa293a2e1dc1e1f1514a9f75aa2eb2 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Thu, 4 Feb 2021 00:55:20 +0100
+Subject: leds: axp20x: Support charger LED on AXP20x like PMICs
+
+There is single LED that can be turned on and off by the user, or set to
+be controlled by the charger in 2 different modes.
+
+The driver initializes the LED to be controlled by the charger, but
+allows to switch it to user control, and change the mode of charging
+indication via a sysfs.
+
+The driver was developed on AXP813, but should work on other PMICs like
+that without changes.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/leds/Kconfig       |  15 +++
+ drivers/leds/Makefile      |   1 +
+ drivers/leds/leds-axp20x.c | 253 +++++++++++++++++++++++++++++++++++++
+ drivers/mfd/axp20x.c       |   3 +
+ 4 files changed, 272 insertions(+)
+ create mode 100644 drivers/leds/leds-axp20x.c
+
+diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig
+index 2b27d043921c..6ee7b96aa3d2 100644
+--- a/drivers/leds/Kconfig
++++ b/drivers/leds/Kconfig
+@@ -996,6 +996,14 @@ config LEDS_IP30
+ 	  To compile this driver as a module, choose M here: the module
+ 	  will be called leds-ip30.
+ 
++config LEDS_SGM3140
++	tristate "LED support for the SGM3140"
++	depends on LEDS_CLASS_FLASH
++	depends on V4L2_FLASH_LED_CLASS || !V4L2_FLASH_LED_CLASS
++	help
++	  This option enables support for the SGM3140 500mA Buck/Boost Charge
++	  Pump LED Driver.
++
+ config LEDS_ACER_A500
+ 	tristate "Power button LED support for Acer Iconia Tab A500"
+ 	depends on LEDS_CLASS && MFD_ACER_A500_EC
+@@ -1003,6 +1011,13 @@ config LEDS_ACER_A500
+ 	  This option enables support for the Power Button LED of
+ 	  Acer Iconia Tab A500.
+ 
++config LEDS_AXP20X
++	tristate "Charger LED support for AXP20X-like PMICs (AXP813, ...)"
++	depends on LEDS_CLASS && MFD_AXP20X
++	help
++	  This option enables support for on-chip LED driver on
++	  AXP20X-like PMICs.
++
+ source "drivers/leds/blink/Kconfig"
+ 
+ comment "Flash and Torch LED drivers"
+diff --git a/drivers/leds/Makefile b/drivers/leds/Makefile
+index 6ad52e219ec6..b8626ca58a6f 100644
+--- a/drivers/leds/Makefile
++++ b/drivers/leds/Makefile
+@@ -96,6 +96,7 @@ obj-$(CONFIG_LEDS_UPBOARD)		+= leds-upboard.o
+ obj-$(CONFIG_LEDS_WM831X_STATUS)	+= leds-wm831x-status.o
+ obj-$(CONFIG_LEDS_WM8350)		+= leds-wm8350.o
+ obj-$(CONFIG_LEDS_WRAP)			+= leds-wrap.o
++obj-$(CONFIG_LEDS_AXP20X)		+= leds-axp20x.o
+ 
+ # Kinetic ExpressWire Protocol
+ obj-$(CONFIG_LEDS_EXPRESSWIRE)		+= leds-expresswire.o
+diff --git a/drivers/leds/leds-axp20x.c b/drivers/leds/leds-axp20x.c
+new file mode 100644
+index 000000000000..e2877af1032a
+--- /dev/null
++++ b/drivers/leds/leds-axp20x.c
+@@ -0,0 +1,253 @@
++// SPDX-License-Identifier: GPL-2.0-or-later
++/*
++ * LED Driver for X-Powers AXP813 PMIC and similar.
++ *
++ * Copyright(c) 2020 Ondrej Jirman <megi@xff.cz>
++ */
++
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/platform_device.h>
++#include <linux/leds.h>
++#include <linux/slab.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/mfd/axp20x.h>
++
++#define AXP20X_CHGLED_CTRL_MASK		BIT(3)
++#define AXP20X_CHGLED_CTRL_CHARGER	BIT(3)
++#define AXP20X_CHGLED_CTRL_USER		0
++
++#define AXP20X_CHRG_CTRL2_MODE		BIT(4)
++
++#define AXP20X_CHGLED_USER_STATE_MASK		GENMASK(5, 4)
++#define AXP20X_CHGLED_USER_STATE_OFF		(0 << 4)
++#define AXP20X_CHGLED_USER_STATE_BLINK_SLOW	(1 << 4)
++#define AXP20X_CHGLED_USER_STATE_BLINK_FAST	(2 << 4)
++#define AXP20X_CHGLED_USER_STATE_ON		(3 << 4)
++
++static struct led_hw_trigger_type axp20x_charger_led_trigger_type;
++
++struct axp20x_led {
++	struct led_classdev cdev;
++	struct regmap *regmap;
++};
++
++static int axp20x_led_set(struct led_classdev *led_cdev,
++			   enum led_brightness value)
++{
++	struct axp20x_led *led =
++			container_of(led_cdev, struct axp20x_led, cdev);
++	unsigned int val;
++
++	val = value == LED_OFF ? AXP20X_CHGLED_USER_STATE_OFF :
++		AXP20X_CHGLED_USER_STATE_ON;
++
++	return regmap_update_bits(led->regmap, AXP20X_OFF_CTRL,
++				  AXP20X_CHGLED_USER_STATE_MASK, val);
++
++}
++
++static int axp20x_set_charger_control(struct led_classdev *led_cdev, bool on)
++{
++	struct axp20x_led *led = container_of(led_cdev, struct axp20x_led, cdev);
++
++	return regmap_update_bits(led->regmap, AXP20X_OFF_CTRL,
++				  AXP20X_CHGLED_CTRL_MASK,
++				  on ? AXP20X_CHGLED_CTRL_CHARGER :
++				  AXP20X_CHGLED_CTRL_USER);
++}
++
++static int axp20x_trig_charger_activate(struct led_classdev *led_cdev)
++{
++	return axp20x_set_charger_control(led_cdev, true);
++}
++
++static void axp20x_trig_charger_deactivate(struct led_classdev *led_cdev)
++{
++	axp20x_set_charger_control(led_cdev, false);
++}
++
++static ssize_t charger_mode_show(struct device *dev,
++				 struct device_attribute *attr, char *buf)
++{
++	struct led_classdev *led_cdev = led_trigger_get_led(dev);
++	struct axp20x_led *led = container_of(led_cdev, struct axp20x_led, cdev);
++	unsigned int val;
++	int ret;
++
++	ret = regmap_read(led->regmap, AXP20X_CHRG_CTRL2, &val);
++	if (ret)
++		return ret;
++
++	return scnprintf(buf, PAGE_SIZE, "%u\n",
++			 val & AXP20X_CHRG_CTRL2_MODE ? 1 : 0);
++}
++
++static ssize_t charger_mode_store(struct device *dev,
++				  struct device_attribute *attr,
++				  const char *buf, size_t len)
++{
++	struct led_classdev *led_cdev = led_trigger_get_led(dev);
++	struct axp20x_led *led = container_of(led_cdev, struct axp20x_led, cdev);
++	unsigned int mode;
++	int ret;
++
++	ret = kstrtouint(buf, 0, &mode);
++	if (ret)
++		return ret;
++
++	if (mode > 1)
++		return -ERANGE;
++
++	ret = regmap_update_bits(led->regmap, AXP20X_CHRG_CTRL2,
++				 AXP20X_CHRG_CTRL2_MODE,
++				 mode ? AXP20X_CHRG_CTRL2_MODE : 0);
++	if (ret)
++		return ret;
++
++	return len;
++}
++static DEVICE_ATTR_RW(charger_mode);
++
++static struct attribute *axp20x_led_attrs[] = {
++	&dev_attr_charger_mode.attr,
++	NULL,
++};
++
++ATTRIBUTE_GROUPS(axp20x_led);
++
++static struct led_trigger axp20x_charger_led_trigger = {
++	.name		= "charger",
++	.trigger_type	= &axp20x_charger_led_trigger_type,
++	.activate	= axp20x_trig_charger_activate,
++	.deactivate	= axp20x_trig_charger_deactivate,
++	.groups		= axp20x_led_groups,
++};
++
++static int axp20x_led_probe(struct platform_device *pdev)
++{
++	struct axp20x_dev *axp20x;
++	struct axp20x_led *led;
++	unsigned int val;
++	int ret;
++
++	if (!of_device_is_available(pdev->dev.of_node))
++		return -ENODEV;
++
++	axp20x = dev_get_drvdata(pdev->dev.parent);
++	if (!axp20x)
++		return -EINVAL;
++
++	led = devm_kzalloc(&pdev->dev,
++			   sizeof(struct axp20x_led),
++			   GFP_KERNEL);
++	if (!led)
++		return -ENOMEM;
++
++	platform_set_drvdata(pdev, led);
++
++	led->regmap = axp20x->regmap;
++
++	led->cdev.name = "axp20x-chgarger-led";
++	led->cdev.brightness_set_blocking = axp20x_led_set;
++	led->cdev.brightness = LED_OFF;
++	led->cdev.max_brightness = 1;
++	led->cdev.trigger_type = &axp20x_charger_led_trigger_type;
++
++	ret = regmap_read(led->regmap, AXP20X_OFF_CTRL, &val);
++	if (ret) {
++		dev_err(&pdev->dev, "Failed to read charger control status\n");
++		return ret;
++	}
++
++	if ((val & AXP20X_CHGLED_CTRL_MASK) == AXP20X_CHGLED_CTRL_CHARGER)
++		led->cdev.default_trigger = axp20x_charger_led_trigger.name;
++
++	ret = devm_led_classdev_register(pdev->dev.parent, &led->cdev);
++	if (ret) {
++		dev_err(&pdev->dev, "Failed to register led %s\n",
++			led->cdev.name);
++		return ret;
++	}
++
++	ret = regmap_update_bits(led->regmap, AXP20X_OFF_CTRL,
++				 AXP20X_CHGLED_CTRL_MASK,
++				 AXP20X_CHGLED_CTRL_CHARGER);
++	if (ret) {
++		dev_err(&pdev->dev, "Failed to enable charger control\n");
++		return ret;
++	}
++
++	ret = axp20x_led_set(&led->cdev, led->cdev.brightness);
++	if (ret) {
++		dev_err(&pdev->dev, "Failed to init led brightness\n");
++		return ret;
++	}
++
++	return 0;
++}
++
++static void axp20x_led_shutdown(struct platform_device *pdev)
++{
++	struct axp20x_led *led = platform_get_drvdata(pdev);
++
++	/* On shutdown, we want to give LED control back to the PMIC,
++	 * so that it doesn't stay on, while the system is off.
++	 */
++
++	axp20x_led_set(&led->cdev, LED_OFF);
++	axp20x_set_charger_control(&led->cdev, true);
++}
++
++static void axp20x_led_remove(struct platform_device *pdev)
++{
++	axp20x_led_shutdown(pdev);
++}
++
++static const struct of_device_id axp20x_leds_of_match[] = {
++	{ .compatible = "x-powers,axp813-charger-led", },
++	{ },
++};
++MODULE_DEVICE_TABLE(of, axp20x_leds_of_match);
++
++static struct platform_driver axp20x_led_driver = {
++	.driver		= {
++		.name	= "leds-axp20x",
++		.of_match_table = axp20x_leds_of_match,
++	},
++	.probe		= axp20x_led_probe,
++	.remove		= axp20x_led_remove,
++	.shutdown	= axp20x_led_shutdown,
++};
++
++static int __init axp20x_led_driver_init(void)
++{
++	int ret;
++
++	ret = led_trigger_register(&axp20x_charger_led_trigger);
++	if (ret)
++		return ret;
++
++	ret = platform_driver_register(&axp20x_led_driver);
++	if (ret) {
++		led_trigger_unregister(&axp20x_charger_led_trigger);
++		return ret;
++	}
++
++	return 0;
++}
++
++static void __exit axp20x_led_driver_exit(void)
++{
++	platform_driver_unregister(&axp20x_led_driver);
++	led_trigger_unregister(&axp20x_charger_led_trigger);
++}
++
++module_init(axp20x_led_driver_init);
++module_exit(axp20x_led_driver_exit);
++
++MODULE_AUTHOR("Ondrej Jirman <megi@xff.cz>");
++MODULE_DESCRIPTION("LED driver for AXP813 PMIC");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:leds-axp20x");
+diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
+index cff56deba24f..4e52c79f8f50 100644
+--- a/drivers/mfd/axp20x.c
++++ b/drivers/mfd/axp20x.c
+@@ -1214,6 +1214,9 @@ static const struct mfd_cell axp813_cells[] = {
+ 		.num_resources	= ARRAY_SIZE(axp803_usb_power_supply_resources),
+ 		.resources	= axp803_usb_power_supply_resources,
+ 		.of_compatible	= "x-powers,axp813-usb-power-supply",
++	}, {
++		.name		= "axp20x-charger-led",
++		.of_compatible	= "x-powers,axp813-charger-led",
+ 	},
+ };
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/mailbox-Allow-to-run-mailbox-while-timekeeping-is-suspended.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/mailbox-Allow-to-run-mailbox-while-timekeeping-is-suspended.patch
new file mode 100644
index 000000000000..7aab58a648b1
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/mailbox-Allow-to-run-mailbox-while-timekeeping-is-suspended.patch
@@ -0,0 +1,64 @@
+From 18fbe636256b55efe55c17b1a9d039ee1fc8c538 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 2 Nov 2019 15:09:01 +0100
+Subject: mailbox: Allow to run mailbox while timekeeping is suspended
+
+This makes it possible to send messages from CPU suspend finisher.
+
+We simply implement cl->tx_block using a busywait loop when
+timekeeping is suspended, instead of using hrtimer.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/mailbox/mailbox.c | 28 ++++++++++++++++++++++++----
+ 1 file changed, 24 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/mailbox/mailbox.c b/drivers/mailbox/mailbox.c
+index d3d26a2c9895..01f918ae71b6 100644
+--- a/drivers/mailbox/mailbox.c
++++ b/drivers/mailbox/mailbox.c
+@@ -84,10 +84,12 @@ static void msg_submit(struct mbox_chan *chan)
+ 	spin_unlock_irqrestore(&chan->lock, flags);
+ 
+ 	if (!err && (chan->txdone_method & TXDONE_BY_POLL)) {
+-		/* kick start the timer immediately to avoid delays */
+-		spin_lock_irqsave(&chan->mbox->poll_hrt_lock, flags);
+-		hrtimer_start(&chan->mbox->poll_hrt, 0, HRTIMER_MODE_REL);
+-		spin_unlock_irqrestore(&chan->mbox->poll_hrt_lock, flags);
++		if (!timekeeping_suspended) {
++			/* kick start the timer immediately to avoid delays */
++			spin_lock_irqsave(&chan->mbox->poll_hrt_lock, flags);
++			hrtimer_start(&chan->mbox->poll_hrt, 0, HRTIMER_MODE_REL);
++			spin_unlock_irqrestore(&chan->mbox->poll_hrt_lock, flags);
++		}
+ 	}
+ }
+ 
+@@ -269,6 +271,24 @@ int mbox_send_message(struct mbox_chan *chan, void *mssg)
+ 
+ 	msg_submit(chan);
+ 
++	if (chan->cl->tx_block && timekeeping_suspended) {
++		int i = chan->cl->tx_tout * 10;
++		bool txdone;
++
++		while (i--) {
++			txdone = chan->mbox->ops->last_tx_done(chan);
++			if (txdone) {
++				tx_tick(chan, 0);
++				return 0;
++			}
++
++			udelay(100);
++		}
++
++		tx_tick(chan, -ETIME);
++		return -ETIME;
++	}
++
+ 	if (chan->cl->tx_block) {
+ 		unsigned long wait;
+ 		int ret;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/media-cedrus-Fix-failure-to-clean-up-hardware-on-probe-failure.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/media-cedrus-Fix-failure-to-clean-up-hardware-on-probe-failure.patch
new file mode 100644
index 000000000000..039bb686cff0
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/media-cedrus-Fix-failure-to-clean-up-hardware-on-probe-failure.patch
@@ -0,0 +1,35 @@
+From d7e104605f90e71fd43fa8a8579b6082c6ffdd76 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sun, 26 Apr 2020 14:38:15 -0500
+Subject: media: cedrus: Fix failure to clean up hardware on probe failure
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/staging/media/sunxi/cedrus/cedrus.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.c b/drivers/staging/media/sunxi/cedrus/cedrus.c
+index 52a9588462ce..b91174246e58 100644
+--- a/drivers/staging/media/sunxi/cedrus/cedrus.c
++++ b/drivers/staging/media/sunxi/cedrus/cedrus.c
+@@ -478,7 +478,7 @@ static int cedrus_probe(struct platform_device *pdev)
+ 	ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
+ 	if (ret) {
+ 		dev_err(&pdev->dev, "Failed to register V4L2 device\n");
+-		return ret;
++		goto err_hw;
+ 	}
+ 
+ 	vfd = &dev->vfd;
+@@ -539,6 +539,8 @@ static int cedrus_probe(struct platform_device *pdev)
+ 	v4l2_m2m_release(dev->m2m_dev);
+ err_v4l2:
+ 	v4l2_device_unregister(&dev->v4l2_dev);
++err_hw:
++	cedrus_hw_remove(dev);
+ 
+ 	return ret;
+ }
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/media-gc2145-Add-PIXEL_RATE-HBLANK-and-VBLANK-controls.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/media-gc2145-Add-PIXEL_RATE-HBLANK-and-VBLANK-controls.patch
new file mode 100644
index 000000000000..d91063a29788
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/media-gc2145-Add-PIXEL_RATE-HBLANK-and-VBLANK-controls.patch
@@ -0,0 +1,549 @@
+From b909ea0af9550a47ce455f0bac451bf8ed37e916 Mon Sep 17 00:00:00 2001
+From: Benjamin Schaaf <ben.schaaf@gmail.com>
+Date: Mon, 22 Nov 2021 23:38:26 +1100
+Subject: media: gc2145: Add PIXEL_RATE, HBLANK and VBLANK controls
+
+---
+ drivers/media/i2c/gc2145.c | 469 ++++++++++++++++++++-----------------
+ 1 file changed, 258 insertions(+), 211 deletions(-)
+
+diff --git a/drivers/media/i2c/gc2145.c b/drivers/media/i2c/gc2145.c
+index df15b72651e2..749dce832aa0 100644
+--- a/drivers/media/i2c/gc2145.c
++++ b/drivers/media/i2c/gc2145.c
+@@ -216,6 +216,9 @@ static const char * const gc2145_supply_name[] = {
+ 
+ struct gc2145_ctrls {
+ 	struct v4l2_ctrl_handler handler;
++	struct v4l2_ctrl *pixel_rate;
++	struct v4l2_ctrl *hblank;
++	struct v4l2_ctrl *vblank;
+ 	struct {
+ 		struct v4l2_ctrl *auto_exposure;
+ 		struct v4l2_ctrl *exposure;
+@@ -866,6 +869,224 @@ static int gc2145_set_exposure(struct gc2145_dev *sensor)
+ 	return gc2145_tx_commit(sensor);;
+ }
+ 
++struct gc2145_sensor_params {
++	unsigned int enable_scaler;
++	unsigned int col_scaler_only;
++	unsigned int row_skip;
++	unsigned int col_skip;
++	unsigned long sh_delay;
++	unsigned long hb;
++	unsigned long vb;
++	unsigned long st;
++	unsigned long et;
++	unsigned long win_width;
++	unsigned long win_height;
++	unsigned long width;
++	unsigned long height;
++};
++
++static void gc2145_sensor_params_init(struct gc2145_sensor_params* p, int width, int height)
++{
++	p->win_height = height + 32;
++	p->win_width = (width + 16);
++	p->width = width;
++	p->height = height;
++	p->st = 2;
++	p->et = 2;
++	p->vb = 8;
++	p->hb = 0x1f0;
++	p->sh_delay = 30;
++}
++
++// unit is PCLK periods
++static unsigned long
++gc2145_sensor_params_get_row_period(struct gc2145_sensor_params* p)
++{
++	return 2 * (p->win_width / 2 / (p->col_skip + 1) + p->sh_delay + p->hb + 4);
++}
++
++static unsigned long
++gc2145_sensor_params_get_frame_period(struct gc2145_sensor_params* p)
++{
++	unsigned long rt = gc2145_sensor_params_get_row_period(p);
++
++	return rt * (p->vb + p->win_height) / (p->row_skip + 1);
++}
++
++static void
++gc2145_sensor_params_fit_hb_to_power_line_period(struct gc2145_sensor_params* p,
++					  unsigned long power_line_freq,
++					  unsigned long pclk)
++{
++	unsigned long rt, power_line_ratio;
++
++        for (p->hb = 0x1f0; p->hb < 2047; p->hb++) {
++		rt = gc2145_sensor_params_get_row_period(p);
++
++		// power_line_ratio is row_freq / power_line_freq * 1000
++                power_line_ratio = pclk / power_line_freq * 1000 / rt;
++
++		// if we're close enough, stop the search
++                if (power_line_ratio % 1000 < 50)
++                        break;
++        }
++
++	// finding the optimal Hb is not critical
++	if (p->hb == 2047)
++		p->hb = 0x1f0;
++}
++
++static void
++gc2145_sensor_params_fit_vb_to_frame_period(struct gc2145_sensor_params* p,
++				     unsigned long frame_period)
++{
++	unsigned long rt, fp;
++
++	p->vb = 8;
++	rt = gc2145_sensor_params_get_row_period(p);
++	fp = gc2145_sensor_params_get_frame_period(p);
++
++	if (frame_period > fp)
++		p->vb = frame_period * (p->row_skip + 1) / rt - p->win_height;
++
++	if (p->vb > 4095)
++		p->vb = 4095;
++}
++
++static struct gc2145_sensor_params gc2145_get_sensor_params(
++	unsigned long framerate,
++	unsigned long width,
++	unsigned long height,
++	unsigned long *pclk2)
++{
++	struct gc2145_sensor_params params = {0};
++	bool scaling_desired;
++	unsigned long frame_period;
++	unsigned long power_line_freq = 50;
++
++	/*
++	 * Equations for calculating framerate are:
++	 *
++	 *    ww = width + 16
++	 *    wh = height + 32
++	 *    Rt = (ww / 2 / (col_skip + 1) + sh_delay + Hb + 4)
++	 *    Ft = Rt * (Vb + wh) / (row_skip + 1)
++	 *    framerate = 2pclk / 4 / Ft
++	 *
++	 * Based on these equations:
++	 *
++	 * 1) First we need to determine what 2PCLK frequency to use. The 2PCLK
++	 *    frequency is not arbitrarily precise, so we need to calculate the
++	 *    actual frequency used, after setting our target frequency.
++	 *
++	 *    We use a simple heuristic:
++	 *
++	 *      If pixel_count * 2 * framerate * 1.15 is > 40MHz, we use 60MHz,
++	 *      otherwise we use 40MHz.
++	 *
++	 * 2) We want to determine lowest Hb that we can use to extend row
++	 *    period so that row time takes an integer fraction of the power
++	 *    line frequency period. Minimum Hb is 0x1f0.
++	 *
++	 * 3) If the requested resolution is less than half the sensor's size,
++	 *    we'll use scaling, or row skipping + column scaling, or row and
++	 *    column skiping, depending on what allows us to achieve the
++	 *    requested framerate.
++	 *
++	 * 4) We use the selected Hb to calculate Vb value that will give
++	 *    us the desired framerate, given the scaling/skipping option
++	 *    selected in 3).
++	 */
++
++	scaling_desired = width <= GC2145_SENSOR_WIDTH_MAX / 2
++			&& height <= GC2145_SENSOR_HEIGHT_MAX / 2;
++
++	*pclk2 = 60000000;
++
++	gc2145_sensor_params_init(&params, width, height);
++
++	// if the resolution is < half the sensor size, enable the scaler
++	// to cover more area of the chip
++	if (scaling_desired) {
++		params.enable_scaler = 1;
++		*pclk2 *= 2;
++		gc2145_sensor_params_init(&params, width * 2, height * 2);
++	}
++
++	// we need to call this each time pclk or power_line_freq is changed
++	gc2145_sensor_params_fit_hb_to_power_line_period(&params,
++							 power_line_freq,
++							 *pclk2 / 2);
++
++	frame_period = gc2145_sensor_params_get_frame_period(&params);
++	if (framerate <= *pclk2 / 2 / frame_period)
++		goto apply;
++
++	if (scaling_desired) {
++		// try using just the column scaler + row skip
++		params.col_scaler_only = 1;
++		params.row_skip = 1;
++		gc2145_sensor_params_fit_hb_to_power_line_period(&params,
++								 power_line_freq,
++								 *pclk2 / 2);
++
++		frame_period = gc2145_sensor_params_get_frame_period(&params);
++		if (framerate <= *pclk2 / 2 / frame_period)
++			goto apply;
++
++
++		/*
++		// try disabling the scaler and just use skipping
++		params.enable_scaler = 0;
++		*pclk2 /= 2;
++		params.col_scaler_only = 0;
++		params.col_skip = 1;
++		gc2145_sensor_params_fit_hb_to_power_line_period(&params, power_line_freq, *pclk2 / 2);
++
++		frame_period = gc2145_sensor_params_get_frame_period(&params);
++
++		if (framerate <= *pclk2 / 2 / frame_period)
++			goto apply;
++		*/
++	}
++
++apply:
++	// adjust vb to fit the target framerate
++	gc2145_sensor_params_fit_vb_to_frame_period(&params,
++						    *pclk2 / 2 / framerate);
++
++	return params;
++}
++
++static int gc2145_sensor_params_apply(struct gc2145_dev *sensor,
++				      struct gc2145_sensor_params* p)
++{
++	u32 off_x = (GC2145_SENSOR_WIDTH_MAX - p->width) / 2;
++	u32 off_y = (GC2145_SENSOR_HEIGHT_MAX - p->height) / 2;
++
++	gc2145_tx_start(sensor);
++
++	gc2145_tx_write8(sensor, 0xfd, (p->enable_scaler ? BIT(0) : 0)
++			| (p->col_scaler_only ? BIT(1) : 0));
++
++	gc2145_tx_write8(sensor, 0x18, 0x0a
++		       | (p->col_skip ? BIT(7) : 0)
++		       | (p->row_skip ? BIT(6) : 0));
++
++	gc2145_tx_write16(sensor, 0x09, off_y);
++	gc2145_tx_write16(sensor, 0x0b, off_x);
++	gc2145_tx_write16(sensor, 0x0d, p->win_height);
++	gc2145_tx_write16(sensor, 0x0f, p->win_width);
++	gc2145_tx_write16(sensor, 0x05, p->hb);
++	gc2145_tx_write16(sensor, 0x07, p->vb);
++	gc2145_tx_write16(sensor, 0x11, p->sh_delay);
++
++	gc2145_tx_write8(sensor, 0x13, p->st);
++	gc2145_tx_write8(sensor, 0x14, p->et);
++
++	return gc2145_tx_commit(sensor);
++}
++
+ /* Test patterns */
+ 
+ enum {
+@@ -1054,12 +1275,31 @@ static int gc2145_init_controls(struct gc2145_dev *sensor)
+ 	//u64 wb_mask = 0;
+ 	//unsigned int i;
+ 	int ret;
++	struct gc2145_sensor_params params;
++	unsigned long pixel_rate;
+ 
+ 	v4l2_ctrl_handler_init(hdl, 32);
+ 
+ 	/* we can use our own mutex for the ctrl lock */
+ 	hdl->lock = &sensor->lock;
+ 
++	/* Clock related controls */
++	params = gc2145_get_sensor_params(sensor->frame_interval.denominator,
++					  sensor->fmt.width,
++					  sensor->fmt.height,
++					  &pixel_rate);
++	ctrls->pixel_rate = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_PIXEL_RATE,
++					      0, INT_MAX, 1,
++					      pixel_rate);
++
++	ctrls->hblank = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_HBLANK,
++					  0, INT_MAX, 1,
++					  params.win_height);
++
++	ctrls->vblank = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_VBLANK,
++					  0, INT_MAX, 1,
++					  params.win_width);
++
+ 	/* Exposure controls */
+ 	ctrls->auto_exposure = v4l2_ctrl_new_std_menu(hdl, ops,
+ 						      V4L2_CID_EXPOSURE_AUTO,
+@@ -1153,6 +1393,10 @@ static int gc2145_init_controls(struct gc2145_dev *sensor)
+ 	v4l2_ctrl_auto_cluster(3, &ctrls->wb, V4L2_WHITE_BALANCE_MANUAL, false);
+ #endif
+ 
++	ctrls->pixel_rate->flags |= V4L2_CTRL_FLAG_READ_ONLY;
++	ctrls->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
++	ctrls->vblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
++
+ 	v4l2_ctrl_auto_cluster(4, &ctrls->auto_exposure, V4L2_EXPOSURE_MANUAL,
+ 			       true);
+ 
+@@ -1386,125 +1630,11 @@ static int gc2145_setup_aec(struct gc2145_dev *sensor,
+ 	return gc2145_tx_commit(sensor);
+ }
+ 
+-struct gc2145_sensor_params {
+-	unsigned int enable_scaler;
+-	unsigned int col_scaler_only;
+-	unsigned int row_skip;
+-	unsigned int col_skip;
+-	unsigned long sh_delay;
+-	unsigned long hb;
+-	unsigned long vb;
+-	unsigned long st;
+-	unsigned long et;
+-	unsigned long win_width;
+-	unsigned long win_height;
+-	unsigned long width;
+-	unsigned long height;
+-};
+-
+-static void gc2145_sensor_params_init(struct gc2145_sensor_params* p, int width, int height)
+-{
+-	p->win_height = height + 32;
+-	p->win_width = (width + 16);
+-	p->width = width;
+-	p->height = height;
+-	p->st = 2;
+-	p->et = 2;
+-	p->vb = 8;
+-	p->hb = 0x1f0;
+-	p->sh_delay = 30;
+-}
+-
+-// unit is PCLK periods
+-static unsigned long
+-gc2145_sensor_params_get_row_period(struct gc2145_sensor_params* p)
+-{
+-	return 2 * (p->win_width / 2 / (p->col_skip + 1) + p->sh_delay + p->hb + 4);
+-}
+-
+-static unsigned long
+-gc2145_sensor_params_get_frame_period(struct gc2145_sensor_params* p)
+-{
+-	unsigned long rt = gc2145_sensor_params_get_row_period(p);
+-
+-	return rt * (p->vb + p->win_height) / (p->row_skip + 1);
+-}
+-
+-static void
+-gc2145_sensor_params_fit_hb_to_power_line_period(struct gc2145_sensor_params* p,
+-					  unsigned long power_line_freq,
+-					  unsigned long pclk)
+-{
+-	unsigned long rt, power_line_ratio;
+-
+-        for (p->hb = 0x1f0; p->hb < 2047; p->hb++) {
+-		rt = gc2145_sensor_params_get_row_period(p);
+-
+-		// power_line_ratio is row_freq / power_line_freq * 1000
+-                power_line_ratio = pclk / power_line_freq * 1000 / rt;
+-
+-		// if we're close enough, stop the search
+-                if (power_line_ratio % 1000 < 50)
+-                        break;
+-        }
+-
+-	// finding the optimal Hb is not critical
+-	if (p->hb == 2047)
+-		p->hb = 0x1f0;
+-}
+-
+-static void
+-gc2145_sensor_params_fit_vb_to_frame_period(struct gc2145_sensor_params* p,
+-				     unsigned long frame_period)
+-{
+-	unsigned long rt, fp;
+-
+-	p->vb = 8;
+-	rt = gc2145_sensor_params_get_row_period(p);
+-	fp = gc2145_sensor_params_get_frame_period(p);
+-
+-	if (frame_period > fp)
+-		p->vb = frame_period * (p->row_skip + 1) / rt - p->win_height;
+-
+-	if (p->vb > 4095)
+-		p->vb = 4095;
+-}
+-
+-static int gc2145_sensor_params_apply(struct gc2145_dev *sensor,
+-				      struct gc2145_sensor_params* p)
+-{
+-	u32 off_x = (GC2145_SENSOR_WIDTH_MAX - p->width) / 2;
+-	u32 off_y = (GC2145_SENSOR_HEIGHT_MAX - p->height) / 2;
+-
+-	gc2145_tx_start(sensor);
+-
+-	gc2145_tx_write8(sensor, 0xfd, (p->enable_scaler ? BIT(0) : 0)
+-			| (p->col_scaler_only ? BIT(1) : 0));
+-
+-	gc2145_tx_write8(sensor, 0x18, 0x0a
+-		       | (p->col_skip ? BIT(7) : 0)
+-		       | (p->row_skip ? BIT(6) : 0));
+-
+-	gc2145_tx_write16(sensor, 0x09, off_y);
+-	gc2145_tx_write16(sensor, 0x0b, off_x);
+-	gc2145_tx_write16(sensor, 0x0d, p->win_height);
+-	gc2145_tx_write16(sensor, 0x0f, p->win_width);
+-	gc2145_tx_write16(sensor, 0x05, p->hb);
+-	gc2145_tx_write16(sensor, 0x07, p->vb);
+-	gc2145_tx_write16(sensor, 0x11, p->sh_delay);
+-
+-	gc2145_tx_write8(sensor, 0x13, p->st);
+-	gc2145_tx_write8(sensor, 0x14, p->et);
+-
+-	return gc2145_tx_commit(sensor);
+-}
+-
+ static int gc2145_setup_mode(struct gc2145_dev *sensor)
+ {
+-	int scaling_desired, ret, pad, i;
+-	struct gc2145_sensor_params params = {0};
+-	unsigned long pclk2, frame_period;
+-	unsigned long power_line_freq = 50;
++	int ret, pad, i;
++	struct gc2145_sensor_params params;
++	unsigned long pclk2;
+ 	unsigned long width = sensor->fmt.width;
+ 	unsigned long height = sensor->fmt.height;
+ 	unsigned long framerate = sensor->frame_interval.denominator;
+@@ -1518,100 +1648,7 @@ static int gc2145_setup_mode(struct gc2145_dev *sensor)
+ 		return -EINVAL;
+ 	}
+ 
+-        /*
+-	 * Equations for calculating framerate are:
+-	 *
+-	 *    ww = width + 16
+-	 *    wh = height + 32
+-	 *    Rt = (ww / 2 / (col_skip + 1) + sh_delay + Hb + 4)
+-	 *    Ft = Rt * (Vb + wh) / (row_skip + 1)
+-	 *    framerate = 2pclk / 4 / Ft
+-	 *
+-	 * Based on these equations:
+-	 *
+-	 * 1) First we need to determine what 2PCLK frequency to use. The 2PCLK
+-	 *    frequency is not arbitrarily precise, so we need to calculate the
+-	 *    actual frequency used, after setting our target frequency.
+-	 *
+-	 *    We use a simple heuristic:
+-	 *
+-	 *      If pixel_count * 2 * framerate * 1.15 is > 40MHz, we use 60MHz,
+-	 *      otherwise we use 40MHz.
+-	 *
+-	 * 2) We want to determine lowest Hb that we can use to extend row
+-	 *    period so that row time takes an integer fraction of the power
+-	 *    line frequency period. Minimum Hb is 0x1f0.
+-	 *
+-	 * 3) If the requested resolution is less than half the sensor's size,
+-	 *    we'll use scaling, or row skipping + column scaling, or row and
+-	 *    column skiping, depending on what allows us to achieve the
+-	 *    requested framerate.
+-         *
+-	 * 4) We use the selected Hb to calculate Vb value that will give
+-	 *    us the desired framerate, given the scaling/skipping option
+-	 *    selected in 3).
+-	 */
+-
+-	scaling_desired = width <= GC2145_SENSOR_WIDTH_MAX / 2
+-			&& height <= GC2145_SENSOR_HEIGHT_MAX / 2;
+-
+-	pclk2 = 60000000;
+-
+-	ret = gc2145_set_2pclk(sensor, &pclk2, false);
+-	if (ret < 0)
+-		return ret;
+-
+-	gc2145_sensor_params_init(&params, width, height);
+-
+-	// if the resolution is < half the sensor size, enable the scaler
+-	// to cover more area of the chip
+-	if (scaling_desired) {
+-		params.enable_scaler = 1;
+-		pclk2 *= 2;
+-		gc2145_sensor_params_init(&params, width * 2, height * 2);
+-	}
+-
+-	// we need to call this each time pclk or power_line_freq is changed
+-	gc2145_sensor_params_fit_hb_to_power_line_period(&params,
+-							 power_line_freq,
+-							 pclk2 / 2);
+-
+-	frame_period = gc2145_sensor_params_get_frame_period(&params);
+-	if (framerate <= pclk2 / 2 / frame_period)
+-		goto apply;
+-
+-	if (scaling_desired) {
+-		// try using just the column scaler + row skip
+-		params.col_scaler_only = 1;
+-		params.row_skip = 1;
+-		gc2145_sensor_params_fit_hb_to_power_line_period(&params,
+-								 power_line_freq,
+-								 pclk2 / 2);
+-
+-		frame_period = gc2145_sensor_params_get_frame_period(&params);
+-		if (framerate <= pclk2 / 2 / frame_period)
+-			goto apply;
+-
+-
+-		/*
+-		// try disabling the scaler and just use skipping
+-		params.enable_scaler = 0;
+-		pclk2 /= 2;
+-		params.col_scaler_only = 0;
+-		params.col_skip = 1;
+-		gc2145_sensor_params_fit_hb_to_power_line_period(&params, power_line_freq, pclk2 / 2);
+-
+-		frame_period = gc2145_sensor_params_get_frame_period(&params);
+-
+-		if (framerate <= pclk2 / 2 / frame_period)
+-			goto apply;
+-                  */
+-	}
+-
+-apply:
+-        // adjust vb to fit the target framerate
+-	gc2145_sensor_params_fit_vb_to_frame_period(&params,
+-						    pclk2 / 2 / framerate);
++	params = gc2145_get_sensor_params(framerate, width, height, &pclk2);
+ 
+ 	gc2145_sensor_params_apply(sensor, &params);
+ 
+@@ -1845,6 +1882,8 @@ static int gc2145_set_fmt(struct v4l2_subdev *sd,
+ 	struct gc2145_dev *sensor = to_gc2145_dev(sd);
+ 	struct v4l2_mbus_framefmt *mf = &format->format;
+ 	const struct gc2145_pixfmt *pixfmt;
++	struct gc2145_sensor_params params;
++	unsigned long pixel_rate;
+ 	int ret = 0;
+ 
+ 	if (format->pad != 0)
+@@ -1884,6 +1923,14 @@ static int gc2145_set_fmt(struct v4l2_subdev *sd,
+ 
+ 	sensor->fmt = *mf;
+ 	sensor->pending_mode_change = true;
++
++	params = gc2145_get_sensor_params(sensor->frame_interval.denominator, mf->width, mf->height, &pixel_rate);
++	__v4l2_ctrl_s_ctrl_int64(sensor->ctrls.pixel_rate,
++				 pixel_rate);
++	__v4l2_ctrl_s_ctrl(sensor->ctrls.hblank,
++			   params.win_height);
++	__v4l2_ctrl_s_ctrl(sensor->ctrls.vblank,
++			   params.win_width);
+ out:
+ 	mutex_unlock(&sensor->lock);
+ 	return ret;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/media-gc2145-Added-BGGR-bayer-mode.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/media-gc2145-Added-BGGR-bayer-mode.patch
new file mode 100644
index 000000000000..54eb5e287c03
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/media-gc2145-Added-BGGR-bayer-mode.patch
@@ -0,0 +1,30 @@
+From c39a8e59c4abd741e172f47ec80b08ad12b85f39 Mon Sep 17 00:00:00 2001
+From: Martijn Braam <martijn@brixit.nl>
+Date: Fri, 4 Sep 2020 17:35:39 +0200
+Subject: media: gc2145: Added BGGR bayer mode
+
+Not all raw bayer modes from the sensor match up with the ones defined
+in v4l, mostly because they're mirrored.
+---
+ drivers/media/i2c/gc2145.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/media/i2c/gc2145.c b/drivers/media/i2c/gc2145.c
+index cc85ac772d5a..7539b122eeef 100644
+--- a/drivers/media/i2c/gc2145.c
++++ b/drivers/media/i2c/gc2145.c
+@@ -187,6 +187,11 @@ static const struct gc2145_pixfmt gc2145_formats[] = {
+ 		.colorspace        = V4L2_COLORSPACE_SRGB,
+ 		.fmt_setup         = 0x06,
+ 	},
++	{
++		.code              = MEDIA_BUS_FMT_SBGGR8_1X8,
++		.colorspace        = V4L2_COLORSPACE_RAW,
++		.fmt_setup         = 0x17,
++	},
+ };
+ 
+ static const struct gc2145_pixfmt *gc2145_find_format(u32 code)
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/media-gc2145-Disable-debug-output.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/media-gc2145-Disable-debug-output.patch
new file mode 100644
index 000000000000..18223184f5f3
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/media-gc2145-Disable-debug-output.patch
@@ -0,0 +1,37 @@
+From 420354a4c5c188185fcc37270e4c41bdbb608e60 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Wed, 27 Oct 2021 17:22:51 +0200
+Subject: media: gc2145: Disable debug output
+
+People don't like it. Hmm...
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/media/i2c/gc2145.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/media/i2c/gc2145.c b/drivers/media/i2c/gc2145.c
+index 7539b122eeef..df15b72651e2 100644
+--- a/drivers/media/i2c/gc2145.c
++++ b/drivers/media/i2c/gc2145.c
+@@ -8,7 +8,7 @@
+  * (at your option) any later version.
+  */
+ 
+-#define DEBUG
++//#define DEBUG
+ 
+ #include <asm/div64.h>
+ #include <linux/clk.h>
+@@ -374,7 +374,7 @@ static int gc2145_switch_bank(struct gc2145_dev *sensor, u16 reg)
+ 			return ret;
+ 
+ 		sensor->current_bank = bank;
+-		dev_info(&sensor->i2c_client->dev, "bank switch: 0x%02x\n",
++		dev_dbg(&sensor->i2c_client->dev, "bank switch: 0x%02x\n",
+ 				(unsigned int)sensor->current_bank);
+ 	}
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/media-gc2145-Galaxycore-camera-module-driver.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/media-gc2145-Galaxycore-camera-module-driver.patch
new file mode 100644
index 000000000000..8c14e25c5c13
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/media-gc2145-Galaxycore-camera-module-driver.patch
@@ -0,0 +1,2306 @@
+From 3226585412fac36bbcb0dc88f54020aeb25feadb Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 23 Jun 2020 19:51:18 +0200
+Subject: media: gc2145: Galaxycore camera module driver
+
+WIP!
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/media/i2c/Kconfig  |   10 +
+ drivers/media/i2c/Makefile |    1 +
+ drivers/media/i2c/gc2145.c | 2252 ++++++++++++++++++++++++++++++++++++
+ 3 files changed, 2263 insertions(+)
+ create mode 100644 drivers/media/i2c/gc2145.c
+
+diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig
+index 43be07cc5b37..2b3b4635c2f0 100644
+--- a/drivers/media/i2c/Kconfig
++++ b/drivers/media/i2c/Kconfig
+@@ -711,6 +711,16 @@ config VIDEO_HM5065
+ 	  This is a V4L2 sensor-level driver for Himax HM5065
+ 	  5 Mpixel camera.
+ 
++config VIDEO_GC2145
++	tristate "GalaxyCore GC2145 sensor support"
++	depends on I2C
++	select V4L2_FWNODE
++	select VIDEO_V4L2_SUBDEV_API
++	select MEDIA_CONTROLLER
++	help
++	  This is a V4L2 sensor-level driver for GalaxyCore GC2145
++	  2 Mpixel camera.
++
+ endif
+ 
+ menu "Camera ISPs"
+diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile
+index 08bd346db54e..8d79cbb0f29c 100644
+--- a/drivers/media/i2c/Makefile
++++ b/drivers/media/i2c/Makefile
+@@ -158,3 +158,4 @@ obj-$(CONFIG_VIDEO_VPX3220) += vpx3220.o
+ obj-$(CONFIG_VIDEO_WM8739) += wm8739.o
+ obj-$(CONFIG_VIDEO_WM8775) += wm8775.o
+ obj-$(CONFIG_VIDEO_HM5065)	+= hm5065.o
++obj-$(CONFIG_VIDEO_GC2145)	+= gc2145.o
+diff --git a/drivers/media/i2c/gc2145.c b/drivers/media/i2c/gc2145.c
+new file mode 100644
+index 000000000000..cc85ac772d5a
+--- /dev/null
++++ b/drivers/media/i2c/gc2145.c
+@@ -0,0 +1,2252 @@
++/*
++ * Galaxycore GC2145 driver.
++ * Copyright (C) 2018 Ondřej Jirman <megi@xff.cz>.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#define DEBUG
++
++#include <asm/div64.h>
++#include <linux/clk.h>
++#include <linux/clk-provider.h>
++#include <linux/clkdev.h>
++#include <linux/ctype.h>
++#include <linux/delay.h>
++#include <linux/device.h>
++#include <linux/firmware.h>
++#include <linux/i2c.h>
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/of_device.h>
++#include <linux/slab.h>
++#include <linux/types.h>
++#include <linux/gpio/consumer.h>
++#include <linux/regulator/consumer.h>
++#include <media/v4l2-async.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-fwnode.h>
++#include <media/v4l2-subdev.h>
++
++/*
++ * GC2145
++ * - 2M pixel
++ * - 1600 x 1200, max frame rate: 720P, 30fps@96MHz
++ * - Bayer RGB, RGB565, YCbCr 4:2:2
++ * - AE, AWB
++ * - PLL
++ * - AVDD 2.7-3V, DVDD 1.7-1.9V, IOVDD 1.7-3V
++ * - Power 180mW / 200uA standby
++ * - Interpolation, denoise, gamma, edge enhance
++ * I2C:
++ * - write reg8
++ * - read reg8
++ * - write reg8 multi
++ *
++ * Power on:
++ * MCLK on
++ * PWDN, RESET low
++ * IOVDD, AVDD, DVDD on in sequence
++ * RESET high
++ *
++ * Power off:
++ * PWDN, RESET low
++ * RESET high
++ * delay
++ * PWDN high
++ * RESET low
++ * IOVDD, AVDD, DVDD off
++ * PWDN low?
++ * MCLK off
++ *
++ * Init:
++ * - check chip id
++ * - setup pll
++ * - setup CSI interface / PAD drive strength
++ * - setup resolution/fps
++ * - enable postprocessing
++ *   (ISP related chapter)
++ *
++ * Stream on:
++ * - ???
++ */
++
++#define GC2145_FIRMWARE_PARAMETERS	"gc2145-init.bin"
++
++#define GC2145_SENSOR_WIDTH_MIN		88u
++#define GC2145_SENSOR_HEIGHT_MIN	72u
++
++//XXX: 1616x1232 8H/16V dummy pixels on each side
++#define GC2145_SENSOR_WIDTH_MAX		1600u
++#define GC2145_SENSOR_HEIGHT_MAX	1200u
++
++/* {{{ Register definitions */
++
++/* system registers */
++#define GC2145_REG_CHIP_ID			0xf0
++#define GC2145_REG_CHIP_ID_VALUE		0x2145
++
++#define GC2145_REG_PAD_IO		0xf2
++#define GC2145_REG_PLL_MODE1		0xf7
++#define GC2145_REG_PLL_MODE2		0xf8
++#define GC2145_REG_CM_MODE		0xf9
++#define GC2145_REG_CLK_DIV_MODE		0xfa
++#define GC2145_REG_ANALOG_PWC		0xfc
++#define GC2145_REG_SCALER_MODE		0xfd
++#define GC2145_REG_RESET		0xfe
++
++#define GC2145_P0_EXPOSURE_HI		0x03
++#define GC2145_P0_EXPOSURE_LO		0x04
++#define GC2145_P0_HBLANK_DELAY_HI	0x05
++#define GC2145_P0_HBLANK_DELAY_LO	0x06
++#define GC2145_P0_VBLANK_DELAY_HI	0x07
++#define GC2145_P0_VBLANK_DELAY_LO	0x08
++#define GC2145_P0_ROW_START_HI		0x09
++#define GC2145_P0_ROW_START_LO		0x0a
++#define GC2145_P0_COL_START_HI		0x0b
++#define GC2145_P0_COL_START_LO		0x0c
++#define GC2145_P0_WIN_HEIGHT_HI		0x0d
++#define GC2145_P0_WIN_HEIGHT_LO		0x0e
++#define GC2145_P0_WIN_WIDTH_HI		0x0f
++#define GC2145_P0_WIN_WIDTH_LO		0x10
++#define GC2145_P0_SH_DELAY_HI		0x11
++#define GC2145_P0_SH_DELAY_LO		0x12
++#define GC2145_P0_START_TIME		0x13
++#define GC2145_P0_END_TIME		0x14
++
++#define GC2145_P0_ISP_BLK_ENABLE1	0x80
++#define GC2145_P0_ISP_BLK_ENABLE2	0x81
++#define GC2145_P0_ISP_BLK_ENABLE3	0x82
++#define GC2145_P0_ISP_SPECIAL_EFFECT	0x83
++#define GC2145_P0_ISP_OUT_FORMAT	0x84
++#define GC2145_P0_FRAME_START		0x85
++#define GC2145_P0_SYNC_MODE		0x86
++#define GC2145_P0_ISP_BLK_ENABLE4	0x87
++#define GC2145_P0_ISP_MODULE_GATING	0x88
++#define GC2145_P0_ISP_BYPASS_MODE	0x89
++#define GC2145_P0_DEBUG_MODE2		0x8c
++#define GC2145_P0_DEBUG_MODE3		0x8d
++
++#define GC2145_P0_CROP_ENABLE		0x90
++#define GC2145_P0_CROP_Y1_HI		0x91
++#define GC2145_P0_CROP_Y1_LO		0x92
++#define GC2145_P0_CROP_X1_HI		0x93
++#define GC2145_P0_CROP_X1_LO		0x94
++#define GC2145_P0_CROP_WIN_HEIGHT_HI	0x95
++#define GC2145_P0_CROP_WIN_HEIGHT_LO	0x96
++#define GC2145_P0_CROP_WIN_WIDTH_HI	0x97
++#define GC2145_P0_CROP_WIN_WIDTH_LO	0x98
++
++#define GC2145_P0_SUBSAMPLE_RATIO	0x99
++#define GC2145_P0_SUBSAMPLE_MODE	0x9a
++#define GC2145_P0_SUB_ROW_N1		0x9b
++#define GC2145_P0_SUB_ROW_N2		0x9c
++#define GC2145_P0_SUB_ROW_N3		0x9d
++#define GC2145_P0_SUB_ROW_N4		0x9e
++#define GC2145_P0_SUB_COL_N1		0x9f
++#define GC2145_P0_SUB_COL_N2		0xa0
++#define GC2145_P0_SUB_COL_N3		0xa1
++#define GC2145_P0_SUB_COL_N4		0xa2
++#define GC2145_P0_OUT_BUF_ENABLE	0xc2
++
++/* }}} */
++
++struct gc2145_pixfmt {
++	u32 code;
++	u32 colorspace;
++	u8 fmt_setup;
++};
++
++static const struct gc2145_pixfmt gc2145_formats[] = {
++	{
++		.code              = MEDIA_BUS_FMT_UYVY8_2X8,
++		.colorspace        = V4L2_COLORSPACE_SRGB,
++		.fmt_setup         = 0x00,
++	},
++	{
++		.code              = MEDIA_BUS_FMT_VYUY8_2X8,
++		.colorspace        = V4L2_COLORSPACE_SRGB,
++		.fmt_setup         = 0x01,
++	},
++	{
++		.code              = MEDIA_BUS_FMT_YUYV8_2X8,
++		.colorspace        = V4L2_COLORSPACE_SRGB,
++		.fmt_setup         = 0x02,
++	},
++	{
++		.code              = MEDIA_BUS_FMT_YVYU8_2X8,
++		.colorspace        = V4L2_COLORSPACE_SRGB,
++		.fmt_setup         = 0x03,
++	},
++	{
++		.code              = MEDIA_BUS_FMT_RGB565_2X8_LE,
++		.colorspace        = V4L2_COLORSPACE_SRGB,
++		.fmt_setup         = 0x06,
++	},
++};
++
++static const struct gc2145_pixfmt *gc2145_find_format(u32 code)
++{
++	int i;
++
++	for (i = 0; i < ARRAY_SIZE(gc2145_formats); i++)
++		if (gc2145_formats[i].code == code)
++			return &gc2145_formats[i];
++
++	return NULL;
++}
++
++/* regulator supplies */
++static const char * const gc2145_supply_name[] = {
++	"IOVDD", /* Digital I/O (1.7-3V) suppply */
++	"AVDD",  /* Analog (2.7-3V) supply */
++	"DVDD",  /* Digital Core (1.7-1.9V) supply */
++};
++
++#define GC2145_NUM_SUPPLIES ARRAY_SIZE(gc2145_supply_name)
++
++struct gc2145_ctrls {
++	struct v4l2_ctrl_handler handler;
++	struct {
++		struct v4l2_ctrl *auto_exposure;
++		struct v4l2_ctrl *exposure;
++		struct v4l2_ctrl *d_gain;
++		struct v4l2_ctrl *a_gain;
++	};
++	struct v4l2_ctrl *metering;
++	struct v4l2_ctrl *exposure_bias;
++	struct {
++		struct v4l2_ctrl *wb;
++		struct v4l2_ctrl *blue_balance;
++		struct v4l2_ctrl *red_balance;
++	};
++	struct v4l2_ctrl *aaa_lock;
++	struct v4l2_ctrl *hflip;
++	struct v4l2_ctrl *vflip;
++	struct v4l2_ctrl *pl_freq;
++	struct v4l2_ctrl *colorfx;
++	struct v4l2_ctrl *brightness;
++	struct v4l2_ctrl *saturation;
++	struct v4l2_ctrl *contrast;
++	struct v4l2_ctrl *gamma;
++	struct v4l2_ctrl *test_pattern;
++	struct v4l2_ctrl *test_data[4];
++};
++
++enum {
++	TX_WRITE = 1,
++	TX_WRITE16,
++	TX_UPDATE_BITS,
++};
++
++#define GC2145_MAX_OPS 64
++
++struct gc2145_tx_op {
++	int op;
++	u16 reg;
++	u16 val;
++	u16 mask;
++};
++
++struct gc2145_dev {
++	struct i2c_client *i2c_client;
++	struct v4l2_subdev sd;
++	struct media_pad pad;
++	struct v4l2_fwnode_endpoint ep; /* the parsed DT endpoint info */
++	struct clk *xclk; /* external clock for GC2145 */
++
++	struct regulator_bulk_data supplies[GC2145_NUM_SUPPLIES];
++	struct gpio_desc *reset_gpio; // nrst pin
++	struct gpio_desc *enable_gpio; // ce pin
++
++	/* lock to protect all members below */
++	struct mutex lock;
++
++	struct v4l2_mbus_framefmt fmt;
++	struct v4l2_fract frame_interval;
++	struct gc2145_ctrls ctrls;
++
++	bool pending_mode_change;
++	bool powered;
++	bool streaming;
++
++	u8 current_bank;
++
++	struct gc2145_tx_op ops[GC2145_MAX_OPS];
++	int n_ops;
++	int tx_started;
++};
++
++static inline struct gc2145_dev *to_gc2145_dev(struct v4l2_subdev *sd)
++{
++	return container_of(sd, struct gc2145_dev, sd);
++}
++
++/* {{{ Register access helpers */
++
++static int gc2145_write_regs(struct gc2145_dev *sensor, u8 addr,
++			     u8 *data, int data_size)
++{
++	struct i2c_client *client = sensor->i2c_client;
++	struct i2c_msg msg;
++	u8 buf[128 + 1];
++	int ret;
++
++	if (data_size > sizeof(buf) - 1) {
++		v4l2_err(&sensor->sd, "%s: oversized transfer (size=%d)\n",
++			 __func__, data_size);
++		return -EINVAL;
++	}
++
++	buf[0] = addr;
++	memcpy(buf + 1, data, data_size);
++
++	msg.addr = client->addr;
++	msg.flags = client->flags;
++	msg.buf = buf;
++	msg.len = data_size + 1;
++
++	dev_dbg(&sensor->i2c_client->dev, "[wr %02x] <= %*ph\n",
++		(u32)addr, data_size, data);
++
++	ret = i2c_transfer(client->adapter, &msg, 1);
++	if (ret < 0) {
++		v4l2_err(&sensor->sd,
++			 "%s: error %d: addr=%x, data=%*ph\n",
++			 __func__, ret, (u32)addr, data_size, data);
++		return ret;
++	}
++
++	return 0;
++}
++
++static int gc2145_read_regs(struct gc2145_dev *sensor, u8 addr,
++			    u8 *data, int data_size)
++{
++	struct i2c_client *client = sensor->i2c_client;
++	struct i2c_msg msg[2];
++	int ret;
++
++	msg[0].addr = client->addr;
++	msg[0].flags = client->flags;
++	msg[0].buf = &addr;
++	msg[0].len = 1;
++
++	msg[1].addr = client->addr;
++	msg[1].flags = client->flags | I2C_M_RD;
++	msg[1].buf = data;
++	msg[1].len = data_size;
++
++	ret = i2c_transfer(client->adapter, msg, 2);
++	if (ret < 0) {
++		v4l2_err(&sensor->sd,
++			 "%s: error %d: start_index=%x, data_size=%d\n",
++			 __func__, ret, (u32)addr, data_size);
++		return ret;
++	}
++
++	dev_dbg(&sensor->i2c_client->dev, "[rd %02x] => %*ph\n",
++		(u32)addr, data_size, data);
++
++	return 0;
++}
++
++static int gc2145_switch_bank(struct gc2145_dev *sensor, u16 reg)
++{
++	int ret;
++	u8 bank = reg >> 8;
++
++	if (bank & ~3u)
++		return -ERANGE;
++
++	if (sensor->current_bank != bank) {
++		ret = gc2145_write_regs(sensor, GC2145_REG_RESET, &bank, 1);
++		if (ret)
++			return ret;
++
++		sensor->current_bank = bank;
++		dev_info(&sensor->i2c_client->dev, "bank switch: 0x%02x\n",
++				(unsigned int)sensor->current_bank);
++	}
++
++	return 0;
++}
++
++static int gc2145_read(struct gc2145_dev *sensor, u16 reg, u8 *val)
++{
++	int ret;
++
++	ret = gc2145_switch_bank(sensor, reg);
++	if (ret)
++		return ret;
++
++	return gc2145_read_regs(sensor, reg, val, 1);
++}
++
++static int gc2145_write(struct gc2145_dev *sensor, u16 reg, u8 val)
++{
++	int ret;
++
++	ret = gc2145_switch_bank(sensor, reg);
++	if (ret)
++		return ret;
++
++	if ((reg & 0xffu) == GC2145_REG_RESET)
++		sensor->current_bank = val & 3;
++
++	return gc2145_write_regs(sensor, reg, &val, 1);
++}
++
++static int gc2145_update_bits(struct gc2145_dev *sensor, u16 reg, u8 mask, u8 val)
++{
++	int ret;
++	u8 tmp;
++
++	ret = gc2145_read(sensor, reg, &tmp);
++	if (ret)
++		return ret;
++
++	tmp &= ~mask;
++	tmp |= val & mask;
++
++	return gc2145_write(sensor, reg, tmp);
++}
++
++static int gc2145_read16(struct gc2145_dev *sensor, u16 reg, u16 *val)
++{
++	int ret;
++
++	ret = gc2145_switch_bank(sensor, reg);
++	if (ret)
++		return ret;
++
++	ret = gc2145_read_regs(sensor, reg, (u8 *)val, sizeof(*val));
++	if (ret)
++		return ret;
++
++	*val = be16_to_cpu(*val);
++	return 0;
++}
++
++static int gc2145_write16(struct gc2145_dev *sensor, u16 reg, u16 val)
++{
++	u16 tmp = cpu_to_be16(val);
++	int ret;
++
++	ret = gc2145_switch_bank(sensor, reg);
++	if (ret)
++		return ret;
++
++	return gc2145_write_regs(sensor, reg, (u8 *)&tmp, sizeof(tmp));
++}
++
++static void gc2145_tx_start(struct gc2145_dev *sensor)
++{
++	if (sensor->tx_started++)
++		dev_err(&sensor->i2c_client->dev,
++				"tx_start called multiple times\n");
++
++	sensor->n_ops = 0;
++}
++
++static void gc2145_tx_add(struct gc2145_dev *sensor, int kind,
++			  u16 reg, u16 val, u16 mask)
++{
++	struct gc2145_tx_op *op;
++
++	if (!sensor->tx_started) {
++		dev_err(&sensor->i2c_client->dev,
++				"op added without calling tx_start\n");
++		return;
++	}
++
++	if (sensor->n_ops >= ARRAY_SIZE(sensor->ops)) {
++		dev_err(&sensor->i2c_client->dev,
++				"ops overflow, increase GC2145_MAX_OPS\n");
++		return;
++	}
++
++	op = &sensor->ops[sensor->n_ops++];
++	op->op = kind;
++	op->reg = reg;
++	op->val = val;
++	op->mask = mask;
++}
++
++static void gc2145_tx_write8(struct gc2145_dev *sensor, u16 reg, u8 val)
++{
++	return gc2145_tx_add(sensor, TX_WRITE, reg, val, 0);
++}
++
++static void gc2145_tx_write16(struct gc2145_dev *sensor, u16 reg, u16 val)
++{
++	return gc2145_tx_add(sensor, TX_WRITE16, reg, val, 0);
++}
++
++static void gc2145_tx_update_bits(struct gc2145_dev *sensor, u16 reg,
++				  u8 mask, u8 val)
++{
++	return gc2145_tx_add(sensor, TX_UPDATE_BITS, reg, val, mask);
++}
++
++static int gc2145_tx_commit(struct gc2145_dev *sensor)
++{
++	struct gc2145_tx_op* op;
++	int i, ret, n_ops;
++
++	if (!sensor->tx_started) {
++		dev_err(&sensor->i2c_client->dev,
++				"tx_commit called without tx_start\n");
++		return 0;
++	}
++
++	n_ops = sensor->n_ops;
++	sensor->tx_started = 0;
++	sensor->n_ops = 0;
++
++	for (i = 0; i < n_ops; i++) {
++		op = &sensor->ops[i];
++
++		switch (op->op) {
++		case TX_WRITE:
++			ret = gc2145_write(sensor, op->reg, op->val);
++			break;
++		case TX_WRITE16:
++			ret = gc2145_write16(sensor, op->reg, op->val);
++			break;
++		case TX_UPDATE_BITS:
++			ret = gc2145_update_bits(sensor, op->reg, op->mask, op->val);
++			break;
++		default:
++			dev_err(&sensor->i2c_client->dev, "invalid op at %d\n", i);
++			ret = -EINVAL;
++		}
++
++		if (ret)
++			return ret;
++	}
++
++	return 0;
++}
++
++/*
++ * Efficiently write to a set of registers, using auto-increment
++ * when possible. User must not use address 0xff. To switch banks,
++ * use sequence: 0xfe, bank_no.
++ */
++static int gc2145_set_registers(struct gc2145_dev *sensor,
++				const uint8_t* data, size_t data_len)
++{
++	int ret = 0, i = 0;
++	u16 start, len;
++	u8 buf[128];
++
++	if (data_len % 2 != 0) {
++		v4l2_err(&sensor->sd, "Register map has invalid size\n");
++		return -EINVAL;
++	}
++
++	/* we speed up communication by using auto-increment functionality */
++	while (i < data_len) {
++		start = data[i];
++		len = 0;
++
++		while (i < data_len && data[i] == (start + len) &&
++		       len < sizeof(buf)) {
++			buf[len++] = data[i + 1];
++			i += 2;
++		}
++
++		ret = gc2145_write_regs(sensor, start, buf, len);
++		if (ret)
++			return ret;
++	}
++
++	sensor->current_bank = 0xff;
++	return 0;
++}
++
++/*
++ * The firmware format:
++ * <record 0>, ..., <record N - 1>
++ * "record" is a 1-byte register address followed by 1-byte data
++ */
++static int gc2145_load_firmware(struct gc2145_dev *sensor, const char *name)
++{
++	const struct firmware *fw;
++	int ret;
++
++	ret = request_firmware(&fw, name, sensor->sd.v4l2_dev->dev);
++	if (ret) {
++		v4l2_warn(&sensor->sd,
++			  "Failed to read firmware %s, continuing anyway...\n",
++			  name);
++		return 1;
++	}
++
++	if (fw->size == 0)
++		return 1;
++
++	ret = gc2145_set_registers(sensor, fw->data, fw->size);
++
++	release_firmware(fw);
++	return ret;
++}
++
++/* }}} */
++/* {{{ Controls */
++
++static inline struct v4l2_subdev *ctrl_to_sd(struct v4l2_ctrl *ctrl)
++{
++	return &container_of(ctrl->handler, struct gc2145_dev,
++			     ctrls.handler)->sd;
++}
++
++#if 0
++static const u8 gc2145_wb_opts[][2] = {
++	{ V4L2_WHITE_BALANCE_MANUAL, GC2145_REG_WB_MODE_OFF },
++	{ V4L2_WHITE_BALANCE_INCANDESCENT, GC2145_REG_WB_MODE_TUNGSTEN_PRESET },
++	{ V4L2_WHITE_BALANCE_FLUORESCENT,
++		GC2145_REG_WB_MODE_FLUORESCENT_PRESET },
++	{ V4L2_WHITE_BALANCE_HORIZON, GC2145_REG_WB_MODE_HORIZON_PRESET },
++	{ V4L2_WHITE_BALANCE_CLOUDY, GC2145_REG_WB_MODE_CLOUDY_PRESET },
++	{ V4L2_WHITE_BALANCE_DAYLIGHT, GC2145_REG_WB_MODE_SUNNY_PRESET },
++	{ V4L2_WHITE_BALANCE_AUTO, GC2145_REG_WB_MODE_AUTOMATIC },
++};
++
++static int gc2145_set_power_line_frequency(struct gc2145_dev *sensor, s32 val)
++{
++	u16 freq;
++	int ret;
++
++	switch (val) {
++	case V4L2_CID_POWER_LINE_FREQUENCY_DISABLED:
++		ret = gc2145_write(sensor, GC2145_REG_ANTI_FLICKER_MODE, 0);
++		if (ret)
++			return ret;
++
++		return gc2145_write(sensor, GC2145_REG_FD_ENABLE_DETECT, 0);
++	case V4L2_CID_POWER_LINE_FREQUENCY_50HZ:
++	case V4L2_CID_POWER_LINE_FREQUENCY_60HZ:
++		ret = gc2145_write(sensor, GC2145_REG_ANTI_FLICKER_MODE, 1);
++		if (ret)
++			return ret;
++
++		ret = gc2145_write(sensor, GC2145_REG_FD_ENABLE_DETECT, 0);
++		if (ret)
++			return ret;
++
++		freq = (val == V4L2_CID_POWER_LINE_FREQUENCY_50HZ) ?
++			0x4b20 : 0x4bc0;
++
++		return gc2145_write16(sensor, GC2145_REG_FD_FLICKER_FREQUENCY,
++				      freq);
++	case V4L2_CID_POWER_LINE_FREQUENCY_AUTO:
++		ret = gc2145_write(sensor, GC2145_REG_FD_ENABLE_DETECT, 1);
++		if (ret)
++			return ret;
++
++		ret = gc2145_write(sensor, GC2145_REG_ANTI_FLICKER_MODE, 1);
++		if (ret)
++			return ret;
++
++		ret = gc2145_write16(sensor, GC2145_REG_FD_MAX_NUMBER_ATTEMP,
++				     100);
++		if (ret)
++			return ret;
++
++		ret = gc2145_write16(sensor, GC2145_REG_FD_FLICKER_FREQUENCY,
++				     0);
++		if (ret)
++			return ret;
++
++		return gc2145_write(sensor, GC2145_REG_FD_DETECTION_START, 1);
++	default:
++		return -EINVAL;
++	}
++}
++
++static int gc2145_set_colorfx(struct gc2145_dev *sensor, s32 val)
++{
++	int ret;
++
++	ret = gc2145_write(sensor, GC2145_REG_EFFECTS_COLOR,
++			   GC2145_REG_EFFECTS_COLOR_NORMAL);
++	if (ret)
++		return ret;
++
++	ret = gc2145_write(sensor, GC2145_REG_EFFECTS_NEGATIVE, 0);
++	if (ret)
++		return ret;
++
++	ret = gc2145_write(sensor, GC2145_REG_EFFECTS_SOLARISING, 0);
++	if (ret)
++		return ret;
++
++	ret = gc2145_write(sensor, GC2145_REG_EFFECTS_SKECTH, 0);
++	if (ret)
++		return ret;
++
++	switch (val) {
++	case V4L2_COLORFX_NONE:
++		return 0;
++	case V4L2_COLORFX_NEGATIVE:
++		return gc2145_write(sensor, GC2145_REG_EFFECTS_NEGATIVE, 1);
++	case V4L2_COLORFX_SOLARIZATION:
++		return gc2145_write(sensor, GC2145_REG_EFFECTS_SOLARISING, 1);
++	case V4L2_COLORFX_SKETCH:
++		return gc2145_write(sensor, GC2145_REG_EFFECTS_SKECTH, 1);
++	case V4L2_COLORFX_ANTIQUE:
++		return gc2145_write(sensor, GC2145_REG_EFFECTS_COLOR,
++				    GC2145_REG_EFFECTS_COLOR_ANTIQUE);
++	case V4L2_COLORFX_SEPIA:
++		return gc2145_write(sensor, GC2145_REG_EFFECTS_COLOR,
++				    GC2145_REG_EFFECTS_COLOR_SEPIA);
++	case V4L2_COLORFX_AQUA:
++		return gc2145_write(sensor, GC2145_REG_EFFECTS_COLOR,
++				    GC2145_REG_EFFECTS_COLOR_AQUA);
++	case V4L2_COLORFX_BW:
++		return gc2145_write(sensor, GC2145_REG_EFFECTS_COLOR,
++				    GC2145_REG_EFFECTS_COLOR_BLACK_WHITE);
++	default:
++		return -EINVAL;
++	}
++}
++
++static int gc2145_3a_lock(struct gc2145_dev *sensor, struct v4l2_ctrl *ctrl)
++{
++	bool awb_lock = ctrl->val & V4L2_LOCK_WHITE_BALANCE;
++	bool ae_lock = ctrl->val & V4L2_LOCK_EXPOSURE;
++	int ret = 0;
++
++	if ((ctrl->val ^ ctrl->cur.val) & V4L2_LOCK_EXPOSURE
++	    && sensor->ctrls.auto_exposure->val == V4L2_EXPOSURE_AUTO) {
++		ret = gc2145_write(sensor, GC2145_REG_FREEZE_AUTO_EXPOSURE,
++				   ae_lock);
++		if (ret)
++			return ret;
++	}
++
++	if (((ctrl->val ^ ctrl->cur.val) & V4L2_LOCK_WHITE_BALANCE)
++	    && sensor->ctrls.wb->val == V4L2_WHITE_BALANCE_AUTO) {
++		ret = gc2145_write(sensor, GC2145_REG_WB_MISC_SETTINGS,
++				   awb_lock ?
++				   GC2145_REG_WB_MISC_SETTINGS_FREEZE_ALGO : 0);
++		if (ret)
++			return ret;
++	}
++
++	return ret;
++}
++
++static int gc2145_set_white_balance(struct gc2145_dev *sensor)
++{
++	struct gc2145_ctrls *ctrls = &sensor->ctrls;
++	bool manual_wb = ctrls->wb->val == V4L2_WHITE_BALANCE_MANUAL;
++	int ret = 0, i;
++	s32 val;
++
++	if (ctrls->wb->is_new) {
++		for (i = 0; i < ARRAY_SIZE(gc2145_wb_opts); i++) {
++			if (gc2145_wb_opts[i][0] != ctrls->wb->val)
++				continue;
++
++			ret = gc2145_write(sensor, GC2145_REG_WB_MODE,
++					    gc2145_wb_opts[i][1]);
++			if (ret)
++				return ret;
++			goto next;
++		}
++
++		return -EINVAL;
++	}
++
++next:
++	if (ctrls->wb->is_new || ctrls->blue_balance->is_new) {
++		val = manual_wb ? ctrls->blue_balance->val : 1000;
++		ret = gc2145_write16(sensor, GC2145_REG_WB_HUE_B_BIAS,
++				     gc2145_mili_to_fp16(val));
++		if (ret)
++			return ret;
++	}
++
++	if (ctrls->wb->is_new || ctrls->red_balance->is_new) {
++		val = manual_wb ? ctrls->red_balance->val : 1000;
++		ret = gc2145_write16(sensor, GC2145_REG_WB_HUE_R_BIAS,
++				     gc2145_mili_to_fp16(val));
++	}
++
++	return ret;
++}
++
++#endif
++
++/* Exposure */
++
++static int gc2145_get_exposure(struct gc2145_dev *sensor)
++{
++	struct gc2145_ctrls *ctrls = &sensor->ctrls;
++	u8 again, dgain;
++	u16 exp;
++	int ret;
++
++	ret = gc2145_read(sensor, 0xb1, &again);
++	if (ret)
++		return ret;
++
++	ret = gc2145_read(sensor, 0xb2, &dgain);
++	if (ret)
++		return ret;
++
++	ret = gc2145_read16(sensor, 0x03, &exp);
++	if (ret)
++		return ret;
++
++	ctrls->exposure->val = exp;
++	ctrls->d_gain->val = dgain;
++	ctrls->a_gain->val = again;
++
++	return 0;
++}
++
++#define AE_BIAS_MENU_DEFAULT_VALUE_INDEX 4
++static const s64 ae_bias_menu_values[] = {
++	-4000, -3000, -2000, -1000, 0, 1000, 2000, 3000, 4000
++};
++
++static const s8 ae_bias_menu_reg_values[] = {
++	0x55, 0x60, 0x65, 0x70, 0x7b, 0x85, 0x90, 0x95, 0xa0
++};
++
++static int gc2145_set_exposure(struct gc2145_dev *sensor)
++{
++	struct gc2145_ctrls *ctrls = &sensor->ctrls;
++	bool is_auto = (ctrls->auto_exposure->val != V4L2_EXPOSURE_MANUAL);
++
++	gc2145_tx_start(sensor);
++
++	if (ctrls->auto_exposure->is_new) {
++		gc2145_tx_write8(sensor, 0xb6, is_auto ? 1 : 0);
++
++		//XXX: remove?
++		//if (ctrls->auto_exposure->cur.val != ctrls->auto_exposure->val &&
++		    //!is_auto) {
++			/*
++			 * Hack: At this point, there are current volatile
++			 * values in val, but control framework will not
++			 * update the cur values for our autocluster, as it
++			 * should. I couldn't find the reason. This fixes
++			 * it for our driver. Remove this after the kernel
++			 * is fixed.
++			 */
++			//ctrls->exposure->cur.val = ctrls->exposure->val;
++			//ctrls->d_gain->cur.val = ctrls->d_gain->val;
++			//ctrls->a_gain->cur.val = ctrls->a_gain->val;
++		//}
++	}
++
++	if (!is_auto && ctrls->exposure->is_new)
++		gc2145_tx_write16(sensor, 0x03, ctrls->exposure->val);
++
++	if (!is_auto && ctrls->d_gain->is_new)
++		gc2145_tx_write8(sensor, 0xb2, ctrls->d_gain->val);
++
++	if (!is_auto && ctrls->a_gain->is_new)
++		gc2145_tx_write8(sensor, 0xb1, ctrls->a_gain->val);
++
++	return gc2145_tx_commit(sensor);;
++}
++
++/* Test patterns */
++
++enum {
++	GC2145_TEST_PATTERN_DISABLED,
++	GC2145_TEST_PATTERN_VGA_COLOR_BARS,
++	GC2145_TEST_PATTERN_UXGA_COLOR_BARS,
++	GC2145_TEST_PATTERN_SKIN_MAP,
++	GC2145_TEST_PATTERN_SOLID_COLOR,
++};
++
++static const char * const test_pattern_menu[] = {
++	"Disabled",
++	"VGA color bars",
++	"UXGA color bars",
++	"Skin map",
++	"Solid black color",
++	"Solid light gray color",
++	"Solid gray color",
++	"Solid dark gray color",
++	"Solid white color",
++	"Solid red color",
++	"Solid green color",
++	"Solid blue color",
++	"Solid yellow color",
++	"Solid cyan color",
++	"Solid magenta color",
++};
++
++static int gc2145_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = ctrl_to_sd(ctrl);
++	struct gc2145_dev *sensor = to_gc2145_dev(sd);
++	int ret;
++
++	/* v4l2_ctrl_lock() locks our own mutex */
++
++	if (!sensor->powered)
++		return -EIO;
++
++	switch (ctrl->id) {
++	case V4L2_CID_EXPOSURE_AUTO:
++		ret = gc2145_get_exposure(sensor);
++		if (ret)
++			return ret;
++		break;
++	default:
++		dev_err(&sensor->i2c_client->dev, "getting unknown control %d\n", ctrl->id);
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static int gc2145_s_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = ctrl_to_sd(ctrl);
++	struct gc2145_dev *sensor = to_gc2145_dev(sd);
++	struct gc2145_ctrls *ctrls = &sensor->ctrls;
++	s32 val = ctrl->val;
++	unsigned int i;
++	int ret;
++	u8 test1, test2;
++
++	/* v4l2_ctrl_lock() locks our own mutex */
++
++	/*
++	 * If the device is not powered up by the host driver do
++	 * not apply any controls to H/W at this time. Instead
++	 * the controls will be restored right after power-up.
++	 */
++	if (!sensor->powered)
++		return 0;
++
++	switch (ctrl->id) {
++	case V4L2_CID_EXPOSURE_AUTO:
++		return gc2145_set_exposure(sensor);
++
++	case V4L2_CID_AUTO_EXPOSURE_BIAS:
++		if (val < 0 || val >= ARRAY_SIZE(ae_bias_menu_reg_values)) {
++			dev_err(&sensor->i2c_client->dev, "ae bias out of range\n");
++			return -EINVAL;
++		}
++
++		return gc2145_write(sensor, 0x113,
++				    (u8)ae_bias_menu_reg_values[val]);
++
++	case V4L2_CID_VFLIP:
++		return gc2145_update_bits(sensor, 0x17, BIT(1), val ? BIT(1) : 0);
++
++	case V4L2_CID_HFLIP:
++		return gc2145_update_bits(sensor, 0x17, BIT(0), val ? BIT(0) : 0);
++
++	case V4L2_CID_TEST_PATTERN:
++		for (i = 0; i < ARRAY_SIZE(ctrls->test_data); i++)
++			v4l2_ctrl_activate(ctrls->test_data[i],
++					   val == 6); /* solid color */
++
++		test1 = 0;
++		test2 = 0x01;
++
++		if (val == GC2145_TEST_PATTERN_VGA_COLOR_BARS)
++			test1 = 0x04;
++		else if (val == GC2145_TEST_PATTERN_UXGA_COLOR_BARS)
++			test1 = 0x44;
++		else if (val == GC2145_TEST_PATTERN_SKIN_MAP)
++			test1 = 0x10;
++		else if (val >= GC2145_TEST_PATTERN_SOLID_COLOR) {
++			test1 = 0x04;
++			test2 = ((val - GC2145_TEST_PATTERN_SOLID_COLOR) << 4) | 0x8;
++		} else if (val != GC2145_TEST_PATTERN_DISABLED) {
++			dev_err(&sensor->i2c_client->dev, "test pattern out of range\n");
++			return -EINVAL;
++		}
++
++		ret = gc2145_write(sensor, 0x8c, test1);
++		if (ret)
++			return ret;
++
++		return gc2145_write(sensor, 0x8d, test2);
++
++#if 0
++	case V4L2_CID_EXPOSURE_METERING:
++		if (val == V4L2_EXPOSURE_METERING_AVERAGE)
++			reg = GC2145_REG_EXPOSURE_METERING_FLAT;
++		else if (val == V4L2_EXPOSURE_METERING_CENTER_WEIGHTED)
++			reg = GC2145_REG_EXPOSURE_METERING_CENTERED;
++		else
++			return -EINVAL;
++
++		return gc2145_write(sensor, GC2145_REG_EXPOSURE_METERING, reg);
++
++	case V4L2_CID_CONTRAST:
++		return gc2145_write(sensor, GC2145_REG_CONTRAST, val);
++
++	case V4L2_CID_SATURATION:
++		return gc2145_write(sensor, GC2145_REG_COLOR_SATURATION, val);
++
++	case V4L2_CID_BRIGHTNESS:
++		return gc2145_write(sensor, GC2145_REG_BRIGHTNESS, val);
++
++	case V4L2_CID_POWER_LINE_FREQUENCY:
++		return gc2145_set_power_line_frequency(sensor, val);
++
++	case V4L2_CID_GAMMA:
++		return gc2145_write(sensor, GC2145_REG_P0_GAMMA_GAIN, val);
++
++	case V4L2_CID_COLORFX:
++		return gc2145_set_colorfx(sensor, val);
++
++	case V4L2_CID_3A_LOCK:
++		return gc2145_3a_lock(sensor, ctrl);
++
++	case V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE:
++		return gc2145_set_white_balance(sensor);
++
++	case V4L2_CID_TEST_PATTERN_RED:
++		return gc2145_write16(sensor, GC2145_REG_TESTDATA_RED, val);
++
++	case V4L2_CID_TEST_PATTERN_GREENR:
++		return gc2145_write16(sensor, GC2145_REG_TESTDATA_GREEN_R, val);
++
++	case V4L2_CID_TEST_PATTERN_BLUE:
++		return gc2145_write16(sensor, GC2145_REG_TESTDATA_BLUE, val);
++
++	case V4L2_CID_TEST_PATTERN_GREENB:
++		return gc2145_write16(sensor, GC2145_REG_TESTDATA_GREEN_B, val);
++
++#endif
++	default:
++		dev_err(&sensor->i2c_client->dev, "setting unknown control %d\n", ctrl->id);
++		return -EINVAL;
++	}
++}
++
++static const struct v4l2_ctrl_ops gc2145_ctrl_ops = {
++	.g_volatile_ctrl = gc2145_g_volatile_ctrl,
++	.s_ctrl = gc2145_s_ctrl,
++};
++
++static int gc2145_init_controls(struct gc2145_dev *sensor)
++{
++	const struct v4l2_ctrl_ops *ops = &gc2145_ctrl_ops;
++	struct gc2145_ctrls *ctrls = &sensor->ctrls;
++	struct v4l2_ctrl_handler *hdl = &ctrls->handler;
++	//u8 wb_max = 0;
++	//u64 wb_mask = 0;
++	//unsigned int i;
++	int ret;
++
++	v4l2_ctrl_handler_init(hdl, 32);
++
++	/* we can use our own mutex for the ctrl lock */
++	hdl->lock = &sensor->lock;
++
++	/* Exposure controls */
++	ctrls->auto_exposure = v4l2_ctrl_new_std_menu(hdl, ops,
++						      V4L2_CID_EXPOSURE_AUTO,
++						      V4L2_EXPOSURE_MANUAL, 0,
++						      V4L2_EXPOSURE_AUTO);
++	ctrls->exposure = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_EXPOSURE,
++					    1, 0x1fff, 1, 0x80);
++	ctrls->a_gain = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_ANALOGUE_GAIN,
++					  0, 255, 1, 0x20);
++	ctrls->d_gain = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_DIGITAL_GAIN,
++					  0, 255, 1, 0x40);
++	ctrls->exposure_bias =
++		v4l2_ctrl_new_int_menu(hdl, ops, V4L2_CID_AUTO_EXPOSURE_BIAS,
++				       ARRAY_SIZE(ae_bias_menu_values) - 1,
++				       AE_BIAS_MENU_DEFAULT_VALUE_INDEX,
++				       ae_bias_menu_values);
++
++	/* V/H flips */
++	ctrls->hflip = v4l2_ctrl_new_std(hdl, ops,
++					 V4L2_CID_HFLIP, 0, 1, 1, 0);
++	ctrls->vflip = v4l2_ctrl_new_std(hdl, ops,
++					 V4L2_CID_VFLIP, 0, 1, 1, 0);
++
++
++	/* Test patterns */
++	ctrls->test_pattern =
++		v4l2_ctrl_new_std_menu_items(hdl, ops, V4L2_CID_TEST_PATTERN,
++					     ARRAY_SIZE(test_pattern_menu) - 1,
++					     0, 0, test_pattern_menu);
++#if 0
++
++	ctrls->metering =
++		v4l2_ctrl_new_std_menu(hdl, ops, V4L2_CID_EXPOSURE_METERING,
++				       V4L2_EXPOSURE_METERING_CENTER_WEIGHTED,
++				       0, V4L2_EXPOSURE_METERING_AVERAGE);
++
++	for (i = 0; i < ARRAY_SIZE(gc2145_wb_opts); i++) {
++		if (wb_max < gc2145_wb_opts[i][0])
++			wb_max = gc2145_wb_opts[i][0];
++		wb_mask |= BIT(gc2145_wb_opts[i][0]);
++	}
++
++	ctrls->wb = v4l2_ctrl_new_std_menu(hdl, ops,
++			V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE,
++			wb_max, ~wb_mask, V4L2_WHITE_BALANCE_AUTO);
++
++	ctrls->blue_balance = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BLUE_BALANCE,
++						0, 4000, 1, 1000);
++	ctrls->red_balance = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_RED_BALANCE,
++					       0, 4000, 1, 1000);
++
++	ctrls->gamma = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAMMA,
++					 0, 31, 1, 20);
++
++	ctrls->colorfx =
++		v4l2_ctrl_new_std_menu(hdl, ops, V4L2_CID_COLORFX, 15,
++				       ~(BIT(V4L2_COLORFX_NONE) |
++					 BIT(V4L2_COLORFX_NEGATIVE) |
++					 BIT(V4L2_COLORFX_SOLARIZATION) |
++					 BIT(V4L2_COLORFX_SKETCH) |
++					 BIT(V4L2_COLORFX_SEPIA) |
++					 BIT(V4L2_COLORFX_ANTIQUE) |
++					 BIT(V4L2_COLORFX_AQUA) |
++					 BIT(V4L2_COLORFX_BW)),
++				       V4L2_COLORFX_NONE);
++
++	ctrls->pl_freq =
++		v4l2_ctrl_new_std_menu(hdl, ops, V4L2_CID_POWER_LINE_FREQUENCY,
++				V4L2_CID_POWER_LINE_FREQUENCY_AUTO, 0,
++				V4L2_CID_POWER_LINE_FREQUENCY_50HZ);
++
++	ctrls->brightness = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BRIGHTNESS,
++					      0, 200, 1, 90);
++	ctrls->saturation = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_SATURATION,
++					      0, 200, 1, 110);
++	ctrls->contrast = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST,
++					    0, 200, 1, 108);
++
++	ctrls->aaa_lock = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_3A_LOCK,
++					    0, 0x7, 0, 0);
++
++	for (i = 0; i < ARRAY_SIZE(ctrls->test_data); i++)
++		ctrls->test_data[i] =
++			v4l2_ctrl_new_std(hdl, ops,
++					  V4L2_CID_TEST_PATTERN_RED + i,
++					  0, 1023, 1, 0);
++
++	ctrls->af_status->flags |= V4L2_CTRL_FLAG_VOLATILE |
++		V4L2_CTRL_FLAG_READ_ONLY;
++
++	v4l2_ctrl_auto_cluster(3, &ctrls->wb, V4L2_WHITE_BALANCE_MANUAL, false);
++#endif
++
++	v4l2_ctrl_auto_cluster(4, &ctrls->auto_exposure, V4L2_EXPOSURE_MANUAL,
++			       true);
++
++	if (hdl->error) {
++		ret = hdl->error;
++		goto free_ctrls;
++	}
++
++	sensor->sd.ctrl_handler = hdl;
++	return 0;
++
++free_ctrls:
++	v4l2_ctrl_handler_free(hdl);
++	return ret;
++}
++
++/* }}} */
++/* {{{ Video ops */
++
++/*
++ * Clock tree
++ * ----------
++ *
++ *     MCLK pin
++ *         |
++ *  DIV2 (optional)        - Divide input MCLK by 2 when 0xf7[1] == 1
++ *         |
++ *   /- PLL mux -\         - PLL selected by 0xf8[7], otherwise fixed 32x mult
++ *   |           |
++ * PLL           |         - PLL multiplies by 0xf8[5:0]+1 * 4
++ *   |      Fixed 32/48x   - Multiplies 32x when 0xf7[2] == 1 otherwise 48x
++ *    \_________/
++ *         |
++ *       DOUBLE  (div by 4 or 8) based on 0xf7[3]
++ *         |
++ *     /-------\
++ *     |       |
++ * pclk_div  sclk_div
++ *     |       |
++ *   2pclk    sclk
++ */
++__maybe_unused
++static int gc2145_get_2pclk(struct gc2145_dev *sensor, unsigned long* pclk)
++{
++	u8 pll_mode1, pll_mode2, clk_div_mode;
++	bool mclk_div2_en; // 0xf7[1]
++	bool pll_en; // 0xf8[7]
++	bool double_clk; // 0xf7[3]
++	bool fixed_32x; // 0xf7[2]
++	unsigned long pll_mult; // 0xf8[5:0] + 1
++	unsigned long sclk_div; // 1 << (0xf7[5:4] + 1)
++	unsigned long pclk_div; // 0xfa[7:4] + 1
++	unsigned long int_clk;
++	unsigned long mclk;
++        int ret;
++
++	ret = gc2145_read(sensor, 0xf7, &pll_mode1);
++	if (ret)
++		return ret;
++
++	ret = gc2145_read(sensor, 0xf8, &pll_mode2);
++	if (ret)
++		return ret;
++
++	ret = gc2145_read(sensor, 0xfa, &clk_div_mode);
++	if (ret)
++		return ret;
++
++	mclk = clk_get_rate(sensor->xclk);
++	if (mclk == 0)
++		return -EINVAL;
++
++	mclk_div2_en = pll_mode1 & BIT(1);
++	pll_en = pll_mode2 & BIT(7);
++	double_clk = pll_mode1 & BIT(3);
++	fixed_32x = pll_mode1 & BIT(2);
++	pll_mult = (pll_mode2 & 0x3f) + 1;
++	pclk_div = (clk_div_mode >> 4) + 1;
++	sclk_div = 1 << (((pll_mode1 >> 4) & 0x3) + 1);
++
++	int_clk = mclk / (mclk_div2_en ? 2 : 1);
++
++	if (pll_en)
++		int_clk *= pll_mult * 4;
++	else
++		int_clk *= fixed_32x ? 32 : 48;
++
++	int_clk /= double_clk ? 4 : 8;
++
++	if (pclk)
++		*pclk = int_clk / pclk_div;
++
++	return 0;
++}
++
++static int gc2145_set_2pclk(struct gc2145_dev *sensor,
++			    unsigned long *freq, bool apply)
++{
++	unsigned long pll_mult, pll_mult_max, /*sclk_div,*/ pclk_div, pclk2,/* sclk,*/
++		      mclk;
++	unsigned long pll_mult_best = 0, pclk_div_best = 0, diff_best = ULONG_MAX, diff,
++		      pclk2_best = 0;
++	int mclk_div2_en; //, double_clk;
++	int mclk_div2_en_best = 0; //, double_clk_best;
++
++	mclk = clk_get_rate(sensor->xclk);
++	if (mclk == 0)
++		return -EINVAL;
++
++        for (mclk_div2_en = 0; mclk_div2_en <= 1; mclk_div2_en++) {
++		pll_mult_max = 768000000 / 4 / (mclk / (mclk_div2_en ? 2 : 1));
++		if (pll_mult_max > 32)
++			pll_mult_max = 32;
++
++		for (pll_mult = 2; pll_mult <= pll_mult_max; pll_mult++) {
++			for (pclk_div = 1; pclk_div <= 8; pclk_div++) {
++				pclk2 = mclk / (mclk_div2_en ? 2 : 1) * pll_mult / pclk_div;
++
++				if (pclk2 > *freq)
++					continue;
++
++				diff = *freq - pclk2;
++
++				if (diff < diff_best) {
++					diff_best = diff;
++					pclk2_best = pclk2;
++
++					pll_mult_best = pll_mult;
++					pclk_div_best = pclk_div;
++					mclk_div2_en_best = mclk_div2_en;
++				}
++
++				if (diff == 0)
++					goto found;
++			}
++		}
++	}
++
++	if (diff_best == ULONG_MAX)
++		return -1;
++
++found:
++	*freq = pclk2_best;
++	if (!apply)
++		return 0;
++
++	gc2145_tx_start(sensor);
++
++	gc2145_tx_write8(sensor, 0xf7,
++			 ((pclk_div_best - 1)) << 4 |
++			 (mclk_div2_en_best << 1) | BIT(0) /* pll_en */);
++	gc2145_tx_write8(sensor, 0xf8, BIT(7) | (pll_mult_best - 1));
++	gc2145_tx_write8(sensor, 0xfa,
++			 (pclk_div_best - 1) << 4 |
++			 (((pclk_div_best - 1) / 2) & 0xf));
++
++	return gc2145_tx_commit(sensor);
++}
++
++static int gc2145_setup_awb(struct gc2145_dev *sensor,
++			     u16 x1, u16 y1, u16 x2, u16 y2)
++{
++	int ratio = 8; //XXX: manual for gc2035 FAE says 4
++
++	gc2145_tx_start(sensor);
++
++	// disable awb
++	gc2145_tx_update_bits(sensor, 0x82, BIT(1), 0);
++
++	// reset white balance RGB gains
++	gc2145_tx_write8(sensor, 0xb3, 0x40);
++	gc2145_tx_write8(sensor, 0xb4, 0x40);
++	gc2145_tx_write8(sensor, 0xb5, 0x40);
++
++	// awb window
++	gc2145_tx_write8(sensor, 0x1ec, x1 / ratio);
++	gc2145_tx_write8(sensor, 0x1ed, y1 / ratio);
++	gc2145_tx_write8(sensor, 0x1ee, x2 / ratio);
++	gc2145_tx_write8(sensor, 0x1ef, y2 / ratio);
++
++	// eanble awb
++	gc2145_tx_update_bits(sensor, 0x82, BIT(1), BIT(1));
++
++	//1051  { 0xfe, 0x01 },
++	//1052  { 0x74, 0x01 },
++
++	return gc2145_tx_commit(sensor);
++}
++
++static int gc2145_setup_aec(struct gc2145_dev *sensor,
++			     u16 x1, u16 y1, u16 x2, u16 y2,
++			     u16 cx1, u16 cy1, u16 cx2, u16 cy2)
++{
++        u16 x_ratio = 8;
++
++	//XXX: gc2035 has x ratio 16
++	//XXX: gc2035 doesn't have low light mode
++	gc2145_tx_start(sensor);
++
++	// disable AEC
++	gc2145_tx_write8(sensor, 0xb6, 0);
++
++	// set reasonable initial exposure and gains
++	gc2145_tx_write16(sensor, 0x03, 1200);
++	gc2145_tx_write8(sensor, 0xb1, 0x20);
++	gc2145_tx_write8(sensor, 0xb2, 0xe0);
++
++	// setup measure window
++	gc2145_tx_write8(sensor, 0x101, x1 / x_ratio);
++	gc2145_tx_write8(sensor, 0x102, x2 / x_ratio);
++	gc2145_tx_write8(sensor, 0x103, y1 / 8);
++	gc2145_tx_write8(sensor, 0x104, y2 / 8);
++
++	// setup center
++	gc2145_tx_write8(sensor, 0x105, cx1 / x_ratio);
++	gc2145_tx_write8(sensor, 0x106, cx2 / x_ratio);
++	gc2145_tx_write8(sensor, 0x107, cy1 / 8);
++	gc2145_tx_write8(sensor, 0x108, cy2 / 8);
++
++	// increase maximum exposure level to 4
++	//gc2145_tx_write8(sensor, 0x13c, 0x60);
++	// setup AEC mode: measure point, adjust_max_gain, skip_mode = 2
++	//gc2145_tx_write8(sensor, 0x10a, 0xc2);
++
++	// AEC_ASDE_select_luma_value AEC_low_light_exp_THD_max:
++	//gc2145_tx_write8(sensor, 0x121, 0x15);
++
++	// enable AEC again
++	gc2145_tx_write8(sensor, 0xb6, 1);
++
++	return gc2145_tx_commit(sensor);
++}
++
++struct gc2145_sensor_params {
++	unsigned int enable_scaler;
++	unsigned int col_scaler_only;
++	unsigned int row_skip;
++	unsigned int col_skip;
++	unsigned long sh_delay;
++	unsigned long hb;
++	unsigned long vb;
++	unsigned long st;
++	unsigned long et;
++	unsigned long win_width;
++	unsigned long win_height;
++	unsigned long width;
++	unsigned long height;
++};
++
++static void gc2145_sensor_params_init(struct gc2145_sensor_params* p, int width, int height)
++{
++	p->win_height = height + 32;
++	p->win_width = (width + 16);
++	p->width = width;
++	p->height = height;
++	p->st = 2;
++	p->et = 2;
++	p->vb = 8;
++	p->hb = 0x1f0;
++	p->sh_delay = 30;
++}
++
++// unit is PCLK periods
++static unsigned long
++gc2145_sensor_params_get_row_period(struct gc2145_sensor_params* p)
++{
++	return 2 * (p->win_width / 2 / (p->col_skip + 1) + p->sh_delay + p->hb + 4);
++}
++
++static unsigned long
++gc2145_sensor_params_get_frame_period(struct gc2145_sensor_params* p)
++{
++	unsigned long rt = gc2145_sensor_params_get_row_period(p);
++
++	return rt * (p->vb + p->win_height) / (p->row_skip + 1);
++}
++
++static void
++gc2145_sensor_params_fit_hb_to_power_line_period(struct gc2145_sensor_params* p,
++					  unsigned long power_line_freq,
++					  unsigned long pclk)
++{
++	unsigned long rt, power_line_ratio;
++
++        for (p->hb = 0x1f0; p->hb < 2047; p->hb++) {
++		rt = gc2145_sensor_params_get_row_period(p);
++
++		// power_line_ratio is row_freq / power_line_freq * 1000
++                power_line_ratio = pclk / power_line_freq * 1000 / rt;
++
++		// if we're close enough, stop the search
++                if (power_line_ratio % 1000 < 50)
++                        break;
++        }
++
++	// finding the optimal Hb is not critical
++	if (p->hb == 2047)
++		p->hb = 0x1f0;
++}
++
++static void
++gc2145_sensor_params_fit_vb_to_frame_period(struct gc2145_sensor_params* p,
++				     unsigned long frame_period)
++{
++	unsigned long rt, fp;
++
++	p->vb = 8;
++	rt = gc2145_sensor_params_get_row_period(p);
++	fp = gc2145_sensor_params_get_frame_period(p);
++
++	if (frame_period > fp)
++		p->vb = frame_period * (p->row_skip + 1) / rt - p->win_height;
++
++	if (p->vb > 4095)
++		p->vb = 4095;
++}
++
++static int gc2145_sensor_params_apply(struct gc2145_dev *sensor,
++				      struct gc2145_sensor_params* p)
++{
++	u32 off_x = (GC2145_SENSOR_WIDTH_MAX - p->width) / 2;
++	u32 off_y = (GC2145_SENSOR_HEIGHT_MAX - p->height) / 2;
++
++	gc2145_tx_start(sensor);
++
++	gc2145_tx_write8(sensor, 0xfd, (p->enable_scaler ? BIT(0) : 0)
++			| (p->col_scaler_only ? BIT(1) : 0));
++
++	gc2145_tx_write8(sensor, 0x18, 0x0a
++		       | (p->col_skip ? BIT(7) : 0)
++		       | (p->row_skip ? BIT(6) : 0));
++
++	gc2145_tx_write16(sensor, 0x09, off_y);
++	gc2145_tx_write16(sensor, 0x0b, off_x);
++	gc2145_tx_write16(sensor, 0x0d, p->win_height);
++	gc2145_tx_write16(sensor, 0x0f, p->win_width);
++	gc2145_tx_write16(sensor, 0x05, p->hb);
++	gc2145_tx_write16(sensor, 0x07, p->vb);
++	gc2145_tx_write16(sensor, 0x11, p->sh_delay);
++
++	gc2145_tx_write8(sensor, 0x13, p->st);
++	gc2145_tx_write8(sensor, 0x14, p->et);
++
++	return gc2145_tx_commit(sensor);
++}
++
++static int gc2145_setup_mode(struct gc2145_dev *sensor)
++{
++	int scaling_desired, ret, pad, i;
++	struct gc2145_sensor_params params = {0};
++	unsigned long pclk2, frame_period;
++	unsigned long power_line_freq = 50;
++	unsigned long width = sensor->fmt.width;
++	unsigned long height = sensor->fmt.height;
++	unsigned long framerate = sensor->frame_interval.denominator;
++	const struct gc2145_pixfmt *pix_fmt;
++	unsigned long rt, ft, ft_rt;
++
++	pix_fmt = gc2145_find_format(sensor->fmt.code);
++	if (!pix_fmt) {
++		dev_err(&sensor->i2c_client->dev,
++			"pixel format not supported %u\n", sensor->fmt.code);
++		return -EINVAL;
++	}
++
++        /*
++	 * Equations for calculating framerate are:
++	 *
++	 *    ww = width + 16
++	 *    wh = height + 32
++	 *    Rt = (ww / 2 / (col_skip + 1) + sh_delay + Hb + 4)
++	 *    Ft = Rt * (Vb + wh) / (row_skip + 1)
++	 *    framerate = 2pclk / 4 / Ft
++	 *
++	 * Based on these equations:
++	 *
++	 * 1) First we need to determine what 2PCLK frequency to use. The 2PCLK
++	 *    frequency is not arbitrarily precise, so we need to calculate the
++	 *    actual frequency used, after setting our target frequency.
++	 *
++	 *    We use a simple heuristic:
++	 *
++	 *      If pixel_count * 2 * framerate * 1.15 is > 40MHz, we use 60MHz,
++	 *      otherwise we use 40MHz.
++	 *
++	 * 2) We want to determine lowest Hb that we can use to extend row
++	 *    period so that row time takes an integer fraction of the power
++	 *    line frequency period. Minimum Hb is 0x1f0.
++	 *
++	 * 3) If the requested resolution is less than half the sensor's size,
++	 *    we'll use scaling, or row skipping + column scaling, or row and
++	 *    column skiping, depending on what allows us to achieve the
++	 *    requested framerate.
++         *
++	 * 4) We use the selected Hb to calculate Vb value that will give
++	 *    us the desired framerate, given the scaling/skipping option
++	 *    selected in 3).
++	 */
++
++	scaling_desired = width <= GC2145_SENSOR_WIDTH_MAX / 2
++			&& height <= GC2145_SENSOR_HEIGHT_MAX / 2;
++
++	pclk2 = 60000000;
++
++	ret = gc2145_set_2pclk(sensor, &pclk2, false);
++	if (ret < 0)
++		return ret;
++
++	gc2145_sensor_params_init(&params, width, height);
++
++	// if the resolution is < half the sensor size, enable the scaler
++	// to cover more area of the chip
++	if (scaling_desired) {
++		params.enable_scaler = 1;
++		pclk2 *= 2;
++		gc2145_sensor_params_init(&params, width * 2, height * 2);
++	}
++
++	// we need to call this each time pclk or power_line_freq is changed
++	gc2145_sensor_params_fit_hb_to_power_line_period(&params,
++							 power_line_freq,
++							 pclk2 / 2);
++
++	frame_period = gc2145_sensor_params_get_frame_period(&params);
++	if (framerate <= pclk2 / 2 / frame_period)
++		goto apply;
++
++	if (scaling_desired) {
++		// try using just the column scaler + row skip
++		params.col_scaler_only = 1;
++		params.row_skip = 1;
++		gc2145_sensor_params_fit_hb_to_power_line_period(&params,
++								 power_line_freq,
++								 pclk2 / 2);
++
++		frame_period = gc2145_sensor_params_get_frame_period(&params);
++		if (framerate <= pclk2 / 2 / frame_period)
++			goto apply;
++
++
++		/*
++		// try disabling the scaler and just use skipping
++		params.enable_scaler = 0;
++		pclk2 /= 2;
++		params.col_scaler_only = 0;
++		params.col_skip = 1;
++		gc2145_sensor_params_fit_hb_to_power_line_period(&params, power_line_freq, pclk2 / 2);
++
++		frame_period = gc2145_sensor_params_get_frame_period(&params);
++
++		if (framerate <= pclk2 / 2 / frame_period)
++			goto apply;
++                  */
++	}
++
++apply:
++        // adjust vb to fit the target framerate
++	gc2145_sensor_params_fit_vb_to_frame_period(&params,
++						    pclk2 / 2 / framerate);
++
++	gc2145_sensor_params_apply(sensor, &params);
++
++	ret = gc2145_set_2pclk(sensor, &pclk2, true);
++	if (ret < 0)
++		return ret;
++
++	pad = (width > 256 && height > 256) ? 32 : 16;
++
++	ret = gc2145_setup_awb(sensor, pad, pad, width - pad * 2, height - pad * 2);
++	if (ret)
++		return ret;
++
++	ret = gc2145_setup_aec(sensor,
++				pad, pad, width - pad * 2, height - pad * 2,
++				2 * pad, 2 * pad, width - pad * 4, height - pad * 4);
++	if (ret)
++		return ret;
++
++	gc2145_tx_start(sensor);
++
++	// anti-flicker step
++	//gc2145_tx_write16(sensor, 0x125, 360); //XXX: get this from the calculator (hb related)
++
++	//XXX: calculate auto exposure settings, there are 4 slots that the HW
++	//uses and exposure settings are set in row_time units
++
++	rt = gc2145_sensor_params_get_row_period(&params);
++	ft = gc2145_sensor_params_get_frame_period(&params);
++	ft_rt = ft / rt / 4;
++
++	for (i = 0; i < 7; i++) {
++		// exposure settings for exposure levels
++		gc2145_tx_write16(sensor, 0x127 + 2 * i, ft_rt * (i + 1));
++		// max dg gains
++		gc2145_tx_write8(sensor, 0x135 + i, 0x50);
++	}
++
++	// max analog gain
++	gc2145_tx_write8(sensor, 0x11f, 0x50);
++	// max digital gain
++	gc2145_tx_write8(sensor, 0x120, 0xe0);
++
++	gc2145_tx_write8(sensor, GC2145_P0_ISP_OUT_FORMAT, pix_fmt->fmt_setup);
++
++	// set gamma curve
++	gc2145_tx_update_bits(sensor, 0x80, BIT(6), BIT(6));
++
++	// disable denoising
++	gc2145_tx_update_bits(sensor, 0x80, BIT(2), 0);
++
++	// drive strength
++	gc2145_tx_write8(sensor, 0x24,
++			 (pclk2 / (params.enable_scaler + 1)) > 40000000 ?
++				0xff : 0x55);
++
++	return gc2145_tx_commit(sensor);
++}
++
++static int gc2145_set_stream(struct gc2145_dev *sensor, int enable)
++{
++	gc2145_tx_start(sensor);
++
++	gc2145_tx_write8(sensor, GC2145_REG_PAD_IO, enable ? 0x0f : 0);
++
++	//XXX: maybe disable cam module function blocks that are not used
++	//and downclock the PLL/disable it when not streaming?
++
++	return gc2145_tx_commit(sensor);
++}
++
++static int gc2145_s_stream(struct v4l2_subdev *sd, int enable)
++{
++	struct gc2145_dev *sensor = to_gc2145_dev(sd);
++	int ret = 0;
++
++	mutex_lock(&sensor->lock);
++
++	if (sensor->streaming == !enable) {
++		if (enable && sensor->pending_mode_change) {
++			ret = gc2145_setup_mode(sensor);
++			if (ret)
++				goto out;
++		}
++
++		ret = gc2145_set_stream(sensor, enable);
++		if (ret)
++			goto out;
++
++		sensor->streaming = !!enable;
++	}
++
++out:
++	mutex_unlock(&sensor->lock);
++	return ret;
++}
++
++/* }}} */
++/* {{{ Pad ops */
++
++static int gc2145_get_frame_interval(struct v4l2_subdev *sd,
++				     struct v4l2_subdev_state *state,
++				     struct v4l2_subdev_frame_interval *fi)
++{
++	struct gc2145_dev *sensor = to_gc2145_dev(sd);
++
++	if (fi->pad != 0)
++		return -EINVAL;
++
++	mutex_lock(&sensor->lock);
++	fi->interval = sensor->frame_interval;
++	mutex_unlock(&sensor->lock);
++
++	return 0;
++}
++
++static int gc2145_set_frame_interval(struct v4l2_subdev *sd,
++				     struct v4l2_subdev_state *state,
++				     struct v4l2_subdev_frame_interval *fi)
++{
++	struct gc2145_dev *sensor = to_gc2145_dev(sd);
++	int ret = 0, fps;
++	struct gc2145_sensor_params params;
++	unsigned long pixel_rate;
++
++	if (fi->pad != 0)
++		return -EINVAL;
++
++	mutex_lock(&sensor->lock);
++
++	/* user requested infinite frame rate */
++	if (fi->interval.numerator == 0)
++		fps = 60;
++	else
++		fps = DIV_ROUND_CLOSEST(fi->interval.denominator,
++					fi->interval.numerator);
++
++	fps = clamp(fps, 1, 60);
++
++	sensor->frame_interval.numerator = 1;
++	sensor->frame_interval.denominator = fps;
++	fi->interval = sensor->frame_interval;
++
++	params = gc2145_get_sensor_params(fps, sensor->fmt.width, sensor->fmt.height, &pixel_rate);
++	__v4l2_ctrl_s_ctrl_int64(sensor->ctrls.pixel_rate,
++				 pixel_rate);
++
++#if 0
++	if (sensor->streaming) {
++		ret = gc2145_write16(sensor, GC2145_REG_DESIRED_FRAME_RATE_NUM,
++				     fps);
++		if (ret)
++			goto err_unlock;
++	}
++err_unlock:
++#endif
++
++	mutex_unlock(&sensor->lock);
++	return ret;
++}
++
++static int gc2145_enum_mbus_code(struct v4l2_subdev *sd,
++				 struct v4l2_subdev_state *sd_state,
++				 struct v4l2_subdev_mbus_code_enum *code)
++{
++	if (code->pad != 0 || code->index >= ARRAY_SIZE(gc2145_formats))
++		return -EINVAL;
++
++	code->code = gc2145_formats[code->index].code;
++
++	return 0;
++}
++
++static int gc2145_enum_frame_size(struct v4l2_subdev *sd,
++				  struct v4l2_subdev_state *sd_state,
++				  struct v4l2_subdev_frame_size_enum *fse)
++{
++	if (fse->pad != 0 || fse->index > 0)
++		return -EINVAL;
++
++	fse->min_width = GC2145_SENSOR_WIDTH_MIN;
++	fse->max_width = GC2145_SENSOR_WIDTH_MAX;
++
++	fse->min_height = GC2145_SENSOR_HEIGHT_MIN;
++	fse->max_height = GC2145_SENSOR_HEIGHT_MAX;
++
++	return 0;
++}
++
++static int gc2145_enum_frame_interval(
++	struct v4l2_subdev *sd,
++	struct v4l2_subdev_state *sd_state,
++	struct v4l2_subdev_frame_interval_enum *fie)
++{
++	if (fie->pad != 0 || fie->index > 0)
++		return -EINVAL;
++
++	fie->interval.numerator = 1;
++	fie->interval.denominator = 30;
++
++	return 0;
++}
++
++static int gc2145_get_fmt(struct v4l2_subdev *sd,
++			  struct v4l2_subdev_state *sd_state,
++			  struct v4l2_subdev_format *format)
++{
++	struct gc2145_dev *sensor = to_gc2145_dev(sd);
++	struct v4l2_mbus_framefmt *mf;
++
++	if (format->pad != 0)
++		return -EINVAL;
++
++	if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
++		mf = v4l2_subdev_state_get_format(sd_state, format->pad);
++		format->format = *mf;
++		return 0;
++	}
++
++	mutex_lock(&sensor->lock);
++	format->format = sensor->fmt;
++	mutex_unlock(&sensor->lock);
++
++	return 0;
++}
++
++static int gc2145_set_fmt(struct v4l2_subdev *sd,
++			  struct v4l2_subdev_state *sd_state,
++			  struct v4l2_subdev_format *format)
++{
++	struct gc2145_dev *sensor = to_gc2145_dev(sd);
++	struct v4l2_mbus_framefmt *mf = &format->format;
++	const struct gc2145_pixfmt *pixfmt;
++	int ret = 0;
++
++	if (format->pad != 0)
++		return -EINVAL;
++
++	/* check if we support requested mbus fmt */
++	pixfmt = gc2145_find_format(mf->code);
++	if (!pixfmt)
++		pixfmt = &gc2145_formats[0];
++
++	mf->code = pixfmt->code;
++	mf->colorspace = pixfmt->colorspace;
++	mf->xfer_func = V4L2_XFER_FUNC_DEFAULT;
++	mf->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
++	mf->quantization = V4L2_QUANTIZATION_DEFAULT;
++	mf->field = V4L2_FIELD_NONE;
++
++	mutex_lock(&sensor->lock);
++
++	mf->width = clamp(mf->width, GC2145_SENSOR_WIDTH_MIN,
++		      GC2145_SENSOR_WIDTH_MAX);
++	mf->height = clamp(mf->height, GC2145_SENSOR_HEIGHT_MIN,
++		       GC2145_SENSOR_HEIGHT_MAX);
++
++	if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
++		struct v4l2_mbus_framefmt *try_mf;
++
++		try_mf = v4l2_subdev_state_get_format(sd_state, format->pad);
++		*try_mf = *mf;
++		goto out;
++	}
++
++	if (sensor->streaming) {
++		ret = -EBUSY;
++		goto out;
++	}
++
++	sensor->fmt = *mf;
++	sensor->pending_mode_change = true;
++out:
++	mutex_unlock(&sensor->lock);
++	return ret;
++}
++
++/* }}} */
++/* {{{ Core Ops */
++
++static int gc2145_configure(struct gc2145_dev *sensor)
++{
++	struct v4l2_mbus_config_parallel *bus = &sensor->ep.bus.parallel;
++	u8 sync_mode = 0;
++	u16 chip_id;
++	int ret;
++
++	ret = gc2145_read16(sensor, GC2145_REG_CHIP_ID, &chip_id);
++	if (ret)
++		return ret;
++
++	dev_info(&sensor->i2c_client->dev, "device id: 0x%04x\n",
++		 (unsigned int)chip_id);
++
++	if (chip_id != GC2145_REG_CHIP_ID_VALUE) {
++		dev_err(&sensor->i2c_client->dev,
++			"unsupported device id: 0x%04x\n",
++			(unsigned int)chip_id);
++		return -EINVAL;
++	}
++
++        // setup parallel bus
++
++	if (bus->flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
++		sync_mode |= 0x01;
++
++	if (bus->flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
++		sync_mode |= 0x02;
++
++	if (bus->flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
++		sync_mode |= 0x04;
++
++	gc2145_tx_start(sensor);
++
++	// soft reset
++	gc2145_tx_write8(sensor, GC2145_REG_RESET, 0xf0);
++
++	// enable analog/digital parts
++	gc2145_tx_write8(sensor, GC2145_REG_ANALOG_PWC, 0x06);
++
++	// safe initial PLL setting
++	gc2145_tx_write8(sensor, GC2145_REG_PLL_MODE1, 0x1d);
++	gc2145_tx_write8(sensor, GC2145_REG_PLL_MODE2, 0x84);
++	gc2145_tx_write8(sensor, GC2145_REG_CLK_DIV_MODE, 0x00);
++
++	gc2145_tx_write8(sensor, GC2145_REG_CM_MODE, 0xfe);
++
++	// disable pads
++	gc2145_tx_write8(sensor, GC2145_REG_PAD_IO, 0);
++
++	gc2145_tx_write8(sensor, 0x19, 0x0c); // set AD pipe number
++	gc2145_tx_write8(sensor, 0x20, 0x01); // AD clk mode
++
++	// enable defect correction, etc.
++	gc2145_tx_write8(sensor, 0x80, 0x0b);
++
++	gc2145_tx_write8(sensor, GC2145_P0_SYNC_MODE, sync_mode);
++
++	ret = gc2145_tx_commit(sensor);
++	if (ret)
++		return ret;
++
++	// load default register values from the firmware file
++	ret = gc2145_load_firmware(sensor, GC2145_FIRMWARE_PARAMETERS);
++	if (ret < 0)
++		return ret;
++
++	return 0;
++}
++
++static int gc2145_set_power(struct gc2145_dev *sensor, bool on)
++{
++	int ret = 0;
++
++	if (on) {
++		ret = regulator_bulk_enable(GC2145_NUM_SUPPLIES,
++					    sensor->supplies);
++		if (ret)
++			return ret;
++
++		ret = clk_set_rate(sensor->xclk, 24000000);
++		if (ret)
++			goto xclk_off;
++
++		ret = clk_prepare_enable(sensor->xclk);
++		if (ret)
++			goto power_off;
++
++		usleep_range(10000, 12000);
++		gpiod_direction_output(sensor->reset_gpio, 1);
++		usleep_range(10000, 12000);
++		gpiod_direction_output(sensor->enable_gpio, 1);
++		usleep_range(10000, 12000);
++		gpiod_direction_output(sensor->reset_gpio, 0);
++		usleep_range(40000, 50000);
++
++		ret = gc2145_configure(sensor);
++		if (ret)
++			goto xclk_off;
++
++		ret = gc2145_setup_mode(sensor);
++		if (ret)
++			goto xclk_off;
++
++		return 0;
++	}
++
++xclk_off:
++	clk_disable_unprepare(sensor->xclk);
++power_off:
++	gpiod_direction_input(sensor->reset_gpio);
++	gpiod_direction_input(sensor->enable_gpio);
++	regulator_bulk_disable(GC2145_NUM_SUPPLIES, sensor->supplies);
++	msleep(100);
++	return ret;
++}
++
++static int gc2145_s_power(struct v4l2_subdev *sd, int on)
++{
++	struct gc2145_dev *sensor = to_gc2145_dev(sd);
++	bool power_up, power_down;
++	int ret = 0;
++
++	mutex_lock(&sensor->lock);
++
++	power_up = on && !sensor->powered;
++	power_down = !on && sensor->powered;
++
++	if (power_up || power_down) {
++		ret = gc2145_set_power(sensor, power_up);
++		if (!ret)
++			sensor->powered = on;
++	}
++
++	mutex_unlock(&sensor->lock);
++
++	if (!ret && power_up) {
++		/* restore controls */
++		ret = v4l2_ctrl_handler_setup(&sensor->ctrls.handler);
++		if (ret)
++			gc2145_s_power(sd, 0);
++	}
++
++	return ret;
++}
++
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++static int gc2145_g_register(struct v4l2_subdev *sd,
++			     struct v4l2_dbg_register *reg)
++{
++	struct gc2145_dev *sensor = to_gc2145_dev(sd);
++	int ret;
++	u8 val = 0;
++
++	if (reg->reg > 0xffff)
++		return -EINVAL;
++
++	reg->size = 1;
++
++	mutex_lock(&sensor->lock);
++	ret = gc2145_read(sensor, reg->reg, &val);
++	mutex_unlock(&sensor->lock);
++	if (ret)
++		return -EIO;
++
++	reg->val = val;
++	return 0;
++}
++
++static int gc2145_s_register(struct v4l2_subdev *sd,
++			     const struct v4l2_dbg_register *reg)
++{
++	struct gc2145_dev *sensor = to_gc2145_dev(sd);
++	int ret;
++
++	if (reg->reg > 0xffff || reg->val > 0xff)
++		return -EINVAL;
++
++	mutex_lock(&sensor->lock);
++	ret = gc2145_write(sensor, reg->reg, reg->val);
++	mutex_unlock(&sensor->lock);
++
++	return ret;
++}
++#endif
++
++/* }}} */
++
++static const struct v4l2_subdev_core_ops gc2145_core_ops = {
++	.s_power = gc2145_s_power,
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++	.g_register = gc2145_g_register,
++	.s_register = gc2145_s_register,
++#endif
++};
++
++static const struct v4l2_subdev_pad_ops gc2145_pad_ops = {
++	.enum_mbus_code = gc2145_enum_mbus_code,
++	.enum_frame_size = gc2145_enum_frame_size,
++	.enum_frame_interval = gc2145_enum_frame_interval,
++	.get_fmt = gc2145_get_fmt,
++	.set_fmt = gc2145_set_fmt,
++	.get_frame_interval = gc2145_get_frame_interval,
++	.set_frame_interval = gc2145_set_frame_interval,
++};
++
++static const struct v4l2_subdev_video_ops gc2145_video_ops = {
++	.s_stream = gc2145_s_stream,
++};
++
++static const struct v4l2_subdev_ops gc2145_subdev_ops = {
++	.core = &gc2145_core_ops,
++	.pad = &gc2145_pad_ops,
++	.video = &gc2145_video_ops,
++};
++
++static int gc2145_get_regulators(struct gc2145_dev *sensor)
++{
++	int i;
++
++	for (i = 0; i < GC2145_NUM_SUPPLIES; i++)
++		sensor->supplies[i].supply = gc2145_supply_name[i];
++
++	return devm_regulator_bulk_get(&sensor->i2c_client->dev,
++				       GC2145_NUM_SUPPLIES,
++				       sensor->supplies);
++}
++
++static int gc2145_probe(struct i2c_client *client)
++{
++	struct device *dev = &client->dev;
++	struct fwnode_handle *endpoint;
++	struct gc2145_dev *sensor;
++	int ret;
++
++	sensor = devm_kzalloc(dev, sizeof(*sensor), GFP_KERNEL);
++	if (!sensor)
++		return -ENOMEM;
++
++	sensor->i2c_client = client;
++
++	sensor->fmt.code = gc2145_formats[0].code;
++	sensor->fmt.width = 1600;
++	sensor->fmt.height = 1200;
++	sensor->fmt.field = V4L2_FIELD_NONE;
++	sensor->frame_interval.numerator = 1;
++	sensor->frame_interval.denominator = 10;
++	sensor->pending_mode_change = true;
++	sensor->current_bank = 0xff;
++
++	endpoint = fwnode_graph_get_next_endpoint(
++		of_fwnode_handle(client->dev.of_node), NULL);
++	if (!endpoint) {
++		dev_err(dev, "endpoint node not found\n");
++		return -EINVAL;
++	}
++
++	ret = v4l2_fwnode_endpoint_parse(endpoint, &sensor->ep);
++	fwnode_handle_put(endpoint);
++	if (ret) {
++		dev_err(dev, "could not parse endpoint\n");
++		return ret;
++	}
++
++	if (sensor->ep.bus_type != V4L2_MBUS_PARALLEL) {
++		dev_err(dev, "unsupported bus type %d\n", sensor->ep.bus_type);
++		return -EINVAL;
++	}
++
++	sensor->xclk = devm_clk_get(dev, "xclk");
++	if (IS_ERR(sensor->xclk)) {
++		dev_err(dev, "failed to get xclk\n");
++		return PTR_ERR(sensor->xclk);
++	}
++
++	sensor->enable_gpio = devm_gpiod_get_optional(dev, "enable", GPIOD_IN);
++	if (IS_ERR(sensor->enable_gpio)) {
++		dev_err(dev, "failed to get enable gpio\n");
++		return PTR_ERR(sensor->enable_gpio);
++	}
++
++	sensor->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_IN);
++	if (IS_ERR(sensor->reset_gpio)) {
++		dev_err(dev, "failed to get reset gpio\n");
++		return PTR_ERR(sensor->reset_gpio);
++	}
++
++	if (!sensor->enable_gpio || !sensor->reset_gpio) {
++		dev_err(dev, "enable and reset pins must be configured\n");
++		return ret;
++	}
++
++	v4l2_i2c_subdev_init(&sensor->sd, client, &gc2145_subdev_ops);
++
++	sensor->sd.flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
++	sensor->pad.flags = MEDIA_PAD_FL_SOURCE;
++	sensor->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
++	ret = media_entity_pads_init(&sensor->sd.entity, 1, &sensor->pad);
++	if (ret)
++		return ret;
++
++	mutex_init(&sensor->lock);
++
++	ret = gc2145_get_regulators(sensor);
++	if (ret)
++		goto entity_cleanup;
++
++	ret = gc2145_init_controls(sensor);
++	if (ret)
++		goto entity_cleanup;
++
++	ret = v4l2_async_register_subdev(&sensor->sd);
++	if (ret)
++		goto free_ctrls;
++
++	return 0;
++
++free_ctrls:
++	v4l2_ctrl_handler_free(&sensor->ctrls.handler);
++entity_cleanup:
++	mutex_destroy(&sensor->lock);
++	media_entity_cleanup(&sensor->sd.entity);
++	return ret;
++}
++
++static void gc2145_remove(struct i2c_client *client)
++{
++	struct v4l2_subdev *sd = i2c_get_clientdata(client);
++	struct gc2145_dev *sensor = to_gc2145_dev(sd);
++
++	v4l2_async_unregister_subdev(&sensor->sd);
++	mutex_destroy(&sensor->lock);
++	media_entity_cleanup(&sensor->sd.entity);
++	v4l2_ctrl_handler_free(&sensor->ctrls.handler);
++}
++
++static const struct i2c_device_id gc2145_id[] = {
++	{"gc2145", 0},
++	{},
++};
++MODULE_DEVICE_TABLE(i2c, gc2145_id);
++
++static const struct of_device_id gc2145_dt_ids[] = {
++	{ .compatible = "galaxycore,gc2145" },
++	{ /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, gc2145_dt_ids);
++
++static struct i2c_driver gc2145_i2c_driver = {
++	.driver = {
++		.name  = "gc2145",
++		.of_match_table	= gc2145_dt_ids,
++	},
++	.id_table = gc2145_id,
++	.probe    = gc2145_probe,
++	.remove   = gc2145_remove,
++};
++
++module_i2c_driver(gc2145_i2c_driver);
++
++MODULE_AUTHOR("Ondrej Jirman <megi@xff.cz>");
++MODULE_DESCRIPTION("GC2145 Camera Subdev Driver");
++MODULE_LICENSE("GPL");
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/media-gc2145-fix-white-balance-colors.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/media-gc2145-fix-white-balance-colors.patch
new file mode 100644
index 000000000000..4249b7883c95
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/media-gc2145-fix-white-balance-colors.patch
@@ -0,0 +1,183 @@
+From 7499b88dc111f8367eb0f8a807e4603627ee2e4e Mon Sep 17 00:00:00 2001
+From: Andrey Skvortsov <andrej.skvortzov@gmail.com>
+Date: Sat, 26 Aug 2023 12:10:49 +0300
+Subject: media: gc2145: fix white-balance colors
+
+awb initialization settings were taken from gc2145.c driver developed
+by STMicroelectronics with a help of Galaxycore. Most of these
+registers are not documented in a publicly available gc2145
+documentation.
+
+Don't reset white balance gains, exposure and gains on every stream
+start. That keeps old values set by AWB/AEC previously and makes
+AWB/AEC algorithms achieve correct settings on stream restart faster.
+
+For Megapixels DCP calibration file for front camera has to be removed
+to get good quality pictures.
+```
+rm /usr/share/megapixels/config/pine64,pinephone,front.dcp
+```
+
+Signed-off-by: Andrey Skvortsov <andrej.skvortzov@gmail.com>
+---
+ drivers/media/i2c/gc2145.c | 118 ++++++++++++++++++++++++++++++-------
+ 1 file changed, 97 insertions(+), 21 deletions(-)
+
+diff --git a/drivers/media/i2c/gc2145.c b/drivers/media/i2c/gc2145.c
+index 429d86bf5f01..b505b3f07387 100644
+--- a/drivers/media/i2c/gc2145.c
++++ b/drivers/media/i2c/gc2145.c
+@@ -1,6 +1,7 @@
+ /*
+  * Galaxycore GC2145 driver.
+  * Copyright (C) 2018 Ondřej Jirman <megi@xff.cz>.
++ * Copyright (C) 2022, STMicroelectronics SA
+  *
+  * This program is free software; you can redistribute it and/or modify
+  * it under the terms of the GNU General Public License as published by
+@@ -1556,34 +1557,114 @@ static int gc2145_set_2pclk(struct gc2145_dev *sensor,
+ 	return gc2145_tx_commit(sensor);
+ }
+ 
++struct gc2145_reg {
++	unsigned char address;
++	unsigned char val;
++};
++
++static const struct gc2145_reg gc2145_awb_regs[] = {
++	{0xfe, 0x01},
++	{0x4f, 0x00}, {0x4f, 0x00}, {0x4b, 0x01}, {0x4f, 0x00},
++	{0x4c, 0x01}, {0x4d, 0x71}, {0x4e, 0x01},
++	{0x4c, 0x01}, {0x4d, 0x91}, {0x4e, 0x01},
++	{0x4c, 0x01}, {0x4d, 0x70}, {0x4e, 0x01},
++	{0x4c, 0x01}, {0x4d, 0x90}, {0x4e, 0x02},
++	{0x4c, 0x01}, {0x4d, 0xb0}, {0x4e, 0x02},
++	{0x4c, 0x01}, {0x4d, 0x8f}, {0x4e, 0x02},
++	{0x4c, 0x01}, {0x4d, 0x6f}, {0x4e, 0x02},
++	{0x4c, 0x01}, {0x4d, 0xaf}, {0x4e, 0x02},
++	{0x4c, 0x01}, {0x4d, 0xd0}, {0x4e, 0x02},
++	{0x4c, 0x01}, {0x4d, 0xf0}, {0x4e, 0x02},
++	{0x4c, 0x01}, {0x4d, 0xcf}, {0x4e, 0x02},
++	{0x4c, 0x01}, {0x4d, 0xef}, {0x4e, 0x02},
++	{0x4c, 0x01}, {0x4d, 0x6e}, {0x4e, 0x03},
++	{0x4c, 0x01}, {0x4d, 0x8e}, {0x4e, 0x03},
++	{0x4c, 0x01}, {0x4d, 0xae}, {0x4e, 0x03},
++	{0x4c, 0x01}, {0x4d, 0xce}, {0x4e, 0x03},
++	{0x4c, 0x01}, {0x4d, 0x4d}, {0x4e, 0x03},
++	{0x4c, 0x01}, {0x4d, 0x6d}, {0x4e, 0x03},
++	{0x4c, 0x01}, {0x4d, 0x8d}, {0x4e, 0x03},
++	{0x4c, 0x01}, {0x4d, 0xad}, {0x4e, 0x03},
++	{0x4c, 0x01}, {0x4d, 0xcd}, {0x4e, 0x03},
++	{0x4c, 0x01}, {0x4d, 0x4c}, {0x4e, 0x03},
++	{0x4c, 0x01}, {0x4d, 0x6c}, {0x4e, 0x03},
++	{0x4c, 0x01}, {0x4d, 0x8c}, {0x4e, 0x03},
++	{0x4c, 0x01}, {0x4d, 0xac}, {0x4e, 0x03},
++	{0x4c, 0x01}, {0x4d, 0xcc}, {0x4e, 0x03},
++	{0x4c, 0x01}, {0x4d, 0xcb}, {0x4e, 0x03},
++	{0x4c, 0x01}, {0x4d, 0x4b}, {0x4e, 0x03},
++	{0x4c, 0x01}, {0x4d, 0x6b}, {0x4e, 0x03},
++	{0x4c, 0x01}, {0x4d, 0x8b}, {0x4e, 0x03},
++	{0x4c, 0x01}, {0x4d, 0xab}, {0x4e, 0x03},
++	{0x4c, 0x01}, {0x4d, 0x8a}, {0x4e, 0x04},
++	{0x4c, 0x01}, {0x4d, 0xaa}, {0x4e, 0x04},
++	{0x4c, 0x01}, {0x4d, 0xca}, {0x4e, 0x04},
++	{0x4c, 0x01}, {0x4d, 0xca}, {0x4e, 0x04},
++	{0x4c, 0x01}, {0x4d, 0xc9}, {0x4e, 0x04},
++	{0x4c, 0x01}, {0x4d, 0x8a}, {0x4e, 0x04},
++	{0x4c, 0x01}, {0x4d, 0x89}, {0x4e, 0x04},
++	{0x4c, 0x01}, {0x4d, 0xa9}, {0x4e, 0x04},
++	{0x4c, 0x02}, {0x4d, 0x0b}, {0x4e, 0x05},
++	{0x4c, 0x02}, {0x4d, 0x0a}, {0x4e, 0x05},
++	{0x4c, 0x01}, {0x4d, 0xeb}, {0x4e, 0x05},
++	{0x4c, 0x01}, {0x4d, 0xea}, {0x4e, 0x05},
++	{0x4c, 0x02}, {0x4d, 0x09}, {0x4e, 0x05},
++	{0x4c, 0x02}, {0x4d, 0x29}, {0x4e, 0x05},
++	{0x4c, 0x02}, {0x4d, 0x2a}, {0x4e, 0x05},
++	{0x4c, 0x02}, {0x4d, 0x4a}, {0x4e, 0x05},
++	{0x4c, 0x02}, {0x4d, 0x8a}, {0x4e, 0x06},
++	{0x4c, 0x02}, {0x4d, 0x49}, {0x4e, 0x06},
++	{0x4c, 0x02}, {0x4d, 0x69}, {0x4e, 0x06},
++	{0x4c, 0x02}, {0x4d, 0x89}, {0x4e, 0x06},
++	{0x4c, 0x02}, {0x4d, 0xa9}, {0x4e, 0x06},
++	{0x4c, 0x02}, {0x4d, 0x48}, {0x4e, 0x06},
++	{0x4c, 0x02}, {0x4d, 0x68}, {0x4e, 0x06},
++	{0x4c, 0x02}, {0x4d, 0x69}, {0x4e, 0x06},
++	{0x4c, 0x02}, {0x4d, 0xca}, {0x4e, 0x07},
++	{0x4c, 0x02}, {0x4d, 0xc9}, {0x4e, 0x07},
++	{0x4c, 0x02}, {0x4d, 0xe9}, {0x4e, 0x07},
++	{0x4c, 0x03}, {0x4d, 0x09}, {0x4e, 0x07},
++	{0x4c, 0x02}, {0x4d, 0xc8}, {0x4e, 0x07},
++	{0x4c, 0x02}, {0x4d, 0xe8}, {0x4e, 0x07},
++	{0x4c, 0x02}, {0x4d, 0xa7}, {0x4e, 0x07},
++	{0x4c, 0x02}, {0x4d, 0xc7}, {0x4e, 0x07},
++	{0x4c, 0x02}, {0x4d, 0xe7}, {0x4e, 0x07},
++	{0x4c, 0x03}, {0x4d, 0x07}, {0x4e, 0x07},
++	{0x4f, 0x01},
++	{0x50, 0x80}, {0x51, 0xa8}, {0x52, 0x47}, {0x53, 0x38},
++	{0x54, 0xc7}, {0x56, 0x0e}, {0x58, 0x08}, {0x5b, 0x00},
++	{0x5c, 0x74}, {0x5d, 0x8b}, {0x61, 0xdb}, {0x62, 0xb8},
++	{0x63, 0x86}, {0x64, 0xc0}, {0x65, 0x04}, {0x67, 0xa8},
++	{0x68, 0xb0}, {0x69, 0x00}, {0x6a, 0xa8}, {0x6b, 0xb0},
++	{0x6c, 0xaf}, {0x6d, 0x8b}, {0x6e, 0x50}, {0x6f, 0x18},
++	{0x73, 0xf0}, {0x70, 0x0d}, {0x71, 0x60}, {0x72, 0x80},
++	{0x74, 0x01}, {0x75, 0x01}, {0x7f, 0x0c}, {0x76, 0x70},
++	{0x77, 0x58}, {0x78, 0xa0}, {0x79, 0x5e}, {0x7a, 0x54},
++	{0x7b, 0x58},
++	{0xfe, 0x00},
++};
++
+ static int gc2145_setup_awb(struct gc2145_dev *sensor,
+ 			     u16 x1, u16 y1, u16 x2, u16 y2)
+ {
+ 	int ratio = 8; //XXX: manual for gc2035 FAE says 4
+ 
+-	gc2145_tx_start(sensor);
+-
+ 	// disable awb
+-	gc2145_tx_update_bits(sensor, 0x82, BIT(1), 0);
++	gc2145_update_bits(sensor, 0x82, BIT(1), 0);
+ 
+-	// reset white balance RGB gains
+-	gc2145_tx_write8(sensor, 0xb3, 0x40);
+-	gc2145_tx_write8(sensor, 0xb4, 0x40);
+-	gc2145_tx_write8(sensor, 0xb5, 0x40);
++	// load awb settings
++	gc2145_set_registers(sensor, (void*)gc2145_awb_regs, sizeof(gc2145_awb_regs));
+ 
+ 	// awb window
+-	gc2145_tx_write8(sensor, 0x1ec, x1 / ratio);
+-	gc2145_tx_write8(sensor, 0x1ed, y1 / ratio);
+-	gc2145_tx_write8(sensor, 0x1ee, x2 / ratio);
+-	gc2145_tx_write8(sensor, 0x1ef, y2 / ratio);
++	gc2145_write(sensor, 0x1ec, x1 / ratio);
++	gc2145_write(sensor, 0x1ed, y1 / ratio);
++	gc2145_write(sensor, 0x1ee, x2 / ratio);
++	gc2145_write(sensor, 0x1ef, y2 / ratio);
+ 
+ 	// eanble awb
+-	gc2145_tx_update_bits(sensor, 0x82, BIT(1), BIT(1));
+-
+-	//1051  { 0xfe, 0x01 },
+-	//1052  { 0x74, 0x01 },
++	gc2145_update_bits(sensor, 0x82, BIT(1), BIT(1));
+ 
+-	return gc2145_tx_commit(sensor);
++	return 0;
+ }
+ 
+ static int gc2145_setup_aec(struct gc2145_dev *sensor,
+@@ -1599,11 +1680,6 @@ static int gc2145_setup_aec(struct gc2145_dev *sensor,
+ 	// disable AEC
+ 	gc2145_tx_write8(sensor, 0xb6, 0);
+ 
+-	// set reasonable initial exposure and gains
+-	gc2145_tx_write16(sensor, 0x03, 1200);
+-	gc2145_tx_write8(sensor, 0xb1, 0x20);
+-	gc2145_tx_write8(sensor, 0xb2, 0xe0);
+-
+ 	// setup measure window
+ 	gc2145_tx_write8(sensor, 0x101, x1 / x_ratio);
+ 	gc2145_tx_write8(sensor, 0x102, x2 / x_ratio);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/media-gc2145-implement-system-suspend.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/media-gc2145-implement-system-suspend.patch
new file mode 100644
index 000000000000..c3396c66bf4f
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/media-gc2145-implement-system-suspend.patch
@@ -0,0 +1,72 @@
+From db757ea5f058b665f3435c42810ff35838f4a28d Mon Sep 17 00:00:00 2001
+From: Andrey Skvortsov <andrej.skvortzov@gmail.com>
+Date: Mon, 14 Aug 2023 13:27:08 +0300
+Subject: media: gc2145: implement system suspend
+
+If system was suspended while camera sensor was used, data and
+interrupts were still coming from sensor and that caused unstable
+system. Sometimes system hanged during a resume.
+
+Signed-off-by: Andrey Skvortsov <andrej.skvortzov@gmail.com>
+---
+ drivers/media/i2c/gc2145.c | 37 +++++++++++++++++++++++++++++++++++++
+ 1 file changed, 37 insertions(+)
+
+diff --git a/drivers/media/i2c/gc2145.c b/drivers/media/i2c/gc2145.c
+index 749dce832aa0..429d86bf5f01 100644
+--- a/drivers/media/i2c/gc2145.c
++++ b/drivers/media/i2c/gc2145.c
+@@ -2275,6 +2275,42 @@ static void gc2145_remove(struct i2c_client *client)
+ 	v4l2_ctrl_handler_free(&sensor->ctrls.handler);
+ }
+ 
++static int gc2145_sensor_suspend(struct device *dev)
++{
++	struct v4l2_subdev *sd = dev_get_drvdata(dev);
++	struct gc2145_dev *sensor = to_gc2145_dev(sd);
++
++	mutex_lock(&sensor->lock);
++	if (sensor->streaming)
++		gc2145_set_stream(sensor, false);
++	mutex_unlock(&sensor->lock);
++
++	return 0;
++}
++
++static int gc2145_sensor_resume(struct device *dev)
++{
++	struct v4l2_subdev *sd = dev_get_drvdata(dev);
++	struct gc2145_dev *sensor = to_gc2145_dev(sd);
++	int ret = 0;
++
++	mutex_lock(&sensor->lock);
++	if (sensor->streaming) {
++		ret = gc2145_set_stream(sensor, true);
++		if (ret) {
++			gc2145_set_stream(sensor, false);
++			sensor->streaming = false;
++		}
++	}
++	mutex_unlock(&sensor->lock);
++
++	return ret;
++}
++
++static const struct dev_pm_ops gc2145_pm_ops = {
++	SET_SYSTEM_SLEEP_PM_OPS(gc2145_sensor_suspend, gc2145_sensor_resume)
++};
++
+ static const struct i2c_device_id gc2145_id[] = {
+ 	{"gc2145", 0},
+ 	{},
+@@ -2291,6 +2327,7 @@ static struct i2c_driver gc2145_i2c_driver = {
+ 	.driver = {
+ 		.name  = "gc2145",
+ 		.of_match_table	= gc2145_dt_ids,
++		.pm = &gc2145_pm_ops,
+ 	},
+ 	.id_table = gc2145_id,
+ 	.probe    = gc2145_probe,
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/media-hm5065-Add-subdev-driver-for-Himax-HM5065-camera-sensor.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/media-hm5065-Add-subdev-driver-for-Himax-HM5065-camera-sensor.patch
new file mode 100644
index 000000000000..9b7294ef167c
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/media-hm5065-Add-subdev-driver-for-Himax-HM5065-camera-sensor.patch
@@ -0,0 +1,2268 @@
+From b6f1f790b9f8dafcf115391cb36d80c8d7b75fb2 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 30 Sep 2017 02:39:48 +0200
+Subject: media: hm5065: Add subdev driver for Himax HM5065 camera sensor
+
+HM5065 is 5MP CMOS sensor. This driver implements support for
+V4L2_MBUS_PARALLEL bus type only. The driver  Other features:
+
+- External clock rates support from 6-27MHz (discrete values)
+- Resolution support from 2592x1944 to 88x72
+- Frame rates are available depending on the PCLK frequency
+  (from VGA@120 to 2592x1944@8)
+- Support for several YUV and RGB media bus formats
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/media/i2c/Kconfig  |   10 +
+ drivers/media/i2c/Makefile |    1 +
+ drivers/media/i2c/hm5065.c | 2207 ++++++++++++++++++++++++++++++++++++
+ 3 files changed, 2218 insertions(+)
+ create mode 100644 drivers/media/i2c/hm5065.c
+
+diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig
+index 8ba096b8ebca..e7da18f3da3c 100644
+--- a/drivers/media/i2c/Kconfig
++++ b/drivers/media/i2c/Kconfig
+@@ -701,6 +701,16 @@ config VIDEO_VGXY61
+ source "drivers/media/i2c/ccs/Kconfig"
+ source "drivers/media/i2c/et8ek8/Kconfig"
+ 
++config VIDEO_HM5065
++	tristate "Himax HM5065 sensor support"
++	depends on I2C
++	select V4L2_FWNODE
++	select VIDEO_V4L2_SUBDEV_API
++	select MEDIA_CONTROLLER
++	help
++	  This is a V4L2 sensor-level driver for Himax HM5065
++	  5 Mpixel camera.
++
+ endif
+ 
+ menu "Camera ISPs"
+diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile
+index fbb988bd067a..b429d9f2e982 100644
+--- a/drivers/media/i2c/Makefile
++++ b/drivers/media/i2c/Makefile
+@@ -157,3 +157,4 @@ obj-$(CONFIG_VIDEO_VP27SMPX) += vp27smpx.o
+ obj-$(CONFIG_VIDEO_VPX3220) += vpx3220.o
+ obj-$(CONFIG_VIDEO_WM8739) += wm8739.o
+ obj-$(CONFIG_VIDEO_WM8775) += wm8775.o
++obj-$(CONFIG_VIDEO_HM5065)	+= hm5065.o
+diff --git a/drivers/media/i2c/hm5065.c b/drivers/media/i2c/hm5065.c
+new file mode 100644
+index 000000000000..a3500a4c1441
+--- /dev/null
++++ b/drivers/media/i2c/hm5065.c
+@@ -0,0 +1,2207 @@
++/*
++ * Himax HM5065 driver.
++ * Copyright (C) 2017-2019 Ondřej Jirman <megi@xff.cz>.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#include <asm/div64.h>
++#include <linux/clk.h>
++#include <linux/clk-provider.h>
++#include <linux/clkdev.h>
++#include <linux/ctype.h>
++#include <linux/delay.h>
++#include <linux/device.h>
++#include <linux/firmware.h>
++#include <linux/i2c.h>
++#include <linux/init.h>
++#include <linux/module.h>
++#include <linux/of_device.h>
++#include <linux/slab.h>
++#include <linux/types.h>
++#include <linux/gpio/consumer.h>
++#include <linux/regulator/consumer.h>
++#include <media/v4l2-async.h>
++#include <media/v4l2-ctrls.h>
++#include <media/v4l2-device.h>
++#include <media/v4l2-fwnode.h>
++#include <media/v4l2-subdev.h>
++
++#define HM5065_AF_FIRMWARE		"hm5065-af.bin"
++#define HM5065_FIRMWARE_PARAMETERS	"hm5065-init.bin"
++
++#define HM5065_SENSOR_WIDTH	2592u
++#define HM5065_SENSOR_HEIGHT	1944u
++#define HM5065_CAPTURE_WIDTH_MIN	88u
++#define HM5065_CAPTURE_HEIGHT_MIN	72u
++
++/* {{{ Register definitions */
++
++/* registers are assumed to be u8 unless otherwise specified */
++
++/* device parameters */
++#define HM5065_REG_DEVICE_ID			0x0000 /* u16 */
++#define HM5065_REG_DEVICE_ID_VALUE		0x039e
++#define HM5065_REG_FIRMWARE_VSN			0x0002
++#define HM5065_REG_PATCH_VSN			0x0003
++#define HM5065_REG_EXCLOCKLUT			0x0009 /* standby */
++
++#define HM5065_REG_INT_EVENT_FLAG		0x000a
++#define HM5065_REG_INT_EVENT_FLAG_OP_MODE	BIT(0)
++#define HM5065_REG_INT_EVENT_FLAG_CAM_MODE	BIT(1)
++#define HM5065_REG_INT_EVENT_FLAG_JPEG_STATUS	BIT(2)
++#define HM5065_REG_INT_EVENT_FLAG_NUM_FRAMES	BIT(3)
++#define HM5065_REG_INT_EVENT_FLAG_AF_LOCKED	BIT(4)
++
++/* mode manager */
++#define HM5065_REG_USER_COMMAND			0x0010
++#define HM5065_REG_USER_COMMAND_STOP		0x00
++#define HM5065_REG_USER_COMMAND_RUN		0x01
++#define HM5065_REG_USER_COMMAND_POWEROFF	0x02
++
++#define HM5065_REG_STATE			0x0011
++#define HM5065_REG_STATE_RAW			0x10
++#define HM5065_REG_STATE_IDLE			0x20
++#define HM5065_REG_STATE_RUNNING		0x30
++
++#define HM5065_REG_ACTIVE_PIPE_SETUP_BANK	0x0012
++#define HM5065_REG_ACTIVE_PIPE_SETUP_BANK_0	0x00
++#define HM5065_REG_ACTIVE_PIPE_SETUP_BANK_1	0x01
++
++#define HM5065_REG_NUMBER_OF_FRAMES_STREAMED	0x0014 /* ro */
++#define HM5065_REG_REQUIRED_STREAM_LENGTH	0x0015
++
++#define HM5065_REG_CSI_ENABLE			0x0016 /* standby */
++#define HM5065_REG_CSI_ENABLE_DISABLE		0x00
++#define HM5065_REG_CSI_ENABLE_CSI2_1LANE	0x01
++#define HM5065_REG_CSI_ENABLE_CSI2_2LANE	0x02
++
++/* pipe setup bank 0 */
++#define HM5065_REG_P0_SENSOR_MODE		0x0040
++#define HM5065_REG_SENSOR_MODE_FULLSIZE		0x00
++#define HM5065_REG_SENSOR_MODE_BINNING_2X2	0x01
++#define HM5065_REG_SENSOR_MODE_BINNING_4X4	0x02
++#define HM5065_REG_SENSOR_MODE_SUBSAMPLING_2X2	0x03
++#define HM5065_REG_SENSOR_MODE_SUBSAMPLING_4X4	0x04
++
++#define HM5065_REG_P0_IMAGE_SIZE		0x0041
++#define HM5065_REG_IMAGE_SIZE_5MP		0x00
++#define HM5065_REG_IMAGE_SIZE_UXGA		0x01
++#define HM5065_REG_IMAGE_SIZE_SXGA		0x02
++#define HM5065_REG_IMAGE_SIZE_SVGA		0x03
++#define HM5065_REG_IMAGE_SIZE_VGA		0x04
++#define HM5065_REG_IMAGE_SIZE_CIF		0x05
++#define HM5065_REG_IMAGE_SIZE_QVGA		0x06
++#define HM5065_REG_IMAGE_SIZE_QCIF		0x07
++#define HM5065_REG_IMAGE_SIZE_QQVGA		0x08
++#define HM5065_REG_IMAGE_SIZE_QQCIF		0x09
++#define HM5065_REG_IMAGE_SIZE_MANUAL		0x0a
++
++#define HM5065_REG_P0_MANUAL_HSIZE		0x0042 /* u16 */
++#define HM5065_REG_P0_MANUAL_VSIZE		0x0044 /* u16 */
++
++#define HM5065_REG_P0_DATA_FORMAT		0x0046
++#define HM5065_REG_DATA_FORMAT_YCBCR_JFIF       0x00
++#define HM5065_REG_DATA_FORMAT_YCBCR_REC601     0x01
++#define HM5065_REG_DATA_FORMAT_YCBCR_CUSTOM     0x02
++#define HM5065_REG_DATA_FORMAT_RGB_565          0x03
++#define HM5065_REG_DATA_FORMAT_RGB_565_CUSTOM   0x04
++#define HM5065_REG_DATA_FORMAT_RGB_444          0x05
++#define HM5065_REG_DATA_FORMAT_RGB_555          0x06
++#define HM5065_REG_DATA_FORMAT_RAW10ITU10       0x07
++#define HM5065_REG_DATA_FORMAT_RAW10ITU8        0x08
++#define HM5065_REG_DATA_FORMAT_JPEG             0x09
++
++#define HM5065_REG_P0_GAMMA_GAIN		0x0049 /* 0-31 */
++#define HM5065_REG_P0_GAMMA_INTERPOLATION	0x004a /* 0-16 */
++#define HM5065_REG_P0_PEAKING_GAIN		0x004c /* 0-63 */
++
++#define HM5065_REG_P0_JPEG_SQUEEZE_MODE		0x004d
++#define HM5065_REG_JPEG_SQUEEZE_MODE_USER	0x00
++#define HM5065_REG_JPEG_SQUEEZE_MODE_AUTO	0x01
++
++#define HM5065_REG_P0_JPEG_TARGET_FILE_SIZE	0x004e /* u16, kB */
++#define HM5065_REG_P0_JPEG_IMAGE_QUALITY	0x0050
++#define HM5065_REG_JPEG_IMAGE_QUALITY_HIGH	0x00
++#define HM5065_REG_JPEG_IMAGE_QUALITY_MEDIUM	0x01
++#define HM5065_REG_JPEG_IMAGE_QUALITY_LOW	0x02
++
++/* pipe setup bank 1 (only register indexes) */
++#define HM5065_REG_P1_SENSOR_MODE		0x0060
++#define HM5065_REG_P1_IMAGE_SIZE		0x0061
++#define HM5065_REG_P1_MANUAL_HSIZE		0x0062 /* u16 */
++#define HM5065_REG_P1_MANUAL_VSIZE		0x0064 /* u16 */
++#define HM5065_REG_P1_DATA_FORMAT		0x0066
++#define HM5065_REG_P1_GAMMA_GAIN		0x0069 /* 0-31 */
++#define HM5065_REG_P1_GAMMA_INTERPOLATION	0x006a /* 0-16 */
++#define HM5065_REG_P1_PEAKING_GAIN		0x006c /* 0-63 */
++#define HM5065_REG_P1_JPEG_SQUEEZE_MODE		0x006d
++#define HM5065_REG_P1_JPEG_TARGET_FILE_SIZE	0x006e /* u16, kB */
++#define HM5065_REG_P1_JPEG_IMAGE_QUALITY	0x0070
++
++/* pipe setup - common registers */
++#define HM5065_REG_CONTRAST			0x0080 /* 0-200 */
++#define HM5065_REG_COLOR_SATURATION		0x0081 /* 0-200 */
++#define HM5065_REG_BRIGHTNESS			0x0082 /* 0-200 */
++#define HM5065_REG_HORIZONTAL_MIRROR		0x0083 /* 0,1 */
++#define HM5065_REG_VERTICAL_FLIP		0x0084 /* 0,1 */
++
++#define HM5065_REG_YCRCB_ORDER			0x0085
++#define HM5065_REG_YCRCB_ORDER_CB_Y_CR_Y	0x00
++#define HM5065_REG_YCRCB_ORDER_CR_Y_CB_Y	0x01
++#define HM5065_REG_YCRCB_ORDER_Y_CB_Y_CR	0x02
++#define HM5065_REG_YCRCB_ORDER_Y_CR_Y_CB	0x03
++
++/* clock chain parameter inputs (floating point) */
++#define HM5065_REG_EXTERNAL_CLOCK_FREQ_MHZ	0x00b0 /* fp16, 6-27, standby */
++#define HM5065_REG_TARGET_PLL_OUTPUT	0x00b2 /* fp16, 450-1000, standby */
++
++/* static frame rate control */
++#define HM5065_REG_DESIRED_FRAME_RATE_NUM	0x00c8 /* u16 */
++#define HM5065_REG_DESIRED_FRAME_RATE_DEN	0x00ca
++
++/* static frame rate status */
++#define HM5065_REG_REQUESTED_FRAME_RATE_HZ	0x00d8 /* fp16 */
++#define HM5065_REG_MAX_FRAME_RATE_HZ		0x00da /* fp16 */
++#define HM5065_REG_MIN_FRAME_RATE_HZ		0x00dc /* fp16 */
++
++/* exposure controls */
++#define HM5065_REG_EXPOSURE_MODE			0x0128
++#define HM5065_REG_EXPOSURE_MODE_AUTO			0x00
++#define HM5065_REG_EXPOSURE_MODE_COMPILED_MANUAL	0x01
++#define HM5065_REG_EXPOSURE_MODE_DIRECT_MANUAL		0x02
++
++#define HM5065_REG_EXPOSURE_METERING		0x0129
++#define HM5065_REG_EXPOSURE_METERING_FLAT	0x00
++#define HM5065_REG_EXPOSURE_METERING_BACKLIT	0x01
++#define HM5065_REG_EXPOSURE_METERING_CENTERED	0x02
++
++#define HM5065_REG_MANUAL_EXPOSURE_TIME_NUM	0x012a
++#define HM5065_REG_MANUAL_EXPOSURE_TIME_DEN	0x012b
++#define HM5065_REG_MANUAL_EXPOSURE_TIME_US	0x012c /* fp16 */
++#define HM5065_REG_COLD_START_DESIRED_TIME_US	0x012e /* fp16, standby */
++#define HM5065_REG_EXPOSURE_COMPENSATION	0x0130 /* s8, -7 - +7 */
++
++#define HM5065_REG_DIRECT_MODE_COARSE_INTEGRATION_LINES	0x0132 /* u16 */
++#define HM5065_REG_DIRECT_MODE_FINE_INTEGRATION_PIXELS	0x0134 /* u16 */
++#define HM5065_REG_DIRECT_MODE_CODED_ANALOG_GAIN	0x0136 /* u16 */
++#define HM5065_REG_DIRECT_MODE_DIGITAL_GAIN		0x0138 /* fp16 */
++#define HM5065_REG_FREEZE_AUTO_EXPOSURE			0x0142 /* 0,1 */
++#define HM5065_REG_USER_MAXIMUM_INTEGRATION_TIME_US	0x0143 /* fp16 */
++#define HM5065_REG_ANTI_FLICKER_MODE			0x0148 /* 0,1 */
++
++/* exposure algorithm controls */
++#define HM5065_REG_DIGITAL_GAIN_FLOOR			0x015c /* fp16 */
++#define HM5065_REG_DIGITAL_GAIN_CEILING			0x015e /* fp16 */
++#define HM5065_REG_ANALOG_GAIN_FLOOR			0x02c0 /* u16 */
++#define HM5065_REG_ANALOG_GAIN_CEILING			0x02c2 /* u16 */
++
++/* exposure status */
++#define HM5065_REG_COARSE_INTEGRATION			0x017c /* u16 */
++#define HM5065_REG_FINE_INTEGRATION_PENDING_PIXELS	0x017e /* u16 */
++#define HM5065_REG_ANALOG_GAIN_PENDING			0x0180 /* fp16 */
++#define HM5065_REG_DIGITAL_GAIN_PENDING			0x0182 /* fp16 */
++#define HM5065_REG_DESIRED_EXPOSURE_TIME_US		0x0184 /* fp16 */
++#define HM5065_REG_COMPILED_EXPOSURE_TIME_US		0x0186 /* fp16 */
++#define HM5065_REG_USER_MAXIMUM_INTEGRATION_LINES	0x0189 /* u16 */
++#define HM5065_REG_TOTAL_INTEGRATION_TIME_PENDING_US	0x018b /* fp16 */
++#define HM5065_REG_CODED_ANALOG_GAIN_PENDING		0x018d /* u16 */
++
++/* flicker detect */
++#define HM5065_REG_FD_ENABLE_DETECT			0x0190 /* 0,1 */
++#define HM5065_REG_FD_DETECTION_START			0x0191 /* 0,1 */
++#define HM5065_REG_FD_MAX_NUMBER_ATTEMP	0x0192 /* 0-255, 0 = continuous */
++#define HM5065_REG_FD_FLICKER_IDENTIFICATION_THRESHOLD	0x0193 /* u16 */
++#define HM5065_REG_FD_WIN_TIMES				0x0195
++#define HM5065_REG_FD_FRAME_RATE_SHIFT_NUMBER		0x0196
++#define HM5065_REG_FD_MANUAL_FREF_ENABLE		0x0197 /* 0,1 */
++#define HM5065_REG_FD_MANU_FREF_100			0x0198 /* u16 */
++#define HM5065_REG_FD_MANU_FREF_120			0x019a /* u16 */
++#define HM5065_REG_FD_FLICKER_FREQUENCY			0x019c /* fp16 */
++
++/* white balance control */
++#define HM5065_REG_WB_MODE			0x01a0
++#define HM5065_REG_WB_MODE_OFF			0x00
++#define HM5065_REG_WB_MODE_AUTOMATIC		0x01
++#define HM5065_REG_WB_MODE_AUTO_INSTANT		0x02
++#define HM5065_REG_WB_MODE_MANUAL_RGB		0x03
++#define HM5065_REG_WB_MODE_CLOUDY_PRESET	0x04
++#define HM5065_REG_WB_MODE_SUNNY_PRESET		0x05
++#define HM5065_REG_WB_MODE_LED_PRESET		0x06
++#define HM5065_REG_WB_MODE_FLUORESCENT_PRESET	0x07
++#define HM5065_REG_WB_MODE_TUNGSTEN_PRESET	0x08
++#define HM5065_REG_WB_MODE_HORIZON_PRESET	0x09
++
++#define HM5065_REG_WB_MANUAL_RED_GAIN		0x01a1
++#define HM5065_REG_WB_MANUAL_GREEN_GAIN		0x01a2
++#define HM5065_REG_WB_MANUAL_BLUE_GAIN		0x01a3
++
++#define HM5065_REG_WB_MISC_SETTINGS		0x01a4
++#define HM5065_REG_WB_MISC_SETTINGS_FREEZE_ALGO	BIT(2)
++
++#define HM5065_REG_WB_HUE_R_BIAS		0x01a5 /* fp16 */
++#define HM5065_REG_WB_HUE_B_BIAS		0x01a7 /* fp16 */
++
++#define HM5065_REG_WB_STATUS			0x01c0
++#define HM5065_REG_WB_STATUS_STABLE		BIT(0)
++
++#define HM5065_REG_WB_NORM_RED_GAIN		0x01c8 /* fp16 */
++#define HM5065_REG_WB_PART_RED_GAIN		0x01e0 /* fp16 */
++#define HM5065_REG_WB_PART_GREEN_GAIN		0x01e2 /* fp16 */
++#define HM5065_REG_WB_PART_BLUE_GAIN		0x01e4 /* fp16 */
++
++/* image stability status */
++#define HM5065_REG_WHITE_BALANCE_STABLE		0x0291 /* 0,1 */
++#define HM5065_REG_EXPOSURE_STABLE		0x0292 /* 0,1 */
++#define HM5065_REG_STABLE			0x0294 /* 0,1 */
++
++/* special effects */
++#define HM5065_REG_EFFECTS_NEGATIVE		0x0380 /* 0,1 */
++#define HM5065_REG_EFFECTS_SOLARISING		0x0381 /* 0,1 */
++#define HM5065_REG_EFFECTS_SKECTH		0x0382 /* 0,1 */
++
++#define HM5065_REG_EFFECTS_COLOR		0x0384
++#define HM5065_REG_EFFECTS_COLOR_NORMAL         0x00
++#define HM5065_REG_EFFECTS_COLOR_RED_ONLY       0x01
++#define HM5065_REG_EFFECTS_COLOR_YELLOW_ONLY    0x02
++#define HM5065_REG_EFFECTS_COLOR_GREEN_ONLY     0x03
++#define HM5065_REG_EFFECTS_COLOR_BLUE_ONLY      0x04
++#define HM5065_REG_EFFECTS_COLOR_BLACK_WHITE    0x05
++#define HM5065_REG_EFFECTS_COLOR_SEPIA          0x06
++#define HM5065_REG_EFFECTS_COLOR_ANTIQUE        0x07
++#define HM5065_REG_EFFECTS_COLOR_AQUA           0x08
++#define HM5065_REG_EFFECTS_COLOR_MANUAL_MATRIX  0x09
++
++/* anti-vignete, otp flash (skipped), page 79-89 */
++
++/* flash control */
++#define HM5065_REG_FLASH_MODE		0x02d0 /* 0,1 */
++#define HM5065_REG_FLASH_RECOMMENDED	0x02d1 /* 0,1 */
++
++/* test pattern */
++#define HM5065_REG_ENABLE_TEST_PATTERN	0x05d8 /* 0,1 */
++
++#define HM5065_REG_TEST_PATTERN				0x05d9
++#define HM5065_REG_TEST_PATTERN_NONE			0x00
++#define HM5065_REG_TEST_PATTERN_HORIZONTAL_GREY_SCALE	0x01
++#define HM5065_REG_TEST_PATTERN_VERTICAL_GREY_SCALE	0x02
++#define HM5065_REG_TEST_PATTERN_DIAGONAL_GREY_SCALE	0x03
++#define HM5065_REG_TEST_PATTERN_PN28			0x04
++#define HM5065_REG_TEST_PATTERN_PN9			0x05
++#define HM5065_REG_TEST_PATTERN_SOLID_COLOR		0x06
++#define HM5065_REG_TEST_PATTERN_COLOR_BARS		0x07
++#define HM5065_REG_TEST_PATTERN_GRADUATED_COLOR_BARS	0x08
++
++#define HM5065_REG_TESTDATA_RED		0x4304 /* u16, 0-1023 */
++#define HM5065_REG_TESTDATA_GREEN_R	0x4308 /* u16, 0-1023 */
++#define HM5065_REG_TESTDATA_BLUE	0x430c /* u16, 0-1023 */
++#define HM5065_REG_TESTDATA_GREEN_B	0x4310 /* u16, 0-1023 */
++
++/* contrast stretch */
++#define HM5065_REG_CS_ENABLE			0x05e8 /* 0,1 */
++#define HM5065_REG_CS_GAIN_CEILING		0x05e9 /* fp16 */
++#define HM5065_REG_CS_BLACK_OFFSET_CEILING	0x05eb
++#define HM5065_REG_CS_WHITE_PIX_TARGET		0x05ec /* fp16 */
++#define HM5065_REG_CS_BLACK_PIX_TARGET		0x05ee /* fp16 */
++#define HM5065_REG_CS_ENABLED			0x05f8 /* 0,1 */
++#define HM5065_REG_CS_TOTAL_PIXEL		0x05f9 /* fp16 */
++#define HM5065_REG_CS_W_TARGET			0x05fb /* u32 */
++#define HM5065_REG_CS_B_TARGET			0x05ff /* u32 */
++#define HM5065_REG_CS_GAIN			0x0603 /* fp16 */
++#define HM5065_REG_CS_BLACK_OFFSET		0x0605
++#define HM5065_REG_CS_WHITE_LIMIT		0x0606
++
++/* preset controls */
++#define HM5065_REG_PRESET_LOADER_ENABLE		0x0638 /* 0,1, standby */
++
++#define HM5065_REG_INDIVIDUAL_PRESET		0x0639 /* standby */
++#define HM5065_REG_INDIVIDUAL_PRESET_ANTIVIGNETTE	BIT(0)
++#define HM5065_REG_INDIVIDUAL_PRESET_WHITE_BALANCE	BIT(1)
++#define HM5065_REG_INDIVIDUAL_PRESET_VCM		BIT(4)
++
++/* jpeg control parameters*/
++#define HM5065_REG_JPEG_STATUS			0x0649
++#define HM5065_REG_JPEG_RESTART			0x064a
++#define HM5065_REG_JPEG_HI_SQUEEZE_VALUE	0x064b /* 5-255 (5 = max q.) */
++#define HM5065_REG_JPEG_MED_SQUEEZE_VALUE	0x064c /* 5-255 */
++#define HM5065_REG_JPEG_LOW_SQUEEZE_VALUE	0x064d /* 5-255 */
++#define HM5065_REG_JPEG_LINE_LENGTH		0x064e /* u16, standby */
++#define HM5065_REG_JPEG_CLOCK_RATIO		0x0650 /* 1-8, standby */
++#define HM5065_REG_JPEG_THRES			0x0651 /* u16, standby */
++#define HM5065_REG_JPEG_BYTE_SENT		0x0653 /* u32 */
++
++/* autofocus */
++
++#define HM5065_REG_AF_WINDOWS_SYSTEM		0x065a
++#define HM5065_REG_AF_WINDOWS_SYSTEM_7_ZONES	0x00
++#define HM5065_REG_AF_WINDOWS_SYSTEM_1_ZONE	0x01
++
++#define HM5065_REG_AF_H_RATIO_NUM		0x065b
++#define HM5065_REG_AF_H_RATIO_DEN		0x065c
++#define HM5065_REG_AF_V_RATIO_NUM		0x065d
++#define HM5065_REG_AF_V_RATIO_DEN		0x065e
++
++#define HM5065_REG_AF_RANGE			0x0709
++#define HM5065_REG_AF_RANGE_FULL		0x00
++#define HM5065_REG_AF_RANGE_LANDSCAPE		0x01
++#define HM5065_REG_AF_RANGE_MACRO		0x02
++
++#define HM5065_REG_AF_MODE			0x070a
++#define HM5065_REG_AF_MODE_MANUAL		0x00
++#define HM5065_REG_AF_MODE_CONTINUOUS		0x01
++#define HM5065_REG_AF_MODE_SINGLE		0x03
++
++#define HM5065_REG_AF_MODE_STATUS		0x0720
++
++#define HM5065_REG_AF_COMMAND			0x070b
++#define HM5065_REG_AF_COMMAND_NULL		0x00
++#define HM5065_REG_AF_COMMAND_RELEASED_BUTTON	0x01
++#define HM5065_REG_AF_COMMAND_HALF_BUTTON	0x02
++#define HM5065_REG_AF_COMMAND_TAKE_SNAPSHOT	0x03
++#define HM5065_REG_AF_COMMAND_REFOCUS		0x04
++
++#define HM5065_REG_AF_LENS_COMMAND		0x070c
++#define HM5065_REG_AF_LENS_COMMAND_NULL				0x00
++#define HM5065_REG_AF_LENS_COMMAND_MOVE_STEP_TO_INFINITY	0x01
++#define HM5065_REG_AF_LENS_COMMAND_MOVE_STEP_TO_MACRO		0x02
++#define HM5065_REG_AF_LENS_COMMAND_GOTO_INFINITY		0x03
++#define HM5065_REG_AF_LENS_COMMAND_GOTO_MACRO			0x04
++#define HM5065_REG_AF_LENS_COMMAND_GOTO_RECOVERY		0x05
++#define HM5065_REG_AF_LENS_COMMAND_GOTO_TARGET_POSITION		0x07
++#define HM5065_REG_AF_LENS_COMMAND_GOTO_HYPERFOCAL		0x0C
++
++#define HM5065_REG_AF_MANUAL_STEP_SIZE		0x070d
++#define HM5065_REG_AF_FACE_LOCATION_CTRL_ENABLE	0x0714
++#define HM5065_REG_AF_FACE_LOCATION_CTRL_ENABLE_AF	BIT(0)
++#define HM5065_REG_AF_FACE_LOCATION_CTRL_ENABLE_AE	BIT(1)
++#define HM5065_REG_AF_FACE_LOCATION_CTRL_ENABLE_AWB	BIT(2)
++#define HM5065_REG_AF_FACE_LOCATION_X_START	0x0715 /* u16 */
++#define HM5065_REG_AF_FACE_LOCATION_X_SIZE	0x0717 /* u16 */
++#define HM5065_REG_AF_FACE_LOCATION_Y_START	0x0719 /* u16 */
++#define HM5065_REG_AF_FACE_LOCATION_Y_SIZE	0x071b /* u16 */
++
++#define HM5065_REG_AF_IN_FOCUS			0x07ae /* ro 0,1 */
++#define HM5065_REG_AF_IS_STABLE			0x0725 /* ro 0,1 */
++
++/* reverse engineered registers */
++#define HM5065_REG_BUS_DATA_FORMAT		0x7000
++#define HM5065_REG_COLORSPACE			0x5200
++#define HM5065_REG_BUS_CONFIG			0x7101
++#define HM5065_REG_BUS_CONFIG_BT656		0x24
++#define HM5065_REG_BUS_CONFIG_PARALLEL_HH_VL	0x44
++
++/* }}} */
++
++struct reg_value {
++	u16 addr;
++	u8 value;
++} __packed;
++
++/*
++ * Sensor has various pre-defined PLL configurations for a set of
++ * external clock frequencies.
++ */
++struct hm5065_clk_lut {
++	unsigned long clk_freq;
++	u8 lut_id;
++};
++
++static const struct hm5065_clk_lut hm5065_clk_luts[] = {
++	{ .clk_freq = 12000000, .lut_id = 0x10 },
++	{ .clk_freq = 13000000, .lut_id = 0x11 },
++	{ .clk_freq = 13500000, .lut_id = 0x12 },
++	{ .clk_freq = 14400000, .lut_id = 0x13 },
++	{ .clk_freq = 18000000, .lut_id = 0x14 },
++	{ .clk_freq = 19200000, .lut_id = 0x15 },
++	{ .clk_freq = 24000000, .lut_id = 0x16 },
++	{ .clk_freq = 26000000, .lut_id = 0x17 },
++	{ .clk_freq = 27000000, .lut_id = 0x18 },
++};
++
++static const struct hm5065_clk_lut *hm5065_find_clk_lut(unsigned long freq)
++{
++	int i;
++
++	for (i = 0; i < ARRAY_SIZE(hm5065_clk_luts); i++)
++		if (hm5065_clk_luts[i].clk_freq == freq)
++			return &hm5065_clk_luts[i];
++
++	return NULL;
++}
++
++struct hm5065_pixfmt {
++	u32 code;
++	u32 colorspace;
++	u8 data_fmt;
++	u8 ycbcr_order;
++	u8 fmt_setup;
++};
++
++//XXX: identify colrorspace correctly, see datasheet page 40
++static const struct hm5065_pixfmt hm5065_formats[] = {
++	{
++		.code              = MEDIA_BUS_FMT_UYVY8_2X8,
++		.colorspace        = V4L2_COLORSPACE_SRGB,
++		.data_fmt          = HM5065_REG_DATA_FORMAT_YCBCR_CUSTOM,
++		.ycbcr_order       = HM5065_REG_YCRCB_ORDER_CB_Y_CR_Y,
++		.fmt_setup         = 0x08
++	},
++	{
++		.code              = MEDIA_BUS_FMT_VYUY8_2X8,
++		.colorspace        = V4L2_COLORSPACE_SRGB,
++		.data_fmt          = HM5065_REG_DATA_FORMAT_YCBCR_CUSTOM,
++		.ycbcr_order       = HM5065_REG_YCRCB_ORDER_CR_Y_CB_Y,
++		.fmt_setup         = 0x08
++	},
++	{
++		.code              = MEDIA_BUS_FMT_YUYV8_2X8,
++		.colorspace        = V4L2_COLORSPACE_SRGB,
++		.data_fmt          = HM5065_REG_DATA_FORMAT_YCBCR_CUSTOM,
++		.ycbcr_order       = HM5065_REG_YCRCB_ORDER_Y_CB_Y_CR,
++		.fmt_setup         = 0x08
++	},
++	{
++		.code              = MEDIA_BUS_FMT_YVYU8_2X8,
++		.colorspace        = V4L2_COLORSPACE_SRGB,
++		.data_fmt          = HM5065_REG_DATA_FORMAT_YCBCR_CUSTOM,
++		.ycbcr_order       = HM5065_REG_YCRCB_ORDER_Y_CR_Y_CB,
++		.fmt_setup         = 0x08
++	},
++	{
++		.code              = MEDIA_BUS_FMT_RGB565_2X8_LE,
++		.colorspace        = V4L2_COLORSPACE_SRGB,
++		.data_fmt          = HM5065_REG_DATA_FORMAT_RGB_565,
++		.ycbcr_order       = HM5065_REG_YCRCB_ORDER_Y_CR_Y_CB,
++		.fmt_setup         = 0x02
++	},
++	{
++		.code              = MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE,
++		.colorspace        = V4L2_COLORSPACE_SRGB,
++		.data_fmt          = HM5065_REG_DATA_FORMAT_RGB_555,
++		.ycbcr_order       = HM5065_REG_YCRCB_ORDER_Y_CR_Y_CB,
++		.fmt_setup         = 0x02
++	},
++};
++
++#define HM5065_NUM_FORMATS ARRAY_SIZE(hm5065_formats)
++
++static const struct hm5065_pixfmt *hm5065_find_format(u32 code)
++{
++	int i;
++
++	for (i = 0; i < HM5065_NUM_FORMATS; i++)
++		if (hm5065_formats[i].code == code)
++			return &hm5065_formats[i];
++
++	return NULL;
++}
++
++/* regulator supplies */
++static const char * const hm5065_supply_name[] = {
++	"IOVDD", /* Digital I/O (2.8V) suppply */
++	"AFVDD",  /* Autofocus (2.8V) supply */
++	"DVDD",  /* Digital Core (1.8V) supply */
++	"AVDD",  /* Analog (2.8V) supply */
++};
++
++#define HM5065_NUM_SUPPLIES ARRAY_SIZE(hm5065_supply_name)
++
++struct hm5065_ctrls {
++	struct v4l2_ctrl_handler handler;
++	struct {
++		struct v4l2_ctrl *auto_exposure;
++		struct v4l2_ctrl *exposure;
++		struct v4l2_ctrl *d_gain;
++		struct v4l2_ctrl *a_gain;
++	};
++	struct v4l2_ctrl *metering;
++	struct v4l2_ctrl *exposure_bias;
++	struct {
++		struct v4l2_ctrl *wb;
++		struct v4l2_ctrl *blue_balance;
++		struct v4l2_ctrl *red_balance;
++	};
++	struct {
++		struct v4l2_ctrl *focus_auto;
++		struct v4l2_ctrl *af_start;
++		struct v4l2_ctrl *af_stop;
++		struct v4l2_ctrl *af_status;
++		struct v4l2_ctrl *af_distance;
++		struct v4l2_ctrl *focus_relative;
++	};
++	struct v4l2_ctrl *aaa_lock;
++	struct v4l2_ctrl *hflip;
++	struct v4l2_ctrl *vflip;
++	struct v4l2_ctrl *pl_freq;
++	struct v4l2_ctrl *colorfx;
++	struct v4l2_ctrl *brightness;
++	struct v4l2_ctrl *saturation;
++	struct v4l2_ctrl *contrast;
++	struct v4l2_ctrl *gamma;
++	struct v4l2_ctrl *test_pattern;
++	struct v4l2_ctrl *test_data[4];
++};
++
++struct hm5065_dev {
++	struct i2c_client *i2c_client;
++	struct v4l2_subdev sd;
++	struct media_pad pad;
++	struct v4l2_fwnode_endpoint ep; /* the parsed DT endpoint info */
++	struct clk *xclk; /* external clock for HM5065 */
++
++	struct regulator_bulk_data supplies[HM5065_NUM_SUPPLIES];
++	struct gpio_desc *reset_gpio; // nrst pin
++	struct gpio_desc *enable_gpio; // ce pin
++
++	/* lock to protect all members below */
++	struct mutex lock;
++
++	struct v4l2_mbus_framefmt fmt;
++	struct v4l2_fract frame_interval;
++	struct hm5065_ctrls ctrls;
++
++	bool pending_mode_change;
++	bool powered;
++	bool streaming;
++};
++
++static inline struct hm5065_dev *to_hm5065_dev(struct v4l2_subdev *sd)
++{
++	return container_of(sd, struct hm5065_dev, sd);
++}
++
++static inline struct v4l2_subdev *ctrl_to_sd(struct v4l2_ctrl *ctrl)
++{
++	return &container_of(ctrl->handler, struct hm5065_dev,
++			     ctrls.handler)->sd;
++}
++
++/* {{{ Register access helpers */
++
++static int hm5065_write_regs(struct hm5065_dev *sensor, u16 start_index,
++			     u8 *data, int data_size)
++{
++	struct i2c_client *client = sensor->i2c_client;
++	struct i2c_msg msg;
++	u8 buf[130];
++	int ret;
++
++	if (data_size > sizeof(buf) - 2) {
++		v4l2_err(&sensor->sd, "%s: oversized transfer (size=%d)\n",
++			 __func__, data_size);
++		return -EINVAL;
++	}
++
++	buf[0] = start_index >> 8;
++	buf[1] = start_index & 0xff;
++	memcpy(buf + 2, data, data_size);
++
++	msg.addr = client->addr;
++	msg.flags = client->flags;
++	msg.buf = buf;
++	msg.len = data_size + 2;
++
++	dev_dbg(&sensor->i2c_client->dev, "wr: %04x <= %*ph\n",
++		(u32)start_index, data_size, data);
++
++	ret = i2c_transfer(client->adapter, &msg, 1);
++	if (ret < 0) {
++		v4l2_err(&sensor->sd,
++			 "%s: error %d: start_index=%x, data=%*ph\n",
++			 __func__, ret, (u32)start_index, data_size, data);
++		return ret;
++	}
++
++	return 0;
++}
++
++static int hm5065_read_regs(struct hm5065_dev *sensor, u16 start_index,
++			    u8 *data, int data_size)
++{
++	struct i2c_client *client = sensor->i2c_client;
++	struct i2c_msg msg[2];
++	u8 buf[2];
++	int ret;
++
++	buf[0] = start_index >> 8;
++	buf[1] = start_index & 0xff;
++
++	msg[0].addr = client->addr;
++	msg[0].flags = client->flags;
++	msg[0].buf = buf;
++	msg[0].len = sizeof(buf);
++
++	msg[1].addr = client->addr;
++	msg[1].flags = client->flags | I2C_M_RD;
++	msg[1].buf = data;
++	msg[1].len = data_size;
++
++	ret = i2c_transfer(client->adapter, msg, 2);
++	if (ret < 0) {
++		v4l2_err(&sensor->sd,
++			 "%s: error %d: start_index=%x, data_size=%d\n",
++			 __func__, ret, (u32)start_index, data_size);
++		return ret;
++	}
++
++	dev_dbg(&sensor->i2c_client->dev, "rd: %04x => %*ph\n",
++		(u32)start_index, data_size, data);
++
++	return 0;
++}
++
++static int hm5065_read(struct hm5065_dev *sensor, u16 reg, u8 *val)
++{
++	return hm5065_read_regs(sensor, reg, val, 1);
++}
++
++static int hm5065_write(struct hm5065_dev *sensor, u16 reg, u8 val)
++{
++	return hm5065_write_regs(sensor, reg, &val, 1);
++}
++
++static int hm5065_read16(struct hm5065_dev *sensor, u16 reg, u16 *val)
++{
++	int ret;
++
++	ret = hm5065_read_regs(sensor, reg, (u8 *)val, sizeof(*val));
++	if (ret)
++		return ret;
++
++	*val = be16_to_cpu(*val);
++	return 0;
++}
++
++static int hm5065_write16(struct hm5065_dev *sensor, u16 reg, u16 val)
++{
++	u16 tmp = cpu_to_be16(val);
++
++	return hm5065_write_regs(sensor, reg, (u8 *)&tmp, sizeof(tmp));
++}
++
++/*
++ * The firmware format:
++ * <record 0>, ..., <record N - 1>
++ * "record" is a 2-byte register address (big endian) followed by 1-byte data
++ */
++static int hm5065_load_firmware(struct hm5065_dev *sensor, const char *name)
++{
++	int ret = 0, i = 0, list_size;
++	const struct firmware *fw;
++	struct reg_value *list;
++	u16 start, len;
++	u8 buf[128];
++
++	ret = request_firmware(&fw, name, sensor->sd.v4l2_dev->dev);
++	if (ret) {
++		v4l2_warn(&sensor->sd,
++			  "Failed to read firmware %s, continuing anyway...\n",
++			  name);
++		return 1;
++	}
++
++	if (fw->size == 0) {
++		ret = 1;
++		goto err_release;
++	}
++
++	if (fw->size % 3 != 0) {
++		v4l2_err(&sensor->sd, "Firmware image %s has invalid size\n",
++			 name);
++		ret = -EINVAL;
++		goto err_release;
++	}
++
++	list_size = fw->size / 3;
++	list = (struct reg_value *)fw->data;
++
++	/* we speed up I2C communication via auto-increment functionality */
++	while (i < list_size) {
++		start = be16_to_cpu(list[i].addr);
++		len = 0;
++
++		while (i < list_size &&
++		       be16_to_cpu(list[i].addr) == (start + len) &&
++		       len < sizeof(buf))
++			buf[len++] = list[i++].value;
++
++		ret = hm5065_write_regs(sensor, start, buf, len);
++		if (ret)
++			goto err_release;
++	}
++
++err_release:
++	release_firmware(fw);
++	return ret;
++}
++
++/*
++ * Sensor uses ST Float900 format to represent floating point numbers.
++ * Binary floating point number: * (s ? -1 : 0) * 1.mmmmmmmmm * 2^eeeeee
++ *
++ * Following functions convert long value to and from the floating point format.
++ *
++ * Example:
++ * mili variant: val = 123456 => fp_val = 123.456
++ * micro variant: val = -12345678 => fp_val = -12.345678
++ */
++static s64 hm5065_mili_from_fp16(u16 fp_val)
++{
++	s64 val;
++	s64 mantisa = fp_val & 0x1ff;
++	int exp = (int)((fp_val >> 9) & 0x3f) - 31;
++
++	val = (1000 * (mantisa | 0x200));
++	if (exp > 0)
++		val <<= exp;
++	else if (exp < 0)
++		val >>= -exp;
++	val >>= 9;
++
++	if (fp_val & 0x8000)
++		val = -val;
++
++	return val;
++}
++
++static u16 hm5065_mili_to_fp16(s32 val)
++{
++	int fls;
++	u16 e, m, s = 0;
++	u64 v, rem;
++
++	if (val == 0)
++		return 0;
++
++	if (val < 0) {
++		val = -val;
++		s = 0x8000;
++	}
++
++	v = (u64)val * 1024;
++	rem = do_div(v, 1000);
++	if (rem >= 500)
++		v++;
++
++	fls = fls64(v) - 1;
++	e = 31 + fls - 10;
++	m = fls > 9 ? v >> (fls - 9) : v << (9 - fls);
++
++	return s | (m & 0x1ff) | (e << 9);
++}
++
++/* }}} */
++/* {{{ Controls */
++
++static int hm5065_get_af_status(struct hm5065_dev *sensor)
++{
++	struct hm5065_ctrls *ctrls = &sensor->ctrls;
++	u8 is_stable, mode;
++	int ret;
++
++	ret = hm5065_read(sensor, HM5065_REG_AF_MODE_STATUS, &mode);
++	if (ret)
++		return ret;
++
++	if (mode == HM5065_REG_AF_MODE_MANUAL) {
++		ctrls->af_status->val = V4L2_AUTO_FOCUS_STATUS_IDLE;
++		return 0;
++	}
++
++	ret = hm5065_read(sensor, HM5065_REG_AF_IS_STABLE, &is_stable);
++	if (ret)
++		return ret;
++
++	if (is_stable)
++		ctrls->af_status->val = V4L2_AUTO_FOCUS_STATUS_REACHED;
++	else if (!is_stable && mode == HM5065_REG_AF_MODE_CONTINUOUS)
++		ctrls->af_status->val = V4L2_AUTO_FOCUS_STATUS_BUSY;
++	else
++		ctrls->af_status->val = V4L2_AUTO_FOCUS_STATUS_IDLE;
++
++	return 0;
++}
++
++static int hm5065_get_exposure(struct hm5065_dev *sensor)
++{
++	struct hm5065_ctrls *ctrls = &sensor->ctrls;
++	u16 again, dgain, exp;
++	int ret;
++
++	ret = hm5065_read16(sensor, HM5065_REG_CODED_ANALOG_GAIN_PENDING,
++			    &again);
++	if (ret)
++		return ret;
++
++	ret = hm5065_read16(sensor, HM5065_REG_DIGITAL_GAIN_PENDING, &dgain);
++	if (ret)
++		return ret;
++
++	ret = hm5065_read16(sensor, HM5065_REG_COARSE_INTEGRATION, &exp);
++	if (ret)
++		return ret;
++
++	ctrls->exposure->val = exp;
++	ctrls->d_gain->val = clamp(hm5065_mili_from_fp16(dgain), 1000ll,
++				   4000ll);
++	ctrls->a_gain->val = again;
++
++	return 0;
++}
++
++static int hm5065_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = ctrl_to_sd(ctrl);
++	struct hm5065_dev *sensor = to_hm5065_dev(sd);
++	int ret;
++
++	/* v4l2_ctrl_lock() locks our own mutex */
++
++	if (!sensor->powered)
++		return -EIO;
++
++	switch (ctrl->id) {
++	case V4L2_CID_FOCUS_AUTO:
++		ret = hm5065_get_af_status(sensor);
++		if (ret)
++			return ret;
++		break;
++	case V4L2_CID_EXPOSURE_AUTO:
++		ret = hm5065_get_exposure(sensor);
++		if (ret)
++			return ret;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static const u8 hm5065_wb_opts[][2] = {
++	{ V4L2_WHITE_BALANCE_MANUAL, HM5065_REG_WB_MODE_OFF },
++	{ V4L2_WHITE_BALANCE_INCANDESCENT, HM5065_REG_WB_MODE_TUNGSTEN_PRESET },
++	{ V4L2_WHITE_BALANCE_FLUORESCENT,
++		HM5065_REG_WB_MODE_FLUORESCENT_PRESET },
++	{ V4L2_WHITE_BALANCE_HORIZON, HM5065_REG_WB_MODE_HORIZON_PRESET },
++	{ V4L2_WHITE_BALANCE_CLOUDY, HM5065_REG_WB_MODE_CLOUDY_PRESET },
++	{ V4L2_WHITE_BALANCE_DAYLIGHT, HM5065_REG_WB_MODE_SUNNY_PRESET },
++	{ V4L2_WHITE_BALANCE_AUTO, HM5065_REG_WB_MODE_AUTOMATIC },
++};
++
++static int hm5065_set_power_line_frequency(struct hm5065_dev *sensor, s32 val)
++{
++	u16 freq;
++	int ret;
++
++	switch (val) {
++	case V4L2_CID_POWER_LINE_FREQUENCY_DISABLED:
++		ret = hm5065_write(sensor, HM5065_REG_ANTI_FLICKER_MODE, 0);
++		if (ret)
++			return ret;
++
++		return hm5065_write(sensor, HM5065_REG_FD_ENABLE_DETECT, 0);
++	case V4L2_CID_POWER_LINE_FREQUENCY_50HZ:
++	case V4L2_CID_POWER_LINE_FREQUENCY_60HZ:
++		ret = hm5065_write(sensor, HM5065_REG_ANTI_FLICKER_MODE, 1);
++		if (ret)
++			return ret;
++
++		ret = hm5065_write(sensor, HM5065_REG_FD_ENABLE_DETECT, 0);
++		if (ret)
++			return ret;
++
++		freq = (val == V4L2_CID_POWER_LINE_FREQUENCY_50HZ) ?
++			0x4b20 : 0x4bc0;
++
++		return hm5065_write16(sensor, HM5065_REG_FD_FLICKER_FREQUENCY,
++				      freq);
++	case V4L2_CID_POWER_LINE_FREQUENCY_AUTO:
++		ret = hm5065_write(sensor, HM5065_REG_FD_ENABLE_DETECT, 1);
++		if (ret)
++			return ret;
++
++		ret = hm5065_write(sensor, HM5065_REG_ANTI_FLICKER_MODE, 1);
++		if (ret)
++			return ret;
++
++		ret = hm5065_write16(sensor, HM5065_REG_FD_MAX_NUMBER_ATTEMP,
++				     100);
++		if (ret)
++			return ret;
++
++		ret = hm5065_write16(sensor, HM5065_REG_FD_FLICKER_FREQUENCY,
++				     0);
++		if (ret)
++			return ret;
++
++		return hm5065_write(sensor, HM5065_REG_FD_DETECTION_START, 1);
++	default:
++		return -EINVAL;
++	}
++}
++
++static int hm5065_set_colorfx(struct hm5065_dev *sensor, s32 val)
++{
++	int ret;
++
++	ret = hm5065_write(sensor, HM5065_REG_EFFECTS_COLOR,
++			   HM5065_REG_EFFECTS_COLOR_NORMAL);
++	if (ret)
++		return ret;
++
++	ret = hm5065_write(sensor, HM5065_REG_EFFECTS_NEGATIVE, 0);
++	if (ret)
++		return ret;
++
++	ret = hm5065_write(sensor, HM5065_REG_EFFECTS_SOLARISING, 0);
++	if (ret)
++		return ret;
++
++	ret = hm5065_write(sensor, HM5065_REG_EFFECTS_SKECTH, 0);
++	if (ret)
++		return ret;
++
++	switch (val) {
++	case V4L2_COLORFX_NONE:
++		return 0;
++	case V4L2_COLORFX_NEGATIVE:
++		return hm5065_write(sensor, HM5065_REG_EFFECTS_NEGATIVE, 1);
++	case V4L2_COLORFX_SOLARIZATION:
++		return hm5065_write(sensor, HM5065_REG_EFFECTS_SOLARISING, 1);
++	case V4L2_COLORFX_SKETCH:
++		return hm5065_write(sensor, HM5065_REG_EFFECTS_SKECTH, 1);
++	case V4L2_COLORFX_ANTIQUE:
++		return hm5065_write(sensor, HM5065_REG_EFFECTS_COLOR,
++				    HM5065_REG_EFFECTS_COLOR_ANTIQUE);
++	case V4L2_COLORFX_SEPIA:
++		return hm5065_write(sensor, HM5065_REG_EFFECTS_COLOR,
++				    HM5065_REG_EFFECTS_COLOR_SEPIA);
++	case V4L2_COLORFX_AQUA:
++		return hm5065_write(sensor, HM5065_REG_EFFECTS_COLOR,
++				    HM5065_REG_EFFECTS_COLOR_AQUA);
++	case V4L2_COLORFX_BW:
++		return hm5065_write(sensor, HM5065_REG_EFFECTS_COLOR,
++				    HM5065_REG_EFFECTS_COLOR_BLACK_WHITE);
++	default:
++		return -EINVAL;
++	}
++}
++
++#define AE_BIAS_MENU_DEFAULT_VALUE_INDEX 7
++static const s64 ae_bias_menu_values[] = {
++	-2100, -1800, -1500, -1200, -900, -600, -300,
++	0, 300, 600, 900, 1200, 1500, 1800, 2100
++};
++
++static const s8 ae_bias_menu_reg_values[] = {
++	-7, -6, -5, -4, -3, -2, -1, 0, 1, 2, 3, 4, 5, 6, 7
++};
++
++static int hm5065_set_exposure(struct hm5065_dev *sensor)
++{
++	struct hm5065_ctrls *ctrls = &sensor->ctrls;
++	bool is_auto = (ctrls->auto_exposure->val != V4L2_EXPOSURE_MANUAL);
++	int ret = 0;
++
++	if (ctrls->auto_exposure->is_new) {
++		ret = hm5065_write(sensor, HM5065_REG_EXPOSURE_MODE,
++				   is_auto ?
++				   HM5065_REG_EXPOSURE_MODE_AUTO :
++				   HM5065_REG_EXPOSURE_MODE_DIRECT_MANUAL);
++		if (ret)
++			return ret;
++
++		if (ctrls->auto_exposure->cur.val != ctrls->auto_exposure->val &&
++		    !is_auto) {
++			/*
++			 * Hack: At this point, there are current volatile
++			 * values in val, but control framework will not
++			 * update the cur values for our autocluster, as it
++			 * should. I couldn't find the reason. This fixes
++			 * it for our driver. Remove this after the kernel
++			 * is fixed.
++			 */
++			ctrls->exposure->cur.val = ctrls->exposure->val;
++			ctrls->d_gain->cur.val = ctrls->d_gain->val;
++			ctrls->a_gain->cur.val = ctrls->a_gain->val;
++		}
++	}
++
++	if (!is_auto && ctrls->exposure->is_new) {
++		ret = hm5065_write16(sensor,
++			   HM5065_REG_DIRECT_MODE_COARSE_INTEGRATION_LINES,
++			   ctrls->exposure->val);
++		if (ret)
++			return ret;
++	}
++
++	if (!is_auto && ctrls->d_gain->is_new) {
++		ret = hm5065_write16(sensor,
++				     HM5065_REG_DIRECT_MODE_DIGITAL_GAIN,
++				     hm5065_mili_to_fp16(ctrls->d_gain->val));
++		if (ret)
++			return ret;
++	}
++
++	if (!is_auto && ctrls->a_gain->is_new)
++		ret = hm5065_write16(sensor,
++				     HM5065_REG_DIRECT_MODE_CODED_ANALOG_GAIN,
++				     ctrls->a_gain->val);
++
++	return ret;
++}
++
++static int hm5065_3a_lock(struct hm5065_dev *sensor, struct v4l2_ctrl *ctrl)
++{
++	bool awb_lock = ctrl->val & V4L2_LOCK_WHITE_BALANCE;
++	bool ae_lock = ctrl->val & V4L2_LOCK_EXPOSURE;
++	int ret = 0;
++
++	if ((ctrl->val ^ ctrl->cur.val) & V4L2_LOCK_EXPOSURE
++	    && sensor->ctrls.auto_exposure->val == V4L2_EXPOSURE_AUTO) {
++		ret = hm5065_write(sensor, HM5065_REG_FREEZE_AUTO_EXPOSURE,
++				   ae_lock);
++		if (ret)
++			return ret;
++	}
++
++	if (((ctrl->val ^ ctrl->cur.val) & V4L2_LOCK_WHITE_BALANCE)
++	    && sensor->ctrls.wb->val == V4L2_WHITE_BALANCE_AUTO) {
++		ret = hm5065_write(sensor, HM5065_REG_WB_MISC_SETTINGS,
++				   awb_lock ?
++				   HM5065_REG_WB_MISC_SETTINGS_FREEZE_ALGO : 0);
++		if (ret)
++			return ret;
++	}
++
++	return ret;
++}
++
++static int hm5065_set_auto_focus(struct hm5065_dev *sensor)
++{
++	struct hm5065_ctrls *ctrls = &sensor->ctrls;
++	bool auto_focus = ctrls->focus_auto->val;
++	int ret = 0;
++	u8 range;
++
++	if (auto_focus && ctrls->af_distance->is_new) {
++		switch (ctrls->af_distance->val) {
++		case V4L2_AUTO_FOCUS_RANGE_MACRO:
++			range = HM5065_REG_AF_RANGE_MACRO;
++			break;
++		case V4L2_AUTO_FOCUS_RANGE_AUTO:
++			range = HM5065_REG_AF_RANGE_FULL;
++			break;
++		case V4L2_AUTO_FOCUS_RANGE_INFINITY:
++			range = HM5065_REG_AF_RANGE_LANDSCAPE;
++			break;
++		default:
++			return -EINVAL;
++		}
++
++		ret = hm5065_write(sensor, HM5065_REG_AF_RANGE, range);
++		if (ret)
++			return ret;
++	}
++
++	if (ctrls->focus_auto->is_new) {
++		v4l2_ctrl_activate(ctrls->af_start, !auto_focus);
++		v4l2_ctrl_activate(ctrls->af_stop, !auto_focus);
++		v4l2_ctrl_activate(ctrls->focus_relative, !auto_focus);
++
++		ret = hm5065_write(sensor, HM5065_REG_AF_MODE,
++				   auto_focus ?
++				   HM5065_REG_AF_MODE_CONTINUOUS :
++				   HM5065_REG_AF_MODE_SINGLE);
++		if (ret)
++			return ret;
++
++		if (!auto_focus) {
++			ret = hm5065_write(sensor, HM5065_REG_AF_COMMAND,
++					 HM5065_REG_AF_COMMAND_RELEASED_BUTTON);
++			if (ret)
++				return ret;
++		}
++	}
++
++	if (!auto_focus && ctrls->af_start->is_new) {
++		ret = hm5065_write(sensor, HM5065_REG_AF_MODE,
++				   HM5065_REG_AF_MODE_SINGLE);
++		if (ret)
++			return ret;
++
++		ret = hm5065_write(sensor, HM5065_REG_AF_COMMAND,
++				   HM5065_REG_AF_COMMAND_RELEASED_BUTTON);
++		if (ret)
++			return ret;
++
++		usleep_range(190000, 200000);
++
++		ret = hm5065_write(sensor, HM5065_REG_AF_COMMAND,
++				   HM5065_REG_AF_COMMAND_HALF_BUTTON);
++		if (ret)
++			return ret;
++	}
++
++	if (!auto_focus && ctrls->af_stop->is_new) {
++		ret = hm5065_write(sensor, HM5065_REG_AF_COMMAND,
++				   HM5065_REG_AF_COMMAND_RELEASED_BUTTON);
++		if (ret)
++			return ret;
++
++		ret = hm5065_write(sensor, HM5065_REG_AF_MODE,
++				   HM5065_REG_AF_MODE_MANUAL);
++		if (ret)
++			return ret;
++	}
++
++	if (!auto_focus && ctrls->focus_relative->is_new &&
++	    ctrls->focus_relative->val) {
++		u8 cmd = 0xff;
++		s32 step = ctrls->focus_relative->val;
++
++		ctrls->focus_relative->val = 0;
++
++		ret = hm5065_write(sensor, HM5065_REG_AF_MODE,
++				   HM5065_REG_AF_MODE_MANUAL);
++		if (ret)
++			return ret;
++
++		ret = hm5065_write(sensor, HM5065_REG_AF_MANUAL_STEP_SIZE,
++				   abs(step));
++		if (ret)
++			return ret;
++
++		if (step < 0)
++			cmd = HM5065_REG_AF_LENS_COMMAND_MOVE_STEP_TO_INFINITY;
++		else if (step > 0)
++			cmd = HM5065_REG_AF_LENS_COMMAND_MOVE_STEP_TO_MACRO;
++
++		if (cmd != 0xff)
++			ret = hm5065_write(sensor, HM5065_REG_AF_LENS_COMMAND,
++					   cmd);
++
++		if (ret)
++			return ret;
++	}
++
++	return ret;
++}
++
++static int hm5065_set_white_balance(struct hm5065_dev *sensor)
++{
++	struct hm5065_ctrls *ctrls = &sensor->ctrls;
++	bool manual_wb = ctrls->wb->val == V4L2_WHITE_BALANCE_MANUAL;
++	int ret = 0, i;
++	s32 val;
++
++	if (ctrls->wb->is_new) {
++		for (i = 0; i < ARRAY_SIZE(hm5065_wb_opts); i++) {
++			if (hm5065_wb_opts[i][0] != ctrls->wb->val)
++				continue;
++
++			ret = hm5065_write(sensor, HM5065_REG_WB_MODE,
++					    hm5065_wb_opts[i][1]);
++			if (ret)
++				return ret;
++			goto next;
++		}
++
++		return -EINVAL;
++	}
++
++next:
++	if (ctrls->wb->is_new || ctrls->blue_balance->is_new) {
++		val = manual_wb ? ctrls->blue_balance->val : 1000;
++		ret = hm5065_write16(sensor, HM5065_REG_WB_HUE_B_BIAS,
++				     hm5065_mili_to_fp16(val));
++		if (ret)
++			return ret;
++	}
++
++	if (ctrls->wb->is_new || ctrls->red_balance->is_new) {
++		val = manual_wb ? ctrls->red_balance->val : 1000;
++		ret = hm5065_write16(sensor, HM5065_REG_WB_HUE_R_BIAS,
++				     hm5065_mili_to_fp16(val));
++	}
++
++	return ret;
++}
++
++static int hm5065_s_ctrl(struct v4l2_ctrl *ctrl)
++{
++	struct v4l2_subdev *sd = ctrl_to_sd(ctrl);
++	struct hm5065_dev *sensor = to_hm5065_dev(sd);
++	struct hm5065_ctrls *ctrls = &sensor->ctrls;
++	s32 val = ctrl->val;
++	unsigned int i;
++	int ret;
++	u8 reg;
++
++	/* v4l2_ctrl_lock() locks our own mutex */
++
++	/*
++	 * If the device is not powered up by the host driver do
++	 * not apply any controls to H/W at this time. Instead
++	 * the controls will be restored right after power-up.
++	 */
++	if (!sensor->powered)
++		return 0;
++
++	switch (ctrl->id) {
++	case V4L2_CID_EXPOSURE_AUTO:
++		return hm5065_set_exposure(sensor);
++
++	case V4L2_CID_EXPOSURE_METERING:
++		if (val == V4L2_EXPOSURE_METERING_AVERAGE)
++			reg = HM5065_REG_EXPOSURE_METERING_FLAT;
++		else if (val == V4L2_EXPOSURE_METERING_CENTER_WEIGHTED)
++			reg = HM5065_REG_EXPOSURE_METERING_CENTERED;
++		else
++			return -EINVAL;
++
++		return hm5065_write(sensor, HM5065_REG_EXPOSURE_METERING, reg);
++
++	case V4L2_CID_AUTO_EXPOSURE_BIAS:
++		if (val < 0 || val >= ARRAY_SIZE(ae_bias_menu_reg_values))
++			return -EINVAL;
++
++		return hm5065_write(sensor, HM5065_REG_EXPOSURE_COMPENSATION,
++				    (u8)ae_bias_menu_reg_values[val]);
++
++	case V4L2_CID_FOCUS_AUTO:
++		return hm5065_set_auto_focus(sensor);
++
++	case V4L2_CID_CONTRAST:
++		return hm5065_write(sensor, HM5065_REG_CONTRAST, val);
++
++	case V4L2_CID_SATURATION:
++		return hm5065_write(sensor, HM5065_REG_COLOR_SATURATION, val);
++
++	case V4L2_CID_BRIGHTNESS:
++		return hm5065_write(sensor, HM5065_REG_BRIGHTNESS, val);
++
++	case V4L2_CID_POWER_LINE_FREQUENCY:
++		return hm5065_set_power_line_frequency(sensor, val);
++
++	case V4L2_CID_GAMMA:
++		return hm5065_write(sensor, HM5065_REG_P0_GAMMA_GAIN, val);
++
++	case V4L2_CID_VFLIP:
++		return hm5065_write(sensor, HM5065_REG_VERTICAL_FLIP,
++				    val ? 1 : 0);
++
++	case V4L2_CID_HFLIP:
++		return hm5065_write(sensor, HM5065_REG_HORIZONTAL_MIRROR,
++				    val ? 1 : 0);
++
++	case V4L2_CID_COLORFX:
++		return hm5065_set_colorfx(sensor, val);
++
++	case V4L2_CID_3A_LOCK:
++		return hm5065_3a_lock(sensor, ctrl);
++
++	case V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE:
++		return hm5065_set_white_balance(sensor);
++
++	case V4L2_CID_TEST_PATTERN_RED:
++		return hm5065_write16(sensor, HM5065_REG_TESTDATA_RED, val);
++
++	case V4L2_CID_TEST_PATTERN_GREENR:
++		return hm5065_write16(sensor, HM5065_REG_TESTDATA_GREEN_R, val);
++
++	case V4L2_CID_TEST_PATTERN_BLUE:
++		return hm5065_write16(sensor, HM5065_REG_TESTDATA_BLUE, val);
++
++	case V4L2_CID_TEST_PATTERN_GREENB:
++		return hm5065_write16(sensor, HM5065_REG_TESTDATA_GREEN_B, val);
++
++	case V4L2_CID_TEST_PATTERN:
++		for (i = 0; i < ARRAY_SIZE(ctrls->test_data); i++)
++			v4l2_ctrl_activate(ctrls->test_data[i],
++					   val == 6); /* solid color */
++
++		ret = hm5065_write(sensor, HM5065_REG_ENABLE_TEST_PATTERN,
++				   val == 0 ? 0 : 1);
++		if (ret)
++			return ret;
++
++		return hm5065_write(sensor, HM5065_REG_TEST_PATTERN, val);
++
++	default:
++		return -EINVAL;
++	}
++}
++
++static const struct v4l2_ctrl_ops hm5065_ctrl_ops = {
++	.g_volatile_ctrl = hm5065_g_volatile_ctrl,
++	.s_ctrl = hm5065_s_ctrl,
++};
++
++static const char * const test_pattern_menu[] = {
++	"Disabled",
++	"Horizontal gray scale",
++	"Vertical gray scale",
++	"Diagonal gray scale",
++	"PN28",
++	"PN9 (bus test)",
++	"Solid color",
++	"Color bars",
++	"Graduated color bars",
++};
++
++static int hm5065_init_controls(struct hm5065_dev *sensor)
++{
++	const struct v4l2_ctrl_ops *ops = &hm5065_ctrl_ops;
++	struct hm5065_ctrls *ctrls = &sensor->ctrls;
++	struct v4l2_ctrl_handler *hdl = &ctrls->handler;
++	u8 wb_max = 0;
++	u64 wb_mask = 0;
++	unsigned int i;
++	int ret;
++
++	v4l2_ctrl_handler_init(hdl, 32);
++
++	/* we can use our own mutex for the ctrl lock */
++	hdl->lock = &sensor->lock;
++
++	ctrls->auto_exposure = v4l2_ctrl_new_std_menu(hdl, ops,
++						      V4L2_CID_EXPOSURE_AUTO,
++						      V4L2_EXPOSURE_MANUAL, 0,
++						      V4L2_EXPOSURE_AUTO);
++	ctrls->exposure = v4l2_ctrl_new_std(hdl, ops,
++					    V4L2_CID_EXPOSURE,
++					    1, HM5065_SENSOR_HEIGHT, 1, 30);
++	ctrls->d_gain = v4l2_ctrl_new_std(hdl, ops,
++					  V4L2_CID_DIGITAL_GAIN,
++					  1000, 4000, 1, 1000);
++
++	ctrls->a_gain = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_ANALOGUE_GAIN,
++					  0, 0xf4, 1, 0);
++
++	ctrls->metering =
++		v4l2_ctrl_new_std_menu(hdl, ops, V4L2_CID_EXPOSURE_METERING,
++				       V4L2_EXPOSURE_METERING_CENTER_WEIGHTED,
++				       0, V4L2_EXPOSURE_METERING_AVERAGE);
++	ctrls->exposure_bias =
++		v4l2_ctrl_new_int_menu(hdl, ops,
++				       V4L2_CID_AUTO_EXPOSURE_BIAS,
++				       ARRAY_SIZE(ae_bias_menu_values) - 1,
++				       AE_BIAS_MENU_DEFAULT_VALUE_INDEX,
++				       ae_bias_menu_values);
++
++	for (i = 0; i < ARRAY_SIZE(hm5065_wb_opts); i++) {
++		if (wb_max < hm5065_wb_opts[i][0])
++			wb_max = hm5065_wb_opts[i][0];
++		wb_mask |= BIT(hm5065_wb_opts[i][0]);
++	}
++
++	ctrls->wb = v4l2_ctrl_new_std_menu(hdl, ops,
++			V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE,
++			wb_max, ~wb_mask, V4L2_WHITE_BALANCE_AUTO);
++
++	ctrls->blue_balance = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BLUE_BALANCE,
++						0, 4000, 1, 1000);
++	ctrls->red_balance = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_RED_BALANCE,
++					       0, 4000, 1, 1000);
++
++	ctrls->gamma = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAMMA,
++					 0, 31, 1, 20);
++
++	ctrls->colorfx =
++		v4l2_ctrl_new_std_menu(hdl, ops, V4L2_CID_COLORFX, 15,
++				       ~(BIT(V4L2_COLORFX_NONE) |
++					 BIT(V4L2_COLORFX_NEGATIVE) |
++					 BIT(V4L2_COLORFX_SOLARIZATION) |
++					 BIT(V4L2_COLORFX_SKETCH) |
++					 BIT(V4L2_COLORFX_SEPIA) |
++					 BIT(V4L2_COLORFX_ANTIQUE) |
++					 BIT(V4L2_COLORFX_AQUA) |
++					 BIT(V4L2_COLORFX_BW)),
++				       V4L2_COLORFX_NONE);
++
++	ctrls->pl_freq =
++		v4l2_ctrl_new_std_menu(hdl, ops, V4L2_CID_POWER_LINE_FREQUENCY,
++				V4L2_CID_POWER_LINE_FREQUENCY_AUTO, 0,
++				V4L2_CID_POWER_LINE_FREQUENCY_50HZ);
++
++	ctrls->hflip = v4l2_ctrl_new_std(hdl, ops,
++					 V4L2_CID_HFLIP, 0, 1, 1, 0);
++	ctrls->vflip = v4l2_ctrl_new_std(hdl, ops,
++					 V4L2_CID_VFLIP, 0, 1, 1, 0);
++
++	ctrls->focus_auto = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_FOCUS_AUTO,
++					      0, 1, 1, 1);
++
++	ctrls->af_start = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_AUTO_FOCUS_START,
++					    0, 1, 1, 0);
++
++	ctrls->af_stop = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_AUTO_FOCUS_STOP,
++					   0, 1, 1, 0);
++
++	ctrls->af_status = v4l2_ctrl_new_std(hdl, ops,
++					     V4L2_CID_AUTO_FOCUS_STATUS, 0,
++					     (V4L2_AUTO_FOCUS_STATUS_BUSY |
++					      V4L2_AUTO_FOCUS_STATUS_REACHED |
++					      V4L2_AUTO_FOCUS_STATUS_FAILED),
++					     0, V4L2_AUTO_FOCUS_STATUS_IDLE);
++
++	ctrls->af_distance =
++		v4l2_ctrl_new_std_menu(hdl, ops,
++				       V4L2_CID_AUTO_FOCUS_RANGE,
++				       V4L2_AUTO_FOCUS_RANGE_MACRO,
++				       ~(BIT(V4L2_AUTO_FOCUS_RANGE_AUTO) |
++					 BIT(V4L2_AUTO_FOCUS_RANGE_INFINITY) |
++					 BIT(V4L2_AUTO_FOCUS_RANGE_MACRO)),
++				       V4L2_AUTO_FOCUS_RANGE_AUTO);
++
++	ctrls->focus_relative = v4l2_ctrl_new_std(hdl, ops,
++						  V4L2_CID_FOCUS_RELATIVE,
++						  -100, 100, 1, 0);
++
++	ctrls->brightness = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BRIGHTNESS,
++					      0, 200, 1, 90);
++	ctrls->saturation = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_SATURATION,
++					      0, 200, 1, 110);
++	ctrls->contrast = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST,
++					    0, 200, 1, 108);
++
++	ctrls->aaa_lock = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_3A_LOCK,
++					    0, 0x7, 0, 0);
++
++	ctrls->test_pattern =
++		v4l2_ctrl_new_std_menu_items(hdl, ops, V4L2_CID_TEST_PATTERN,
++					     ARRAY_SIZE(test_pattern_menu) - 1,
++					     0, 0, test_pattern_menu);
++	for (i = 0; i < ARRAY_SIZE(ctrls->test_data); i++)
++		ctrls->test_data[i] =
++			v4l2_ctrl_new_std(hdl, ops,
++					  V4L2_CID_TEST_PATTERN_RED + i,
++					  0, 1023, 1, 0);
++
++	if (hdl->error) {
++		ret = hdl->error;
++		goto free_ctrls;
++	}
++
++	ctrls->af_status->flags |= V4L2_CTRL_FLAG_VOLATILE |
++		V4L2_CTRL_FLAG_READ_ONLY;
++
++	v4l2_ctrl_auto_cluster(3, &ctrls->wb, V4L2_WHITE_BALANCE_MANUAL, false);
++	v4l2_ctrl_auto_cluster(4, &ctrls->auto_exposure, V4L2_EXPOSURE_MANUAL,
++			       true);
++	v4l2_ctrl_cluster(6, &ctrls->focus_auto);
++
++	sensor->sd.ctrl_handler = hdl;
++	return 0;
++
++free_ctrls:
++	v4l2_ctrl_handler_free(hdl);
++	return ret;
++}
++
++/* }}} */
++/* {{{ Video ops */
++
++static int hm5065_get_frame_interval(struct v4l2_subdev *sd,
++				     struct v4l2_subdev_state *sd_state,
++				     struct v4l2_subdev_frame_interval *fi)
++{
++	struct hm5065_dev *sensor = to_hm5065_dev(sd);
++
++	if (fi->pad != 0)
++		return -EINVAL;
++
++	mutex_lock(&sensor->lock);
++	fi->interval = sensor->frame_interval;
++	mutex_unlock(&sensor->lock);
++
++	return 0;
++}
++
++static int hm5065_get_max_binning(int width, int height)
++{
++	if (width < HM5065_SENSOR_WIDTH / 4 &&
++	    height < HM5065_SENSOR_HEIGHT / 4)
++		return 4;
++	else if (width < HM5065_SENSOR_WIDTH / 2 &&
++		 height < HM5065_SENSOR_HEIGHT / 2)
++		return 2;
++
++	return 1;
++}
++
++static int hm5065_get_max_fps(int width, int height)
++{
++	int max_fps, bin_factor;
++
++	// more bining allows for faster readouts
++	bin_factor = hm5065_get_max_binning(width, height);
++	max_fps = 25000000 / (width * height * 2) * bin_factor;
++
++	return clamp(max_fps, 1, 60);
++}
++
++static int hm5065_set_frame_interval(struct v4l2_subdev *sd,
++				     struct v4l2_subdev_state *sd_state,
++				     struct v4l2_subdev_frame_interval *fi)
++{
++	struct hm5065_dev *sensor = to_hm5065_dev(sd);
++	int ret = 0, fps, max_fps;
++
++	if (fi->pad != 0)
++		return -EINVAL;
++
++	mutex_lock(&sensor->lock);
++
++	max_fps = hm5065_get_max_fps(sensor->fmt.width, sensor->fmt.height);
++
++	/* user requested infinite frame rate */
++	if (fi->interval.numerator == 0)
++		fps = max_fps;
++	else
++		fps = DIV_ROUND_CLOSEST(fi->interval.denominator,
++					fi->interval.numerator);
++
++	fps = clamp(fps, 1, max_fps);
++
++	sensor->frame_interval.numerator = 1;
++	sensor->frame_interval.denominator = fps;
++	fi->interval = sensor->frame_interval;
++
++	if (sensor->streaming) {
++		ret = hm5065_write16(sensor, HM5065_REG_DESIRED_FRAME_RATE_NUM,
++				     fps);
++		if (ret)
++			goto err_unlock;
++
++		ret = hm5065_write(sensor, HM5065_REG_DESIRED_FRAME_RATE_DEN,
++				   1);
++	}
++
++err_unlock:
++	mutex_unlock(&sensor->lock);
++	return ret;
++}
++
++static int hm5065_setup_mode(struct hm5065_dev *sensor)
++{
++	const struct hm5065_pixfmt *pix_fmt;
++	u8 sensor_mode;
++	int ret, fps;
++
++	pix_fmt = hm5065_find_format(sensor->fmt.code);
++	if (!pix_fmt) {
++		dev_err(&sensor->i2c_client->dev,
++			"pixel format not supported %u\n", sensor->fmt.code);
++		return -EINVAL;
++	}
++
++	ret = hm5065_write(sensor, HM5065_REG_USER_COMMAND,
++			   HM5065_REG_USER_COMMAND_POWEROFF);
++	if (ret)
++		return ret;
++
++	switch (hm5065_get_max_binning(sensor->fmt.width, sensor->fmt.height)) {
++	case 4:
++		sensor_mode = HM5065_REG_SENSOR_MODE_BINNING_4X4;
++		break;
++	case 2:
++		sensor_mode = HM5065_REG_SENSOR_MODE_BINNING_2X2;
++		break;
++	default:
++		sensor_mode = HM5065_REG_SENSOR_MODE_FULLSIZE;
++	}
++
++	ret = hm5065_write(sensor, HM5065_REG_P0_SENSOR_MODE, sensor_mode);
++	if (ret)
++		return ret;
++
++	ret = hm5065_write16(sensor, HM5065_REG_P0_MANUAL_HSIZE,
++			     sensor->fmt.width);
++	if (ret)
++		return ret;
++
++	ret = hm5065_write16(sensor, HM5065_REG_P0_MANUAL_VSIZE,
++			     sensor->fmt.height);
++	if (ret)
++		return ret;
++
++	ret = hm5065_write(sensor, HM5065_REG_P0_IMAGE_SIZE,
++			   HM5065_REG_IMAGE_SIZE_MANUAL);
++	if (ret)
++		return ret;
++
++	ret = hm5065_write(sensor, HM5065_REG_P0_DATA_FORMAT,
++			   pix_fmt->data_fmt);
++	if (ret)
++		return ret;
++
++	ret = hm5065_write(sensor, HM5065_REG_YCRCB_ORDER,
++			   pix_fmt->ycbcr_order);
++	if (ret)
++		return ret;
++
++	/* without this, brightness, contrast and saturation will not work */
++	ret = hm5065_write(sensor, HM5065_REG_COLORSPACE, 9);
++	if (ret)
++		return ret;
++
++	ret = hm5065_write(sensor, HM5065_REG_BUS_DATA_FORMAT,
++			   pix_fmt->fmt_setup);
++	if (ret)
++		return ret;
++
++	fps = hm5065_get_max_fps(sensor->fmt.width, sensor->fmt.height);
++	fps = clamp(fps, 1, (int)sensor->frame_interval.denominator);
++
++	ret = hm5065_write16(sensor, HM5065_REG_DESIRED_FRAME_RATE_NUM, fps);
++	if (ret)
++		return ret;
++
++	ret = hm5065_write(sensor, HM5065_REG_DESIRED_FRAME_RATE_DEN, 1);
++	if (ret)
++		return ret;
++
++	return 0;
++}
++
++static int hm5065_set_stream(struct hm5065_dev *sensor, int enable)
++{
++	return hm5065_write(sensor, HM5065_REG_USER_COMMAND, enable ?
++			    HM5065_REG_USER_COMMAND_RUN :
++			    HM5065_REG_USER_COMMAND_STOP);
++}
++
++static int hm5065_s_stream(struct v4l2_subdev *sd, int enable)
++{
++	struct hm5065_dev *sensor = to_hm5065_dev(sd);
++	int ret = 0;
++
++	mutex_lock(&sensor->lock);
++
++	if (sensor->streaming == !enable) {
++		if (enable && sensor->pending_mode_change) {
++			ret = hm5065_setup_mode(sensor);
++			if (ret)
++				goto out;
++		}
++
++		ret = hm5065_set_stream(sensor, enable);
++		if (ret)
++			goto out;
++
++		if (enable && sensor->ctrls.focus_auto->cur.val) {
++			msleep(100);
++
++			/* checking error here is not super important */
++			hm5065_write(sensor, HM5065_REG_AF_MODE,
++				     HM5065_REG_AF_MODE_CONTINUOUS);
++		}
++
++		sensor->streaming = !!enable;
++	}
++
++out:
++	mutex_unlock(&sensor->lock);
++	return ret;
++}
++
++/* }}} */
++/* {{{ Pad ops */
++
++static int hm5065_enum_mbus_code(struct v4l2_subdev *sd,
++				 struct v4l2_subdev_state *sd_state,
++				 struct v4l2_subdev_mbus_code_enum *code)
++{
++	if (code->pad != 0)
++		return -EINVAL;
++	if (code->index >= HM5065_NUM_FORMATS)
++		return -EINVAL;
++
++	code->code = hm5065_formats[code->index].code;
++
++	return 0;
++}
++
++static int hm5065_enum_frame_size(struct v4l2_subdev *sd,
++				  struct v4l2_subdev_state *sd_state,
++				  struct v4l2_subdev_frame_size_enum *fse)
++{
++	if (fse->pad != 0)
++		return -EINVAL;
++	if (fse->index != 0)
++		return -EINVAL;
++
++	fse->min_width = HM5065_CAPTURE_WIDTH_MIN;
++	fse->min_height = HM5065_CAPTURE_HEIGHT_MIN;
++
++	fse->max_width = HM5065_SENSOR_WIDTH;
++	fse->max_height = HM5065_SENSOR_HEIGHT;
++
++	return 0;
++}
++
++static int hm5065_enum_frame_interval(struct v4l2_subdev *sd,
++				      struct v4l2_subdev_state *sd_state,
++				      struct v4l2_subdev_frame_interval_enum
++				      *fie)
++{
++	struct v4l2_fract tpf;
++	u32 max_fps, width, height;
++
++	if (fie->pad != 0)
++		return -EINVAL;
++
++	width = clamp(fie->width, HM5065_CAPTURE_WIDTH_MIN,
++		      HM5065_SENSOR_WIDTH);
++	height = clamp(fie->height, HM5065_CAPTURE_HEIGHT_MIN,
++		       HM5065_SENSOR_HEIGHT);
++
++	max_fps = hm5065_get_max_fps(width, height);
++
++	if (fie->index + 1 > max_fps)
++		return -EINVAL;
++
++	tpf.numerator = 1;
++	tpf.denominator = fie->index + 1;
++	fie->interval = tpf;
++
++	return 0;
++}
++
++static int hm5065_get_fmt(struct v4l2_subdev *sd,
++			  struct v4l2_subdev_state *sd_state,
++			  struct v4l2_subdev_format *format)
++{
++	struct hm5065_dev *sensor = to_hm5065_dev(sd);
++	struct v4l2_mbus_framefmt *mf;
++
++	if (format->pad != 0)
++		return -EINVAL;
++
++	if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
++		mf = v4l2_subdev_state_get_format(sd_state, format->pad);
++		format->format = *mf;
++		return 0;
++	}
++
++	mutex_lock(&sensor->lock);
++	format->format = sensor->fmt;
++	mutex_unlock(&sensor->lock);
++
++	return 0;
++}
++
++static int hm5065_set_fmt(struct v4l2_subdev *sd,
++			  struct v4l2_subdev_state *sd_state,
++			  struct v4l2_subdev_format *format)
++{
++	struct hm5065_dev *sensor = to_hm5065_dev(sd);
++	struct v4l2_mbus_framefmt *mf = &format->format;
++	const struct hm5065_pixfmt *pixfmt;
++	int ret = 0;
++
++	if (format->pad != 0)
++		return -EINVAL;
++
++	/* check if we support requested mbus fmt */
++	pixfmt = hm5065_find_format(mf->code);
++	if (!pixfmt)
++		pixfmt = &hm5065_formats[0];
++
++	mf->code = pixfmt->code;
++	mf->colorspace = pixfmt->colorspace;
++	mf->xfer_func = V4L2_XFER_FUNC_DEFAULT;
++	mf->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
++	mf->quantization = V4L2_QUANTIZATION_DEFAULT;
++	mf->field = V4L2_FIELD_NONE;
++
++	mutex_lock(&sensor->lock);
++
++	mf->width = clamp(mf->width, HM5065_CAPTURE_WIDTH_MIN,
++			  HM5065_SENSOR_WIDTH);
++	mf->height = clamp(mf->height, HM5065_CAPTURE_HEIGHT_MIN,
++			  HM5065_SENSOR_HEIGHT);
++
++	if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
++		struct v4l2_mbus_framefmt *try_mf;
++
++		try_mf = v4l2_subdev_state_get_format(sd_state, format->pad);
++		*try_mf = *mf;
++		goto out;
++	}
++
++	if (sensor->streaming) {
++		ret = -EBUSY;
++		goto out;
++	}
++
++	sensor->fmt = *mf;
++	sensor->pending_mode_change = true;
++out:
++	mutex_unlock(&sensor->lock);
++	return ret;
++}
++
++/* }}} */
++/* {{{ Core Ops */
++
++static void hm5065_chip_enable(struct hm5065_dev *sensor, bool enable)
++{
++	gpiod_set_value(sensor->enable_gpio, enable ? 1 : 0);
++	gpiod_set_value(sensor->reset_gpio, enable ? 0 : 1);
++}
++
++static int hm5065_configure(struct hm5065_dev *sensor)
++{
++	int ret;
++	u16 device_id;
++	const struct hm5065_clk_lut *lut;
++	unsigned long xclk_freq;
++
++	ret = hm5065_read16(sensor, HM5065_REG_DEVICE_ID, &device_id);
++	if (ret)
++		return ret;
++
++	if (device_id != HM5065_REG_DEVICE_ID_VALUE) {
++		dev_err(&sensor->i2c_client->dev,
++			"unsupported device id: 0x%04x\n",
++			(unsigned int)device_id);
++		return -EINVAL;
++	}
++
++	xclk_freq = clk_get_rate(sensor->xclk);
++	lut = hm5065_find_clk_lut(xclk_freq);
++	if (!lut) {
++		dev_err(&sensor->i2c_client->dev,
++			"xclk frequency out of range: %lu Hz\n", xclk_freq);
++		return -EINVAL;
++	}
++
++	ret = hm5065_write(sensor, HM5065_REG_EXCLOCKLUT, lut->lut_id);
++	if (ret)
++		return ret;
++
++	ret = hm5065_load_firmware(sensor, HM5065_AF_FIRMWARE);
++	if (ret < 0)
++		return ret;
++
++	if (ret == 0) /* ret == 1 means firmware file missing */
++		mdelay(200);
++
++	ret = hm5065_load_firmware(sensor, HM5065_FIRMWARE_PARAMETERS);
++	if (ret < 0)
++		return ret;
++
++	if (sensor->ep.bus_type == V4L2_MBUS_BT656) {
++		ret = hm5065_write(sensor, HM5065_REG_BUS_CONFIG,
++				   HM5065_REG_BUS_CONFIG_BT656);
++	} else {
++		ret = hm5065_write(sensor, HM5065_REG_BUS_CONFIG,
++				   HM5065_REG_BUS_CONFIG_PARALLEL_HH_VL);
++	}
++
++	return ret;
++}
++
++static int hm5065_set_power(struct hm5065_dev *sensor, bool on)
++{
++	int ret = 0;
++
++	if (on) {
++		ret = regulator_bulk_enable(HM5065_NUM_SUPPLIES,
++					    sensor->supplies);
++		if (ret)
++			return ret;
++
++		ret = clk_prepare_enable(sensor->xclk);
++		if (ret)
++			goto power_off;
++
++		ret = clk_set_rate(sensor->xclk, 24000000);
++		if (ret)
++			goto xclk_off;
++
++		usleep_range(1000, 2000);
++		hm5065_chip_enable(sensor, false);
++		usleep_range(1000, 2000);
++		hm5065_chip_enable(sensor, true);
++		usleep_range(50000, 70000);
++
++		ret = hm5065_configure(sensor);
++		if (ret)
++			goto xclk_off;
++
++		ret = hm5065_setup_mode(sensor);
++		if (ret)
++			goto xclk_off;
++
++		return 0;
++	}
++
++xclk_off:
++	clk_disable_unprepare(sensor->xclk);
++power_off:
++	hm5065_chip_enable(sensor, false);
++	regulator_bulk_disable(HM5065_NUM_SUPPLIES, sensor->supplies);
++	msleep(100);
++	return ret;
++}
++
++static int hm5065_s_power(struct v4l2_subdev *sd, int on)
++{
++	struct hm5065_dev *sensor = to_hm5065_dev(sd);
++	bool power_up, power_down;
++	int ret = 0;
++
++	mutex_lock(&sensor->lock);
++
++	power_up = on && !sensor->powered;
++	power_down = !on && sensor->powered;
++
++	if (power_up || power_down) {
++		ret = hm5065_set_power(sensor, power_up);
++		if (!ret)
++			sensor->powered = on;
++	}
++
++	mutex_unlock(&sensor->lock);
++
++	if (!ret && power_up) {
++		/* restore controls */
++		ret = v4l2_ctrl_handler_setup(&sensor->ctrls.handler);
++		if (ret)
++			hm5065_s_power(sd, 0);
++	}
++
++	return ret;
++}
++
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++static int hm5065_g_register(struct v4l2_subdev *sd,
++			     struct v4l2_dbg_register *reg)
++{
++	struct hm5065_dev *sensor = to_hm5065_dev(sd);
++	int ret;
++	u8 val = 0;
++
++	if (reg->reg > 0xffff)
++		return -EINVAL;
++
++	reg->size = 1;
++
++	mutex_lock(&sensor->lock);
++	ret = hm5065_read(sensor, reg->reg, &val);
++	mutex_unlock(&sensor->lock);
++	if (ret)
++		return -EIO;
++
++	reg->val = val;
++	return 0;
++}
++
++static int hm5065_s_register(struct v4l2_subdev *sd,
++			     const struct v4l2_dbg_register *reg)
++{
++	struct hm5065_dev *sensor = to_hm5065_dev(sd);
++	int ret;
++
++	if (reg->reg > 0xffff || reg->val > 0xff)
++		return -EINVAL;
++
++	mutex_lock(&sensor->lock);
++	ret = hm5065_write(sensor, reg->reg, reg->val);
++	mutex_unlock(&sensor->lock);
++
++	return ret;
++}
++#endif
++
++/* }}} */
++
++static const struct v4l2_subdev_core_ops hm5065_core_ops = {
++	.s_power = hm5065_s_power,
++#ifdef CONFIG_VIDEO_ADV_DEBUG
++	.g_register = hm5065_g_register,
++	.s_register = hm5065_s_register,
++#endif
++};
++
++static const struct v4l2_subdev_pad_ops hm5065_pad_ops = {
++	.enum_mbus_code = hm5065_enum_mbus_code,
++	.enum_frame_size = hm5065_enum_frame_size,
++	.enum_frame_interval = hm5065_enum_frame_interval,
++	.get_fmt = hm5065_get_fmt,
++	.set_fmt = hm5065_set_fmt,
++	.get_frame_interval = hm5065_get_frame_interval,
++	.set_frame_interval = hm5065_set_frame_interval,
++};
++
++static const struct v4l2_subdev_video_ops hm5065_video_ops = {
++	.s_stream = hm5065_s_stream,
++};
++
++static const struct v4l2_subdev_ops hm5065_subdev_ops = {
++	.core = &hm5065_core_ops,
++	.pad = &hm5065_pad_ops,
++	.video = &hm5065_video_ops,
++};
++
++static int hm5065_get_regulators(struct hm5065_dev *sensor)
++{
++	int i;
++
++	for (i = 0; i < HM5065_NUM_SUPPLIES; i++)
++		sensor->supplies[i].supply = hm5065_supply_name[i];
++
++	return devm_regulator_bulk_get(&sensor->i2c_client->dev,
++				       HM5065_NUM_SUPPLIES,
++				       sensor->supplies);
++}
++
++#define HM5065_PARALLEL_SUPPORT_FLAGS \
++	(V4L2_MBUS_HSYNC_ACTIVE_LOW | V4L2_MBUS_VSYNC_ACTIVE_HIGH | \
++	 V4L2_MBUS_PCLK_SAMPLE_FALLING | V4L2_MBUS_DATA_ACTIVE_HIGH)
++
++static int hm5065_probe(struct i2c_client *client)
++{
++	struct device *dev = &client->dev;
++	struct fwnode_handle *endpoint;
++	struct hm5065_dev *sensor;
++	int ret;
++
++	sensor = devm_kzalloc(dev, sizeof(*sensor), GFP_KERNEL);
++	if (!sensor)
++		return -ENOMEM;
++
++	sensor->i2c_client = client;
++
++	sensor->fmt.code = hm5065_formats[0].code;
++	sensor->fmt.width = 1280;
++	sensor->fmt.height = 720;
++	sensor->fmt.field = V4L2_FIELD_NONE;
++	sensor->frame_interval.numerator = 1;
++	sensor->frame_interval.denominator = 15;
++	sensor->pending_mode_change = true;
++
++	endpoint = fwnode_graph_get_next_endpoint(
++		of_fwnode_handle(client->dev.of_node), NULL);
++	if (!endpoint) {
++		dev_err(dev, "endpoint node not found\n");
++		return -EINVAL;
++	}
++
++	ret = v4l2_fwnode_endpoint_parse(endpoint, &sensor->ep);
++	fwnode_handle_put(endpoint);
++	if (ret) {
++		dev_err(dev, "could not parse endpoint\n");
++		return ret;
++	}
++
++	/*
++	 * We don't know how to configure the camera for any other parallel
++	 * mode, yet.
++	 */
++	if (sensor->ep.bus_type != V4L2_MBUS_BT656 &&
++	    !(sensor->ep.bus_type == V4L2_MBUS_PARALLEL &&
++	      (sensor->ep.bus.parallel.flags & HM5065_PARALLEL_SUPPORT_FLAGS) ==
++	      HM5065_PARALLEL_SUPPORT_FLAGS)) {
++		dev_err(dev, "unsupported bus configuration %d/%08x\n",
++			sensor->ep.bus_type, sensor->ep.bus.parallel.flags);
++		return -EINVAL;
++	}
++
++	/* get system clock (xclk) */
++	sensor->xclk = devm_clk_get(dev, "xclk");
++	if (IS_ERR(sensor->xclk)) {
++		dev_err(dev, "failed to get xclk\n");
++		return PTR_ERR(sensor->xclk);
++	}
++
++	sensor->enable_gpio = devm_gpiod_get_optional(dev, "enable",
++							  GPIOD_OUT_LOW);
++	sensor->reset_gpio = devm_gpiod_get_optional(dev, "reset",
++						     GPIOD_OUT_HIGH);
++
++	if (!sensor->enable_gpio && !sensor->reset_gpio) {
++		dev_err(dev,
++			"either chip enable or reset pin must be configured\n");
++		return ret;
++	}
++
++	v4l2_i2c_subdev_init(&sensor->sd, client, &hm5065_subdev_ops);
++
++	sensor->sd.flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
++	sensor->pad.flags = MEDIA_PAD_FL_SOURCE;
++	sensor->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
++	ret = media_entity_pads_init(&sensor->sd.entity, 1, &sensor->pad);
++	if (ret)
++		return ret;
++
++	ret = hm5065_get_regulators(sensor);
++	if (ret)
++		return ret;
++
++	mutex_init(&sensor->lock);
++
++	ret = hm5065_init_controls(sensor);
++	if (ret)
++		goto entity_cleanup;
++
++	ret = v4l2_async_register_subdev(&sensor->sd);
++	if (ret)
++		goto free_ctrls;
++
++	return 0;
++
++free_ctrls:
++	v4l2_ctrl_handler_free(&sensor->ctrls.handler);
++entity_cleanup:
++	mutex_destroy(&sensor->lock);
++	media_entity_cleanup(&sensor->sd.entity);
++	return ret;
++}
++
++static void hm5065_remove(struct i2c_client *client)
++{
++	struct v4l2_subdev *sd = i2c_get_clientdata(client);
++	struct hm5065_dev *sensor = to_hm5065_dev(sd);
++
++	v4l2_async_unregister_subdev(&sensor->sd);
++	mutex_destroy(&sensor->lock);
++	media_entity_cleanup(&sensor->sd.entity);
++	v4l2_ctrl_handler_free(&sensor->ctrls.handler);
++}
++
++static const struct i2c_device_id hm5065_id[] = {
++	{"hm5065", 0},
++	{ /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(i2c, hm5065_id);
++
++static const struct of_device_id hm5065_dt_ids[] = {
++	{ .compatible = "himax,hm5065" },
++	{ /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, hm5065_dt_ids);
++
++static struct i2c_driver hm5065_i2c_driver = {
++	.driver = {
++		.name  = "hm5065",
++		.of_match_table	= hm5065_dt_ids,
++	},
++	.id_table = hm5065_id,
++	.probe    = hm5065_probe,
++	.remove   = hm5065_remove,
++};
++
++module_i2c_driver(hm5065_i2c_driver);
++
++MODULE_AUTHOR("Ondrej Jirman <megi@xff.cz>");
++MODULE_DESCRIPTION("HM5065 Camera Subdev Driver");
++MODULE_LICENSE("GPL");
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/media-i2c-gc2145-Move-upstream-driver-out-of-the-way.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/media-i2c-gc2145-Move-upstream-driver-out-of-the-way.patch
new file mode 100644
index 000000000000..c808ad0e6693
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/media-i2c-gc2145-Move-upstream-driver-out-of-the-way.patch
@@ -0,0 +1,52 @@
+From 430f13bc72248989cdf797c828aff616164e4ebf Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sat, 13 Jan 2024 21:00:27 +0100
+Subject: media: i2c: gc2145: Move upstream driver out of the way
+
+Upstream only implements MIPI CSI, but we already have a driver
+with parallel bus support.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/media/i2c/Kconfig                     | 4 ++--
+ drivers/media/i2c/Makefile                    | 2 +-
+ drivers/media/i2c/{gc2145.c => gc2145-mipi.c} | 0
+ 3 files changed, 3 insertions(+), 3 deletions(-)
+ rename drivers/media/i2c/{gc2145.c => gc2145-mipi.c} (100%)
+
+diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig
+index e7da18f3da3c..43be07cc5b37 100644
+--- a/drivers/media/i2c/Kconfig
++++ b/drivers/media/i2c/Kconfig
+@@ -90,9 +90,9 @@ config VIDEO_GC08A3
+ 	  To compile this driver as a module, choose M here: the
+ 	  module will be called gc08a3.
+ 
+-config VIDEO_GC2145
++config VIDEO_GC2145_MIPI
+ 	select V4L2_CCI_I2C
+-	tristate "GalaxyCore GC2145 sensor support"
++	tristate "GalaxyCore GC2145 sensor support - MIPI variant"
+ 	help
+ 	  This is a V4L2 sensor-level driver for GalaxyCore GC2145
+ 	  2 Mpixel camera.
+diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile
+index b429d9f2e982..08bd346db54e 100644
+--- a/drivers/media/i2c/Makefile
++++ b/drivers/media/i2c/Makefile
+@@ -40,7 +40,7 @@ obj-$(CONFIG_VIDEO_ET8EK8) += et8ek8/
+ obj-$(CONFIG_VIDEO_GC0308) += gc0308.o
+ obj-$(CONFIG_VIDEO_GC05A2) += gc05a2.o
+ obj-$(CONFIG_VIDEO_GC08A3) += gc08a3.o
+-obj-$(CONFIG_VIDEO_GC2145) += gc2145.o
++obj-$(CONFIG_VIDEO_GC2145_MIPI) += gc2145-mipi.o
+ obj-$(CONFIG_VIDEO_HI556) += hi556.o
+ obj-$(CONFIG_VIDEO_HI846) += hi846.o
+ obj-$(CONFIG_VIDEO_HI847) += hi847.o
+diff --git a/drivers/media/i2c/gc2145.c b/drivers/media/i2c/gc2145-mipi.c
+similarity index 100%
+rename from drivers/media/i2c/gc2145.c
+rename to drivers/media/i2c/gc2145-mipi.c
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/media-i2c-gc2145-Parse-and-register-properties.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/media-i2c-gc2145-Parse-and-register-properties.patch
new file mode 100644
index 000000000000..3c2e227a68ca
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/media-i2c-gc2145-Parse-and-register-properties.patch
@@ -0,0 +1,43 @@
+From 4e13c92260d7cce43f7278488993cf4ed4b4c591 Mon Sep 17 00:00:00 2001
+From: Robert Mader <robert.mader@collabora.com>
+Date: Mon, 6 May 2024 16:36:05 -0700
+Subject: media: i2c: gc2145: Parse and register properties
+
+In order to propagate V4L2_CID_CAMERA_SENSOR_ROTATION and
+V4L2_CID_CAMERA_ORIENTATION values from the DT to userspace.
+
+Signed-off-by: Robert Mader <robert.mader@collabora.com>
+---
+ drivers/media/i2c/gc2145.c | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/drivers/media/i2c/gc2145.c b/drivers/media/i2c/gc2145.c
+index b505b3f07387..d80e457f275b 100644
+--- a/drivers/media/i2c/gc2145.c
++++ b/drivers/media/i2c/gc2145.c
+@@ -1272,6 +1272,7 @@ static int gc2145_init_controls(struct gc2145_dev *sensor)
+ 	const struct v4l2_ctrl_ops *ops = &gc2145_ctrl_ops;
+ 	struct gc2145_ctrls *ctrls = &sensor->ctrls;
+ 	struct v4l2_ctrl_handler *hdl = &ctrls->handler;
++	struct v4l2_fwnode_device_properties props;
+ 	//u8 wb_max = 0;
+ 	//u64 wb_mask = 0;
+ 	//unsigned int i;
+@@ -1324,6 +1325,14 @@ static int gc2145_init_controls(struct gc2145_dev *sensor)
+ 	ctrls->vflip = v4l2_ctrl_new_std(hdl, ops,
+ 					 V4L2_CID_VFLIP, 0, 1, 1, 0);
+ 
++	ret = v4l2_fwnode_device_parse(&sensor->i2c_client->dev, &props);
++	if (ret)
++		goto free_ctrls;
++
++	ret = v4l2_ctrl_new_fwnode_properties(hdl, &gc2145_ctrl_ops,
++					      &props);
++	if (ret)
++		goto free_ctrls;
+ 
+ 	/* Test patterns */
+ 	ctrls->test_pattern =
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/media-ov5640-Add-read-only-property-for-vblank.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/media-ov5640-Add-read-only-property-for-vblank.patch
new file mode 100644
index 000000000000..c0c4296b5471
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/media-ov5640-Add-read-only-property-for-vblank.patch
@@ -0,0 +1,24 @@
+From 8f82ed74e5a0e9bc121429492cc09ff99b12aa9b Mon Sep 17 00:00:00 2001
+From: Adam Pigg <adam@piggz.co.uk>
+Date: Thu, 29 Dec 2022 11:10:41 +0000
+Subject: media: ov5640: Add read-only property for vblank
+
+---
+ drivers/media/i2c/ov5640.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/media/i2c/ov5640.c b/drivers/media/i2c/ov5640.c
+index 07e5af3073ec..5d69b74a5cd7 100644
+--- a/drivers/media/i2c/ov5640.c
++++ b/drivers/media/i2c/ov5640.c
+@@ -3846,6 +3846,7 @@ static int ov5640_init_controls(struct ov5640_dev *sensor)
+ 	ctrls->pixel_rate->flags |= V4L2_CTRL_FLAG_READ_ONLY;
+ 	ctrls->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
+ 	ctrls->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
++	ctrls->vblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
+ 	ctrls->gain->flags |= V4L2_CTRL_FLAG_VOLATILE;
+ 	ctrls->exposure->flags |= V4L2_CTRL_FLAG_VOLATILE;
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/media-ov5640-Don-t-powerup-the-sensor-during-driver-probe.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/media-ov5640-Don-t-powerup-the-sensor-during-driver-probe.patch
new file mode 100644
index 000000000000..3eda71ea0008
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/media-ov5640-Don-t-powerup-the-sensor-during-driver-probe.patch
@@ -0,0 +1,119 @@
+From 699b30b9278830c2ad7ae7331b3e6ee5016199da Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Wed, 8 Nov 2023 19:13:37 +0100
+Subject: media: ov5640: Don't powerup the sensor during driver probe
+
+It causes autofocus clicking during boot on some devices, and
+it's enough to do it when turning on the sensor power by media
+pipeline via s_power callback, later on.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/media/i2c/ov5640.c | 55 +++++++++-----------------------------
+ 1 file changed, 12 insertions(+), 43 deletions(-)
+
+diff --git a/drivers/media/i2c/ov5640.c b/drivers/media/i2c/ov5640.c
+index 78a24f58888c..0e98ed8b3e08 100644
+--- a/drivers/media/i2c/ov5640.c
++++ b/drivers/media/i2c/ov5640.c
+@@ -2497,6 +2497,7 @@ static void ov5640_powerup_sequence(struct ov5640_dev *sensor)
+ static int ov5640_set_power_on(struct ov5640_dev *sensor)
+ {
+ 	struct i2c_client *client = sensor->i2c_client;
++	u16 chip_id;
+ 	int ret;
+ 
+ 	ret = clk_prepare_enable(sensor->xclk);
+@@ -2520,6 +2521,13 @@ static int ov5640_set_power_on(struct ov5640_dev *sensor)
+ 	if (ret)
+ 		goto power_off;
+ 
++	ret = ov5640_read_reg16(sensor, OV5640_REG_CHIP_ID, &chip_id);
++	if (ret) {
++		dev_err(&client->dev, "%s: failed to read chip identifier\n",
++			__func__);
++		goto power_off;
++	}
++
+ 	return 0;
+ 
+ power_off:
+@@ -3841,28 +3849,6 @@ static int ov5640_get_regulators(struct ov5640_dev *sensor)
+ 				       sensor->supplies);
+ }
+ 
+-static int ov5640_check_chip_id(struct ov5640_dev *sensor)
+-{
+-	struct i2c_client *client = sensor->i2c_client;
+-	int ret = 0;
+-	u16 chip_id;
+-
+-	ret = ov5640_read_reg16(sensor, OV5640_REG_CHIP_ID, &chip_id);
+-	if (ret) {
+-		dev_err(&client->dev, "%s: failed to read chip identifier\n",
+-			__func__);
+-		return ret;
+-	}
+-
+-	if (chip_id != 0x5640) {
+-		dev_err(&client->dev, "%s: wrong chip identifier, expected 0x5640, got 0x%x\n",
+-			__func__, chip_id);
+-		return -ENXIO;
+-	}
+-
+-	return 0;
+-}
+-
+ static int ov5640_probe(struct i2c_client *client)
+ {
+ 	struct device *dev = &client->dev;
+@@ -3963,35 +3949,16 @@ static int ov5640_probe(struct i2c_client *client)
+ 	if (ret)
+ 		goto entity_cleanup;
+ 
+-	ret = ov5640_sensor_resume(dev);
+-	if (ret) {
+-		dev_err(dev, "failed to power on\n");
+-		goto free_ctrls;
+-	}
+-
+-	pm_runtime_set_active(dev);
+-	pm_runtime_get_noresume(dev);
+-	pm_runtime_enable(dev);
+-
+-	ret = ov5640_check_chip_id(sensor);
+-	if (ret)
+-		goto err_pm_runtime;
+-
+ 	ret = v4l2_async_register_subdev_sensor(&sensor->sd);
+ 	if (ret)
+-		goto err_pm_runtime;
++		goto free_ctrls;
+ 
++	pm_runtime_enable(dev);
+ 	pm_runtime_set_autosuspend_delay(dev, 1000);
+ 	pm_runtime_use_autosuspend(dev);
+-	pm_runtime_mark_last_busy(dev);
+-	pm_runtime_put_autosuspend(dev);
+ 
+ 	return 0;
+ 
+-err_pm_runtime:
+-	pm_runtime_put_noidle(dev);
+-	pm_runtime_disable(dev);
+-	ov5640_sensor_suspend(dev);
+ free_ctrls:
+ 	v4l2_ctrl_handler_free(&sensor->ctrls.handler);
+ entity_cleanup:
+@@ -4006,6 +3973,8 @@ static void ov5640_remove(struct i2c_client *client)
+ 	struct ov5640_dev *sensor = to_ov5640_dev(sd);
+ 	struct device *dev = &client->dev;
+ 
++	pm_runtime_dont_use_autosuspend(dev);
++
+ 	pm_runtime_disable(dev);
+ 	if (!pm_runtime_status_suspended(dev))
+ 		ov5640_sensor_suspend(dev);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/media-ov5640-Experiment-Try-to-disable-denoising-sharpening.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/media-ov5640-Experiment-Try-to-disable-denoising-sharpening.patch
new file mode 100644
index 000000000000..05abfd3fe916
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/media-ov5640-Experiment-Try-to-disable-denoising-sharpening.patch
@@ -0,0 +1,50 @@
+From 3fcdfc009b409cd64bb7926fecab2633486caf3b Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Fri, 24 Jan 2020 18:25:59 +0100
+Subject: media: ov5640: [Experiment] Try to disable denoising/sharpening
+
+Not sure how this works exactly. More tests are needed.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/media/i2c/ov5640.c | 17 +++++++++++++++++
+ 1 file changed, 17 insertions(+)
+
+diff --git a/drivers/media/i2c/ov5640.c b/drivers/media/i2c/ov5640.c
+index 0dae0438aa80..e408946782c6 100644
+--- a/drivers/media/i2c/ov5640.c
++++ b/drivers/media/i2c/ov5640.c
+@@ -2327,6 +2327,7 @@ static int ov5640_set_mode(struct ov5640_dev *sensor)
+ 	bool auto_gain = sensor->ctrls.auto_gain->val == 1;
+ 	bool auto_exp =  sensor->ctrls.auto_exp->val == V4L2_EXPOSURE_AUTO;
+ 	int ret;
++	u8 tmp;
+ 
+ 	dn_mode = mode->dn_mode;
+ 	orig_dn_mode = orig_mode->dn_mode;
+@@ -2390,6 +2391,22 @@ static int ov5640_set_mode(struct ov5640_dev *sensor)
+ 	if (ret < 0)
+ 		return ret;
+ 
++	ret = ov5640_read_reg(sensor, 0x5308, &tmp);
++	if (ret)
++		return ret;
++
++	ret = ov5640_write_reg(sensor, 0x5308, tmp | 0x10 | 0x40);
++	if (ret)
++		return ret;
++
++	ret = ov5640_write_reg(sensor, 0x5306, 0);
++	if (ret)
++		return ret;
++
++	ret = ov5640_write_reg(sensor, 0x5302, 0);
++	if (ret)
++		return ret;
++
+ 	sensor->pending_mode_change = false;
+ 	sensor->last_mode = mode;
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/media-ov5640-Fix-focus-commands-blocking-until-complete.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/media-ov5640-Fix-focus-commands-blocking-until-complete.patch
new file mode 100644
index 000000000000..e92f0af9181f
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/media-ov5640-Fix-focus-commands-blocking-until-complete.patch
@@ -0,0 +1,113 @@
+From eb9964740528f9aa25ee2c7591e92d3ed8f296a3 Mon Sep 17 00:00:00 2001
+From: Benjamin Schaaf <ben.schaaf@gmail.com>
+Date: Mon, 22 Nov 2021 23:38:26 +1100
+Subject: media: ov5640: Fix focus commands blocking until complete
+
+Previously setting the focus controls would block until the sensor
+completed the focus routine.
+---
+ drivers/media/i2c/ov5640.c | 67 ++++++++++----------------------------
+ 1 file changed, 18 insertions(+), 49 deletions(-)
+
+diff --git a/drivers/media/i2c/ov5640.c b/drivers/media/i2c/ov5640.c
+index 93cfd1b51713..07e5af3073ec 100644
+--- a/drivers/media/i2c/ov5640.c
++++ b/drivers/media/i2c/ov5640.c
+@@ -2643,6 +2643,19 @@ static int ov5640_copy_fw_to_device(struct ov5640_dev *sensor,
+ 	return -ETIMEDOUT;
+ }
+ 
++static int ov5640_fw_command(struct ov5640_dev *sensor, int command)
++{
++	int ret;
++
++	ret = ov5640_write_reg(sensor, OV5640_REG_FW_CMD_MAIN, command);
++	if(ret)
++		return ret;
++
++	msleep(5);
++
++	return 0;
++}
++
+ static int ov5640_af_init(struct ov5640_dev *sensor)
+ {
+ 	struct i2c_client *client = sensor->i2c_client;
+@@ -2680,6 +2693,11 @@ static int ov5640_af_init(struct ov5640_dev *sensor)
+ 
+ 	// Set lens focus driver on
+ 	ret = ov5640_write_reg(sensor, OV5640_REG_VCM_CONTROL4, 0x3f);
++	if (ret)
++		return ret;
++
++	// Set the default focus zone
++	ret = ov5640_fw_command(sensor, OV5640_FW_CMD_ZONE_CONFIG);
+ 	if (ret)
+ 		return ret;
+ 	return ret;
+@@ -3304,35 +3322,6 @@ static int ov5640_set_framefmt(struct ov5640_dev *sensor,
+ 			      is_jpeg ? (BIT(5) | BIT(3)) : 0);
+ }
+ 
+-static int ov5640_fw_command(struct ov5640_dev *sensor, int command)
+-{
+-	u8 fw_ack;
+-	int i;
+-	int ret;
+-
+-	ret = ov5640_write_reg(sensor, OV5640_REG_FW_CMD_ACK, 0x01);
+-	if(ret)
+-		return ret;
+-	
+-	ret = ov5640_write_reg(sensor, OV5640_REG_FW_CMD_MAIN, command);
+-	if(ret)
+-		return ret;
+-
+-	for (i = 0; i < 100; i++) {
+-		ret = ov5640_read_reg(sensor, OV5640_REG_FW_CMD_ACK, &fw_ack);
+-		if (ret)
+-			return ret;
+-
+-		if (fw_ack == 0){
+-			return ret;
+-		}
+-
+-		msleep(50);
+-	}
+-	return -ETIMEDOUT;
+-}
+-
+-
+ /*
+  * Sensor Controls.
+  */
+@@ -3468,26 +3457,6 @@ static int ov5640_set_ctrl_focus(struct ov5640_dev *sensor, int command)
+ 		return 0;
+ 	}
+ 
+-	if (command == OV5640_FW_CMD_RELEASE_FOCUS) {
+-		dev_dbg(&client->dev, "%s: Releasing autofocus\n",
+-			__func__);
+-		return ov5640_fw_command(sensor, OV5640_FW_CMD_RELEASE_FOCUS);
+-	}
+-	
+-	// Restart zone config
+-	ret = ov5640_fw_command(sensor, OV5640_FW_CMD_ZONE_CONFIG);
+-	if (ret)
+-		return ret;
+-
+-	// Set default focus zones
+-	ret = ov5640_fw_command(sensor, OV5640_FW_CMD_DEFAULT_ZONES);
+-	if (ret)
+-		return ret;
+-
+-	dev_dbg(&client->dev, "%s: Triggering autofocus\n",
+-		__func__);
+-
+-	// Start focussing
+ 	return ov5640_fw_command(sensor, command);
+ }
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/media-ov5640-Implement-autofocus.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/media-ov5640-Implement-autofocus.patch
new file mode 100644
index 000000000000..ddfb542dc994
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/media-ov5640-Implement-autofocus.patch
@@ -0,0 +1,395 @@
+From e4f5aafa6a9584e382e62fe88386a58efc19ac29 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sun, 7 Aug 2022 15:17:09 +0200
+Subject: media: ov5640: Implement autofocus
+
+The autofocus functionality needs a firmware blob loaded into the
+internal microcontroller.
+
+V4L2 doesn't have an api to control all autofocus functionality, but
+this at least makes it possible to focus on the center of the sensor.
+
+Signed-off-by: Martijn Braam <martijn@brixit.nl>
+---
+ drivers/media/i2c/ov5640.c | 279 +++++++++++++++++++++++++++++++++++++
+ 1 file changed, 279 insertions(+)
+
+diff --git a/drivers/media/i2c/ov5640.c b/drivers/media/i2c/ov5640.c
+index 0ff3a2c51d4d..83206c5b649a 100644
+--- a/drivers/media/i2c/ov5640.c
++++ b/drivers/media/i2c/ov5640.c
+@@ -9,6 +9,7 @@
+ #include <linux/clkdev.h>
+ #include <linux/ctype.h>
+ #include <linux/delay.h>
++#include <linux/firmware.h>
+ #include <linux/device.h>
+ #include <linux/gpio/consumer.h>
+ #include <linux/i2c.h>
+@@ -119,6 +120,38 @@
+ #define OV5640_REG_SDE_CTRL5		0x5585
+ #define OV5640_REG_AVG_READOUT		0x56a1
+ 
++/* autofocus registers */
++
++#define OV5640_REG_SYS_RESET00		0x3000
++#define OV5640_REG_SYS_RESET01		0x3001
++#define OV5640_REG_SYS_CLOCK_ENABLE00	0x3004
++#define OV5640_REG_SYS_CLOCK_ENABLE01	0x3005
++
++#define OV5640_REG_FW_CMD_MAIN		0x3022
++#define OV5640_REG_FW_CMD_ACK		0x3023
++#define OV5640_REG_FW_CMD_PARA0		0x3024
++#define OV5640_REG_FW_CMD_PARA1		0x3025
++#define OV5640_REG_FW_CMD_PARA2		0x3026
++#define OV5640_REG_FW_CMD_PARA3		0x3027
++#define OV5640_REG_FW_CMD_PARA4		0x3028
++#define OV5640_REG_FW_STATUS		0x3029
++
++#define OV5640_REG_VCM_CONTROL4		0x3606
++#define OV5640_REG_FIRMWARE_BASE	0x8000
++
++#define OV5640_FW_STATUS_S_FIRMWARE	0x7f
++#define OV5640_FW_STATUS_S_STARTUP	0x7e
++#define OV5640_FW_STATUS_S_IDLE		0x70
++#define OV5640_FW_STATUS_S_FOCUSING	0x00
++#define OV5640_FW_STATUS_S_FOCUSED	0x10
++
++#define OV5640_FW_CMD_TRIGGER_FOCUS	0x03
++#define OV5640_FW_CMD_CONTINUOUS_FOCUS	0x04
++#define OV5640_FW_CMD_GET_FOCUS_RESULT	0x07
++#define OV5640_FW_CMD_RELEASE_FOCUS	0x08
++#define OV5640_FW_CMD_ZONE_CONFIG	0x12
++#define OV5640_FW_CMD_DEFAULT_ZONES	0x80
++
+ enum ov5640_mode_id {
+ 	OV5640_MODE_QQVGA_160_120 = 0,
+ 	OV5640_MODE_QCIF_176_144,
+@@ -423,6 +456,12 @@ struct ov5640_ctrls {
+ 		struct v4l2_ctrl *auto_gain;
+ 		struct v4l2_ctrl *gain;
+ 	};
++	struct {
++		struct v4l2_ctrl *focus_auto;
++		struct v4l2_ctrl *af_start;
++		struct v4l2_ctrl *af_stop;
++		struct v4l2_ctrl *af_status;
++	};
+ 	struct v4l2_ctrl *brightness;
+ 	struct v4l2_ctrl *light_freq;
+ 	struct v4l2_ctrl *saturation;
+@@ -465,6 +504,8 @@ struct ov5640_dev {
+ 
+ 	bool pending_mode_change;
+ 	bool streaming;
++
++	bool af_initialized;
+ };
+ 
+ static inline struct ov5640_dev *to_ov5640_dev(struct v4l2_subdev *sd)
+@@ -2494,6 +2535,118 @@ static void ov5640_powerup_sequence(struct ov5640_dev *sensor)
+ 			 OV5640_REG_SYS_CTRL0_SW_PWDN);
+ }
+ 
++static int ov5640_copy_fw_to_device(struct ov5640_dev *sensor,
++					const struct firmware *fw)
++{
++	struct i2c_client *client = sensor->i2c_client;
++	const u8 *data = (const u8 *)fw->data;
++	u8 fw_status;
++	int i;
++	int ret;
++
++	// Putting MCU in reset state
++	ret = ov5640_write_reg(sensor, OV5640_REG_SYS_RESET00, 0x20);
++	if (ret)
++		return ret;
++
++	// Write firmware
++	for (i = 0; i < fw->size / sizeof(u8); i++)
++		ov5640_write_reg(sensor,
++				OV5640_REG_FIRMWARE_BASE + i, 
++				data[i]);
++
++	// Reset MCU state
++	ov5640_write_reg(sensor, OV5640_REG_FW_CMD_MAIN, 0x00);
++	ov5640_write_reg(sensor, OV5640_REG_FW_CMD_ACK, 0x00);
++	ov5640_write_reg(sensor, OV5640_REG_FW_CMD_PARA0, 0x00);
++	ov5640_write_reg(sensor, OV5640_REG_FW_CMD_PARA1, 0x00);
++	ov5640_write_reg(sensor, OV5640_REG_FW_CMD_PARA2, 0x00);
++	ov5640_write_reg(sensor, OV5640_REG_FW_CMD_PARA3, 0x00);
++	ov5640_write_reg(sensor, OV5640_REG_FW_CMD_PARA4, 0x00);
++	ov5640_write_reg(sensor, OV5640_REG_FW_STATUS, 0x7f);
++
++	// Start AF MCU
++	ret = ov5640_write_reg(sensor, OV5640_REG_SYS_RESET00, 0x00);
++	if (ret)
++		return ret;
++
++	dev_info(&client->dev, "firmware upload success\n");
++
++	// Wait for firmware to be ready
++	for (i = 0; i < 5; i++) {
++		ret = ov5640_read_reg(sensor, OV5640_REG_FW_STATUS, &fw_status);
++		if (fw_status == OV5640_FW_STATUS_S_IDLE) {
++			dev_info(&client->dev, "fw started after %d ms\n", i * 50);
++			return ret;
++		}
++		msleep(50);
++	}
++	dev_err(&client->dev, "uploaded firmware didn't start, got to 0x%x, retrying...\n", fw_status);
++
++	// Putting MCU in reset state
++	ret = ov5640_write_reg(sensor, OV5640_REG_SYS_RESET00, 0x20);
++	if (ret)
++		return ret;
++	// Start AF MCU
++	ret = ov5640_write_reg(sensor, OV5640_REG_SYS_RESET00, 0x00);
++	if (ret)
++		return ret;
++	// Wait for firmware to be ready
++	for (i = 0; i < 5; i++) {
++		ret = ov5640_read_reg(sensor, OV5640_REG_FW_STATUS, &fw_status);
++		if (fw_status == OV5640_FW_STATUS_S_IDLE) {
++			dev_info(&client->dev, "fw started after %d ms\n", i * 50);
++			return ret;
++		}
++		msleep(50);
++	}
++	dev_err(&client->dev, "uploaded firmware didn't start, got to 0x%x\n", fw_status);
++	return -ETIMEDOUT;
++}
++
++static int ov5640_af_init(struct ov5640_dev *sensor)
++{
++	struct i2c_client *client = sensor->i2c_client;
++	const char* fwname = "ov5640_af.bin";
++	const struct firmware *fw;
++	int ret;
++
++	if (sensor->af_initialized) {
++		return 0;
++	}
++
++	if (firmware_request_nowarn(&fw, fwname, &client->dev) == 0) {
++		ret = ov5640_copy_fw_to_device(sensor, fw);
++		if (ret == 0)
++			sensor->af_initialized = 1;
++	} else {
++		dev_warn(&client->dev, "%s: no autofocus firmware available (%s)\n",
++			__func__, fwname);
++		ret = -1;
++	}
++	release_firmware(fw);
++
++	if (ret)
++		return ret;
++
++	// Enable AF systems
++	ret = ov5640_mod_reg(sensor, OV5640_REG_SYS_CLOCK_ENABLE00,
++			     (BIT(6) | BIT(5)), (BIT(6) | BIT(5)));
++	if (ret)
++		return ret;
++	ret = ov5640_mod_reg(sensor, OV5640_REG_SYS_CLOCK_ENABLE01,
++			     BIT(6), BIT(6));
++	if (ret)
++		return ret;
++
++	// Set lens focus driver on
++	ov5640_write_reg(sensor, OV5640_REG_VCM_CONTROL4, 0x3f);
++	if (ret)
++		return ret;
++
++	return ret;
++}
++
+ static int ov5640_set_power_on(struct ov5640_dev *sensor)
+ {
+ 	struct i2c_client *client = sensor->i2c_client;
+@@ -2515,8 +2668,11 @@ static int ov5640_set_power_on(struct ov5640_dev *sensor)
+ 		goto xclk_off;
+ 	}
+ 
++	sensor->af_initialized = 0;
++
+ 	ov5640_powerup_sequence(sensor);
+ 
++
+ 	ret = ov5640_init_slave_id(sensor);
+ 	if (ret)
+ 		goto power_off;
+@@ -3110,6 +3266,35 @@ static int ov5640_set_framefmt(struct ov5640_dev *sensor,
+ 			      is_jpeg ? (BIT(5) | BIT(3)) : 0);
+ }
+ 
++static int ov5640_fw_command(struct ov5640_dev *sensor, int command)
++{
++	u8 fw_ack;
++	int i;
++	int ret;
++
++	ret = ov5640_write_reg(sensor, OV5640_REG_FW_CMD_ACK, 0x01);
++	if(ret)
++		return ret;
++	
++	ret = ov5640_write_reg(sensor, OV5640_REG_FW_CMD_MAIN, command);
++	if(ret)
++		return ret;
++
++	for (i = 0; i < 100; i++) {
++		ret = ov5640_read_reg(sensor, OV5640_REG_FW_CMD_ACK, &fw_ack);
++		if (ret)
++			return ret;
++
++		if (fw_ack == 0){
++			return ret;
++		}
++
++		msleep(50);
++	}
++	return -ETIMEDOUT;
++}
++
++
+ /*
+  * Sensor Controls.
+  */
+@@ -3226,6 +3411,41 @@ static int ov5640_set_ctrl_exposure(struct ov5640_dev *sensor,
+ 	return ret;
+ }
+ 
++static int ov5640_set_ctrl_focus(struct ov5640_dev *sensor, int command)
++{
++	struct i2c_client *client = sensor->i2c_client;
++	int ret;
++
++	ret = ov5640_af_init(sensor);
++	if (ret) {
++		dev_err(&client->dev, "%s: no autofocus firmware loaded\n",
++			__func__);
++		return 0;
++	}
++
++	if (command == OV5640_FW_CMD_RELEASE_FOCUS) {
++		dev_dbg(&client->dev, "%s: Releasing autofocus\n",
++			__func__);
++		return ov5640_fw_command(sensor, OV5640_FW_CMD_RELEASE_FOCUS);
++	}
++	
++	// Restart zone config
++	ret = ov5640_fw_command(sensor, OV5640_FW_CMD_ZONE_CONFIG);
++	if (ret)
++		return ret;
++
++	// Set default focus zones
++	ret = ov5640_fw_command(sensor, OV5640_FW_CMD_DEFAULT_ZONES);
++	if (ret)
++		return ret;
++
++	dev_dbg(&client->dev, "%s: Triggering autofocus\n",
++		__func__);
++
++	// Start focussing
++	return ov5640_fw_command(sensor, command);
++}
++
+ static int ov5640_set_ctrl_gain(struct ov5640_dev *sensor, bool auto_gain)
+ {
+ 	struct ov5640_ctrls *ctrls = &sensor->ctrls;
+@@ -3341,6 +3561,32 @@ static int ov5640_set_ctrl_vblank(struct ov5640_dev *sensor, int value)
+ 				  mode->height + value);
+ }
+ 
++static int ov5640_get_af_status(struct ov5640_dev *sensor)
++{
++	u8 fw_status;
++	int ret;
++
++	ret = ov5640_read_reg(sensor, OV5640_REG_FW_STATUS, &fw_status);
++	if (ret)
++		return ret;
++
++	switch (fw_status) {
++		case OV5640_FW_STATUS_S_FIRMWARE:
++		case OV5640_FW_STATUS_S_STARTUP:
++			return V4L2_AUTO_FOCUS_STATUS_FAILED;
++			break;
++		case OV5640_FW_STATUS_S_IDLE:
++			return V4L2_AUTO_FOCUS_STATUS_IDLE;
++			break;
++		case OV5640_FW_STATUS_S_FOCUSED:
++			return V4L2_AUTO_FOCUS_STATUS_REACHED;
++			break;
++		default:
++			return V4L2_AUTO_FOCUS_STATUS_BUSY;
++			break;
++	}
++}
++
+ static int ov5640_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
+ {
+ 	struct v4l2_subdev *sd = ctrl_to_sd(ctrl);
+@@ -3365,6 +3611,12 @@ static int ov5640_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
+ 			return val;
+ 		sensor->ctrls.exposure->val = val;
+ 		break;
++	case V4L2_CID_FOCUS_AUTO:
++		val = ov5640_get_af_status(sensor);
++		if (val < 0)
++			return val;
++		sensor->ctrls.af_status->val = val;
++		break;
+ 	}
+ 
+ 	pm_runtime_mark_last_busy(&sensor->i2c_client->dev);
+@@ -3414,6 +3666,18 @@ static int ov5640_s_ctrl(struct v4l2_ctrl *ctrl)
+ 	case V4L2_CID_AUTO_WHITE_BALANCE:
+ 		ret = ov5640_set_ctrl_white_balance(sensor, ctrl->val);
+ 		break;
++	case V4L2_CID_FOCUS_AUTO:
++		if (ctrl->val)
++			ret = ov5640_set_ctrl_focus(sensor, OV5640_FW_CMD_CONTINUOUS_FOCUS);
++		else
++			ret = ov5640_set_ctrl_focus(sensor, OV5640_FW_CMD_RELEASE_FOCUS);
++		break;
++	case V4L2_CID_AUTO_FOCUS_START:
++		ret = ov5640_set_ctrl_focus(sensor, OV5640_FW_CMD_TRIGGER_FOCUS);
++		break;
++	case V4L2_CID_AUTO_FOCUS_STOP:
++		ret = ov5640_set_ctrl_focus(sensor, OV5640_FW_CMD_RELEASE_FOCUS);
++		break;
+ 	case V4L2_CID_HUE:
+ 		ret = ov5640_set_ctrl_hue(sensor, ctrl->val);
+ 		break;
+@@ -3514,6 +3778,20 @@ static int ov5640_init_controls(struct ov5640_dev *sensor)
+ 	ctrls->gain = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_ANALOGUE_GAIN,
+ 					0, 1023, 1, 0);
+ 
++	/* Autofocus */
++	ctrls->focus_auto = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_FOCUS_AUTO,
++					    0, 1, 1, 0);
++	ctrls->af_start = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_AUTO_FOCUS_START,
++					    0, 1, 1, 0);
++	ctrls->af_stop = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_AUTO_FOCUS_STOP,
++					   0, 1, 1, 0);
++	ctrls->af_status = v4l2_ctrl_new_std(hdl, ops,
++					     V4L2_CID_AUTO_FOCUS_STATUS, 0,
++					     (V4L2_AUTO_FOCUS_STATUS_BUSY |
++					      V4L2_AUTO_FOCUS_STATUS_REACHED |
++					      V4L2_AUTO_FOCUS_STATUS_FAILED),
++					     0, V4L2_AUTO_FOCUS_STATUS_IDLE);
++
+ 	ctrls->saturation = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_SATURATION,
+ 					      0, 255, 1, 64);
+ 	ctrls->hue = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_HUE,
+@@ -3560,6 +3838,7 @@ static int ov5640_init_controls(struct ov5640_dev *sensor)
+ 	v4l2_ctrl_auto_cluster(3, &ctrls->auto_wb, 0, false);
+ 	v4l2_ctrl_auto_cluster(2, &ctrls->auto_gain, 0, true);
+ 	v4l2_ctrl_auto_cluster(2, &ctrls->auto_exp, 1, true);
++	v4l2_ctrl_cluster(4, &ctrls->focus_auto);
+ 
+ 	sensor->sd.ctrl_handler = hdl;
+ 	return 0;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/media-ov5640-Improve-error-reporting.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/media-ov5640-Improve-error-reporting.patch
new file mode 100644
index 000000000000..3cd68e2c425b
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/media-ov5640-Improve-error-reporting.patch
@@ -0,0 +1,43 @@
+From bba2d0b661c0d2e89df60ea31e93307367407e75 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Fri, 22 Oct 2021 19:52:49 +0200
+Subject: media: ov5640: Improve error reporting
+
+Some probe errors are currently not reported. Report them properly.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/media/i2c/ov5640.c | 8 ++++++--
+ 1 file changed, 6 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/media/i2c/ov5640.c b/drivers/media/i2c/ov5640.c
+index 4e0803484fd4..0ff3a2c51d4d 100644
+--- a/drivers/media/i2c/ov5640.c
++++ b/drivers/media/i2c/ov5640.c
+@@ -3940,8 +3940,10 @@ static int ov5640_probe(struct i2c_client *client)
+ 		return ret;
+ 
+ 	ret = ov5640_get_regulators(sensor);
+-	if (ret)
++	if (ret) {
++		dev_err_probe(dev, ret, "Failed to get regulators\n");
+ 		goto entity_cleanup;
++	}
+ 
+ 	mutex_init(&sensor->lock);
+ 
+@@ -3950,8 +3952,10 @@ static int ov5640_probe(struct i2c_client *client)
+ 		goto entity_cleanup;
+ 
+ 	ret = v4l2_async_register_subdev_sensor(&sensor->sd);
+-	if (ret)
++	if (ret) {
++		dev_err_probe(dev, ret, "Failed to register sensor\n");
+ 		goto free_ctrls;
++	}
+ 
+ 	pm_runtime_enable(dev);
+ 	pm_runtime_set_autosuspend_delay(dev, 1000);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/media-ov5640-Improve-firmware-load-time.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/media-ov5640-Improve-firmware-load-time.patch
new file mode 100644
index 000000000000..d35a05c60315
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/media-ov5640-Improve-firmware-load-time.patch
@@ -0,0 +1,177 @@
+From 20eee5b2d15278056cfddaddebbe2870b368ea1e Mon Sep 17 00:00:00 2001
+From: Benjamin Schaaf <ben.schaaf@gmail.com>
+Date: Mon, 22 Nov 2021 23:38:26 +1100
+Subject: media: ov5640: Improve firmware load time
+
+Downloading the firmware can be done in groups to minimize i2c packets.
+The firmware status is set practically immediately upon successfully
+loading it, so there's no need for a long timeout or retry. The
+firmware can also not be loaded when the sensor isn't powered on, so
+don't bother trying.
+---
+ drivers/media/i2c/ov5640.c | 97 ++++++++++++++++++++++++++++----------
+ 1 file changed, 71 insertions(+), 26 deletions(-)
+
+diff --git a/drivers/media/i2c/ov5640.c b/drivers/media/i2c/ov5640.c
+index 83206c5b649a..93cfd1b51713 100644
+--- a/drivers/media/i2c/ov5640.c
++++ b/drivers/media/i2c/ov5640.c
+@@ -1232,6 +1232,8 @@ static int ov5640_write_reg(struct ov5640_dev *sensor, u16 reg, u8 val)
+ 	msg.buf = buf;
+ 	msg.len = sizeof(buf);
+ 
++	dev_dbg(&client->dev, "[wr %04x] <= %d\n", reg, val);
++
+ 	ret = i2c_transfer(client->adapter, &msg, 1);
+ 	if (ret < 0) {
+ 		dev_err(&client->dev, "%s: error: reg=%x, val=%x\n",
+@@ -1242,6 +1244,42 @@ static int ov5640_write_reg(struct ov5640_dev *sensor, u16 reg, u8 val)
+ 	return 0;
+ }
+ 
++static int ov5640_write_regs(struct ov5640_dev *sensor, u16 reg,
++			     const u8 *data, int data_size)
++{
++	struct i2c_client *client = sensor->i2c_client;
++	struct i2c_msg msg;
++	u8 buf[254 + 2];
++	int ret;
++
++	if (data_size > sizeof(buf) - 2) {
++		v4l2_err(&sensor->sd, "%s: oversized transfer (size=%d)\n",
++			 __func__, data_size);
++		return -EINVAL;
++	}
++
++	buf[0] = reg >> 8;
++	buf[1] = reg & 0xff;
++	memcpy(buf + 2, data, data_size);
++
++	msg.addr = client->addr;
++	msg.flags = client->flags;
++	msg.buf = buf;
++	msg.len = data_size + 2;
++
++	dev_dbg(&client->dev, "[wr %04x] <= %*ph\n", (u32)reg, data_size, data);
++
++	ret = i2c_transfer(client->adapter, &msg, 1);
++	if (ret < 0) {
++		v4l2_err(&sensor->sd,
++			 "%s: error %d: reg=%x, data=%*ph\n",
++			 __func__, ret, (u32)reg, data_size, data);
++		return ret;
++	}
++
++	return 0;
++}
++
+ static int ov5640_read_reg(struct ov5640_dev *sensor, u16 reg, u8 *val)
+ {
+ 	struct i2c_client *client = sensor->i2c_client;
+@@ -2543,6 +2581,7 @@ static int ov5640_copy_fw_to_device(struct ov5640_dev *sensor,
+ 	u8 fw_status;
+ 	int i;
+ 	int ret;
++	int num_groups, group_size = 254;
+ 
+ 	// Putting MCU in reset state
+ 	ret = ov5640_write_reg(sensor, OV5640_REG_SYS_RESET00, 0x20);
+@@ -2550,10 +2589,24 @@ static int ov5640_copy_fw_to_device(struct ov5640_dev *sensor,
+ 		return ret;
+ 
+ 	// Write firmware
+-	for (i = 0; i < fw->size / sizeof(u8); i++)
+-		ov5640_write_reg(sensor,
+-				OV5640_REG_FIRMWARE_BASE + i, 
+-				data[i]);
++	num_groups = fw->size / group_size;
++	for (i = 0; i < num_groups; i++) {
++		ret = ov5640_write_regs(sensor,
++					OV5640_REG_FIRMWARE_BASE + i * group_size,
++					data + i * group_size,
++					group_size);
++		if (ret)
++			return ret;
++	}
++
++	if (i * group_size < fw->size) {
++		ret = ov5640_write_regs(sensor,
++					OV5640_REG_FIRMWARE_BASE + i * group_size,
++					data + i * group_size,
++					fw->size - i * group_size);
++		if (ret)
++			return ret;
++	}
+ 
+ 	// Reset MCU state
+ 	ov5640_write_reg(sensor, OV5640_REG_FW_CMD_MAIN, 0x00);
+@@ -2575,31 +2628,17 @@ static int ov5640_copy_fw_to_device(struct ov5640_dev *sensor,
+ 	// Wait for firmware to be ready
+ 	for (i = 0; i < 5; i++) {
+ 		ret = ov5640_read_reg(sensor, OV5640_REG_FW_STATUS, &fw_status);
+-		if (fw_status == OV5640_FW_STATUS_S_IDLE) {
+-			dev_info(&client->dev, "fw started after %d ms\n", i * 50);
++		if (ret) {
+ 			return ret;
+ 		}
+-		msleep(50);
+-	}
+-	dev_err(&client->dev, "uploaded firmware didn't start, got to 0x%x, retrying...\n", fw_status);
+ 
+-	// Putting MCU in reset state
+-	ret = ov5640_write_reg(sensor, OV5640_REG_SYS_RESET00, 0x20);
+-	if (ret)
+-		return ret;
+-	// Start AF MCU
+-	ret = ov5640_write_reg(sensor, OV5640_REG_SYS_RESET00, 0x00);
+-	if (ret)
+-		return ret;
+-	// Wait for firmware to be ready
+-	for (i = 0; i < 5; i++) {
+-		ret = ov5640_read_reg(sensor, OV5640_REG_FW_STATUS, &fw_status);
+ 		if (fw_status == OV5640_FW_STATUS_S_IDLE) {
+-			dev_info(&client->dev, "fw started after %d ms\n", i * 50);
+-			return ret;
++			dev_info(&client->dev, "fw started after %d ms\n", i * 5);
++			return 0;
+ 		}
+-		msleep(50);
++		msleep(5);
+ 	}
++
+ 	dev_err(&client->dev, "uploaded firmware didn't start, got to 0x%x\n", fw_status);
+ 	return -ETIMEDOUT;
+ }
+@@ -2640,10 +2679,9 @@ static int ov5640_af_init(struct ov5640_dev *sensor)
+ 		return ret;
+ 
+ 	// Set lens focus driver on
+-	ov5640_write_reg(sensor, OV5640_REG_VCM_CONTROL4, 0x3f);
++	ret = ov5640_write_reg(sensor, OV5640_REG_VCM_CONTROL4, 0x3f);
+ 	if (ret)
+ 		return ret;
+-
+ 	return ret;
+ }
+ 
+@@ -3416,9 +3454,16 @@ static int ov5640_set_ctrl_focus(struct ov5640_dev *sensor, int command)
+ 	struct i2c_client *client = sensor->i2c_client;
+ 	int ret;
+ 
++	// Don't attempt to do focus if the embedded controller is powered down
++	if (!sensor->streaming) {
++		dev_err(&client->dev, "%s: can't set focus when not powered\n",
++			__func__);
++		return 0;
++	}
++
+ 	ret = ov5640_af_init(sensor);
+ 	if (ret) {
+-		dev_err(&client->dev, "%s: no autofocus firmware loaded\n",
++		dev_err(&client->dev, "%s: autofocus firmware load failed\n",
+ 			__func__);
+ 		return 0;
+ 	}
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/media-ov5640-Sleep-after-poweroff-to-ensure-next-poweron-is-not.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/media-ov5640-Sleep-after-poweroff-to-ensure-next-poweron-is-not.patch
new file mode 100644
index 000000000000..98c89d238412
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/media-ov5640-Sleep-after-poweroff-to-ensure-next-poweron-is-not.patch
@@ -0,0 +1,29 @@
+From 8649c6af904ecf4098b858e6d622b5cee6ffd1cf Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 26 Jan 2020 00:19:40 +0100
+Subject: media: ov5640: Sleep after poweroff to ensure next poweron is not too
+ early
+
+It's easy to use v4l2 userspace api in such a way that user can trigger
+a brownout on the sensor instead of a proper powerdown and powerup.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/media/i2c/ov5640.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/media/i2c/ov5640.c b/drivers/media/i2c/ov5640.c
+index e408946782c6..78a24f58888c 100644
+--- a/drivers/media/i2c/ov5640.c
++++ b/drivers/media/i2c/ov5640.c
+@@ -2535,6 +2535,7 @@ static void ov5640_set_power_off(struct ov5640_dev *sensor)
+ 	ov5640_power(sensor, false);
+ 	regulator_bulk_disable(OV5640_NUM_SUPPLIES, sensor->supplies);
+ 	clk_disable_unprepare(sensor->xclk);
++	msleep(100);
+ }
+ 
+ static int ov5640_set_power_mipi(struct ov5640_dev *sensor, bool on)
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/media-ov5640-set-default-ae-target-lower.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/media-ov5640-set-default-ae-target-lower.patch
new file mode 100644
index 000000000000..ab30ecb068b2
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/media-ov5640-set-default-ae-target-lower.patch
@@ -0,0 +1,27 @@
+From 098ea461478192bdce1c8daf9dced8b2edba861b Mon Sep 17 00:00:00 2001
+From: Martijn Braam <martijn@brixit.nl>
+Date: Wed, 7 Oct 2020 17:33:43 +0200
+Subject: media: ov5640: set default ae target lower
+
+The OV5640 tries to overexpose all photos by about 1 stop. This makes
+the exposure target one stop lower.
+---
+ drivers/media/i2c/ov5640.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/media/i2c/ov5640.c b/drivers/media/i2c/ov5640.c
+index 0e98ed8b3e08..4e0803484fd4 100644
+--- a/drivers/media/i2c/ov5640.c
++++ b/drivers/media/i2c/ov5640.c
+@@ -3875,7 +3875,7 @@ static int ov5640_probe(struct i2c_client *client)
+ 	sensor->current_link_freq =
+ 		ov5640_csi2_link_freqs[OV5640_DEFAULT_LINK_FREQ];
+ 
+-	sensor->ae_target = 52;
++	sensor->ae_target = 28;
+ 
+ 	endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(&client->dev),
+ 						  NULL);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/media-ov5640-use-pm_runtime_force_suspend-resume-for-system-sus.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/media-ov5640-use-pm_runtime_force_suspend-resume-for-system-sus.patch
new file mode 100644
index 000000000000..edf72ed5e4d5
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/media-ov5640-use-pm_runtime_force_suspend-resume-for-system-sus.patch
@@ -0,0 +1,31 @@
+From b05dfe5ce59ad5c2bae740af6d2b44518a7754fd Mon Sep 17 00:00:00 2001
+From: Andrey Skvortsov <andrej.skvortzov@gmail.com>
+Date: Mon, 14 Aug 2023 13:25:07 +0300
+Subject: media: ov5640: use pm_runtime_force_suspend/resume for system suspend
+
+If system was suspended while camera sensor was used, data and
+interrupts were still coming from sensor and that caused unstable
+system. Sometimes system hanged during a resume. Use
+pm_runtime_force_* helpers in order to support system suspend.
+
+Signed-off-by: Andrey Skvortsov <andrej.skvortzov@gmail.com>
+---
+ drivers/media/i2c/ov5640.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/drivers/media/i2c/ov5640.c b/drivers/media/i2c/ov5640.c
+index 5d69b74a5cd7..50177b44ed61 100644
+--- a/drivers/media/i2c/ov5640.c
++++ b/drivers/media/i2c/ov5640.c
+@@ -4285,6 +4285,8 @@ static void ov5640_remove(struct i2c_client *client)
+ }
+ 
+ static const struct dev_pm_ops ov5640_pm_ops = {
++	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
++				pm_runtime_force_resume)
+ 	SET_RUNTIME_PM_OPS(ov5640_sensor_suspend, ov5640_sensor_resume, NULL)
+ };
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/media-ov5648-Fix-call-to-pm_runtime_set_suspended.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/media-ov5648-Fix-call-to-pm_runtime_set_suspended.patch
new file mode 100644
index 000000000000..fe435c8ad2c5
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/media-ov5648-Fix-call-to-pm_runtime_set_suspended.patch
@@ -0,0 +1,29 @@
+From 2f64c8745d4217a3375648c0e3af0f3ab0765a5d Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Wed, 24 Apr 2024 00:00:31 +0200
+Subject: media: ov5648: Fix call to pm_runtime_set_suspended
+
+It should be done when RPM is disabled.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/media/i2c/ov5648.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/media/i2c/ov5648.c b/drivers/media/i2c/ov5648.c
+index 4b86d2631bd1..c691e235388a 100644
+--- a/drivers/media/i2c/ov5648.c
++++ b/drivers/media/i2c/ov5648.c
+@@ -2566,8 +2566,8 @@ static int ov5648_probe(struct i2c_client *client)
+ 
+ 	/* Runtime PM */
+ 
+-	pm_runtime_enable(sensor->dev);
+ 	pm_runtime_set_suspended(sensor->dev);
++	pm_runtime_enable(sensor->dev);
+ 
+ 	/* V4L2 subdev register */
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/media-sun6i-csi-Add-multicamera-support-for-parallel-bus.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/media-sun6i-csi-Add-multicamera-support-for-parallel-bus.patch
new file mode 100644
index 000000000000..62222bc51a88
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/media-sun6i-csi-Add-multicamera-support-for-parallel-bus.patch
@@ -0,0 +1,166 @@
+From 9bdb57f474095a3e7ab25410a24d4b7dbf8028aa Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Fri, 6 Jan 2023 11:25:09 +0100
+Subject: media: sun6i-csi: Add multicamera support for parallel bus
+
+Multiple cameras may be connected to parallel bus eg. in a tablet.
+Allow to register multiple parallel bus subdevices and switch between
+them by enabling/disabling media graph links.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../sunxi/sun6i-csi/sun6i_csi_bridge.c        | 51 +++++++++++--------
+ .../sunxi/sun6i-csi/sun6i_csi_bridge.h        |  4 +-
+ 2 files changed, 33 insertions(+), 22 deletions(-)
+
+diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.c b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.c
+index 92290876a8b3..0ea1fae7352e 100644
+--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.c
++++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.c
+@@ -207,12 +207,12 @@ static void sun6i_csi_bridge_disable(struct sun6i_csi_device *csi_dev)
+ 
+ static void
+ sun6i_csi_bridge_configure_parallel(struct sun6i_csi_device *csi_dev,
+-				    struct v4l2_subdev_state *state)
++				    struct v4l2_subdev_state *state,
++				    struct sun6i_csi_bridge_source *source)
+ {
+ 	struct device *dev = csi_dev->dev;
+ 	struct regmap *regmap = csi_dev->regmap;
+-	struct v4l2_fwnode_endpoint *endpoint =
+-		&csi_dev->bridge.source_parallel.endpoint;
++	struct v4l2_fwnode_endpoint *endpoint = &source->endpoint;
+ 	unsigned char bus_width = endpoint->bus.parallel.bus_width;
+ 	unsigned int flags = endpoint->bus.parallel.flags;
+ 	const struct v4l2_mbus_framefmt *sink_format;
+@@ -377,10 +377,8 @@ static void sun6i_csi_bridge_configure(struct sun6i_csi_device *csi_dev,
+ 				       struct sun6i_csi_bridge_source *source,
+ 				       struct v4l2_subdev_state *state)
+ {
+-	struct sun6i_csi_bridge *bridge = &csi_dev->bridge;
+-
+-	if (source == &bridge->source_parallel)
+-		sun6i_csi_bridge_configure_parallel(csi_dev, state);
++	if (source->endpoint.bus_type == V4L2_MBUS_PARALLEL)
++		sun6i_csi_bridge_configure_parallel(csi_dev, state, source);
+ 	else
+ 		sun6i_csi_bridge_configure_mipi_csi2(csi_dev, state);
+ 
+@@ -396,11 +394,11 @@ static int sun6i_csi_bridge_s_stream(struct v4l2_subdev *subdev, int on)
+ 	struct media_pad *local_pad = &bridge->pads[SUN6I_CSI_BRIDGE_PAD_SINK];
+ 	bool capture_streaming = csi_dev->capture.state.streaming;
+ 	struct device *dev = csi_dev->dev;
+-	struct sun6i_csi_bridge_source *source;
++	struct sun6i_csi_bridge_source *source = NULL;
+ 	struct v4l2_subdev *source_subdev;
+ 	struct media_pad *remote_pad;
+ 	struct v4l2_subdev_state *state;
+-	int ret;
++	int ret, i;
+ 
+ 	/* Source */
+ 
+@@ -413,10 +411,20 @@ static int sun6i_csi_bridge_s_stream(struct v4l2_subdev *subdev, int on)
+ 
+ 	source_subdev = media_entity_to_v4l2_subdev(remote_pad->entity);
+ 
+-	if (source_subdev == bridge->source_parallel.subdev)
+-		source = &bridge->source_parallel;
+-	else
++	if (source_subdev == bridge->source_mipi_csi2.subdev) {
+ 		source = &bridge->source_mipi_csi2;
++	} else {
++		for (i = 0; i < SUN6I_CSI_SOURCE_PARALLEL_MAX; i++) {
++			if (source_subdev == bridge->source_parallel[i].subdev) {
++				source = &bridge->source_parallel[i];
++				break;
++			}
++		}
++	}
++	if (!source) {
++		dev_err(dev, "bridge source not found\n");
++		return -ENODEV;
++	}
+ 
+ 	if (!on) {
+ 		v4l2_subdev_call(source_subdev, video, s_stream, 0);
+@@ -647,10 +655,10 @@ sun6i_csi_bridge_notifier_bound(struct v4l2_async_notifier *notifier,
+ 
+ 	switch (source->endpoint.base.port) {
+ 	case SUN6I_CSI_PORT_PARALLEL:
+-		enabled = true;
++		enabled = source->endpoint.base.id == 0;
+ 		break;
+ 	case SUN6I_CSI_PORT_MIPI_CSI2:
+-		enabled = !bridge->source_parallel.expected;
++		enabled = !bridge->source_parallel[0].expected;
+ 		break;
+ 	default:
+ 		return -EINVAL;
+@@ -696,7 +704,7 @@ sun6i_csi_bridge_notifier_ops = {
+ 
+ static int sun6i_csi_bridge_source_setup(struct sun6i_csi_device *csi_dev,
+ 					 struct sun6i_csi_bridge_source *source,
+-					 u32 port,
++					 u32 port, u32 ep,
+ 					 enum v4l2_mbus_type *bus_types)
+ {
+ 	struct device *dev = csi_dev->dev;
+@@ -706,7 +714,7 @@ static int sun6i_csi_bridge_source_setup(struct sun6i_csi_device *csi_dev,
+ 	struct fwnode_handle *handle;
+ 	int ret;
+ 
+-	handle = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), port, 0, 0);
++	handle = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), port, ep, 0);
+ 	if (!handle)
+ 		return -ENODEV;
+ 
+@@ -765,7 +773,7 @@ int sun6i_csi_bridge_setup(struct sun6i_csi_device *csi_dev)
+ 		V4L2_MBUS_BT656,
+ 		V4L2_MBUS_INVALID
+ 	};
+-	int ret;
++	int ret, i;
+ 
+ 	/* V4L2 Subdev */
+ 
+@@ -817,11 +825,12 @@ int sun6i_csi_bridge_setup(struct sun6i_csi_device *csi_dev)
+ 		v4l2_async_nf_init(notifier, v4l2_dev);
+ 	notifier->ops = &sun6i_csi_bridge_notifier_ops;
+ 
+-	sun6i_csi_bridge_source_setup(csi_dev, &bridge->source_parallel,
+-				      SUN6I_CSI_PORT_PARALLEL,
+-				      parallel_mbus_types);
++	for (i = 0; i < SUN6I_CSI_SOURCE_PARALLEL_MAX; i++)
++		sun6i_csi_bridge_source_setup(csi_dev, &bridge->source_parallel[i],
++					      SUN6I_CSI_PORT_PARALLEL, i,
++					      parallel_mbus_types);
+ 	sun6i_csi_bridge_source_setup(csi_dev, &bridge->source_mipi_csi2,
+-				      SUN6I_CSI_PORT_MIPI_CSI2, NULL);
++				      SUN6I_CSI_PORT_MIPI_CSI2, 0, NULL);
+ 
+ 	ret = v4l2_async_nf_register(notifier);
+ 	if (ret) {
+diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.h b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.h
+index a5b0a6f064dd..e755b67a2db3 100644
+--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.h
++++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.h
+@@ -38,12 +38,14 @@ struct sun6i_csi_bridge_async_subdev {
+ 	struct sun6i_csi_bridge_source	*source;
+ };
+ 
++#define SUN6I_CSI_SOURCE_PARALLEL_MAX 2
++
+ struct sun6i_csi_bridge {
+ 	struct v4l2_subdev		subdev;
+ 	struct v4l2_async_notifier	notifier;
+ 	struct media_pad		pads[2];
+ 
+-	struct sun6i_csi_bridge_source	source_parallel;
++	struct sun6i_csi_bridge_source	source_parallel[SUN6I_CSI_SOURCE_PARALLEL_MAX];
+ 	struct sun6i_csi_bridge_source	source_mipi_csi2;
+ };
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/media-sun6i-csi-add-V4L2_CAP_IO_MC-capability.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/media-sun6i-csi-add-V4L2_CAP_IO_MC-capability.patch
new file mode 100644
index 000000000000..c68600405109
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/media-sun6i-csi-add-V4L2_CAP_IO_MC-capability.patch
@@ -0,0 +1,82 @@
+From 8f97c0cb4b2e06ba17b6c6d020ff22af2f9ed265 Mon Sep 17 00:00:00 2001
+From: Adam Pigg <adam@piggz.co.uk>
+Date: Tue, 3 Jan 2023 18:52:04 +0000
+Subject: media: sun6i-csi: add V4L2_CAP_IO_MC capability
+
+Advertise the V4L2_CAP_IO_MC flag and update
+sun6i_csi_capture_enum_fmt to work with this capability.
+
+With the capability adverstised, the VIDIOC_ENUM_FMT ioctl
+implementation is updated to enumerate pixel formats depending
+on the supplied mbus_code.  If the code is 0, all formats are
+enumerated, if not, only pixel formats that match with the supplied
+mbus_code are enumeratd.
+
+Signed-off-by: Adam Pigg <adam@piggz.co.uk>
+---
+ .../sunxi/sun6i-csi/sun6i_csi_capture.c       | 37 +++++++++++++++++--
+ 1 file changed, 34 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c
+index ad9d1fca338d..f63862fd4e76 100644
+--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c
++++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c
+@@ -720,13 +720,43 @@ static int sun6i_csi_capture_enum_fmt(struct file *file, void *private,
+ 				      struct v4l2_fmtdesc *fmtdesc)
+ {
+ 	u32 index = fmtdesc->index;
++	unsigned int i;
+ 
+ 	if (index >= ARRAY_SIZE(sun6i_csi_capture_formats))
+ 		return -EINVAL;
+ 
+-	fmtdesc->pixelformat = sun6i_csi_capture_formats[index].pixelformat;
++	for (i = 0; i < ARRAY_SIZE(sun6i_csi_capture_formats); i++) {
++		const struct sun6i_csi_capture_format *format =
++			&sun6i_csi_capture_formats[i];
+ 
+-	return 0;
++		/*
++		 * If a media bus code is specified, only consider formats that
++		 * match it.
++		 */
++		if (fmtdesc->mbus_code) {
++			unsigned int j;
++
++			if (!format->mbus_codes)
++				continue;
++
++			for (j = 0; format->mbus_codes[j]; j++) {
++				if (fmtdesc->mbus_code == format->mbus_codes[j])
++					break;
++			}
++
++			if (!format->mbus_codes[j])
++				continue;
++		}
++
++		if (index == 0) {
++			fmtdesc->pixelformat = format->pixelformat;
++			return 0;
++		}
++
++		index--;
++	}
++
++	return -EINVAL;
+ }
+ 
+ static int sun6i_csi_capture_g_fmt(struct file *file, void *private,
+@@ -1032,7 +1062,8 @@ int sun6i_csi_capture_setup(struct sun6i_csi_device *csi_dev)
+ 
+ 	strscpy(video_dev->name, SUN6I_CSI_CAPTURE_NAME,
+ 		sizeof(video_dev->name));
+-	video_dev->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
++	video_dev->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING
++				| V4L2_CAP_IO_MC;
+ 	video_dev->vfl_dir = VFL_DIR_RX;
+ 	video_dev->release = video_device_release_empty;
+ 	video_dev->fops = &sun6i_csi_capture_fops;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/media-sun6i-csi-capture-Use-subdev-operation-to-access-bridge-f.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/media-sun6i-csi-capture-Use-subdev-operation-to-access-bridge-f.patch
new file mode 100644
index 000000000000..c3995fc04f7b
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/media-sun6i-csi-capture-Use-subdev-operation-to-access-bridge-f.patch
@@ -0,0 +1,128 @@
+From 92fb79b20a3d74951ac19b53d684d6b5f9a284de Mon Sep 17 00:00:00 2001
+From: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+Date: Wed, 4 Jan 2023 12:29:56 +0200
+Subject: media: sun6i-csi: capture: Use subdev operation to access bridge
+ format
+
+Replace the sun6i_csi_bridge helper functions sun6i_csi_bridge_format()
+and sun6i_csi_bridge_dimensions() that access the bridge fields from the
+capture side with usage of the subdev .get_fmt() operation. This
+decouples the bridge and capture side better by using abstractions
+provided by the V4L2 subdev API, and prepares for usage of the subdev
+active state in the bridge.
+
+The sun6i_csi_bridge_dimensions() helper is now unused and is removed.
+The sun6i_csi_bridge_format() helper will be removed in a subsequent
+change.
+
+Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+(cherry picked from commit e728c6bbead7a10d9ffd1139e416e1199b5837a6)
+---
+ .../sunxi/sun6i-csi/sun6i_csi_bridge.c        | 13 ++---------
+ .../sunxi/sun6i-csi/sun6i_csi_bridge.h        |  7 ------
+ .../sunxi/sun6i-csi/sun6i_csi_capture.c       | 23 ++++++++++++-------
+ 3 files changed, 17 insertions(+), 26 deletions(-)
+
+diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.c b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.c
+index d006d9dd0170..2303e5d2baee 100644
+--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.c
++++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.c
+@@ -15,17 +15,8 @@
+ 
+ /* Helpers */
+ 
+-void sun6i_csi_bridge_dimensions(struct sun6i_csi_device *csi_dev,
+-				 unsigned int *width, unsigned int *height)
+-{
+-	if (width)
+-		*width = csi_dev->bridge.mbus_format.width;
+-	if (height)
+-		*height = csi_dev->bridge.mbus_format.height;
+-}
+-
+-void sun6i_csi_bridge_format(struct sun6i_csi_device *csi_dev,
+-			     u32 *mbus_code, u32 *field)
++static void sun6i_csi_bridge_format(struct sun6i_csi_device *csi_dev,
++				    u32 *mbus_code, u32 *field)
+ {
+ 	if (mbus_code)
+ 		*mbus_code = csi_dev->bridge.mbus_format.code;
+diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.h b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.h
+index 44653b38f722..722b633b7893 100644
+--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.h
++++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.h
+@@ -49,13 +49,6 @@ struct sun6i_csi_bridge {
+ 	struct sun6i_csi_bridge_source	source_mipi_csi2;
+ };
+ 
+-/* Helpers */
+-
+-void sun6i_csi_bridge_dimensions(struct sun6i_csi_device *csi_dev,
+-				 unsigned int *width, unsigned int *height);
+-void sun6i_csi_bridge_format(struct sun6i_csi_device *csi_dev,
+-			     u32 *mbus_code, u32 *field);
+-
+ /* Format */
+ 
+ const struct sun6i_csi_bridge_format *
+diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c
+index 76356bc7f10e..4c43eaa42346 100644
+--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c
++++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c
+@@ -891,11 +891,14 @@ static int sun6i_csi_capture_link_validate(struct media_link *link)
+ 	const struct sun6i_csi_capture_format *capture_format;
+ 	const struct sun6i_csi_bridge_format *bridge_format;
+ 	unsigned int capture_width, capture_height;
+-	unsigned int bridge_width, bridge_height;
+ 	const struct v4l2_format_info *format_info;
+ 	u32 pixelformat, capture_field;
+-	u32 mbus_code, bridge_field;
++	struct v4l2_subdev_format fmt = {
++		.which = V4L2_SUBDEV_FORMAT_ACTIVE,
++		.pad = SUN6I_CSI_BRIDGE_PAD_SOURCE,
++	};
+ 	bool match;
++	int ret;
+ 
+ 	sun6i_csi_capture_dimensions(csi_dev, &capture_width, &capture_height);
+ 
+@@ -904,18 +907,21 @@ static int sun6i_csi_capture_link_validate(struct media_link *link)
+ 	if (WARN_ON(!capture_format))
+ 		return -EINVAL;
+ 
+-	sun6i_csi_bridge_dimensions(csi_dev, &bridge_width, &bridge_height);
++	ret = v4l2_subdev_call_state_active(&csi_dev->bridge.subdev, pad,
++					    get_fmt, &fmt);
++	if (ret)
++		return ret;
+ 
+-	sun6i_csi_bridge_format(csi_dev, &mbus_code, &bridge_field);
+-	bridge_format = sun6i_csi_bridge_format_find(mbus_code);
++	bridge_format = sun6i_csi_bridge_format_find(fmt.format.code);
+ 	if (WARN_ON(!bridge_format))
+ 		return -EINVAL;
+ 
+ 	/* No cropping/scaling is supported. */
+-	if (capture_width != bridge_width || capture_height != bridge_height) {
++	if (capture_width != fmt.format.width ||
++	    capture_height != fmt.format.height) {
+ 		v4l2_err(v4l2_dev,
+ 			 "invalid input/output dimensions: %ux%u/%ux%u\n",
+-			 bridge_width, bridge_height, capture_width,
++			 fmt.format.width, fmt.format.height, capture_width,
+ 			 capture_height);
+ 		return -EINVAL;
+ 	}
+@@ -947,7 +953,8 @@ static int sun6i_csi_capture_link_validate(struct media_link *link)
+ 	/* With raw input mode, we need a 1:1 match between input and output. */
+ 	if (bridge_format->input_format == SUN6I_CSI_INPUT_FMT_RAW ||
+ 	    capture_format->input_format_raw) {
+-		match = sun6i_csi_capture_format_match(pixelformat, mbus_code);
++		match = sun6i_csi_capture_format_match(pixelformat,
++						       fmt.format.code);
+ 		if (!match)
+ 			goto invalid;
+ 	}
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/media-sun6i-csi-implement-vidioc_enum_framesizes.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/media-sun6i-csi-implement-vidioc_enum_framesizes.patch
new file mode 100644
index 000000000000..ecfc5c5204fe
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/media-sun6i-csi-implement-vidioc_enum_framesizes.patch
@@ -0,0 +1,65 @@
+From 5d32b5ed1d4592469ac598972ed467486a9c3641 Mon Sep 17 00:00:00 2001
+From: Adam Pigg <adam@piggz.co.uk>
+Date: Wed, 4 Jan 2023 21:18:51 +0000
+Subject: media: sun6i-csi: implement vidioc_enum_framesizes
+
+Create sun6i_csi_capture_enum_framesizes which defines the min
+and max frame sizes.
+
+As per the specification of vidioc_enum_framesizes, if the supplied
+index is >0 or no valid formats are found for the supplied format,
+return -EINVAL.
+
+Set the type to V4L2_FRMSIZE_TYPE_CONTINUOUS and set the min and max
+width and height from the approriate macros, 32x32 - 4800x4800.
+
+Signed-off-by: Adam Pigg <adam@piggz.co.uk>
+---
+ .../sunxi/sun6i-csi/sun6i_csi_capture.c       | 24 +++++++++++++++++++
+ 1 file changed, 24 insertions(+)
+
+diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c
+index f63862fd4e76..68560f451204 100644
+--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c
++++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c
+@@ -793,6 +793,29 @@ static int sun6i_csi_capture_try_fmt(struct file *file, void *private,
+ 	return 0;
+ }
+ 
++static int sun6i_csi_capture_enum_framesizes(struct file *file, void *fh,
++					  struct v4l2_frmsizeenum *fsize)
++{
++	const struct sun6i_csi_capture_format *format;
++
++	if (fsize->index > 0)
++		return -EINVAL;
++
++	format = sun6i_csi_capture_format_find(fsize->pixel_format);
++	if (!format)
++		return -EINVAL;
++
++	fsize->type = V4L2_FRMSIZE_TYPE_CONTINUOUS;
++	fsize->stepwise.min_width = SUN6I_CSI_CAPTURE_WIDTH_MIN;
++	fsize->stepwise.max_width = SUN6I_CSI_CAPTURE_WIDTH_MAX;
++	fsize->stepwise.min_height = SUN6I_CSI_CAPTURE_HEIGHT_MIN;
++	fsize->stepwise.max_height = SUN6I_CSI_CAPTURE_HEIGHT_MAX;
++	fsize->stepwise.step_width = 1;
++	fsize->stepwise.step_height = 1;
++
++	return 0;
++}
++
+ static int sun6i_csi_capture_enum_input(struct file *file, void *private,
+ 					struct v4l2_input *input)
+ {
+@@ -829,6 +852,7 @@ static const struct v4l2_ioctl_ops sun6i_csi_capture_ioctl_ops = {
+ 	.vidioc_g_fmt_vid_cap		= sun6i_csi_capture_g_fmt,
+ 	.vidioc_s_fmt_vid_cap		= sun6i_csi_capture_s_fmt,
+ 	.vidioc_try_fmt_vid_cap		= sun6i_csi_capture_try_fmt,
++	.vidioc_enum_framesizes		= sun6i_csi_capture_enum_framesizes,
+ 
+ 	.vidioc_enum_input		= sun6i_csi_capture_enum_input,
+ 	.vidioc_g_input			= sun6i_csi_capture_g_input,
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/media-sun6i-csi-merge-sun6i_csi_formats-and-sun6i_csi_formats_m.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/media-sun6i-csi-merge-sun6i_csi_formats-and-sun6i_csi_formats_m.patch
new file mode 100644
index 000000000000..3c35ff6faa51
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/media-sun6i-csi-merge-sun6i_csi_formats-and-sun6i_csi_formats_m.patch
@@ -0,0 +1,431 @@
+From 4a94459f3c9f24e22331bb5e100ca885faa6a3bb Mon Sep 17 00:00:00 2001
+From: Adam Pigg <adam@piggz.co.uk>
+Date: Tue, 3 Jan 2023 18:20:21 +0000
+Subject: media: sun6i-csi: merge sun6i_csi_formats and sun6i_csi_formats_match
+
+Information about media bus formats and pixel formats supported by the
+driver is split between the sun6i_csi_capture_formats and
+sun6i_csi_capture_format_matches arrays. This makes it difficult to map
+media bus formats to pixel formats when enumerating the supported pixel
+formats by walking the sun6i_csi_capture_formats array. To prepare for
+support of media bus format support in sun6i_csi_capture_enum_fmt(),
+merge the two arrays toegether.
+
+To do this, sun6i_csi_capture_formats gains a const u32* to store the
+mbus_codes previously from sun6i_csi_capture_format_matches and
+sun6i_csi_capture_format_match is updated to iterate through this to
+find the mbus code while iterating sun6i_csi_capture_formats.
+
+In addition to merging the arrys, to produce semi-planar or multi-planar
+YUV formats, related mbus codes have been added to the *NV* and related
+pixel formats.
+
+Signed-off-by: Adam Pigg <adam@piggz.co.uk>
+---
+ .../sunxi/sun6i-csi/sun6i_csi_capture.c       | 211 +++++++++---------
+ .../sunxi/sun6i-csi/sun6i_csi_capture.h       |   6 +-
+ 2 files changed, 102 insertions(+), 115 deletions(-)
+
+diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c
+index 4c43eaa42346..ad9d1fca338d 100644
+--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c
++++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.c
+@@ -22,6 +22,8 @@
+ 
+ /* Helpers */
+ 
++#define SUN6I_BUS_FMTS(fmt...) (const u32[]) {fmt, 0}
++
+ void sun6i_csi_capture_dimensions(struct sun6i_csi_device *csi_dev,
+ 				  unsigned int *width, unsigned int *height)
+ {
+@@ -49,72 +51,86 @@ static const struct sun6i_csi_capture_format sun6i_csi_capture_formats[] = {
+ 		.pixelformat		= V4L2_PIX_FMT_SBGGR8,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_RAW_8,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_RAW_8,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_SBGGR8_1X8),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_SGBRG8,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_RAW_8,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_RAW_8,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_SGBRG8_1X8),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_SGRBG8,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_RAW_8,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_RAW_8,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_SGRBG8_1X8),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_SRGGB8,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_RAW_8,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_RAW_8,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_SRGGB8_1X8),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_SBGGR10,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_RAW_10,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_RAW_10,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_SBGGR10_1X10),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_SGBRG10,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_RAW_10,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_RAW_10,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_SGBRG10_1X10),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_SGRBG10,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_RAW_10,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_RAW_10,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_SGRBG10_1X10),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_SRGGB10,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_RAW_10,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_RAW_10,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_SRGGB10_1X10),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_SBGGR12,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_RAW_12,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_RAW_12,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_SBGGR12_1X12),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_SGBRG12,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_RAW_12,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_RAW_12,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_SGBRG12_1X12),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_SGRBG12,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_RAW_12,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_RAW_12,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_SGRBG12_1X12),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_SRGGB12,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_RAW_12,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_RAW_12,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_SRGGB12_1X12),
+ 	},
+ 	/* RGB */
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_RGB565,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_RGB565,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_RGB565,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_RGB565_2X8_LE),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_RGB565X,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_RGB565,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_RGB565,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_RGB565_2X8_BE),
+ 	},
+ 	/* YUV422 */
+ 	{
+@@ -123,6 +139,8 @@ static const struct sun6i_csi_capture_format sun6i_csi_capture_formats[] = {
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_RAW_8,
+ 		.input_format_raw	= true,
+ 		.hsize_len_factor	= 2,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_YUYV8_2X8,
++							 MEDIA_BUS_FMT_YUYV8_1X16),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_YVYU,
+@@ -130,6 +148,8 @@ static const struct sun6i_csi_capture_format sun6i_csi_capture_formats[] = {
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_RAW_8,
+ 		.input_format_raw	= true,
+ 		.hsize_len_factor	= 2,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_YVYU8_2X8,
++							 MEDIA_BUS_FMT_YVYU8_1X16),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_UYVY,
+@@ -137,6 +157,8 @@ static const struct sun6i_csi_capture_format sun6i_csi_capture_formats[] = {
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_RAW_8,
+ 		.input_format_raw	= true,
+ 		.hsize_len_factor	= 2,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_UYVY8_2X8,
++							 MEDIA_BUS_FMT_UYVY8_1X16),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_VYUY,
+@@ -144,57 +166,124 @@ static const struct sun6i_csi_capture_format sun6i_csi_capture_formats[] = {
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_RAW_8,
+ 		.input_format_raw	= true,
+ 		.hsize_len_factor	= 2,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_VYUY8_2X8,
++							 MEDIA_BUS_FMT_VYUY8_1X16),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_NV16,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_YUV422SP,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_YUV422SP,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_UYVY8_2X8,
++                                                         MEDIA_BUS_FMT_UYVY8_1X16,
++                                                         MEDIA_BUS_FMT_VYUY8_2X8,
++                                                         MEDIA_BUS_FMT_VYUY8_1X16,
++                                                         MEDIA_BUS_FMT_YUYV8_2X8,
++                                                         MEDIA_BUS_FMT_YUYV8_1X16,
++                                                         MEDIA_BUS_FMT_YVYU8_2X8,
++                                                         MEDIA_BUS_FMT_YVYU8_1X16),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_NV61,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_YUV422SP,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_YUV422SP,
+ 		.input_yuv_seq_invert	= true,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_UYVY8_2X8,
++                                                         MEDIA_BUS_FMT_UYVY8_1X16,
++                                                         MEDIA_BUS_FMT_VYUY8_2X8,
++                                                         MEDIA_BUS_FMT_VYUY8_1X16,
++                                                         MEDIA_BUS_FMT_YUYV8_2X8,
++                                                         MEDIA_BUS_FMT_YUYV8_1X16,
++                                                         MEDIA_BUS_FMT_YVYU8_2X8,
++                                                         MEDIA_BUS_FMT_YVYU8_1X16),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_YUV422P,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_YUV422P,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_YUV422P,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_UYVY8_2X8,
++                                                         MEDIA_BUS_FMT_UYVY8_1X16,
++                                                         MEDIA_BUS_FMT_VYUY8_2X8,
++                                                         MEDIA_BUS_FMT_VYUY8_1X16,
++                                                         MEDIA_BUS_FMT_YUYV8_2X8,
++                                                         MEDIA_BUS_FMT_YUYV8_1X16,
++                                                         MEDIA_BUS_FMT_YVYU8_2X8,
++                                                         MEDIA_BUS_FMT_YVYU8_1X16),
+ 	},
+ 	/* YUV420 */
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_NV12_16L16,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_YUV420MB,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_YUV420MB,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_UYVY8_2X8,
++                                                         MEDIA_BUS_FMT_UYVY8_1X16,
++                                                         MEDIA_BUS_FMT_VYUY8_2X8,
++                                                         MEDIA_BUS_FMT_VYUY8_1X16,
++                                                         MEDIA_BUS_FMT_YUYV8_2X8,
++                                                         MEDIA_BUS_FMT_YUYV8_1X16,
++                                                         MEDIA_BUS_FMT_YVYU8_2X8,
++                                                         MEDIA_BUS_FMT_YVYU8_1X16),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_NV12,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_YUV420SP,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_YUV420SP,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_UYVY8_2X8,
++                                                         MEDIA_BUS_FMT_UYVY8_1X16,
++                                                         MEDIA_BUS_FMT_VYUY8_2X8,
++                                                         MEDIA_BUS_FMT_VYUY8_1X16,
++                                                         MEDIA_BUS_FMT_YUYV8_2X8,
++                                                         MEDIA_BUS_FMT_YUYV8_1X16,
++                                                         MEDIA_BUS_FMT_YVYU8_2X8,
++                                                         MEDIA_BUS_FMT_YVYU8_1X16),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_NV21,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_YUV420SP,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_YUV420SP,
+ 		.input_yuv_seq_invert	= true,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_UYVY8_2X8,
++                                                         MEDIA_BUS_FMT_UYVY8_1X16,
++                                                         MEDIA_BUS_FMT_VYUY8_2X8,
++                                                         MEDIA_BUS_FMT_VYUY8_1X16,
++                                                         MEDIA_BUS_FMT_YUYV8_2X8,
++                                                         MEDIA_BUS_FMT_YUYV8_1X16,
++                                                         MEDIA_BUS_FMT_YVYU8_2X8,
++                                                         MEDIA_BUS_FMT_YVYU8_1X16),
+ 	},
+ 
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_YUV420,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_YUV420P,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_YUV420P,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_UYVY8_2X8,
++                                                         MEDIA_BUS_FMT_UYVY8_1X16,
++                                                         MEDIA_BUS_FMT_VYUY8_2X8,
++                                                         MEDIA_BUS_FMT_VYUY8_1X16,
++                                                         MEDIA_BUS_FMT_YUYV8_2X8,
++                                                         MEDIA_BUS_FMT_YUYV8_1X16,
++                                                         MEDIA_BUS_FMT_YVYU8_2X8,
++                                                         MEDIA_BUS_FMT_YVYU8_1X16),
+ 	},
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_YVU420,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_YUV420P,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_YUV420P,
+ 		.input_yuv_seq_invert	= true,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_UYVY8_2X8,
++                                                         MEDIA_BUS_FMT_UYVY8_1X16,
++                                                         MEDIA_BUS_FMT_VYUY8_2X8,
++                                                         MEDIA_BUS_FMT_VYUY8_1X16,
++                                                         MEDIA_BUS_FMT_YUYV8_2X8,
++                                                         MEDIA_BUS_FMT_YUYV8_1X16,
++                                                         MEDIA_BUS_FMT_YVYU8_2X8,
++                                                         MEDIA_BUS_FMT_YVYU8_1X16),
+ 	},
+ 	/* Compressed */
+ 	{
+ 		.pixelformat		= V4L2_PIX_FMT_JPEG,
+ 		.output_format_frame	= SUN6I_CSI_OUTPUT_FMT_FRAME_RAW_8,
+ 		.output_format_field	= SUN6I_CSI_OUTPUT_FMT_FIELD_RAW_8,
++		.mbus_codes		= SUN6I_BUS_FMTS(MEDIA_BUS_FMT_JPEG_1X8),
+ 	},
+ };
+ 
+@@ -210,118 +299,20 @@ struct sun6i_csi_capture_format *sun6i_csi_capture_format_find(u32 pixelformat)
+ 	return NULL;
+ }
+ 
+-/* RAW formats need an exact match between pixel and mbus formats. */
+-static const
+-struct sun6i_csi_capture_format_match sun6i_csi_capture_format_matches[] = {
+-	/* YUV420 */
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_YUYV,
+-		.mbus_code	= MEDIA_BUS_FMT_YUYV8_2X8,
+-	},
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_YUYV,
+-		.mbus_code	= MEDIA_BUS_FMT_YUYV8_1X16,
+-	},
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_YVYU,
+-		.mbus_code	= MEDIA_BUS_FMT_YVYU8_2X8,
+-	},
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_YVYU,
+-		.mbus_code	= MEDIA_BUS_FMT_YVYU8_1X16,
+-	},
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_UYVY,
+-		.mbus_code	= MEDIA_BUS_FMT_UYVY8_2X8,
+-	},
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_UYVY,
+-		.mbus_code	= MEDIA_BUS_FMT_UYVY8_1X16,
+-	},
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_VYUY,
+-		.mbus_code	= MEDIA_BUS_FMT_VYUY8_2X8,
+-	},
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_VYUY,
+-		.mbus_code	= MEDIA_BUS_FMT_VYUY8_1X16,
+-	},
+-	/* RGB */
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_RGB565,
+-		.mbus_code	= MEDIA_BUS_FMT_RGB565_2X8_LE,
+-	},
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_RGB565X,
+-		.mbus_code	= MEDIA_BUS_FMT_RGB565_2X8_BE,
+-	},
+-	/* Bayer */
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_SBGGR8,
+-		.mbus_code	= MEDIA_BUS_FMT_SBGGR8_1X8,
+-	},
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_SGBRG8,
+-		.mbus_code	= MEDIA_BUS_FMT_SGBRG8_1X8,
+-	},
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_SGRBG8,
+-		.mbus_code	= MEDIA_BUS_FMT_SGRBG8_1X8,
+-	},
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_SRGGB8,
+-		.mbus_code	= MEDIA_BUS_FMT_SRGGB8_1X8,
+-	},
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_SBGGR10,
+-		.mbus_code	= MEDIA_BUS_FMT_SBGGR10_1X10,
+-	},
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_SGBRG10,
+-		.mbus_code	= MEDIA_BUS_FMT_SGBRG10_1X10,
+-	},
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_SGRBG10,
+-		.mbus_code	= MEDIA_BUS_FMT_SGRBG10_1X10,
+-	},
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_SRGGB10,
+-		.mbus_code	= MEDIA_BUS_FMT_SRGGB10_1X10,
+-	},
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_SBGGR12,
+-		.mbus_code	= MEDIA_BUS_FMT_SBGGR12_1X12,
+-	},
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_SGBRG12,
+-		.mbus_code	= MEDIA_BUS_FMT_SGBRG12_1X12,
+-	},
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_SGRBG12,
+-		.mbus_code	= MEDIA_BUS_FMT_SGRBG12_1X12,
+-	},
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_SRGGB12,
+-		.mbus_code	= MEDIA_BUS_FMT_SRGGB12_1X12,
+-	},
+-	/* Compressed */
+-	{
+-		.pixelformat	= V4L2_PIX_FMT_JPEG,
+-		.mbus_code	= MEDIA_BUS_FMT_JPEG_1X8,
+-	},
+-};
+-
+ static bool sun6i_csi_capture_format_match(u32 pixelformat, u32 mbus_code)
+ {
+-	unsigned int i;
+-
+-	for (i = 0; i < ARRAY_SIZE(sun6i_csi_capture_format_matches); i++) {
+-		const struct sun6i_csi_capture_format_match *match =
+-			&sun6i_csi_capture_format_matches[i];
+-
+-		if (match->pixelformat == pixelformat &&
+-		    match->mbus_code == mbus_code)
+-			return true;
++	unsigned int i, j;
++
++	for (i = 0; i < ARRAY_SIZE(sun6i_csi_capture_formats); i++) {
++		const struct sun6i_csi_capture_format *format =
++			&sun6i_csi_capture_formats[i];
++
++		if (format->pixelformat == pixelformat) {
++			for (j = 0; format->mbus_codes[j]; j++) {
++				if (mbus_code == format->mbus_codes[j])
++					return true;
++			}
++		}
+ 	}
+ 
+ 	return false;
+diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.h b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.h
+index 3ee5ccefbd10..0484942834e3 100644
+--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.h
++++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_capture.h
+@@ -27,11 +27,7 @@ struct sun6i_csi_capture_format {
+ 	bool	input_yuv_seq_invert;
+ 	bool	input_format_raw;
+ 	u32	hsize_len_factor;
+-};
+-
+-struct sun6i_csi_capture_format_match {
+-	u32	pixelformat;
+-	u32	mbus_code;
++	const u32 *mbus_codes;
+ };
+ 
+ #undef current
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/media-sun6i-csi-subdev-Use-subdev-active-state-to-store-active-.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/media-sun6i-csi-subdev-Use-subdev-active-state-to-store-active-.patch
new file mode 100644
index 000000000000..60b52676a2fd
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/media-sun6i-csi-subdev-Use-subdev-active-state-to-store-active-.patch
@@ -0,0 +1,346 @@
+From 7ca3f841e2a66d2145bedc06dbcce5044725f622 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sat, 13 Jan 2024 21:24:24 +0100
+Subject: media: sun6i-csi: subdev: Use subdev active state to store active
+ format
+
+The sun6i_csi_bridge structure stores the active format as a struct
+v4l2_mbus_framefmt instance. Now that the V4L2 subdev core supports
+managing the active state, use it to replace the manually-managed
+format. This simplifies the implementation of the subdev operations by
+removing the need for a custom .get_fmt() handler.
+
+The subdev state now needs to be passed manually from the .s_stream()
+operation to internal functions that need to access the format. As a
+result, the sun6i_csi_bridge_format() helper function is now unused and
+can be dropped.
+
+The .init_state() and .set_fmt() operations also need to be updated
+accordingly. As a result, .set_fmt() now correctly propagates the format
+from the sink pad to the source pad.
+
+Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+(cherry picked from commit b14038f024ad84473ed79f3baecc2da9ca16d9a5)
+---
+ .../sunxi/sun6i-csi/sun6i_csi_bridge.c        | 149 +++++++++---------
+ .../sunxi/sun6i-csi/sun6i_csi_bridge.h        |   2 -
+ 2 files changed, 73 insertions(+), 78 deletions(-)
+
+diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.c b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.c
+index 2303e5d2baee..92290876a8b3 100644
+--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.c
++++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.c
+@@ -13,17 +13,6 @@
+ #include "sun6i_csi_bridge.h"
+ #include "sun6i_csi_reg.h"
+ 
+-/* Helpers */
+-
+-static void sun6i_csi_bridge_format(struct sun6i_csi_device *csi_dev,
+-				    u32 *mbus_code, u32 *field)
+-{
+-	if (mbus_code)
+-		*mbus_code = csi_dev->bridge.mbus_format.code;
+-	if (field)
+-		*field = csi_dev->bridge.mbus_format.field;
+-}
+-
+ /* Format */
+ 
+ static const struct sun6i_csi_bridge_format sun6i_csi_bridge_formats[] = {
+@@ -217,7 +206,8 @@ static void sun6i_csi_bridge_disable(struct sun6i_csi_device *csi_dev)
+ }
+ 
+ static void
+-sun6i_csi_bridge_configure_parallel(struct sun6i_csi_device *csi_dev)
++sun6i_csi_bridge_configure_parallel(struct sun6i_csi_device *csi_dev,
++				    struct v4l2_subdev_state *state)
+ {
+ 	struct device *dev = csi_dev->dev;
+ 	struct regmap *regmap = csi_dev->regmap;
+@@ -225,14 +215,14 @@ sun6i_csi_bridge_configure_parallel(struct sun6i_csi_device *csi_dev)
+ 		&csi_dev->bridge.source_parallel.endpoint;
+ 	unsigned char bus_width = endpoint->bus.parallel.bus_width;
+ 	unsigned int flags = endpoint->bus.parallel.flags;
+-	u32 field;
++	const struct v4l2_mbus_framefmt *sink_format;
+ 	u32 value = SUN6I_CSI_IF_CFG_IF_CSI;
+ 
+-	sun6i_csi_bridge_format(csi_dev, NULL, &field);
++	sink_format = v4l2_subdev_state_get_format(state, SUN6I_CSI_BRIDGE_PAD_SINK);
+ 
+-	if (field == V4L2_FIELD_INTERLACED ||
+-	    field == V4L2_FIELD_INTERLACED_TB ||
+-	    field == V4L2_FIELD_INTERLACED_BT)
++	if (sink_format->field == V4L2_FIELD_INTERLACED ||
++	    sink_format->field == V4L2_FIELD_INTERLACED_TB ||
++	    sink_format->field == V4L2_FIELD_INTERLACED_BT)
+ 		value |= SUN6I_CSI_IF_CFG_SRC_TYPE_INTERLACED |
+ 			 SUN6I_CSI_IF_CFG_FIELD_DT_PCLK_SHIFT(1) |
+ 			 SUN6I_CSI_IF_CFG_FIELD_DT_FIELD_VSYNC;
+@@ -308,17 +298,18 @@ sun6i_csi_bridge_configure_parallel(struct sun6i_csi_device *csi_dev)
+ }
+ 
+ static void
+-sun6i_csi_bridge_configure_mipi_csi2(struct sun6i_csi_device *csi_dev)
++sun6i_csi_bridge_configure_mipi_csi2(struct sun6i_csi_device *csi_dev,
++				     struct v4l2_subdev_state *state)
+ {
++	const struct v4l2_mbus_framefmt *sink_format;
+ 	struct regmap *regmap = csi_dev->regmap;
+ 	u32 value = SUN6I_CSI_IF_CFG_IF_MIPI;
+-	u32 field;
+ 
+-	sun6i_csi_bridge_format(csi_dev, NULL, &field);
++	sink_format = v4l2_subdev_state_get_format(state, SUN6I_CSI_BRIDGE_PAD_SINK);
+ 
+-	if (field == V4L2_FIELD_INTERLACED ||
+-	    field == V4L2_FIELD_INTERLACED_TB ||
+-	    field == V4L2_FIELD_INTERLACED_BT)
++	if (sink_format->field == V4L2_FIELD_INTERLACED ||
++	    sink_format->field == V4L2_FIELD_INTERLACED_TB ||
++	    sink_format->field == V4L2_FIELD_INTERLACED_BT)
+ 		value |= SUN6I_CSI_IF_CFG_SRC_TYPE_INTERLACED;
+ 	else
+ 		value |= SUN6I_CSI_IF_CFG_SRC_TYPE_PROGRESSIVE;
+@@ -326,19 +317,20 @@ sun6i_csi_bridge_configure_mipi_csi2(struct sun6i_csi_device *csi_dev)
+ 	regmap_write(regmap, SUN6I_CSI_IF_CFG_REG, value);
+ }
+ 
+-static void sun6i_csi_bridge_configure_format(struct sun6i_csi_device *csi_dev)
++static void sun6i_csi_bridge_configure_format(struct sun6i_csi_device *csi_dev,
++					      struct v4l2_subdev_state *state)
+ {
+ 	struct regmap *regmap = csi_dev->regmap;
+ 	bool capture_streaming = csi_dev->capture.state.streaming;
+ 	const struct sun6i_csi_bridge_format *bridge_format;
+ 	const struct sun6i_csi_capture_format *capture_format;
+-	u32 mbus_code, field, pixelformat;
++	const struct v4l2_mbus_framefmt *sink_format;
++	u32 pixelformat;
+ 	u8 input_format, input_yuv_seq, output_format;
+ 	u32 value = 0;
+ 
+-	sun6i_csi_bridge_format(csi_dev, &mbus_code, &field);
+-
+-	bridge_format = sun6i_csi_bridge_format_find(mbus_code);
++	sink_format = v4l2_subdev_state_get_format(state, SUN6I_CSI_BRIDGE_PAD_SINK);
++	bridge_format = sun6i_csi_bridge_format_find(sink_format->code);
+ 	if (WARN_ON(!bridge_format))
+ 		return;
+ 
+@@ -358,9 +350,9 @@ static void sun6i_csi_bridge_configure_format(struct sun6i_csi_device *csi_dev)
+ 		if (capture_format->input_yuv_seq_invert)
+ 			input_yuv_seq = bridge_format->input_yuv_seq_invert;
+ 
+-		if (field == V4L2_FIELD_INTERLACED ||
+-		    field == V4L2_FIELD_INTERLACED_TB ||
+-		    field == V4L2_FIELD_INTERLACED_BT)
++		if (sink_format->field == V4L2_FIELD_INTERLACED ||
++		    sink_format->field == V4L2_FIELD_INTERLACED_TB ||
++		    sink_format->field == V4L2_FIELD_INTERLACED_BT)
+ 			output_format = capture_format->output_format_field;
+ 		else
+ 			output_format = capture_format->output_format_frame;
+@@ -371,9 +363,9 @@ static void sun6i_csi_bridge_configure_format(struct sun6i_csi_device *csi_dev)
+ 	value |= SUN6I_CSI_CH_CFG_INPUT_FMT(input_format);
+ 	value |= SUN6I_CSI_CH_CFG_INPUT_YUV_SEQ(input_yuv_seq);
+ 
+-	if (field == V4L2_FIELD_TOP)
++	if (sink_format->field == V4L2_FIELD_TOP)
+ 		value |= SUN6I_CSI_CH_CFG_FIELD_SEL_FIELD0;
+-	else if (field == V4L2_FIELD_BOTTOM)
++	else if (sink_format->field == V4L2_FIELD_BOTTOM)
+ 		value |= SUN6I_CSI_CH_CFG_FIELD_SEL_FIELD1;
+ 	else
+ 		value |= SUN6I_CSI_CH_CFG_FIELD_SEL_EITHER;
+@@ -382,16 +374,17 @@ static void sun6i_csi_bridge_configure_format(struct sun6i_csi_device *csi_dev)
+ }
+ 
+ static void sun6i_csi_bridge_configure(struct sun6i_csi_device *csi_dev,
+-				       struct sun6i_csi_bridge_source *source)
++				       struct sun6i_csi_bridge_source *source,
++				       struct v4l2_subdev_state *state)
+ {
+ 	struct sun6i_csi_bridge *bridge = &csi_dev->bridge;
+ 
+ 	if (source == &bridge->source_parallel)
+-		sun6i_csi_bridge_configure_parallel(csi_dev);
++		sun6i_csi_bridge_configure_parallel(csi_dev, state);
+ 	else
+-		sun6i_csi_bridge_configure_mipi_csi2(csi_dev);
++		sun6i_csi_bridge_configure_mipi_csi2(csi_dev, state);
+ 
+-	sun6i_csi_bridge_configure_format(csi_dev);
++	sun6i_csi_bridge_configure_format(csi_dev, state);
+ }
+ 
+ /* V4L2 Subdev */
+@@ -406,6 +399,7 @@ static int sun6i_csi_bridge_s_stream(struct v4l2_subdev *subdev, int on)
+ 	struct sun6i_csi_bridge_source *source;
+ 	struct v4l2_subdev *source_subdev;
+ 	struct media_pad *remote_pad;
++	struct v4l2_subdev_state *state;
+ 	int ret;
+ 
+ 	/* Source */
+@@ -441,8 +435,9 @@ static int sun6i_csi_bridge_s_stream(struct v4l2_subdev *subdev, int on)
+ 	sun6i_csi_bridge_irq_clear(csi_dev);
+ 
+ 	/* Configure */
+-
+-	sun6i_csi_bridge_configure(csi_dev, source);
++	state = v4l2_subdev_lock_and_get_active_state(subdev);
++	sun6i_csi_bridge_configure(csi_dev, source, state);
++	v4l2_subdev_unlock_state(state);
+ 
+ 	if (capture_streaming)
+ 		sun6i_csi_capture_configure(csi_dev);
+@@ -495,13 +490,9 @@ sun6i_csi_bridge_mbus_format_prepare(struct v4l2_mbus_framefmt *mbus_format)
+ static int sun6i_csi_bridge_init_state(struct v4l2_subdev *subdev,
+ 				       struct v4l2_subdev_state *state)
+ {
+-	struct sun6i_csi_device *csi_dev = v4l2_get_subdevdata(subdev);
+ 	unsigned int pad = SUN6I_CSI_BRIDGE_PAD_SINK;
+ 	struct v4l2_mbus_framefmt *mbus_format =
+ 		v4l2_subdev_state_get_format(state, pad);
+-	struct mutex *lock = &csi_dev->bridge.lock;
+-
+-	mutex_lock(lock);
+ 
+ 	mbus_format->code = sun6i_csi_bridge_formats[0].mbus_code;
+ 	mbus_format->width = 1280;
+@@ -509,8 +500,6 @@ static int sun6i_csi_bridge_init_state(struct v4l2_subdev *subdev,
+ 
+ 	sun6i_csi_bridge_mbus_format_prepare(mbus_format);
+ 
+-	mutex_unlock(lock);
+-
+ 	return 0;
+ }
+ 
+@@ -527,53 +516,60 @@ sun6i_csi_bridge_enum_mbus_code(struct v4l2_subdev *subdev,
+ 	return 0;
+ }
+ 
+-static int sun6i_csi_bridge_get_fmt(struct v4l2_subdev *subdev,
+-				    struct v4l2_subdev_state *state,
+-				    struct v4l2_subdev_format *format)
+-{
+-	struct sun6i_csi_device *csi_dev = v4l2_get_subdevdata(subdev);
+-	struct v4l2_mbus_framefmt *mbus_format = &format->format;
+-	struct mutex *lock = &csi_dev->bridge.lock;
+-
+-	mutex_lock(lock);
+-
+-	if (format->which == V4L2_SUBDEV_FORMAT_TRY)
+-		*mbus_format = *v4l2_subdev_state_get_format(state,
+-							     format->pad);
+-	else
+-		*mbus_format = csi_dev->bridge.mbus_format;
+-
+-	mutex_unlock(lock);
+-
+-	return 0;
+-}
+-
+ static int sun6i_csi_bridge_set_fmt(struct v4l2_subdev *subdev,
+ 				    struct v4l2_subdev_state *state,
+ 				    struct v4l2_subdev_format *format)
+ {
+-	struct sun6i_csi_device *csi_dev = v4l2_get_subdevdata(subdev);
+-	struct v4l2_mbus_framefmt *mbus_format = &format->format;
+-	struct mutex *lock = &csi_dev->bridge.lock;
++	struct v4l2_mbus_framefmt *sink_format;
++	struct v4l2_mbus_framefmt *src_format;
+ 
+-	mutex_lock(lock);
++	/*
++	 * As the source format can't change independently of the sink format,
++	 * a set operation on the source is a get.
++	 */
++	if (format->pad == SUN6I_CSI_BRIDGE_PAD_SOURCE)
++		return v4l2_subdev_get_fmt(subdev, state, format);
+ 
+-	sun6i_csi_bridge_mbus_format_prepare(mbus_format);
++	sink_format = v4l2_subdev_state_get_format(state, SUN6I_CSI_BRIDGE_PAD_SINK);
+ 
++	/*
+ 	if (format->which == V4L2_SUBDEV_FORMAT_TRY)
+ 		*v4l2_subdev_state_get_format(state, format->pad) =
+ 			*mbus_format;
++	*/
++
++	if (!sun6i_csi_bridge_format_find(format->format.code))
++		sink_format->code = sun6i_csi_bridge_formats[0].mbus_code;
+ 	else
+-		csi_dev->bridge.mbus_format = *mbus_format;
++		sink_format->code = format->format.code;
++
++	sink_format->width = format->format.width;
++	sink_format->height = format->format.height;
++
++	/* Accept any colorspace as the CSI bridge isn't colorspace-aware. */
++	sink_format->colorspace = format->format.colorspace;
++	sink_format->xfer_func = format->format.xfer_func;
++	sink_format->ycbcr_enc = format->format.ycbcr_enc;
++	sink_format->quantization = format->format.quantization;
++
++	sink_format->field = V4L2_FIELD_NONE;
+ 
+-	mutex_unlock(lock);
++	format->format = *sink_format;
++
++	/*
++	 * Propagate the format to the source pad. The CSI bridge can't
++	 * transcode, the format on the source pad always matches the sink pad
++	 * exactly.
++	 */
++	src_format = v4l2_subdev_state_get_format(state, SUN6I_CSI_BRIDGE_PAD_SOURCE);
++	*src_format = *sink_format;
+ 
+ 	return 0;
+ }
+ 
+ static const struct v4l2_subdev_pad_ops sun6i_csi_bridge_pad_ops = {
+ 	.enum_mbus_code	= sun6i_csi_bridge_enum_mbus_code,
+-	.get_fmt	= sun6i_csi_bridge_get_fmt,
++	.get_fmt	= v4l2_subdev_get_fmt,
+ 	.set_fmt	= sun6i_csi_bridge_set_fmt,
+ };
+ 
+@@ -771,8 +767,6 @@ int sun6i_csi_bridge_setup(struct sun6i_csi_device *csi_dev)
+ 	};
+ 	int ret;
+ 
+-	mutex_init(&bridge->lock);
+-
+ 	/* V4L2 Subdev */
+ 
+ 	v4l2_subdev_init(subdev, &sun6i_csi_bridge_subdev_ops);
+@@ -801,6 +795,9 @@ int sun6i_csi_bridge_setup(struct sun6i_csi_device *csi_dev)
+ 		return ret;
+ 
+ 	/* V4L2 Subdev */
++	ret = v4l2_subdev_init_finalize(subdev);
++	if (ret)
++		goto error_media_entity;
+ 
+ 	if (csi_dev->isp_available)
+ 		ret = v4l2_async_register_subdev(subdev);
+diff --git a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.h b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.h
+index 722b633b7893..a5b0a6f064dd 100644
+--- a/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.h
++++ b/drivers/media/platform/sunxi/sun6i-csi/sun6i_csi_bridge.h
+@@ -42,8 +42,6 @@ struct sun6i_csi_bridge {
+ 	struct v4l2_subdev		subdev;
+ 	struct v4l2_async_notifier	notifier;
+ 	struct media_pad		pads[2];
+-	struct v4l2_mbus_framefmt	mbus_format;
+-	struct mutex			lock; /* Mbus format lock. */
+ 
+ 	struct sun6i_csi_bridge_source	source_parallel;
+ 	struct sun6i_csi_bridge_source	source_mipi_csi2;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/mfd-axp20x-Add-battery-IRQ-resources.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/mfd-axp20x-Add-battery-IRQ-resources.patch
new file mode 100644
index 000000000000..0321218d50c2
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/mfd-axp20x-Add-battery-IRQ-resources.patch
@@ -0,0 +1,102 @@
+From 183f5386ee44033042a23dcb7051572cb5a229a9 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 29 Feb 2020 01:01:58 -0600
+Subject: mfd: axp20x: Add battery IRQ resources
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/mfd/axp20x.c | 36 ++++++++++++++++++++++++++++++++++++
+ 1 file changed, 36 insertions(+)
+
+diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
+index 4e52c79f8f50..8ff8bc4a22b2 100644
+--- a/drivers/mfd/axp20x.c
++++ b/drivers/mfd/axp20x.c
+@@ -311,6 +311,15 @@ static const struct resource axp20x_ac_power_supply_resources[] = {
+ 	DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_ACIN_OVER_V, "ACIN_OVER_V"),
+ };
+ 
++static const struct resource axp20x_battery_resources[] = {
++	DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_BATT_PLUGIN, "BATT_PLUGIN"),
++	DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_BATT_REMOVAL, "BATT_REMOVAL"),
++	DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_BATT_ENT_ACT_MODE, "BATT_HEALTH_DEAD"),
++	DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_BATT_EXIT_ACT_MODE, "BATT_HEALTH_GOOD"),
++	DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_CHARG, "BATT_CHARGING"),
++	DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_CHARG_DONE, "BATT_CHARGING_DONE"),
++};
++
+ static const struct resource axp20x_pek_resources[] = {
+ 	DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_PEK_RIS_EDGE, "PEK_DBR"),
+ 	DEFINE_RES_IRQ_NAMED(AXP20X_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
+@@ -369,6 +378,23 @@ static const struct resource axp717_pek_resources[] = {
+ 	DEFINE_RES_IRQ_NAMED(AXP717_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
+ };
+ 
++static const struct resource axp803_battery_resources[] = {
++	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_BATT_PLUGIN, "BATT_PLUGIN"),
++	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_BATT_REMOVAL, "BATT_REMOVAL"),
++	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_BATT_ENT_ACT_MODE, "BATT_HEALTH_DEAD"),
++	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_BATT_EXIT_ACT_MODE, "BATT_HEALTH_GOOD"),
++	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_CHARG, "BATT_CHARGING"),
++	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_CHARG_DONE, "BATT_CHARGING_DONE"),
++	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_BATT_CHG_TEMP_HIGH, "BATT_CHG_TEMP_HIGH"),
++	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_BATT_CHG_TEMP_HIGH_END, "BATT_CHG_TEMP_HIGH_END"),
++	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_BATT_CHG_TEMP_LOW, "BATT_CHG_TEMP_LOW"),
++	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_BATT_CHG_TEMP_LOW_END, "BATT_CHG_TEMP_LOW_END"),
++	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_BATT_ACT_TEMP_HIGH, "BATT_ACT_TEMP_HIGH"),
++	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_BATT_ACT_TEMP_HIGH_END, "BATT_ACT_TEMP_HIGH_END"),
++	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_BATT_ACT_TEMP_LOW, "BATT_ACT_TEMP_LOW"),
++	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_BATT_ACT_TEMP_LOW_END, "BATT_ACT_TEMP_LOW_END"),
++};
++
+ static const struct resource axp803_pek_resources[] = {
+ 	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_PEK_RIS_EDGE, "PEK_DBR"),
+ 	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_PEK_FAL_EDGE, "PEK_DBF"),
+@@ -972,6 +998,8 @@ static const struct mfd_cell axp20x_cells[] = {
+ 	}, {
+ 		.name		= "axp20x-battery-power-supply",
+ 		.of_compatible	= "x-powers,axp209-battery-power-supply",
++		.num_resources	= ARRAY_SIZE(axp20x_battery_resources),
++		.resources	= axp20x_battery_resources,
+ 	}, {
+ 		.name		= "axp20x-ac-power-supply",
+ 		.of_compatible	= "x-powers,axp202-ac-power-supply",
+@@ -1006,6 +1034,8 @@ static const struct mfd_cell axp221_cells[] = {
+ 	}, {
+ 		.name		= "axp20x-battery-power-supply",
+ 		.of_compatible	= "x-powers,axp221-battery-power-supply",
++		.num_resources	= ARRAY_SIZE(axp20x_battery_resources),
++		.resources	= axp20x_battery_resources,
+ 	}, {
+ 		.name		= "axp20x-usb-power-supply",
+ 		.of_compatible	= "x-powers,axp221-usb-power-supply",
+@@ -1028,6 +1058,8 @@ static const struct mfd_cell axp223_cells[] = {
+ 	}, {
+ 		.name		= "axp20x-battery-power-supply",
+ 		.of_compatible	= "x-powers,axp221-battery-power-supply",
++		.num_resources	= ARRAY_SIZE(axp20x_battery_resources),
++		.resources	= axp20x_battery_resources,
+ 	}, {
+ 		.name		= "axp20x-regulator",
+ 	}, {
+@@ -1144,6 +1176,8 @@ static const struct mfd_cell axp803_cells[] = {
+ 	}, {
+ 		.name		= "axp20x-battery-power-supply",
+ 		.of_compatible	= "x-powers,axp813-battery-power-supply",
++		.num_resources	= ARRAY_SIZE(axp803_battery_resources),
++		.resources	= axp803_battery_resources,
+ 	}, {
+ 		.name		= "axp20x-ac-power-supply",
+ 		.of_compatible	= "x-powers,axp813-ac-power-supply",
+@@ -1204,6 +1238,8 @@ static const struct mfd_cell axp813_cells[] = {
+ 	}, {
+ 		.name		= "axp20x-battery-power-supply",
+ 		.of_compatible	= "x-powers,axp813-battery-power-supply",
++		.num_resources	= ARRAY_SIZE(axp803_battery_resources),
++		.resources	= axp803_battery_resources,
+ 	}, {
+ 		.name		= "axp20x-ac-power-supply",
+ 		.of_compatible	= "x-powers,axp813-ac-power-supply",
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/misc-modem-power-Power-manager-for-modems.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/misc-modem-power-Power-manager-for-modems.patch
new file mode 100644
index 000000000000..ca2f31770057
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/misc-modem-power-Power-manager-for-modems.patch
@@ -0,0 +1,2048 @@
+From ec41719fff6c6b38703993687e10ee49d795092e Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 12 Nov 2017 02:10:15 +0100
+Subject: misc: modem-power: Power manager for modems
+
+This driver allows for powering/resetting devices that are otherwise
+handled by other subsytems (USB). It also has mechanismsm for polling
+from userspace on device->SoC wakeup events via GPIO.
+
+This is mostly useful for controling modems. The supported modems are:
+
+- Quectel EG25
+- ZTE MG3732
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/misc/Kconfig       |    7 +
+ drivers/misc/Makefile      |    1 +
+ drivers/misc/modem-power.c | 1990 ++++++++++++++++++++++++++++++++++++
+ 3 files changed, 1998 insertions(+)
+ create mode 100644 drivers/misc/modem-power.c
+
+diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
+index 56bc72c7ce4a..c0efb3129661 100644
+--- a/drivers/misc/Kconfig
++++ b/drivers/misc/Kconfig
+@@ -632,6 +632,13 @@ config MCHP_LAN966X_PCI
+ 	    - lan966x-miim (MDIO_MSCC_MIIM)
+ 	    - lan966x-switch (LAN966X_SWITCH)
+ 
++config MODEM_POWER
++	tristate "Modem power/wakeup support for EG25, MG3732, etc."
++	depends on OF && SERIAL_DEV_BUS && RFKILL
++	help
++	  This driver provides support for powering up and handling
++	  wakeup signals for various modems.
++
+ source "drivers/misc/c2port/Kconfig"
+ source "drivers/misc/eeprom/Kconfig"
+ source "drivers/misc/cb710/Kconfig"
+diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
+index 545aad06d088..9b20ffa44835 100644
+--- a/drivers/misc/Makefile
++++ b/drivers/misc/Makefile
+@@ -75,3 +75,4 @@ lan966x-pci-objs		:= lan966x_pci.o
+ lan966x-pci-objs		+= lan966x_pci.dtbo.o
+ obj-$(CONFIG_MCHP_LAN966X_PCI)	+= lan966x-pci.o
+ obj-y				+= keba/
++obj-$(CONFIG_MODEM_POWER)	+= modem-power.o
+diff --git a/drivers/misc/modem-power.c b/drivers/misc/modem-power.c
+new file mode 100644
+index 000000000000..069790db953d
+--- /dev/null
++++ b/drivers/misc/modem-power.c
+@@ -0,0 +1,1990 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++/*
++ * Modem power control driver.
++ *
++ * Ondrej Jirman <megi@xff.cz>
++ *
++ * How this works
++ * --------------
++ *
++ * The driver:
++ * - can be registered as a platform or serial device
++ * - will use gpios, regulator and (optionally) serial port to control the modem
++ * - exposes a character device to control the modem power and receive various
++ *   events
++ * - exposes sysfs interface to control modem power and wakeup
++ * - supports multiple modem types and instances
++ *
++ * Power up/power down:
++ * - may take a lot of time (eg. ~13-22s powerup, >22s powerdown)
++ * - happens on a private workqueue under a lock
++ * - may happen from shutdown hook
++ * - prevents suspend when powerup/powerdown is in progress
++ * - is serialized and there's no abort of in-progress operations
++ * - for specific power sequence see comments in the section for each
++ *   supported modem variant
++ * - the driver monitors the power status of the modem (optionally)
++ *   and tries to complete the powerdown initiated via AT command
++ * - the driver tries to detect when the modem is killswitched off
++ *   and updates the driver status to reflect that
++ *
++ * Suspend/resume:
++ * - suspend is blocked if powerup/down is in progress
++ * - modem can wakeup the host over gpio based IRQ (RI signal)
++ * - the driver will assert ap_ready after resume finishes
++ *
++ * Rfkill:
++ * - the driver implements a rfkill interface if rfkill gpio is available
++ */
++
++//#define DEBUG
++
++#include <linux/wait.h>
++#include <linux/interrupt.h>
++#include <linux/device.h>
++#include <linux/cdev.h>
++#include <linux/kfifo.h>
++#include <linux/module.h>
++#include <linux/poll.h>
++#include <linux/spinlock.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/platform_device.h>
++#include <linux/gpio/consumer.h>
++#include <linux/regulator/consumer.h>
++#include <linux/delay.h>
++#include <linux/slab.h>
++#include <linux/serdev.h>
++#include <linux/rfkill.h>
++
++#define DRIVER_NAME "modem-power"
++
++enum {
++	MPWR_REQ_NONE = 0,
++	MPWR_REQ_RESET,
++	MPWR_REQ_PWDN,
++	MPWR_REQ_PWUP,
++};
++
++enum {
++	MPWR_MODE_NORMAL = 1,
++	MPWR_MODE_DUMB,
++	MPWR_MODE_FASTBOOT,
++	MPWR_MODE_ALT1,
++	MPWR_MODE_ALT2,
++};
++
++struct mpwr_dev;
++
++struct mpwr_gpio {
++	const char* name;
++	unsigned desc_off;
++	int flags;
++	bool required;
++	int irq_flags;
++	unsigned irq_off;
++};
++
++#define MPWR_GPIO_DEF(_name, _flags, _req) \
++	{ .name = #_name, \
++	  .desc_off = offsetof(struct mpwr_dev, _name##_gpio), \
++	  .flags = _flags, \
++	  .required = _req, \
++	}
++
++#define MPWR_GPIO_DEF_IRQ(_name, _flags, _req, _irq_flags) \
++	{ .name = #_name, \
++	  .desc_off = offsetof(struct mpwr_dev, _name##_gpio), \
++	  .flags = _flags, \
++	  .required = _req, \
++	  .irq_flags = _irq_flags, \
++	  .irq_off = offsetof(struct mpwr_dev, _name##_irq), \
++	}
++
++struct mpwr_variant {
++	int (*power_init)(struct mpwr_dev* mpwr);
++	int (*power_up)(struct mpwr_dev* mpwr);
++	int (*power_down)(struct mpwr_dev* mpwr);
++	int (*reset)(struct mpwr_dev* mpwr);
++	void (*recv_msg)(struct mpwr_dev *mpwr, const char *msg);
++	int (*suspend)(struct mpwr_dev *mpwr);
++	int (*resume)(struct mpwr_dev *mpwr);
++	const struct mpwr_gpio* gpios;
++	bool regulator_required;
++	bool monitor_wakeup;
++};
++
++struct mpwr_dev {
++	struct device *dev;
++	const struct mpwr_variant* variant;
++
++	wait_queue_head_t wait;
++
++	/* serdev */
++	struct serdev_device *serdev;
++	char rcvbuf[4096];
++	size_t rcvbuf_fill;
++	char msg[4096];
++        int msg_len;
++        int msg_ok;
++	//struct kfifo kfifo;
++	DECLARE_KFIFO(kfifo, unsigned char, 4096);
++
++	/* power */
++	struct regulator *regulator;
++	struct regulator *regulator_vbus;
++
++	/* outputs */
++	struct gpio_desc *enable_gpio;
++	struct gpio_desc *reset_gpio;
++	struct gpio_desc *pwrkey_gpio;
++	struct gpio_desc *sleep_gpio;
++	struct gpio_desc *dtr_gpio;
++	struct gpio_desc *host_ready_gpio;
++	struct gpio_desc *cts_gpio;
++	struct gpio_desc *rts_gpio;
++
++	/* inputs */
++	struct gpio_desc *status_gpio;
++	struct gpio_desc *wakeup_gpio;
++	int wakeup_irq;
++	bool status_pwrkey_multiplexed;
++
++	/* config */
++	struct cdev cdev;
++	dev_t major;
++
++	/* rfkill */
++	struct rfkill *rfkill;
++
++	/* powerup/dn work queue */
++	struct workqueue_struct *wq;
++	struct work_struct power_work;
++	struct work_struct finish_pdn_work;
++        struct mutex modem_lock;
++
++	// change
++	spinlock_t lock; /* protects last_request */
++	int last_request;
++	int powerup_mode;
++	ktime_t last_wakeup;
++
++	struct timer_list wd_timer;
++        struct delayed_work host_ready_work;
++
++	unsigned long flags[1];
++};
++
++enum {
++	/* modem is powered */
++	MPWR_F_POWERED,
++	MPWR_F_POWER_CHANGE_INPROGRESS,
++	MPWR_F_KILLSWITCHED,
++	/* we got a wakeup from the modem */
++	MPWR_F_GOT_WAKEUP,
++        /* serdev */
++        MPWR_F_RECEIVING_MSG,
++        /* eg25 */
++        MPWR_F_GOT_PDN,
++	/* config options */
++        MPWR_F_BLOCKED,
++	/* file */
++	MPWR_F_OPEN,
++	MPWR_F_OVERFLOW,
++};
++
++static struct class* mpwr_class;
++
++static int mpwr_serdev_at_cmd(struct mpwr_dev *mpwr, const char *msg, int timeout_ms);
++static int mpwr_serdev_at_cmd_with_retry(struct mpwr_dev *mpwr, const char *msg,
++					 int timeout_ms, int tries);
++static int mpwr_serdev_at_cmd_with_retry_ignore_timeout(struct mpwr_dev *mpwr, const char *msg,
++							int timeout_ms, int tries);
++
++// {{{ mg2723 variant
++
++static int mpwr_mg2723_power_init(struct mpwr_dev* mpwr)
++{
++	// if the device has power applied or doesn't have regulator
++	// configured (we assume it's always powered) initialize GPIO
++	// to shut it down initially
++	if (!mpwr->regulator || regulator_is_enabled(mpwr->regulator)) {
++		gpiod_set_value(mpwr->enable_gpio, 0);
++		gpiod_set_value(mpwr->reset_gpio, 1);
++	} else {
++		// device is not powered, don't drive the gpios
++		gpiod_direction_input(mpwr->enable_gpio);
++		gpiod_direction_input(mpwr->reset_gpio);
++	}
++
++	return 0;
++}
++
++static int mpwr_mg2723_power_up(struct mpwr_dev* mpwr)
++{
++	int ret;
++
++	// power up
++	if (mpwr->regulator) {
++		ret = regulator_enable(mpwr->regulator);
++		if (ret < 0) {
++			dev_err(mpwr->dev,
++				"can't enable power supply err=%d", ret);
++			return ret;
++		}
++	}
++
++	gpiod_direction_output(mpwr->enable_gpio, 1);
++	gpiod_direction_output(mpwr->reset_gpio, 1);
++	msleep(300);
++	gpiod_set_value(mpwr->reset_gpio, 0);
++
++	return 0;
++}
++
++static int mpwr_mg2723_power_down(struct mpwr_dev* mpwr)
++{
++	gpiod_set_value(mpwr->enable_gpio, 0);
++	msleep(50);
++
++	if (mpwr->regulator) {
++		regulator_disable(mpwr->regulator);
++
++		gpiod_direction_input(mpwr->enable_gpio);
++		gpiod_direction_input(mpwr->reset_gpio);
++	} else {
++		gpiod_set_value(mpwr->reset_gpio, 1);
++	}
++
++	return 0;
++}
++
++static int mpwr_mg2723_reset(struct mpwr_dev* mpwr)
++{
++	gpiod_set_value(mpwr->reset_gpio, 1);
++	msleep(300);
++	gpiod_set_value(mpwr->reset_gpio, 0);
++
++	return 0;
++}
++
++static const struct mpwr_gpio mpwr_mg2723_gpios[] = {
++	MPWR_GPIO_DEF(enable, GPIOD_IN, true),
++	MPWR_GPIO_DEF(reset, GPIOD_IN, true),
++	MPWR_GPIO_DEF_IRQ(wakeup, GPIOD_IN, true, IRQF_TRIGGER_FALLING),
++	{ },
++};
++
++static const struct mpwr_variant mpwr_mg2723_variant = {
++	.power_init = mpwr_mg2723_power_init,
++	.power_up = mpwr_mg2723_power_up,
++	.power_down = mpwr_mg2723_power_down,
++	.reset = mpwr_mg2723_reset,
++	.gpios = mpwr_mg2723_gpios,
++};
++
++// }}}
++// {{{ eg25 variant
++
++static bool mpwr_eg25_qcfg_airplanecontrol_is_ok(const char* v)
++{
++	return strstarts(v, "1,");
++}
++
++struct mpwr_eg25_qcfg {
++	const char* name;
++	const char* val;
++	bool (*is_ok)(const char* val);
++};
++
++#define EG25G_LATEST_KNOWN_FIRMWARE "EG25GGBR07A08M2G_01.002.07"
++
++static const struct mpwr_eg25_qcfg mpwr_eg25_qcfgs[] = {
++	//{ "risignaltype",       "\"respective\"", },
++	{ "risignaltype",       "\"physical\"", },
++	{ "urc/ri/ring",        "\"pulse\",1,1000,5000,\"off\",1", },
++	{ "urc/ri/smsincoming", "\"pulse\",1,1", },
++	{ "urc/ri/other",       "\"off\",1,1", },
++	{ "urc/ri/pin",         "uart_ri", },
++	{ "urc/delay",          "0", },
++
++	//{ "sleep/datactrl",     "0,300,1", },
++
++	{ "sleepind/level",     "0", },
++	{ "wakeupin/level",     "0", },
++
++	{ "ApRstLevel",		"0", },
++	{ "ModemRstLevel",	"0", },
++
++	// in EG25-G this tries to modify file in /etc (read-only)
++	// and fails
++	//{ "dbgctl",		"0", },
++
++	// we don't need AP_READY
++	{ "apready",            "0,0,500", },
++
++	{ "airplanecontrol",    "1",   mpwr_eg25_qcfg_airplanecontrol_is_ok },
++
++	// available since firmware R07A08_01.002.01.002
++	{ "fast/poweroff",	"1" },
++};
++
++static char* mpwr_serdev_get_response_value(struct mpwr_dev *mpwr,
++					    const char* prefix)
++{
++	int off;
++
++	for (off = 0; off < mpwr->msg_len; off += strlen(mpwr->msg + off) + 1)
++		if (strstarts(mpwr->msg + off, prefix))
++			return mpwr->msg + off + strlen(prefix);
++
++	return NULL;
++}
++
++static struct gpio_desc *mpwr_eg25_get_pwrkey_gpio(struct mpwr_dev *mpwr)
++{
++	if (mpwr->status_pwrkey_multiplexed)
++		return mpwr->status_gpio;
++
++	return mpwr->pwrkey_gpio;
++}
++
++/*
++ * Gpio meanings
++ * -------------
++ *
++ * enable_gpio - 1 = enables RF, 0 = disables RF
++ * sleep_gpio  - 1 = puts modem to sleep, 0 = wakes up the modem (must be 0
++ *               during poweron)
++ * reset_gpio  - accepts 150-460ms reset pulse (high __|^|__)
++ * pwrkey_gpio - accepts 100ms-650ms pulse for powerup (high __|^|__)
++ *                       650ms+ pulse for powerdown
++ *                       (initiated after pulse ends, pulse may have indefinite
++ *                        duration)
++ * status_gpio - modem power status 0 = powered  1 = unpowered
++ * wakeup_gpio - "ring indicator" output from the modem
++ * host_ready_gpio - AP_READY pin - host is ready to receive URCs
++ *
++ * (pwrkey may be multiplexed with status_gpio)
++ *
++ * Modem behavior
++ * --------------
++ *
++ * wakeup_gpio (RI):
++ * - goes high shortly after power is applied (~15ms)
++ * - goes low when RDY is sent
++ *
++ * dtr_gpio
++ * - when high, modem can sleep if requested
++ * - H->L will wake up a sleeping modem
++ * - internal pull-up
++ *
++ * ri
++ * - pulled low when there's URC
++ * - modem wakes up on URC automatically
++ *
++ * - AT+QURCCFG
++ * - AT+QINDCFG="csq",1
++ * - AT+QINDCFG="ring",1
++ * - AT+QINDCFG="smsincoming",1
++ * - AT+CGREG=0
++ * - AT+CREG=0
++ *
++ * - AT+QURCCFG="urcport","uart1"
++ */
++static int mpwr_eg25_power_up(struct mpwr_dev* mpwr)
++{
++	struct gpio_desc *pwrkey_gpio = mpwr_eg25_get_pwrkey_gpio(mpwr);
++	bool wakeup_ok, status_ok;
++	bool needs_restart = false;
++	u32 speed = 115200;
++	int ret, i, off;
++	ktime_t start;
++	int mode = mpwr->powerup_mode;
++
++	if (regulator_is_enabled(mpwr->regulator))
++		dev_warn(mpwr->dev,
++			 "regulator was already enabled during powerup");
++
++	/* Enable the modem power. */
++	ret = regulator_enable(mpwr->regulator);
++	if (ret < 0) {
++		dev_err(mpwr->dev,
++			"can't enable power supply err=%d", ret);
++		return ret;
++	}
++
++	ret = regulator_enable(mpwr->regulator_vbus);
++	if (ret < 0) {
++		dev_err(mpwr->dev,
++			"can't enable vbus power supply err=%d", ret);
++		regulator_disable(mpwr->regulator);
++		return ret;
++	}
++
++	/* Drive default gpio signals during powerup */
++	/* host_ready_gpio should be 1 during normal powerup */
++	gpiod_direction_output(mpwr->host_ready_gpio, mode != MPWR_MODE_ALT2);
++	/* #W_DISABLE must be left pulled up during modem power up
++	 * early on, because opensource bootloader uses this signal to enter
++	 * fastboot mode when it's pulled down.
++	 *
++	 * This should be 1 for normal powerup and 0 for fastboot mode with
++	 * special Biktor's firmware.
++	 */
++	gpiod_direction_output(mpwr->enable_gpio, mode != MPWR_MODE_FASTBOOT);
++	gpiod_direction_output(mpwr->sleep_gpio, 0);
++	gpiod_direction_output(mpwr->reset_gpio, 0);
++	gpiod_direction_output(pwrkey_gpio, 0);
++	/* dtr_gpio should be 0 during normal powerup */
++	gpiod_direction_output(mpwr->dtr_gpio, mode == MPWR_MODE_ALT1);
++
++	/* Wait for powerup. (30ms min. according to datasheet) */
++	msleep(50);
++
++	/* Send 200ms pwrkey pulse to initiate poweron */
++	gpiod_set_value(pwrkey_gpio, 1);
++	msleep(200);
++	gpiod_set_value(pwrkey_gpio, 0);
++
++	/* skip modem killswitch status checks in fastboot bootloader entry mode */
++	if (mode != MPWR_MODE_NORMAL)
++		goto open_serdev;
++
++	/* Switch status key to input, in case it's multiplexed with pwrkey. */
++	gpiod_direction_input(mpwr->status_gpio);
++
++	/*
++	 * Wait for status/wakeup change, assume good values, if CTS/status
++	 * signals, are not configured.
++	 */
++	status_ok = mpwr->status_gpio ? false : true;
++	wakeup_ok = mpwr->wakeup_gpio ? false : true;
++
++	/* wait up to 10s for status */
++	start = ktime_get();
++	while (ktime_ms_delta(ktime_get(), start) < 10000) {
++		if (!wakeup_ok && mpwr->wakeup_gpio && gpiod_get_value(mpwr->wakeup_gpio)) {
++			dev_info(mpwr->dev, "wakeup ok\n");
++			wakeup_ok = true;
++		}
++
++		if (!status_ok && mpwr->status_gpio && !gpiod_get_value(mpwr->status_gpio)) {
++			dev_info(mpwr->dev, "status ok\n");
++			status_ok = true;
++		}
++
++		/* modem is ready */
++		if (wakeup_ok && status_ok)
++			break;
++
++		msleep(50);
++	}
++
++	if (!wakeup_ok) {
++		dev_err(mpwr->dev, "The modem looks kill-switched\n");
++		if (!test_and_set_bit(MPWR_F_KILLSWITCHED, mpwr->flags))
++			sysfs_notify(&mpwr->dev->kobj, NULL, "killswitched");
++		goto err_shutdown_noclose;
++	}
++
++	if (!status_ok) {
++		dev_err(mpwr->dev, "The modem didn't report powerup success in time\n");
++		goto err_shutdown_noclose;
++	}
++
++	if (test_and_clear_bit(MPWR_F_KILLSWITCHED, mpwr->flags))
++		sysfs_notify(&mpwr->dev->kobj, NULL, "killswitched");
++
++open_serdev:
++	/* open serial console */
++	ret = serdev_device_open(mpwr->serdev);
++	if (ret) {
++		dev_err(mpwr->dev, "error opening serdev (%d)\n", ret);
++		goto err_shutdown_noclose;
++	}
++
++	of_property_read_u32(mpwr->dev->of_node, "current-speed", &speed);
++	serdev_device_set_baudrate(mpwr->serdev, speed);
++	serdev_device_set_flow_control(mpwr->serdev, false);
++	ret = serdev_device_set_parity(mpwr->serdev, SERDEV_PARITY_NONE);
++	if (ret) {
++		dev_err(mpwr->dev, "error setting serdev parity (%d)\n", ret);
++		goto err_shutdown;
++	}
++
++	if (mode != MPWR_MODE_NORMAL)
++		goto powered_up;
++
++	ret = mpwr_serdev_at_cmd_with_retry_ignore_timeout(mpwr, "AT&FE0", 1000, 30);
++	if (ret)
++		goto err_shutdown;
++
++	/* print firmware version */
++        ret = mpwr_serdev_at_cmd_with_retry(mpwr, "AT+QVERSION;+QSUBSYSVER", 1000, 15);
++        if (ret == 0 && mpwr->msg_len > 0) {
++		bool outdated = false;
++
++		dev_info(mpwr->dev, "===================================================\n");
++		for (off = 0; off < mpwr->msg_len; off += strlen(mpwr->msg + off) + 1) {
++			if (strstr(mpwr->msg + off, "Project Rev") && !strstr(mpwr->msg + off, EG25G_LATEST_KNOWN_FIRMWARE))
++				outdated = true;
++
++			dev_info(mpwr->dev, "%s\n", mpwr->msg + off);
++		}
++		dev_info(mpwr->dev, "===================================================\n");
++
++		if (outdated)
++			dev_warn(mpwr->dev, "Your modem has an outdated firmware. Latest know version is %s. Consider updating.\n", EG25G_LATEST_KNOWN_FIRMWARE);
++	}
++
++	/* print ADB key to dmesg */
++        ret = mpwr_serdev_at_cmd_with_retry(mpwr, "AT+QADBKEY?", 1000, 15);
++        if (ret == 0) {
++		const char *val = mpwr_serdev_get_response_value(mpwr, "+QADBKEY: ");
++		if (val)
++			dev_info(mpwr->dev, "ADB KEY is '%s' (you can use it to unlock ADB access to the modem, see https://xnux.eu/devices/feature/modem-pp.html)\n", val);
++	}
++
++        // check DAI config
++        ret = mpwr_serdev_at_cmd_with_retry(mpwr, "AT+QDAI?", 1000, 15);
++        if (ret == 0) {
++		const char *val = mpwr_serdev_get_response_value(mpwr, "+QDAI: ");
++		const char *needed_val = NULL;
++		char buf[128];
++
++		if (val) {
++			of_property_read_string(mpwr->dev->of_node, "quectel,qdai", &needed_val);
++
++			if (needed_val && strcmp(needed_val, val)) {
++				dev_warn(mpwr->dev, "QDAI is '%s' (changing to '%s')\n", val, needed_val);
++
++				/* update qdai */
++				snprintf(buf, sizeof buf, "AT+QDAI=%s", needed_val);
++				ret = mpwr_serdev_at_cmd(mpwr, buf, 5000);
++				if (ret == 0)
++					needs_restart = true;
++			} else {
++				dev_info(mpwr->dev, "QDAI is '%s'\n", val);
++			}
++		}
++	}
++
++	/* reset the modem, to apply QDAI config if necessary */
++	if (needs_restart) {
++		dev_info(mpwr->dev, "Restarting modem\n");
++
++		/* reboot is broken with fastboot enabled */
++		mpwr_serdev_at_cmd(mpwr, "AT+QCFG=\"fast/poweroff\",0", 5000);
++
++		ret = mpwr_serdev_at_cmd(mpwr, "AT+CFUN=1,1", 5000);
++		if (ret)
++			goto err_shutdown;
++
++		/* wait a bit before starting to probe the modem again */
++		msleep(6000);
++
++		ret = mpwr_serdev_at_cmd_with_retry_ignore_timeout(mpwr, "AT&FE0", 1000, 30);
++		if (ret)
++			goto err_shutdown;
++
++		// wait until QDAI starts succeeding (then the modem is ready
++		// to accept the following QCFGs)
++		ret = mpwr_serdev_at_cmd_with_retry(mpwr, "AT+QDAI?", 1000, 15);
++		if (ret)
++			goto err_shutdown;
++	}
++
++        /* check and update important QCFGs */
++        for (i = 0; i < ARRAY_SIZE(mpwr_eg25_qcfgs); i++) {
++                const char* name = mpwr_eg25_qcfgs[i].name;
++                const char* needed_val = mpwr_eg25_qcfgs[i].val;
++		bool (*is_ok)(const char* val) = mpwr_eg25_qcfgs[i].is_ok;
++		const char *val;
++                char buf[128];
++
++                snprintf(buf, sizeof buf, "AT+QCFG=\"%s\"", name);
++                ret = mpwr_serdev_at_cmd(mpwr, buf, 1000);
++                if (ret)
++			continue;
++
++                snprintf(buf, sizeof buf, "+QCFG: \"%s\",", name);
++		val = mpwr_serdev_get_response_value(mpwr, buf);
++		if (val) {
++			if (needed_val && (is_ok ? !is_ok(val) : strcmp(needed_val, val))) {
++				dev_info(mpwr->dev, "QCFG '%s' is '%s' (changing to '%s')\n", name, val, needed_val);
++
++				/* update qcfg */
++				snprintf(buf, sizeof buf, "AT+QCFG=\"%s\",%s", name, needed_val);
++				ret = mpwr_serdev_at_cmd(mpwr, buf, 1000);
++				if (ret)
++					break; /* go to next QCFG */
++			} else {
++				dev_info(mpwr->dev, "QCFG '%s' is '%s'\n", name, val);
++			}
++		}
++        }
++
++	/* setup URC port */
++	ret = mpwr_serdev_at_cmd(mpwr, "AT+QURCCFG=\"urcport\",\"all\"", 2000);
++        if (ret) {
++		dev_info(mpwr->dev, "Your modem doesn't support AT+QURCCFG=\"urcport\",\"all\", consider upgrading the firmware.\n");
++
++		ret = mpwr_serdev_at_cmd(mpwr, "AT+QURCCFG=\"urcport\",\"usbat\"", 2000);
++		if (ret)
++			dev_err(mpwr->dev, "Modem may not report URCs to the right port!\n");
++	}
++
++	/* enable the modem to go to sleep when DTR is low */
++	ret = mpwr_serdev_at_cmd(mpwr, "AT+QSCLK=1", 2000);
++        if (ret)
++		dev_err(mpwr->dev, "Modem will probably not sleep!\n");
++
++powered_up:
++	// if we're signaling some alternate boot mode via GPIO, we need to
++	// sleep here so that modem's boot script notices the gpio
++	if (mode == MPWR_MODE_ALT1 || mode == MPWR_MODE_FASTBOOT || mode == MPWR_MODE_ALT2)
++		msleep(12000);
++
++	gpiod_direction_output(mpwr->dtr_gpio, 1);
++
++	return 0;
++
++err_shutdown:
++	serdev_device_close(mpwr->serdev);
++err_shutdown_noclose:
++	dev_warn(mpwr->dev,
++		 "Forcibly cutting off power, data loss may occur.\n");
++	gpiod_direction_input(mpwr->enable_gpio);
++	gpiod_direction_input(mpwr->reset_gpio);
++	gpiod_direction_input(mpwr->sleep_gpio);
++	gpiod_direction_input(pwrkey_gpio);
++	gpiod_direction_input(mpwr->host_ready_gpio);
++	gpiod_direction_input(mpwr->dtr_gpio);
++
++	regulator_disable(mpwr->regulator_vbus);
++	regulator_disable(mpwr->regulator);
++	return -ENODEV;
++}
++
++static int mpwr_eg25_power_down_finish(struct mpwr_dev* mpwr)
++{
++	struct gpio_desc *pwrkey_gpio = mpwr_eg25_get_pwrkey_gpio(mpwr);
++	ktime_t start = ktime_get();
++	int ret;
++
++	serdev_device_close(mpwr->serdev);
++
++	/*
++	 * This function is called right after POWERED DOWN message is received.
++	 *
++	 * In case of fast/poweroff == 1, no POWERED DOWN message is sent.
++	 * Fast power off times are around 1s since the end of 800ms
++	 * POK pulse.
++	 *
++	 * When the modem powers down RI (wakeup) goes low and STATUS goes
++	 * high at the same time. Status is not connected on some boards.
++	 * RI should be inactive during poweroff, but we don't know for sure.
++	 *
++	 * Therfore:
++	 * - wait for STATUS going low
++	 * - in case that's not available wait for RI going low
++	 * - in case timings seem off, warn the user
++	 *
++	 * In addition, some boards have PWRKEY multiplexed with STATUS signal.
++	 * In that case we need to switch STATUS to output high level, as soon
++	 * as it goes low in order to prevent a power-up signal being registered
++	 * by the modem.
++	 */
++
++	if (mpwr->status_gpio) {
++		/* wait up to 30s for status going high */
++		while (ktime_ms_delta(ktime_get(), start) < 30000) {
++			if (gpiod_get_value(mpwr->status_gpio)) {
++				if (ktime_ms_delta(ktime_get(), start) < 500)
++					dev_warn(mpwr->dev,
++						 "STATUS signal is high too soon during powerdown. Modem is already off?\n");
++				goto powerdown;
++			}
++
++			msleep(20);
++		}
++
++		dev_warn(mpwr->dev,
++			 "STATUS signal didn't go high during shutdown. Modem is still on?\n");
++		goto force_powerdown;
++	} else {
++		clear_bit(MPWR_F_GOT_WAKEUP, mpwr->flags);
++
++		if (!gpiod_get_value(mpwr->wakeup_gpio)) {
++			dev_warn(mpwr->dev,
++				 "RI signal is low too soon during powerdown. Modem is already off, or spurious wakeup?\n");
++			msleep(2000);
++			goto powerdown;
++		}
++
++		ret = wait_event_timeout(mpwr->wait,
++					 test_bit(MPWR_F_GOT_WAKEUP, mpwr->flags),
++					 msecs_to_jiffies(30000));
++		if (ret <= 0) {
++			dev_warn(mpwr->dev,
++				 "RI signal didn't go low during shutdown, is modem really powering down?\n");
++			goto force_powerdown;
++		}
++
++		if (ktime_ms_delta(ktime_get(), start) < 500) {
++			dev_warn(mpwr->dev,
++				 "RI signal is low too soon during powerdown. Modem is already off, or spurious wakeup?\n");
++			msleep(2000);
++			goto powerdown;
++		}
++	}
++
++powerdown:
++	gpiod_direction_input(mpwr->enable_gpio);
++	gpiod_direction_input(mpwr->reset_gpio);
++	gpiod_direction_input(mpwr->sleep_gpio);
++	gpiod_direction_input(pwrkey_gpio);
++	gpiod_direction_input(mpwr->host_ready_gpio);
++	gpiod_direction_input(mpwr->dtr_gpio);
++
++	regulator_disable(mpwr->regulator_vbus);
++	regulator_disable(mpwr->regulator);
++
++	return 0;
++
++force_powerdown:
++	dev_warn(mpwr->dev,
++		 "Forcibly cutting off power, data loss may occur.\n");
++	goto powerdown;
++}
++
++static int mpwr_eg25_power_down(struct mpwr_dev* mpwr)
++{
++	struct gpio_desc *pwrkey_gpio = mpwr_eg25_get_pwrkey_gpio(mpwr);
++	//int ret;
++
++	/* Send 800ms pwrkey pulse to initiate powerdown. */
++	gpiod_direction_output(pwrkey_gpio, 1);
++	msleep(800);
++	gpiod_set_value(pwrkey_gpio, 0);
++
++	/* Switch status key to input, in case it's multiplexed with pwrkey. */
++	gpiod_direction_input(mpwr->status_gpio);
++
++	msleep(20);
++
++#if 0
++	// wait for POWERED DOWN message
++	clear_bit(MPWR_F_GOT_PDN, mpwr->flags);
++	ret = wait_event_timeout(mpwr->wait,
++				 test_bit(MPWR_F_GOT_PDN, mpwr->flags),
++				 msecs_to_jiffies(7000));
++	if (ret <= 0)
++		dev_warn(mpwr->dev,
++			 "POWERED DOWN message not received, is modem really powering down?\n");
++#endif
++
++	return mpwr_eg25_power_down_finish(mpwr);
++}
++
++static void mpwr_finish_pdn_work(struct work_struct *work)
++{
++	/*
++	struct mpwr_dev *mpwr = container_of(work, struct mpwr_dev, power_work);
++	unsigned long flags;
++
++	spin_lock_irqsave(&mpwr->lock, flags);
++	spin_unlock_irqrestore(&mpwr->lock, flags);
++
++	pm_stay_awake(mpwr->dev);
++
++	mutex_lock(&mpwr->modem_lock);
++
++	mutex_unlock(&mpwr->modem_lock);
++
++	pm_relax(mpwr->dev);
++	*/
++}
++
++static void mpwr_eg25_receive_msg(struct mpwr_dev *mpwr, const char *msg)
++{
++	unsigned int msg_len;
++
++	if (!strcmp(msg, "POWERED DOWN")) {
++		// system is powering down
++                set_bit(MPWR_F_GOT_PDN, mpwr->flags);
++		wake_up(&mpwr->wait);
++
++		/*
++		if (mutex_trylock(&mpwr->modem_lock)) {
++			// if no power op is in progress, this means userspace
++			// tried to shut the modem down via AT command, finish up
++			// the job
++
++			pm_stay_awake(mpwr->dev);
++
++			queue_work(mpwr->wq, &mpwr->power_work);
++			dev_warn(mpwr->dev, "userspace shut down the modem via AT command, finishing the job\n");
++			mpwr_eg25_power_down_finish(mpwr);
++			mutex_unlock(&mpwr->modem_lock);
++
++			pm_relax(mpwr->dev);
++		}
++                  */
++                return;
++	}
++
++	if (!strcmp(msg, "RDY")) {
++		// system is ready after powerup
++                return;
++	}
++
++	if (!test_bit(MPWR_F_OPEN, mpwr->flags))
++		return;
++
++	msg_len = strlen(msg);
++
++	if (msg_len + 1 > kfifo_avail(&mpwr->kfifo)) {
++		if (!test_and_set_bit(MPWR_F_OVERFLOW, mpwr->flags))
++			wake_up(&mpwr->wait);
++		return;
++	}
++
++	kfifo_in(&mpwr->kfifo, msg, msg_len);
++	kfifo_in(&mpwr->kfifo, "\n", 1);
++	wake_up(&mpwr->wait);
++}
++
++static void mpwr_host_ready_work(struct work_struct *work)
++{
++        struct mpwr_dev *mpwr = container_of(work, struct mpwr_dev, host_ready_work.work);
++	int ret;
++
++	mutex_lock(&mpwr->modem_lock);
++	gpiod_direction_output(mpwr->dtr_gpio, 0);
++
++	/*
++	 * We need to give the modem some time to wake up.
++	 */
++	msleep(5);
++
++	ret = mpwr_serdev_at_cmd(mpwr, "AT+QCFG=\"urc/cache\",0", 500);
++	if (ret)
++		dev_warn(mpwr->dev,
++			 "Failed to disable urc/cache, you may not be able to see URCs\n");
++
++	gpiod_direction_output(mpwr->dtr_gpio, 1);
++	mutex_unlock(&mpwr->modem_lock);
++
++	gpiod_direction_output(mpwr->host_ready_gpio, 1);
++}
++
++static int mpwr_eg25_suspend(struct mpwr_dev *mpwr)
++{
++	int ret;
++
++	cancel_delayed_work_sync(&mpwr->host_ready_work);
++
++	gpiod_direction_output(mpwr->host_ready_gpio, 0);
++
++	mutex_lock(&mpwr->modem_lock);
++	gpiod_direction_output(mpwr->dtr_gpio, 0);
++
++	msleep(5);
++
++	ret = mpwr_serdev_at_cmd(mpwr, "AT+QCFG=\"urc/cache\",1", 500);
++	if (ret)
++		dev_warn(mpwr->dev,
++			 "Failed to enable urc/cache, you may lose URCs during suspend\n");
++
++	gpiod_direction_output(mpwr->dtr_gpio, 1);
++	mutex_unlock(&mpwr->modem_lock);
++
++	return 0;
++}
++
++static int mpwr_eg25_resume(struct mpwr_dev *mpwr)
++{
++	//gpiod_direction_output(mpwr->dtr_gpio, 0);
++
++	// delay disabling URC cache until the whole system is hopefully resumed...
++	schedule_delayed_work(&mpwr->host_ready_work, msecs_to_jiffies(1000));
++
++	return 0;
++}
++
++static const struct mpwr_gpio mpwr_eg25_gpios[] = {
++	MPWR_GPIO_DEF(enable, GPIOD_OUT_HIGH, true),
++	MPWR_GPIO_DEF(reset, GPIOD_OUT_LOW, true),
++	MPWR_GPIO_DEF(pwrkey, GPIOD_OUT_LOW, false),
++	MPWR_GPIO_DEF(dtr, GPIOD_OUT_LOW, true),
++	MPWR_GPIO_DEF(status, GPIOD_IN, false),
++	MPWR_GPIO_DEF_IRQ(wakeup, GPIOD_IN, true,
++			  IRQF_TRIGGER_FALLING),
++
++	// XXX: not really needed...
++	MPWR_GPIO_DEF(sleep, GPIOD_OUT_LOW, false),
++	MPWR_GPIO_DEF(host_ready, GPIOD_OUT_HIGH, false),
++	MPWR_GPIO_DEF(cts, GPIOD_IN, false),
++	MPWR_GPIO_DEF(rts, GPIOD_OUT_LOW, false),
++	{ },
++};
++
++static const struct mpwr_variant mpwr_eg25_variant = {
++	.power_up = mpwr_eg25_power_up,
++	.power_down = mpwr_eg25_power_down,
++	.recv_msg = mpwr_eg25_receive_msg,
++	.suspend = mpwr_eg25_suspend,
++	.resume = mpwr_eg25_resume,
++	.gpios = mpwr_eg25_gpios,
++	.regulator_required = true,
++	.monitor_wakeup = true,
++};
++
++// }}}
++// {{{ generic helpers
++
++static void mpwr_reset(struct mpwr_dev* mpwr)
++{
++	struct device *dev = mpwr->dev;
++	int ret;
++
++	if (!test_bit(MPWR_F_POWERED, mpwr->flags)) {
++		dev_err(dev, "reset requested but device is not enabled");
++		return;
++	}
++
++	if (!mpwr->reset_gpio) {
++		dev_err(dev, "reset is not configured for this device");
++		return;
++	}
++
++	if (!mpwr->variant->reset) {
++		dev_err(dev, "reset requested but not implemented");
++		return;
++	}
++
++	dev_info(dev, "resetting");
++	ret = mpwr->variant->reset(mpwr);
++	if (ret) {
++		dev_err(dev, "reset failed");
++	}
++}
++
++static void mpwr_power_down(struct mpwr_dev* mpwr)
++{
++	struct device *dev = mpwr->dev;
++	ktime_t start = ktime_get();
++	int ret;
++
++	if (!test_bit(MPWR_F_POWERED, mpwr->flags))
++		return;
++
++	if (!mpwr->variant->power_down) {
++		dev_err(dev, "power down requested but not implemented");
++		return;
++	}
++
++	dev_info(dev, "powering down");
++
++	ret = mpwr->variant->power_down(mpwr);
++	if (ret) {
++		dev_err(dev, "power down failed");
++	} else {
++		clear_bit(MPWR_F_POWERED, mpwr->flags);
++		sysfs_notify(&mpwr->dev->kobj, NULL, "powered");
++		dev_info(mpwr->dev, "powered down in %lld ms\n",
++			 ktime_ms_delta(ktime_get(), start));
++	}
++}
++
++static void mpwr_power_up(struct mpwr_dev* mpwr)
++{
++	struct device *dev = mpwr->dev;
++	ktime_t start = ktime_get();
++	int ret;
++
++	if (test_bit(MPWR_F_POWERED, mpwr->flags))
++		return;
++
++	if (!mpwr->variant->power_up) {
++		dev_err(dev, "power up requested but not implemented");
++		return;
++	}
++
++	dev_info(dev, "powering up");
++
++	ret = mpwr->variant->power_up(mpwr);
++	if (ret) {
++		dev_err(dev, "power up failed");
++	} else {
++		set_bit(MPWR_F_POWERED, mpwr->flags);
++		sysfs_notify(&mpwr->dev->kobj, NULL, "powered");
++		dev_info(mpwr->dev, "powered up in %lld ms\n",
++			 ktime_ms_delta(ktime_get(), start));
++	}
++}
++
++// }}}
++// {{{ chardev
++
++static int mpwr_release(struct inode *ip, struct file *fp)
++{
++	struct mpwr_dev* mpwr = fp->private_data;
++
++	clear_bit(MPWR_F_OPEN, mpwr->flags);
++
++	return 0;
++}
++
++static int mpwr_open(struct inode *ip, struct file *fp)
++{
++	struct mpwr_dev* mpwr = container_of(ip->i_cdev, struct mpwr_dev, cdev);
++
++	fp->private_data = mpwr;
++
++	if (test_and_set_bit(MPWR_F_OPEN, mpwr->flags))
++		return -EBUSY;
++
++	nonseekable_open(ip, fp);
++	return 0;
++}
++
++static ssize_t mpwr_read(struct file *fp, char __user *buf, size_t len,
++			 loff_t *off)
++{
++	struct mpwr_dev* mpwr = fp->private_data;
++	int non_blocking = fp->f_flags & O_NONBLOCK;
++	unsigned int copied;
++	int ret;
++
++	if (non_blocking && kfifo_is_empty(&mpwr->kfifo))
++		return -EWOULDBLOCK;
++
++	ret = wait_event_interruptible(mpwr->wait,
++				       !kfifo_is_empty(&mpwr->kfifo)
++				       || test_bit(MPWR_F_OVERFLOW, mpwr->flags));
++	if (ret)
++		return ret;
++
++	if (test_and_clear_bit(MPWR_F_OVERFLOW, mpwr->flags)) {
++		if (len < 9)
++			return -E2BIG;
++		if (copy_to_user(buf, "OVERFLOW\n", 9))
++			return -EFAULT;
++		return 9;
++	}
++
++	ret = kfifo_to_user(&mpwr->kfifo, buf, len, &copied);
++
++	return ret ? ret : copied;
++}
++
++static unsigned int mpwr_poll(struct file *fp, poll_table *wait)
++{
++	struct mpwr_dev* mpwr = fp->private_data;
++
++	poll_wait(fp, &mpwr->wait, wait);
++
++	if (!kfifo_is_empty(&mpwr->kfifo))
++		return EPOLLIN | EPOLLRDNORM;
++
++	return 0;
++}
++
++static const struct file_operations mpwr_fops = {
++	.owner		= THIS_MODULE,
++	.open		= mpwr_open,
++	.release	= mpwr_release,
++	.llseek		= noop_llseek,
++	.read		= mpwr_read,
++	.poll		= mpwr_poll,
++};
++
++// }}}
++
++static void mpwr_work_handler(struct work_struct *work)
++{
++	struct mpwr_dev *mpwr = container_of(work, struct mpwr_dev, power_work);
++	unsigned long flags;
++	int last_request;
++
++	spin_lock_irqsave(&mpwr->lock, flags);
++	last_request = mpwr->last_request;
++	mpwr->last_request = 0;
++	spin_unlock_irqrestore(&mpwr->lock, flags);
++
++	pm_stay_awake(mpwr->dev);
++
++	mutex_lock(&mpwr->modem_lock);
++
++	if (last_request == MPWR_REQ_RESET) {
++		mpwr_reset(mpwr);
++	} else if (last_request == MPWR_REQ_PWDN) {
++		mpwr_power_down(mpwr);
++	} else if (last_request == MPWR_REQ_PWUP) {
++		mpwr_power_up(mpwr);
++	}
++
++	mutex_unlock(&mpwr->modem_lock);
++
++	clear_bit(MPWR_F_POWER_CHANGE_INPROGRESS, mpwr->flags);
++	sysfs_notify(&mpwr->dev->kobj, NULL, "is_busy");
++	wake_up(&mpwr->wait);
++
++	pm_relax(mpwr->dev);
++}
++
++static void mpwr_request_power_change(struct mpwr_dev* mpwr, int request, int mode)
++{
++	unsigned long flags;
++
++	set_bit(MPWR_F_POWER_CHANGE_INPROGRESS, mpwr->flags);
++	sysfs_notify(&mpwr->dev->kobj, NULL, "is_busy");
++
++	spin_lock_irqsave(&mpwr->lock, flags);
++	mpwr->last_request = request;
++	if (mode >= 0)
++		mpwr->powerup_mode = mode;
++	spin_unlock_irqrestore(&mpwr->lock, flags);
++
++	queue_work(mpwr->wq, &mpwr->power_work);
++}
++
++static irqreturn_t mpwr_gpio_isr(int irq, void *dev_id)
++{
++	struct mpwr_dev *mpwr = dev_id;
++
++	if (irq == mpwr->wakeup_irq) {
++		dev_dbg(mpwr->dev, "wakeup irq\n");
++
++		if (device_can_wakeup(mpwr->dev))
++			pm_wakeup_event(mpwr->dev, 2000);
++
++		set_bit(MPWR_F_GOT_WAKEUP, mpwr->flags);
++		spin_lock(&mpwr->lock);
++		mpwr->last_wakeup = ktime_get();
++		spin_unlock(&mpwr->lock);
++		wake_up(&mpwr->wait);
++	}
++
++	return IRQ_HANDLED;
++}
++
++static void mpwr_wd_timer_fn(struct timer_list *t)
++{
++	struct mpwr_dev *mpwr = from_timer(mpwr, t, wd_timer);
++
++	if (!mpwr->variant->monitor_wakeup || !test_bit(MPWR_F_POWERED, mpwr->flags))
++		return;
++
++	/*
++	 * Monitor wakeup status:
++	 *
++	 * If RI signal is low for too long we assume the user killswitched
++	 * the modem at runtime.
++	 */
++	spin_lock(&mpwr->lock);
++	if (!gpiod_get_value(mpwr->wakeup_gpio)) {
++		if (ktime_ms_delta(ktime_get(), mpwr->last_wakeup) > 5000) {
++			if (!test_and_set_bit(MPWR_F_KILLSWITCHED, mpwr->flags))
++				sysfs_notify(&mpwr->dev->kobj, NULL, "killswitched");
++			wake_up(&mpwr->wait);
++			dev_warn(mpwr->dev, "modem looks killswitched at runtime!\n");
++		}
++	}
++	spin_unlock(&mpwr->lock);
++
++	mod_timer(t, jiffies + msecs_to_jiffies(1000));
++}
++
++// {{{ sysfs
++
++static ssize_t powered_show(struct device *dev,
++			    struct device_attribute *attr, char *buf)
++{
++	struct mpwr_dev *mpwr = platform_get_drvdata(to_platform_device(dev));
++
++	return scnprintf(buf, PAGE_SIZE, "%u\n",
++			 !!test_bit(MPWR_F_POWERED, mpwr->flags));
++}
++
++static ssize_t powered_store(struct device *dev,
++			     struct device_attribute *attr,
++			     const char *buf, size_t len)
++{
++	struct mpwr_dev *mpwr = platform_get_drvdata(to_platform_device(dev));
++	unsigned status;
++	int ret;
++
++	if (test_bit(MPWR_F_BLOCKED, mpwr->flags))
++		return -EPERM;
++
++	ret = kstrtouint(buf, 10, &status);
++	if (ret)
++		return ret;
++
++	mpwr_request_power_change(mpwr, status ? MPWR_REQ_PWUP : MPWR_REQ_PWDN, status);
++
++	return len;
++}
++
++static ssize_t powered_blocking_store(struct device *dev,
++				      struct device_attribute *attr,
++				      const char *buf, size_t len)
++{
++	struct mpwr_dev *mpwr = platform_get_drvdata(to_platform_device(dev));
++	unsigned status;
++	int ret;
++
++	if (test_bit(MPWR_F_BLOCKED, mpwr->flags))
++		return -EPERM;
++
++	ret = kstrtouint(buf, 10, &status);
++	if (ret)
++		return ret;
++
++	mpwr_request_power_change(mpwr, status ? MPWR_REQ_PWUP : MPWR_REQ_PWDN, status);
++
++	ret = wait_event_interruptible_timeout(mpwr->wait,
++					       !test_bit(MPWR_F_POWER_CHANGE_INPROGRESS, mpwr->flags),
++					       msecs_to_jiffies(60000));
++	if (ret <= 0) {
++		dev_err(mpwr->dev, "Power state change timeout\n");
++		return -EIO;
++	}
++
++	if (!!status != !!test_bit(MPWR_F_POWERED, mpwr->flags))
++		return -EIO;
++
++	return len;
++}
++
++static ssize_t help_show(struct device *dev, struct device_attribute *attr, char *buf)
++{
++	return scnprintf(buf, PAGE_SIZE,
++			"echo N > powered, where N can be:\n"
++			"0: power off\n"
++			"1: normal powerup\n"
++			"2: dumb powerup (no AT commands and little error checking during powerup)\n"
++			"3: fastboot powerup (with biktor's patched aboot - #W_DISABLE held low during powerup)\n"
++			"4: alternate powerup (megi's userspace - DTR held high during powerup)\n\n"
++			"echo N > powered_blocking can be used for the write to block until power status transition completes\n");
++}
++
++static ssize_t killswitched_show(struct device *dev,
++				 struct device_attribute *attr, char *buf)
++{
++	struct mpwr_dev *mpwr = platform_get_drvdata(to_platform_device(dev));
++
++	return scnprintf(buf, PAGE_SIZE, "%u\n",
++			 !!test_bit(MPWR_F_KILLSWITCHED, mpwr->flags));
++}
++
++static ssize_t is_busy_show(struct device *dev,
++			    struct device_attribute *attr, char *buf)
++{
++	struct mpwr_dev *mpwr = platform_get_drvdata(to_platform_device(dev));
++
++	return scnprintf(buf, PAGE_SIZE, "%u\n",
++			 !!test_bit(MPWR_F_POWER_CHANGE_INPROGRESS, mpwr->flags));
++}
++
++static ssize_t hard_reset_store(struct device *dev,
++				struct device_attribute *attr,
++				const char *buf, size_t len)
++{
++	struct mpwr_dev *mpwr = platform_get_drvdata(to_platform_device(dev));
++	bool val;
++	int ret;
++
++	if (test_bit(MPWR_F_BLOCKED, mpwr->flags))
++		return -EPERM;
++
++	ret = kstrtobool(buf, &val);
++	if (ret)
++		return ret;
++	if (val)
++		mpwr_request_power_change(mpwr, MPWR_REQ_RESET, -1);
++
++	return len;
++}
++
++static ssize_t debug_pins_store(struct device *dev,
++				struct device_attribute *attr,
++				const char *buf, size_t len)
++{
++	struct mpwr_dev *mpwr = platform_get_drvdata(to_platform_device(dev));
++	unsigned val;
++	int ret;
++
++	if (test_bit(MPWR_F_BLOCKED, mpwr->flags))
++		return -EPERM;
++
++	ret = kstrtouint(buf, 16, &val);
++	if (ret)
++		return ret;
++
++	gpiod_direction_output(mpwr->host_ready_gpio, val & BIT(0));
++	gpiod_direction_output(mpwr->enable_gpio, val & BIT(1));
++	gpiod_direction_output(mpwr->dtr_gpio, val & BIT(2));
++	gpiod_direction_output(mpwr->rts_gpio, val & BIT(3));
++
++	return len;
++}
++
++static ssize_t debug_pins_show(struct device *dev,
++			       struct device_attribute *attr, char *buf)
++{
++	struct mpwr_dev *mpwr = platform_get_drvdata(to_platform_device(dev));
++
++	return scnprintf(buf, PAGE_SIZE, "CTS=%u RI=%u\n",
++			 gpiod_get_value(mpwr->cts_gpio), gpiod_get_value(mpwr->wakeup_gpio));
++}
++
++static DEVICE_ATTR_RW(powered);
++static DEVICE_ATTR_WO(powered_blocking);
++static DEVICE_ATTR_RO(killswitched);
++static DEVICE_ATTR_RO(is_busy);
++static DEVICE_ATTR_RO(help);
++static DEVICE_ATTR_WO(hard_reset);
++static DEVICE_ATTR_RW(debug_pins);
++
++static struct attribute *mpwr_attrs[] = {
++	&dev_attr_powered.attr,
++	&dev_attr_powered_blocking.attr,
++	&dev_attr_killswitched.attr,
++	&dev_attr_is_busy.attr,
++	&dev_attr_help.attr,
++	&dev_attr_hard_reset.attr,
++	&dev_attr_debug_pins.attr,
++	NULL,
++};
++
++static const struct attribute_group mpwr_group = {
++	.attrs = mpwr_attrs,
++};
++
++// }}}
++// {{{ rfkill
++
++static int mpwr_rfkill_set(void *data, bool blocked)
++{
++	struct mpwr_dev *mpwr = data;
++
++	gpiod_set_value(mpwr->enable_gpio, !blocked);
++	return 0;
++}
++
++static void mpwr_rfkill_query(struct rfkill *rfkill, void *data)
++{
++	struct mpwr_dev *mpwr = data;
++
++	rfkill_set_sw_state(rfkill, !gpiod_get_value(mpwr->enable_gpio));
++}
++
++static const struct rfkill_ops mpwr_rfkill_ops = {
++	.set_block = mpwr_rfkill_set,
++	.query = mpwr_rfkill_query,
++};
++
++// }}}
++// {{{ probe
++
++static int mpwr_probe_generic(struct device *dev, struct mpwr_dev **mpwr_out)
++{
++	struct mpwr_dev *mpwr;
++	struct device_node *np = dev->of_node;
++	struct device *sdev;
++	const char* cdev_name = NULL;
++	int ret, i;
++
++	mpwr = devm_kzalloc(dev, sizeof(*mpwr), GFP_KERNEL);
++	if (!mpwr)
++		return -ENOMEM;
++
++	mpwr->variant = of_device_get_match_data(dev);
++	if (!mpwr->variant)
++		return -EINVAL;
++
++	mpwr->dev = dev;
++	init_waitqueue_head(&mpwr->wait);
++        mutex_init(&mpwr->modem_lock);
++        spin_lock_init(&mpwr->lock);
++	INIT_WORK(&mpwr->power_work, &mpwr_work_handler);
++	INIT_WORK(&mpwr->finish_pdn_work, &mpwr_finish_pdn_work);
++        INIT_DELAYED_WORK(&mpwr->host_ready_work, mpwr_host_ready_work);
++	INIT_KFIFO(mpwr->kfifo);
++
++	ret = of_property_read_string(np, "char-device-name", &cdev_name);
++	if (ret) {
++		dev_err(dev, "char-device-name is not configured");
++		return -EINVAL;
++	}
++
++	if (of_property_read_bool(np, "blocked"))
++		set_bit(MPWR_F_BLOCKED, mpwr->flags);
++
++	mpwr->status_pwrkey_multiplexed =
++		of_property_read_bool(np, "status-pwrkey-multiplexed");
++
++	mpwr->regulator = devm_regulator_get_optional(dev, "power");
++	if (IS_ERR(mpwr->regulator)) {
++		ret = PTR_ERR(mpwr->regulator);
++                if (ret != -ENODEV) {
++			dev_err(dev, "can't get power supply err=%d", ret);
++			return ret;
++		}
++
++		mpwr->regulator = NULL;
++	}
++
++	if (!mpwr->regulator && mpwr->variant->regulator_required) {
++		dev_err(dev, "can't get power supply err=%d", -ENODEV);
++		return -ENODEV;
++	}
++
++	mpwr->regulator_vbus = devm_regulator_get(dev, "vbus");
++	if (IS_ERR(mpwr->regulator_vbus))
++		return dev_err_probe(dev, PTR_ERR(mpwr->regulator_vbus),
++				     "can't get vbus power supply\n");
++
++	for (i = 0; mpwr->variant->gpios[i].name; i++) {
++		const struct mpwr_gpio *io = &mpwr->variant->gpios[i];
++		struct gpio_desc **desc = (struct gpio_desc **)((u8*)mpwr +
++								io->desc_off);
++		int *irq = (int*)((u8*)mpwr + io->irq_off);
++		char buf[64];
++
++		if (io->required)
++			*desc = devm_gpiod_get(dev, io->name, io->flags);
++		else
++			*desc = devm_gpiod_get_optional(dev, io->name, io->flags);
++
++		if (IS_ERR(*desc)) {
++			dev_err(dev, "can't get %s gpio err=%ld", io->name,
++				PTR_ERR(*desc));
++			return PTR_ERR(*desc);
++		}
++
++		if (!*desc)
++			continue;
++
++		if (io->irq_flags == 0 || io->irq_off == 0)
++			continue;
++
++		*irq = gpiod_to_irq(*desc);
++		if (*irq <= 0) {
++			dev_err(dev, "error converting %s gpio to irq: %d",
++				io->name, ret);
++			return *irq;
++		}
++
++		snprintf(buf, sizeof buf, "modem-%s-gpio", io->name);
++		ret = devm_request_irq(dev, *irq, mpwr_gpio_isr, io->irq_flags,
++				       devm_kstrdup(dev, buf, GFP_KERNEL), mpwr);
++		if (ret) {
++			dev_err(dev, "error requesting %s irq: %d",
++				io->name, ret);
++			return ret;
++		}
++	}
++
++	if (mpwr->status_pwrkey_multiplexed && mpwr->pwrkey_gpio) {
++		dev_err(dev, "status and pwrkey are multiplexed, but pwrkey defined\n");
++		return -EINVAL;
++	}
++
++	if (mpwr->status_pwrkey_multiplexed && !mpwr->status_gpio) {
++		dev_err(dev, "status and pwrkey are multiplexed, but status is not defined\n");
++		return -EINVAL;
++	}
++
++	ret = devm_device_add_group(dev, &mpwr_group);
++	if (ret)
++		return ret;
++
++	// create char device
++	ret = alloc_chrdev_region(&mpwr->major, 0, 1, "modem-power");
++	if (ret) {
++		dev_err(dev, "can't allocate chrdev region");
++		goto err_disable_regulator;
++	}
++
++	cdev_init(&mpwr->cdev, &mpwr_fops);
++	mpwr->cdev.owner = THIS_MODULE;
++	ret = cdev_add(&mpwr->cdev, mpwr->major, 1);
++	if (ret) {
++		dev_err(dev, "can't add cdev");
++		goto err_unreg_chrev_region;
++	}
++
++	sdev = device_create(mpwr_class, dev, mpwr->major, mpwr, cdev_name);
++	if (IS_ERR(sdev)) {
++		ret = PTR_ERR(sdev);
++		goto err_del_cdev;
++	}
++
++	if (mpwr->wakeup_irq > 0) {
++		ret = device_init_wakeup(dev, true);
++		if (ret) {
++			dev_err(dev, "failed to init wakeup (%d)\n", ret);
++			goto err_free_dev;
++		}
++	}
++
++	if (mpwr->enable_gpio) {
++		mpwr->rfkill = rfkill_alloc("modem", dev, RFKILL_TYPE_WWAN,
++					    &mpwr_rfkill_ops, mpwr);
++		if (!mpwr->rfkill) {
++			dev_err(dev, "failed to alloc rfkill\n");
++			ret = -ENOMEM;
++			goto err_deinit_wakeup;
++		}
++
++                rfkill_init_sw_state(mpwr->rfkill, false);
++
++		ret = rfkill_register(mpwr->rfkill);
++		if (ret) {
++			dev_err(dev, "failed to register rfkill (%d)\n", ret);
++			goto err_free_rfkill;
++		}
++	}
++
++	mpwr->wq = alloc_ordered_workqueue("modem-power", 0);
++	if (!mpwr->wq) {
++		ret = -ENOMEM;
++		dev_err(dev, "failed to allocate workqueue\n");
++		goto err_unreg_rfkill;
++	}
++
++	if (mpwr->variant->power_init)
++		mpwr->variant->power_init(mpwr);
++
++	timer_setup(&mpwr->wd_timer, mpwr_wd_timer_fn, 0);
++	mod_timer(&mpwr->wd_timer, jiffies + msecs_to_jiffies(50));
++
++	dev_info(dev, "modem power manager ready");
++	*mpwr_out = mpwr;
++
++	return 0;
++
++err_unreg_rfkill:
++	if (mpwr->rfkill)
++		rfkill_unregister(mpwr->rfkill);
++err_free_rfkill:
++	if (mpwr->rfkill)
++		rfkill_destroy(mpwr->rfkill);
++err_deinit_wakeup:
++	if (mpwr->wakeup_irq > 0)
++		device_init_wakeup(dev, false);
++err_free_dev:
++	device_destroy(mpwr_class, mpwr->major);
++err_del_cdev:
++	cdev_del(&mpwr->cdev);
++err_unreg_chrev_region:
++	unregister_chrdev_region(mpwr->major, 1);
++err_disable_regulator:
++	cancel_work_sync(&mpwr->power_work);
++	return ret;
++}
++
++static void mpwr_remove_generic(struct mpwr_dev *mpwr)
++{
++	if (mpwr->rfkill) {
++		rfkill_unregister(mpwr->rfkill);
++		rfkill_destroy(mpwr->rfkill);
++	}
++
++	if (mpwr->wakeup_irq > 0)
++		device_init_wakeup(mpwr->dev, false);
++
++	del_timer_sync(&mpwr->wd_timer);
++        cancel_delayed_work_sync(&mpwr->host_ready_work);
++
++	cancel_work_sync(&mpwr->power_work);
++	destroy_workqueue(mpwr->wq);
++
++	mutex_lock(&mpwr->modem_lock);
++	mpwr_power_down(mpwr);
++	mutex_unlock(&mpwr->modem_lock);
++
++	device_destroy(mpwr_class, mpwr->major);
++	cdev_del(&mpwr->cdev);
++	unregister_chrdev_region(mpwr->major, 1);
++}
++
++static void mpwr_shutdown_generic(struct mpwr_dev *mpwr)
++{
++	cancel_work_sync(&mpwr->power_work);
++        cancel_delayed_work_sync(&mpwr->host_ready_work);
++
++	mutex_lock(&mpwr->modem_lock);
++	mpwr_power_down(mpwr);
++	mutex_unlock(&mpwr->modem_lock);
++}
++
++// }}}
++// {{{ suspend/resume
++
++static int __maybe_unused mpwr_suspend(struct device *dev)
++{
++	struct mpwr_dev *mpwr = dev_get_drvdata(dev);
++	int ret = 0;
++
++	if (!test_bit(MPWR_F_POWERED, mpwr->flags))
++		return 0;
++
++	//if (mpwr->sleep_gpio)
++		//gpiod_direction_output(mpwr->sleep_gpio, 1);
++
++	if (mpwr->variant->suspend)
++		mpwr->variant->suspend(mpwr);
++
++	if (mpwr->wakeup_irq && device_may_wakeup(mpwr->dev))
++		enable_irq_wake(mpwr->wakeup_irq);
++
++	return ret;
++}
++
++static int __maybe_unused mpwr_resume(struct device *dev)
++{
++	struct mpwr_dev *mpwr = dev_get_drvdata(dev);
++	int ret = 0;
++
++	if (!test_bit(MPWR_F_POWERED, mpwr->flags))
++		return 0;
++
++	//if (mpwr->sleep_gpio)
++		//gpiod_direction_output(mpwr->sleep_gpio, 0);
++
++	if (mpwr->variant->resume)
++		mpwr->variant->resume(mpwr);
++
++	if (mpwr->wakeup_irq && device_may_wakeup(mpwr->dev))
++		disable_irq_wake(mpwr->wakeup_irq);
++
++	return ret;
++}
++
++static const struct dev_pm_ops mpwr_pm_ops = {
++	SET_SYSTEM_SLEEP_PM_OPS(mpwr_suspend, mpwr_resume)
++};
++
++// }}}
++// {{{ serdev
++
++static int mpwr_serdev_send_msg(struct mpwr_dev *mpwr, const char *msg)
++{
++	int ret, len;
++	char buf[128];
++
++	if (!mpwr->serdev)
++		return -ENODEV;
++
++	len = snprintf(buf, sizeof buf, "%s\r\n", msg);
++	if (len >= sizeof buf)
++		return -E2BIG;
++
++	ret = serdev_device_write(mpwr->serdev, buf, len, msecs_to_jiffies(3000));
++	if (ret < len)
++		return -EIO;
++
++	serdev_device_wait_until_sent(mpwr->serdev, msecs_to_jiffies(3000));
++
++	return 0;
++}
++
++static int __mpwr_serdev_at_cmd(struct mpwr_dev *mpwr, const char *msg,
++				int timeout_ms, bool report_error, bool report_timeout)
++{
++        int ret;
++
++        if (test_and_set_bit(MPWR_F_RECEIVING_MSG, mpwr->flags))
++		return -EBUSY;
++
++	mpwr->msg_len = 0;
++
++	dev_dbg(mpwr->dev, "SEND: %s\n", msg);
++
++	ret = mpwr_serdev_send_msg(mpwr, msg);
++        if (ret) {
++		clear_bit(MPWR_F_RECEIVING_MSG, mpwr->flags);
++		dev_err(mpwr->dev, "AT command '%s' can't be sent (%d)\n", msg, ret);
++                return ret;
++        }
++
++	ret = wait_event_interruptible_timeout(mpwr->wait,
++					       !test_bit(MPWR_F_RECEIVING_MSG, mpwr->flags),
++					       msecs_to_jiffies(timeout_ms));
++	if (ret <= 0) {
++		clear_bit(MPWR_F_RECEIVING_MSG, mpwr->flags);
++		if (report_timeout)
++			dev_err(mpwr->dev, "AT command '%s' timed out\n", msg);
++                return ret ? ret : -ETIMEDOUT;
++	}
++
++        if (!mpwr->msg_ok) {
++		if (report_error)
++			dev_err(mpwr->dev, "AT command '%s' returned ERROR\n", msg);
++                return -EINVAL;
++	}
++
++        return 0;
++}
++
++static int mpwr_serdev_at_cmd(struct mpwr_dev *mpwr, const char *msg, int timeout_ms)
++{
++	return __mpwr_serdev_at_cmd(mpwr, msg, timeout_ms, true, true);
++}
++
++static int __mpwr_serdev_at_cmd_with_retry(struct mpwr_dev *mpwr, const char *msg,
++					   int timeout_ms, int tries, bool ignore_timeout)
++{
++	int ret = 0;
++
++	if (tries < 1)
++		tries = 1;
++
++	while (tries-- > 0) {
++		ret = __mpwr_serdev_at_cmd(mpwr, msg, timeout_ms, false, !ignore_timeout);
++		if (ret != -EINVAL && (!ignore_timeout || ret != -ETIMEDOUT))
++			return ret;
++
++		if (ret != -ETIMEDOUT)
++			msleep(1000);
++	}
++
++	dev_err(mpwr->dev, "AT command '%s' returned ERROR\n", msg);
++	return ret;
++}
++
++static int mpwr_serdev_at_cmd_with_retry(struct mpwr_dev *mpwr, const char *msg,
++					 int timeout_ms, int tries)
++{
++	return __mpwr_serdev_at_cmd_with_retry(mpwr, msg, timeout_ms, tries, false);
++}
++
++static int mpwr_serdev_at_cmd_with_retry_ignore_timeout(struct mpwr_dev *mpwr, const char *msg,
++							int timeout_ms, int tries)
++{
++	return __mpwr_serdev_at_cmd_with_retry(mpwr, msg, timeout_ms, tries, true);
++}
++
++static void mpwr_serdev_receive_msg(struct mpwr_dev *mpwr, const char *msg)
++{
++	dev_dbg(mpwr->dev, "RECV: %s\n", msg);
++
++	if (mpwr->variant->recv_msg)
++		mpwr->variant->recv_msg(mpwr, msg);
++
++        if (!test_bit(MPWR_F_RECEIVING_MSG, mpwr->flags))
++                return;
++
++	if (!strcmp(msg, "OK")) {
++                clear_bit(MPWR_F_RECEIVING_MSG, mpwr->flags);
++                mpwr->msg_ok = true;
++		wake_up(&mpwr->wait);
++                return;
++	} else if (!strcmp(msg, "ERROR")) {
++                clear_bit(MPWR_F_RECEIVING_MSG, mpwr->flags);
++                mpwr->msg_ok = false;
++		wake_up(&mpwr->wait);
++                return;
++	} else {
++                int len = strlen(msg);
++
++                if (mpwr->msg_len + len + 1 > sizeof(mpwr->msg)) {
++                        dev_warn(mpwr->dev, "message buffer overflow, ignoring message\n");
++                        return;
++                }
++
++                memcpy(mpwr->msg + mpwr->msg_len, msg, len + 1);
++                mpwr->msg_len += len + 1;
++        }
++}
++
++static size_t mpwr_serdev_receive_buf(struct serdev_device *serdev,
++				      const u8 *buf, size_t count)
++{
++	struct mpwr_dev *mpwr = serdev_device_get_drvdata(serdev);
++	size_t avail = sizeof(mpwr->rcvbuf) - mpwr->rcvbuf_fill;
++	char* p;
++
++	if (avail < count)
++		count = avail;
++
++	if (avail > 0) {
++		memcpy(mpwr->rcvbuf + mpwr->rcvbuf_fill, buf, count);
++		mpwr->rcvbuf_fill += count;
++	}
++
++	while (true) {
++		p = strnstr(mpwr->rcvbuf, "\r\n", mpwr->rcvbuf_fill);
++		if (p) {
++			if (p > mpwr->rcvbuf) {
++				*p = 0;
++				mpwr_serdev_receive_msg(mpwr, mpwr->rcvbuf);
++			}
++
++			mpwr->rcvbuf_fill -= (p - mpwr->rcvbuf) + 2;
++			memmove(mpwr->rcvbuf, p + 2, mpwr->rcvbuf_fill);
++		} else {
++			if (sizeof(mpwr->rcvbuf) - mpwr->rcvbuf_fill == 0) {
++				mpwr->rcvbuf_fill = 0;
++				dev_warn(mpwr->dev, "rcvbuf overflow\n");
++			}
++
++			break;
++		}
++	}
++
++        return count;
++}
++
++static const struct serdev_device_ops mpwr_serdev_ops = {
++	.receive_buf = mpwr_serdev_receive_buf,
++	.write_wakeup = serdev_device_write_wakeup,
++};
++
++static int mpwr_serdev_probe(struct serdev_device *serdev)
++{
++	struct device *dev = &serdev->dev;
++        struct mpwr_dev* mpwr;
++        int ret;
++
++	ret = mpwr_probe_generic(dev, &mpwr);
++	if (ret)
++		return ret;
++
++	serdev_device_set_drvdata(serdev, mpwr);
++	serdev_device_set_client_ops(serdev, &mpwr_serdev_ops);
++	mpwr->serdev = serdev;
++
++        return 0;
++}
++
++static void mpwr_serdev_remove(struct serdev_device *serdev)
++{
++	struct mpwr_dev *mpwr = serdev_device_get_drvdata(serdev);
++
++	mpwr_remove_generic(mpwr);
++}
++
++static const struct of_device_id mpwr_of_match_serdev[] = {
++	{ .compatible = "quectel,eg25",
++	  .data = &mpwr_eg25_variant },
++	{},
++};
++MODULE_DEVICE_TABLE(of, mpwr_of_match_serdev);
++
++static void mpwr_serdev_shutdown(struct device *dev)
++{
++	struct mpwr_dev *mpwr = dev_get_drvdata(dev);
++
++	mpwr_shutdown_generic(mpwr);
++}
++
++static struct serdev_device_driver mpwr_serdev_driver = {
++        .probe  = mpwr_serdev_probe,
++        .remove = mpwr_serdev_remove,
++        .driver = {
++                .name = DRIVER_NAME,
++                .of_match_table = mpwr_of_match_serdev,
++		.pm = &mpwr_pm_ops,
++		.shutdown = mpwr_serdev_shutdown,
++        },
++};
++
++// }}}
++// {{{ platdev
++
++static int mpwr_pdev_probe(struct platform_device *pdev)
++{
++        struct mpwr_dev* mpwr;
++        int ret;
++
++	ret = mpwr_probe_generic(&pdev->dev, &mpwr);
++	if (ret)
++		return ret;
++
++	platform_set_drvdata(pdev, mpwr);
++        return 0;
++}
++
++static void mpwr_pdev_remove(struct platform_device *pdev)
++{
++	struct mpwr_dev *mpwr = platform_get_drvdata(pdev);
++
++	mpwr_remove_generic(mpwr);
++}
++
++static void mpwr_pdev_shutdown(struct platform_device *pdev)
++{
++	struct mpwr_dev *mpwr = platform_get_drvdata(pdev);
++
++	mpwr_shutdown_generic(mpwr);
++}
++
++static const struct of_device_id mpwr_of_match_plat[] = {
++	{ .compatible = "zte,mg3732",
++	  .data = &mpwr_mg2723_variant },
++	{},
++};
++MODULE_DEVICE_TABLE(of, mpwr_of_match_plat);
++
++static struct platform_driver mpwr_platform_driver = {
++	.probe = mpwr_pdev_probe,
++	.remove = mpwr_pdev_remove,
++	.shutdown = mpwr_pdev_shutdown,
++	.driver = {
++		.name = DRIVER_NAME,
++		.of_match_table = mpwr_of_match_plat,
++		.pm = &mpwr_pm_ops,
++	},
++};
++
++// }}}
++// {{{ driver init
++
++static int __init mpwr_driver_init(void)
++{
++	int ret;
++
++	mpwr_class = class_create("modem-power");
++	if (IS_ERR(mpwr_class))
++		return PTR_ERR(mpwr_class);
++
++	ret = serdev_device_driver_register(&mpwr_serdev_driver);
++	if (ret)
++		goto err_class;
++
++	ret = platform_driver_register(&mpwr_platform_driver);
++	if (ret)
++		goto err_serdev;
++
++	return ret;
++
++err_serdev:
++	serdev_device_driver_unregister(&mpwr_serdev_driver);
++err_class:
++	class_destroy(mpwr_class);
++	return ret;
++}
++
++static void __exit mpwr_driver_exit(void)
++{
++	serdev_device_driver_unregister(&mpwr_serdev_driver);
++	platform_driver_unregister(&mpwr_platform_driver);
++	class_destroy(mpwr_class);
++}
++
++module_init(mpwr_driver_init);
++module_exit(mpwr_driver_exit);
++
++MODULE_DESCRIPTION("Modem power manager");
++MODULE_AUTHOR("Ondrej Jirman <megi@xff.cz>");
++MODULE_LICENSE("GPL v2");
++
++// }}}
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/mmc-add-delay-after-power-class-selection.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/mmc-add-delay-after-power-class-selection.patch
new file mode 100644
index 000000000000..cfb802902e4f
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/mmc-add-delay-after-power-class-selection.patch
@@ -0,0 +1,38 @@
+From e943000632398ac560d05492d23665c8ea0113cf Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Fri, 16 Mar 2018 20:31:55 +0100
+Subject: mmc: add delay after power class selection
+
+This seems to fix issue with sporadic ETIMEOUT in eMMC cache
+initialization on second generation TBS A711 tablet.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/mmc/core/mmc.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c
+index 6a23be214543..8ef20ffc9828 100644
+--- a/drivers/mmc/core/mmc.c
++++ b/drivers/mmc/core/mmc.c
+@@ -1840,6 +1840,8 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr,
+ 	 */
+ 	mmc_select_powerclass(card);
+ 
++	msleep(20);
++
+ 	/*
+ 	 * Enable HPI feature (if supported)
+ 	 */
+@@ -1858,6 +1860,8 @@ static int mmc_init_card(struct mmc_host *host, u32 ocr,
+ 		}
+ 	}
+ 
++	msleep(20);
++
+ 	/*
+ 	 * If cache size is higher than 0, this indicates the existence of cache
+ 	 * and it can be turned on. Note that some eMMCs from Micron has been
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/mmc-dw-mmc-rockchip-fix-sdmmc-after-soft-reboot.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/mmc-dw-mmc-rockchip-fix-sdmmc-after-soft-reboot.patch
new file mode 100644
index 000000000000..01b6d0777ad2
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/mmc-dw-mmc-rockchip-fix-sdmmc-after-soft-reboot.patch
@@ -0,0 +1,52 @@
+From a276625b2b8b781c6e50fb66ddc747a8c761c076 Mon Sep 17 00:00:00 2001
+From: Peter Geis <pgwipeout@gmail.com>
+Date: Sat, 22 Jan 2022 20:35:39 +0000
+Subject: mmc: dw-mmc-rockchip: fix sdmmc after soft reboot
+
+During shutdown the dw-mmc driver shuts down the vqmmc regulator.
+This leads to situations where the sdmmc is unavailable after a soft
+reboot.
+Fix this by ensuring the vqmmc regulator is powered up on kernel
+shutdown.
+
+Signed-off-by: Peter Geis <pgwipeout@gmail.com>
+---
+ drivers/mmc/host/dw_mmc-rockchip.c | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/drivers/mmc/host/dw_mmc-rockchip.c b/drivers/mmc/host/dw_mmc-rockchip.c
+index baa23b517731..42edf219623b 100644
+--- a/drivers/mmc/host/dw_mmc-rockchip.c
++++ b/drivers/mmc/host/dw_mmc-rockchip.c
+@@ -10,6 +10,7 @@
+ #include <linux/of_address.h>
+ #include <linux/mmc/slot-gpio.h>
+ #include <linux/pm_runtime.h>
++#include <linux/regulator/consumer.h>
+ #include <linux/slab.h>
+ 
+ #include "dw_mmc.h"
+@@ -575,9 +576,20 @@ static const struct dev_pm_ops dw_mci_rockchip_dev_pm_ops = {
+ 			   NULL)
+ };
+ 
++static void dw_mci_rockchip_shutdown(struct platform_device *pdev)
++{
++	struct dw_mci *host = dev_get_drvdata(&pdev->dev);
++	struct mmc_host *mmc = host->slot->mmc;
++
++	if (!IS_ERR(mmc->supply.vqmmc) && !(host->vqmmc_enabled))
++		if(!regulator_enable(mmc->supply.vqmmc))
++			host->vqmmc_enabled = true;
++}
++
+ static struct platform_driver dw_mci_rockchip_pltfm_driver = {
+ 	.probe		= dw_mci_rockchip_probe,
+ 	.remove		= dw_mci_rockchip_remove,
++	.shutdown	= dw_mci_rockchip_shutdown,
+ 	.driver		= {
+ 		.name		= "dwmmc_rockchip",
+ 		.probe_type	= PROBE_PREFER_ASYNCHRONOUS,
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/mmc-sunxi-mmc-Remove-runtime-PM.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/mmc-sunxi-mmc-Remove-runtime-PM.patch
new file mode 100644
index 000000000000..808b333b01fc
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/mmc-sunxi-mmc-Remove-runtime-PM.patch
@@ -0,0 +1,143 @@
+From 2cdaf7e64d4df7a1f4cc2be5f04d0831cc87b0a6 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 15 Feb 2021 09:11:16 +0100
+Subject: mmc: sunxi-mmc: Remove runtime-PM
+
+With runtime PM I get a lot of errors like (on H5/H6 f2fs formatted
+rootfs):
+
+[81360.499781] mmc_erase: group start error -110, status 0x0
+[81360.550703] mmc_erase: group start error -110, status 0x0
+[81360.599594] sunxi-mmc 4020000.mmc: data error, sending stop command
+[81360.599611] sunxi-mmc 4020000.mmc: send stop command failed
+[83474.053131] mmc_erase: group start error -110, status 0x0
+[83474.104043] mmc_erase: group start error -110, status 0x0
+[83850.888258] mmc_erase: group start error -110, status 0x0
+[83850.938810] mmc_erase: group start error -110, status 0x0
+[83850.989808] mmc_erase: group start error -110, status 0x0
+[83851.040888] mmc_erase: group start error -110, status 0x0
+[83851.091908] mmc_erase: group start error -110, status 0x0
+[83851.142938] mmc_erase: group start error -110, status 0x0
+[83851.193806] sunxi-mmc 4020000.mmc: data error, sending stop command
+[83851.193825] sunxi-mmc 4020000.mmc: send stop command failed
+[83851.201040] sunxi-mmc 4020000.mmc: data error, sending stop command
+[83851.201062] sunxi-mmc 4020000.mmc: send stop command failed
+[83851.720183] mmc_erase: group start error -110, status 0x0
+[83851.770866] mmc_erase: group start error -110, status 0x0
+[83851.821418] mmc_erase: group start error -110, status 0x0
+[83851.872081] mmc_erase: group start error -110, status 0x0
+[83851.922757] mmc_erase: group start error -110, status 0x0
+[83851.999497] mmc_erase: group start error -110, status 0x0
+[83852.050151] mmc_erase: group start error -110, status 0x0
+[83852.101319] mmc_erase: group start error -110, status 0x0
+[83852.152189] mmc_erase: group start error -110, status 0x0
+[83852.202866] mmc_erase: group start error -110, status 0x0
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/mmc/host/sunxi-mmc.c | 35 +++++++++++++++++++----------------
+ 1 file changed, 19 insertions(+), 16 deletions(-)
+
+diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
+index 1508eead5d01..30b596562281 100644
+--- a/drivers/mmc/host/sunxi-mmc.c
++++ b/drivers/mmc/host/sunxi-mmc.c
+@@ -949,9 +949,15 @@ static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+ {
+ 	struct sunxi_mmc_host *host = mmc_priv(mmc);
+ 
++	if (ios->power_mode == MMC_POWER_OFF)
++		sunxi_mmc_reset_host(host);
++
+ 	sunxi_mmc_card_power(host, ios);
+ 	sunxi_mmc_set_bus_width(host, ios->bus_width);
+ 	sunxi_mmc_set_clk(host, ios);
++
++	if (ios->power_mode == MMC_POWER_UP)
++		sunxi_mmc_init_host(host);
+ }
+ 
+ static int sunxi_mmc_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios)
+@@ -977,8 +983,8 @@ static void sunxi_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
+ 	unsigned long flags;
+ 	u32 imask;
+ 
+-	if (enable)
+-		pm_runtime_get_noresume(host->dev);
++	//if (enable)
++		//pm_runtime_get_noresume(host->dev);
+ 
+ 	spin_lock_irqsave(&host->lock, flags);
+ 
+@@ -993,8 +999,8 @@ static void sunxi_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
+ 	mmc_writel(host, REG_IMASK, imask);
+ 	spin_unlock_irqrestore(&host->lock, flags);
+ 
+-	if (!enable)
+-		pm_runtime_put_noidle(host->mmc->parent);
++	//if (!enable)
++		//pm_runtime_put_noidle(host->mmc->parent);
+ }
+ 
+ static void sunxi_mmc_hw_reset(struct mmc_host *mmc)
+@@ -1464,10 +1470,10 @@ static int sunxi_mmc_probe(struct platform_device *pdev)
+ 	if (ret)
+ 		goto error_free_dma;
+ 
+-	pm_runtime_set_active(&pdev->dev);
+-	pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
+-	pm_runtime_use_autosuspend(&pdev->dev);
+-	pm_runtime_enable(&pdev->dev);
++	//pm_runtime_set_active(&pdev->dev);
++	//pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
++	//pm_runtime_use_autosuspend(&pdev->dev);
++	//pm_runtime_enable(&pdev->dev);
+ 
+ 	ret = mmc_add_host(mmc);
+ 	if (ret)
+@@ -1492,11 +1498,11 @@ static void sunxi_mmc_remove(struct platform_device *pdev)
+ 	struct sunxi_mmc_host *host = mmc_priv(mmc);
+ 
+ 	mmc_remove_host(mmc);
+-	pm_runtime_disable(&pdev->dev);
+-	if (!pm_runtime_status_suspended(&pdev->dev)) {
++	//pm_runtime_disable(&pdev->dev);
++	//if (!pm_runtime_status_suspended(&pdev->dev)) {
+ 		disable_irq(host->irq);
+ 		sunxi_mmc_disable(host);
+-	}
++	//}
+ 	dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
+ 	mmc_free_host(mmc);
+ }
+@@ -1531,7 +1537,6 @@ static int sunxi_mmc_runtime_suspend(struct device *dev)
+ 	 * Disabling the irq  will prevent this.
+ 	 */
+ 	disable_irq(host->irq);
+-	sunxi_mmc_reset_host(host);
+ 	sunxi_mmc_disable(host);
+ 
+ 	return 0;
+@@ -1539,8 +1544,6 @@ static int sunxi_mmc_runtime_suspend(struct device *dev)
+ #endif
+ 
+ static const struct dev_pm_ops sunxi_mmc_pm_ops = {
+-	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
+-				pm_runtime_force_resume)
+ 	SET_RUNTIME_PM_OPS(sunxi_mmc_runtime_suspend,
+ 			   sunxi_mmc_runtime_resume,
+ 			   NULL)
+@@ -1550,8 +1553,8 @@ static struct platform_driver sunxi_mmc_driver = {
+ 	.driver = {
+ 		.name	= "sunxi-mmc",
+ 		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
+-		.of_match_table = sunxi_mmc_of_match,
+-		.pm = &sunxi_mmc_pm_ops,
++		.of_match_table = of_match_ptr(sunxi_mmc_of_match),
++		//.pm = &sunxi_mmc_pm_ops,
+ 	},
+ 	.probe		= sunxi_mmc_probe,
+ 	.remove		= sunxi_mmc_remove,
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/mtd-spi-nor-Add-Alliance-memory-support.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/mtd-spi-nor-Add-Alliance-memory-support.patch
new file mode 100644
index 000000000000..2030dbbc2e54
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/mtd-spi-nor-Add-Alliance-memory-support.patch
@@ -0,0 +1,85 @@
+From 3b39764173b1cd726267af2c4510f1ac145c1def Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Tue, 1 Aug 2023 14:56:33 +0200
+Subject: mtd: spi-nor: Add Alliance memory support
+
+- 128MBit flash: as25f1128mq
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/mtd/spi-nor/Makefile   |  1 +
+ drivers/mtd/spi-nor/alliance.c | 24 ++++++++++++++++++++++++
+ drivers/mtd/spi-nor/core.c     |  1 +
+ drivers/mtd/spi-nor/core.h     |  1 +
+ 4 files changed, 27 insertions(+)
+ create mode 100644 drivers/mtd/spi-nor/alliance.c
+
+diff --git a/drivers/mtd/spi-nor/Makefile b/drivers/mtd/spi-nor/Makefile
+index 5dd9c35f6b6f..998876920319 100644
+--- a/drivers/mtd/spi-nor/Makefile
++++ b/drivers/mtd/spi-nor/Makefile
+@@ -1,6 +1,7 @@
+ # SPDX-License-Identifier: GPL-2.0
+ 
+ spi-nor-objs			:= core.o sfdp.o swp.o otp.o sysfs.o
++spi-nor-objs			+= alliance.o
+ spi-nor-objs			+= atmel.o
+ spi-nor-objs			+= eon.o
+ spi-nor-objs			+= esmt.o
+diff --git a/drivers/mtd/spi-nor/alliance.c b/drivers/mtd/spi-nor/alliance.c
+new file mode 100644
+index 000000000000..f3f03d458a5c
+--- /dev/null
++++ b/drivers/mtd/spi-nor/alliance.c
+@@ -0,0 +1,24 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (C) 2023, Ondrej Jirman <megi@xff.cz>
++ */
++
++#include <linux/mtd/spi-nor.h>
++
++#include "core.h"
++
++static const struct flash_info alliance_nor_parts[] = {
++	{
++		.id = SNOR_ID(0x52, 0x42, 0x18),
++		.name = "as25f1128mq",
++		.size = SZ_16M,
++		.flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB,
++		.no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
++	},
++};
++
++const struct spi_nor_manufacturer spi_nor_alliance = {
++	.name = "alliance",
++	.parts = alliance_nor_parts,
++	.nparts = ARRAY_SIZE(alliance_nor_parts),
++};
+diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
+index 7bb44fabe093..12c3b844e135 100644
+--- a/drivers/mtd/spi-nor/core.c
++++ b/drivers/mtd/spi-nor/core.c
+@@ -1967,6 +1967,7 @@ int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor)
+ }
+ 
+ static const struct spi_nor_manufacturer *manufacturers[] = {
++	&spi_nor_alliance,
+ 	&spi_nor_atmel,
+ 	&spi_nor_eon,
+ 	&spi_nor_esmt,
+diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
+index ceff412f7d65..fff7ee7c504e 100644
+--- a/drivers/mtd/spi-nor/core.h
++++ b/drivers/mtd/spi-nor/core.h
+@@ -584,6 +584,7 @@ struct sfdp {
+ };
+ 
+ /* Manufacturer drivers. */
++extern const struct spi_nor_manufacturer spi_nor_alliance;
+ extern const struct spi_nor_manufacturer spi_nor_atmel;
+ extern const struct spi_nor_manufacturer spi_nor_eon;
+ extern const struct spi_nor_manufacturer spi_nor_esmt;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/mtd-spi-nor-Add-vdd-regulator-support.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/mtd-spi-nor-Add-vdd-regulator-support.patch
new file mode 100644
index 000000000000..851e4b30a2d6
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/mtd-spi-nor-Add-vdd-regulator-support.patch
@@ -0,0 +1,33 @@
+From 397be32cffa8fe179989e754f15cdfd42d32d325 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 30 Sep 2019 11:49:54 +0200
+Subject: mtd: spi-nor: Add vdd regulator support
+
+On some boards, SPI NOR needs a regulator be enabled.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/mtd/spi-nor/core.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
+index 19eb98bd6821..7bb44fabe093 100644
+--- a/drivers/mtd/spi-nor/core.c
++++ b/drivers/mtd/spi-nor/core.c
+@@ -3596,6 +3596,13 @@ static int spi_nor_probe(struct spi_mem *spimem)
+ 	if (!nor)
+ 		return -ENOMEM;
+ 
++	ret = devm_regulator_get_enable(&spi->dev, "vdd");
++	if (ret)
++		return dev_err_probe(&spi->dev, ret,
++				     "unable to get vdd regulator\n");
++
++	msleep(5);
++
+ 	nor->spimem = spimem;
+ 	nor->dev = dev;
+ 	spi_nor_set_flash_node(nor, dev->of_node);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/net-stmmac-sun8i-Add-support-for-enabling-a-regulator-for-PHY-I.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/net-stmmac-sun8i-Add-support-for-enabling-a-regulator-for-PHY-I.patch
new file mode 100644
index 000000000000..90ae368e2223
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/net-stmmac-sun8i-Add-support-for-enabling-a-regulator-for-PHY-I.patch
@@ -0,0 +1,89 @@
+From 7b4eda27c79bedf2ce5ed68df717b53e84bf15e2 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 20 Aug 2019 14:31:38 +0200
+Subject: net: stmmac: sun8i: Add support for enabling a regulator for PHY I/O
+ pins
+
+Orange Pi 3 has two regulators that power the Realtek RTL8211E. According
+to the phy datasheet, both regulators need to be enabled at the same time.
+
+Add support for the second optional regulator, "phy-io", to the glue
+driver.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 20 ++++++++++++++++++-
+ 1 file changed, 19 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+index 9c2685cb72d2..6e82638d314a 100644
+--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+@@ -61,6 +61,8 @@ struct emac_variant {
+ /* struct sunxi_priv_data - hold all sunxi private data
+  * @ephy_clk:	reference to the optional EPHY clock for the internal PHY
+  * @regulator_phy: reference to the optional regulator
++ * @regulator_phy_io: reference to the optional regulator for
++ *		PHY I/O pins
+  * @rst_ephy:	reference to the optional EPHY reset for the internal PHY
+  * @variant:	reference to the current board variant
+  * @regmap:	regmap for using the syscon
+@@ -71,6 +73,7 @@ struct emac_variant {
+ struct sunxi_priv_data {
+ 	struct clk *ephy_clk;
+ 	struct regulator *regulator_phy;
++	struct regulator *regulator_phy_io;
+ 	struct reset_control *rst_ephy;
+ 	const struct emac_variant *variant;
+ 	struct regmap_field *regmap_field;
+@@ -588,10 +591,16 @@ static int sun8i_dwmac_init(struct platform_device *pdev, void *priv)
+ 	struct sunxi_priv_data *gmac = priv;
+ 	int ret;
+ 
++	ret = regulator_enable(gmac->regulator_phy_io);
++	if (ret) {
++		dev_err(&pdev->dev, "Fail to enable PHY I/O regulator\n");
++		return ret;
++	}
++
+ 	ret = regulator_enable(gmac->regulator_phy);
+ 	if (ret) {
+ 		dev_err(&pdev->dev, "Fail to enable PHY regulator\n");
+-		return ret;
++		goto err_disable_regulator_phy_io;
+ 	}
+ 
+ 	if (gmac->use_internal_phy) {
+@@ -604,6 +613,8 @@ static int sun8i_dwmac_init(struct platform_device *pdev, void *priv)
+ 
+ err_disable_regulator:
+ 	regulator_disable(gmac->regulator_phy);
++err_disable_regulator_phy_io:
++	regulator_disable(gmac->regulator_phy_io);
+ 
+ 	return ret;
+ }
+@@ -1049,6 +1060,7 @@ static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv)
+ 		sun8i_dwmac_unpower_internal_phy(gmac);
+ 
+ 	regulator_disable(gmac->regulator_phy);
++	regulator_disable(gmac->regulator_phy_io);
+ }
+ 
+ static void sun8i_dwmac_set_mac_loopback(void __iomem *ioaddr, bool enable)
+@@ -1177,6 +1189,12 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
+ 		return dev_err_probe(dev, PTR_ERR(gmac->regulator_phy),
+ 				     "Failed to get PHY regulator\n");
+ 
++	/* Optional regulator for PHY I/O pins */
++	gmac->regulator_phy_io = devm_regulator_get(dev, "phy-io");
++	if (IS_ERR(gmac->regulator_phy_io))
++		return dev_err_probe(dev, PTR_ERR(gmac->regulator_phy_io),
++				     "Failed to get PHY I/O regulator\n");
++
+ 	/* The "GMAC clock control" register might be located in the
+ 	 * CCU address range (on the R40), or the system control address
+ 	 * range (on most other sun8i and later SoCs).
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/net-stmmac-sun8i-Rename-PHY-regulator-variable-to-regulator_phy.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/net-stmmac-sun8i-Rename-PHY-regulator-variable-to-regulator_phy.patch
new file mode 100644
index 000000000000..21f3ba8b2c06
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/net-stmmac-sun8i-Rename-PHY-regulator-variable-to-regulator_phy.patch
@@ -0,0 +1,81 @@
+From e75d0648a45ace112ac64688f87b05b23b8bb1c5 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 20 Aug 2019 14:29:29 +0200
+Subject: net: stmmac: sun8i: Rename PHY regulator variable to regulator_phy
+
+We'll be adding further optional regulators, and this makes it clearer
+what the regulator is for.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../net/ethernet/stmicro/stmmac/dwmac-sun8i.c  | 18 +++++++++---------
+ 1 file changed, 9 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+index 7983df0d0eaa..9c2685cb72d2 100644
+--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+@@ -60,7 +60,7 @@ struct emac_variant {
+ 
+ /* struct sunxi_priv_data - hold all sunxi private data
+  * @ephy_clk:	reference to the optional EPHY clock for the internal PHY
+- * @regulator:	reference to the optional regulator
++ * @regulator_phy: reference to the optional regulator
+  * @rst_ephy:	reference to the optional EPHY reset for the internal PHY
+  * @variant:	reference to the current board variant
+  * @regmap:	regmap for using the syscon
+@@ -70,7 +70,7 @@ struct emac_variant {
+  */
+ struct sunxi_priv_data {
+ 	struct clk *ephy_clk;
+-	struct regulator *regulator;
++	struct regulator *regulator_phy;
+ 	struct reset_control *rst_ephy;
+ 	const struct emac_variant *variant;
+ 	struct regmap_field *regmap_field;
+@@ -588,9 +588,9 @@ static int sun8i_dwmac_init(struct platform_device *pdev, void *priv)
+ 	struct sunxi_priv_data *gmac = priv;
+ 	int ret;
+ 
+-	ret = regulator_enable(gmac->regulator);
++	ret = regulator_enable(gmac->regulator_phy);
+ 	if (ret) {
+-		dev_err(&pdev->dev, "Fail to enable regulator\n");
++		dev_err(&pdev->dev, "Fail to enable PHY regulator\n");
+ 		return ret;
+ 	}
+ 
+@@ -603,7 +603,7 @@ static int sun8i_dwmac_init(struct platform_device *pdev, void *priv)
+ 	return 0;
+ 
+ err_disable_regulator:
+-	regulator_disable(gmac->regulator);
++	regulator_disable(gmac->regulator_phy);
+ 
+ 	return ret;
+ }
+@@ -1048,7 +1048,7 @@ static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv)
+ 	if (gmac->variant->soc_has_internal_phy)
+ 		sun8i_dwmac_unpower_internal_phy(gmac);
+ 
+-	regulator_disable(gmac->regulator);
++	regulator_disable(gmac->regulator_phy);
+ }
+ 
+ static void sun8i_dwmac_set_mac_loopback(void __iomem *ioaddr, bool enable)
+@@ -1172,9 +1172,9 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
+ 	}
+ 
+ 	/* Optional regulator for PHY */
+-	gmac->regulator = devm_regulator_get(dev, "phy");
+-	if (IS_ERR(gmac->regulator))
+-		return dev_err_probe(dev, PTR_ERR(gmac->regulator),
++	gmac->regulator_phy = devm_regulator_get(dev, "phy");
++	if (IS_ERR(gmac->regulator_phy))
++		return dev_err_probe(dev, PTR_ERR(gmac->regulator_phy),
+ 				     "Failed to get PHY regulator\n");
+ 
+ 	/* The "GMAC clock control" register might be located in the
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/net-stmmac-sun8i-Use-devm_regulator_get-for-PHY-regulator.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/net-stmmac-sun8i-Use-devm_regulator_get-for-PHY-regulator.patch
new file mode 100644
index 000000000000..f7b3898ce43f
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/net-stmmac-sun8i-Use-devm_regulator_get-for-PHY-regulator.patch
@@ -0,0 +1,84 @@
+From e79f7a9f2ca1b767b63f924b43ee363e850a911c Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Wed, 27 Mar 2019 13:21:06 +0100
+Subject: net: stmmac: sun8i: Use devm_regulator_get for PHY regulator
+
+Use devm_regulator_get instead of devm_regulator_get_optional and rely
+on dummy supply. This avoids NULL checks before regulator_enable/disable
+calls.
+
+This path also improves error reporting, because we now report both
+use of dummy supply and error during registration with more detail,
+instead of generic info level message "No regulator found" that
+was reported previously on errors and lack of regulator property in DT.
+
+Finally, we'll be adding further optional regulators, and the overall
+code will be simpler.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 27 +++++++------------
+ 1 file changed, 10 insertions(+), 17 deletions(-)
+
+diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+index 4b7b2582a120..7983df0d0eaa 100644
+--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+@@ -588,12 +588,10 @@ static int sun8i_dwmac_init(struct platform_device *pdev, void *priv)
+ 	struct sunxi_priv_data *gmac = priv;
+ 	int ret;
+ 
+-	if (gmac->regulator) {
+-		ret = regulator_enable(gmac->regulator);
+-		if (ret) {
+-			dev_err(&pdev->dev, "Fail to enable regulator\n");
+-			return ret;
+-		}
++	ret = regulator_enable(gmac->regulator);
++	if (ret) {
++		dev_err(&pdev->dev, "Fail to enable regulator\n");
++		return ret;
+ 	}
+ 
+ 	if (gmac->use_internal_phy) {
+@@ -605,8 +603,7 @@ static int sun8i_dwmac_init(struct platform_device *pdev, void *priv)
+ 	return 0;
+ 
+ err_disable_regulator:
+-	if (gmac->regulator)
+-		regulator_disable(gmac->regulator);
++	regulator_disable(gmac->regulator);
+ 
+ 	return ret;
+ }
+@@ -1051,8 +1048,7 @@ static void sun8i_dwmac_exit(struct platform_device *pdev, void *priv)
+ 	if (gmac->variant->soc_has_internal_phy)
+ 		sun8i_dwmac_unpower_internal_phy(gmac);
+ 
+-	if (gmac->regulator)
+-		regulator_disable(gmac->regulator);
++	regulator_disable(gmac->regulator);
+ }
+ 
+ static void sun8i_dwmac_set_mac_loopback(void __iomem *ioaddr, bool enable)
+@@ -1176,13 +1172,10 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
+ 	}
+ 
+ 	/* Optional regulator for PHY */
+-	gmac->regulator = devm_regulator_get_optional(dev, "phy");
+-	if (IS_ERR(gmac->regulator)) {
+-		if (PTR_ERR(gmac->regulator) == -EPROBE_DEFER)
+-			return -EPROBE_DEFER;
+-		dev_info(dev, "No regulator found\n");
+-		gmac->regulator = NULL;
+-	}
++	gmac->regulator = devm_regulator_get(dev, "phy");
++	if (IS_ERR(gmac->regulator))
++		return dev_err_probe(dev, PTR_ERR(gmac->regulator),
++				     "Failed to get PHY regulator\n");
+ 
+ 	/* The "GMAC clock control" register might be located in the
+ 	 * CCU address range (on the R40), or the system control address
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/nfc-pn544-Add-support-for-VBAT-PVDD-regulators.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/nfc-pn544-Add-support-for-VBAT-PVDD-regulators.patch
new file mode 100644
index 000000000000..dc481d76c7ab
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/nfc-pn544-Add-support-for-VBAT-PVDD-regulators.patch
@@ -0,0 +1,106 @@
+From 1734c610a0f7ac87fbbad98ffc8fc13b5b84d066 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Fri, 10 Nov 2017 14:29:26 +0100
+Subject: nfc: pn544: Add support for VBAT/PVDD regulators
+
+Regulators are required, so this can't go into mainline as is.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/nfc/pn544/i2c.c | 31 +++++++++++++++++++++++++++++--
+ 1 file changed, 29 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/nfc/pn544/i2c.c b/drivers/nfc/pn544/i2c.c
+index a0dfb3f98d5a..4b980d87f7ae 100644
+--- a/drivers/nfc/pn544/i2c.c
++++ b/drivers/nfc/pn544/i2c.c
+@@ -16,6 +16,7 @@
+ #include <linux/nfc.h>
+ #include <linux/firmware.h>
+ #include <linux/gpio/consumer.h>
++#include <linux/regulator/consumer.h>
+ 
+ #include <linux/unaligned.h>
+ 
+@@ -59,6 +60,14 @@ MODULE_DEVICE_TABLE(acpi, pn544_hci_i2c_acpi_match);
+ 
+ #define PN544_HCI_I2C_DRIVER_NAME "pn544_hci_i2c"
+ 
++/* regulator supplies */
++static const char * const pn544_supply_names[] = {
++	"PVDD",  /* Digital Core (1.8V) supply */
++	"VBAT",  /* Analog (2.9V-5.5V) supply */
++};
++
++#define PN544_NUM_SUPPLIES ARRAY_SIZE(pn544_supply_names)
++
+ /*
+  * Exposed through the 4 most significant bytes
+  * from the HCI SW_VERSION first byte, a.k.a.
+@@ -148,6 +157,7 @@ struct pn544_i2c_phy {
+ 	struct i2c_client *i2c_dev;
+ 	struct nfc_hci_dev *hdev;
+ 
++	struct regulator_bulk_data supplies[PN544_NUM_SUPPLIES];
+ 	struct gpio_desc *gpiod_en;
+ 	struct gpio_desc *gpiod_fw;
+ 
+@@ -238,6 +248,13 @@ static void pn544_hci_i2c_enable_mode(struct pn544_i2c_phy *phy, int run_mode)
+ static int pn544_hci_i2c_enable(void *phy_id)
+ {
+ 	struct pn544_i2c_phy *phy = phy_id;
++	int ret;
++
++	pr_info("%s\n", __func__);
++
++	ret = regulator_bulk_enable(PN544_NUM_SUPPLIES, phy->supplies);
++	if (ret)
++		return ret;
+ 
+ 	pn544_hci_i2c_enable_mode(phy, PN544_HCI_MODE);
+ 
+@@ -260,6 +277,8 @@ static void pn544_hci_i2c_disable(void *phy_id)
+ 	gpiod_set_value_cansleep(phy->gpiod_en, !phy->en_polarity);
+ 	usleep_range(10000, 15000);
+ 
++	regulator_bulk_disable(PN544_NUM_SUPPLIES, phy->supplies);
++
+ 	phy->powered = 0;
+ }
+ 
+@@ -366,7 +385,7 @@ static int pn544_hci_i2c_read(struct pn544_i2c_phy *phy, struct sk_buff **skb)
+ 
+ 	if ((len < (PN544_HCI_I2C_LLC_MIN_SIZE - 1)) ||
+ 	    (len > (PN544_HCI_I2C_LLC_MAX_SIZE - 1))) {
+-		nfc_err(&client->dev, "invalid len byte\n");
++		nfc_err(&client->dev, "invalid len byte %hhx\n", len);
+ 		r = -EBADMSG;
+ 		goto flush;
+ 	}
+@@ -868,7 +887,7 @@ static int pn544_hci_i2c_probe(struct i2c_client *client)
+ {
+ 	struct device *dev = &client->dev;
+ 	struct pn544_i2c_phy *phy;
+-	int r = 0;
++	int r = 0, i;
+ 
+ 	if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
+ 		nfc_err(&client->dev, "Need I2C_FUNC_I2C\n");
+@@ -890,6 +909,14 @@ static int pn544_hci_i2c_probe(struct i2c_client *client)
+ 	if (r)
+ 		dev_dbg(dev, "Unable to add GPIO mapping table\n");
+ 
++	for (i = 0; i < PN544_NUM_SUPPLIES; i++)
++		phy->supplies[i].supply = pn544_supply_names[i];
++
++	r = devm_regulator_bulk_get(&client->dev, PN544_NUM_SUPPLIES,
++				    phy->supplies);
++	if (r)
++		return r;
++
+ 	/* Get EN GPIO */
+ 	phy->gpiod_en = devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW);
+ 	if (IS_ERR(phy->gpiod_en)) {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/of-property-fw_devlink-Support-allwinner-sram-links.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/of-property-fw_devlink-Support-allwinner-sram-links.patch
new file mode 100644
index 000000000000..228851a4fd49
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/of-property-fw_devlink-Support-allwinner-sram-links.patch
@@ -0,0 +1,58 @@
+From ffba28a2260e995a9170bea3a008d84a130fa583 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 15 May 2021 21:43:44 +0200
+Subject: of: property: fw_devlink: Support allwinner,sram links
+
+allwinner,sram property points to a node representing section of SRAM,
+which is implemented by its ancestor (syscon), so we link to the
+parent of parent of the actual SRAM section node that the link points
+to.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/of/property.c | 22 ++++++++++++++++++++++
+ 1 file changed, 22 insertions(+)
+
+diff --git a/drivers/of/property.c b/drivers/of/property.c
+index 208d922cc24c..8c9f3ea663a6 100644
+--- a/drivers/of/property.c
++++ b/drivers/of/property.c
+@@ -1455,6 +1455,27 @@ static struct device_node *parse_remote_endpoint(struct device_node *np,
+ 	return of_graph_get_remote_port_parent(np);
+ }
+ 
++static struct device_node *parse_allwinner_sram(struct device_node *np,
++						const char *prop_name, int index)
++{
++	struct device_node *sram_node;
++
++	if (!IS_ENABLED(CONFIG_SUNXI_SRAM))
++		return NULL;
++
++	if (strcmp(prop_name, "allwinner,sram"))
++		return NULL;
++
++	if (index > 0)
++		return NULL;
++
++	sram_node = of_parse_phandle(np, prop_name, 0);
++	sram_node = of_get_parent(sram_node);
++	sram_node = of_get_parent(sram_node);
++
++	return sram_node;
++}
++
+ static const struct supplier_bindings of_supplier_bindings[] = {
+ 	{ .parse_prop = parse_clocks, },
+ 	{ .parse_prop = parse_interconnects, },
+@@ -1502,6 +1523,7 @@ static const struct supplier_bindings of_supplier_bindings[] = {
+ 		.parse_prop = parse_post_init_providers,
+ 		.fwlink_flags = FWLINK_FLAG_IGNORE,
+ 	},
++	{ .parse_prop = parse_allwinner_sram, },
+ 	{}
+ };
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/opp-core-Avoid-confusing-error-when-no-regulator-is-defined-in-.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/opp-core-Avoid-confusing-error-when-no-regulator-is-defined-in-.patch
new file mode 100644
index 000000000000..bf907bfae41c
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/opp-core-Avoid-confusing-error-when-no-regulator-is-defined-in-.patch
@@ -0,0 +1,31 @@
+From c0d7f75b2beb43824f91642088643e90e5eeb19e Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sat, 29 Oct 2022 23:16:51 +0200
+Subject: opp: core: Avoid confusing error when no regulator is defined in DT
+
+A64 GPU doesn't have a separate regulator. Avoid useless error.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/opp/core.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/opp/core.c b/drivers/opp/core.c
+index 73e9a3b2f29b..388d2622cf69 100644
+--- a/drivers/opp/core.c
++++ b/drivers/opp/core.c
+@@ -2240,6 +2240,11 @@ static int _opp_set_regulators(struct opp_table *opp_table, struct device *dev,
+ 	for (i = 0; i < count; i++) {
+ 		reg = regulator_get_optional(dev, names[i]);
+ 		if (IS_ERR(reg)) {
++			if (PTR_ERR(reg) == -ENODEV) {
++				ret = -ENODEV;
++				goto free_regulators;
++			}
++
+ 			ret = dev_err_probe(dev, PTR_ERR(reg),
+ 					    "%s: no regulator (%s) found\n",
+ 					    __func__, names[i]);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/pci-Workaround-ITS-timeouts-on-poweroff-reboot-on-Orange-Pi-5-P.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/pci-Workaround-ITS-timeouts-on-poweroff-reboot-on-Orange-Pi-5-P.patch
new file mode 100644
index 000000000000..2fb7a14ffb04
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/pci-Workaround-ITS-timeouts-on-poweroff-reboot-on-Orange-Pi-5-P.patch
@@ -0,0 +1,32 @@
+From a624070758979300cfc1b684162a2fb881773cae Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Wed, 14 Jun 2023 00:48:21 +0200
+Subject: pci: Workaround ITS timeouts on poweroff/reboot on Orange Pi 5 Plus
+
+Call to pci_free_irq_vectors on PCIE2x ports causes ITS timeout messages
+and delayed shutdown/reboot (by up to a minute).
+
+The root cause will be elsewhere. This is not for upstream. Anyway,
+there should be no harm from this, since we're shutting down anyway.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/pci/pcie/portdrv.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/pci/pcie/portdrv.c b/drivers/pci/pcie/portdrv.c
+index e8318fd5f6ed..22d65c83396e 100644
+--- a/drivers/pci/pcie/portdrv.c
++++ b/drivers/pci/pcie/portdrv.c
+@@ -743,7 +743,7 @@ static void pcie_portdrv_shutdown(struct pci_dev *dev)
+ 		pm_runtime_dont_use_autosuspend(&dev->dev);
+ 	}
+ 
+-	pcie_port_device_remove(dev);
++	device_for_each_child(&dev->dev, NULL, remove_iter);
+ }
+ 
+ static pci_ers_result_t pcie_portdrv_error_detected(struct pci_dev *dev,
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/phy-allwinner-sun4i-usb-Add-support-for-usb_role_switch.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/phy-allwinner-sun4i-usb-Add-support-for-usb_role_switch.patch
new file mode 100644
index 000000000000..bb0c22ce8b44
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/phy-allwinner-sun4i-usb-Add-support-for-usb_role_switch.patch
@@ -0,0 +1,146 @@
+From 0179ed04b8454eca07abc91a41c213423f4d1b1d Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 8 Jun 2020 00:11:06 +0200
+Subject: phy: allwinner: sun4i-usb: Add support for usb_role_switch
+
+This allow controlling the usb0 data role from a typec port driver.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/phy/allwinner/Kconfig         |  1 +
+ drivers/phy/allwinner/phy-sun4i-usb.c | 51 ++++++++++++++++++++++++++-
+ 2 files changed, 51 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/phy/allwinner/Kconfig b/drivers/phy/allwinner/Kconfig
+index fb584518b2d0..e93a53139460 100644
+--- a/drivers/phy/allwinner/Kconfig
++++ b/drivers/phy/allwinner/Kconfig
+@@ -12,6 +12,7 @@ config PHY_SUN4I_USB
+ 	depends on USB_SUPPORT
+ 	select GENERIC_PHY
+ 	select USB_COMMON
++	select USB_ROLE_SWITCH
+ 	help
+ 	  Enable this to support the transceiver that is part of Allwinner
+ 	  sunxi SoCs.
+diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c
+index 29b8fd4b9351..3a42865f9a5b 100644
+--- a/drivers/phy/allwinner/phy-sun4i-usb.c
++++ b/drivers/phy/allwinner/phy-sun4i-usb.c
+@@ -31,6 +31,7 @@
+ #include <linux/reset.h>
+ #include <linux/spinlock.h>
+ #include <linux/usb/of.h>
++#include <linux/usb/role.h>
+ #include <linux/workqueue.h>
+ 
+ #define REG_ISCR			0x00
+@@ -139,6 +140,9 @@ struct sun4i_usb_phy_data {
+ 	int id_det;
+ 	int vbus_det;
+ 	struct delayed_work detect;
++	struct usb_role_switch_desc switch_desc;
++	struct usb_role_switch *role_switch;
++	int usb_role;
+ };
+ 
+ #define to_sun4i_usb_phy_data(phy) \
+@@ -401,6 +405,9 @@ static int sun4i_usb_phy_exit(struct phy *_phy)
+ 
+ static int sun4i_usb_phy0_get_id_det(struct sun4i_usb_phy_data *data)
+ {
++	if (data->usb_role >= 0)
++		return data->usb_role == USB_ROLE_HOST ? 0 : 1;
++
+ 	switch (data->dr_mode) {
+ 	case USB_DR_MODE_OTG:
+ 		if (data->id_det_gpio)
+@@ -417,6 +424,9 @@ static int sun4i_usb_phy0_get_id_det(struct sun4i_usb_phy_data *data)
+ 
+ static int sun4i_usb_phy0_get_vbus_det(struct sun4i_usb_phy_data *data)
+ {
++	if (data->usb_role >= 0)
++		return data->usb_role == USB_ROLE_NONE ? 0 : 1;
++
+ 	if (data->vbus_det_gpio)
+ 		return gpiod_get_value_cansleep(data->vbus_det_gpio);
+ 
+@@ -436,7 +446,7 @@ static int sun4i_usb_phy0_get_vbus_det(struct sun4i_usb_phy_data *data)
+ 
+ static bool sun4i_usb_phy0_have_vbus_det(struct sun4i_usb_phy_data *data)
+ {
+-	return data->vbus_det_gpio || data->vbus_power_supply;
++	return data->usb_role >= 0 || data->vbus_det_gpio || data->vbus_power_supply;
+ }
+ 
+ static bool sun4i_usb_phy0_poll(struct sun4i_usb_phy_data *data)
+@@ -695,6 +705,24 @@ static struct phy *sun4i_usb_phy_xlate(struct device *dev,
+ 	return data->phys[args->args[0]].phy;
+ }
+ 
++static int sun4i_usb_role_set(struct usb_role_switch *sw, enum usb_role role)
++{
++	struct sun4i_usb_phy_data *data = usb_role_switch_get_drvdata(sw);
++
++	data->usb_role = role;
++	queue_delayed_work(system_wq, &data->detect, 0);
++
++	return 0;
++}
++
++static enum usb_role sun4i_usb_role_get(struct usb_role_switch *sw)
++{
++	struct sun4i_usb_phy_data *data = usb_role_switch_get_drvdata(sw);
++	int role = sun4i_usb_phy0_get_id_det(data) ? USB_ROLE_DEVICE : USB_ROLE_HOST;
++
++	return data->usb_role >= 0 ? data->usb_role : role;
++}
++
+ static void sun4i_usb_phy_remove(struct platform_device *pdev)
+ {
+ 	struct device *dev = &pdev->dev;
+@@ -708,6 +736,8 @@ static void sun4i_usb_phy_remove(struct platform_device *pdev)
+ 		devm_free_irq(dev, data->vbus_det_irq, data);
+ 
+ 	cancel_delayed_work_sync(&data->detect);
++
++	usb_role_switch_unregister(data->role_switch);
+ }
+ 
+ static const unsigned int sun4i_usb_phy0_cable[] = {
+@@ -735,6 +765,8 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
+ 	if (!data->cfg)
+ 		return -EINVAL;
+ 
++	data->usb_role = -1;
++
+ 	data->base = devm_platform_ioremap_resource_byname(pdev, "phy_ctrl");
+ 	if (IS_ERR(data->base))
+ 		return PTR_ERR(data->base);
+@@ -895,6 +927,23 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
+ 		return PTR_ERR(phy_provider);
+ 	}
+ 
++	/* setup role switcher */
++	data->switch_desc.name = "usb0";
++	data->switch_desc.fwnode = dev_fwnode(dev);
++	data->switch_desc.set = sun4i_usb_role_set;
++	data->switch_desc.get = sun4i_usb_role_get;
++	data->switch_desc.driver_data = data;
++
++	/*
++	 * Don't interfere with the default behavior of this driver until
++	 * the consumer of the role switch uses the switch for the first time.
++	 */
++	data->role_switch = usb_role_switch_register(dev, &data->switch_desc);
++	if (IS_ERR(data->role_switch)) {
++		dev_warn(dev, "Unable to register Role Switch\n");
++		data->role_switch = NULL;
++	}
++
+ 	dev_dbg(dev, "successfully loaded\n");
+ 
+ 	return 0;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/power-axp20x_battery-Allow-to-set-target-voltage-to-4.35V.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/power-axp20x_battery-Allow-to-set-target-voltage-to-4.35V.patch
new file mode 100644
index 000000000000..173af001b73d
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/power-axp20x_battery-Allow-to-set-target-voltage-to-4.35V.patch
@@ -0,0 +1,31 @@
+From aa242f8de59b3c71dd8541e635ddcb3fbe319ff2 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Thu, 27 Feb 2020 00:53:17 +0100
+Subject: power: axp20x_battery: Allow to set target voltage to 4.35V
+
+Some devices have batteries that allow that.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/power/supply/axp20x_battery.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/power/supply/axp20x_battery.c b/drivers/power/supply/axp20x_battery.c
+index 3c3158f31a48..96d2856ef318 100644
+--- a/drivers/power/supply/axp20x_battery.c
++++ b/drivers/power/supply/axp20x_battery.c
+@@ -629,6 +629,11 @@ static int axp20x_battery_set_max_voltage(struct axp20x_batt_ps *axp20x_batt,
+ 		val = AXP20X_CHRG_CTRL1_TGT_4_2V;
+ 		break;
+ 
++	case 4350000:
++	case 4360000:
++		val = AXP20X_CHRG_CTRL1_TGT_4_36V;
++		break;
++
+ 	default:
+ 		/*
+ 		 * AXP20x max voltage can be set to 4.36V and AXP22X max voltage
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/power-axp803-Add-interrupts-for-low-battery-power-condition.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/power-axp803-Add-interrupts-for-low-battery-power-condition.patch
new file mode 100644
index 000000000000..b5db132dfb13
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/power-axp803-Add-interrupts-for-low-battery-power-condition.patch
@@ -0,0 +1,43 @@
+From 3128559dbbdafac2ca2b68bf52d1472b349dd330 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 14 Mar 2021 15:49:34 +0100
+Subject: power: axp803: Add interrupts for low battery power condition
+
+These are necessary so that the device is woken up by interrupt
+when low on battery, to handle the condition.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/mfd/axp20x.c                  | 2 ++
+ drivers/power/supply/axp20x_battery.c | 2 ++
+ 2 files changed, 4 insertions(+)
+
+diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
+index 8ff8bc4a22b2..5da865469679 100644
+--- a/drivers/mfd/axp20x.c
++++ b/drivers/mfd/axp20x.c
+@@ -393,6 +393,8 @@ static const struct resource axp803_battery_resources[] = {
+ 	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_BATT_ACT_TEMP_HIGH_END, "BATT_ACT_TEMP_HIGH_END"),
+ 	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_BATT_ACT_TEMP_LOW, "BATT_ACT_TEMP_LOW"),
+ 	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_BATT_ACT_TEMP_LOW_END, "BATT_ACT_TEMP_LOW_END"),
++	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_LOW_PWR_LVL1, "BATT_LOW_PWR_LVL1"),
++	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_LOW_PWR_LVL2, "BATT_LOW_PWR_LVL2"),
+ };
+ 
+ static const struct resource axp803_pek_resources[] = {
+diff --git a/drivers/power/supply/axp20x_battery.c b/drivers/power/supply/axp20x_battery.c
+index 3a5f77219d83..988741b7d3be 100644
+--- a/drivers/power/supply/axp20x_battery.c
++++ b/drivers/power/supply/axp20x_battery.c
+@@ -1098,6 +1098,8 @@ static const struct axp_irq_data axp813_irqs[] = {
+ 	{ "BATT_HEALTH_GOOD",		axp20x_battery_changed_irq },
+ 	{ "BATT_CHARGING",		axp20x_battery_changed_irq },
+ 	{ "BATT_CHARGING_DONE",		axp20x_battery_changed_irq },
++	{ "BATT_LOW_PWR_LVL1",		axp20x_battery_changed_irq },
++	{ "BATT_LOW_PWR_LVL2",		axp20x_battery_changed_irq },
+ 	{ "BATT_CHG_TEMP_HIGH",		axp20x_battery_temp_hot_irq },
+ 	{ "BATT_CHG_TEMP_HIGH_END",	axp20x_battery_temp_normal_irq },
+ 	{ "BATT_CHG_TEMP_LOW",		axp20x_battery_temp_cold_irq },
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/power-supply-Add-support-for-USB_BC_ENABLED-and-USB_DCP_INPUT_C.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/power-supply-Add-support-for-USB_BC_ENABLED-and-USB_DCP_INPUT_C.patch
new file mode 100644
index 000000000000..ed3390245414
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/power-supply-Add-support-for-USB_BC_ENABLED-and-USB_DCP_INPUT_C.patch
@@ -0,0 +1,45 @@
+From d997e3a57c6e83fa651b6f9daa80ac308b17c51f Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 22 Jun 2020 02:28:01 +0200
+Subject: power: supply: Add support for USB_BC_ENABLED and
+ USB_DCP_INPUT_CURRENT_LIMIT
+
+- USB_BC_ENABLED - enabling/disabling BC 1.2 USB type detection
+- USB_DCP_INPUT_CURRENT_LIMIT - setting a default current limit for DCP/CDP
+                                ports
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/power/supply/power_supply_sysfs.c | 2 ++
+ include/linux/power_supply.h              | 2 ++
+ 2 files changed, 4 insertions(+)
+
+diff --git a/drivers/power/supply/power_supply_sysfs.c b/drivers/power/supply/power_supply_sysfs.c
+index edb058c19c9c..430d64b974c0 100644
+--- a/drivers/power/supply/power_supply_sysfs.c
++++ b/drivers/power/supply/power_supply_sysfs.c
+@@ -213,6 +213,8 @@ static struct power_supply_attr power_supply_attrs[] __ro_after_init = {
+ 	POWER_SUPPLY_ATTR(TIME_TO_FULL_AVG),
+ 	POWER_SUPPLY_ENUM_ATTR(TYPE),
+ 	POWER_SUPPLY_ENUM_ATTR(USB_TYPE),
++	POWER_SUPPLY_ATTR(USB_BC_ENABLED),
++	POWER_SUPPLY_ATTR(USB_DCP_INPUT_CURRENT_LIMIT),
+ 	POWER_SUPPLY_ENUM_ATTR(SCOPE),
+ 	POWER_SUPPLY_ATTR(PRECHARGE_CURRENT),
+ 	POWER_SUPPLY_ATTR(CHARGE_TERM_CURRENT),
+diff --git a/include/linux/power_supply.h b/include/linux/power_supply.h
+index 6ed53b292162..dec890d882c2 100644
+--- a/include/linux/power_supply.h
++++ b/include/linux/power_supply.h
+@@ -166,6 +166,8 @@ enum power_supply_property {
+ 	POWER_SUPPLY_PROP_TIME_TO_FULL_NOW,
+ 	POWER_SUPPLY_PROP_TIME_TO_FULL_AVG,
+ 	POWER_SUPPLY_PROP_TYPE, /* use power_supply.type instead */
++	POWER_SUPPLY_PROP_USB_BC_ENABLED,
++	POWER_SUPPLY_PROP_USB_DCP_INPUT_CURRENT_LIMIT,
+ 	POWER_SUPPLY_PROP_USB_TYPE,
+ 	POWER_SUPPLY_PROP_SCOPE,
+ 	POWER_SUPPLY_PROP_PRECHARGE_CURRENT,
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/power-supply-axp20x-battery-Add-support-for-POWER_SUPPLY_PROP_E.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/power-supply-axp20x-battery-Add-support-for-POWER_SUPPLY_PROP_E.patch
new file mode 100644
index 000000000000..f33ff736a084
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/power-supply-axp20x-battery-Add-support-for-POWER_SUPPLY_PROP_E.patch
@@ -0,0 +1,90 @@
+From fcfd714cac86026d77c397e3f52740ab2eb76566 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Thu, 10 Nov 2022 20:05:58 +0100
+Subject: power: supply: axp20x-battery: Add support for
+ POWER_SUPPLY_PROP_ENERGY_FULL_DESIGN
+
+Report total battery capacity.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/power/supply/axp20x_battery.c | 30 +++++++++++++++++++++++----
+ 1 file changed, 26 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/power/supply/axp20x_battery.c b/drivers/power/supply/axp20x_battery.c
+index ba7c45e4bf10..9b4b1b8d09b1 100644
+--- a/drivers/power/supply/axp20x_battery.c
++++ b/drivers/power/supply/axp20x_battery.c
+@@ -127,6 +127,7 @@ struct axp20x_batt_ps {
+ 	/* Maximum constant charge current */
+ 	unsigned int max_ccc;
+ 	const struct axp_data	*data;
++	struct power_supply_battery_info *info;
+ };
+ 
+ static int axp20x_battery_get_max_voltage(struct axp20x_batt_ps *axp20x_batt,
+@@ -460,6 +461,16 @@ static int axp20x_battery_get_prop(struct power_supply *psy,
+ 
+ 		break;
+ 
++	case POWER_SUPPLY_PROP_ENERGY_FULL_DESIGN:
++		val->intval = 0;
++		if (axp20x_batt->info)
++			val->intval = axp20x_batt->info->energy_full_design_uwh;
++		return 0;
++
++	case POWER_SUPPLY_PROP_ENERGY_EMPTY_DESIGN:
++		val->intval = 0;
++		return 0;
++
+ 	default:
+ 		return -EINVAL;
+ 	}
+@@ -914,6 +925,8 @@ static enum power_supply_property axp20x_battery_props[] = {
+ 	POWER_SUPPLY_PROP_VOLTAGE_MIN,
+ 	POWER_SUPPLY_PROP_VOLTAGE_OCV,
+ 	POWER_SUPPLY_PROP_CAPACITY,
++	POWER_SUPPLY_PROP_ENERGY_FULL_DESIGN,
++	POWER_SUPPLY_PROP_ENERGY_EMPTY_DESIGN,
+ };
+ 
+ static enum power_supply_property axp717_battery_props[] = {
+@@ -1213,12 +1226,18 @@ static const struct of_device_id axp20x_battery_ps_id[] = {
+ };
+ MODULE_DEVICE_TABLE(of, axp20x_battery_ps_id);
+ 
++static void axp20x_put_battery_info(void *data)
++{
++	struct axp20x_batt_ps *axp20x_batt = data;
++
++	power_supply_put_battery_info(axp20x_batt->batt, axp20x_batt->info);
++}
++
+ static int axp20x_power_probe(struct platform_device *pdev)
+ {
+ 	struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
+ 	struct axp20x_batt_ps *axp20x_batt;
+ 	struct power_supply_config psy_cfg = {};
+-	struct power_supply_battery_info *info;
+ 	struct device *dev = &pdev->dev;
+ 	const struct axp_irq_data *irq_data;
+ 	int irq, ret;
+@@ -1256,9 +1275,12 @@ static int axp20x_power_probe(struct platform_device *pdev)
+ 
+ 	axp20x_batt->health = POWER_SUPPLY_HEALTH_GOOD;
+ 
+-	if (!power_supply_get_battery_info(axp20x_batt->batt, &info)) {
+-		axp20x_batt->data->set_bat_info(pdev, axp20x_batt, info);
+-		power_supply_put_battery_info(axp20x_batt->batt, info);
++	if (!power_supply_get_battery_info(axp20x_batt->batt, &axp20x_batt->info)) {
++		axp20x_batt->data->set_bat_info(pdev, axp20x_batt, axp20x_batt->info);
++
++		ret = devm_add_action_or_reset(&pdev->dev, axp20x_put_battery_info, axp20x_batt);
++		if (ret)
++			return ret;
+ 	}
+ 
+ 	/* Request irqs after registering, as irqs may trigger immediately */
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/power-supply-axp20x-battery-Enable-poweron-by-RTC-alarm.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/power-supply-axp20x-battery-Enable-poweron-by-RTC-alarm.patch
new file mode 100644
index 000000000000..82a1d06936ca
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/power-supply-axp20x-battery-Enable-poweron-by-RTC-alarm.patch
@@ -0,0 +1,35 @@
+From 1f7bdbc2a3c8d4b6deb77a4ef6b7bf5dada6a662 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sat, 27 Aug 2022 20:50:43 +0200
+Subject: power: supply: axp20x-battery: Enable poweron by RTC alarm
+
+For the Pinephone to be able to poweron on RTC alarm, some bits in
+PMIC need to be enabled. This will cause PMIC to be wakeable by
+SoC pulling the interrupt line low.
+
+This may need some coordination from a bootloader.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/power/supply/axp20x_battery.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/drivers/power/supply/axp20x_battery.c b/drivers/power/supply/axp20x_battery.c
+index 1899af1810fd..ba7c45e4bf10 100644
+--- a/drivers/power/supply/axp20x_battery.c
++++ b/drivers/power/supply/axp20x_battery.c
+@@ -1333,6 +1333,11 @@ static int axp20x_power_probe(struct platform_device *pdev)
+ 		ret = regmap_update_bits(axp20x_batt->regmap, 0x84, 0x37, 0x31);
+ 		if (ret)
+ 			goto warn_bat;
++
++		// enable poweron by RTC
++		ret = regmap_update_bits(axp20x_batt->regmap, 0x8f, BIT(7), BIT(7));
++		if (ret)
++			goto warn_bat;
+ 	}
+ 
+ 	return 0;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/power-supply-axp20x-battery-Improve-probe-error-reporting.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/power-supply-axp20x-battery-Improve-probe-error-reporting.patch
new file mode 100644
index 000000000000..8da1d25fce75
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/power-supply-axp20x-battery-Improve-probe-error-reporting.patch
@@ -0,0 +1,69 @@
+From e452c5a4a3d43d07132fcd9eaf2b041bddafc3fb Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Tue, 7 Jan 2025 18:53:23 +0100
+Subject: power: supply: axp20x-battery: Improve probe error reporting
+
+Use dev_err_probe in places...
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/power/supply/axp20x_battery.c | 28 ++++++++++++---------------
+ 1 file changed, 12 insertions(+), 16 deletions(-)
+
+diff --git a/drivers/power/supply/axp20x_battery.c b/drivers/power/supply/axp20x_battery.c
+index 9b4b1b8d09b1..bab9b4a8f623 100644
+--- a/drivers/power/supply/axp20x_battery.c
++++ b/drivers/power/supply/axp20x_battery.c
+@@ -1262,16 +1262,15 @@ static int axp20x_power_probe(struct platform_device *pdev)
+ 
+ 	ret = axp20x_batt->data->cfg_iio_chan(pdev, axp20x_batt);
+ 	if (ret)
+-		return ret;
++		return dev_err_probe(&pdev->dev, ret,
++				     "failed to configure iio channels\n");
+ 
+ 	axp20x_batt->batt = devm_power_supply_register(&pdev->dev,
+ 						       axp20x_batt->data->bat_ps_desc,
+ 						       &psy_cfg);
+-	if (IS_ERR(axp20x_batt->batt)) {
+-		dev_err(&pdev->dev, "failed to register power supply: %ld\n",
+-			PTR_ERR(axp20x_batt->batt));
+-		return PTR_ERR(axp20x_batt->batt);
+-	}
++	if (IS_ERR(axp20x_batt->batt))
++		return dev_err_probe(&pdev->dev, PTR_ERR(axp20x_batt->batt),
++				     "failed to register power supply\n");
+ 
+ 	axp20x_batt->health = POWER_SUPPLY_HEALTH_GOOD;
+ 
+@@ -1286,20 +1285,17 @@ static int axp20x_power_probe(struct platform_device *pdev)
+ 	/* Request irqs after registering, as irqs may trigger immediately */
+ 	for (irq_data = axp20x_batt->data->irqs; irq_data->name; irq_data++) {
+ 		irq = platform_get_irq_byname(pdev, irq_data->name);
+-		if (irq < 0) {
+-			dev_err(&pdev->dev, "No IRQ for %s: %d\n",
+-				irq_data->name, irq);
+-			return irq;
+-		}
++		if (irq < 0)
++			return dev_err_probe(&pdev->dev, irq,
++					     "No IRQ for %s\n", irq_data->name);
++
+ 		irq = regmap_irq_get_virq(axp20x->regmap_irqc, irq);
+ 		ret = devm_request_any_context_irq(&pdev->dev, irq,
+ 						   irq_data->handler, 0,
+ 						   DRVNAME, axp20x_batt);
+-		if (ret < 0) {
+-			dev_err(&pdev->dev, "Error requesting %s IRQ: %d\n",
+-				irq_data->name, ret);
+-			return ret;
+-		}
++		if (ret < 0)
++			return dev_err_probe(&pdev->dev, ret,
++					     "Error requesting %s IRQ\n", irq_data->name);
+ 	}
+ 
+ 	/*
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/power-supply-axp20x-battery-Support-POWER_SUPPLY_PROP_CHARGE_BE.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/power-supply-axp20x-battery-Support-POWER_SUPPLY_PROP_CHARGE_BE.patch
new file mode 100644
index 000000000000..c5cd63b88fec
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/power-supply-axp20x-battery-Support-POWER_SUPPLY_PROP_CHARGE_BE.patch
@@ -0,0 +1,86 @@
+From 69e253126549eb8af47a0145651f4fc575b1332c Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sat, 2 Apr 2022 02:50:14 +0200
+Subject: power: supply: axp20x-battery: Support
+ POWER_SUPPLY_PROP_CHARGE_BEHAVIOUR
+
+Support force disabling the charger in a more standardized way.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/power/supply/axp20x_battery.c | 31 +++++++++++++++++++++++++++
+ 1 file changed, 31 insertions(+)
+
+diff --git a/drivers/power/supply/axp20x_battery.c b/drivers/power/supply/axp20x_battery.c
+index 988741b7d3be..1899af1810fd 100644
+--- a/drivers/power/supply/axp20x_battery.c
++++ b/drivers/power/supply/axp20x_battery.c
+@@ -317,6 +317,19 @@ static int axp20x_battery_get_prop(struct power_supply *psy,
+ 		val->intval = !!(reg & AXP20X_PWR_OP_BATT_PRESENT);
+ 		break;
+ 
++	case POWER_SUPPLY_PROP_CHARGE_BEHAVIOUR:
++		ret = regmap_read(axp20x_batt->regmap, AXP20X_CHRG_CTRL1,
++				  &reg);
++		if (ret)
++			return ret;
++
++		if (reg & AXP20X_CHRG_CTRL1_ENABLE)
++			val->intval = POWER_SUPPLY_CHARGE_BEHAVIOUR_AUTO;
++		else
++			val->intval = POWER_SUPPLY_CHARGE_BEHAVIOUR_INHIBIT_CHARGE;
++
++		return 0;
++
+ 	case POWER_SUPPLY_PROP_STATUS:
+ 		ret = regmap_read(axp20x_batt->regmap, AXP20X_PWR_OP_MODE,
+ 				  &reg);
+@@ -819,6 +832,21 @@ static int axp20x_battery_set_prop(struct power_supply *psy,
+ 	case POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT_MAX:
+ 		return axp20x_set_max_constant_charge_current(axp20x_batt,
+ 							      val->intval);
++	case POWER_SUPPLY_PROP_CHARGE_BEHAVIOUR:
++		switch (val->intval) {
++		case POWER_SUPPLY_CHARGE_BEHAVIOUR_AUTO:
++			return regmap_update_bits(axp20x_batt->regmap,
++						  AXP20X_CHRG_CTRL1,
++						  AXP20X_CHRG_CTRL1_ENABLE,
++						  AXP20X_CHRG_CTRL1_ENABLE);
++		case POWER_SUPPLY_CHARGE_BEHAVIOUR_INHIBIT_CHARGE:
++			return regmap_update_bits(axp20x_batt->regmap,
++						  AXP20X_CHRG_CTRL1,
++						  AXP20X_CHRG_CTRL1_ENABLE, 0);
++		default:
++			return -EINVAL;
++		}
++
+ 	case POWER_SUPPLY_PROP_STATUS:
+ 		switch (val->intval) {
+ 		case POWER_SUPPLY_STATUS_CHARGING:
+@@ -876,6 +904,7 @@ static enum power_supply_property axp20x_battery_props[] = {
+ 	POWER_SUPPLY_PROP_PRESENT,
+ 	POWER_SUPPLY_PROP_ONLINE,
+ 	POWER_SUPPLY_PROP_STATUS,
++	POWER_SUPPLY_PROP_CHARGE_BEHAVIOUR,
+ 	POWER_SUPPLY_PROP_VOLTAGE_NOW,
+ 	POWER_SUPPLY_PROP_CURRENT_NOW,
+ 	POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT,
+@@ -907,6 +936,7 @@ static int axp20x_battery_prop_writeable(struct power_supply *psy,
+ 	return psp == POWER_SUPPLY_PROP_STATUS ||
+ 	       psp == POWER_SUPPLY_PROP_VOLTAGE_MIN ||
+ 	       psp == POWER_SUPPLY_PROP_VOLTAGE_MAX ||
++	       psp == POWER_SUPPLY_PROP_CHARGE_BEHAVIOUR ||
+ 	       psp == POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT ||
+ 	       psp == POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT_MAX;
+ }
+@@ -928,6 +958,7 @@ static const struct power_supply_desc axp209_batt_ps_desc = {
+ 	.property_is_writeable = axp20x_battery_prop_writeable,
+ 	.get_property = axp20x_battery_get_prop,
+ 	.set_property = axp20x_battery_set_prop,
++	.charge_behaviours = BIT(POWER_SUPPLY_CHARGE_BEHAVIOUR_AUTO) | BIT(POWER_SUPPLY_CHARGE_BEHAVIOUR_INHIBIT_CHARGE),
+ };
+ 
+ static const struct power_supply_desc axp717_batt_ps_desc = {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/power-supply-axp20x-usb-power-Add-missing-interrupts.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/power-supply-axp20x-usb-power-Add-missing-interrupts.patch
new file mode 100644
index 000000000000..a7196f1c6a2e
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/power-supply-axp20x-usb-power-Add-missing-interrupts.patch
@@ -0,0 +1,59 @@
+From c5a7633f0da393dd7ba0d1ea7e7c205470c3c72d Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Fri, 15 Mar 2024 21:48:34 +0100
+Subject: power: supply: axp20x-usb-power: Add missing interrupts
+
+Notify power_supply_change on BC detection interrupts for the consumers
+to get BC results ASAP.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/mfd/axp20x.c                    |  2 ++
+ drivers/power/supply/axp20x_usb_power.c | 11 +++++++++--
+ 2 files changed, 11 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
+index 5da865469679..94651380ecdb 100644
+--- a/drivers/mfd/axp20x.c
++++ b/drivers/mfd/axp20x.c
+@@ -347,6 +347,8 @@ static const struct resource axp717_usb_power_supply_resources[] = {
+ static const struct resource axp803_usb_power_supply_resources[] = {
+ 	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_VBUS_PLUGIN, "VBUS_PLUGIN"),
+ 	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_VBUS_REMOVAL, "VBUS_REMOVAL"),
++	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_BC_USB_CHNG, "BC_USB_CHNG"),
++	DEFINE_RES_IRQ_NAMED(AXP803_IRQ_MV_CHNG, "MV_CHNG"),
+ };
+ 
+ static const struct resource axp22x_pek_resources[] = {
+diff --git a/drivers/power/supply/axp20x_usb_power.c b/drivers/power/supply/axp20x_usb_power.c
+index b555ba9bf6ad..44cbd429cb91 100644
+--- a/drivers/power/supply/axp20x_usb_power.c
++++ b/drivers/power/supply/axp20x_usb_power.c
+@@ -728,6 +728,13 @@ static const char * const axp717_irq_names[] = {
+ 	"VBUS_OVER_V",
+ };
+ 
++static const char * const axp813_irq_names[] = {
++	"VBUS_PLUGIN",
++	"VBUS_REMOVAL",
++	"BC_USB_CHNG",
++	"MV_CHNG",
++};
++
+ static int axp192_usb_curr_lim_table[] = {
+ 	-1,
+ 	-1,
+@@ -831,8 +838,8 @@ static const struct axp_data axp717_data = {
+ 
+ static const struct axp_data axp813_data = {
+ 	.power_desc	= &axp813_usb_power_desc,
+-	.irq_names	= axp22x_irq_names,
+-	.num_irq_names	= ARRAY_SIZE(axp22x_irq_names),
++	.irq_names	= axp813_irq_names,
++	.num_irq_names	= ARRAY_SIZE(axp813_irq_names),
+ 	.curr_lim_table = axp813_usb_curr_lim_table,
+ 	.curr_lim_table_size = ARRAY_SIZE(axp813_usb_curr_lim_table),
+ 	.curr_lim_fld	= REG_FIELD(AXP22X_CHRG_CTRL3, 4, 7),
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/power-supply-axp20x-usb-power-Change-Vbus-hold-voltage-to-4.5V.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/power-supply-axp20x-usb-power-Change-Vbus-hold-voltage-to-4.5V.patch
new file mode 100644
index 000000000000..7ab6ac65ec69
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/power-supply-axp20x-usb-power-Change-Vbus-hold-voltage-to-4.5V.patch
@@ -0,0 +1,38 @@
+From 66616b654c38ff3cb0b34b6b676fa13425c40d4e Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 14 Dec 2020 07:42:08 +0100
+Subject: power: supply: axp20x-usb-power: Change Vbus hold voltage to 4.5V
+
+This fixes USB-PD charger resets.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/power/supply/axp20x_usb_power.c | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/drivers/power/supply/axp20x_usb_power.c b/drivers/power/supply/axp20x_usb_power.c
+index 9722912268fe..b555ba9bf6ad 100644
+--- a/drivers/power/supply/axp20x_usb_power.c
++++ b/drivers/power/supply/axp20x_usb_power.c
+@@ -1011,6 +1011,18 @@ static int axp20x_usb_power_probe(struct platform_device *pdev)
+ 			return ret;
+ 	}
+ 
++	/*TODO: Re-work this into a supply property with OF based default value */
++	if (of_machine_is_compatible("pine64,pinephone-1.2") > 0 ||
++		of_machine_is_compatible("pine64,pinephone-1.1") > 0 ||
++		of_machine_is_compatible("pine64,pinephone-1.0") > 0) {
++
++		dev_info(&pdev->dev, "Increasing Vbus hold voltage to 4.5V\n");
++
++		ret = regmap_update_bits(axp20x->regmap, 0x30, 0x7 << 3, 0x5 << 3);
++		if (ret)
++			return ret;
++	}
++
+ 	psy_cfg.of_node = pdev->dev.of_node;
+ 	psy_cfg.drv_data = power;
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/power-supply-axp20x_battery-Add-support-for-reporting-OCV.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/power-supply-axp20x_battery-Add-support-for-reporting-OCV.patch
new file mode 100644
index 000000000000..b90a7396da0d
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/power-supply-axp20x_battery-Add-support-for-reporting-OCV.patch
@@ -0,0 +1,63 @@
+From 008e3cc97745fbba5e3273a5d9395d1791ff8df7 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Fri, 28 Feb 2020 19:16:46 +0100
+Subject: power: supply: axp20x_battery: Add support for reporting OCV
+
+Export OCV reported by PMIC via sysfs.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/power/supply/axp20x_battery.c | 23 +++++++++++++++++++++++
+ 1 file changed, 23 insertions(+)
+
+diff --git a/drivers/power/supply/axp20x_battery.c b/drivers/power/supply/axp20x_battery.c
+index 96d2856ef318..f19ab493245b 100644
+--- a/drivers/power/supply/axp20x_battery.c
++++ b/drivers/power/supply/axp20x_battery.c
+@@ -270,6 +270,25 @@ static int axp717_get_constant_charge_current(struct axp20x_batt_ps *axp,
+ 	return 0;
+ }
+ 
++static int axp20x_get_ocv_voltage(struct axp20x_batt_ps *axp, int *val)
++{
++	int ret;
++	unsigned int ocvh, ocvl, ocv;
++
++	ret = regmap_read(axp->regmap, AXP288_FG_OCVH_REG, &ocvh);
++	if (ret)
++		return ret;
++
++	ret = regmap_read(axp->regmap, AXP288_FG_OCVL_REG, &ocvl);
++	if (ret)
++		return ret;
++
++	ocv = ocvh << 4 | (ocvl & 0xf);
++
++	*val = ocv * 1100;
++	return 0;
++}
++
+ static int axp20x_battery_get_prop(struct power_supply *psy,
+ 				   enum power_supply_property psp,
+ 				   union power_supply_propval *val)
+@@ -368,6 +387,9 @@ static int axp20x_battery_get_prop(struct power_supply *psy,
+ 
+ 		break;
+ 
++	case POWER_SUPPLY_PROP_VOLTAGE_OCV:
++		return axp20x_get_ocv_voltage(axp20x_batt, &val->intval);
++
+ 	case POWER_SUPPLY_PROP_CAPACITY:
+ 		/* When no battery is present, return capacity is 100% */
+ 		ret = regmap_read(axp20x_batt->regmap, AXP20X_PWR_OP_MODE,
+@@ -851,6 +873,7 @@ static enum power_supply_property axp20x_battery_props[] = {
+ 	POWER_SUPPLY_PROP_HEALTH,
+ 	POWER_SUPPLY_PROP_VOLTAGE_MAX,
+ 	POWER_SUPPLY_PROP_VOLTAGE_MIN,
++	POWER_SUPPLY_PROP_VOLTAGE_OCV,
+ 	POWER_SUPPLY_PROP_CAPACITY,
+ };
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/power-supply-axp20x_battery-Fix-charging-done-detection.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/power-supply-axp20x_battery-Fix-charging-done-detection.patch
new file mode 100644
index 000000000000..b55a095a05be
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/power-supply-axp20x_battery-Fix-charging-done-detection.patch
@@ -0,0 +1,40 @@
+From 1159cc7534f19ea3fad016e3651cce77df029e6f Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 29 Feb 2020 00:55:09 -0600
+Subject: power: supply: axp20x_battery: Fix charging done detection
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/power/supply/axp20x_battery.c | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/power/supply/axp20x_battery.c b/drivers/power/supply/axp20x_battery.c
+index 1bac1a934614..74a5d53d7cf2 100644
+--- a/drivers/power/supply/axp20x_battery.c
++++ b/drivers/power/supply/axp20x_battery.c
+@@ -38,6 +38,7 @@
+ #define AXP717_PWR_STATUS_BAT_CHRG	1
+ #define AXP717_PWR_STATUS_BAT_DISCHRG	2
+ 
++#define AXP20X_PWR_OP_BATT_CHARGING	BIT(6)
+ #define AXP20X_PWR_OP_BATT_PRESENT	BIT(5)
+ #define AXP20X_PWR_OP_BATT_ACTIVATED	BIT(3)
+ #define AXP717_PWR_OP_BATT_PRESENT	BIT(3)
+@@ -308,12 +309,12 @@ static int axp20x_battery_get_prop(struct power_supply *psy,
+ 		break;
+ 
+ 	case POWER_SUPPLY_PROP_STATUS:
+-		ret = regmap_read(axp20x_batt->regmap, AXP20X_PWR_INPUT_STATUS,
++		ret = regmap_read(axp20x_batt->regmap, AXP20X_PWR_OP_MODE,
+ 				  &reg);
+ 		if (ret)
+ 			return ret;
+ 
+-		if (reg & AXP20X_PWR_STATUS_BAT_CHARGING) {
++		if (reg & AXP20X_PWR_OP_BATT_CHARGING) {
+ 			val->intval = POWER_SUPPLY_STATUS_CHARGING;
+ 			return 0;
+ 		}
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/power-supply-axp20x_battery-Monitor-battery-health.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/power-supply-axp20x_battery-Monitor-battery-health.patch
new file mode 100644
index 000000000000..f063c5ea9611
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/power-supply-axp20x_battery-Monitor-battery-health.patch
@@ -0,0 +1,117 @@
+From fad659e393bcf094adcd4cd5661a8c19bcb1bdfd Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 29 Feb 2020 01:04:33 -0600
+Subject: power: supply: axp20x_battery: Monitor battery health
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/power/supply/axp20x_battery.c | 58 ++++++++++++++++++++++++++-
+ 1 file changed, 56 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/power/supply/axp20x_battery.c b/drivers/power/supply/axp20x_battery.c
+index 1c4d5f2eac62..3a5f77219d83 100644
+--- a/drivers/power/supply/axp20x_battery.c
++++ b/drivers/power/supply/axp20x_battery.c
+@@ -123,6 +123,7 @@ struct axp20x_batt_ps {
+ 	struct iio_channel *batt_chrg_i;
+ 	struct iio_channel *batt_dischrg_i;
+ 	struct iio_channel *batt_v;
++	int health;
+ 	/* Maximum constant charge current */
+ 	unsigned int max_ccc;
+ 	const struct axp_data	*data;
+@@ -362,7 +363,7 @@ static int axp20x_battery_get_prop(struct power_supply *psy,
+ 			return 0;
+ 		}
+ 
+-		val->intval = POWER_SUPPLY_HEALTH_GOOD;
++		val->intval = axp20x_batt->health;
+ 		break;
+ 
+ 	case POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT:
+@@ -1047,6 +1048,39 @@ static irqreturn_t axp20x_battery_changed_irq(int irq, void *devid)
+ 	return IRQ_HANDLED;
+ }
+ 
++static irqreturn_t axp20x_battery_temp_cold_irq(int irq, void *devid)
++{
++	struct axp20x_batt_ps *axp20x_batt = devid;
++
++	axp20x_batt->health = POWER_SUPPLY_HEALTH_COLD;
++
++	power_supply_changed(axp20x_batt->batt);
++
++	return IRQ_HANDLED;
++}
++
++static irqreturn_t axp20x_battery_temp_hot_irq(int irq, void *devid)
++{
++	struct axp20x_batt_ps *axp20x_batt = devid;
++
++	axp20x_batt->health = POWER_SUPPLY_HEALTH_OVERHEAT;
++
++	power_supply_changed(axp20x_batt->batt);
++
++	return IRQ_HANDLED;
++}
++
++static irqreturn_t axp20x_battery_temp_normal_irq(int irq, void *devid)
++{
++	struct axp20x_batt_ps *axp20x_batt = devid;
++
++	axp20x_batt->health = POWER_SUPPLY_HEALTH_GOOD;
++
++	power_supply_changed(axp20x_batt->batt);
++
++	return IRQ_HANDLED;
++}
++
+ static const struct axp_irq_data axp20x_irqs[] = {
+ 	{ "BATT_PLUGIN",		axp20x_battery_changed_irq },
+ 	{ "BATT_REMOVAL",		axp20x_battery_changed_irq },
+@@ -1057,6 +1091,24 @@ static const struct axp_irq_data axp20x_irqs[] = {
+ 	{}
+ };
+ 
++static const struct axp_irq_data axp813_irqs[] = {
++	{ "BATT_PLUGIN",		axp20x_battery_changed_irq },
++	{ "BATT_REMOVAL",		axp20x_battery_changed_irq },
++	{ "BATT_HEALTH_DEAD",		axp20x_battery_changed_irq },
++	{ "BATT_HEALTH_GOOD",		axp20x_battery_changed_irq },
++	{ "BATT_CHARGING",		axp20x_battery_changed_irq },
++	{ "BATT_CHARGING_DONE",		axp20x_battery_changed_irq },
++	{ "BATT_CHG_TEMP_HIGH",		axp20x_battery_temp_hot_irq },
++	{ "BATT_CHG_TEMP_HIGH_END",	axp20x_battery_temp_normal_irq },
++	{ "BATT_CHG_TEMP_LOW",		axp20x_battery_temp_cold_irq },
++	{ "BATT_CHG_TEMP_LOW_END",	axp20x_battery_temp_normal_irq },
++	{ "BATT_ACT_TEMP_HIGH",		axp20x_battery_temp_hot_irq },
++	{ "BATT_ACT_TEMP_HIGH_END",	axp20x_battery_temp_normal_irq },
++	{ "BATT_ACT_TEMP_LOW",		axp20x_battery_temp_cold_irq },
++	{ "BATT_ACT_TEMP_LOW_END",	axp20x_battery_temp_normal_irq },
++	{}
++};
++
+ static const struct axp_data axp209_data = {
+ 	.ccc_scale = 100000,
+ 	.ccc_offset = 300000,
+@@ -1108,7 +1160,7 @@ static const struct axp_data axp813_data = {
+ 	.set_max_voltage = axp20x_battery_set_max_voltage,
+ 	.cfg_iio_chan = axp209_bat_cfg_iio_channels,
+ 	.set_bat_info = axp209_set_battery_info,
+-	.irqs = axp20x_irqs,
++	.irqs = axp813_irqs,
+ };
+ 
+ static const struct of_device_id axp20x_battery_ps_id[] = {
+@@ -1169,6 +1221,8 @@ static int axp20x_power_probe(struct platform_device *pdev)
+ 		return PTR_ERR(axp20x_batt->batt);
+ 	}
+ 
++	axp20x_batt->health = POWER_SUPPLY_HEALTH_GOOD;
++
+ 	if (!power_supply_get_battery_info(axp20x_batt->batt, &info)) {
+ 		axp20x_batt->data->set_bat_info(pdev, axp20x_batt, info);
+ 		power_supply_put_battery_info(axp20x_batt->batt, info);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/power-supply-axp20x_battery-Send-uevents-for-status-changes.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/power-supply-axp20x_battery-Send-uevents-for-status-changes.patch
new file mode 100644
index 000000000000..12f0738a1d37
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/power-supply-axp20x_battery-Send-uevents-for-status-changes.patch
@@ -0,0 +1,149 @@
+From 3370f271bac47c366689c2372d201bc48cb99b15 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 29 Feb 2020 01:04:17 -0600
+Subject: power: supply: axp20x_battery: Send uevents for status changes
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/power/supply/axp20x_battery.c | 56 ++++++++++++++++++++++++++-
+ 1 file changed, 54 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/power/supply/axp20x_battery.c b/drivers/power/supply/axp20x_battery.c
+index 74a5d53d7cf2..1c4d5f2eac62 100644
+--- a/drivers/power/supply/axp20x_battery.c
++++ b/drivers/power/supply/axp20x_battery.c
+@@ -90,8 +90,15 @@
+ #define AXP717_BAT_CC_MIN_UA		0
+ #define AXP717_BAT_CC_MAX_UA		3008000
+ 
++#define DRVNAME "axp20x-battery-power-supply"
++
+ struct axp20x_batt_ps;
+ 
++struct axp_irq_data {
++	const char *name;
++	irq_handler_t handler;
++};
++
+ struct axp_data {
+ 	int		ccc_scale;
+ 	int		ccc_offset;
+@@ -106,6 +113,7 @@ struct axp_data {
+ 	void	(*set_bat_info)(struct platform_device *pdev,
+ 				struct axp20x_batt_ps *axp_batt,
+ 				struct power_supply_battery_info *info);
++	const struct axp_irq_data *irqs;
+ };
+ 
+ struct axp20x_batt_ps {
+@@ -1030,6 +1038,25 @@ static void axp717_set_battery_info(struct platform_device *pdev,
+ 	}
+ }
+ 
++static irqreturn_t axp20x_battery_changed_irq(int irq, void *devid)
++{
++	struct axp20x_batt_ps *axp20x_batt = devid;
++
++	power_supply_changed(axp20x_batt->batt);
++
++	return IRQ_HANDLED;
++}
++
++static const struct axp_irq_data axp20x_irqs[] = {
++	{ "BATT_PLUGIN",		axp20x_battery_changed_irq },
++	{ "BATT_REMOVAL",		axp20x_battery_changed_irq },
++	{ "BATT_HEALTH_DEAD",		axp20x_battery_changed_irq },
++	{ "BATT_HEALTH_GOOD",		axp20x_battery_changed_irq },
++	{ "BATT_CHARGING",		axp20x_battery_changed_irq },
++	{ "BATT_CHARGING_DONE",		axp20x_battery_changed_irq },
++	{}
++};
++
+ static const struct axp_data axp209_data = {
+ 	.ccc_scale = 100000,
+ 	.ccc_offset = 300000,
+@@ -1040,6 +1067,7 @@ static const struct axp_data axp209_data = {
+ 	.set_max_voltage = axp20x_battery_set_max_voltage,
+ 	.cfg_iio_chan = axp209_bat_cfg_iio_channels,
+ 	.set_bat_info = axp209_set_battery_info,
++	.irqs = axp20x_irqs,
+ };
+ 
+ static const struct axp_data axp221_data = {
+@@ -1053,6 +1081,7 @@ static const struct axp_data axp221_data = {
+ 	.set_max_voltage = axp22x_battery_set_max_voltage,
+ 	.cfg_iio_chan = axp209_bat_cfg_iio_channels,
+ 	.set_bat_info = axp209_set_battery_info,
++	.irqs = axp20x_irqs,
+ };
+ 
+ static const struct axp_data axp717_data = {
+@@ -1065,6 +1094,7 @@ static const struct axp_data axp717_data = {
+ 	.set_max_voltage = axp717_battery_set_max_voltage,
+ 	.cfg_iio_chan = axp717_bat_cfg_iio_channels,
+ 	.set_bat_info = axp717_set_battery_info,
++	.irqs = axp20x_irqs,
+ };
+ 
+ static const struct axp_data axp813_data = {
+@@ -1078,6 +1108,7 @@ static const struct axp_data axp813_data = {
+ 	.set_max_voltage = axp20x_battery_set_max_voltage,
+ 	.cfg_iio_chan = axp209_bat_cfg_iio_channels,
+ 	.set_bat_info = axp209_set_battery_info,
++	.irqs = axp20x_irqs,
+ };
+ 
+ static const struct of_device_id axp20x_battery_ps_id[] = {
+@@ -1099,11 +1130,13 @@ MODULE_DEVICE_TABLE(of, axp20x_battery_ps_id);
+ 
+ static int axp20x_power_probe(struct platform_device *pdev)
+ {
++	struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
+ 	struct axp20x_batt_ps *axp20x_batt;
+ 	struct power_supply_config psy_cfg = {};
+ 	struct power_supply_battery_info *info;
+ 	struct device *dev = &pdev->dev;
+-	int ret;
++	const struct axp_irq_data *irq_data;
++	int irq, ret;
+ 
+ 	if (!of_device_is_available(pdev->dev.of_node))
+ 		return -ENODEV;
+@@ -1141,6 +1174,25 @@ static int axp20x_power_probe(struct platform_device *pdev)
+ 		power_supply_put_battery_info(axp20x_batt->batt, info);
+ 	}
+ 
++	/* Request irqs after registering, as irqs may trigger immediately */
++	for (irq_data = axp20x_batt->data->irqs; irq_data->name; irq_data++) {
++		irq = platform_get_irq_byname(pdev, irq_data->name);
++		if (irq < 0) {
++			dev_err(&pdev->dev, "No IRQ for %s: %d\n",
++				irq_data->name, irq);
++			return irq;
++		}
++		irq = regmap_irq_get_virq(axp20x->regmap_irqc, irq);
++		ret = devm_request_any_context_irq(&pdev->dev, irq,
++						   irq_data->handler, 0,
++						   DRVNAME, axp20x_batt);
++		if (ret < 0) {
++			dev_err(&pdev->dev, "Error requesting %s IRQ: %d\n",
++				irq_data->name, ret);
++			return ret;
++		}
++	}
++
+ 	/*
+ 	 * Update max CCC to a valid value if battery info is present or set it
+ 	 * to current register value by default.
+@@ -1206,7 +1258,7 @@ static int axp20x_power_probe(struct platform_device *pdev)
+ static struct platform_driver axp20x_batt_driver = {
+ 	.probe    = axp20x_power_probe,
+ 	.driver   = {
+-		.name  = "axp20x-battery-power-supply",
++		.name		= DRVNAME,
+ 		.of_match_table = axp20x_battery_ps_id,
+ 	},
+ };
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/power-supply-axp20x_battery-Setup-thermal-regulation-experiment.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/power-supply-axp20x_battery-Setup-thermal-regulation-experiment.patch
new file mode 100644
index 000000000000..6886f02f3223
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/power-supply-axp20x_battery-Setup-thermal-regulation-experiment.patch
@@ -0,0 +1,82 @@
+From c402714c643950ffe020804c98bb8e23e31ae050 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Wed, 23 Sep 2020 14:59:41 +0200
+Subject: power: supply: axp20x_battery: Setup thermal regulation
+ (experimental)
+
+Values for NTC resistances were pulled out of thin air!
+
+None of this is tested to actually work.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/power/supply/axp20x_battery.c | 53 +++++++++++++++++++++++++++
+ 1 file changed, 53 insertions(+)
+
+diff --git a/drivers/power/supply/axp20x_battery.c b/drivers/power/supply/axp20x_battery.c
+index f19ab493245b..1bac1a934614 100644
+--- a/drivers/power/supply/axp20x_battery.c
++++ b/drivers/power/supply/axp20x_battery.c
+@@ -1146,6 +1146,59 @@ static int axp20x_power_probe(struct platform_device *pdev)
+ 	 */
+ 	axp20x_get_constant_charge_current(axp20x_batt, &axp20x_batt->max_ccc);
+ 
++	if (of_machine_is_compatible("pine64,pinephone-1.2") > 0 ||
++		of_machine_is_compatible("pine64,pinephone-1.1") > 0 ||
++		of_machine_is_compatible("pine64,pinephone-1.0") > 0) {
++		// 3kOhm NTC inside PinePhone batery
++		// ---------------------------------
++		//
++		// Charging:
++		//  0 - 15 °C: Max 0.2C CC to 4.35V : 9750 Ohm - 4710 Ohm
++		// 15 - 50 °C: Max 0.5C CC to 4.35V : 4710 Ohm - 1080 Ohm
++		//
++		// Discharging:
++		// -10 °C : 16500 Ohm
++		//  55 °C : 896 Ohm
++		// enable TS pin input to ADC
++
++		dev_info(dev, "Configuring battery thermal regulation for Pinephone\n");
++
++		ret = regmap_update_bits(axp20x_batt->regmap, 0x82, BIT(0), BIT(0));
++		if (ret)
++			goto warn_bat;
++
++		// safety thresholds:
++
++		// voltage = reg_val * 12800 uV (range is 0 - 3.264V)
++		ret = regmap_write(axp20x_batt->regmap, 0x38,  9750 * 80 / 12800); // V_LTF-charge
++		if (ret)
++			goto warn_bat;
++
++		ret = regmap_write(axp20x_batt->regmap, 0x39,  1080 * 80 / 12800); // V_HTF-charge
++		if (ret)
++			goto warn_bat;
++
++		ret = regmap_write(axp20x_batt->regmap, 0x3c, 16500 * 80 / 12800); // V_LTF-work
++		if (ret)
++			goto warn_bat;
++
++		ret = regmap_write(axp20x_batt->regmap, 0x3d,   896 * 80 / 12800); // V_HTF-work
++		if (ret)
++			goto warn_bat;
++
++		// There is a hysteresis of 460.8 mV(refer to TS pin voltage) for UTP
++		// threshold, and there is a hysteresis of 57.6 mV for OTP threshold.
++
++		// use TS pin only when charging, make it affect the charger, I = 80uA
++		ret = regmap_update_bits(axp20x_batt->regmap, 0x84, 0x37, 0x31);
++		if (ret)
++			goto warn_bat;
++	}
++
++	return 0;
++
++warn_bat:
++	dev_err(dev, "Failed to configure battery thermal regulation\n");
+ 	return 0;
+ }
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/regulator-Add-simple-driver-for-enabling-a-regulator-from-users.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/regulator-Add-simple-driver-for-enabling-a-regulator-from-users.patch
new file mode 100644
index 000000000000..35711ff4fbdb
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/regulator-Add-simple-driver-for-enabling-a-regulator-from-users.patch
@@ -0,0 +1,192 @@
+From b6d9a904952e90d848cb7dc88a4f1e2a9ae8b438 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 5 Oct 2019 15:10:11 +0200
+Subject: regulator: Add simple driver for enabling a regulator from userspace
+
+This is just like userspace-consumer, but can be used from device
+tree.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/regulator/Kconfig                 |   9 ++
+ drivers/regulator/Makefile                |   1 +
+ drivers/regulator/userspace-consumer-of.c | 135 ++++++++++++++++++++++
+ 3 files changed, 145 insertions(+)
+ create mode 100644 drivers/regulator/userspace-consumer-of.c
+
+diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
+index 39297f7d8177..db7f70e9a015 100644
+--- a/drivers/regulator/Kconfig
++++ b/drivers/regulator/Kconfig
+@@ -66,6 +66,15 @@ config REGULATOR_NETLINK_EVENTS
+ 
+ 	  If unsure, say no.
+ 
++config REGULATOR_USERSPACE_CONSUMER_OF
++	tristate "Userspace regulator consumer support (OF)"
++	help
++	  There are some classes of devices that are controlled entirely
++	  from user space. Userspace consumer driver provides ability to
++	  control power supplies for such devices.
++
++	  If unsure, say no.
++
+ config REGULATOR_88PG86X
+ 	tristate "Marvell 88PG86X voltage regulators"
+ 	depends on I2C
+diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
+index 3d5a803dce8a..267a09e14295 100644
+--- a/drivers/regulator/Makefile
++++ b/drivers/regulator/Makefile
+@@ -10,6 +10,7 @@ obj-$(CONFIG_OF) += of_regulator.o
+ obj-$(CONFIG_REGULATOR_FIXED_VOLTAGE) += fixed.o
+ obj-$(CONFIG_REGULATOR_VIRTUAL_CONSUMER) += virtual.o
+ obj-$(CONFIG_REGULATOR_USERSPACE_CONSUMER) += userspace-consumer.o
++obj-$(CONFIG_REGULATOR_USERSPACE_CONSUMER_OF) += userspace-consumer-of.o
+ 
+ obj-$(CONFIG_REGULATOR_88PG86X) += 88pg86x.o
+ obj-$(CONFIG_REGULATOR_88PM800) += 88pm800-regulator.o
+diff --git a/drivers/regulator/userspace-consumer-of.c b/drivers/regulator/userspace-consumer-of.c
+new file mode 100644
+index 000000000000..bcc9433c352d
+--- /dev/null
++++ b/drivers/regulator/userspace-consumer-of.c
+@@ -0,0 +1,135 @@
++// SPDX-License-Identifier: GPL-2.0-or-later
++
++#include <linux/err.h>
++#include <linux/mutex.h>
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/regulator/consumer.h>
++#include <linux/slab.h>
++#include <linux/of.h>
++
++struct userspace_consumer_data {
++	struct mutex lock;
++	bool enabled;
++	struct regulator *supply;
++};
++
++static ssize_t reg_show_state(struct device *dev,
++			  struct device_attribute *attr, char *buf)
++{
++	struct userspace_consumer_data *data = dev_get_drvdata(dev);
++
++	if (data->enabled)
++		return sprintf(buf, "enabled\n");
++
++	return sprintf(buf, "disabled\n");
++}
++
++static ssize_t reg_set_state(struct device *dev, struct device_attribute *attr,
++			 const char *buf, size_t count)
++{
++	struct userspace_consumer_data *data = dev_get_drvdata(dev);
++	bool enabled;
++	int ret;
++
++	/*
++	 * sysfs_streq() doesn't need the \n's, but we add them so the strings
++	 * will be shared with show_state(), above.
++	 */
++	if (sysfs_streq(buf, "enabled\n") || sysfs_streq(buf, "1"))
++		enabled = true;
++	else if (sysfs_streq(buf, "disabled\n") || sysfs_streq(buf, "0"))
++		enabled = false;
++	else {
++		dev_err(dev, "Configuring invalid mode\n");
++		return count;
++	}
++
++	mutex_lock(&data->lock);
++	if (enabled != data->enabled) {
++		if (enabled)
++			ret = regulator_enable(data->supply);
++		else
++			ret = regulator_disable(data->supply);
++
++		if (ret == 0)
++			data->enabled = enabled;
++		else
++			dev_err(dev, "Failed to configure state: %d\n", ret);
++	}
++	mutex_unlock(&data->lock);
++
++	return count;
++}
++
++static DEVICE_ATTR(state, 0644, reg_show_state, reg_set_state);
++
++static struct attribute *attributes[] = {
++	&dev_attr_state.attr,
++	NULL,
++};
++
++static const struct attribute_group attr_group = {
++	.attrs	= attributes,
++};
++
++static int regulator_userspace_consumer_probe(struct platform_device *pdev)
++{
++	struct userspace_consumer_data *drvdata;
++	int ret;
++
++	drvdata = devm_kzalloc(&pdev->dev,
++			       sizeof(struct userspace_consumer_data),
++			       GFP_KERNEL);
++	if (drvdata == NULL)
++		return -ENOMEM;
++
++	mutex_init(&drvdata->lock);
++
++	drvdata->supply = devm_regulator_get(&pdev->dev, "controlled");
++	if (IS_ERR(drvdata->supply)) {
++		ret = PTR_ERR(drvdata->supply);
++		if (ret != -EPROBE_DEFER)
++			dev_err(&pdev->dev, "Failed to get supply: %d\n", ret);
++		return ret;
++	}
++
++	ret = sysfs_create_group(&pdev->dev.kobj, &attr_group);
++	if (ret != 0)
++		return ret;
++
++	platform_set_drvdata(pdev, drvdata);
++
++	return 0;
++}
++
++static void regulator_userspace_consumer_remove(struct platform_device *pdev)
++{
++	struct userspace_consumer_data *data = platform_get_drvdata(pdev);
++
++	sysfs_remove_group(&pdev->dev.kobj, &attr_group);
++
++	if (data->enabled)
++		regulator_disable(data->supply);
++}
++
++static const struct of_device_id ids_of_match[] = {
++	{ .compatible = "custom,reg-userspace-consumer", },
++	{},
++};
++MODULE_DEVICE_TABLE(of, ids_of_match);
++
++static struct platform_driver regulator_userspace_consumer_driver = {
++	.probe		= regulator_userspace_consumer_probe,
++	.remove		= regulator_userspace_consumer_remove,
++	.driver		= {
++		.name		= "reg-userspace-consumer-of",
++		.of_match_table = of_match_ptr(ids_of_match),
++	},
++};
++
++module_platform_driver(regulator_userspace_consumer_driver);
++
++MODULE_AUTHOR("Mike Rapoport <mike@compulab.co.il>");
++MODULE_DESCRIPTION("Userspace consumer for voltage and current regulators");
++MODULE_LICENSE("GPL");
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/regulator-axp20x-Add-support-for-vin-supply-for-drivevbus.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/regulator-axp20x-Add-support-for-vin-supply-for-drivevbus.patch
new file mode 100644
index 000000000000..968e1a579f32
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/regulator-axp20x-Add-support-for-vin-supply-for-drivevbus.patch
@@ -0,0 +1,61 @@
+From 8a7a8e2c300da9d317bc12cad53e4f495978b476 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 8 Jun 2020 00:15:04 +0200
+Subject: regulator: axp20x: Add support for vin-supply for drivevbus
+
+When drivevbus is used to control some regulator via the N_VBUSEN
+pin of the PMIC, this regulator may have a source supply. Allow to
+specify the supply using the vin-supply property.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/regulator/axp20x-regulator.c | 30 +++++++++++++++++++++++++---
+ 1 file changed, 27 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/regulator/axp20x-regulator.c b/drivers/regulator/axp20x-regulator.c
+index dca99cfb7cbb..0f2480316d5a 100644
+--- a/drivers/regulator/axp20x-regulator.c
++++ b/drivers/regulator/axp20x-regulator.c
+@@ -1734,12 +1734,36 @@ static int axp20x_regulator_probe(struct platform_device *pdev)
+ 	}
+ 
+ 	if (drivevbus) {
++		struct regulator_desc *new_desc;
++		bool drivevbus_vin = false;
++		struct device_node *nr, *nd;
++
++		nr = of_get_child_by_name(pdev->dev.parent->of_node, "regulators");
++		if (nr) {
++			nd = of_get_child_by_name(nr, "drivevbus");
++			if (nd) {
++				drivevbus_vin = !!of_find_property(nd, "vin-supply", NULL);
++				of_node_put(nd);
++			}
++
++			of_node_put(nr);
++		}
++
++		new_desc = devm_kzalloc(&pdev->dev, sizeof(*new_desc), GFP_KERNEL);
++		if (!new_desc)
++			return -ENOMEM;
++
++		*new_desc = axp22x_drivevbus_regulator;
++
++		if (drivevbus_vin) {
++			new_desc->supply_name = "vin";
++			dev_info(&pdev->dev, "drivevbus has vin\n");
++		}
++
+ 		/* Change N_VBUSEN sense pin to DRIVEVBUS output pin */
+ 		regmap_update_bits(axp20x->regmap, AXP20X_OVER_TMP,
+ 				   AXP22X_MISC_N_VBUSEN_FUNC, 0);
+-		rdev = devm_regulator_register(&pdev->dev,
+-					       &axp22x_drivevbus_regulator,
+-					       &config);
++		rdev = devm_regulator_register(&pdev->dev, new_desc, &config);
+ 		if (IS_ERR(rdev)) {
+ 			dev_err(&pdev->dev, "Failed to register drivevbus\n");
+ 			return PTR_ERR(rdev);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/regulator-axp20x-Enable-over-temperature-protection-and-16s-res.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/regulator-axp20x-Enable-over-temperature-protection-and-16s-res.patch
new file mode 100644
index 000000000000..6a74bb5bfdc6
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/regulator-axp20x-Enable-over-temperature-protection-and-16s-res.patch
@@ -0,0 +1,41 @@
+From 3071728a895acee0ad98869a26eac2d25376718d Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 18 Feb 2020 23:57:20 +0100
+Subject: regulator: axp20x: Enable over-temperature protection and 16s reset
+ function
+
+Why not? Also why here, but whatever.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/regulator/axp20x-regulator.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/drivers/regulator/axp20x-regulator.c b/drivers/regulator/axp20x-regulator.c
+index f304d393f5e0..95bb3ffd76b9 100644
+--- a/drivers/regulator/axp20x-regulator.c
++++ b/drivers/regulator/axp20x-regulator.c
+@@ -92,6 +92,8 @@
+ #define AXP22X_WORKMODE_DCDCX_MASK(x)	BIT_MASK(x)
+ 
+ #define AXP22X_MISC_N_VBUSEN_FUNC	BIT(4)
++#define AXP22X_MISC_16S_RESET_FUNC	BIT(3)
++#define AXP22X_MISC_OTP			BIT(2)
+ 
+ #define AXP22X_DCDC1_V_OUT_MASK		GENMASK(4, 0)
+ #define AXP22X_DCDC2_V_OUT_MASK		GENMASK(5, 0)
+@@ -1778,6 +1780,11 @@ static int axp20x_regulator_probe(struct platform_device *pdev)
+ 		}
+ 	}
+ 
++	// enable 16s power-on reset and over-temperature protection
++	regmap_update_bits(axp20x->regmap, AXP20X_OVER_TMP,
++			   AXP22X_MISC_16S_RESET_FUNC | AXP22X_MISC_OTP,
++			   AXP22X_MISC_16S_RESET_FUNC | AXP22X_MISC_OTP);
++
+ 	return 0;
+ }
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/regulator-axp20x-Turn-N_VBUSEN-to-input-on-x-powers-sense-vbus-.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/regulator-axp20x-Turn-N_VBUSEN-to-input-on-x-powers-sense-vbus-.patch
new file mode 100644
index 000000000000..64cc3bce3267
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/regulator-axp20x-Turn-N_VBUSEN-to-input-on-x-powers-sense-vbus-.patch
@@ -0,0 +1,53 @@
+From 161f933ab81767414c88de145df9220a8a66ae2e Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 9 Jun 2020 22:00:36 +0200
+Subject: regulator: axp20x: Turn N_VBUSEN to input on x-powers,sense-vbus-en
+
+When x-powers,sense-vbus-en is present on the PMIC DT node, force
+the N_VBUSEN to be an input. This is necessary on boards that
+have N_VBUSEN connected to VBUS enabling switch to make PMIC
+not charge when the board is generating VBUS voltage itself.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ .../arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts | 4 ++++
+ drivers/regulator/axp20x-regulator.c                      | 8 ++++++++
+ 2 files changed, 12 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
+index c4e3547e02e9..ec4927dfe9dc 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone-1.2.dts
+@@ -15,6 +15,10 @@ wifi_pwrseq: wifi-pwrseq {
+ 	};
+ };
+ 
++&axp803 {
++	x-powers,sense-vbus-en;
++};
++
+ &backlight {
+ 	power-supply = <&reg_ldo_io0>;
+ 	lth-brightness = <10>;
+diff --git a/drivers/regulator/axp20x-regulator.c b/drivers/regulator/axp20x-regulator.c
+index 0f2480316d5a..f304d393f5e0 100644
+--- a/drivers/regulator/axp20x-regulator.c
++++ b/drivers/regulator/axp20x-regulator.c
+@@ -1733,6 +1733,14 @@ static int axp20x_regulator_probe(struct platform_device *pdev)
+ 						&aldo1_name);
+ 	}
+ 
++	if (!drivevbus &&
++	    of_property_read_bool(pdev->dev.parent->of_node, "x-powers,sense-vbus-en")) {
++		/* make N_VBUSEN an input */
++		regmap_update_bits(axp20x->regmap, AXP20X_OVER_TMP,
++				   AXP22X_MISC_N_VBUSEN_FUNC,
++				   AXP22X_MISC_N_VBUSEN_FUNC);
++	}
++
+ 	if (drivevbus) {
+ 		struct regulator_desc *new_desc;
+ 		bool drivevbus_vin = false;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/regulator-tp65185-Add-hwmon-device-for-reading-temperature.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/regulator-tp65185-Add-hwmon-device-for-reading-temperature.patch
new file mode 100644
index 000000000000..11e8579f6fdf
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/regulator-tp65185-Add-hwmon-device-for-reading-temperature.patch
@@ -0,0 +1,235 @@
+From 6a9067668d70903cdeb7420f6e759c0f175390bb Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Thu, 17 Oct 2019 23:23:17 +0200
+Subject: regulator: tp65185: Add hwmon device for reading temperature
+
+Temperature for the display waveforms compensation is read
+via a special NTC measurement hardware inside the tp65185x.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/regulator/tp65185x.c | 134 +++++++++++++++++++++++++++++++++--
+ 1 file changed, 127 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/regulator/tp65185x.c b/drivers/regulator/tp65185x.c
+index 8b57a11ff2f9..08245b50e334 100644
+--- a/drivers/regulator/tp65185x.c
++++ b/drivers/regulator/tp65185x.c
+@@ -7,10 +7,12 @@
+ #include <linux/err.h>
+ #include <linux/i2c.h>
+ #include <linux/module.h>
++#include <linux/mutex.h>
+ #include <linux/regmap.h>
+ #include <linux/regulator/driver.h>
+ #include <linux/regulator/of_regulator.h>
+ #include <linux/gpio/consumer.h>
++#include <linux/hwmon.h>
+ #include <linux/delay.h>
+ 
+ #define REG_TMST_VALUE    0x00
+@@ -31,6 +33,9 @@
+ #define REG_PG            0x0F
+ #define REG_REVID         0x10
+ 
++#define REG_TMST1_READ_THERM	0x80
++#define REG_TMST1_CONV_END	0x20
++
+ struct tp65185x {
+ 	struct device* dev;
+ 	struct gpio_desc* wakeup_gpio;
+@@ -39,6 +44,8 @@ struct tp65185x {
+ 	struct gpio_desc* powergood_gpio;
+ 	struct regmap *regmap;
+ 	bool is_enabled;
++	struct mutex wakeup_mutex;
++	int wake_refs;
+ 	int vcom;
+ };
+ 
+@@ -192,6 +199,30 @@ static int wait_for_power_good(struct tp65185x *tp)
+ 	return -ETIMEDOUT;
+ }
+ 
++static void wakeup_regulator(struct tp65185x *tp, int wake)
++{
++	mutex_lock(&tp->wakeup_mutex);
++
++	if (wake) {
++		tp->wake_refs++;
++		if (tp->wake_refs > 1)
++			goto out_unlock;
++
++		gpiod_set_value(tp->wakeup_gpio, 1);
++		usleep_range(3000, 4000);
++	} else {
++		tp->wake_refs--;
++		if (tp->wake_refs > 0)
++			goto out_unlock;
++
++		gpiod_set_value(tp->wakeup_gpio, 0);
++		usleep_range(100, 200);
++	}
++
++out_unlock:
++	mutex_unlock(&tp->wakeup_mutex);
++}
++
+ static int enable_supply(struct regulator_dev *rdev)
+ {
+ 	struct tp65185x* tp = rdev_get_drvdata(rdev);
+@@ -200,9 +231,7 @@ static int enable_supply(struct regulator_dev *rdev)
+ 	if (tp->is_enabled)
+ 		return 0;
+ 
+-	// wake up the regulator
+-	gpiod_set_value(tp->wakeup_gpio, 1);
+-	usleep_range(3000, 4000);
++	wakeup_regulator(tp, 1);
+ 
+ 	ret = apply_voltage(tp, tp->vcom);
+ 	if (ret) {
+@@ -247,7 +276,7 @@ static int enable_supply(struct regulator_dev *rdev)
+ 	usleep_range(2000, 3000);
+ 	gpiod_set_value(tp->powerup_gpio, 0);
+ 	msleep(100);
+-	gpiod_set_value(tp->wakeup_gpio, 0);
++	wakeup_regulator(tp, 0);
+ 	return ret;
+ }
+ 
+@@ -273,7 +302,7 @@ static int disable_supply(struct regulator_dev *rdev)
+ 	show_power_status(tp, "power down");
+ 
+ 	// this will power down the V3P3 switch too
+-	gpiod_set_value(tp->wakeup_gpio, 0);
++	wakeup_regulator(tp, 0);
+ 
+ 	tp->is_enabled = false;
+ 
+@@ -309,8 +338,85 @@ static const struct regulator_desc tp65185x_reg = {
+ 	.owner = THIS_MODULE,
+ };
+ 
+-static int tp65185x_i2c_probe(struct i2c_client *i2c,
+-			      const struct i2c_device_id *id)
++static int tp65185x_ntc_read_temperature(struct tp65185x* tp, long *val)
++{
++	int ret;
++	unsigned int reg;
++
++	wakeup_regulator(tp, 1);
++
++	ret = regmap_update_bits(tp->regmap, REG_TMST1,
++				 REG_TMST1_READ_THERM,
++				 REG_TMST1_READ_THERM);
++	if (ret)
++		goto err_sleep;
++
++	ret = regmap_read_poll_timeout(tp->regmap, REG_TMST1, reg,
++				       reg & REG_TMST1_CONV_END,
++				       2000, 100000);
++	if (ret)
++		goto err_sleep;
++
++	ret = regmap_read(tp->regmap, REG_TMST_VALUE, &reg);
++	if (ret)
++		goto err_sleep;
++
++	*val = (s8)(u8)reg;
++
++err_sleep:
++	wakeup_regulator(tp, 0);
++	return ret;
++}
++
++static int tp65185x_ntc_read(struct device *dev, enum hwmon_sensor_types type,
++			     u32 attr, int channel, long *val)
++{
++	struct tp65185x *tp = dev_get_drvdata(dev);
++
++	if (type == hwmon_temp && attr == hwmon_temp_input) {
++		return tp65185x_ntc_read_temperature(tp, val);
++	} else if (type == hwmon_temp && attr == hwmon_temp_type) {
++		*val = 4;
++		return 0;
++	}
++
++	return -EINVAL;
++}
++
++static umode_t tp65185x_ntc_is_visible(const void *data,
++				       enum hwmon_sensor_types type,
++				       u32 attr, int channel)
++{
++	if (type == hwmon_temp) {
++		switch (attr) {
++		case hwmon_temp_input:
++		case hwmon_temp_type:
++			return 0444;
++		default:
++			break;
++		}
++	}
++
++	return 0;
++}
++
++static const struct hwmon_channel_info *tp65185x_ntc_info[] = {
++	HWMON_CHANNEL_INFO(chip, HWMON_C_REGISTER_TZ),
++	HWMON_CHANNEL_INFO(temp, HWMON_T_INPUT | HWMON_T_TYPE),
++	NULL
++};
++
++static const struct hwmon_ops tp65185x_ntc_hwmon_ops = {
++	.is_visible = tp65185x_ntc_is_visible,
++	.read = tp65185x_ntc_read,
++};
++
++static const struct hwmon_chip_info tp65185x_ntc_chip_info = {
++	.ops = &tp65185x_ntc_hwmon_ops,
++	.info = tp65185x_ntc_info,
++};
++
++static int tp65185x_i2c_probe(struct i2c_client *i2c)
+ {
+ 	struct device *dev = &i2c->dev;
+ 	struct regulator_dev *rdev;
+@@ -318,6 +424,7 @@ static int tp65185x_i2c_probe(struct i2c_client *i2c,
+ 	unsigned int reg;
+ 	struct tp65185x* tp;
+ 	const char* rev = NULL;
++	struct device *hwmon_dev;
+ 	int ret;
+ 
+ 	tp = devm_kzalloc(dev, sizeof(*tp), GFP_KERNEL);
+@@ -325,6 +432,7 @@ static int tp65185x_i2c_probe(struct i2c_client *i2c,
+ 		return -ENOMEM;
+ 
+ 	tp->dev = dev;
++	mutex_init(&tp->wakeup_mutex);
+ 
+ 	tp->powergood_gpio = devm_gpiod_get(dev, "powergood", GPIOD_IN);
+ 	if (IS_ERR(tp->powergood_gpio)) {
+@@ -404,6 +512,18 @@ static int tp65185x_i2c_probe(struct i2c_client *i2c,
+ 		return ret;
+ 	}
+ 
++	hwmon_dev = devm_hwmon_device_register_with_info(&i2c->dev,
++							 "tps65185",
++							 tp,
++							 &tp65185x_ntc_chip_info,
++							 NULL);
++        if (IS_ERR(hwmon_dev)) {
++		ret = PTR_ERR(hwmon_dev);
++                dev_err(dev, "unable to register tmst as hwmon device (%d)\n",
++			ret);
++                return ret;
++        }
++
+ 	return 0;
+ }
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/regulator-tp65185x-Add-tp65185x-eInk-panel-regulator-driver.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/regulator-tp65185x-Add-tp65185x-eInk-panel-regulator-driver.patch
new file mode 100644
index 000000000000..6a69fc03c784
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/regulator-tp65185x-Add-tp65185x-eInk-panel-regulator-driver.patch
@@ -0,0 +1,487 @@
+From 654021b95149522cd06ce47f7378a5ca0025aef4 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 5 Oct 2019 15:12:51 +0200
+Subject: regulator: tp65185x: Add tp65185x eInk panel regulator driver
+
+This is a very simple driver that doesn't try to expose individual
+regulators, and implements the specific power sequencing necessary
+for the eInk panel power up directly.
+
+All the 6 regulators are thus represented as one logical supply.
+VCOM output is the only voltage that needs setting, and it can
+be changed by setting the voltage of the regulator exported by
+the driver.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/regulator/Kconfig    |   8 +
+ drivers/regulator/Makefile   |   1 +
+ drivers/regulator/tp65185x.c | 428 +++++++++++++++++++++++++++++++++++
+ 3 files changed, 437 insertions(+)
+ create mode 100644 drivers/regulator/tp65185x.c
+
+diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
+index db7f70e9a015..887d8a78a1ba 100644
+--- a/drivers/regulator/Kconfig
++++ b/drivers/regulator/Kconfig
+@@ -1729,4 +1729,12 @@ config REGULATOR_QCOM_LABIBB
+ 	  boost regulator and IBB can be used as a negative boost regulator
+ 	  for LCD display panel.
+ 
++config REGULATOR_TP65185X
++	tristate "eInk display regulator tp65185x"
++	depends on I2C
++	select REGMAP_I2C
++	help
++	  This driver provides support for the voltage regulators for
++	  eInk displays on various e-book readers.
++
+ endif
+diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
+index 267a09e14295..c0266414e3e4 100644
+--- a/drivers/regulator/Makefile
++++ b/drivers/regulator/Makefile
+@@ -202,5 +202,6 @@ obj-$(CONFIG_REGULATOR_WM831X) += wm831x-ldo.o
+ obj-$(CONFIG_REGULATOR_WM8350) += wm8350-regulator.o
+ obj-$(CONFIG_REGULATOR_WM8400) += wm8400-regulator.o
+ obj-$(CONFIG_REGULATOR_WM8994) += wm8994-regulator.o
++obj-$(CONFIG_REGULATOR_TP65185X) += tp65185x.o
+ 
+ ccflags-$(CONFIG_REGULATOR_DEBUG) += -DDEBUG
+diff --git a/drivers/regulator/tp65185x.c b/drivers/regulator/tp65185x.c
+new file mode 100644
+index 000000000000..8b57a11ff2f9
+--- /dev/null
++++ b/drivers/regulator/tp65185x.c
+@@ -0,0 +1,428 @@
++// SPDX-License-Identifier: GPL-2.0+
++//
++// Regulator device driver for tp65185x (eInk panel regulator)
++//
++// Copyright (C) 2019 Ondřej Jirman <megi@xff.cz>
++
++#include <linux/err.h>
++#include <linux/i2c.h>
++#include <linux/module.h>
++#include <linux/regmap.h>
++#include <linux/regulator/driver.h>
++#include <linux/regulator/of_regulator.h>
++#include <linux/gpio/consumer.h>
++#include <linux/delay.h>
++
++#define REG_TMST_VALUE    0x00
++#define REG_ENABLE        0x01
++#define REG_VADJ          0x02
++#define REG_VCOM1         0x03
++#define REG_VCOM2         0x04
++#define REG_INT_EN1       0x05
++#define REG_INT_EN2       0x06
++#define REG_INT1          0x07
++#define REG_INT2          0x08
++#define REG_UPSEQ0        0x09
++#define REG_UPSEQ1        0x0A
++#define REG_DWNSEQ0       0x0B
++#define REG_DWNSEQ1       0x0C
++#define REG_TMST1         0x0D
++#define REG_TMST2         0x0E
++#define REG_PG            0x0F
++#define REG_REVID         0x10
++
++struct tp65185x {
++	struct device* dev;
++	struct gpio_desc* wakeup_gpio;
++	struct gpio_desc* vcom_gpio;
++	struct gpio_desc* powerup_gpio;
++	struct gpio_desc* powergood_gpio;
++	struct regmap *regmap;
++	bool is_enabled;
++	int vcom;
++};
++
++static const struct regmap_config tp65185x_regmap_config = {
++	.reg_bits = 8,
++	.val_bits = 8,
++	.max_register = 0x10,
++	.cache_type = REGCACHE_NONE,
++};
++
++struct voltage_rail {
++	const char* name;
++	int bit;
++	int bit_en;
++};
++
++static const struct voltage_rail rails[] = {
++	{ "VB",    7, -1 },
++	{ "VDDH",  6, 3 },
++	{ "VN",    5, -1 },
++	{ "VPOS",  4, 2 },
++	{ "VEE",   3, 1 },
++	{ "VNEG",  1, 0 },
++	{ "VCOM",  -1, 4 },
++	{ "V3P3",  -1, 5 },
++};
++
++static int apply_voltage(struct tp65185x *tp, int vcom)
++{
++	int ret;
++
++	ret = regmap_write(tp->regmap, REG_VCOM1, vcom & 0xff);
++	if (ret)
++		return ret;
++
++	return regmap_write(tp->regmap, REG_VCOM2, (vcom >> 8) & 1);
++}
++
++static int set_voltage(struct regulator_dev *rdev, int min_uV, int max_uV,
++		       unsigned *selector)
++{
++	struct tp65185x* tp = rdev_get_drvdata(rdev);
++	unsigned int vcom = min_uV / 10000;
++
++	if (vcom > 511 || min_uV < 0)
++		return -EINVAL;
++
++	tp->vcom = vcom;
++
++	// setup VCOM
++
++	if (!tp->is_enabled)
++		return 0;
++
++	return apply_voltage(tp, vcom);
++}
++
++static int get_voltage(struct regulator_dev *rdev)
++{
++	struct tp65185x* tp = rdev_get_drvdata(rdev);
++	unsigned int lsb, msb;
++	int ret;
++
++	if (tp->is_enabled) {
++		ret = regmap_read(rdev->regmap, REG_VCOM1, &lsb);
++		if (ret)
++			return ret;
++
++		ret = regmap_read(rdev->regmap, REG_VCOM2, &msb);
++		if (ret)
++			return ret;
++
++		return (lsb | ((msb & 1) << 8)) * 10000;
++	}
++
++	return tp->vcom * 10000;
++}
++
++#ifdef DEBUG
++static int show_power_status(struct tp65185x* tp, const char* state)
++{
++	unsigned int reg;
++	int i, ret;
++
++	ret = regmap_read(tp->regmap, REG_PG, &reg);
++	if (ret)
++		return ret;
++
++	dev_warn(tp->dev, "%s:\n", state);
++
++	dev_warn(tp->dev, "  voltage rail power good:\n");
++	for (i = 0; i < ARRAY_SIZE(rails); i++)
++		if (rails[i].bit >= 0)
++			dev_warn(tp->dev, "    %s %s\n", rails[i].name,
++				 reg & BIT(rails[i].bit) ? "good" : "fail");
++
++	ret = regmap_read(tp->regmap, REG_ENABLE, &reg);
++	if (ret)
++		return ret;
++
++	dev_warn(tp->dev, "  voltage rail enable status:\n");
++	for (i = 0; i < ARRAY_SIZE(rails); i++)
++		if (rails[i].bit_en >= 0)
++			dev_warn(tp->dev, "    %s %s\n", rails[i].name,
++				 reg & BIT(rails[i].bit_en)
++					? "enabled" : "disabled");
++
++	return 0;
++}
++#else
++static int show_power_status(struct tp65185x* tp, const char* state)
++{
++	return 0;
++}
++#endif
++
++static int show_power_bad(struct tp65185x* tp)
++{
++	unsigned int reg;
++	int i, ret;
++
++	ret = regmap_read(tp->regmap, REG_PG, &reg);
++	if (ret)
++		return ret;
++
++	dev_warn(tp->dev, "Voltage rail failures:\n");
++	for (i = 0; i < ARRAY_SIZE(rails); i++)
++		if (rails[i].bit >= 0 && !(reg & BIT(rails[i].bit)))
++			dev_warn(tp->dev, "  %s failed\n", rails[i].name);
++
++	return 0;
++}
++
++static int wait_for_power_good(struct tp65185x *tp)
++{
++	int ret, loops = 10;
++
++	// wait for power good
++	while (loops-- > 0) {
++		ret = gpiod_get_value(tp->powergood_gpio);
++		if (ret < 0)
++			return ret;
++
++		if (ret)
++			return 0;
++
++		msleep(5);
++	}
++
++	show_power_bad(tp);
++	return -ETIMEDOUT;
++}
++
++static int enable_supply(struct regulator_dev *rdev)
++{
++	struct tp65185x* tp = rdev_get_drvdata(rdev);
++	int ret;
++
++	if (tp->is_enabled)
++		return 0;
++
++	// wake up the regulator
++	gpiod_set_value(tp->wakeup_gpio, 1);
++	usleep_range(3000, 4000);
++
++	ret = apply_voltage(tp, tp->vcom);
++	if (ret) {
++		dev_err(tp->dev, "vcom restore failed (%d)\n", ret);
++		goto err;
++	}
++
++	show_power_status(tp, "pre-powerup");
++
++	// enable the VDD on the panel (V3P3) first
++	ret = regmap_write(tp->regmap, REG_ENABLE, 0x20);
++	if (ret) {
++		dev_err(tp->dev, "vdd enable failed (%d)\n", ret);
++		goto err;
++	}
++
++	usleep_range(2000, 2200);
++
++	show_power_status(tp, "V3P3 en");
++
++	// powerup by default takes about 20ms
++	gpiod_set_value(tp->powerup_gpio, 1);
++	usleep_range(22000, 24000);
++
++	ret = wait_for_power_good(tp);
++	if (ret)
++		goto err;
++
++	show_power_status(tp, "powerup done");
++
++	// enable VCOM last
++	gpiod_set_value(tp->vcom_gpio, 1);
++	usleep_range(4000, 5000);
++
++	show_power_status(tp, "powerup vcom");
++
++        tp->is_enabled = true;
++	return 0;
++
++err:
++	gpiod_set_value(tp->vcom_gpio, 0);
++	usleep_range(2000, 3000);
++	gpiod_set_value(tp->powerup_gpio, 0);
++	msleep(100);
++	gpiod_set_value(tp->wakeup_gpio, 0);
++	return ret;
++}
++
++static int disable_supply(struct regulator_dev *rdev)
++{
++	struct tp65185x* tp = rdev_get_drvdata(rdev);
++
++	if (!tp->is_enabled)
++		return 0;
++
++	show_power_status(tp, "pre-poweroff");
++
++	gpiod_set_value(tp->vcom_gpio, 0);
++	usleep_range(5000, 6000);
++
++	show_power_status(tp, "vcom down");
++
++	gpiod_set_value(tp->powerup_gpio, 0);
++
++	// it may take up to 100ms to power off all high voltage rails
++	msleep(100);
++
++	show_power_status(tp, "power down");
++
++	// this will power down the V3P3 switch too
++	gpiod_set_value(tp->wakeup_gpio, 0);
++
++	tp->is_enabled = false;
++
++	return 0;
++}
++
++static int is_supply_enabled(struct regulator_dev *rdev)
++{
++	struct tp65185x* tp = rdev_get_drvdata(rdev);
++	//int ret;
++
++	//ret = gpiod_get_value(tp->powergood_gpio);
++	//if (ret < 0)
++		//return ret;
++
++	return tp->is_enabled;
++}
++
++static const struct regulator_ops tp65185x_ops = {
++	.is_enabled		= is_supply_enabled,
++	.enable			= enable_supply,
++	.disable		= disable_supply,
++	.set_voltage		= set_voltage,
++	.get_voltage		= get_voltage,
++};
++
++static const struct regulator_desc tp65185x_reg = {
++	.name = "tp65185x",
++	.id = 0,
++	.continuous_voltage_range = 1,
++	.ops = &tp65185x_ops,
++	.type = REGULATOR_VOLTAGE,
++	.owner = THIS_MODULE,
++};
++
++static int tp65185x_i2c_probe(struct i2c_client *i2c,
++			      const struct i2c_device_id *id)
++{
++	struct device *dev = &i2c->dev;
++	struct regulator_dev *rdev;
++	struct regulator_config config = { };
++	unsigned int reg;
++	struct tp65185x* tp;
++	const char* rev = NULL;
++	int ret;
++
++	tp = devm_kzalloc(dev, sizeof(*tp), GFP_KERNEL);
++	if (!tp)
++		return -ENOMEM;
++
++	tp->dev = dev;
++
++	tp->powergood_gpio = devm_gpiod_get(dev, "powergood", GPIOD_IN);
++	if (IS_ERR(tp->powergood_gpio)) {
++		ret = PTR_ERR(tp->powergood_gpio);
++		dev_err(dev, "Can't get wakeup gpio (%d)\n", ret);
++		return ret;
++	}
++
++	tp->powerup_gpio = devm_gpiod_get(dev, "powerup", GPIOD_OUT_LOW);
++	if (IS_ERR(tp->powerup_gpio)) {
++		ret = PTR_ERR(tp->powerup_gpio);
++		dev_err(dev, "Can't get wakeup gpio (%d)\n", ret);
++		return ret;
++	}
++
++	tp->vcom_gpio = devm_gpiod_get(dev, "vcom", GPIOD_OUT_LOW);
++	if (IS_ERR(tp->vcom_gpio)) {
++		ret = PTR_ERR(tp->vcom_gpio);
++		dev_err(dev, "Can't get wakeup gpio (%d)\n", ret);
++		return ret;
++	}
++
++	tp->wakeup_gpio = devm_gpiod_get(dev, "wakeup", GPIOD_OUT_HIGH);
++	if (IS_ERR(tp->wakeup_gpio)) {
++		ret = PTR_ERR(tp->wakeup_gpio);
++		dev_err(dev, "Can't get wakeup gpio (%d)\n", ret);
++		return ret;
++	}
++
++	// wait for wakeup
++	usleep_range(10000, 12000);
++
++	i2c_set_clientdata(i2c, tp);
++
++	tp->regmap = devm_regmap_init_i2c(i2c, &tp65185x_regmap_config);
++	if (IS_ERR(tp->regmap)) {
++		ret = PTR_ERR(tp->regmap);
++		dev_err(dev, "Failed to allocate register map: %d\n", ret);
++		return ret;
++	}
++
++	ret = regmap_read(tp->regmap, REG_REVID, &reg);
++	if (ret) {
++		dev_err(dev, "chip id read failed (%d)\n", ret);
++		return ret;
++	}
++
++	switch (reg) {
++		case 0x45: rev = "TPS65185 1p0"; break;
++		case 0x55: rev = "TPS65185 1p1"; break;
++		case 0x65: rev = "TPS65185 1p2"; break;
++		case 0x66: rev = "TPS651851 1p0"; break;
++		default:
++			dev_err(dev, "reading chip id\n");
++			break;
++
++	}
++
++	dev_info(dev, "detected chip id 0x%02x (%s)\n", (int)reg, rev);
++
++	// disable regulators, move to sleep
++	gpiod_set_value(tp->wakeup_gpio, 0);
++
++	config.driver_data = tp;
++	config.dev = &i2c->dev;
++	config.regmap = tp->regmap;
++	config.of_node = dev->of_node;
++	config.init_data = of_get_regulator_init_data(dev, dev->of_node,
++						      &tp65185x_reg);
++	if (!config.init_data)
++		return -ENOMEM;
++
++	rdev = devm_regulator_register(&i2c->dev, &tp65185x_reg, &config);
++	if (IS_ERR(rdev)) {
++		ret = PTR_ERR(rdev);
++		dev_err(&i2c->dev, "Failed to register egulator (%d)\n", ret);
++		return ret;
++	}
++
++	return 0;
++}
++
++static const struct i2c_device_id tp65185x_i2c_id[] = {
++	{ "tp65185x", 0 },
++	{ },
++};
++MODULE_DEVICE_TABLE(i2c, tp65185x_i2c_id);
++
++static struct i2c_driver tp65185x_regulator_driver = {
++	.driver = {
++		.name = "tp65185x",
++	},
++	.probe = tp65185x_i2c_probe,
++	.id_table = tp65185x_i2c_id,
++};
++
++module_i2c_driver(tp65185x_regulator_driver);
++
++MODULE_AUTHOR("Ondřej Jirman <megi@xff.cz>");
++MODULE_DESCRIPTION("Regulator device driver for tp65185x");
++MODULE_LICENSE("GPL");
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/rtc-Print-which-error-caused-RTC-read-failure.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/rtc-Print-which-error-caused-RTC-read-failure.patch
new file mode 100644
index 000000000000..59e01a9eeaeb
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/rtc-Print-which-error-caused-RTC-read-failure.patch
@@ -0,0 +1,31 @@
+From 8952f8ddf5ac1e61907aed9d5ec6f061175efd36 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sat, 2 Mar 2024 15:08:57 +0100
+Subject: rtc: Print which error caused RTC read failure
+
+Currently we can't know from kernel log, whether the read failed due
+to I2C bus error, or invalid time value, etc. Print the error in error
+message.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/rtc/class.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/rtc/class.c b/drivers/rtc/class.c
+index e31fa0ad127e..2f14aecf0e24 100644
+--- a/drivers/rtc/class.c
++++ b/drivers/rtc/class.c
+@@ -66,7 +66,8 @@ static void rtc_hctosys(struct rtc_device *rtc)
+ 	err = rtc_read_time(rtc, &tm);
+ 	if (err) {
+ 		dev_err(rtc->dev.parent,
+-			"hctosys: unable to read the hardware clock\n");
++			"hctosys: unable to read the hardware clock %pe\n",
++			ERR_PTR(err));
+ 		goto err_read;
+ 	}
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/rtc-sun6i-Allow-RTC-wakeup-after-shutdown.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/rtc-sun6i-Allow-RTC-wakeup-after-shutdown.patch
new file mode 100644
index 000000000000..1327813df4b3
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/rtc-sun6i-Allow-RTC-wakeup-after-shutdown.patch
@@ -0,0 +1,69 @@
+From 78d0c26df5a45af3c229534210c1a73b91a7f2fd Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 2 Jan 2021 15:52:27 -0600
+Subject: rtc: sun6i: Allow RTC wakeup after shutdown
+
+Only IRQs that have enable_irq_wake() called on them can wake the system
+from sleep or after it has been shut down. Currently, the RTC alarm can
+only wake the system from sleep. Run the suspend callback to arm the IRQ
+during the shutdown process, so the RTC alarm also works after shutdown.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/rtc/rtc-sun6i.c | 12 +++++++++++-
+ 1 file changed, 11 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/rtc/rtc-sun6i.c b/drivers/rtc/rtc-sun6i.c
+index e5e6013d080e..c8eca3b1b96d 100644
+--- a/drivers/rtc/rtc-sun6i.c
++++ b/drivers/rtc/rtc-sun6i.c
+@@ -710,6 +710,7 @@ static struct nvmem_config sun6i_rtc_nvmem_cfg = {
+ };
+ 
+ #ifdef CONFIG_PM_SLEEP
++
+ /* Enable IRQ wake on suspend, to wake up from RTC. */
+ static int sun6i_rtc_suspend(struct device *dev)
+ {
+@@ -722,7 +723,7 @@ static int sun6i_rtc_suspend(struct device *dev)
+ }
+ 
+ /* Disable IRQ wake on resume. */
+-static int sun6i_rtc_resume(struct device *dev)
++static int __maybe_unused sun6i_rtc_resume(struct device *dev)
+ {
+ 	struct sun6i_rtc_dev *chip = dev_get_drvdata(dev);
+ 
+@@ -731,6 +732,7 @@ static int sun6i_rtc_resume(struct device *dev)
+ 
+ 	return 0;
+ }
++
+ #endif
+ 
+ static SIMPLE_DEV_PM_OPS(sun6i_rtc_pm_ops,
+@@ -850,6 +852,13 @@ static int sun6i_rtc_probe(struct platform_device *pdev)
+ 	return 0;
+ }
+ 
++static void sun6i_rtc_shutdown(struct platform_device *pdev)
++{
++#ifdef CONFIG_PM_SLEEP
++	sun6i_rtc_suspend(&pdev->dev);
++#endif
++}
++
+ /*
+  * As far as RTC functionality goes, all models are the same. The
+  * datasheets claim that different models have different number of
+@@ -874,6 +883,7 @@ MODULE_DEVICE_TABLE(of, sun6i_rtc_dt_ids);
+ 
+ static struct platform_driver sun6i_rtc_driver = {
+ 	.probe		= sun6i_rtc_probe,
++	.shutdown	= sun6i_rtc_shutdown,
+ 	.driver		= {
+ 		.name		= "sun6i-rtc",
+ 		.of_match_table = sun6i_rtc_dt_ids,
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/sound-soc-ac100-codec-Support-analog-part-of-X-Powers-AC100-cod.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/sound-soc-ac100-codec-Support-analog-part-of-X-Powers-AC100-cod.patch
new file mode 100644
index 000000000000..e2cd38ce47c3
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/sound-soc-ac100-codec-Support-analog-part-of-X-Powers-AC100-cod.patch
@@ -0,0 +1,1074 @@
+From d0f048c22adc859780fb354f0f229ef524306066 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 12 Nov 2017 23:09:14 +0100
+Subject: sound: soc: ac100-codec: Support analog part of X-Powers AC100 codec
+
+Most of the controls are implemented.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/mfd/ac100.c           |   3 +
+ include/linux/mfd/ac100.h     |   1 +
+ sound/soc/sunxi/Kconfig       |  11 +
+ sound/soc/sunxi/Makefile      |   1 +
+ sound/soc/sunxi/ac100-codec.c | 990 ++++++++++++++++++++++++++++++++++
+ 5 files changed, 1006 insertions(+)
+ create mode 100644 sound/soc/sunxi/ac100-codec.c
+
+diff --git a/drivers/mfd/ac100.c b/drivers/mfd/ac100.c
+index 8f47c392cbd1..6cc9b1035642 100644
+--- a/drivers/mfd/ac100.c
++++ b/drivers/mfd/ac100.c
+@@ -79,6 +79,9 @@ static struct mfd_cell ac100_cells[] = {
+ 	{
+ 		.name		= "ac100-codec",
+ 		.of_compatible	= "x-powers,ac100-codec",
++	}, {
++		.name		= "ac100-codec-analog",
++		.of_compatible	= "x-powers,ac100-codec-analog",
+ 	}, {
+ 		.name		= "ac100-rtc",
+ 		.of_compatible	= "x-powers,ac100-rtc",
+diff --git a/include/linux/mfd/ac100.h b/include/linux/mfd/ac100.h
+index 88005c3a1b2d..621bd10b79b2 100644
+--- a/include/linux/mfd/ac100.h
++++ b/include/linux/mfd/ac100.h
+@@ -80,6 +80,7 @@ struct ac100_dev {
+ #define AC100_ERPOUT_CTRL		0x57
+ #define AC100_SPKOUT_CTRL		0x58
+ #define AC100_LINEOUT_CTRL		0x59
++#define AC100_ADDA_TUNE1 		0x5a
+ 
+ /* ADC digital audio processing (high pass filter & auto gain control */
+ #define AC100_ADC_DAP_L_STA		0x80
+diff --git a/sound/soc/sunxi/Kconfig b/sound/soc/sunxi/Kconfig
+index 1f18f016acbb..7b2b3bcb062e 100644
+--- a/sound/soc/sunxi/Kconfig
++++ b/sound/soc/sunxi/Kconfig
+@@ -22,6 +22,17 @@ config SND_SUN8I_CODEC
+ 
+ 	  Say Y or M if you want to add sun8i digital audio codec support.
+ 
++config SND_AC100_CODEC
++	tristate "Allwinner (X-Powers) AC100 audio codec (analog part)"
++	depends on OF
++	depends on MACH_SUN8I || COMPILE_TEST
++	select MFD_AC100
++	help
++	  This option enables the audio codec support for Allwinner (X-Powers)
++	  AC100 chip.
++
++	  Say Y or M if you want to add AC100 audio codec support.
++
+ config SND_SUN8I_CODEC_ANALOG
+ 	tristate "Allwinner sun8i Codec Analog Controls Support"
+ 	depends on MACH_SUN8I || (ARM64 && ARCH_SUNXI) || COMPILE_TEST
+diff --git a/sound/soc/sunxi/Makefile b/sound/soc/sunxi/Makefile
+index 4483fe9c94ef..6131aea97efa 100644
+--- a/sound/soc/sunxi/Makefile
++++ b/sound/soc/sunxi/Makefile
+@@ -1,4 +1,5 @@
+ # SPDX-License-Identifier: GPL-2.0
++obj-$(CONFIG_SND_AC100_CODEC) += ac100-codec.o
+ obj-$(CONFIG_SND_SUN4I_CODEC) += sun4i-codec.o
+ obj-$(CONFIG_SND_SUN4I_I2S) += sun4i-i2s.o
+ obj-$(CONFIG_SND_SUN4I_SPDIF) += sun4i-spdif.o
+diff --git a/sound/soc/sunxi/ac100-codec.c b/sound/soc/sunxi/ac100-codec.c
+new file mode 100644
+index 000000000000..a36c168d4994
+--- /dev/null
++++ b/sound/soc/sunxi/ac100-codec.c
+@@ -0,0 +1,990 @@
++/*
++ * This driver supports the controls for X-Powers (Allwinner)
++ * AC100 audio codec. This codec is co-packaged with AXP81x PMICs.
++ *
++ * (C) Copyright 2020 Ondrej Jirman <megi@xff.cz>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ */
++
++#include <linux/module.h>
++#include <linux/delay.h>
++#include <linux/clk.h>
++#include <linux/io.h>
++#include <linux/pm_runtime.h>
++#include <linux/regmap.h>
++#include <linux/mfd/ac100.h>
++
++#include <sound/pcm_params.h>
++#include <sound/soc.h>
++#include <sound/tlv.h>
++#include <sound/soc-dapm.h>
++
++#define AC100_ADC_APC_CTRL_ADCR_EN_OFF                          15
++#define AC100_ADC_APC_CTRL_ADCR_EN_MASK                         BIT(15)
++#define AC100_ADC_APC_CTRL_ADCR_EN_DISABLED                     0
++#define AC100_ADC_APC_CTRL_ADCR_EN_ENABLED                      BIT(15)
++#define AC100_ADC_APC_CTRL_ADCR_GAIN_OFF                        12
++#define AC100_ADC_APC_CTRL_ADCR_GAIN(v)                         (((v) & 0x7) << 12)
++#define AC100_ADC_APC_CTRL_ADCL_EN_OFF                          11
++#define AC100_ADC_APC_CTRL_ADCL_EN_MASK                         BIT(11)
++#define AC100_ADC_APC_CTRL_ADCL_EN_DISABLED                     0
++#define AC100_ADC_APC_CTRL_ADCL_EN_ENABLED                      BIT(11)
++#define AC100_ADC_APC_CTRL_ADCL_GAIN_OFF                        8
++#define AC100_ADC_APC_CTRL_ADCL_GAIN(v)                         (((v) & 0x7) << 8)
++#define AC100_ADC_APC_CTRL_MBIAS_EN_OFF                         7
++#define AC100_ADC_APC_CTRL_MBIAS_EN_MASK                        BIT(7)
++#define AC100_ADC_APC_CTRL_MBIAS_EN_DISABLED                    0
++#define AC100_ADC_APC_CTRL_MBIAS_EN_ENABLED                     BIT(7)
++#define AC100_ADC_APC_CTRL_MMIC_BIAS_CHOPPER_EN_OFF             6
++#define AC100_ADC_APC_CTRL_MMIC_BIAS_CHOPPER_EN_MASK            BIT(6)
++#define AC100_ADC_APC_CTRL_MMIC_BIAS_CHOPPER_EN_DISABLED        0
++#define AC100_ADC_APC_CTRL_MMIC_BIAS_CHOPPER_EN_ENABLED         BIT(6)
++#define AC100_ADC_APC_CTRL_MMIC_BIAS_CHOPPER_CKS_OFF            4
++#define AC100_ADC_APC_CTRL_MMIC_BIAS_CHOPPER_CKS_MASK           GENMASK(5, 4)
++#define AC100_ADC_APC_CTRL_MMIC_BIAS_CHOPPER_CKS_250K           (0x0 << 4)
++#define AC100_ADC_APC_CTRL_MMIC_BIAS_CHOPPER_CKS_500K           (0x1 << 4)
++#define AC100_ADC_APC_CTRL_MMIC_BIAS_CHOPPER_CKS_1M             (0x2 << 4)
++#define AC100_ADC_APC_CTRL_MMIC_BIAS_CHOPPER_CKS_2M             (0x3 << 4)
++#define AC100_ADC_APC_CTRL_HBIAS_MODE_OFF                       2
++#define AC100_ADC_APC_CTRL_HBIAS_MODE_MASK                      BIT(2)
++#define AC100_ADC_APC_CTRL_HBIAS_MODE_LOAD                      0
++#define AC100_ADC_APC_CTRL_HBIAS_MODE_HBIAS_EN                  BIT(2)
++#define AC100_ADC_APC_CTRL_HBIAS_EN_OFF                         1
++#define AC100_ADC_APC_CTRL_HBIAS_EN_MASK                        BIT(1)
++#define AC100_ADC_APC_CTRL_HBIAS_EN_DISABLED                    0
++#define AC100_ADC_APC_CTRL_HBIAS_EN_ENABLED                     BIT(1)
++#define AC100_ADC_APC_CTRL_HBIAS_ADC_EN_OFF                     0
++#define AC100_ADC_APC_CTRL_HBIAS_ADC_EN_MASK                    BIT(0)
++#define AC100_ADC_APC_CTRL_HBIAS_ADC_EN_DISABLED                0
++#define AC100_ADC_APC_CTRL_HBIAS_ADC_EN_ENABLED                 BIT(0)
++
++#define AC100_ADC_SRC_ADCR_MIC1_BOOST_OFF                       13
++#define AC100_ADC_SRC_ADCR_MIC1_BOOST_MASK                      BIT(13)
++#define AC100_ADC_SRC_ADCR_MIC1_BOOST_DISABLED                  0
++#define AC100_ADC_SRC_ADCR_MIC1_BOOST_ENABLED                   BIT(13)
++#define AC100_ADC_SRC_ADCR_MIC2_BOOST_OFF                       12
++#define AC100_ADC_SRC_ADCR_MIC2_BOOST_MASK                      BIT(12)
++#define AC100_ADC_SRC_ADCR_MIC2_BOOST_DISABLED                  0
++#define AC100_ADC_SRC_ADCR_MIC2_BOOST_ENABLED                   BIT(12)
++#define AC100_ADC_SRC_ADCR_LINEINL_LINEINR_OFF                  11
++#define AC100_ADC_SRC_ADCR_LINEINL_LINEINR_MASK                 BIT(11)
++#define AC100_ADC_SRC_ADCR_LINEINL_LINEINR_DISABLED             0
++#define AC100_ADC_SRC_ADCR_LINEINL_LINEINR_ENABLED              BIT(11)
++#define AC100_ADC_SRC_ADCR_LINEINR_OFF                          10
++#define AC100_ADC_SRC_ADCR_LINEINR_MASK                         BIT(10)
++#define AC100_ADC_SRC_ADCR_LINEINR_DISABLED                     0
++#define AC100_ADC_SRC_ADCR_LINEINR_ENABLED                      BIT(10)
++#define AC100_ADC_SRC_ADCR_AUXINR_OFF                           9
++#define AC100_ADC_SRC_ADCR_AUXINR_MASK                          BIT(9)
++#define AC100_ADC_SRC_ADCR_AUXINR_DISABLED                      0
++#define AC100_ADC_SRC_ADCR_AUXINR_ENABLED                       BIT(9)
++#define AC100_ADC_SRC_ADCR_ROUTMIX_OFF                          8
++#define AC100_ADC_SRC_ADCR_ROUTMIX_MASK                         BIT(8)
++#define AC100_ADC_SRC_ADCR_ROUTMIX_DISABLED                     0
++#define AC100_ADC_SRC_ADCR_ROUTMIX_ENABLED                      BIT(8)
++#define AC100_ADC_SRC_ADCR_LOUTMIX_OFF                          7
++#define AC100_ADC_SRC_ADCR_LOUTMIX_MASK                         BIT(7)
++#define AC100_ADC_SRC_ADCR_LOUTMIX_DISABLED                     0
++#define AC100_ADC_SRC_ADCR_LOUTMIX_ENABLED                      BIT(7)
++#define AC100_ADC_SRC_ADCL_MIC1_BOOST_OFF                       6
++#define AC100_ADC_SRC_ADCL_MIC1_BOOST_MASK                      BIT(6)
++#define AC100_ADC_SRC_ADCL_MIC1_BOOST_DISABLED                  0
++#define AC100_ADC_SRC_ADCL_MIC1_BOOST_ENABLED                   BIT(6)
++#define AC100_ADC_SRC_ADCL_MIC2_BOOST_OFF                       5
++#define AC100_ADC_SRC_ADCL_MIC2_BOOST_MASK                      BIT(5)
++#define AC100_ADC_SRC_ADCL_MIC2_BOOST_DISABLED                  0
++#define AC100_ADC_SRC_ADCL_MIC2_BOOST_ENABLED                   BIT(5)
++#define AC100_ADC_SRC_ADCL_LINEINL_LINEINR_OFF                  4
++#define AC100_ADC_SRC_ADCL_LINEINL_LINEINR_MASK                 BIT(4)
++#define AC100_ADC_SRC_ADCL_LINEINL_LINEINR_DISABLED             0
++#define AC100_ADC_SRC_ADCL_LINEINL_LINEINR_ENABLED              BIT(4)
++#define AC100_ADC_SRC_ADCL_LINEINL_OFF                          3
++#define AC100_ADC_SRC_ADCL_LINEINL_MASK                         BIT(3)
++#define AC100_ADC_SRC_ADCL_LINEINL_DISABLED                     0
++#define AC100_ADC_SRC_ADCL_LINEINL_ENABLED                      BIT(3)
++#define AC100_ADC_SRC_ADCL_AUXINL_OFF                           2
++#define AC100_ADC_SRC_ADCL_AUXINL_MASK                          BIT(2)
++#define AC100_ADC_SRC_ADCL_AUXINL_DISABLED                      0
++#define AC100_ADC_SRC_ADCL_AUXINL_ENABLED                       BIT(2)
++#define AC100_ADC_SRC_ADCL_LOUTMIX_OFF                          1
++#define AC100_ADC_SRC_ADCL_LOUTMIX_MASK                         BIT(1)
++#define AC100_ADC_SRC_ADCL_LOUTMIX_DISABLED                     0
++#define AC100_ADC_SRC_ADCL_LOUTMIX_ENABLED                      BIT(1)
++#define AC100_ADC_SRC_ADCL_ROUTMIX_OFF                          0
++#define AC100_ADC_SRC_ADCL_ROUTMIX_MASK                         BIT(0)
++#define AC100_ADC_SRC_ADCL_ROUTMIX_DISABLED                     0
++#define AC100_ADC_SRC_ADCL_ROUTMIX_ENABLED                      BIT(0)
++
++#define AC100_ADC_SRC_BST_CTRL_MIC1AMPEN_OFF                    15
++#define AC100_ADC_SRC_BST_CTRL_MIC1AMPEN_MASK                   BIT(15)
++#define AC100_ADC_SRC_BST_CTRL_MIC1AMPEN_DISABLED               0
++#define AC100_ADC_SRC_BST_CTRL_MIC1AMPEN_ENABLED                BIT(15)
++#define AC100_ADC_SRC_BST_CTRL_MIC1BOOST_OFF                    12
++#define AC100_ADC_SRC_BST_CTRL_MIC1BOOST(v)                     (((v) & 0x7) << 12)
++#define AC100_ADC_SRC_BST_CTRL_MIC2AMPEN_OFF                    11
++#define AC100_ADC_SRC_BST_CTRL_MIC2AMPEN_MASK                   BIT(11)
++#define AC100_ADC_SRC_BST_CTRL_MIC2AMPEN_DISABLED               0
++#define AC100_ADC_SRC_BST_CTRL_MIC2AMPEN_ENABLED                BIT(11)
++#define AC100_ADC_SRC_BST_CTRL_MIC2BOOST_OFF                    8
++#define AC100_ADC_SRC_BST_CTRL_MIC2BOOST(v)                     (((v) & 0x7) << 8)
++#define AC100_ADC_SRC_BST_CTRL_MIC2SLT_OFF                      7
++#define AC100_ADC_SRC_BST_CTRL_MIC2SLT_MASK                     BIT(7)
++#define AC100_ADC_SRC_BST_CTRL_MIC2SLT_MIC2                     0
++#define AC100_ADC_SRC_BST_CTRL_MIC2SLT_MIC3                     BIT(7)
++#define AC100_ADC_SRC_BST_CTRL_LINEIN_DIFF_PREG_OFF             4
++#define AC100_ADC_SRC_BST_CTRL_LINEIN_DIFF_PREG(v)              (((v) & 0x7) << 4)
++#define AC100_ADC_SRC_BST_CTRL_AXI_PREG_OFF                     0
++#define AC100_ADC_SRC_BST_CTRL_AXI_PREG(v)                      ((v) & 0x7)
++
++#define AC100_OUT_MXR_DAC_A_CTRL_DAC_AR_EN_OFF                  15
++#define AC100_OUT_MXR_DAC_A_CTRL_DAC_AR_EN_MASK                 BIT(15)
++#define AC100_OUT_MXR_DAC_A_CTRL_DAC_AR_EN_DISABLED             0
++#define AC100_OUT_MXR_DAC_A_CTRL_DAC_AR_EN_ENABLED              BIT(15)
++#define AC100_OUT_MXR_DAC_A_CTRL_DAC_AL_EN_OFF                  14
++#define AC100_OUT_MXR_DAC_A_CTRL_DAC_AL_EN_MASK                 BIT(14)
++#define AC100_OUT_MXR_DAC_A_CTRL_DAC_AL_EN_DISABLED             0
++#define AC100_OUT_MXR_DAC_A_CTRL_DAC_AL_EN_ENABLED              BIT(14)
++#define AC100_OUT_MXR_DAC_A_CTRL_AR_MIX_EN_OFF                  13
++#define AC100_OUT_MXR_DAC_A_CTRL_AR_MIX_EN_MASK                 BIT(13)
++#define AC100_OUT_MXR_DAC_A_CTRL_AR_MIX_EN_DISABLED             0
++#define AC100_OUT_MXR_DAC_A_CTRL_AR_MIX_EN_ENABLED              BIT(13)
++#define AC100_OUT_MXR_DAC_A_CTRL_AL_MIX_EN_OFF                  12
++#define AC100_OUT_MXR_DAC_A_CTRL_AL_MIX_EN_MASK                 BIT(12)
++#define AC100_OUT_MXR_DAC_A_CTRL_AL_MIX_EN_DISABLED             0
++#define AC100_OUT_MXR_DAC_A_CTRL_AL_MIX_EN_ENABLED              BIT(12)
++#define AC100_OUT_MXR_DAC_A_CTRL_HP_DCRM_EN_OFF                 8
++#define AC100_OUT_MXR_DAC_A_CTRL_HP_DCRM_EN(v)                  (((v) & 0xf) << 8)
++
++#define AC100_OUT_MXR_SRC_RMIX_MIC1_BOOST_OFF                   13
++#define AC100_OUT_MXR_SRC_RMIX_MIC1_BOOST_MASK                  BIT(13)
++#define AC100_OUT_MXR_SRC_RMIX_MIC1_BOOST_DISABLED              0
++#define AC100_OUT_MXR_SRC_RMIX_MIC1_BOOST_ENABLED               BIT(13)
++#define AC100_OUT_MXR_SRC_RMIX_MIC2_BOOST_OFF                   12
++#define AC100_OUT_MXR_SRC_RMIX_MIC2_BOOST_MASK                  BIT(12)
++#define AC100_OUT_MXR_SRC_RMIX_MIC2_BOOST_DISABLED              0
++#define AC100_OUT_MXR_SRC_RMIX_MIC2_BOOST_ENABLED               BIT(12)
++#define AC100_OUT_MXR_SRC_RMIX_LINEINL_LINEINR_OFF              11
++#define AC100_OUT_MXR_SRC_RMIX_LINEINL_LINEINR_MASK             BIT(11)
++#define AC100_OUT_MXR_SRC_RMIX_LINEINL_LINEINR_DISABLED         0
++#define AC100_OUT_MXR_SRC_RMIX_LINEINL_LINEINR_ENABLED          BIT(11)
++#define AC100_OUT_MXR_SRC_RMIX_LINEINR_OFF                      10
++#define AC100_OUT_MXR_SRC_RMIX_LINEINR_MASK                     BIT(10)
++#define AC100_OUT_MXR_SRC_RMIX_LINEINR_DISABLED                 0
++#define AC100_OUT_MXR_SRC_RMIX_LINEINR_ENABLED                  BIT(10)
++#define AC100_OUT_MXR_SRC_RMIX_AUXINR_OFF                       9
++#define AC100_OUT_MXR_SRC_RMIX_AUXINR_MASK                      BIT(9)
++#define AC100_OUT_MXR_SRC_RMIX_AUXINR_DISABLED                  0
++#define AC100_OUT_MXR_SRC_RMIX_AUXINR_ENABLED                   BIT(9)
++#define AC100_OUT_MXR_SRC_RMIX_DACR_OFF                         8
++#define AC100_OUT_MXR_SRC_RMIX_DACR_MASK                        BIT(8)
++#define AC100_OUT_MXR_SRC_RMIX_DACR_DISABLED                    0
++#define AC100_OUT_MXR_SRC_RMIX_DACR_ENABLED                     BIT(8)
++#define AC100_OUT_MXR_SRC_RMIX_DACL_OFF                         7
++#define AC100_OUT_MXR_SRC_RMIX_DACL_MASK                        BIT(7)
++#define AC100_OUT_MXR_SRC_RMIX_DACL_DISABLED                    0
++#define AC100_OUT_MXR_SRC_RMIX_DACL_ENABLED                     BIT(7)
++#define AC100_OUT_MXR_SRC_LMIX_MIC1_BOOST_OFF                   6
++#define AC100_OUT_MXR_SRC_LMIX_MIC1_BOOST_MASK                  BIT(6)
++#define AC100_OUT_MXR_SRC_LMIX_MIC1_BOOST_DISABLED              0
++#define AC100_OUT_MXR_SRC_LMIX_MIC1_BOOST_ENABLED               BIT(6)
++#define AC100_OUT_MXR_SRC_LMIX_MIC2_BOOST_OFF                   5
++#define AC100_OUT_MXR_SRC_LMIX_MIC2_BOOST_MASK                  BIT(5)
++#define AC100_OUT_MXR_SRC_LMIX_MIC2_BOOST_DISABLED              0
++#define AC100_OUT_MXR_SRC_LMIX_MIC2_BOOST_ENABLED               BIT(5)
++#define AC100_OUT_MXR_SRC_LMIX_LINEINL_LINEINR_OFF              4
++#define AC100_OUT_MXR_SRC_LMIX_LINEINL_LINEINR_MASK             BIT(4)
++#define AC100_OUT_MXR_SRC_LMIX_LINEINL_LINEINR_DISABLED         0
++#define AC100_OUT_MXR_SRC_LMIX_LINEINL_LINEINR_ENABLED          BIT(4)
++#define AC100_OUT_MXR_SRC_LMIX_LINEINL_OFF                      3
++#define AC100_OUT_MXR_SRC_LMIX_LINEINL_MASK                     BIT(3)
++#define AC100_OUT_MXR_SRC_LMIX_LINEINL_DISABLED                 0
++#define AC100_OUT_MXR_SRC_LMIX_LINEINL_ENABLED                  BIT(3)
++#define AC100_OUT_MXR_SRC_LMIX_AUXINL_OFF                       2
++#define AC100_OUT_MXR_SRC_LMIX_AUXINL_MASK                      BIT(2)
++#define AC100_OUT_MXR_SRC_LMIX_AUXINL_DISABLED                  0
++#define AC100_OUT_MXR_SRC_LMIX_AUXINL_ENABLED                   BIT(2)
++#define AC100_OUT_MXR_SRC_LMIX_DACL_OFF                         1
++#define AC100_OUT_MXR_SRC_LMIX_DACL_MASK                        BIT(1)
++#define AC100_OUT_MXR_SRC_LMIX_DACL_DISABLED                    0
++#define AC100_OUT_MXR_SRC_LMIX_DACL_ENABLED                     BIT(1)
++#define AC100_OUT_MXR_SRC_LMIX_DACR_OFF                         0
++#define AC100_OUT_MXR_SRC_LMIX_DACR_MASK                        BIT(0)
++#define AC100_OUT_MXR_SRC_LMIX_DACR_DISABLED                    0
++#define AC100_OUT_MXR_SRC_LMIX_DACR_ENABLED                     BIT(0)
++
++#define AC100_OUT_MXR_SRC_BST_HMICBIAS_VOLTAGE_OFF              14
++#define AC100_OUT_MXR_SRC_BST_HMICBIAS_VOLTAGE_MASK             GENMASK(15, 14)
++#define AC100_OUT_MXR_SRC_BST_HMICBIAS_VOLTAGE_1_88V            (0x0 << 14)
++#define AC100_OUT_MXR_SRC_BST_HMICBIAS_VOLTAGE_2_09V            (0x1 << 14)
++#define AC100_OUT_MXR_SRC_BST_HMICBIAS_VOLTAGE_2_33V            (0x2 << 14)
++#define AC100_OUT_MXR_SRC_BST_HMICBIAS_VOLTAGE_2_50V            (0x3 << 14)
++#define AC100_OUT_MXR_SRC_BST_MMICBIAS_VOLTAGE_OFF              12
++#define AC100_OUT_MXR_SRC_BST_MMICBIAS_VOLTAGE_MASK             GENMASK(13, 12)
++#define AC100_OUT_MXR_SRC_BST_MMICBIAS_VOLTAGE_1_88V            (0x0 << 12)
++#define AC100_OUT_MXR_SRC_BST_MMICBIAS_VOLTAGE_2_09V            (0x1 << 12)
++#define AC100_OUT_MXR_SRC_BST_MMICBIAS_VOLTAGE_2_33V            (0x2 << 12)
++#define AC100_OUT_MXR_SRC_BST_MMICBIAS_VOLTAGE_2_50V            (0x3 << 12)
++#define AC100_OUT_MXR_SRC_BST_AX_GAIN_OFF                       9
++#define AC100_OUT_MXR_SRC_BST_AX_GAIN(v)                        (((v) & 0x7) << 9)
++#define AC100_OUT_MXR_SRC_BST_MIC1_GAIN_OFF                     6
++#define AC100_OUT_MXR_SRC_BST_MIC1_GAIN(v)                      (((v) & 0x7) << 6)
++#define AC100_OUT_MXR_SRC_BST_MIC2_GAIN_OFF                     3
++#define AC100_OUT_MXR_SRC_BST_MIC2_GAIN(v)                      (((v) & 0x7) << 3)
++#define AC100_OUT_MXR_SRC_BST_LINEIN_GAIN_OFF                   0
++#define AC100_OUT_MXR_SRC_BST_LINEIN_GAIN(v)                    ((v) & 0x7)
++
++#define AC100_HPOUT_CTRL_RIGHT_SRC_OFF                          15
++#define AC100_HPOUT_CTRL_RIGHT_SRC_MASK                         BIT(15)
++#define AC100_HPOUT_CTRL_RIGHT_SRC_DACR                         0
++#define AC100_HPOUT_CTRL_RIGHT_SRC_RAMIX                        BIT(15)
++#define AC100_HPOUT_CTRL_LEFT_SRC_OFF                           14
++#define AC100_HPOUT_CTRL_LEFT_SRC_MASK                          BIT(14)
++#define AC100_HPOUT_CTRL_LEFT_SRC_DACL                          0
++#define AC100_HPOUT_CTRL_LEFT_SRC_LAMIX                         BIT(14)
++#define AC100_HPOUT_CTRL_RIGHT_PA_MUTE_OFF                      13
++#define AC100_HPOUT_CTRL_RIGHT_PA_MUTE_MASK                     BIT(13)
++#define AC100_HPOUT_CTRL_RIGHT_PA_MUTE_MUTE                     0
++#define AC100_HPOUT_CTRL_RIGHT_PA_MUTE_NOT_MUTE                 BIT(13)
++#define AC100_HPOUT_CTRL_LEFT_PA_MUTE_OFF                       12
++#define AC100_HPOUT_CTRL_LEFT_PA_MUTE_MASK                      BIT(12)
++#define AC100_HPOUT_CTRL_LEFT_PA_MUTE_MUTE                      0
++#define AC100_HPOUT_CTRL_LEFT_PA_MUTE_NOT_MUTE                  BIT(12)
++#define AC100_HPOUT_CTRL_PA_EN_OFF                              11
++#define AC100_HPOUT_CTRL_PA_EN_MASK                             BIT(11)
++#define AC100_HPOUT_CTRL_PA_EN_DISABLED                         0
++#define AC100_HPOUT_CTRL_PA_EN_ENABLED                          BIT(11)
++#define AC100_HPOUT_CTRL_VOLUME_OFF                             4
++#define AC100_HPOUT_CTRL_VOLUME(v)                              (((v) & 0x3f) << 4)
++#define AC100_HPOUT_CTRL_STARTUP_DELAY_OFF                      2
++#define AC100_HPOUT_CTRL_STARTUP_DELAY_MASK                     GENMASK(3, 2)
++#define AC100_HPOUT_CTRL_STARTUP_DELAY_4ms                      (0x0 << 2)
++#define AC100_HPOUT_CTRL_STARTUP_DELAY_8ms                      (0x1 << 2)
++#define AC100_HPOUT_CTRL_STARTUP_DELAY_16ms                     (0x2 << 2)
++#define AC100_HPOUT_CTRL_STARTUP_DELAY_32ms                     (0x3 << 2)
++#define AC100_HPOUT_CTRL_OUTPUT_CURRENT_OFF                     0
++#define AC100_HPOUT_CTRL_OUTPUT_CURRENT(v)                      ((v) & 0x3)
++
++#define AC100_ERPOUT_CTRL_RAMP_TIME_OFF                         11
++#define AC100_ERPOUT_CTRL_RAMP_TIME_MASK                        GENMASK(12, 11)
++#define AC100_ERPOUT_CTRL_RAMP_TIME_256ms                       (0x0 << 11)
++#define AC100_ERPOUT_CTRL_RAMP_TIME_512ms                       (0x1 << 11)
++#define AC100_ERPOUT_CTRL_RAMP_TIME_640ms                       (0x2 << 11)
++#define AC100_ERPOUT_CTRL_RAMP_TIME_768ms                       (0x3 << 11)
++#define AC100_ERPOUT_CTRL_OUT_CURRENT_OFF                       9
++#define AC100_ERPOUT_CTRL_OUT_CURRENT(v)                        (((v) & 0x3) << 9)
++#define AC100_ERPOUT_CTRL_INPUT_SOURCE_OFF                      7
++#define AC100_ERPOUT_CTRL_INPUT_SOURCE_MASK                     GENMASK(8, 7)
++#define AC100_ERPOUT_CTRL_INPUT_SOURCE_DACR                     (0x0 << 7)
++#define AC100_ERPOUT_CTRL_INPUT_SOURCE_DACL                     (0x1 << 7)
++#define AC100_ERPOUT_CTRL_INPUT_SOURCE_RAMIX                    (0x2 << 7)
++#define AC100_ERPOUT_CTRL_INPUT_SOURCE_LAMIX                    (0x3 << 7)
++#define AC100_ERPOUT_CTRL_MUTE_OFF                              6
++#define AC100_ERPOUT_CTRL_MUTE_MASK                             BIT(6)
++#define AC100_ERPOUT_CTRL_MUTE_MUTE                             0
++#define AC100_ERPOUT_CTRL_MUTE_NOT_MUTE                         BIT(6)
++#define AC100_ERPOUT_CTRL_PA_EN_OFF                             5
++#define AC100_ERPOUT_CTRL_PA_EN_MASK                            BIT(5)
++#define AC100_ERPOUT_CTRL_PA_EN_DISABLED                        0
++#define AC100_ERPOUT_CTRL_PA_EN_ENABLED                         BIT(5)
++#define AC100_ERPOUT_CTRL_VOLUME_OFF                            0
++#define AC100_ERPOUT_CTRL_VOLUME(v)                             ((v) & 0x1f)
++
++#define AC100_SPKOUT_CTRL_RIGHT_SRC_OFF                         12
++#define AC100_SPKOUT_CTRL_RIGHT_SRC_MASK                        BIT(12)
++#define AC100_SPKOUT_CTRL_RIGHT_SRC_MIXR                        0
++#define AC100_SPKOUT_CTRL_RIGHT_SRC_MIXL_MIXR                   BIT(12)
++#define AC100_SPKOUT_CTRL_RIGHT_INV_EN_OFF                      11
++#define AC100_SPKOUT_CTRL_RIGHT_INV_EN_MASK                     BIT(11)
++#define AC100_SPKOUT_CTRL_RIGHT_INV_EN_DISABLED                 0
++#define AC100_SPKOUT_CTRL_RIGHT_INV_EN_ENABLED                  BIT(11)
++#define AC100_SPKOUT_CTRL_RIGHT_EN_OFF                          9
++#define AC100_SPKOUT_CTRL_RIGHT_EN_MASK                         BIT(9)
++#define AC100_SPKOUT_CTRL_RIGHT_EN_DISABLED                     0
++#define AC100_SPKOUT_CTRL_RIGHT_EN_ENABLED                      BIT(9)
++#define AC100_SPKOUT_CTRL_LEFT_SRC_OFF                          8
++#define AC100_SPKOUT_CTRL_LEFT_SRC_MASK                         BIT(8)
++#define AC100_SPKOUT_CTRL_LEFT_SRC_MIXL                         0
++#define AC100_SPKOUT_CTRL_LEFT_SRC_MIXL_MIXR                    BIT(8)
++#define AC100_SPKOUT_CTRL_LEFT_INV_EN_OFF                       7
++#define AC100_SPKOUT_CTRL_LEFT_INV_EN_MASK                      BIT(7)
++#define AC100_SPKOUT_CTRL_LEFT_INV_EN_DISABLED                  0
++#define AC100_SPKOUT_CTRL_LEFT_INV_EN_ENABLED                   BIT(7)
++#define AC100_SPKOUT_CTRL_LEFT_EN_OFF                           5
++#define AC100_SPKOUT_CTRL_LEFT_EN_MASK                          BIT(5)
++#define AC100_SPKOUT_CTRL_LEFT_EN_DISABLED                      0
++#define AC100_SPKOUT_CTRL_LEFT_EN_ENABLED                       BIT(5)
++#define AC100_SPKOUT_CTRL_VOLUME_OFF                            0
++#define AC100_SPKOUT_CTRL_VOLUME(v)                             ((v) & 0x1f)
++
++#define AC100_LINEOUT_CTRL_LINEOUT_GAIN_OFF                     5
++#define AC100_LINEOUT_CTRL_LINEOUT_GAIN(v)                      (((v) & 0x7) << 5)
++#define AC100_LINEOUT_CTRL_LINEOUT_EN_OFF                       4
++#define AC100_LINEOUT_CTRL_LINEOUT_EN_MASK                      BIT(4)
++#define AC100_LINEOUT_CTRL_LINEOUT_EN_DISABLED                  0
++#define AC100_LINEOUT_CTRL_LINEOUT_EN_ENABLED                   BIT(4)
++#define AC100_LINEOUT_CTRL_LINEOUT_S0_OFF                       3
++#define AC100_LINEOUT_CTRL_LINEOUT_S0_MASK                      BIT(3)
++#define AC100_LINEOUT_CTRL_LINEOUT_S0_MUTE                      0
++#define AC100_LINEOUT_CTRL_LINEOUT_S0_ON                        BIT(3)
++#define AC100_LINEOUT_CTRL_LINEOUT_S1_OFF                       2
++#define AC100_LINEOUT_CTRL_LINEOUT_S1_MASK                      BIT(2)
++#define AC100_LINEOUT_CTRL_LINEOUT_S1_MUTE                      0
++#define AC100_LINEOUT_CTRL_LINEOUT_S1_ON                        BIT(2)
++#define AC100_LINEOUT_CTRL_LINEOUT_S2_OFF                       1
++#define AC100_LINEOUT_CTRL_LINEOUT_S2_MASK                      BIT(1)
++#define AC100_LINEOUT_CTRL_LINEOUT_S2_MUTE                      0
++#define AC100_LINEOUT_CTRL_LINEOUT_S2_ON                        BIT(1)
++#define AC100_LINEOUT_CTRL_LINEOUT_S3_OFF                       0
++#define AC100_LINEOUT_CTRL_LINEOUT_S3_MASK                      BIT(0)
++#define AC100_LINEOUT_CTRL_LINEOUT_S3_MUTE                      0
++#define AC100_LINEOUT_CTRL_LINEOUT_S3_ON                        BIT(0)
++
++#define AC100_ADDA_TUNE1_ZERO_CROSSOVER_EN_OFF                  8
++#define AC100_ADDA_TUNE1_ZERO_CROSSOVER_EN_MASK                 BIT(8)
++#define AC100_ADDA_TUNE1_ZERO_CROSSOVER_EN_DIS                  0
++#define AC100_ADDA_TUNE1_ZERO_CROSSOVER_EN_EN                   BIT(8)
++#define AC100_ADDA_TUNE1_ZERO_CROSSOVER_TIME_OFF                7
++#define AC100_ADDA_TUNE1_ZERO_CROSSOVER_TIME                    BIT(7)
++
++struct ac100_codec {
++	struct device *dev;
++	struct snd_soc_component component;
++};
++
++/* ADC mixer controls */
++static const struct snd_kcontrol_new ac100_codec_adc_mixer_controls[] = {
++	SOC_DAPM_DOUBLE("Mic1 Capture Switch",
++			AC100_ADC_SRC,
++			AC100_ADC_SRC_ADCL_MIC1_BOOST_OFF,
++			AC100_ADC_SRC_ADCR_MIC1_BOOST_OFF, 1, 0),
++	SOC_DAPM_DOUBLE("Mic2 Capture Switch",
++			AC100_ADC_SRC,
++			AC100_ADC_SRC_ADCL_MIC2_BOOST_OFF,
++			AC100_ADC_SRC_ADCR_MIC2_BOOST_OFF, 1, 0),
++	SOC_DAPM_DOUBLE("Line In Differential Capture Switch",
++			AC100_ADC_SRC,
++			AC100_ADC_SRC_ADCL_LINEINL_LINEINR_OFF,
++			AC100_ADC_SRC_ADCR_LINEINL_LINEINR_OFF, 1, 0),
++	SOC_DAPM_DOUBLE("Line In Capture Switch",
++			AC100_ADC_SRC,
++			AC100_ADC_SRC_ADCL_LINEINL_OFF,
++			AC100_ADC_SRC_ADCR_LINEINR_OFF, 1, 0),
++	SOC_DAPM_DOUBLE("Aux In Capture Switch",
++			AC100_ADC_SRC,
++			AC100_ADC_SRC_ADCL_AUXINL_OFF,
++			AC100_ADC_SRC_ADCR_AUXINR_OFF, 1, 0),
++	SOC_DAPM_DOUBLE("Mixer Capture Switch",
++			AC100_ADC_SRC,
++			AC100_ADC_SRC_ADCL_LOUTMIX_OFF,
++			AC100_ADC_SRC_ADCR_ROUTMIX_OFF, 1, 0),
++	SOC_DAPM_DOUBLE("Mixer Reversed Capture Switch",
++			AC100_ADC_SRC,
++			AC100_ADC_SRC_ADCL_ROUTMIX_OFF,
++			AC100_ADC_SRC_ADCR_LOUTMIX_OFF, 1, 0),
++};
++
++/* Output mixer controls */
++static const struct snd_kcontrol_new ac100_codec_mixer_controls[] = {
++	SOC_DAPM_DOUBLE("Mic1 Playback Switch",
++			AC100_OUT_MXR_SRC,
++			AC100_OUT_MXR_SRC_LMIX_MIC1_BOOST_OFF,
++			AC100_OUT_MXR_SRC_RMIX_MIC1_BOOST_OFF, 1, 0),
++	SOC_DAPM_DOUBLE("Mic2 Playback Switch",
++			AC100_OUT_MXR_SRC,
++			AC100_OUT_MXR_SRC_LMIX_MIC2_BOOST_OFF,
++			AC100_OUT_MXR_SRC_RMIX_MIC2_BOOST_OFF, 1, 0),
++	SOC_DAPM_DOUBLE("Line In Differential Playback Switch",
++			AC100_OUT_MXR_SRC,
++			AC100_OUT_MXR_SRC_LMIX_LINEINL_LINEINR_OFF,
++			AC100_OUT_MXR_SRC_RMIX_LINEINL_LINEINR_OFF, 1, 0),
++	SOC_DAPM_DOUBLE("Line In Playback Switch",
++			AC100_OUT_MXR_SRC,
++			AC100_OUT_MXR_SRC_LMIX_LINEINL_OFF,
++			AC100_OUT_MXR_SRC_RMIX_LINEINR_OFF, 1, 0),
++	SOC_DAPM_DOUBLE("Aux In Playback Switch",
++			AC100_OUT_MXR_SRC,
++			AC100_OUT_MXR_SRC_LMIX_AUXINL_OFF,
++			AC100_OUT_MXR_SRC_RMIX_AUXINR_OFF, 1, 0),
++	SOC_DAPM_DOUBLE("DAC Playback Switch",
++			AC100_OUT_MXR_SRC,
++			AC100_OUT_MXR_SRC_LMIX_DACL_OFF,
++			AC100_OUT_MXR_SRC_RMIX_DACR_OFF, 1, 0),
++	SOC_DAPM_DOUBLE("DAC Reversed Playback Switch",
++			AC100_OUT_MXR_SRC,
++			AC100_OUT_MXR_SRC_LMIX_DACR_OFF,
++			AC100_OUT_MXR_SRC_RMIX_DACL_OFF, 1, 0),
++};
++
++static const DECLARE_TLV_DB_SCALE(ac100_codec_out_mixer_pregain_scale,
++				  -450, 150, 0);
++
++static const DECLARE_TLV_DB_RANGE(ac100_codec_mic_gain_scale,
++	0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
++	1, 7, TLV_DB_SCALE_ITEM(3000, 300, 0),
++);
++
++static const DECLARE_TLV_DB_SCALE(ac100_codec_pre_gain_scale,
++				  -1200, 300, 0);
++
++static const DECLARE_TLV_DB_RANGE(ac100_codec_earpiece_vol_scale,
++	0, 1, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 1),
++	2, 31, TLV_DB_SCALE_ITEM(-4350, 150, 0),
++);
++
++static const DECLARE_TLV_DB_SCALE(ac100_codec_lineout_vol_scale, -450, 150, 0);
++
++static const DECLARE_TLV_DB_SCALE(ac100_codec_hp_vol_scale, -6300, 100, 1);
++
++static const char *ac100_codec_hp_pa_delay_texts[] = {
++	"4ms", "8ms", "16ms", "32ms"
++};
++
++static SOC_ENUM_SINGLE_DECL(ac100_codec_hp_pa_delay_enum,
++			    AC100_HPOUT_CTRL,
++			    AC100_HPOUT_CTRL_STARTUP_DELAY_OFF,
++			    ac100_codec_hp_pa_delay_texts);
++
++static const char *ac100_codec_hp_pa_cur_texts[] = {
++	"low", "mid", "higher", "highest"
++};
++
++static SOC_ENUM_SINGLE_DECL(ac100_codec_hp_pa_cur_enum,
++			    AC100_HPOUT_CTRL,
++			    AC100_HPOUT_CTRL_OUTPUT_CURRENT_OFF,
++			    ac100_codec_hp_pa_cur_texts);
++
++static SOC_ENUM_SINGLE_DECL(ac100_codec_ep_pa_cur_enum,
++			    AC100_ERPOUT_CTRL,
++			    AC100_ERPOUT_CTRL_OUT_CURRENT_OFF,
++			    ac100_codec_hp_pa_cur_texts);
++
++static const char *ac100_codec_ep_pa_ramp_time_texts[] = {
++	"256ms", "512ms", "640ms", "768ms"
++};
++
++static SOC_ENUM_SINGLE_DECL(ac100_codec_ep_pa_ramp_time_enum,
++			    AC100_ERPOUT_CTRL,
++			    AC100_ERPOUT_CTRL_RAMP_TIME_OFF,
++			    ac100_codec_ep_pa_ramp_time_texts);
++
++static const char *ac100_codec_mic_bv_texts[] = {
++	"1.88V", "2.09V", "2.33V", "2.5V"
++};
++
++static SOC_ENUM_SINGLE_DECL(ac100_codec_mic1_bv_enum,
++			    AC100_OUT_MXR_SRC_BST,
++			    AC100_OUT_MXR_SRC_BST_MMICBIAS_VOLTAGE_OFF,
++			    ac100_codec_mic_bv_texts);
++
++static SOC_ENUM_SINGLE_DECL(ac100_codec_mic2_bv_enum,
++			    AC100_OUT_MXR_SRC_BST,
++			    AC100_OUT_MXR_SRC_BST_HMICBIAS_VOLTAGE_OFF,
++			    ac100_codec_mic_bv_texts);
++
++/* volume / mute controls */
++static const struct snd_kcontrol_new ac100_codec_controls[] = {
++	/* Microphone Amp boost gain */
++	SOC_SINGLE_TLV("Mic1 Boost Volume", AC100_ADC_SRC_BST_CTRL,
++		       AC100_ADC_SRC_BST_CTRL_MIC1BOOST_OFF, 0x7, 0,
++		       ac100_codec_mic_gain_scale),
++
++	SOC_SINGLE_TLV("Mic2 Boost Volume", AC100_ADC_SRC_BST_CTRL,
++		       AC100_ADC_SRC_BST_CTRL_MIC2BOOST_OFF, 0x7, 0,
++		       ac100_codec_mic_gain_scale),
++
++	SOC_SINGLE_TLV("Line In Pre-Gain Volume", AC100_ADC_SRC_BST_CTRL,
++		       AC100_ADC_SRC_BST_CTRL_LINEIN_DIFF_PREG_OFF, 0x7, 0,
++		       ac100_codec_pre_gain_scale),
++
++	SOC_SINGLE_TLV("Aux In Pre-Gain Volume", AC100_ADC_SRC_BST_CTRL,
++		       AC100_ADC_SRC_BST_CTRL_AXI_PREG_OFF, 0x7, 0,
++		       ac100_codec_pre_gain_scale),
++
++	/* ADC */
++	SOC_DOUBLE_TLV("ADC Gain Capture Volume", AC100_ADC_APC_CTRL,
++		       AC100_ADC_APC_CTRL_ADCL_GAIN_OFF,
++		       AC100_ADC_APC_CTRL_ADCR_GAIN_OFF, 0x7, 0,
++		       ac100_codec_out_mixer_pregain_scale),
++
++	/* Mixer pre-gain */
++	SOC_SINGLE_TLV("Mic1 Playback Volume", AC100_OUT_MXR_SRC_BST,
++		       AC100_OUT_MXR_SRC_BST_MIC1_GAIN_OFF,
++		       0x7, 0, ac100_codec_out_mixer_pregain_scale),
++
++	SOC_SINGLE_TLV("Mic2 Playback Volume", AC100_OUT_MXR_SRC_BST,
++		       AC100_OUT_MXR_SRC_BST_MIC2_GAIN_OFF,
++		       0x7, 0, ac100_codec_out_mixer_pregain_scale),
++
++	SOC_SINGLE_TLV("Line In Playback Volume", AC100_OUT_MXR_SRC_BST,
++		       AC100_OUT_MXR_SRC_BST_LINEIN_GAIN_OFF,
++		       0x7, 0, ac100_codec_out_mixer_pregain_scale),
++
++	SOC_SINGLE_TLV("Aux In Playback Volume", AC100_OUT_MXR_SRC_BST,
++		       AC100_OUT_MXR_SRC_BST_AX_GAIN_OFF,
++		       0x7, 0, ac100_codec_out_mixer_pregain_scale),
++
++	SOC_SINGLE_TLV("Headphone Playback Volume",
++		       AC100_HPOUT_CTRL,
++		       AC100_HPOUT_CTRL_VOLUME_OFF, 0x3f, 0,
++		       ac100_codec_hp_vol_scale),
++
++	SOC_SINGLE_TLV("Earpiece Playback Volume",
++		       AC100_ERPOUT_CTRL,
++		       AC100_ERPOUT_CTRL_VOLUME_OFF, 0x1f, 0,
++		       ac100_codec_earpiece_vol_scale),
++
++	SOC_SINGLE_TLV("Speaker Playback Volume",
++		       AC100_SPKOUT_CTRL,
++		       AC100_SPKOUT_CTRL_VOLUME_OFF, 0x1f, 0,
++		       ac100_codec_earpiece_vol_scale),
++
++	SOC_SINGLE_TLV("Line Out Playback Volume",
++		       AC100_LINEOUT_CTRL,
++		       AC100_LINEOUT_CTRL_LINEOUT_GAIN_OFF, 0x7, 0,
++		       ac100_codec_lineout_vol_scale),
++
++	SOC_ENUM("Headphone Amplifier Startup Delay",
++		 ac100_codec_hp_pa_delay_enum),
++	SOC_ENUM("Headphone Amplifier Current", ac100_codec_hp_pa_cur_enum),
++
++	SOC_ENUM("Earpiece Amplifier Ramp Time",
++		 ac100_codec_ep_pa_ramp_time_enum),
++	SOC_ENUM("Earpiece Amplifier Current", ac100_codec_ep_pa_cur_enum),
++
++	SOC_ENUM("Mic1 Bias Voltage", ac100_codec_mic1_bv_enum),
++	SOC_ENUM("Mic2 Bias Voltage", ac100_codec_mic2_bv_enum),
++};
++
++/* Headphone */
++
++static const char * const ac100_codec_hp_src_enum_text[] = {
++	"DAC", "Mixer",
++};
++
++static SOC_ENUM_DOUBLE_DECL(ac100_codec_hp_src_enum,
++			    AC100_HPOUT_CTRL,
++			    AC100_HPOUT_CTRL_LEFT_SRC_OFF,
++			    AC100_HPOUT_CTRL_RIGHT_SRC_OFF,
++			    ac100_codec_hp_src_enum_text);
++
++static const struct snd_kcontrol_new ac100_codec_hp_src[] = {
++	SOC_DAPM_ENUM("Headphone Source Playback Route",
++		      ac100_codec_hp_src_enum),
++};
++
++static const struct snd_kcontrol_new ac100_codec_hp_switch =
++	SOC_DAPM_DOUBLE("Headphone Playback Switch",
++			AC100_HPOUT_CTRL,
++			AC100_HPOUT_CTRL_LEFT_PA_MUTE_OFF,
++			AC100_HPOUT_CTRL_RIGHT_PA_MUTE_OFF, 1, 0);
++
++/* Earpiece */
++
++static const struct snd_kcontrol_new ac100_codec_earpiece_switch =
++	SOC_DAPM_SINGLE("Playback Switch",
++			AC100_ERPOUT_CTRL,
++			AC100_ERPOUT_CTRL_MUTE_OFF, 1, 0);
++
++static const char * const ac100_codec_earpiece_src_enum_text[] = {
++	"DACR", "DACL", "Right Mixer", "Left Mixer",
++};
++
++static SOC_ENUM_SINGLE_DECL(ac100_codec_earpiece_src_enum,
++			    AC100_ERPOUT_CTRL,
++			    AC100_ERPOUT_CTRL_INPUT_SOURCE_OFF,
++			    ac100_codec_earpiece_src_enum_text);
++
++static const struct snd_kcontrol_new ac100_codec_earpiece_src[] = {
++	SOC_DAPM_ENUM("Earpiece Source Playback Route",
++		      ac100_codec_earpiece_src_enum),
++};
++
++/* Speaker */
++
++static const char * const ac100_codec_spk_src_enum_text[] = {
++	"Stereo", "Mono",
++};
++
++static SOC_ENUM_DOUBLE_DECL(ac100_codec_spk_src_enum,
++			    AC100_SPKOUT_CTRL,
++			    AC100_SPKOUT_CTRL_LEFT_SRC_OFF,
++			    AC100_SPKOUT_CTRL_RIGHT_SRC_OFF,
++			    ac100_codec_spk_src_enum_text);
++
++static const struct snd_kcontrol_new ac100_codec_spk_src[] = {
++	SOC_DAPM_ENUM("Speaker Source Playback Route",
++		      ac100_codec_spk_src_enum),
++};
++
++static const struct snd_kcontrol_new ac100_codec_spk_switch =
++	SOC_DAPM_DOUBLE("Speaker Playback Switch",
++			AC100_SPKOUT_CTRL,
++			AC100_SPKOUT_CTRL_LEFT_EN_OFF,
++			AC100_SPKOUT_CTRL_RIGHT_EN_OFF, 1, 0);
++
++static const struct snd_kcontrol_new ac100_codec_spk_inv_switch =
++	SOC_DAPM_DOUBLE("Speaker Invert Switch",
++			AC100_SPKOUT_CTRL,
++			AC100_SPKOUT_CTRL_LEFT_INV_EN_OFF,
++			AC100_SPKOUT_CTRL_RIGHT_INV_EN_OFF, 1, 0);
++
++/* Line Out */
++
++static const struct snd_kcontrol_new ac100_codec_lineout_mixer_controls[] = {
++	SOC_DAPM_SINGLE("Mic1 Playback Switch",
++			AC100_LINEOUT_CTRL,
++			AC100_LINEOUT_CTRL_LINEOUT_S0_OFF, 1, 0),
++	SOC_DAPM_SINGLE("Mic2 Playback Switch",
++			AC100_LINEOUT_CTRL,
++			AC100_LINEOUT_CTRL_LINEOUT_S1_OFF, 1, 0),
++	SOC_DAPM_SINGLE("Right Mixer Playback Switch",
++			AC100_LINEOUT_CTRL,
++			AC100_LINEOUT_CTRL_LINEOUT_S2_OFF, 1, 0),
++	SOC_DAPM_SINGLE("Left Mixer Playback Switch",
++			AC100_LINEOUT_CTRL,
++			AC100_LINEOUT_CTRL_LINEOUT_S3_OFF, 1, 0),
++};
++
++static const struct snd_kcontrol_new ac100_codec_lineout_switch =
++	SOC_DAPM_SINGLE("Playback Switch",
++			AC100_LINEOUT_CTRL,
++			AC100_LINEOUT_CTRL_LINEOUT_EN_OFF, 1, 0);
++
++/* Mic2 Boost Source */
++
++static const char * const ac100_codec_mic2boost_src_enum_text[] = {
++	"Mic2", "Mic3",
++};
++
++static SOC_ENUM_SINGLE_DECL(ac100_codec_mic2boost_src_enum,
++			    AC100_ADC_SRC_BST_CTRL,
++			    AC100_ADC_SRC_BST_CTRL_MIC2SLT_OFF,
++			    ac100_codec_mic2boost_src_enum_text);
++
++static const struct snd_kcontrol_new ac100_codec_mic2boost_src[] = {
++	SOC_DAPM_ENUM("Mic2 Source Capture Route",
++		      ac100_codec_mic2boost_src_enum),
++};
++
++/* This is done to remove the headphone buffer DC offset. */
++static int ac100_codec_hp_power(struct snd_soc_dapm_widget *w,
++				struct snd_kcontrol *k, int event)
++{
++	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
++	unsigned int val = SND_SOC_DAPM_EVENT_ON(event) ? 0xf : 0;
++
++	// zero cross detection
++	if (SND_SOC_DAPM_EVENT_OFF(event)) {
++		snd_soc_component_update_bits(component,
++					      AC100_ADDA_TUNE1,
++					      AC100_ADDA_TUNE1_ZERO_CROSSOVER_EN_MASK,
++					      AC100_ADDA_TUNE1_ZERO_CROSSOVER_EN_EN);
++	} else {
++		snd_soc_component_update_bits(component,
++					      AC100_ADDA_TUNE1,
++					      AC100_ADDA_TUNE1_ZERO_CROSSOVER_EN_MASK,
++					      AC100_ADDA_TUNE1_ZERO_CROSSOVER_EN_DIS);
++	}
++
++	snd_soc_component_update_bits(component, AC100_OUT_MXR_DAC_A_CTRL,
++				      AC100_OUT_MXR_DAC_A_CTRL_HP_DCRM_EN(0xf),
++				      AC100_OUT_MXR_DAC_A_CTRL_HP_DCRM_EN(val));
++	return 0;
++}
++
++static const struct snd_soc_dapm_widget ac100_codec_widgets[] = {
++	/* DAC */
++	SND_SOC_DAPM_DAC("Left DAC", NULL, AC100_OUT_MXR_DAC_A_CTRL,
++			 AC100_OUT_MXR_DAC_A_CTRL_DAC_AL_EN_OFF, 0),
++	SND_SOC_DAPM_DAC("Right DAC", NULL, AC100_OUT_MXR_DAC_A_CTRL,
++			 AC100_OUT_MXR_DAC_A_CTRL_DAC_AR_EN_OFF, 0),
++
++	/* ADC */
++	SND_SOC_DAPM_ADC("Left ADC", NULL, AC100_ADC_APC_CTRL,
++			 AC100_ADC_APC_CTRL_ADCL_EN_OFF, 0),
++	SND_SOC_DAPM_ADC("Right ADC", NULL, AC100_ADC_APC_CTRL,
++			 AC100_ADC_APC_CTRL_ADCR_EN_OFF, 0),
++
++	/*
++	 * Due to this component and the codec belonging to separate DAPM
++	 * contexts, we need to manually link the above widgets to their
++	 * stream widgets at the card level.
++	 */
++
++        /* Headphones */
++
++	SND_SOC_DAPM_REGULATOR_SUPPLY("cpvdd", 0, 0),
++	SND_SOC_DAPM_MUX("Left Headphone Source",
++			 SND_SOC_NOPM, 0, 0, ac100_codec_hp_src),
++	SND_SOC_DAPM_MUX("Right Headphone Source",
++			 SND_SOC_NOPM, 0, 0, ac100_codec_hp_src),
++	SND_SOC_DAPM_SWITCH("Left Headphone Switch",
++			    SND_SOC_NOPM, 0, 0, &ac100_codec_hp_switch),
++	SND_SOC_DAPM_SWITCH("Right Headphone Switch",
++			    SND_SOC_NOPM, 0, 0, &ac100_codec_hp_switch),
++	SND_SOC_DAPM_OUT_DRV("Left Headphone Amp",
++			     SND_SOC_NOPM, 0, 0, NULL, 0),
++	SND_SOC_DAPM_OUT_DRV("Right Headphone Amp",
++			     SND_SOC_NOPM, 0, 0, NULL, 0),
++	SND_SOC_DAPM_SUPPLY("Headphone Amp", AC100_HPOUT_CTRL,
++			    AC100_HPOUT_CTRL_PA_EN_OFF, 0,
++			    ac100_codec_hp_power,
++			    SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_PRE_PMD),
++	SND_SOC_DAPM_OUTPUT("HP"),
++
++        /* Earpiece */
++
++	SND_SOC_DAPM_MUX("Earpiece Source Playback Route",
++			 SND_SOC_NOPM, 0, 0, ac100_codec_earpiece_src),
++	SND_SOC_DAPM_SWITCH("Earpiece",
++			    SND_SOC_NOPM, 0, 0, &ac100_codec_earpiece_switch),
++	SND_SOC_DAPM_OUT_DRV("Earpiece Amp", AC100_ERPOUT_CTRL,
++			     AC100_ERPOUT_CTRL_PA_EN_OFF, 0, NULL, 0),
++	SND_SOC_DAPM_OUTPUT("EARPIECE"),
++
++	/* Speaker */
++
++	SND_SOC_DAPM_MUX("Left Speaker Source",
++			 SND_SOC_NOPM, 0, 0, ac100_codec_spk_src),
++	SND_SOC_DAPM_MUX("Right Speaker Source",
++			 SND_SOC_NOPM, 0, 0, ac100_codec_spk_src),
++	SND_SOC_DAPM_SWITCH("Left Speaker Switch",
++			    SND_SOC_NOPM, 0, 0, &ac100_codec_spk_switch),
++	SND_SOC_DAPM_SWITCH("Right Speaker Switch",
++			    SND_SOC_NOPM, 0, 0, &ac100_codec_spk_switch),
++	SND_SOC_DAPM_SWITCH("Left Speaker Invert Switch",
++			    SND_SOC_NOPM, 0, 0, &ac100_codec_spk_inv_switch),
++	SND_SOC_DAPM_SWITCH("Right Speaker Invert Switch",
++			    SND_SOC_NOPM, 0, 0, &ac100_codec_spk_inv_switch),
++	SND_SOC_DAPM_OUTPUT("SPKOUTL"),
++	SND_SOC_DAPM_OUTPUT("SPKOUTR"),
++
++	/* Line Out */
++
++	SND_SOC_DAPM_MIXER("Line Out Mixer", SND_SOC_NOPM, 0, 0,
++			   ac100_codec_lineout_mixer_controls,
++			   ARRAY_SIZE(ac100_codec_lineout_mixer_controls)),
++	SND_SOC_DAPM_SWITCH("Line Out",
++			    SND_SOC_NOPM, 0, 0, &ac100_codec_lineout_switch),
++	SND_SOC_DAPM_OUTPUT("LINEOUT"),
++
++	/* Microphone 1 */
++
++	SND_SOC_DAPM_INPUT("MIC1"),
++	SND_SOC_DAPM_SUPPLY("MBIAS", AC100_ADC_APC_CTRL,
++			    AC100_ADC_APC_CTRL_MBIAS_EN_OFF,
++			    0, NULL, 0),
++	SND_SOC_DAPM_PGA("Mic1 Amplifier", AC100_ADC_SRC_BST_CTRL,
++			 AC100_ADC_SRC_BST_CTRL_MIC1AMPEN_OFF, 0, NULL, 0),
++
++        /* Microphone 2 and 3 */
++
++	SND_SOC_DAPM_INPUT("MIC2"),
++	SND_SOC_DAPM_INPUT("MIC3"),
++	SND_SOC_DAPM_MUX("Mic2 Amplifier Source",
++			 SND_SOC_NOPM, 0, 0, ac100_codec_mic2boost_src),
++	SND_SOC_DAPM_SUPPLY("HBIAS", AC100_ADC_APC_CTRL,
++			    AC100_ADC_APC_CTRL_HBIAS_EN_OFF,
++			    0, NULL, 0),
++	SND_SOC_DAPM_PGA("Mic2 Amplifier", AC100_ADC_SRC_BST_CTRL,
++			 AC100_ADC_SRC_BST_CTRL_MIC2AMPEN_OFF, 0, NULL, 0),
++
++	/* Line input */
++
++	SND_SOC_DAPM_INPUT("LINEIN"),
++
++	/* Aux input */
++
++	SND_SOC_DAPM_INPUT("AUXIN"),
++
++	/* Output mixers */
++	SND_SOC_DAPM_MIXER("Left Mixer", AC100_OUT_MXR_DAC_A_CTRL,
++			   AC100_OUT_MXR_DAC_A_CTRL_AL_MIX_EN_OFF, 0,
++			   ac100_codec_mixer_controls,
++			   ARRAY_SIZE(ac100_codec_mixer_controls)),
++	SND_SOC_DAPM_MIXER("Right Mixer", AC100_OUT_MXR_DAC_A_CTRL,
++			   AC100_OUT_MXR_DAC_A_CTRL_AR_MIX_EN_OFF, 0,
++			   ac100_codec_mixer_controls,
++			   ARRAY_SIZE(ac100_codec_mixer_controls)),
++
++	/* Input mixers */
++	SND_SOC_DAPM_MIXER("Left ADC Mixer", SND_SOC_NOPM, 0, 0,
++			   ac100_codec_adc_mixer_controls,
++			   ARRAY_SIZE(ac100_codec_adc_mixer_controls)),
++	SND_SOC_DAPM_MIXER("Right ADC Mixer", SND_SOC_NOPM, 0, 0,
++			   ac100_codec_adc_mixer_controls,
++			   ARRAY_SIZE(ac100_codec_adc_mixer_controls)),
++};
++
++static const struct snd_soc_dapm_route ac100_codec_routes[] = {
++	/* Microphone Routes */
++	{ "Mic1 Amplifier", NULL, "MIC1"},
++	{ "Mic2 Amplifier", NULL, "Mic2 Amplifier Source"},
++	{ "Mic2 Amplifier Source", "Mic2", "MIC2" },
++	{ "Mic2 Amplifier Source", "Mic3", "MIC3" },
++
++	/* Mixer Routes */
++	{ "Left Mixer", "Mic1 Playback Switch", "Mic1 Amplifier" },
++	{ "Left Mixer", "Mic2 Playback Switch", "Mic2 Amplifier" },
++	{ "Left Mixer", "Line In Differential Playback Switch", "LINEIN" },
++	{ "Left Mixer", "Line In Playback Switch", "LINEIN" },
++	{ "Left Mixer", "Aux In Playback Switch", "AUXIN" },
++	{ "Left Mixer", "DAC Playback Switch", "Left DAC" },
++	{ "Left Mixer", "DAC Reversed Playback Switch", "Right DAC" },
++
++	{ "Right Mixer", "Mic1 Playback Switch", "Mic1 Amplifier" },
++	{ "Right Mixer", "Mic2 Playback Switch", "Mic2 Amplifier" },
++	{ "Right Mixer", "Line In Differential Playback Switch", "LINEIN" },
++	{ "Right Mixer", "Line In Playback Switch", "LINEIN" },
++	{ "Right Mixer", "Aux In Playback Switch", "AUXIN" },
++	{ "Right Mixer", "DAC Playback Switch", "Right DAC" },
++	{ "Right Mixer", "DAC Reversed Playback Switch", "Left DAC" },
++
++	/* ADC Mixer Routes */
++	{ "Left ADC Mixer", "Mic1 Capture Switch", "Mic1 Amplifier" },
++	{ "Left ADC Mixer", "Mic2 Capture Switch", "Mic2 Amplifier" },
++	{ "Left ADC Mixer", "Line In Differential Capture Switch", "LINEIN" },
++	{ "Left ADC Mixer", "Line In Capture Switch", "LINEIN" },
++	{ "Left ADC Mixer", "Aux In Capture Switch", "AUXIN" },
++	{ "Left ADC Mixer", "Mixer Capture Switch", "Left Mixer" },
++	{ "Left ADC Mixer", "Mixer Reversed Capture Switch", "Right Mixer" },
++
++	{ "Right ADC Mixer", "Mic1 Capture Switch", "Mic1 Amplifier" },
++	{ "Right ADC Mixer", "Mic2 Capture Switch", "Mic2 Amplifier" },
++	{ "Right ADC Mixer", "Line In Differential Capture Switch", "LINEIN" },
++	{ "Right ADC Mixer", "Line In Capture Switch", "LINEIN" },
++	{ "Right ADC Mixer", "Aux In Capture Switch", "AUXIN" },
++	{ "Right ADC Mixer", "Mixer Capture Switch", "Right Mixer" },
++	{ "Right ADC Mixer", "Mixer Reversed Capture Switch", "Left Mixer" },
++
++	/* ADC Routes */
++	{ "Left ADC", NULL, "Left ADC Mixer" },
++	{ "Right ADC", NULL, "Right ADC Mixer" },
++
++	/* Headphone Routes */
++	{ "Left Headphone Source", "DAC", "Left DAC" },
++	{ "Left Headphone Source", "Mixer", "Left Mixer" },
++	{ "Left Headphone Switch", "Headphone Playback Switch", "Left Headphone Source" },
++	{ "Left Headphone Amp", NULL, "Left Headphone Switch" },
++	{ "Left Headphone Amp", NULL, "Headphone Amp" },
++	{ "HP", NULL, "Left Headphone Amp" },
++
++	{ "Right Headphone Source", "DAC", "Right DAC" },
++	{ "Right Headphone Source", "Mixer", "Right Mixer" },
++	{ "Right Headphone Switch", "Headphone Playback Switch", "Right Headphone Source" },
++	{ "Right Headphone Amp", NULL, "Right Headphone Switch" },
++	{ "Right Headphone Amp", NULL, "Headphone Amp" },
++	{ "HP", NULL, "Right Headphone Amp" },
++
++	{ "Headphone Amp", NULL, "cpvdd" },
++
++	/* Speaker Routes */
++	{ "Left Speaker Source", "Stereo", "Left Mixer" },
++	{ "Left Speaker Source", "Mono", "Right Mixer" },
++	{ "Left Speaker Source", "Mono", "Left Mixer" },
++	{ "Left Speaker Switch", "Speaker Playback Switch", "Left Speaker Source" },
++	{ "SPKOUTL", NULL, "Left Speaker Switch" },
++
++	{ "Right Speaker Source", "Stereo", "Right Mixer" },
++	{ "Right Speaker Source", "Mono", "Right Mixer" },
++	{ "Right Speaker Source", "Mono", "Left Mixer" },
++	{ "Right Speaker Switch", "Speaker Playback Switch", "Right Speaker Source" },
++	{ "SPKOUTR", NULL, "Right Speaker Switch" },
++
++	/* Earpiece Routes */
++	{ "Earpiece Source Playback Route", "DACR", "Right DAC" },
++	{ "Earpiece Source Playback Route", "DACL", "Left DAC" },
++	{ "Earpiece Source Playback Route", "Right Mixer", "Right Mixer" },
++	{ "Earpiece Source Playback Route", "Left Mixer", "Left Mixer" },
++	{ "Earpiece", "Playback Switch", "Earpiece Source Playback Route" },
++	{ "Earpiece Amp", NULL, "Earpiece" },
++	{ "EARPIECE", NULL, "Earpiece Amp" },
++
++	/* Line-out Routes */
++	{ "Line Out", "Playback Switch", "Line Out Mixer" },
++	{ "Line Out Mixer", "Mic1 Playback Switch", "Mic1 Amplifier" },
++	{ "Line Out Mixer", "Mic2 Playback Switch", "Mic2 Amplifier" },
++	{ "Line Out Mixer", "Right Mixer Playback Switch", "Right Mixer" },
++	{ "Line Out Mixer", "Left Mixer Playback Switch", "Left Mixer" },
++	{ "LINEOUT", NULL, "Line Out" },
++};
++
++static const struct snd_soc_component_driver ac100_codec_analog_cmpnt_drv = {
++	.controls		= ac100_codec_controls,
++	.num_controls		= ARRAY_SIZE(ac100_codec_controls),
++	.dapm_widgets		= ac100_codec_widgets,
++	.num_dapm_widgets	= ARRAY_SIZE(ac100_codec_widgets),
++	.dapm_routes		= ac100_codec_routes,
++	.num_dapm_routes	= ARRAY_SIZE(ac100_codec_routes),
++};
++
++static int ac100_codec_probe(struct platform_device *pdev)
++{
++	struct ac100_dev *ac100 = dev_get_drvdata(pdev->dev.parent);
++	struct ac100_codec *codec;
++	int ret = 0;
++
++	codec = devm_kzalloc(&pdev->dev, sizeof(*codec), GFP_KERNEL);
++	if (!codec)
++		return -ENOMEM;
++
++	codec->dev = &pdev->dev;
++	platform_set_drvdata(pdev, codec);
++
++	snd_soc_component_init_regmap(&codec->component, ac100->regmap);
++
++	ret = snd_soc_component_initialize(&codec->component,
++					   &ac100_codec_analog_cmpnt_drv,
++					   &pdev->dev);
++	if (ret < 0)
++		return ret;
++
++	ret = snd_soc_add_component(&codec->component, NULL, 0);
++	if (ret) {
++		dev_err(&pdev->dev,
++			"Failed to register codec component (%d)\n", ret);
++		return ret;
++	}
++
++	return ret;
++}
++
++static void ac100_codec_remove(struct platform_device *pdev)
++{
++	snd_soc_unregister_component(&pdev->dev);
++
++	/*
++	 * We do not call snd_soc_component_exit_regmap, because regmap
++	 * is still owned by the mfd device.
++	 */
++}
++
++static const struct of_device_id ac100_codec_of_match[] = {
++	{ .compatible = "x-powers,ac100-codec-analog" },
++	{}
++};
++MODULE_DEVICE_TABLE(of, ac100_codec_of_match);
++
++static struct platform_driver ac100_codec_driver = {
++	.driver = {
++		.name = "ac100-codec-analog",
++		.of_match_table = ac100_codec_of_match,
++	},
++	.probe = ac100_codec_probe,
++	.remove = ac100_codec_remove,
++};
++module_platform_driver(ac100_codec_driver);
++
++MODULE_DESCRIPTION("X-Powers AC100 codec driver");
++MODULE_AUTHOR("Ondrej Jirman <megi@xff.cz>");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:ac100-codec");
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/sound-soc-sun8i-codec-Add-support-for-digital-part-of-the-AC100.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/sound-soc-sun8i-codec-Add-support-for-digital-part-of-the-AC100.patch
new file mode 100644
index 000000000000..e305ebd3f3c5
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/sound-soc-sun8i-codec-Add-support-for-digital-part-of-the-AC100.patch
@@ -0,0 +1,371 @@
+From 098efa67e28d6ed17911b54030337059db3ff7a9 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 9 Feb 2020 17:58:59 +0100
+Subject: sound: soc: sun8i-codec: Add support for digital part of the AC100
+ codec
+
+X-Power AC100 codec has almost the same digital part as the A64 codec.
+The major difference is that registers are spaced differently. A64
+has codec register address stride of 4 bytes, while AC100 has addresses
+packed together.
+
+We use a custom regmap/regmap_bus to translate register addresses from
+the A64 regmap to the correct registers in the AC100's MFD regmap.
+
+We also need to power the codec, so AC100's regulators are also enabled
+by the codec driver.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ sound/soc/sunxi/Kconfig       |   4 +-
+ sound/soc/sunxi/sun8i-codec.c | 216 ++++++++++++++++++++++++++++++++--
+ 2 files changed, 212 insertions(+), 8 deletions(-)
+
+diff --git a/sound/soc/sunxi/Kconfig b/sound/soc/sunxi/Kconfig
+index 7b2b3bcb062e..f87b061f59b2 100644
+--- a/sound/soc/sunxi/Kconfig
++++ b/sound/soc/sunxi/Kconfig
+@@ -16,9 +16,11 @@ config SND_SUN8I_CODEC
+ 	depends on MACH_SUN8I || (ARM64 && ARCH_SUNXI) || COMPILE_TEST
+ 	depends on COMMON_CLK
+ 	select REGMAP_MMIO
++	select MFD_AC100
+ 	help
+ 	  This option enables the digital part of the internal audio codec for
+-	  Allwinner sun8i SoC (and particularly A33).
++	  Allwinner sun8i SoC (and particularly A33). It also supports digital
++	  part of X-Powers AC100.
+ 
+ 	  Say Y or M if you want to add sun8i digital audio codec support.
+ 
+diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c
+index b195ddc5d5cf..d6408c7af76c 100644
+--- a/sound/soc/sunxi/sun8i-codec.c
++++ b/sound/soc/sunxi/sun8i-codec.c
+@@ -21,7 +21,9 @@
+ #include <linux/of.h>
+ #include <linux/pm_runtime.h>
+ #include <linux/regmap.h>
++#include <linux/regulator/consumer.h>
+ #include <linux/log2.h>
++#include <linux/mfd/ac100.h>
+ 
+ #include <sound/jack.h>
+ #include <sound/pcm_params.h>
+@@ -194,6 +196,50 @@
+ 				 SNDRV_PCM_RATE_192000    |\
+ 				 SNDRV_PCM_RATE_KNOT)
+ 
++#define AC100_SYSCLK_CTRL_PLLCLK_ENA_OFF	15
++#define AC100_SYSCLK_CTRL_PLLCLK_ENA_MASK	BIT(15)
++#define AC100_SYSCLK_CTRL_PLLCLK_ENA_DISABLED	0
++#define AC100_SYSCLK_CTRL_PLLCLK_ENA_ENABLED	BIT(15)
++#define AC100_SYSCLK_CTRL_PLLCLK_SRC_OFF	12
++#define AC100_SYSCLK_CTRL_PLLCLK_SRC_MASK	GENMASK(13, 12)
++#define AC100_SYSCLK_CTRL_PLLCLK_SRC_MCLK1	(0x0 << 12)
++#define AC100_SYSCLK_CTRL_PLLCLK_SRC_MCLK2	(0x1 << 12)
++#define AC100_SYSCLK_CTRL_PLLCLK_SRC_BCLK1	(0x2 << 12)
++#define AC100_SYSCLK_CTRL_PLLCLK_SRC_BCLK2	(0x3 << 12)
++#define AC100_SYSCLK_CTRL_I2S1CLK_ENA_OFF	11
++#define AC100_SYSCLK_CTRL_I2S1CLK_ENA_MASK	BIT(11)
++#define AC100_SYSCLK_CTRL_I2S1CLK_ENA_DISABLED	0
++#define AC100_SYSCLK_CTRL_I2S1CLK_ENA_ENABLED	BIT(11)
++#define AC100_SYSCLK_CTRL_I2S1CLK_SRC_OFF	8
++#define AC100_SYSCLK_CTRL_I2S1CLK_SRC_MASK	GENMASK(9, 8)
++#define AC100_SYSCLK_CTRL_I2S1CLK_SRC_MCLK1	(0x0 << 8)
++#define AC100_SYSCLK_CTRL_I2S1CLK_SRC_MCLK2	(0x1 << 8)
++#define AC100_SYSCLK_CTRL_I2S1CLK_SRC_PLL	(0x2 << 8)
++#define AC100_SYSCLK_CTRL_I2S2CLK_ENA_OFF	7
++#define AC100_SYSCLK_CTRL_I2S2CLK_ENA_MASK	BIT(7)
++#define AC100_SYSCLK_CTRL_I2S2CLK_ENA_DISABLED	0
++#define AC100_SYSCLK_CTRL_I2S2CLK_ENA_ENABLED	BIT(7)
++#define AC100_SYSCLK_CTRL_I2S2CLK_SRC_OFF	4
++#define AC100_SYSCLK_CTRL_I2S2CLK_SRC_MASK	GENMASK(5, 4)
++#define AC100_SYSCLK_CTRL_I2S2CLK_SRC_MCLK1	(0x0 << 4)
++#define AC100_SYSCLK_CTRL_I2S2CLK_SRC_MCLK2	(0x1 << 4)
++#define AC100_SYSCLK_CTRL_I2S2CLK_SRC_PLL	(0x2 << 4)
++#define AC100_SYSCLK_CTRL_SYSCLK_ENA_OFF	3
++#define AC100_SYSCLK_CTRL_SYSCLK_ENA_MASK	BIT(3)
++#define AC100_SYSCLK_CTRL_SYSCLK_ENA_DISABLED	0
++#define AC100_SYSCLK_CTRL_SYSCLK_ENA_ENABLED	BIT(3)
++#define AC100_SYSCLK_CTRL_SYSCLK_SRC_OFF	0
++#define AC100_SYSCLK_CTRL_SYSCLK_SRC_MASK	BIT(0)
++#define AC100_SYSCLK_CTRL_SYSCLK_SRC_I2S1CLK	0
++#define AC100_SYSCLK_CTRL_SYSCLK_SRC_I2S2CLK	BIT(0)
++
++static const char *const ac100_supply_names[] = {
++	"LDOIN",
++	"AVCC",
++	"VDDIO1",
++	"VDDIO2",
++};
++
+ enum {
+ 	SUN8I_CODEC_AIF1,
+ 	SUN8I_CODEC_AIF2,
+@@ -242,6 +288,9 @@ struct sun8i_codec {
+ 	int				last_hmic_irq;
+ 	unsigned int			sysclk_rate;
+ 	int				sysclk_refcnt;
++
++	struct regmap			*ac100_regmap;
++	struct regulator_bulk_data	supplies[ARRAY_SIZE(ac100_supply_names)];
+ };
+ 
+ static struct snd_soc_dai_driver sun8i_codec_dais[];
+@@ -645,6 +694,10 @@ static int sun8i_codec_hw_params(struct snd_pcm_substream *substream,
+ 			   SUN8I_AIF_CLK_CTRL_BCLK_DIV_MASK,
+ 			   bclk_div << SUN8I_AIF_CLK_CTRL_BCLK_DIV);
+ 
++	/* TODO: Implement clk driver for AC100 codec system clock */
++	if (scodec->ac100_regmap)
++		goto update_sample_rate;
++
+ 	/*
+ 	 * SYSCLK rate
+ 	 *
+@@ -667,6 +720,7 @@ static int sun8i_codec_hw_params(struct snd_pcm_substream *substream,
+ 		scodec->sysclk_refcnt++;
+ 	scodec->sysclk_rate = sysclk_rate;
+ 
++update_sample_rate:
+ 	aif->lrck_div_order = lrck_div_order;
+ 	aif->sample_rate = sample_rate;
+ 	aif->open_streams |= BIT(substream->stream);
+@@ -684,8 +738,11 @@ static int sun8i_codec_hw_free(struct snd_pcm_substream *substream,
+ 	if (aif->open_streams != BIT(substream->stream))
+ 		goto done;
+ 
+-	clk_rate_exclusive_put(scodec->clk_module);
+-	scodec->sysclk_refcnt--;
++	if (!scodec->ac100_regmap) {
++		clk_rate_exclusive_put(scodec->clk_module);
++		scodec->sysclk_refcnt--;
++	}
++
+ 	aif->lrck_div_order = 0;
+ 	aif->sample_rate = 0;
+ 
+@@ -958,8 +1015,6 @@ static const struct snd_kcontrol_new sun8i_dac_mixer_controls[] = {
+ 
+ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = {
+ 	/* System Clocks */
+-	SND_SOC_DAPM_CLOCK_SUPPLY("mod"),
+-
+ 	SND_SOC_DAPM_SUPPLY("AIF1CLK",
+ 			    SUN8I_SYSCLK_CTL,
+ 			    SUN8I_SYSCLK_CTL_AIF1CLK_ENA, 0, NULL, 0),
+@@ -1120,8 +1175,6 @@ static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets[] = {
+ 
+ static const struct snd_soc_dapm_route sun8i_codec_dapm_routes[] = {
+ 	/* Clock Routes */
+-	{ "AIF1CLK", NULL, "mod" },
+-
+ 	{ "SYSCLK", NULL, "AIF1CLK" },
+ 
+ 	{ "CLK AIF1", NULL, "AIF1CLK" },
+@@ -1291,6 +1344,16 @@ static const struct snd_soc_dapm_route sun8i_codec_legacy_routes[] = {
+ 	{ "AIF1 Slot 0 Right", NULL, "DACR" },
+ };
+ 
++static const struct snd_soc_dapm_widget sun8i_codec_dapm_widgets_sun8i[] = {
++	SND_SOC_DAPM_CLOCK_SUPPLY("mod"),
++};
++
++static const struct snd_soc_dapm_route sun8i_codec_dapm_routes_sun8i[] = {
++	{ "AIF1CLK", NULL, "mod" },
++};
++
++static int ac100_codec_component_probe(struct snd_soc_component *component);
++
+ static int sun8i_codec_component_probe(struct snd_soc_component *component)
+ {
+ 	struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
+@@ -1299,6 +1362,21 @@ static int sun8i_codec_component_probe(struct snd_soc_component *component)
+ 
+ 	scodec->component = component;
+ 
++	if (scodec->ac100_regmap)
++                return ac100_codec_component_probe(component);
++
++	ret = snd_soc_dapm_new_controls(dapm,
++					sun8i_codec_dapm_widgets_sun8i,
++					ARRAY_SIZE(sun8i_codec_dapm_widgets_sun8i));
++	if (ret)
++		return ret;
++
++	ret = snd_soc_dapm_add_routes(dapm,
++				      sun8i_codec_dapm_routes_sun8i,
++				      ARRAY_SIZE(sun8i_codec_dapm_routes_sun8i));
++	if (ret)
++		return ret;
++
+ 	/* Add widgets for backward compatibility with old device trees. */
+ 	if (scodec->quirks->legacy_widgets) {
+ 		ret = snd_soc_dapm_new_controls(dapm, sun8i_codec_legacy_widgets,
+@@ -1640,7 +1718,7 @@ static bool sun8i_codec_volatile_reg(struct device *dev, unsigned int reg)
+ 	return reg == SUN8I_HMIC_STS;
+ }
+ 
+-static const struct regmap_config sun8i_codec_regmap_config = {
++static struct regmap_config sun8i_codec_regmap_config = {
+ 	.reg_bits	= 32,
+ 	.reg_stride	= 4,
+ 	.val_bits	= 32,
+@@ -1650,12 +1728,124 @@ static const struct regmap_config sun8i_codec_regmap_config = {
+ 	.cache_type	= REGCACHE_FLAT,
+ };
+ 
++/* AC100 Codec Support (digital parts) */
++
++static int sun8i_codec_ac100_regmap_read(void *context,
++					 unsigned int reg, unsigned int *val)
++{
++	struct sun8i_codec *scodec = context;
++
++	return regmap_read(scodec->ac100_regmap, reg / 4, val);
++}
++
++static int sun8i_codec_ac100_regmap_write(void *context,
++					  unsigned int reg, unsigned int val)
++{
++	struct sun8i_codec *scodec = context;
++
++	return regmap_write(scodec->ac100_regmap, reg / 4, val);
++}
++
++static struct regmap_bus sun8i_codec_ac100_regmap_bus = {
++	.reg_write = sun8i_codec_ac100_regmap_write,
++	.reg_read = sun8i_codec_ac100_regmap_read,
++};
++
++static int ac100_codec_component_probe(struct snd_soc_component *component)
++{
++	struct sun8i_codec *scodec = snd_soc_component_get_drvdata(component);
++
++        /*
++	 * The system clock(SYSCLK) of AC100 must be 512*fs(fs=48KHz or 44.1KHz)
++	 * Source clocks from the SoC.
++	 */
++
++        regmap_update_bits(scodec->ac100_regmap, AC100_SYSCLK_CTRL,
++                            AC100_SYSCLK_CTRL_I2S1CLK_SRC_MASK,
++                            AC100_SYSCLK_CTRL_I2S1CLK_SRC_MCLK1);
++        regmap_update_bits(scodec->ac100_regmap, AC100_SYSCLK_CTRL,
++                            AC100_SYSCLK_CTRL_I2S2CLK_SRC_MASK,
++                            AC100_SYSCLK_CTRL_I2S2CLK_SRC_MCLK1);
++        regmap_update_bits(scodec->ac100_regmap, AC100_SYSCLK_CTRL,
++                            AC100_SYSCLK_CTRL_SYSCLK_SRC_MASK,
++                            AC100_SYSCLK_CTRL_SYSCLK_SRC_I2S1CLK);
++
++	/* Program the default sample rate. */
++	return sun8i_codec_update_sample_rate(scodec);
++}
++
++static int sun8i_codec_probe_ac100(struct platform_device *pdev)
++{
++	struct ac100_dev *ac100 = dev_get_drvdata(pdev->dev.parent);
++	struct device* dev = &pdev->dev;
++	struct sun8i_codec *scodec;
++	int ret, i;
++
++	scodec = devm_kzalloc(dev, sizeof(*scodec), GFP_KERNEL);
++	if (!scodec)
++		return -ENOMEM;
++
++	scodec->quirks = of_device_get_match_data(&pdev->dev);
++	scodec->ac100_regmap = ac100->regmap;
++
++	platform_set_drvdata(pdev, scodec);
++
++	/*
++	 * Caching is done by the MFD regmap, so disable the mapped regmap
++	 * cache.
++	 */
++	sun8i_codec_regmap_config.cache_type = REGCACHE_NONE;
++
++	/*
++	 * We need to create a custom regmap_bus that will map reads/writes to
++	 * the MFD regmap
++	 */
++	scodec->regmap = __regmap_lockdep_wrapper(__devm_regmap_init,
++		 "ac100-regmap-codec", dev,
++		  &sun8i_codec_ac100_regmap_bus, scodec,
++		  &sun8i_codec_regmap_config);
++	if (IS_ERR(scodec->regmap))
++		return dev_err_probe(dev, PTR_ERR(scodec->regmap),
++				     "Failed to create our regmap\n");
++
++	for (i = 0; i < ARRAY_SIZE(scodec->supplies); i++)
++		scodec->supplies[i].supply = ac100_supply_names[i];
++
++        ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(scodec->supplies),
++                                      scodec->supplies);
++        if (ret)
++		return dev_err_probe(dev, ret, "Failed to request supplies\n");
++
++	ret = regulator_bulk_enable(ARRAY_SIZE(scodec->supplies),
++				    scodec->supplies);
++	if (ret)
++		return dev_err_probe(dev, ret, "Failed to enable supplies\n");
++
++	ret = devm_snd_soc_register_component(dev, &sun8i_soc_component,
++					      sun8i_codec_dais,
++					      ARRAY_SIZE(sun8i_codec_dais));
++	if (ret) {
++		dev_err_probe(dev, ret, "Failed to register codec\n");
++		goto err_disable_reg;
++	}
++
++	return 0;
++
++err_disable_reg:
++	regulator_bulk_disable(ARRAY_SIZE(scodec->supplies),
++			       scodec->supplies);
++	return ret;
++}
++
+ static int sun8i_codec_probe(struct platform_device *pdev)
+ {
+ 	struct sun8i_codec *scodec;
+ 	void __iomem *base;
+ 	int ret;
+ 
++	if (of_device_is_compatible(pdev->dev.of_node, "x-powers,ac100-codec"))
++		return sun8i_codec_probe_ac100(pdev);
++
+ 	scodec = devm_kzalloc(&pdev->dev, sizeof(*scodec), GFP_KERNEL);
+ 	if (!scodec)
+ 		return -ENOMEM;
+@@ -1728,6 +1918,14 @@ static int sun8i_codec_probe(struct platform_device *pdev)
+ 
+ static void sun8i_codec_remove(struct platform_device *pdev)
+ {
++	struct sun8i_codec *scodec = dev_get_drvdata(&pdev->dev);
++
++	if (scodec->ac100_regmap) {
++		regulator_bulk_disable(ARRAY_SIZE(scodec->supplies),
++				       scodec->supplies);
++		return;
++	}
++
+ 	pm_runtime_disable(&pdev->dev);
+ 	if (!pm_runtime_status_suspended(&pdev->dev))
+ 		sun8i_codec_runtime_suspend(&pdev->dev);
+@@ -1744,9 +1942,13 @@ static const struct sun8i_codec_quirks sun50i_a64_quirks = {
+ 	.jack_detection	= true,
+ };
+ 
++static const struct sun8i_codec_quirks ac100_quirks = {
++};
++
+ static const struct of_device_id sun8i_codec_of_match[] = {
+ 	{ .compatible = "allwinner,sun8i-a33-codec", .data = &sun8i_a33_quirks },
+ 	{ .compatible = "allwinner,sun50i-a64-codec", .data = &sun50i_a64_quirks },
++	{ .compatible = "x-powers,ac100-codec", .data = &ac100_quirks },
+ 	{}
+ };
+ MODULE_DEVICE_TABLE(of, sun8i_codec_of_match);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/sunxi-Use-dev_err_probe-to-handle-EPROBE_DEFER-errors.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/sunxi-Use-dev_err_probe-to-handle-EPROBE_DEFER-errors.patch
new file mode 100644
index 000000000000..7ae868ce5db9
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/sunxi-Use-dev_err_probe-to-handle-EPROBE_DEFER-errors.patch
@@ -0,0 +1,150 @@
+From d4a21d660b3fd92157aef4a08d0451c171c529e9 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 2 Sep 2019 14:51:17 +0200
+Subject: sunxi: Use dev_err_probe to handle EPROBE_DEFER errors
+
+This makes it easier to debug EPROBE_DEFER issues via debugfs.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ arch/arm/kernel/topology.c                    |  2 +-
+ drivers/gpu/drm/panel/panel-sitronix-st7703.c |  2 +-
+ drivers/i2c/busses/i2c-gpio.c                 | 11 +++++++++--
+ drivers/phy/allwinner/phy-sun4i-usb.c         | 16 ++++++++++------
+ drivers/phy/allwinner/phy-sun6i-mipi-dphy.c   |  6 ++++--
+ 5 files changed, 25 insertions(+), 12 deletions(-)
+
+diff --git a/arch/arm/kernel/topology.c b/arch/arm/kernel/topology.c
+index 2336ee2aa44a..20efde3cb1c2 100644
+--- a/arch/arm/kernel/topology.c
++++ b/arch/arm/kernel/topology.c
+@@ -121,7 +121,7 @@ static void __init parse_dt_topology(void)
+ 
+ 		rate = of_get_property(cn, "clock-frequency", &len);
+ 		if (!rate || len != 4) {
+-			pr_err("%pOF missing clock-frequency property\n", cn);
++			//pr_err("%pOF missing clock-frequency property\n", cn);
+ 			continue;
+ 		}
+ 
+diff --git a/drivers/gpu/drm/panel/panel-sitronix-st7703.c b/drivers/gpu/drm/panel/panel-sitronix-st7703.c
+index 8e359c9e0a09..ff6871e93730 100644
+--- a/drivers/gpu/drm/panel/panel-sitronix-st7703.c
++++ b/drivers/gpu/drm/panel/panel-sitronix-st7703.c
+@@ -904,7 +904,7 @@ static int st7703_probe(struct mipi_dsi_device *dsi)
+ 
+ 	ret = mipi_dsi_attach(dsi);
+ 	if (ret < 0) {
+-		dev_err(dev, "mipi_dsi_attach failed (%d). Is host ready?\n", ret);
++		dev_err_probe(dev, ret, "mipi_dsi_attach failed\n");
+ 		drm_panel_remove(&ctx->panel);
+ 		return ret;
+ 	}
+diff --git a/drivers/i2c/busses/i2c-gpio.c b/drivers/i2c/busses/i2c-gpio.c
+index f4355b17bfbf..3f158ca4b58f 100644
+--- a/drivers/i2c/busses/i2c-gpio.c
++++ b/drivers/i2c/busses/i2c-gpio.c
+@@ -314,6 +314,13 @@ static struct gpio_desc *i2c_gpio_get_desc(struct device *dev,
+ 		return retdesc;
+ 	}
+ 
++	/* return early so that EPROBE_DEFER is not ignored on named gpios */
++	if (PTR_ERR(retdesc) == -EPROBE_DEFER) {
++		dev_err_probe(dev, PTR_ERR(retdesc),
++			      "error trying to get descriptor\n");
++		return retdesc;
++	}
++
+ 	retdesc = devm_gpiod_get_index(dev, NULL, index, gflags);
+ 	if (!IS_ERR(retdesc)) {
+ 		dev_dbg(dev, "got GPIO from index %u\n", index);
+@@ -330,8 +337,8 @@ static struct gpio_desc *i2c_gpio_get_desc(struct device *dev,
+ 	if (ret == -ENOENT)
+ 		retdesc = ERR_PTR(-EPROBE_DEFER);
+ 
+-	if (PTR_ERR(retdesc) != -EPROBE_DEFER)
+-		dev_err(dev, "error trying to get descriptor: %d\n", ret);
++	dev_err_probe(dev, PTR_ERR(retdesc),
++		      "error trying to get descriptor\n");
+ 
+ 	return retdesc;
+ }
+diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c
+index 3a42865f9a5b..3d8d94594bc5 100644
+--- a/drivers/phy/allwinner/phy-sun4i-usb.c
++++ b/drivers/phy/allwinner/phy-sun4i-usb.c
+@@ -774,14 +774,16 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
+ 	data->id_det_gpio = devm_gpiod_get_optional(dev, "usb0_id_det",
+ 						    GPIOD_IN);
+ 	if (IS_ERR(data->id_det_gpio)) {
+-		dev_err(dev, "Couldn't request ID GPIO\n");
++		dev_err_probe(dev, PTR_ERR(data->id_det_gpio),
++			      "Couldn't request ID GPIO\n");
+ 		return PTR_ERR(data->id_det_gpio);
+ 	}
+ 
+ 	data->vbus_det_gpio = devm_gpiod_get_optional(dev, "usb0_vbus_det",
+ 						      GPIOD_IN);
+ 	if (IS_ERR(data->vbus_det_gpio)) {
+-		dev_err(dev, "Couldn't request VBUS detect GPIO\n");
++		dev_err_probe(dev, PTR_ERR(data->vbus_det_gpio),
++			      "Couldn't request VBUS detect GPIO\n");
+ 		return PTR_ERR(data->vbus_det_gpio);
+ 	}
+ 
+@@ -789,7 +791,8 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
+ 		data->vbus_power_supply = devm_power_supply_get_by_phandle(dev,
+ 						     "usb0_vbus_power-supply");
+ 		if (IS_ERR(data->vbus_power_supply)) {
+-			dev_err(dev, "Couldn't get the VBUS power supply\n");
++			dev_err_probe(dev, PTR_ERR(data->vbus_power_supply),
++				      "Couldn't get the VBUS power supply\n");
+ 			return PTR_ERR(data->vbus_power_supply);
+ 		}
+ 
+@@ -822,8 +825,8 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
+ 		phy->vbus = devm_regulator_get_optional(dev, name);
+ 		if (IS_ERR(phy->vbus)) {
+ 			if (PTR_ERR(phy->vbus) == -EPROBE_DEFER) {
+-				dev_err(dev,
+-					"Couldn't get regulator %s... Deferring probe\n",
++				dev_err_probe(dev, PTR_ERR(phy->vbus),
++					"Couldn't get regulator %s\n",
+ 					name);
+ 				return -EPROBE_DEFER;
+ 			}
+@@ -838,7 +841,8 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
+ 
+ 		phy->clk = devm_clk_get(dev, name);
+ 		if (IS_ERR(phy->clk)) {
+-			dev_err(dev, "failed to get clock %s\n", name);
++			dev_err_probe(dev, PTR_ERR(phy->clk),
++				      "failed to get clock %s\n", name);
+ 			return PTR_ERR(phy->clk);
+ 		}
+ 
+diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
+index a19a27cea860..0107514e7d2b 100644
+--- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
++++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
+@@ -584,13 +584,15 @@ static int sun6i_dphy_probe(struct platform_device *pdev)
+ 	dphy->regs = devm_regmap_init_mmio_clk(&pdev->dev, "bus",
+ 					       regs, &sun6i_dphy_regmap_config);
+ 	if (IS_ERR(dphy->regs)) {
+-		dev_err(&pdev->dev, "Couldn't create the DPHY encoder regmap\n");
++		dev_err_probe(&pdev->dev, PTR_ERR(dphy->regs),
++			      "Couldn't create the DPHY encoder regmap\n");
+ 		return PTR_ERR(dphy->regs);
+ 	}
+ 
+ 	dphy->reset = devm_reset_control_get_shared(&pdev->dev, NULL);
+ 	if (IS_ERR(dphy->reset)) {
+-		dev_err(&pdev->dev, "Couldn't get our reset line\n");
++		dev_err_probe(&pdev->dev, PTR_ERR(dphy->reset),
++			      "Couldn't get our reset line\n");
+ 		return PTR_ERR(dphy->reset);
+ 	}
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/thermal-sun8i-Be-loud-when-probe-fails.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/thermal-sun8i-Be-loud-when-probe-fails.patch
new file mode 100644
index 000000000000..8826a4a6f8f5
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/thermal-sun8i-Be-loud-when-probe-fails.patch
@@ -0,0 +1,88 @@
+From a1a6076e6a12342802c48ab522e841b8386ab0fc Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Wed, 8 Jul 2020 12:21:14 +0200
+Subject: thermal: sun8i: Be loud when probe fails
+
+I noticed several mobile Linux distributions failing to enable the
+thermal regulation correctly, because the kernel is silent
+when thermal driver fails to probe. Add enough error reporting
+to debug issues and warn users in case thermal sensor is failing
+to probe.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/thermal/sun8i_thermal.c | 22 +++++++++++++++++++---
+ 1 file changed, 19 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/thermal/sun8i_thermal.c b/drivers/thermal/sun8i_thermal.c
+index 22674790629a..1fc7fe3a1531 100644
+--- a/drivers/thermal/sun8i_thermal.c
++++ b/drivers/thermal/sun8i_thermal.c
+@@ -309,8 +309,13 @@ static int sun8i_ths_calibrate(struct ths_device *tmdev)
+ 
+ 	calcell = nvmem_cell_get(dev, "calibration");
+ 	if (IS_ERR(calcell)) {
++		dev_err_probe(dev, PTR_ERR(calcell),
++			      "Failed to get calibration nvmem cell (%pe)\n",
++			      calcell);
++
+ 		if (PTR_ERR(calcell) == -EPROBE_DEFER)
+ 			return -EPROBE_DEFER;
++
+ 		/*
+ 		 * Even if the external calibration data stored in sid is
+ 		 * not accessible, the THS hardware can still work, although
+@@ -330,6 +335,8 @@ static int sun8i_ths_calibrate(struct ths_device *tmdev)
+ 	caldata = nvmem_cell_read(calcell, &callen);
+ 	if (IS_ERR(caldata)) {
+ 		ret = PTR_ERR(caldata);
++		dev_err(dev, "Failed to read calibration data (%pe)\n",
++			caldata);
+ 		goto out;
+ 	}
+ 
+@@ -385,13 +392,17 @@ static int sun8i_ths_resource_init(struct ths_device *tmdev)
+ 		return PTR_ERR(base);
+ 
+ 	tmdev->regmap = devm_regmap_init_mmio(dev, base, &config);
+-	if (IS_ERR(tmdev->regmap))
++	if (IS_ERR(tmdev->regmap)) {
++		dev_err(dev, "Failed to init regmap (%pe)\n", tmdev->regmap);
+ 		return PTR_ERR(tmdev->regmap);
++	}
+ 
+ 	if (tmdev->chip->has_bus_clk_reset) {
+ 		tmdev->reset = devm_reset_control_get(dev, NULL);
+-		if (IS_ERR(tmdev->reset))
++		if (IS_ERR(tmdev->reset)) {
++			dev_err(dev, "Failed to get reset (%pe)\n", tmdev->reset);
+ 			return PTR_ERR(tmdev->reset);
++		}
+ 
+ 		ret = reset_control_deassert(tmdev->reset);
+ 		if (ret)
+@@ -542,6 +553,9 @@ static int sun8i_ths_register(struct ths_device *tmdev)
+ 		if (IS_ERR(tmdev->sensor[i].tzd)) {
+ 			if (PTR_ERR(tmdev->sensor[i].tzd) == -EPROBE_DEFER)
+ 				return PTR_ERR(tmdev->sensor[i].tzd);
++			dev_err(tmdev->dev,
++				"Failed to register sensor %d (%pe)\n",
++				i, tmdev->sensor[i].tzd);
+ 			continue;
+ 		}
+ 
+@@ -590,8 +604,10 @@ static int sun8i_ths_probe(struct platform_device *pdev)
+ 	ret = devm_request_threaded_irq(dev, irq, NULL,
+ 					sun8i_irq_thread,
+ 					IRQF_ONESHOT, "ths", tmdev);
+-	if (ret)
++	if (ret) {
++		dev_err(dev, "Failed to request irq (%d)\n", ret);
+ 		return ret;
++	}
+ 
+ 	return 0;
+ }
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/usb-gadget-Fix-dangling-pointer-in-netdev-private-data.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/usb-gadget-Fix-dangling-pointer-in-netdev-private-data.patch
new file mode 100644
index 000000000000..ea0cf34ca45a
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/usb-gadget-Fix-dangling-pointer-in-netdev-private-data.patch
@@ -0,0 +1,307 @@
+From f2dc4bc534baf1d2cf7f43dbf040601e1542f9c5 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Thu, 7 Sep 2023 14:07:26 +0200
+Subject: usb: gadget: Fix dangling pointer in netdev private data
+
+Some USB drivers destroy and re-create the gadget regularly. This
+leads to stale gadget pointer in gether_* using USB gadget functions
+(ecm, eem, ncm, rndis, etc.).
+
+Don't parent the netdev to the gadget device, and set gadget to
+NULL in function unbind callback, to avoid potential user-after-free
+issues.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/gadget/function/f_ecm.c    | 12 ++++++-----
+ drivers/usb/gadget/function/f_eem.c    | 28 +++++++++++++-------------
+ drivers/usb/gadget/function/f_ncm.c    |  9 ++++++---
+ drivers/usb/gadget/function/f_rndis.c  | 26 ++++++++++++------------
+ drivers/usb/gadget/function/f_subset.c | 18 +++++++++++------
+ drivers/usb/gadget/function/u_ether.c  | 10 ++++-----
+ 6 files changed, 56 insertions(+), 47 deletions(-)
+
+diff --git a/drivers/usb/gadget/function/f_ecm.c b/drivers/usb/gadget/function/f_ecm.c
+index 80841de845b0..4758994b5f26 100644
+--- a/drivers/usb/gadget/function/f_ecm.c
++++ b/drivers/usb/gadget/function/f_ecm.c
+@@ -685,14 +685,12 @@ ecm_bind(struct usb_configuration *c, struct usb_function *f)
+ 	ecm_opts = container_of(f->fi, struct f_ecm_opts, func_inst);
+ 
+ 	mutex_lock(&ecm_opts->lock);
+-
+ 	gether_set_gadget(ecm_opts->net, cdev->gadget);
+-
+ 	if (!ecm_opts->bound) {
+ 		status = gether_register_netdev(ecm_opts->net);
+-		ecm_opts->bound = true;
++		if (!status)
++			ecm_opts->bound = true;
+ 	}
+-
+ 	mutex_unlock(&ecm_opts->lock);
+ 	if (status)
+ 		return status;
+@@ -907,7 +905,9 @@ static void ecm_free(struct usb_function *f)
+ 
+ static void ecm_unbind(struct usb_configuration *c, struct usb_function *f)
+ {
+-	struct f_ecm		*ecm = func_to_ecm(f);
++	struct f_ecm *ecm = func_to_ecm(f);
++	struct f_ecm_opts *opts = container_of(f->fi, struct f_ecm_opts,
++					       func_inst);
+ 
+ 	DBG(c->cdev, "ecm unbind\n");
+ 
+@@ -920,6 +920,8 @@ static void ecm_unbind(struct usb_configuration *c, struct usb_function *f)
+ 
+ 	kfree(ecm->notify_req->buf);
+ 	usb_ep_free_request(ecm->notify, ecm->notify_req);
++
++	gether_set_gadget(opts->net, NULL);
+ }
+ 
+ static struct usb_function *ecm_alloc(struct usb_function_instance *fi)
+diff --git a/drivers/usb/gadget/function/f_eem.c b/drivers/usb/gadget/function/f_eem.c
+index 6de81ea17274..b1e1a26808dd 100644
+--- a/drivers/usb/gadget/function/f_eem.c
++++ b/drivers/usb/gadget/function/f_eem.c
+@@ -247,28 +247,23 @@ static int eem_bind(struct usb_configuration *c, struct usb_function *f)
+ 	struct usb_composite_dev *cdev = c->cdev;
+ 	struct f_eem		*eem = func_to_eem(f);
+ 	struct usb_string	*us;
+-	int			status;
++	int			status = 0;
+ 	struct usb_ep		*ep;
+ 
+ 	struct f_eem_opts	*eem_opts;
+ 
+ 	eem_opts = container_of(f->fi, struct f_eem_opts, func_inst);
+-	/*
+-	 * in drivers/usb/gadget/configfs.c:configfs_composite_bind()
+-	 * configurations are bound in sequence with list_for_each_entry,
+-	 * in each configuration its functions are bound in sequence
+-	 * with list_for_each_entry, so we assume no race condition
+-	 * with regard to eem_opts->bound access
+-	 */
++
++	mutex_lock(&eem_opts->lock);
++	gether_set_gadget(eem_opts->net, cdev->gadget);
+ 	if (!eem_opts->bound) {
+-		mutex_lock(&eem_opts->lock);
+-		gether_set_gadget(eem_opts->net, cdev->gadget);
+ 		status = gether_register_netdev(eem_opts->net);
+-		mutex_unlock(&eem_opts->lock);
+-		if (status)
+-			return status;
+-		eem_opts->bound = true;
++		if (!status)
++			eem_opts->bound = true;
+ 	}
++	mutex_unlock(&eem_opts->lock);
++	if (status)
++		return status;
+ 
+ 	us = usb_gstrings_attach(cdev, eem_strings,
+ 				 ARRAY_SIZE(eem_string_defs));
+@@ -635,9 +630,14 @@ static void eem_free(struct usb_function *f)
+ 
+ static void eem_unbind(struct usb_configuration *c, struct usb_function *f)
+ {
++	struct f_eem_opts *opts = container_of(f->fi, struct f_eem_opts,
++					       func_inst);
++
+ 	DBG(c->cdev, "eem unbind\n");
+ 
+ 	usb_free_all_descriptors(f);
++
++	gether_set_gadget(opts->net, NULL);
+ }
+ 
+ static struct usb_function *eem_alloc(struct usb_function_instance *fi)
+diff --git a/drivers/usb/gadget/function/f_ncm.c b/drivers/usb/gadget/function/f_ncm.c
+index f60576a65ca6..454a451491b1 100644
+--- a/drivers/usb/gadget/function/f_ncm.c
++++ b/drivers/usb/gadget/function/f_ncm.c
+@@ -1455,14 +1455,13 @@ static int ncm_bind(struct usb_configuration *c, struct usb_function *f)
+ 	if (!ncm_opts->bound) {
+ 		ncm_opts->net->mtu = (ncm_opts->max_segment_size - ETH_HLEN);
+ 		status = gether_register_netdev(ncm_opts->net);
++		if (!status)
++			ncm_opts->bound = true;
+ 	}
+ 	mutex_unlock(&ncm_opts->lock);
+-
+ 	if (status)
+ 		goto fail;
+ 
+-	ncm_opts->bound = true;
+-
+ 	us = usb_gstrings_attach(cdev, ncm_strings,
+ 				 ARRAY_SIZE(ncm_string_defs));
+ 	if (IS_ERR(us)) {
+@@ -1729,6 +1728,8 @@ static void ncm_free(struct usb_function *f)
+ static void ncm_unbind(struct usb_configuration *c, struct usb_function *f)
+ {
+ 	struct f_ncm *ncm = func_to_ncm(f);
++	struct f_ncm_opts *opts = container_of(f->fi, struct f_ncm_opts,
++					       func_inst);
+ 
+ 	DBG(c->cdev, "ncm unbind\n");
+ 
+@@ -1747,6 +1748,8 @@ static void ncm_unbind(struct usb_configuration *c, struct usb_function *f)
+ 
+ 	kfree(ncm->notify_req->buf);
+ 	usb_ep_free_request(ncm->notify, ncm->notify_req);
++
++	gether_set_gadget(opts->net, NULL);
+ }
+ 
+ static struct usb_function *ncm_alloc(struct usb_function_instance *fi)
+diff --git a/drivers/usb/gadget/function/f_rndis.c b/drivers/usb/gadget/function/f_rndis.c
+index 7cec19d65fb5..c2138f17a1c4 100644
+--- a/drivers/usb/gadget/function/f_rndis.c
++++ b/drivers/usb/gadget/function/f_rndis.c
+@@ -658,7 +658,7 @@ rndis_bind(struct usb_configuration *c, struct usb_function *f)
+ 	struct usb_composite_dev *cdev = c->cdev;
+ 	struct f_rndis		*rndis = func_to_rndis(f);
+ 	struct usb_string	*us;
+-	int			status;
++	int			status = 0;
+ 	struct usb_ep		*ep;
+ 
+ 	struct f_rndis_opts *rndis_opts;
+@@ -681,20 +681,16 @@ rndis_bind(struct usb_configuration *c, struct usb_function *f)
+ 	rndis_iad_descriptor.bFunctionSubClass = rndis_opts->subclass;
+ 	rndis_iad_descriptor.bFunctionProtocol = rndis_opts->protocol;
+ 
+-	/*
+-	 * in drivers/usb/gadget/configfs.c:configfs_composite_bind()
+-	 * configurations are bound in sequence with list_for_each_entry,
+-	 * in each configuration its functions are bound in sequence
+-	 * with list_for_each_entry, so we assume no race condition
+-	 * with regard to rndis_opts->bound access
+-	 */
++	mutex_lock(&rndis_opts->lock);
++	gether_set_gadget(rndis_opts->net, cdev->gadget);
+ 	if (!rndis_opts->bound) {
+-		gether_set_gadget(rndis_opts->net, cdev->gadget);
+ 		status = gether_register_netdev(rndis_opts->net);
+-		if (status)
+-			goto fail;
+-		rndis_opts->bound = true;
++		if (!status)
++			rndis_opts->bound = true;
+ 	}
++	mutex_unlock(&rndis_opts->lock);
++	if (status)
++		goto fail;
+ 
+ 	us = usb_gstrings_attach(cdev, rndis_strings,
+ 				 ARRAY_SIZE(rndis_string_defs));
+@@ -954,7 +950,9 @@ static void rndis_free(struct usb_function *f)
+ 
+ static void rndis_unbind(struct usb_configuration *c, struct usb_function *f)
+ {
+-	struct f_rndis		*rndis = func_to_rndis(f);
++	struct f_rndis *rndis = func_to_rndis(f);
++	struct f_rndis_opts *opts = container_of(f->fi, struct f_rndis_opts,
++						 func_inst);
+ 
+ 	kfree(f->os_desc_table);
+ 	f->os_desc_n = 0;
+@@ -962,6 +960,8 @@ static void rndis_unbind(struct usb_configuration *c, struct usb_function *f)
+ 
+ 	kfree(rndis->notify_req->buf);
+ 	usb_ep_free_request(rndis->notify, rndis->notify_req);
++
++	gether_set_gadget(opts->net, NULL);
+ }
+ 
+ static struct usb_function *rndis_alloc(struct usb_function_instance *fi)
+diff --git a/drivers/usb/gadget/function/f_subset.c b/drivers/usb/gadget/function/f_subset.c
+index ea3fdd842462..b595beb5f474 100644
+--- a/drivers/usb/gadget/function/f_subset.c
++++ b/drivers/usb/gadget/function/f_subset.c
+@@ -308,15 +308,16 @@ geth_bind(struct usb_configuration *c, struct usb_function *f)
+ 	 * with list_for_each_entry, so we assume no race condition
+ 	 * with regard to gether_opts->bound access
+ 	 */
++	mutex_lock(&gether_opts->lock);
++	gether_set_gadget(gether_opts->net, cdev->gadget);
+ 	if (!gether_opts->bound) {
+-		mutex_lock(&gether_opts->lock);
+-		gether_set_gadget(gether_opts->net, cdev->gadget);
+ 		status = gether_register_netdev(gether_opts->net);
+-		mutex_unlock(&gether_opts->lock);
+-		if (status)
+-			return status;
+-		gether_opts->bound = true;
++		if (!status)
++			gether_opts->bound = true;
+ 	}
++	mutex_unlock(&gether_opts->lock);
++	if (status)
++		return status;
+ 
+ 	us = usb_gstrings_attach(cdev, geth_strings,
+ 				 ARRAY_SIZE(geth_string_defs));
+@@ -456,8 +457,13 @@ static void geth_free(struct usb_function *f)
+ 
+ static void geth_unbind(struct usb_configuration *c, struct usb_function *f)
+ {
++	struct f_gether_opts *opts = container_of(f->fi, struct f_gether_opts,
++						  func_inst);
++
+ 	geth_string_defs[0].id = 0;
+ 	usb_free_all_descriptors(f);
++
++	gether_set_gadget(opts->net, NULL);
+ }
+ 
+ static struct usb_function *geth_alloc(struct usb_function_instance *fi)
+diff --git a/drivers/usb/gadget/function/u_ether.c b/drivers/usb/gadget/function/u_ether.c
+index f58590bf5e02..a522e9d43a3a 100644
+--- a/drivers/usb/gadget/function/u_ether.c
++++ b/drivers/usb/gadget/function/u_ether.c
+@@ -112,8 +112,10 @@ static void eth_get_drvinfo(struct net_device *net, struct ethtool_drvinfo *p)
+ 
+ 	strscpy(p->driver, "g_ether", sizeof(p->driver));
+ 	strscpy(p->version, UETH__VERSION, sizeof(p->version));
+-	strscpy(p->fw_version, dev->gadget->name, sizeof(p->fw_version));
+-	strscpy(p->bus_info, dev_name(&dev->gadget->dev), sizeof(p->bus_info));
++	if (dev->gadget) {
++		strscpy(p->fw_version, dev->gadget->name, sizeof(p->fw_version));
++		strscpy(p->bus_info, dev_name(&dev->gadget->dev), sizeof(p->bus_info));
++	}
+ }
+ 
+ /* REVISIT can also support:
+@@ -787,7 +789,6 @@ struct eth_dev *gether_setup_name(struct usb_gadget *g,
+ 	net->max_mtu = GETHER_MAX_MTU_SIZE;
+ 
+ 	dev->gadget = g;
+-	SET_NETDEV_DEV(net, &g->dev);
+ 	SET_NETDEV_DEVTYPE(net, &gadget_type);
+ 
+ 	status = register_netdev(net);
+@@ -860,8 +861,6 @@ int gether_register_netdev(struct net_device *net)
+ 	struct usb_gadget *g;
+ 	int status;
+ 
+-	if (!net->dev.parent)
+-		return -EINVAL;
+ 	dev = netdev_priv(net);
+ 	g = dev->gadget;
+ 
+@@ -892,7 +891,6 @@ void gether_set_gadget(struct net_device *net, struct usb_gadget *g)
+ 
+ 	dev = netdev_priv(net);
+ 	dev->gadget = g;
+-	SET_NETDEV_DEV(net, &g->dev);
+ }
+ EXPORT_SYMBOL_GPL(gether_set_gadget);
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/usb-musb-sunxi-Avoid-enabling-host-side-code-on-SoCs-where-it-s.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/usb-musb-sunxi-Avoid-enabling-host-side-code-on-SoCs-where-it-s.patch
new file mode 100644
index 000000000000..501c5fb6a4aa
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/usb-musb-sunxi-Avoid-enabling-host-side-code-on-SoCs-where-it-s.patch
@@ -0,0 +1,107 @@
+From 0766c518fb42f94f9ae7c24dcdaf79423eaa3b43 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Mon, 6 Mar 2023 01:19:52 +0100
+Subject: usb: musb: sunxi: Avoid enabling host side code on SoCs where it's
+ not used
+
+For some sunxi SoCs host side code is active but unused, because
+phy re-routes USB handling to a regular EHCI/OHCI driver.
+
+When host side code of musb is left initialized it sometimes
+interferes with suspend to RAM. Disabling the host side code
+on SoCs that re-route host mode to a regular *HCI hardware
+block fixes the issue.
+
+Issue: https://gitlab.com/postmarketOS/pmaports/-/issues/1478
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/musb/musb_core.c | 10 ++++++++++
+ drivers/usb/musb/sunxi.c     | 30 +++++++++++++++++++++++-------
+ 2 files changed, 33 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c
+index 7f349f5e781d..521074d68c3b 100644
+--- a/drivers/usb/musb/musb_core.c
++++ b/drivers/usb/musb/musb_core.c
+@@ -976,6 +976,16 @@ static void musb_handle_intr_disconnect(struct musb *musb, u8 devctl)
+ 	case OTG_STATE_B_IDLE:
+ 		musb_g_disconnect(musb);
+ 		break;
++	case OTG_STATE_A_WAIT_VRISE:
++		/*
++		 * For sunxi use case, where host side of the musb driver
++		 * is not used for host mode, we want to ignore
++		 * OTG_STATE_A_WAIT_VRISE state set in sunxi glue code
++		 * when transitioning to host mode on disconnect, in
++		 * order to not confuse the dmesg reader about possible
++		 * issues.
++		 */
++		break;
+ 	default:
+ 		WARNING("unhandled DISCONNECT transition (%s)\n",
+ 			musb_otg_state_string(musb));
+diff --git a/drivers/usb/musb/sunxi.c b/drivers/usb/musb/sunxi.c
+index eac1cde86be3..e7b9c9bd56aa 100644
+--- a/drivers/usb/musb/sunxi.c
++++ b/drivers/usb/musb/sunxi.c
+@@ -350,12 +350,6 @@ static int sunxi_musb_set_mode(struct musb *musb, u8 mode)
+ 	if (glue->phy_mode == new_mode)
+ 		return 0;
+ 
+-	if (musb->port_mode != MUSB_OTG) {
+-		dev_err(musb->controller->parent,
+-			"Error changing modes is only supported in dual role mode\n");
+-		return -EINVAL;
+-	}
+-
+ 	if (musb->port1_status & USB_PORT_STAT_ENABLE)
+ 		musb_root_disconnect(musb);
+ 
+@@ -674,13 +668,22 @@ static const struct musb_hdrc_config sunxi_musb_hdrc_config_4eps = {
+ 	.ram_bits	= SUNXI_MUSB_RAM_BITS,
+ };
+ 
++static const char * const sunxi_musb_host_rerouted_phys[] = {
++	"allwinner,sun8i-h3-usb-phy",
++	"allwinner,sun8i-r40-usb-phy",
++	"allwinner,sun8i-v3s-usb-phy",
++	"allwinner,sun50i-a64-usb-phy",
++	"allwinner,sun50i-h6-usb-phy",
++	NULL,
++};
++
+ static int sunxi_musb_probe(struct platform_device *pdev)
+ {
+ 	struct musb_hdrc_platform_data	pdata;
+ 	struct platform_device_info	pinfo;
+ 	struct sunxi_glue		*glue;
+-	struct device_node		*np = pdev->dev.of_node;
+ 	const struct sunxi_musb_cfg	*cfg;
++	struct device_node		*np = pdev->dev.of_node, *phy_np;
+ 	int ret;
+ 
+ 	if (!np) {
+@@ -761,6 +764,19 @@ static int sunxi_musb_probe(struct platform_device *pdev)
+ 		return dev_err_probe(&pdev->dev, PTR_ERR(glue->phy),
+ 				     "Error getting phy\n");
+ 
++	/*
++	 * Host mode is handled outside of the musb driver on some allwinner
++	 * SoCs. We don't need musb host side code to be enabled at all.
++	 * In fact it causes occasional issues with suspend to ram, when
++	 * the host side code is enabled and unused (due to phy being re-routed
++	 * to a different *HCI controller).
++	 */
++	phy_np = glue->phy->dev.of_node;
++	if (of_device_compatible_match(phy_np, sunxi_musb_host_rerouted_phys)) {
++		dev_info(&pdev->dev, "Disabling musb host side code due to re-routed phy\n");
++		pdata.mode = MUSB_PERIPHERAL;
++	}
++
+ 	glue->usb_phy = usb_phy_generic_register();
+ 	if (IS_ERR(glue->usb_phy)) {
+ 		dev_err(&pdev->dev, "Error registering usb-phy %ld\n",
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/usb-serial-option-add-reset_resume-callback-for-WWAN-devices.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/usb-serial-option-add-reset_resume-callback-for-WWAN-devices.patch
new file mode 100644
index 000000000000..9001f922ab63
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/usb-serial-option-add-reset_resume-callback-for-WWAN-devices.patch
@@ -0,0 +1,33 @@
+From 0e8b72e264443819a1e8674ac9318ec382c84050 Mon Sep 17 00:00:00 2001
+From: Thomas Thorne <Thomas.Thorne@Net2Edge.com>
+Date: Tue, 20 Sep 2022 20:34:57 -0400
+Subject: usb: serial: option: add 'reset_resume' callback for WWAN devices
+
+This avoids the issue where the PPP modem does not reset correctly on resume,
+causing issues with incoming calls on suspend.
+
+Noted here: https://github.com/the-modem-distro/pinephone_modem_sdk/issues/97
+
+This is part of a larger patch:
+https://github.com/Quectel-Community/meta-quectel-community/commit/24adef2128f79b4d31490634438a917b3df462e2#diff-45dc5960ca2f1ef57139fe751587b3b043de9cca5864e2801210c00e75bd0780
+
+However the rest of the patch is not needed/already upstreamed.
+---
+ drivers/usb/serial/option.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/usb/serial/option.c b/drivers/usb/serial/option.c
+index 5cd26dac2069..f65c1d78a2cc 100644
+--- a/drivers/usb/serial/option.c
++++ b/drivers/usb/serial/option.c
+@@ -2471,6 +2471,7 @@ static struct usb_serial_driver option_1port_device = {
+ #ifdef CONFIG_PM
+ 	.suspend           = usb_wwan_suspend,
+ 	.resume            = usb_wwan_resume,
++	.reset_resume	   = usb_wwan_resume,
+ #endif
+ };
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-altmodes-displayport-Respect-DP_CAP_RECEPTACLE-bit.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-altmodes-displayport-Respect-DP_CAP_RECEPTACLE-bit.patch
new file mode 100644
index 000000000000..753bdb81747b
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-altmodes-displayport-Respect-DP_CAP_RECEPTACLE-bit.patch
@@ -0,0 +1,99 @@
+From d7895c7ef2ffbb7c8ad7e949a4427e82c77150e6 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Mon, 5 Sep 2022 00:56:07 +0200
+Subject: usb: typec: altmodes: displayport: Respect DP_CAP_RECEPTACLE bit
+
+DP_CAP_RECEPTACLE swaps the meaning of pin assignments. So eg.
+pin assignments for DFP_D plug are stored in DP_CAP_UFP_D_PIN_ASSIGN
+bits. Yes, it's slightly confusing. :)
+
+Make the kernel report lack of match in supported pin configurations
+between connected ports, so that the user is not confused why their
+USB-C dock doesn't have working Alt-DP mode, in case the dock returns
+wrong VDO.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/typec/altmodes/displayport.c | 50 +++++++++++++++++++++---
+ 1 file changed, 45 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/usb/typec/altmodes/displayport.c b/drivers/usb/typec/altmodes/displayport.c
+index ac84a6d64c2f..c9dfccaeeff3 100644
+--- a/drivers/usb/typec/altmodes/displayport.c
++++ b/drivers/usb/typec/altmodes/displayport.c
+@@ -116,11 +116,29 @@ static int dp_altmode_configure(struct dp_altmode *dp, u8 con)
+ 		/* Account for active cable capabilities */
+ 		if (dp->plug_prime)
+ 			pin_assign &= DP_CAP_UFP_D_PIN_ASSIGN(dp->plug_prime->vdo);
++
++		/*
++		 * The Display Port Alt mode standard is not publicly available,
++		 * so this is based on guesswork and real VDOs received from
++		 * receptacle based and plug based Type-C alt mode supporting
++		 * docks to make configuration work in practice:
++		 *
++		 * Plug (captive cable) based dock: port=c46 alt=c05
++		 * Recpetacle based dock: port=c46 alt=c0045
++		 *
++		pin_assign = DP_CAP_DFP_D_PIN_ASSIGN(dp->port->vdo);
++		pin_assign &= dp->alt->vdo & DP_CAP_RECEPTACLE ?
++			DP_CAP_UFP_D_PIN_ASSIGN(dp->alt->vdo) :
++			DP_CAP_DFP_D_PIN_ASSIGN(dp->alt->vdo);
++		 */
+ 		break;
+ 	default:
+ 		break;
+ 	}
+ 
++	dev_info(&dp->alt->dev, "con=%d pin_assign=%x (port=%x alt=%x)\n",
++		 (int)con, (unsigned)pin_assign, dp->port->vdo, dp->alt->vdo);
++
+ 	/* Determining the initial pin assignment. */
+ 	if (!DP_CONF_GET_PIN_ASSIGN(dp->data.conf)) {
+ 		/* Is USB together with DP preferred */
+@@ -726,15 +744,37 @@ int dp_altmode_probe(struct typec_altmode *alt)
+ 	struct typec_altmode *plug = typec_altmode_get_plug(alt, TYPEC_PLUG_SOP_P);
+ 	struct fwnode_handle *fwnode;
+ 	struct dp_altmode *dp;
++	u32 port_pins, alt_pins;
+ 
+ 	/* FIXME: Port can only be DFP_U. */
+ 
+-	/* Make sure we have compatible pin configurations */
+-	if (!(DP_CAP_PIN_ASSIGN_DFP_D(port->vdo) &
+-	      DP_CAP_PIN_ASSIGN_UFP_D(alt->vdo)) &&
+-	    !(DP_CAP_PIN_ASSIGN_UFP_D(port->vdo) &
+-	      DP_CAP_PIN_ASSIGN_DFP_D(alt->vdo)))
++	/*
++	 * When port is a receptacle DP_CAP_xFP_D_PIN_ASSIGN macros have the
++	 * regular meaning. When the port is a plug, the meaning is swapped.
++	 *
++	 * Check if we have any matching DFP_D<->UFP_D or UFP_D<->DFP_D pin assignment.
++	 */
++        port_pins = port->vdo & DP_CAP_RECEPTACLE ?
++		DP_CAP_DFP_D_PIN_ASSIGN(port->vdo) | DP_CAP_UFP_D_PIN_ASSIGN(port->vdo) << 8 :
++		DP_CAP_UFP_D_PIN_ASSIGN(port->vdo) | DP_CAP_DFP_D_PIN_ASSIGN(port->vdo) << 8;
++
++        alt_pins = alt->vdo & DP_CAP_RECEPTACLE ?
++		DP_CAP_UFP_D_PIN_ASSIGN(alt->vdo) | DP_CAP_DFP_D_PIN_ASSIGN(alt->vdo) << 8 :
++		DP_CAP_DFP_D_PIN_ASSIGN(alt->vdo) | DP_CAP_UFP_D_PIN_ASSIGN(alt->vdo) << 8;
++
++	/* Can't plug plug into a plug */
++	if (!(port->vdo & DP_CAP_RECEPTACLE) && !(alt->vdo & DP_CAP_RECEPTACLE)) {
++		dev_warn(&alt->dev, "Our Alt-DP VDO 0x%06x and peer port VDO 0x%06x are not compatible (both are reported as plugs!)\n",
++			 port->vdo, alt->vdo);
++		return -ENODEV;
++	}
++
++	/* Make sure we have compatiple pin configurations */
++	if (!(port_pins & alt_pins)) {
++		dev_warn(&alt->dev, "Our Alt-DP VDO 0x%06x and peer port VDO 0x%06x are not compatible (no shared pinconf %04x<->%04x (UUDD))\n",
++			 port->vdo, alt->vdo, port_pins, alt_pins);
+ 		return -ENODEV;
++	}
+ 
+ 	dp = devm_kzalloc(&alt->dev, sizeof(*dp), GFP_KERNEL);
+ 	if (!dp)
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-anx7688-Add-driver-for-ANX7688-USB-C-HDMI-bridge.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-anx7688-Add-driver-for-ANX7688-USB-C-HDMI-bridge.patch
new file mode 100644
index 000000000000..f9f8fa152ee9
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-anx7688-Add-driver-for-ANX7688-USB-C-HDMI-bridge.patch
@@ -0,0 +1,2333 @@
+From 08c64a2d7b390c78dccd932d6c8f53127bbc18e3 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Thu, 13 Feb 2020 15:37:25 +0100
+Subject: usb: typec: anx7688: Add driver for ANX7688 USB-C HDMI bridge
+
+The driver is now ready for some testing with more USB-C devices.
+It supports data and power role switching properly on all PinePhone
+variants, that have the HW mod: https://xnux.eu/devices/pp-usbc-fix.jpg.
+
+- fix possibly unbalanced connect/disconnect
+- better cabledet interrupt handling
+  - handle connect/disconnect in a workqueue
+  - debounce cabledet changes
+- send PDO to the right i2c address
+- proper error handling where it matters the most
+- proper locking
+- handle power supplies
+- handle inital connection/cable status after driver probe
+  not just on cabledet change
+- handle software interrupts from OCM
+- allow to update OCM firmware via sysfs
+- allow to dump OCM firmware via debugfs
+- allow to dump registers via debugfs
+- hook into allwinner usb phy driver to handle change in
+  data role (via usb_role_switch)
+- handle vbus/vconn enable/disable based on firmware
+  requests
+- proper cleanup of resources on driver unload
+
+Todo:
+- tell PMIC what USB input current limit to set based on
+  PD messages from firmware
+- add support for manual data/power role setting for devices
+  without the HW mod
+
+Signed-off-by: Martijn Braam <martijn@brixit.nl>
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/typec/Kconfig   |   12 +
+ drivers/usb/typec/Makefile  |    1 +
+ drivers/usb/typec/anx7688.c | 2237 +++++++++++++++++++++++++++++++++++
+ 3 files changed, 2250 insertions(+)
+ create mode 100644 drivers/usb/typec/anx7688.c
+
+diff --git a/drivers/usb/typec/Kconfig b/drivers/usb/typec/Kconfig
+index 2f80c2792dbd..982b7c444a1f 100644
+--- a/drivers/usb/typec/Kconfig
++++ b/drivers/usb/typec/Kconfig
+@@ -52,6 +52,7 @@ source "drivers/usb/typec/ucsi/Kconfig"
+ 
+ source "drivers/usb/typec/tipd/Kconfig"
+ 
++
+ config TYPEC_ANX7411
+ 	tristate "Analogix ANX7411 Type-C DRP Port controller driver"
+ 	depends on I2C
+@@ -64,6 +65,17 @@ config TYPEC_ANX7411
+ 	  If you choose to build this driver as a dynamically linked module, the
+ 	  module will be called anx7411.ko.
+ 
++config TYPEC_ANX7688
++	tristate "Analogix ANX7688 Type-C DRP Port controller and mux driver"
++	depends on I2C
++	depends on USB_ROLE_SWITCH
++	help
++	  Say Y or M here if your system has Analogix ANX7688 Type-C Bridge
++	  controller driver.
++
++	  If you choose to build this driver as a dynamically linked module, the
++	  module will be called anx7688.ko.
++
+ config TYPEC_RT1719
+ 	tristate "Richtek RT1719 Sink Only Type-C controller driver"
+ 	depends on USB_ROLE_SWITCH || !USB_ROLE_SWITCH
+diff --git a/drivers/usb/typec/Makefile b/drivers/usb/typec/Makefile
+index 7a368fea61bc..3f8ff94ad294 100644
+--- a/drivers/usb/typec/Makefile
++++ b/drivers/usb/typec/Makefile
+@@ -7,6 +7,7 @@ obj-$(CONFIG_TYPEC_TCPM)	+= tcpm/
+ obj-$(CONFIG_TYPEC_UCSI)	+= ucsi/
+ obj-$(CONFIG_TYPEC_TPS6598X)	+= tipd/
+ obj-$(CONFIG_TYPEC_ANX7411)	+= anx7411.o
++obj-$(CONFIG_TYPEC_ANX7688)	+= anx7688.o
+ obj-$(CONFIG_TYPEC_HD3SS3220)	+= hd3ss3220.o
+ obj-$(CONFIG_TYPEC_STUSB160X) 	+= stusb160x.o
+ obj-$(CONFIG_TYPEC_RT1719)	+= rt1719.o
+diff --git a/drivers/usb/typec/anx7688.c b/drivers/usb/typec/anx7688.c
+new file mode 100644
+index 000000000000..fa1d3496af73
+--- /dev/null
++++ b/drivers/usb/typec/anx7688.c
+@@ -0,0 +1,2237 @@
++/*
++ * ANX7688 USB-C HDMI bridge/PD driver
++ *
++ * Warning, this driver is somewhat PinePhone specific.
++ *
++ * How this works:
++ * - this driver allows to program firmware into ANX7688 EEPROM, and
++ *   initialize it
++ * - it then communicates with the firmware running on the OCM (on-chip
++ *   microcontroller)
++ * - it detects whether there is cable plugged in or not and powers
++ *   up or down the ANX7688 based on that
++ * - when the cable is connected the firmware on the OCM will handle
++ *   the detection of the nature of the device on the other end
++ *   of the USB-C cable
++ * - this driver then communicates with the USB phy to let it swap
++ *   data roles accordingly
++ * - it also enables VBUS and VCONN regulators as appropriate
++ * - USB phy driver (Allwinner) needs to know whether to switch to
++ *   device or host mode, or whether to turn off
++ * - when the firmware detects SRC.1.5A or SRC.3.0A via CC pins
++ *   or something else via PD, it notifies this driver via software
++ *   interrupt and this driver will determine how to update the TypeC
++ *   port status and what input current limit is appropriate
++ * - input current limit determination happens 500ms after cable
++ *   insertion or hard reset (delay is necessary to determine whether
++ *   the remote end is PD capable or not)
++ * - this driver tells to the PMIC driver that the input current limit
++ *   needs to be changed
++ * - this driver also monitors PMIC status and re-sets the input current
++ *   limit if it changes for some reason (due to PMIC internal decision
++ *   making) (this is disabled for now)
++ *
++ * ANX7688 FW behavior as observed:
++ *
++ * - DO NOT SET MORE THAN 1 SINK CAPABILITY! Firmware will ignore what
++ *   you set and send hardcoded PDO_BATT 5-21V 30W message!
++ */
++
++#define DEBUG
++
++#include <linux/debugfs.h>
++#include <linux/delay.h>
++#include <linux/extcon-provider.h>
++#include <linux/firmware.h>
++#include <linux/gpio/consumer.h>
++#include <linux/i2c.h>
++#include <linux/interrupt.h>
++#include <linux/irqreturn.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/of_irq.h>
++#include <linux/power_supply.h>
++#include <linux/regulator/consumer.h>
++#include <linux/usb/pd.h>
++#include <linux/usb/role.h>
++#include <linux/usb/typec.h>
++
++#define DISABLE_OCM 0
++
++/* firmware regs */
++
++#define ANX7688_REG_VBUS_OFF_DELAY_TIME 0x22
++#define ANX7688_REG_FEATURE_CTRL        0x27
++#define ANX7688_REG_EEPROM_LOAD_STATUS1 0x11
++#define ANX7688_REG_EEPROM_LOAD_STATUS0 0x12
++#define ANX7688_REG_FW_VERSION1         0x15
++#define ANX7688_REG_FW_VERSION0         0x16
++
++#define ANX7688_EEPROM_FW_LOADED	0x01
++
++#define ANX7688_REG_STATUS_INT_MASK     0x17
++#define ANX7688_REG_STATUS_INT          0x28
++#define ANX7688_IRQS_RECEIVED_MSG       BIT(0)
++#define ANX7688_IRQS_RECEIVED_ACK       BIT(1)
++#define ANX7688_IRQS_VCONN_CHANGE       BIT(2)
++#define ANX7688_IRQS_VBUS_CHANGE        BIT(3)
++#define ANX7688_IRQS_CC_STATUS_CHANGE   BIT(4)
++#define ANX7688_IRQS_DATA_ROLE_CHANGE   BIT(5)
++
++#define ANX7688_REG_STATUS              0x29
++#define ANX7688_VCONN_STATUS            BIT(2) /* 0 = off  1 = on */
++#define ANX7688_VBUS_STATUS             BIT(3) /* 0 = off  1 = on */
++#define ANX7688_DATA_ROLE_STATUS        BIT(5) /* 0 = device 1 = host */
++
++#define ANX7688_REG_CC_STATUS           0x2a
++#define ANX7688_REG_TRY_UFP_TIMER       0x23
++#define ANX7688_REG_TIME_CTRL           0x24
++
++#define ANX7688_REG_MAX_VOLTAGE         0x1b
++#define ANX7688_REG_MAX_POWER           0x1c
++#define ANX7688_REG_MIN_POWER           0x1d
++#define ANX7688_REG_MAX_VOLTAGE_STATUS  0x1e
++#define ANX7688_REG_MAX_POWER_STATUS    0x1f
++
++#define ANX7688_SOFT_INT_MASK           0x7f
++
++/* tcpc regs */
++
++#define ANX7688_TCPC_REG_VENDOR_ID0     0x00
++#define ANX7688_TCPC_REG_VENDOR_ID1     0x01
++#define ANX7688_TCPC_REG_ALERT0         0x10
++#define ANX7688_TCPC_REG_ALERT1         0x11
++#define ANX7688_TCPC_REG_ALERT_MASK0    0x12
++#define ANX7688_TCPC_REG_ALERT_MASK1    0x13
++#define ANX7688_TCPC_REG_INTERFACE_SEND 0x30
++#define ANX7688_TCPC_REG_INTERFACE_RECV 0x51
++
++/* hw regs */
++
++#define ANX7688_REG_IRQ_EXT_SOURCE0     0x3e
++#define ANX7688_REG_IRQ_EXT_SOURCE1     0x4e
++#define ANX7688_REG_IRQ_EXT_SOURCE2     0x4f
++#define ANX7688_REG_IRQ_EXT_MASK0       0x3b
++#define ANX7688_REG_IRQ_EXT_MASK1       0x3c
++#define ANX7688_REG_IRQ_EXT_MASK2       0x3d
++#define ANX7688_REG_IRQ_SOURCE0         0x54
++#define ANX7688_REG_IRQ_SOURCE1         0x55
++#define ANX7688_REG_IRQ_SOURCE2         0x56
++#define ANX7688_REG_IRQ_MASK0           0x57
++#define ANX7688_REG_IRQ_MASK1           0x58
++#define ANX7688_REG_IRQ_MASK2           0x59
++
++#define ANX7688_IRQ2_SOFT_INT           BIT(2)
++
++#define ANX7688_REG_USBC_RESET_CTRL		0x05
++#define ANX7688_USBC_RESET_CTRL_OCM_RESET	BIT(4)
++
++//#define ANX7688_IRQ2_USB_PLUGIN         BIT(4)
++//#define ANX7688_REG_IRQ_STATUS          0x53
++
++/* ocm messages */
++
++#define ANX7688_OCM_MSG_PWR_SRC_CAP     0x00
++#define ANX7688_OCM_MSG_PWR_SNK_CAP     0x01
++#define ANX7688_OCM_MSG_DP_SNK_IDENTITY 0x02
++#define ANX7688_OCM_MSG_SVID            0x03
++#define ANX7688_OCM_MSG_GET_DP_SNK_CAP  0x04
++#define ANX7688_OCM_MSG_ACCEPT          0x05
++#define ANX7688_OCM_MSG_REJECT          0x06
++#define ANX7688_OCM_MSG_PSWAP_REQ       0x10
++#define ANX7688_OCM_MSG_DSWAP_REQ       0x11
++#define ANX7688_OCM_MSG_GOTO_MIN_REQ    0x12
++#define ANX7688_OCM_MSG_VCONN_SWAP_REQ  0x13
++#define ANX7688_OCM_MSG_VDM             0x14
++#define ANX7688_OCM_MSG_DP_SNK_CFG      0x15
++#define ANX7688_OCM_MSG_PWR_OBJ_REQ     0x16
++#define ANX7688_OCM_MSG_PD_STATUS_REQ   0x17
++#define ANX7688_OCM_MSG_DP_ALT_ENTER    0x19
++#define ANX7688_OCM_MSG_DP_ALT_EXIT     0x1a
++#define ANX7688_OCM_MSG_GET_SNK_CAP     0x1b
++#define ANX7688_OCM_MSG_RESPONSE_TO_REQ 0xf0
++#define ANX7688_OCM_MSG_SOFT_RST        0xf1
++#define ANX7688_OCM_MSG_HARD_RST        0xf2
++#define ANX7688_OCM_MSG_RESTART         0xf3
++
++static const char * const anx7688_supply_names[] = {
++	"avdd33",
++	"avdd18",
++	"dvdd18",
++	"avdd10",
++	"dvdd10",
++	"i2c",
++	"hdmi_vt",
++
++	"vconn", // power for VCONN1/VCONN2 switches
++	"vbus", // vbus power
++};
++
++#define ANX7688_NUM_SUPPLIES ARRAY_SIZE(anx7688_supply_names)
++#define ANX7688_NUM_ALWAYS_ON_SUPPLIES (ANX7688_NUM_SUPPLIES - 1)
++
++#define ANX7688_I2C_INDEX (ANX7688_NUM_SUPPLIES - 4)
++#define ANX7688_VCONN_INDEX (ANX7688_NUM_SUPPLIES - 2)
++#define ANX7688_VBUS_INDEX (ANX7688_NUM_SUPPLIES - 1)
++
++enum {
++	ANX7688_F_POWERED,
++	ANX7688_F_CONNECTED,
++	ANX7688_F_FW_FAILED,
++	ANX7688_F_PWRSUPPLY_CHANGE,
++	ANX7688_F_CURRENT_UPDATE,
++};
++
++struct anx7688 {
++	struct device *dev;
++	struct i2c_client *client;
++	struct i2c_client *client_tcpc;
++	struct regulator_bulk_data supplies[ANX7688_NUM_SUPPLIES];
++	struct power_supply *vbus_in_supply;
++	struct notifier_block vbus_in_nb;
++	int input_current_limit; // mA
++	struct gpio_desc *gpio_enable;
++	struct gpio_desc *gpio_reset;
++	struct gpio_desc *gpio_cabledet;
++
++	uint32_t src_caps[8];
++	unsigned n_src_caps;
++
++	uint32_t snk_caps[8];
++	unsigned n_snk_caps;
++
++	unsigned long flags[1];
++
++	struct delayed_work work;
++	struct timer_list work_timer;
++
++	struct mutex lock;
++	bool vbus_on, vconn_on;
++	bool pd_capable;
++	int pd_current_limit; // mA
++	ktime_t current_update_deadline;
++
++	struct typec_port *port;
++	struct typec_partner *partner;
++	struct usb_pd_identity partner_identity;
++	struct usb_role_switch *role_sw;
++	int pwr_role, data_role;
++
++	struct dentry *debug_root;
++
++	/* for debug */
++	int last_status;
++	int last_cc_status;
++	int last_dp_state;
++	int last_bc_result;
++
++	/* for HDMI HPD */
++	struct extcon_dev *extcon;
++	int last_extcon_state;
++};
++
++static const unsigned int anx7688_extcon_cable[] = {
++	EXTCON_DISP_HDMI,
++	EXTCON_NONE,
++};
++
++static int anx7688_reg_read(struct anx7688 *anx7688, u8 reg_addr)
++{
++	int ret;
++
++	ret = i2c_smbus_read_byte_data(anx7688->client, reg_addr);
++	if (ret < 0)
++		dev_err(anx7688->dev, "i2c read failed at 0x%x (%d)\n",
++			reg_addr, ret);
++
++	return ret;
++}
++
++static int anx7688_reg_write(struct anx7688 *anx7688, u8 reg_addr, u8 value)
++{
++	int ret;
++
++	ret = i2c_smbus_write_byte_data(anx7688->client, reg_addr, value);
++	if (ret < 0)
++		dev_err(anx7688->dev, "i2c write failed at 0x%x (%d)\n",
++			reg_addr, ret);
++
++	return ret;
++}
++
++static int anx7688_reg_update_bits(struct anx7688 *anx7688, u8 reg_addr,
++				   u8 mask, u8 value)
++{
++	int ret;
++
++	ret = anx7688_reg_read(anx7688, reg_addr);
++	if (ret < 0)
++		return ret;
++
++	ret &= ~mask;
++	ret |= value;
++
++	return anx7688_reg_write(anx7688, reg_addr, ret);
++}
++
++static int anx7688_tcpc_reg_read(struct anx7688 *anx7688, u8 reg_addr)
++{
++	int ret;
++
++	ret = i2c_smbus_read_byte_data(anx7688->client_tcpc, reg_addr);
++	if (ret < 0)
++		dev_err(anx7688->dev, "tcpc i2c read failed at 0x%x (%d)\n",
++			reg_addr, ret);
++
++	return ret;
++}
++
++static int anx7688_tcpc_reg_write(struct anx7688 *anx7688, u8 reg_addr, u8 value)
++{
++	int ret;
++
++	ret = i2c_smbus_write_byte_data(anx7688->client_tcpc, reg_addr, value);
++	if (ret < 0)
++		dev_err(anx7688->dev, "tcpc i2c write failed at 0x%x (%d)\n",
++			reg_addr, ret);
++
++	return ret;
++}
++
++static void anx7688_power_enable(struct anx7688 *anx7688)
++{
++	gpiod_set_value(anx7688->gpio_reset, 1);
++	gpiod_set_value(anx7688->gpio_enable, 1);
++
++	/* wait for power to stabilize and release reset */
++	msleep(10);
++	gpiod_set_value(anx7688->gpio_reset, 0);
++	udelay(2);
++
++	dev_dbg(anx7688->dev, "power enabled\n");
++
++	set_bit(ANX7688_F_POWERED, anx7688->flags);
++}
++
++static void anx7688_power_disable(struct anx7688 *anx7688)
++{
++	gpiod_set_value(anx7688->gpio_reset, 1);
++	msleep(5);
++	gpiod_set_value(anx7688->gpio_enable, 0);
++
++	dev_dbg(anx7688->dev, "power disabled\n");
++
++	clear_bit(ANX7688_F_POWERED, anx7688->flags);
++}
++
++static int anx7688_send_ocm_message(struct anx7688 *anx7688, int cmd,
++				    const u8 *data, int data_len)
++{
++	int ret = 0, i;
++	u8 pkt[32];
++
++	if (data_len > sizeof(pkt) - 3) {
++		dev_dbg(anx7688->dev,
++			"invalid ocm message length cmd=0x%02x len=%d\n",
++			cmd, data_len);
++		return -EINVAL;
++	}
++
++	// prepare pd packet
++	pkt[0] = data_len + 1;
++	pkt[1] = cmd;
++	if (data_len > 0)
++		memcpy(pkt + 2, data, data_len);
++	pkt[2 + data_len] = 0;
++	for (i = 0; i < data_len + 2; i++)
++		pkt[data_len + 2] -= pkt[i];
++
++	dev_dbg(anx7688->dev, "send pd packet cmd=0x%02x %*ph\n",
++		cmd, data_len + 3, pkt);
++
++	ret = anx7688_tcpc_reg_read(anx7688, ANX7688_TCPC_REG_INTERFACE_SEND);
++	if (ret) {
++		dev_err(anx7688->dev,
++			"failed to send pd packet (tx buffer full)\n");
++		return -EBUSY;
++	}
++
++	ret = i2c_smbus_write_i2c_block_data(anx7688->client_tcpc,
++					     ANX7688_TCPC_REG_INTERFACE_SEND,
++					     data_len + 3, pkt);
++	if (ret < 0)
++		dev_err(anx7688->dev,
++			"failed to send pd packet (err=%d)\n", ret);
++
++	// wait until the message is processed (30ms max)
++	for (i = 0; i < 300; i++) {
++		ret = anx7688_tcpc_reg_read(anx7688, ANX7688_TCPC_REG_INTERFACE_SEND);
++		if (ret <= 0)
++			return ret;
++
++		udelay(100);
++	}
++
++	dev_err(anx7688->dev, "timeout waiting for the message queue flush\n");
++	return -ETIMEDOUT;
++}
++
++static int anx7688_connect(struct anx7688 *anx7688)
++{
++#if DISABLE_OCM
++	int ret;
++
++	dev_dbg(anx7688->dev, "cable inserted\n");
++
++	msleep(10);
++	anx7688_power_enable(anx7688);
++
++	/* reset the OCM right away */
++	ret = anx7688_reg_update_bits(anx7688, ANX7688_REG_USBC_RESET_CTRL,
++				      ANX7688_USBC_RESET_CTRL_OCM_RESET,
++				      ANX7688_USBC_RESET_CTRL_OCM_RESET);
++	if (ret)
++		goto err_poweroff;
++
++	/* enable interrupts for VBUS, etc. */
++	ret = anx7688_reg_write(anx7688, ANX7688_REG_IRQ_EXT_SOURCE2, 0xff);
++	if (ret)
++		goto err_poweroff;
++
++	ret = anx7688_reg_write(anx7688, ANX7688_REG_IRQ_EXT_MASK2, ~(BIT(6) | BIT(5) | BIT(4)));
++	if (ret)
++		goto err_poweroff;
++
++	set_bit(ANX7688_F_CONNECTED, anx7688->flags);
++	return 0;
++
++err_poweroff:
++	anx7688_power_disable(anx7688);
++	return ret;
++#else
++	struct typec_partner_desc desc = {};
++	int ret, i;
++	u8 fw[2];
++	const u8 dp_snk_identity[16] = {
++		0x00, 0x00, 0x00, 0xec,	/* id header */
++		0x00, 0x00, 0x00, 0x00,	/* cert stat */
++		0x00, 0x00, 0x00, 0x00,	/* product type */
++		0x39, 0x00, 0x00, 0x51	/* alt mode adapter */
++	};
++	const u8 svid[4] = {
++		0x00, 0x00, 0x01, 0xff,
++	};
++	u32 caps[8];
++
++	dev_dbg(anx7688->dev, "cable inserted\n");
++
++	anx7688->last_status = -1;
++	anx7688->last_cc_status = -1;
++	anx7688->last_dp_state = -1;
++
++	msleep(10);
++	anx7688_power_enable(anx7688);
++
++	ret = regulator_enable(anx7688->supplies[ANX7688_VCONN_INDEX].consumer);
++	if (ret) {
++		dev_err(anx7688->dev, "failed to enable vconn\n");
++		goto err_poweroff;
++	}
++	anx7688->vconn_on = true;
++
++	/* wait till the firmware is loaded (typically ~30ms) */
++	for (i = 0; i < 100; i++) {
++		ret = anx7688_reg_read(anx7688, ANX7688_REG_EEPROM_LOAD_STATUS0);
++
++		if (ret >= 0 && (ret & ANX7688_EEPROM_FW_LOADED) == ANX7688_EEPROM_FW_LOADED) {
++			dev_dbg(anx7688->dev, "eeprom0 = 0x%02x\n", ret);
++			dev_info(anx7688->dev, "fw loaded after %d ms\n", i * 10);
++			goto fw_loaded;
++		}
++
++		msleep(5);
++	}
++
++	set_bit(ANX7688_F_FW_FAILED, anx7688->flags);
++	dev_err(anx7688->dev, "boot firmware load failed (you may need to flash FW to anx7688 first)\n");
++	ret = -ETIMEDOUT;
++	goto err_vconoff;
++
++fw_loaded:
++	ret = i2c_smbus_read_i2c_block_data(anx7688->client,
++					    ANX7688_REG_FW_VERSION1, 2, fw);
++	if (ret < 0) {
++		dev_err(anx7688->dev, "failed to read firmware version\n");
++		goto err_vconoff;
++	}
++
++	dev_info(anx7688->dev, "OCM firmware loaded (version 0x%04x)\n",
++		 fw[1] | fw[0] << 8);
++
++	/* Unmask interrupts */
++	ret = anx7688_reg_write(anx7688, ANX7688_REG_STATUS_INT, 0);
++	if (ret)
++		goto err_vconoff;
++
++	ret = anx7688_reg_write(anx7688, ANX7688_REG_STATUS_INT_MASK, ~ANX7688_SOFT_INT_MASK);
++	if (ret)
++		goto err_vconoff;
++
++	ret = anx7688_reg_write(anx7688, ANX7688_REG_IRQ_EXT_SOURCE2, 0xff);
++	if (ret)
++		goto err_vconoff;
++
++	ret = anx7688_reg_write(anx7688, ANX7688_REG_IRQ_EXT_MASK2, (u8)~ANX7688_IRQ2_SOFT_INT);
++	if (ret)
++		goto err_vconoff;
++
++	/* time to turn off vbus after cc disconnect (unit is 4 ms) */
++	ret = anx7688_reg_write(anx7688, ANX7688_REG_VBUS_OFF_DELAY_TIME, 100 / 4);
++	if (ret)
++		goto err_vconoff;
++
++	//anx7688_reg_write(anx7688, ANX7688_REG_TIME_CTRL, 0x00);
++
++	/* 300ms (unit is 2 ms) */
++	ret = anx7688_reg_write(anx7688, ANX7688_REG_TRY_UFP_TIMER, 300 / 2);
++	if (ret)
++		goto err_vconoff;
++
++	/* maximum voltage in 100 mV units */
++	ret = anx7688_reg_write(anx7688, ANX7688_REG_MAX_VOLTAGE, 50); /* 5 V */
++	if (ret)
++		goto err_vconoff;
++
++	/* min/max power in 500 mW units */
++	ret = anx7688_reg_write(anx7688, ANX7688_REG_MAX_POWER, 15 * 2); /* 15 W */
++	if (ret)
++		goto err_vconoff;
++
++	ret = anx7688_reg_write(anx7688, ANX7688_REG_MIN_POWER, 1);  /* 0.5 W */
++	if (ret)
++		goto err_vconoff;
++
++	/* auto_pd, try.src, try.sink, goto safe 5V */
++	ret = anx7688_reg_write(anx7688, ANX7688_REG_FEATURE_CTRL, 0x1e & ~BIT(2)); // disable try_src
++	if (ret)
++		goto err_vconoff;
++
++	for (i = 0; i < anx7688->n_src_caps; i++)
++		caps[i] = cpu_to_le32(anx7688->src_caps[i]);
++	ret = anx7688_send_ocm_message(anx7688, ANX7688_OCM_MSG_PWR_SRC_CAP,
++				       (u8*)&caps, 4 * anx7688->n_src_caps);
++	if (ret)
++		goto err_vconoff;
++
++	for (i = 0; i < anx7688->n_snk_caps; i++)
++		caps[i] = cpu_to_le32(anx7688->snk_caps[i]);
++	ret = anx7688_send_ocm_message(anx7688, ANX7688_OCM_MSG_PWR_SNK_CAP,
++				       (u8*)&caps, 4 * anx7688->n_snk_caps);
++	if (ret)
++		goto err_vconoff;
++
++	/* Send DP SNK identity */
++	ret = anx7688_send_ocm_message(anx7688, ANX7688_OCM_MSG_DP_SNK_IDENTITY,
++				       dp_snk_identity, sizeof dp_snk_identity);
++	if (ret)
++		goto err_vconoff;
++
++	ret = anx7688_send_ocm_message(anx7688, ANX7688_OCM_MSG_SVID,
++				       svid, sizeof svid);
++	if (ret)
++		goto err_vconoff;
++
++	dev_dbg(anx7688->dev, "OCM configuration completed\n");
++
++	desc.accessory = TYPEC_ACCESSORY_NONE;
++
++	typec_unregister_partner(anx7688->partner);
++
++	anx7688->partner = typec_register_partner(anx7688->port, &desc);
++	if (IS_ERR(anx7688->partner)) {
++		ret = PTR_ERR(anx7688->partner);
++		goto err_vconoff;
++	}
++
++	// after this deadline passes we'll check if device is pd_capable and
++	// set up the current limit accordingly
++	anx7688->current_update_deadline = ktime_add_ms(ktime_get(), 3000);
++
++	set_bit(ANX7688_F_CONNECTED, anx7688->flags);
++	return 0;
++
++err_vconoff:
++	regulator_disable(anx7688->supplies[ANX7688_VCONN_INDEX].consumer);
++	anx7688->vconn_on = false;
++err_poweroff:
++	anx7688_power_disable(anx7688);
++	dev_err(anx7688->dev, "OCM configuration failed\n");
++	return ret;
++#endif
++}
++
++static void anx7688_set_hdmi_hpd(struct anx7688 *anx7688, int state)
++{
++	if (!anx7688->extcon)
++		return;
++
++	if (anx7688->last_extcon_state != state) {
++		extcon_set_state_sync(anx7688->extcon, EXTCON_DISP_HDMI, state);
++		anx7688->last_extcon_state = state;
++	}
++}
++
++static void anx7688_disconnect(struct anx7688 *anx7688)
++{
++	union power_supply_propval val = {0,};
++	struct device *dev = anx7688->dev;
++	int ret;
++
++	dev_dbg(dev, "cable removed\n");
++
++	anx7688->current_update_deadline = 0;
++
++	anx7688_set_hdmi_hpd(anx7688, 0);
++
++	if (anx7688->vconn_on) {
++		regulator_disable(anx7688->supplies[ANX7688_VCONN_INDEX].consumer);
++		anx7688->vconn_on = false;
++	}
++
++	if (anx7688->vbus_on) {
++		regulator_disable(anx7688->supplies[ANX7688_VBUS_INDEX].consumer);
++		anx7688->vbus_on = false;
++	}
++
++	anx7688_power_disable(anx7688);
++
++	anx7688->pd_capable = false;
++
++	typec_unregister_partner(anx7688->partner);
++	anx7688->partner = NULL;
++
++	anx7688->pwr_role = TYPEC_SINK;
++	anx7688->data_role = TYPEC_DEVICE;
++	typec_set_pwr_role(anx7688->port, anx7688->pwr_role);
++	typec_set_data_role(anx7688->port, anx7688->data_role);
++	typec_set_pwr_opmode(anx7688->port, TYPEC_PWR_MODE_USB);
++	typec_set_vconn_role(anx7688->port, TYPEC_SINK);
++
++	usb_role_switch_set_role(anx7688->role_sw, USB_ROLE_NONE);
++
++	val.intval = 500 * 1000;
++	dev_dbg(dev, "setting vbus_in current limit to %d mA\n", val.intval);
++	ret = power_supply_set_property(anx7688->vbus_in_supply,
++					POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT,
++					&val);
++	if (ret)
++		dev_err(dev, "failed to set vbus_in current to %d mA\n",
++			val.intval / 1000);
++
++	val.intval = 0;
++	dev_dbg(dev, "disabling vbus_in power path\n");
++	ret = power_supply_set_property(anx7688->vbus_in_supply,
++					POWER_SUPPLY_PROP_ONLINE,
++					&val);
++	if (ret)
++		dev_err(dev, "failed to offline vbus_in\n");
++
++	val.intval = 1;
++	dev_dbg(dev, "enabling USB BC 1.2 detection\n");
++	ret = power_supply_set_property(anx7688->vbus_in_supply,
++					POWER_SUPPLY_PROP_USB_BC_ENABLED,
++					&val);
++	if (ret)
++		dev_err(dev, "failed to enabled USB BC1.2 detection\n");
++
++	clear_bit(ANX7688_F_CONNECTED, anx7688->flags);
++}
++
++static void anx7688_handle_cable_change(struct anx7688* anx7688)
++{
++	int cabledet;
++	bool connected;
++
++	connected = test_bit(ANX7688_F_CONNECTED, anx7688->flags);
++	cabledet = gpiod_get_value(anx7688->gpio_cabledet);
++
++	if (cabledet && !connected)
++		anx7688_connect(anx7688);
++	else if (!cabledet && connected)
++		anx7688_disconnect(anx7688);
++}
++
++static irqreturn_t anx7688_irq_plug_handler(int irq, void *data)
++{
++	struct anx7688 *anx7688 = data;
++
++	dev_dbg(anx7688->dev, "plug irq (cd=%d)\n",
++		gpiod_get_value(anx7688->gpio_cabledet));
++
++	/*
++	 * After each cabledet change the scheduled work timer is reset
++	 * to fire in ~10ms. So the work is done only after the cabledet
++	 * is stable for ~10ms.
++	 */
++	schedule_delayed_work(&anx7688->work, msecs_to_jiffies(10));
++
++	return IRQ_HANDLED;
++}
++
++enum {
++	CMD_SUCCESS,
++	CMD_REJECT,
++	CMD_FAIL,
++	CMD_BUSY,
++};
++
++static const char* anx7688_cmd_statuses[] = {
++	"SUCCESS",
++	"REJECT",
++	"FAIL",
++	"BUSY",
++};
++
++static int anx7688_handle_pd_message_response(struct anx7688* anx7688,
++					      u8 to_cmd, u8 resp)
++{
++	const char* status = resp <= CMD_BUSY ? anx7688_cmd_statuses[resp] : "UNKNOWN";
++
++	switch (to_cmd) {
++	case ANX7688_OCM_MSG_PSWAP_REQ:
++		dev_info(anx7688->dev, "received response to PSWAP_REQ (%s)\n", status);
++		break;
++
++	case ANX7688_OCM_MSG_DSWAP_REQ:
++		dev_info(anx7688->dev, "received response to DSWAP_REQ (%s)\n", status);
++		break;
++
++	case ANX7688_OCM_MSG_VCONN_SWAP_REQ:
++		dev_info(anx7688->dev, "received response to VCONN_SWAP_REQ (%s)\n", status);
++		break;
++
++	case ANX7688_OCM_MSG_PWR_OBJ_REQ:
++		dev_info(anx7688->dev, "received response to PWR_OBJ_REQ (%s)\n", status);
++		break;
++
++	case ANX7688_OCM_MSG_VDM:
++		dev_info(anx7688->dev, "received response to VDM (%s)\n", status);
++		break;
++
++	case ANX7688_OCM_MSG_GOTO_MIN_REQ:
++		dev_info(anx7688->dev, "received response to GOTO_MIN_REQ (%s)\n", status);
++		break;
++
++	case ANX7688_OCM_MSG_GET_SNK_CAP:
++		dev_info(anx7688->dev, "received response to GET_SNK_CAP (%s)\n", status);
++		break;
++
++	default:
++		dev_info(anx7688->dev, "received response to unknown request (%s)\n", status);
++		break;
++	}
++
++	return 0;
++}
++
++static int anx7688_handle_pd_message(struct anx7688* anx7688,
++				     u8 cmd, u8* msg, unsigned len)
++{
++	struct device *dev = anx7688->dev;
++	union power_supply_propval psy_val = {0,};
++	uint32_t* pdos = (uint32_t*)msg;
++	int ret, i, rdo_max_v, rdo_max_p;
++	uint32_t pdo, rdo;
++
++	switch (cmd) {
++	case ANX7688_OCM_MSG_PWR_SRC_CAP:
++		dev_info(anx7688->dev, "received SRC_CAP\n");
++
++		if (len % 4 != 0) {
++			dev_warn(anx7688->dev, "received invalid sized PDO array\n");
++			break;
++		}
++
++		/* the partner is PD capable */
++		anx7688->pd_capable = true;
++
++		for (i = 0; i < len / 4; i++) {
++			pdo = le32_to_cpu(pdos[i]);
++
++			if (pdo_type(pdo) == PDO_TYPE_FIXED) {
++				unsigned voltage = pdo_fixed_voltage(pdo);
++				unsigned max_curr = pdo_max_current(pdo);
++
++				dev_info(anx7688->dev, "SRC_CAP PDO_FIXED (%umV %umA)\n", voltage, max_curr);
++			} else if (pdo_type(pdo) == PDO_TYPE_BATT) {
++				unsigned min_volt = pdo_min_voltage(pdo);
++				unsigned max_volt = pdo_max_voltage(pdo);
++				unsigned max_pow = pdo_max_power(pdo);
++
++				dev_info(anx7688->dev, "SRC_CAP PDO_BATT (%umV-%umV %umW)\n", min_volt, max_volt, max_pow);
++			} else if (pdo_type(pdo) == PDO_TYPE_VAR) {
++				unsigned min_volt = pdo_min_voltage(pdo);
++				unsigned max_volt = pdo_max_voltage(pdo);
++				unsigned max_curr = pdo_max_current(pdo);
++
++				dev_info(anx7688->dev, "SRC_CAP PDO_VAR (%umV-%umV %umA)\n", min_volt, max_volt, max_curr);
++			} else {
++				dev_info(anx7688->dev, "SRC_CAP PDO_APDO (0x%08X)\n", pdo);
++			}
++		}
++
++		/* when auto_pd mode is enabled, the FW has already set
++		 * RDO_MAX_VOLTAGE and RDO_MAX_POWER for the RDO it sent to the
++		 * partner based on the received SOURCE_CAPs. This does not
++		 * mean, the request was acked, but we can't do better here than
++		 * calculate the current_limit to set later and hope for the best.
++		 */
++		rdo_max_v = anx7688_reg_read(anx7688, ANX7688_REG_MAX_VOLTAGE_STATUS);
++		if (rdo_max_v < 0)
++			return rdo_max_v;
++		if (rdo_max_v == 0)
++			return -EINVAL;
++
++		rdo_max_p = anx7688_reg_read(anx7688, ANX7688_REG_MAX_POWER_STATUS);
++		if (rdo_max_p < 0)
++			return rdo_max_p;
++
++		anx7688->pd_current_limit = rdo_max_p * 5000 / rdo_max_v;
++
++		dev_dbg(anx7688->dev, "RDO max voltage = %dmV, max power = %dmW, PD current limit = %dmA\n",
++			rdo_max_v * 100, rdo_max_p * 500, anx7688->pd_current_limit);
++
++		// update current limit sooner, now that we have PD negotiation result
++		anx7688->current_update_deadline = ktime_add_ms(ktime_get(), 500);
++
++		//TODO: we should go through PDOs and decide which one
++		//to request, build a RDO with a proper index of the
++		//selected PDO and send it via PWR_OBJ_REQ message to FW
++		//but we're using auto_pd, so FW does this for us
++		//
++		//rdo = cpu_to_le32(RDO_FIXED(0, 1500, 1500, RDO_USB_COMM));
++		//ret = anx7688_send_ocm_message(anx7688, ANX7688_OCM_MSG_PWR_OBJ_REQ, &rdo, 4);
++
++		break;
++
++	case ANX7688_OCM_MSG_PWR_SNK_CAP:
++		dev_info(anx7688->dev, "received SNK_CAP\n");
++
++		if (len % 4 != 0) {
++			dev_warn(anx7688->dev, "received invalid sized PDO array\n");
++			break;
++		}
++
++		for (i = 0; i < len / 4; i++) {
++			pdo = le32_to_cpu(pdos[i]);
++
++			if (pdo_type(pdo) == PDO_TYPE_FIXED) {
++				unsigned voltage = pdo_fixed_voltage(pdo);
++				unsigned max_curr = pdo_max_current(pdo);
++
++				dev_info(anx7688->dev, "SNK_CAP PDO_FIXED (%umV %umA)\n", voltage, max_curr);
++			} else if (pdo_type(pdo) == PDO_TYPE_BATT) {
++				unsigned min_volt = pdo_min_voltage(pdo);
++				unsigned max_volt = pdo_max_voltage(pdo);
++				unsigned max_pow = pdo_max_power(pdo);
++
++				dev_info(anx7688->dev, "SNK_CAP PDO_BATT (%umV-%umV %umW)\n", min_volt, max_volt, max_pow);
++			} else if (pdo_type(pdo) == PDO_TYPE_VAR) {
++				unsigned min_volt = pdo_min_voltage(pdo);
++				unsigned max_volt = pdo_max_voltage(pdo);
++				unsigned max_curr = pdo_max_current(pdo);
++
++				dev_info(anx7688->dev, "SNK_CAP PDO_VAR (%umV-%umV %umA)\n", min_volt, max_volt, max_curr);
++			} else {
++				dev_info(anx7688->dev, "SNK_CAP PDO_APDO (0x%08X)\n", pdo);
++			}
++		}
++
++		break;
++
++	case ANX7688_OCM_MSG_PWR_OBJ_REQ:
++		dev_info(anx7688->dev, "received PWR_OBJ_REQ\n");
++
++		anx7688->pd_capable = true;
++
++		if (len != 4) {
++			dev_warn(anx7688->dev, "received invalid sized RDO\n");
++			break;
++		}
++
++		rdo = le32_to_cpu(pdos[0]);
++
++		if (rdo_index(rdo) >= 1 && rdo_index(rdo) <= anx7688->n_src_caps) {
++			unsigned rdo_op_curr = rdo_op_current(rdo);
++			unsigned rdo_max_curr = rdo_max_current(rdo);
++			unsigned rdo_idx = rdo_index(rdo) - 1;
++			unsigned pdo_volt, pdo_max_curr;
++
++			pdo = anx7688->src_caps[rdo_idx];
++			pdo_volt = pdo_fixed_voltage(pdo);
++			pdo_max_curr = pdo_max_current(pdo);
++
++			dev_info(anx7688->dev, "RDO (idx=%d op=%umA max=%umA)\n",
++				 rdo_idx, rdo_op_curr, rdo_max_curr);
++
++			dev_info(anx7688->dev, "PDO_FIXED (%umV %umA)\n",
++				 pdo_volt, pdo_max_curr);
++
++			//TODO: we should check the req and respond with accept/reject
++			// but we're using auto_pd feature, so the FW will do
++			// this for us
++			if (rdo_op_curr > pdo_max_curr || rdo_max_curr > pdo_max_curr) {
++				//ret = anx7688_send_ocm_message(anx7688, ANX7688_OCM_MSG_REJECT, 0, 0);
++			} else {
++				//ret = anx7688_send_ocm_message(anx7688, ANX7688_OCM_MSG_ACCEPT, 0, 0);
++			}
++		} else {
++			dev_info(anx7688->dev, "PWR_OBJ RDO index out of range (RDO = 0x%08X)\n", rdo);
++		}
++
++		break;
++
++	case ANX7688_OCM_MSG_ACCEPT:
++		dev_info(anx7688->dev, "received ACCEPT\n");
++		break;
++
++	case ANX7688_OCM_MSG_REJECT:
++		dev_info(anx7688->dev, "received REJECT\n");
++		break;
++
++	case ANX7688_OCM_MSG_RESPONSE_TO_REQ:
++		if (len < 2) {
++			dev_warn(anx7688->dev, "received short RESPONSE_TO_REQ\n");
++			break;
++		}
++
++		anx7688_handle_pd_message_response(anx7688, msg[0], msg[1]);
++		break;
++
++	case ANX7688_OCM_MSG_SOFT_RST:
++		dev_info(anx7688->dev, "received SOFT_RST\n");
++		break;
++
++	case ANX7688_OCM_MSG_HARD_RST:
++		if (anx7688->pd_capable) {
++			dev_info(anx7688->dev, "received HARD_RST\n");
++
++			// stop drawing power from VBUS
++			psy_val.intval = 0;
++			dev_dbg(dev, "disabling vbus_in power path\n");
++			ret = power_supply_set_property(anx7688->vbus_in_supply,
++							POWER_SUPPLY_PROP_ONLINE,
++							&psy_val);
++			if (ret)
++				dev_err(anx7688->dev, "failed to offline vbus_in\n");
++
++			// wait till the dust settles
++			anx7688->current_update_deadline = ktime_add_ms(ktime_get(), 3000);
++		} else {
++			dev_dbg(anx7688->dev, "received HARD_RST, idiot firmware is bored\n");
++		}
++
++		break;
++
++	case ANX7688_OCM_MSG_RESTART:
++		dev_info(anx7688->dev, "received RESTART\n");
++		break;
++
++	case ANX7688_OCM_MSG_PSWAP_REQ:
++		dev_info(anx7688->dev, "received PSWAP_REQ\n");
++		break;
++
++	case ANX7688_OCM_MSG_DSWAP_REQ:
++		dev_info(anx7688->dev, "received DSWAP_REQ\n");
++		break;
++
++	case ANX7688_OCM_MSG_VCONN_SWAP_REQ:
++		dev_info(anx7688->dev, "received VCONN_SWAP_REQ\n");
++		break;
++
++	case ANX7688_OCM_MSG_DP_ALT_ENTER:
++		dev_info(anx7688->dev, "received DP_ALT_ENTER\n");
++		break;
++
++	case ANX7688_OCM_MSG_DP_ALT_EXIT:
++		dev_info(anx7688->dev, "received DP_ALT_EXIT\n");
++		break;
++
++	case ANX7688_OCM_MSG_DP_SNK_IDENTITY:
++		dev_info(anx7688->dev, "received DP_SNK_IDENTITY\n");
++		break;
++
++	case ANX7688_OCM_MSG_SVID:
++		dev_info(anx7688->dev, "received SVID\n");
++		break;
++
++	case ANX7688_OCM_MSG_VDM:
++		dev_info(anx7688->dev, "received VDM\n");
++		break;
++
++	case ANX7688_OCM_MSG_GOTO_MIN_REQ:
++		dev_info(anx7688->dev, "received GOTO_MIN_REQ\n");
++		break;
++
++	case ANX7688_OCM_MSG_PD_STATUS_REQ:
++		dev_info(anx7688->dev, "received PD_STATUS_REQ\n");
++		break;
++
++	case ANX7688_OCM_MSG_GET_DP_SNK_CAP:
++		dev_info(anx7688->dev, "received GET_DP_SNK_CAP\n");
++		break;
++
++	case ANX7688_OCM_MSG_DP_SNK_CFG:
++		dev_info(anx7688->dev, "received DP_SNK_CFG\n");
++		break;
++
++	default:
++		dev_info(anx7688->dev, "received unknown message 0x%02x\n", cmd);
++		break;
++	}
++
++	return 0;
++}
++
++static int anx7688_receive_msg(struct anx7688* anx7688)
++{
++	u8 pkt[32], checksum = 0;
++	int i, ret;
++
++	ret = i2c_smbus_read_i2c_block_data(anx7688->client_tcpc,
++					    ANX7688_TCPC_REG_INTERFACE_RECV,
++					    32, pkt);
++	if (ret < 0) {
++		dev_err(anx7688->dev, "failed to read pd msg\n");
++		return ret;
++	}
++
++	ret = anx7688_tcpc_reg_write(anx7688, ANX7688_TCPC_REG_INTERFACE_RECV, 0);
++	if (ret) {
++		dev_warn(anx7688->dev, "failed to clear recv fifo\n");
++	}
++
++	if (pkt[0] == 0 || pkt[0] > sizeof(pkt) - 2) {
++		dev_err(anx7688->dev, "received invalid pd message: %*ph\n",
++			(int)sizeof(pkt), pkt);
++		return -EINVAL;
++	}
++
++	dev_dbg(anx7688->dev, "recv ocm message cmd=0x%02x %*ph\n",
++		pkt[1], pkt[0] + 2, pkt);
++
++	for (i = 0; i < pkt[0] + 2; i++)
++		checksum += pkt[i];
++
++	if (checksum != 0) {
++		dev_err(anx7688->dev, "bad checksum on received message\n");
++		return -EINVAL;
++	}
++
++	anx7688_handle_pd_message(anx7688, pkt[1], pkt + 2, pkt[0] - 1);
++	return 0;
++}
++
++static const char* anx7688_cc_status_string(unsigned v)
++{
++	switch (v) {
++	case 0: return "SRC.Open";
++	case 1: return "SRC.Rd";
++	case 2: return "SRC.Ra";
++	case 4: return "SNK.Default";
++	case 8: return "SNK.Power1.5";
++	case 12: return "SNK.Power3.0";
++	default: return "UNK";
++	}
++}
++
++static int anx7688_update_status(struct anx7688 *anx7688)
++{
++	struct device *dev = anx7688->dev;
++	bool vbus_on, vconn_on, dr_dfp;
++	int status, cc_status, dp_state, dp_substate, ret;
++
++	status = anx7688_reg_read(anx7688, ANX7688_REG_STATUS);
++	if (status < 0)
++		return status;
++
++	cc_status = anx7688_reg_read(anx7688, ANX7688_REG_CC_STATUS);
++	if (cc_status < 0)
++		return cc_status;
++
++	dp_state = anx7688_tcpc_reg_read(anx7688, 0x87);
++	if (dp_state < 0)
++		return dp_state;
++
++	dp_substate = anx7688_tcpc_reg_read(anx7688, 0x88);
++	if (dp_substate < 0)
++		return dp_substate;
++
++	anx7688_set_hdmi_hpd(anx7688, dp_state >= 3);
++
++	dp_state = (dp_state << 8) | dp_substate;
++
++	if (anx7688->last_status == -1 || anx7688->last_status != status) {
++		anx7688->last_status = status;
++		dev_dbg(dev, "status changed to 0x%02x\n", status);
++	}
++
++	if (anx7688->last_cc_status == -1 || anx7688->last_cc_status != cc_status) {
++		anx7688->last_cc_status = cc_status;
++		dev_dbg(dev, "cc_status changed to CC1 = %s CC2 = %s\n",
++			anx7688_cc_status_string(cc_status & 0xf),
++			anx7688_cc_status_string((cc_status >> 4) & 0xf));
++	}
++
++	if (anx7688->last_dp_state == -1 || anx7688->last_dp_state != dp_state) {
++		anx7688->last_dp_state = dp_state;
++		dev_dbg(dev, "DP state changed to 0x%04x\n", dp_state);
++	}
++
++	vbus_on = !!(status & ANX7688_VBUS_STATUS);
++	vconn_on = !!(status & ANX7688_VCONN_STATUS);
++	dr_dfp = !!(status & ANX7688_DATA_ROLE_STATUS);
++
++	if (anx7688->vbus_on != vbus_on) {
++		dev_dbg(anx7688->dev, "POWER role change to %s\n",
++			vbus_on ? "SOURCE" : "SINK");
++
++		if (vbus_on) {
++			ret = regulator_enable(anx7688->supplies[ANX7688_VBUS_INDEX].consumer);
++			if (ret) {
++				dev_err(anx7688->dev, "failed to enable vbus\n");
++				return ret;
++			}
++		} else {
++			ret = regulator_disable(anx7688->supplies[ANX7688_VBUS_INDEX].consumer);
++			if (ret) {
++				dev_err(anx7688->dev, "failed to disable vbus\n");
++				return ret;
++			}
++		}
++
++		anx7688->pwr_role = vbus_on ? TYPEC_SOURCE : TYPEC_SINK;
++		typec_set_pwr_role(anx7688->port, anx7688->pwr_role);
++		anx7688->vbus_on = vbus_on;
++	}
++
++	if (anx7688->vconn_on != vconn_on) {
++		dev_dbg(anx7688->dev, "VCONN role change to %s\n",
++			vconn_on ? "SOURCE" : "SINK");
++
++		if (vconn_on) {
++			ret = regulator_enable(anx7688->supplies[ANX7688_VCONN_INDEX].consumer);
++			if (ret) {
++				dev_err(anx7688->dev, "failed to enable vconn\n");
++				return ret;
++			}
++		} else {
++			ret = regulator_disable(anx7688->supplies[ANX7688_VCONN_INDEX].consumer);
++			if (ret) {
++				dev_err(anx7688->dev, "failed to disable vconn\n");
++				return ret;
++			}
++		}
++
++		typec_set_vconn_role(anx7688->port, vconn_on ? TYPEC_SOURCE : TYPEC_SINK);
++		anx7688->vconn_on = vconn_on;
++	}
++
++	anx7688->data_role = dr_dfp ? TYPEC_HOST : TYPEC_DEVICE;
++	typec_set_data_role(anx7688->port, anx7688->data_role);
++
++	if (usb_role_switch_get_role(anx7688->role_sw) !=
++	    (dr_dfp ? USB_ROLE_HOST : USB_ROLE_DEVICE)) {
++		dev_dbg(anx7688->dev, "DATA role change requested to %s\n",
++			dr_dfp ? "DFP" : "UFP");
++
++		ret = usb_role_switch_set_role(anx7688->role_sw,
++					       dr_dfp ? USB_ROLE_HOST : USB_ROLE_DEVICE);
++		if (ret)
++			return ret;
++	}
++
++	return 0;
++}
++
++static irqreturn_t anx7688_irq_status_handler(int irq, void *data)
++{
++#if DISABLE_OCM
++	struct anx7688 *anx7688 = data;
++	struct device *dev = anx7688->dev;
++	int ext2_status;
++
++	mutex_lock(&anx7688->lock);
++
++	if (!test_bit(ANX7688_F_CONNECTED, anx7688->flags)) {
++		/*
++		 * The chip should be disabled and powered off, nothing
++		 * more to do.
++		 */
++		dev_dbg(dev, "spurious status irq\n");
++		goto out_unlock;
++	}
++
++	//dev_dbg(dev, "status irq\n");
++
++	ext2_status = anx7688_reg_read(anx7688, ANX7688_REG_IRQ_EXT_SOURCE2);
++	dev_dbg(dev, "  ext2 = 0x%02x\n", ext2_status);
++	anx7688_reg_write(anx7688, ANX7688_REG_IRQ_EXT_SOURCE2, ext2_status);
++
++out_unlock:
++	mutex_unlock(&anx7688->lock);
++
++	return IRQ_HANDLED;
++#else
++	struct anx7688 *anx7688 = data;
++	struct device *dev = anx7688->dev;
++	int tcpc_status, ext2_status, soft_status;
++
++	mutex_lock(&anx7688->lock);
++
++	if (!test_bit(ANX7688_F_CONNECTED, anx7688->flags)) {
++		dev_dbg(dev, "spurious status irq\n");
++		/* anx chip should be disabled and power off, nothing
++		 * more to do */
++		goto out_unlock;
++	}
++
++	//dev_dbg(dev, "status irq\n");
++
++	// clear tcpc interrupt
++	tcpc_status = anx7688_tcpc_reg_read(anx7688, ANX7688_TCPC_REG_ALERT0);
++	if (tcpc_status > 0) {
++		//dev_dbg(dev, "  tcpc = 0x%02x\n", tcpc_status);
++		anx7688_tcpc_reg_write(anx7688, ANX7688_TCPC_REG_ALERT0, tcpc_status);
++	}
++
++	ext2_status = anx7688_reg_read(anx7688, ANX7688_REG_IRQ_EXT_SOURCE2);
++	if (ext2_status & ANX7688_IRQ2_SOFT_INT) {
++		soft_status = anx7688_reg_read(anx7688, ANX7688_REG_STATUS_INT);
++		anx7688_reg_write(anx7688, ANX7688_REG_STATUS_INT, 0);
++
++		//dev_dbg(dev, "  soft = 0x%02x\n", soft_status);
++
++		if (soft_status > 0) {
++			soft_status &= ANX7688_SOFT_INT_MASK;
++
++			if (soft_status & ANX7688_IRQS_RECEIVED_MSG)
++				anx7688_receive_msg(anx7688);
++
++			if (soft_status & (ANX7688_IRQS_CC_STATUS_CHANGE |
++					   ANX7688_IRQS_VBUS_CHANGE |
++					   ANX7688_IRQS_VCONN_CHANGE |
++					   ANX7688_IRQS_DATA_ROLE_CHANGE)) {
++				anx7688_update_status(anx7688);
++			}
++		}
++
++		anx7688_reg_write(anx7688, ANX7688_REG_IRQ_EXT_SOURCE2, ANX7688_IRQ2_SOFT_INT);
++	}
++
++out_unlock:
++	mutex_unlock(&anx7688->lock);
++
++	return IRQ_HANDLED;
++#endif
++}
++
++static int anx7688_dr_set(struct typec_port *port, enum typec_data_role role)
++{
++	struct anx7688 *anx7688 = typec_get_drvdata(port);
++	int ret = 0;
++
++	dev_info(anx7688->dev, "data role set %d\n", role);
++
++	if (anx7688->data_role != role) {
++		mutex_lock(&anx7688->lock);
++		ret = anx7688_send_ocm_message(anx7688, ANX7688_OCM_MSG_DSWAP_REQ, 0, 0);
++		mutex_unlock(&anx7688->lock);
++	}
++
++	return ret;
++}
++
++static int anx7688_pr_set(struct typec_port *port, enum typec_role role)
++{
++	struct anx7688 *anx7688 = typec_get_drvdata(port);
++	int ret = 0;
++
++	dev_info(anx7688->dev, "power role set %d\n", role);
++
++	if (anx7688->pwr_role != role) {
++		mutex_lock(&anx7688->lock);
++		ret = anx7688_send_ocm_message(anx7688, ANX7688_OCM_MSG_PSWAP_REQ, 0, 0);
++		mutex_unlock(&anx7688->lock);
++	}
++
++	return ret;
++}
++
++/*
++ * Calls to the eerpom functions need to be taken under the anx7688 lock.
++ */
++
++static int anx7688_eeprom_set_address(struct anx7688 *anx7688, u16 addr)
++{
++	int ret;
++
++	ret = anx7688_reg_write(anx7688, 0xe0, (addr >> 8) & 0xff);
++	if (ret < 0)
++		return ret;
++
++	return anx7688_reg_write(anx7688, 0xe1, addr & 0xff);
++}
++
++static int anx7688_eeprom_wait_done(struct anx7688 *anx7688)
++{
++	ktime_t timeout;
++	int ret;
++
++	// wait for read to be done
++	timeout = ktime_add_us(ktime_get(), 50000);
++	while (true) {
++		ret = anx7688_reg_read(anx7688, 0xe2);
++		if (ret < 0)
++			return ret;
++
++		if (ret & BIT(3))
++			return 0;
++
++		if (ktime_after(ktime_get(), timeout)) {
++			dev_err(anx7688->dev, "timeout waiting for eeprom\n");
++			return -ETIMEDOUT;
++		}
++	}
++}
++
++/* wait for internal FSM of EEPROM to be in a state ready for
++ * programming/reading
++ */
++static int anx7688_eeprom_wait_ready(struct anx7688 *anx7688)
++{
++	ktime_t timeout;
++	int ret;
++
++	// wait until eeprom is ready
++	timeout = ktime_add_us(ktime_get(), 1000000);
++	while (true) {
++		ret = anx7688_reg_read(anx7688, 0x7f);
++		if (ret < 0)
++			return ret;
++
++		if ((ret & 0x0f) == 7)
++			return 0;
++
++		if (ktime_after(ktime_get(), timeout)) {
++			dev_err(anx7688->dev, "timeout waiting for eeprom to initialize\n");
++			return -ETIMEDOUT;
++		}
++
++		msleep(5);
++	}
++}
++
++static int anx7688_eeprom_read(struct anx7688 *anx7688, unsigned addr, u8 buf[16])
++{
++	int ret;
++
++	ret = anx7688_eeprom_set_address(anx7688, addr);
++	if (ret)
++		return ret;
++
++	// initiate read
++	ret = anx7688_reg_write(anx7688, 0xe2, 0x06);
++	if (ret < 0)
++		return ret;
++
++	ret = anx7688_eeprom_wait_done(anx7688);
++	if (ret)
++		return ret;
++
++	ret = i2c_smbus_read_i2c_block_data(anx7688->client, 0xd0, 16, buf);
++	if (ret < 0) {
++		dev_err(anx7688->dev,
++			"failed to read eeprom data (err=%d)\n", ret);
++		return ret;
++	}
++
++	return 0;
++}
++
++static int anx7688_eeprom_write(struct anx7688 *anx7688, unsigned addr,
++				const u8 buf[16])
++{
++	int ret;
++
++	ret = anx7688_eeprom_set_address(anx7688, addr);
++	if (ret)
++		return ret;
++
++	ret = i2c_smbus_write_i2c_block_data(anx7688->client, 0xd0, 16, buf);
++	if (ret < 0) {
++		dev_err(anx7688->dev,
++			"failed to write eeprom data (err=%d)\n", ret);
++		return ret;
++	}
++
++	dev_info(anx7688->dev, "eeprom wr %x %*ph\n", addr, 16, buf);
++
++	// initiate write
++	ret = anx7688_reg_write(anx7688, 0xe2, 0x01);
++	if (ret < 0)
++		return ret;
++
++	ret = anx7688_eeprom_wait_done(anx7688);
++	if (ret)
++		return ret;
++
++	udelay(1500);
++	udelay(1000);
++
++	return 0;
++}
++
++/*
++ * The firmware is flashed as is from address 0x10 up to 0xffff.
++ */
++static int anx7688_flash_firmware(struct anx7688 *anx7688)
++{
++	const char* fw_name = "anx7688-fw.bin";
++	const struct firmware *fw;
++	unsigned addr;
++	u8 buf[16];
++	int ret;
++
++	ret = request_firmware(&fw, fw_name, anx7688->dev);
++	if (ret < 0)
++		return ret;
++
++	if (fw->size > 0x10000 - 16) {
++		dev_err(anx7688->dev, "Firmware is too big %s\n", fw_name);
++		ret = -E2BIG;
++		goto err_release;
++	}
++
++	mutex_lock(&anx7688->lock);
++
++	/*
++	 * Cabledet changes will not be processed, since we're holding the
++	 * lock, so the firmware flashing is safe from interruptions.
++	 */
++
++	if (test_bit(ANX7688_F_CONNECTED, anx7688->flags))
++		anx7688_disconnect(anx7688);
++
++	msleep(20);
++
++	anx7688_power_enable(anx7688);
++
++	// reset OCM
++	ret = anx7688_reg_update_bits(anx7688, ANX7688_REG_USBC_RESET_CTRL,
++				      ANX7688_USBC_RESET_CTRL_OCM_RESET,
++				      ANX7688_USBC_RESET_CTRL_OCM_RESET);
++	if (ret < 0)
++		goto err_unlock;
++
++	ret = anx7688_eeprom_wait_ready(anx7688);
++	if (ret)
++		goto err_unlock;
++
++	msleep(10);
++
++	/*
++	 * Write to some magic registers to unlock flashing the EEPROM.
++	 */
++	ret = anx7688_reg_update_bits(anx7688, 0x3f, BIT(5), BIT(5));
++	if (ret < 0)
++		goto err_unlock;
++
++	ret = anx7688_reg_update_bits(anx7688, 0x44,
++				      BIT(0) | BIT(7),
++				      BIT(0) | BIT(7));
++	if (ret < 0)
++		goto err_unlock;
++
++	ret = anx7688_reg_update_bits(anx7688, 0x66, BIT(3), BIT(3));
++	if (ret < 0)
++		goto err_unlock;
++
++	msleep(50);
++
++	ret = anx7688_eeprom_wait_done(anx7688);
++	if (ret)
++		goto err_unlock;
++
++	for (addr = 0; addr < fw->size; addr += sizeof buf) {
++		memset(buf, 0, sizeof buf);
++		memcpy(buf, fw->data + addr, min_t(unsigned, fw->size - addr, sizeof buf));
++
++		ret = anx7688_eeprom_write(anx7688, addr + 0x10, buf);
++		if (ret < 0)
++			goto err_unlock;
++	}
++
++	clear_bit(ANX7688_F_FW_FAILED, anx7688->flags);
++
++err_unlock:
++	anx7688_power_disable(anx7688);
++	schedule_delayed_work(&anx7688->work, msecs_to_jiffies(20));
++	mutex_unlock(&anx7688->lock);
++
++err_release:
++	release_firmware(fw);
++	return ret;
++}
++
++static const struct typec_operations anx7688_typec_ops = {
++	.dr_set = anx7688_dr_set,
++	.pr_set = anx7688_pr_set,
++};
++
++static ssize_t flash_eeprom_show(struct device *dev,
++				 struct device_attribute *attr, char *buf)
++{
++	return scnprintf(buf, PAGE_SIZE, "Write 1 to this file to initiate firmware flashing. Consult dmesg for results.\n");
++}
++
++static ssize_t flash_eeprom_store(struct device *dev,
++				  struct device_attribute *attr,
++				  const char *buf, size_t len)
++{
++	struct anx7688 *anx7688 = i2c_get_clientdata(to_i2c_client(dev));
++	unsigned val;
++	int ret;
++
++	ret = kstrtouint(buf, 0, &val);
++	if (ret)
++		return ret;
++
++	if (val == 1) {
++		ret = anx7688_flash_firmware(anx7688);
++		if (ret)
++			return ret;
++	}
++
++	return len;
++}
++static DEVICE_ATTR_RW(flash_eeprom);
++
++static ssize_t reg_update_store(struct device *dev,
++				struct device_attribute *attr,
++				const char *buf, size_t len)
++{
++	struct anx7688 *anx7688 = i2c_get_clientdata(to_i2c_client(dev));
++	unsigned val, addr, devaddr, data;
++	int ret;
++
++	ret = kstrtouint(buf, 16, &val);
++	if (ret)
++		return ret;
++
++	data = val & 0xff;
++	addr = (val >> 8) & 0xff;
++	devaddr = (val >> 16) & 0xff;
++
++	mutex_lock(&anx7688->lock);
++
++	if (!test_bit(ANX7688_F_POWERED, anx7688->flags)) {
++		ret = -ENODEV;
++		goto out_unlock;
++	}
++
++	if (devaddr == 0x50)
++		ret = anx7688_reg_write(anx7688, addr, val);
++	else if (devaddr == 0x58)
++		ret = anx7688_tcpc_reg_write(anx7688, addr, val);
++	else
++		ret = -EINVAL;
++
++out_unlock:
++	mutex_unlock(&anx7688->lock);
++
++	return ret ? ret : len;
++}
++static DEVICE_ATTR_WO(reg_update);
++
++static ssize_t hwreset_store(struct device *dev,
++			     struct device_attribute *attr,
++			     const char *buf, size_t len)
++{
++	struct anx7688 *anx7688 = i2c_get_clientdata(to_i2c_client(dev));
++
++	mutex_lock(&anx7688->lock);
++
++	if (test_bit(ANX7688_F_CONNECTED, anx7688->flags))
++		anx7688_disconnect(anx7688);
++
++	schedule_delayed_work(&anx7688->work, msecs_to_jiffies(20));
++	mutex_unlock(&anx7688->lock);
++
++	return len;
++}
++static DEVICE_ATTR_WO(hwreset);
++
++static struct attribute *anx7688_attrs[] = {
++	&dev_attr_flash_eeprom.attr,
++	&dev_attr_reg_update.attr,
++	&dev_attr_hwreset.attr,
++	NULL,
++};
++
++ATTRIBUTE_GROUPS(anx7688);
++
++/*
++ * This function has to work when the ANX7688 is active, and when
++ * it is powered down. It power cycles the chip and asserts the OCM
++ * reset, to prevent OCM FW interfering with EEPROM reading.
++ *
++ * After reading EEPROM, the reconnection is scheduled.
++ */
++static int anx7688_firmware_show(struct seq_file *s, void *data)
++{
++	struct anx7688 *anx7688 = s->private;
++	unsigned addr;
++	u8 buf[16];
++	int ret;
++
++	mutex_lock(&anx7688->lock);
++
++	if (test_bit(ANX7688_F_CONNECTED, anx7688->flags))
++		anx7688_disconnect(anx7688);
++
++	msleep(20);
++
++	anx7688_power_enable(anx7688);
++
++	ret = anx7688_reg_update_bits(anx7688, ANX7688_REG_USBC_RESET_CTRL,
++				      ANX7688_USBC_RESET_CTRL_OCM_RESET,
++				      ANX7688_USBC_RESET_CTRL_OCM_RESET);
++	if (ret < 0)
++		goto out_powerdown;
++
++	ret = anx7688_eeprom_wait_ready(anx7688);
++	if (ret)
++		goto out_powerdown;
++
++	msleep(10);
++
++	for (addr = 0x10; addr < 0x10000; addr += 16) {
++		// set address
++		ret = anx7688_eeprom_read(anx7688, addr, buf);
++		if (ret < 0)
++			goto out_powerdown;
++
++		seq_write(s, buf, sizeof buf);
++	}
++
++out_powerdown:
++	anx7688_power_disable(anx7688);
++	schedule_delayed_work(&anx7688->work, 0);
++	mutex_unlock(&anx7688->lock);
++
++	return ret;
++}
++DEFINE_SHOW_ATTRIBUTE(anx7688_firmware);
++
++static int anx7688_regs_show(struct seq_file *s, void *data)
++{
++	struct anx7688 *anx7688 = s->private;
++	u8 buf[16];
++	unsigned i, addr;
++	int ret = -ENODEV;
++
++	mutex_lock(&anx7688->lock);
++
++	if (!test_bit(ANX7688_F_POWERED, anx7688->flags))
++		goto out_unlock;
++
++	for (addr = 0; addr < 256; addr += 16) {
++		ret = i2c_smbus_read_i2c_block_data(anx7688->client, addr,
++						    sizeof buf, buf);
++		if (ret < 0) {
++			dev_err(anx7688->dev,
++				"failed to read registers (err=%d)\n", ret);
++			goto out_unlock;
++		}
++
++		for (i = 0; i < 16; i++)
++			seq_printf(s, "50%02x: %02x\n", addr + i, buf[i]);
++	}
++
++	for (addr = 0; addr < 256; addr += 16) {
++		ret = i2c_smbus_read_i2c_block_data(anx7688->client_tcpc, addr,
++						    sizeof buf, buf);
++		if (ret < 0) {
++			dev_err(anx7688->dev,
++				"failed to read registers (err=%d)\n", ret);
++			goto out_unlock;
++		}
++
++		for (i = 0; i < 16; i++)
++			seq_printf(s, "58%02x: %02x\n", addr + i, buf[i]);
++	}
++
++out_unlock:
++	mutex_unlock(&anx7688->lock);
++
++	return ret;
++}
++DEFINE_SHOW_ATTRIBUTE(anx7688_regs);
++
++static int anx7688_status_show(struct seq_file *s, void *data)
++{
++	struct anx7688 *anx7688 = s->private;
++
++	mutex_lock(&anx7688->lock);
++
++	seq_printf(s, "not much\n");
++
++	mutex_unlock(&anx7688->lock);
++
++	return 0;
++}
++DEFINE_SHOW_ATTRIBUTE(anx7688_status);
++
++/*
++ * This is just a 1s watchdog checking the state if cabledet pin.
++ */
++static void anx7688_cabledet_timer_fn(struct timer_list *t)
++{
++	struct anx7688 *anx7688 = from_timer(anx7688, t, work_timer);
++
++	schedule_delayed_work(&anx7688->work, 0);
++	mod_timer(t, jiffies + msecs_to_jiffies(1000));
++}
++
++static void anx7688_handle_vbus_in_notify(struct anx7688* anx7688)
++{
++	union power_supply_propval psy_val = {0,};
++	struct device *dev = anx7688->dev;
++	int ret;
++
++	/* PD charger doesn't like this for some reason, so it's disabled for now */
++	if (anx7688->input_current_limit && false) {
++		ret = power_supply_get_property(anx7688->vbus_in_supply,
++						POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT,
++						&psy_val);
++		if (ret) {
++			dev_err(dev, "failed to get vbus_in current\n");
++			return;
++		}
++
++		if (psy_val.intval == anx7688->input_current_limit)
++			goto check_type;
++
++		psy_val.intval = anx7688->input_current_limit * 1000;
++		dev_dbg(dev, "setting vbus_in current limit to %d mA\n",
++			psy_val.intval / 1000);
++		ret = power_supply_set_property(anx7688->vbus_in_supply,
++						POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT,
++						&psy_val);
++		if (ret)
++			dev_err(dev, "failed to set vbus_in current to %d mA\n",
++				psy_val.intval / 1000);
++	}
++
++check_type:
++	ret = power_supply_get_property(anx7688->vbus_in_supply,
++					POWER_SUPPLY_PROP_USB_TYPE,
++					&psy_val);
++	if (ret) {
++		dev_err(dev, "failed to get USB BC1.2 result\n");
++		return;
++	}
++
++	if (anx7688->last_bc_result == psy_val.intval)
++		return;
++
++	anx7688->last_bc_result = psy_val.intval;
++
++	switch (psy_val.intval) {
++	case POWER_SUPPLY_USB_TYPE_DCP:
++	case POWER_SUPPLY_USB_TYPE_CDP:
++		dev_dbg(dev, "BC 1.2 result: DCP or CDP\n");
++		break;
++	case POWER_SUPPLY_USB_TYPE_SDP:
++	default:
++		dev_dbg(dev, "BC 1.2 result: SDP\n");
++		break;
++	}
++}
++
++static int anx7688_cc_status(unsigned v)
++{
++	switch (v) {
++	case 0: return -1;
++	case 1: return -1;
++	case 2: return -1;
++	case 4: return TYPEC_PWR_MODE_USB;
++	case 8: return TYPEC_PWR_MODE_1_5A;
++	case 12: return TYPEC_PWR_MODE_3_0A;
++	default: return -1;
++	}
++}
++
++static const char* anx7688_get_power_mode_name(enum typec_pwr_opmode mode)
++{
++	switch (mode) {
++	case TYPEC_PWR_MODE_USB: return "USB";
++	case TYPEC_PWR_MODE_1_5A: return "1.5A";
++	case TYPEC_PWR_MODE_3_0A: return "3.0A";
++	case TYPEC_PWR_MODE_PD: return "PD";
++	default: return "Unknown";
++	}
++}
++
++/*
++ * This is called after 500ms after connection when the PD contract should have
++ * been negotiated. We should inspect CC pins or PD status here and decide what
++ * input current limit to set.
++ */
++static void anx7688_handle_current_update(struct anx7688* anx7688)
++{
++	unsigned cc_status = anx7688->last_cc_status;
++	union power_supply_propval val = {0,};
++	struct device *dev = anx7688->dev;
++	int pwr_mode, ret, current_limit = 0;
++
++	if (anx7688->pd_capable) {
++		pwr_mode = TYPEC_PWR_MODE_PD;
++	} else if (cc_status < 0) {
++		pwr_mode = TYPEC_PWR_MODE_USB;
++	} else {
++		pwr_mode = anx7688_cc_status(cc_status & 0xf);
++		if (pwr_mode < 0)
++			pwr_mode = anx7688_cc_status((cc_status >> 4) & 0xf);
++		if (pwr_mode < 0)
++			pwr_mode = TYPEC_PWR_MODE_USB;
++	}
++
++	if (pwr_mode == TYPEC_PWR_MODE_1_5A)
++		current_limit = 1500;
++	else if (pwr_mode == TYPEC_PWR_MODE_3_0A)
++		current_limit = 3000;
++	else if (pwr_mode == TYPEC_PWR_MODE_PD)
++		current_limit = anx7688->pd_current_limit;
++
++	anx7688->input_current_limit = current_limit;
++
++	dev_info(anx7688->dev, "updating power mode to %s, current limit %dmA (0 => BC1.2)\n",
++		 anx7688_get_power_mode_name(pwr_mode), current_limit);
++
++	if (current_limit) {
++		/*
++		 * Disable BC1.2 detection, because we'll be setting
++		 * a current limit determined by USB-PD
++		 */
++		val.intval = 0;
++		dev_dbg(dev, "disabling USB BC 1.2 detection\n");
++		ret = power_supply_set_property(anx7688->vbus_in_supply,
++						POWER_SUPPLY_PROP_USB_BC_ENABLED,
++						&val);
++		if (ret)
++			dev_err(dev, "failed to disable USB BC1.2 detection\n");
++
++		val.intval = current_limit * 1000;
++		dev_dbg(dev, "setting vbus_in current limit to %d mA\n", current_limit);
++		ret = power_supply_set_property(anx7688->vbus_in_supply,
++						POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT,
++						&val);
++		if (ret)
++			dev_err(dev, "failed to set vbus_in current to %d mA\n",
++				current_limit);
++	} else {
++		/*
++		 * Use the result of BC1.2 detection performed by PMIC.
++		 */
++		ret = power_supply_get_property(anx7688->vbus_in_supply,
++						POWER_SUPPLY_PROP_USB_BC_ENABLED,
++						&val);
++		if (ret)
++			dev_err(dev, "failed to get USB BC1.2 detection status\n");
++
++		if (ret != 0 || val.intval == 0) {
++			/*
++			 * If BC is disabled or we can't get its status,
++			 * set conservative 500mA limit. Otherwise leave
++			 * the limit to BC1.2.
++			 */
++			val.intval = 500 * 1000;
++			dev_dbg(dev, "setting vbus_in current limit to %d mA\n",
++				val.intval / 1000);
++			ret = power_supply_set_property(anx7688->vbus_in_supply,
++							POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT,
++							&val);
++			if (ret)
++				dev_err(dev, "failed to set vbus_in current to %d mA\n",
++					val.intval / 1000);
++		}
++	}
++
++	/* Turn on VBUS power path inside PMIC. */
++	val.intval = 1;
++	dev_dbg(dev, "enabling vbus_in power path\n");
++	ret = power_supply_set_property(anx7688->vbus_in_supply,
++					POWER_SUPPLY_PROP_ONLINE,
++					&val);
++	if (ret)
++		dev_err(anx7688->dev, "failed to enable vbus_in\n");
++
++	typec_set_pwr_opmode(anx7688->port, pwr_mode);
++}
++
++static int anx7688_vbus_in_notify(struct notifier_block *nb,
++				  unsigned long val, void *v)
++{
++	struct anx7688 *anx7688 = container_of(nb, struct anx7688, vbus_in_nb);
++	struct power_supply *psy = v;
++
++	/* atomic context */
++	if (val == PSY_EVENT_PROP_CHANGED && psy == anx7688->vbus_in_supply) {
++		set_bit(ANX7688_F_PWRSUPPLY_CHANGE, anx7688->flags);
++		schedule_delayed_work(&anx7688->work, 0);
++	}
++
++	return NOTIFY_OK;
++}
++
++static void anx7688_work(struct work_struct *work)
++{
++	struct anx7688 *anx7688 = container_of(work, struct anx7688, work.work);
++
++	if (test_bit(ANX7688_F_FW_FAILED, anx7688->flags))
++		return;
++
++	mutex_lock(&anx7688->lock);
++
++	if (test_and_clear_bit(ANX7688_F_PWRSUPPLY_CHANGE, anx7688->flags))
++		anx7688_handle_vbus_in_notify(anx7688);
++
++	anx7688_handle_cable_change(anx7688);
++
++	if (test_bit(ANX7688_F_CONNECTED, anx7688->flags)) {
++		/*
++		 * We check status periodically outside of interrupt, just to
++		 * be sure we didn't miss any status interrupts
++		 */
++		anx7688_update_status(anx7688);
++
++		if (anx7688->current_update_deadline &&
++		    ktime_after(ktime_get(), anx7688->current_update_deadline)) {
++			anx7688->current_update_deadline = 0;
++			anx7688_handle_current_update(anx7688);
++		}
++	}
++
++	mutex_unlock(&anx7688->lock);
++}
++
++static int anx7688_i2c_probe(struct i2c_client *client)
++{
++	struct anx7688 *anx7688;
++	struct device *dev = &client->dev;
++	struct typec_capability typec_cap = { };
++	union power_supply_propval psy_val;
++	int i, vid_h, vid_l;
++	int irq_cabledet;
++	int ret = 0;
++
++	anx7688 = devm_kzalloc(dev, sizeof(*anx7688), GFP_KERNEL);
++	if (!anx7688)
++		return -ENOMEM;
++
++	i2c_set_clientdata(client, anx7688);
++	anx7688->client = client;
++	anx7688->dev = &client->dev;
++	mutex_init(&anx7688->lock);
++	INIT_DELAYED_WORK(&anx7688->work, anx7688_work);
++	anx7688->last_extcon_state = -1;
++
++	ret = of_property_read_variable_u32_array(dev->of_node, "source-caps",
++						  anx7688->src_caps,
++						  1, ARRAY_SIZE(anx7688->src_caps));
++	if (ret < 0) {
++		dev_err(dev, "failed to get source-caps from DT\n");
++		return ret;
++	}
++	anx7688->n_src_caps = ret;
++
++	ret = of_property_read_variable_u32_array(dev->of_node, "sink-caps",
++						  anx7688->snk_caps,
++						  1, ARRAY_SIZE(anx7688->snk_caps));
++	if (ret < 0) {
++		dev_err(dev, "failed to get sink-caps from DT\n");
++		return ret;
++	}
++	anx7688->n_snk_caps = ret;
++
++	for (i = 0; i < ANX7688_NUM_SUPPLIES; i++)
++		anx7688->supplies[i].supply = anx7688_supply_names[i];
++	ret = devm_regulator_bulk_get(dev, ANX7688_NUM_SUPPLIES,
++				      anx7688->supplies);
++	if (ret)
++		return ret;
++
++	anx7688->vbus_in_supply =
++		devm_power_supply_get_by_phandle(dev, "vbus_in-supply");
++	if (IS_ERR(anx7688->vbus_in_supply)) {
++		dev_err(dev, "Couldn't get the VBUS power supply\n");
++		return PTR_ERR(anx7688->vbus_in_supply);
++	}
++
++	if (!anx7688->vbus_in_supply)
++		return -EPROBE_DEFER;
++
++	anx7688->gpio_enable = devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW);
++	if (IS_ERR(anx7688->gpio_enable)) {
++		dev_err(dev, "Could not get enable gpio\n");
++		return PTR_ERR(anx7688->gpio_enable);
++	}
++
++	anx7688->gpio_reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
++	if (IS_ERR(anx7688->gpio_reset)) {
++		dev_err(dev, "Could not get reset gpio\n");
++		return PTR_ERR(anx7688->gpio_reset);
++	}
++
++	anx7688->gpio_cabledet = devm_gpiod_get(dev, "cabledet", GPIOD_IN);
++	if (IS_ERR(anx7688->gpio_cabledet)) {
++		dev_err(dev, "Could not get cabledet gpio\n");
++		return PTR_ERR(anx7688->gpio_cabledet);
++	}
++
++	irq_cabledet = gpiod_to_irq(anx7688->gpio_cabledet);
++	if (irq_cabledet < 0) {
++		dev_err(dev, "Could not get cabledet irq\n");
++		return irq_cabledet;
++	}
++
++	ret = devm_device_add_groups(&client->dev, anx7688_groups);
++	if (ret)
++		return ret;
++
++	// Initialize extcon device
++	anx7688->extcon = devm_extcon_dev_allocate(dev, anx7688_extcon_cable);
++	if (IS_ERR(anx7688->extcon))
++		return -ENOMEM;
++
++	ret = devm_extcon_dev_register(dev, anx7688->extcon);
++	if (ret) {
++		dev_err(dev, "failed to register extcon device\n");
++		return ret;
++	}
++
++	// Register the TCPC i2c interface as second interface (0x58)
++	anx7688->client_tcpc = i2c_new_dummy_device(client->adapter, 0x2c);
++	if (IS_ERR(anx7688->client_tcpc)) {
++		dev_err(dev, "Could not register tcpc i2c client\n");
++		return PTR_ERR(anx7688->client_tcpc);
++	}
++	i2c_set_clientdata(anx7688->client_tcpc, anx7688);
++
++	// powerup and probe the ANX chip
++
++	ret = regulator_bulk_enable(ANX7688_NUM_ALWAYS_ON_SUPPLIES,
++				    anx7688->supplies);
++	if (ret) {
++		dev_err(dev, "Could not enable regulators\n");
++		goto err_dummy_dev;
++	}
++
++	msleep(10);
++
++	anx7688_power_enable(anx7688);
++
++	vid_l = anx7688_tcpc_reg_read(anx7688, ANX7688_TCPC_REG_VENDOR_ID0);
++	vid_h = anx7688_tcpc_reg_read(anx7688, ANX7688_TCPC_REG_VENDOR_ID1);
++	if (vid_l < 0 || vid_h < 0) {
++		ret = vid_l < 0 ? vid_l : vid_h;
++		anx7688_power_disable(anx7688);
++		goto err_disable_reg;
++	}
++
++	dev_info(dev, "Vendor id 0x%04x\n", vid_l | vid_h << 8);
++
++	anx7688_power_disable(anx7688);
++
++	anx7688->role_sw = usb_role_switch_get(dev);
++	if (IS_ERR(anx7688->role_sw)) {
++		dev_err(dev, "Could not get role switch\n");
++		ret = PTR_ERR(anx7688->role_sw);
++		goto err_disable_reg;
++	}
++
++	// setup a typec port device
++	typec_cap.revision = USB_TYPEC_REV_1_2;
++	typec_cap.pd_revision = 0x200;
++	typec_cap.prefer_role = TYPEC_NO_PREFERRED_ROLE;
++	typec_cap.type = TYPEC_PORT_DRP;
++	typec_cap.data = TYPEC_PORT_DRD;
++	typec_cap.driver_data = anx7688;
++	typec_cap.ops = &anx7688_typec_ops;
++
++	anx7688->port = typec_register_port(dev, &typec_cap);
++	if (IS_ERR(anx7688->port)) {
++		dev_err(dev, "Could not register type-c port\n");
++		ret = PTR_ERR(anx7688->port);
++		goto err_role_sw;
++	}
++
++	anx7688->pwr_role = TYPEC_SINK;
++	anx7688->data_role = TYPEC_DEVICE;
++	typec_set_pwr_role(anx7688->port, anx7688->pwr_role);
++	typec_set_data_role(anx7688->port, anx7688->data_role);
++	typec_set_pwr_opmode(anx7688->port, TYPEC_PWR_MODE_USB);
++	typec_set_vconn_role(anx7688->port, TYPEC_SINK);
++
++	// make sure BC1.2 detection in PMIC is enabled
++	anx7688->last_bc_result = -1;
++	psy_val.intval = 1;
++	dev_dbg(dev, "enabling USB BC 1.2 detection\n");
++	ret = power_supply_set_property(anx7688->vbus_in_supply,
++					POWER_SUPPLY_PROP_USB_BC_ENABLED,
++					&psy_val);
++	if (ret) {
++		dev_err(anx7688->dev, "failed to enable BC1.2 detection\n");
++		goto err_cport;
++	}
++
++	ret = devm_request_irq(dev, irq_cabledet, anx7688_irq_plug_handler,
++			       IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
++			       "anx7688-cabledet", anx7688);
++	if (ret < 0) {
++		dev_err(dev, "Could not request cabledet irq (%d)\n", ret);
++		goto err_cport;
++	}
++
++	ret = devm_request_threaded_irq(dev, client->irq,
++					NULL, anx7688_irq_status_handler,
++					IRQF_ONESHOT, NULL, anx7688);
++	if (ret < 0) {
++		dev_err(dev, "Could not request irq (%d)\n", ret);
++		goto err_cport;
++	}
++
++	anx7688->vbus_in_nb.notifier_call = anx7688_vbus_in_notify;
++	anx7688->vbus_in_nb.priority = 0;
++	ret = power_supply_reg_notifier(&anx7688->vbus_in_nb);
++	if (ret)
++		goto err_cport;
++
++	anx7688->debug_root = debugfs_create_dir("anx7688", NULL);
++	debugfs_create_file("firmware", 0444, anx7688->debug_root, anx7688,
++			    &anx7688_firmware_fops);
++	debugfs_create_file("regs", 0444, anx7688->debug_root, anx7688,
++			    &anx7688_regs_fops);
++	debugfs_create_file("status", 0444, anx7688->debug_root, anx7688,
++			    &anx7688_status_fops);
++
++	schedule_delayed_work(&anx7688->work, msecs_to_jiffies(10));
++
++	timer_setup(&anx7688->work_timer, anx7688_cabledet_timer_fn, 0);
++	mod_timer(&anx7688->work_timer, jiffies + msecs_to_jiffies(1000));
++
++	return 0;
++
++err_cport:
++	typec_unregister_port(anx7688->port);
++err_role_sw:
++	usb_role_switch_put(anx7688->role_sw);
++err_disable_reg:
++	regulator_bulk_disable(ANX7688_NUM_ALWAYS_ON_SUPPLIES, anx7688->supplies);
++err_dummy_dev:
++	i2c_unregister_device(anx7688->client_tcpc);
++	return ret;
++}
++
++static void anx7688_i2c_remove(struct i2c_client *client)
++{
++	struct anx7688 *anx7688 = i2c_get_clientdata(client);
++
++	mutex_lock(&anx7688->lock);
++
++	power_supply_unreg_notifier(&anx7688->vbus_in_nb);
++
++	del_timer_sync(&anx7688->work_timer);
++
++	cancel_delayed_work_sync(&anx7688->work);
++
++	if (test_bit(ANX7688_F_CONNECTED, anx7688->flags))
++		anx7688_disconnect(anx7688);
++
++	typec_unregister_partner(anx7688->partner);
++	typec_unregister_port(anx7688->port);
++	usb_role_switch_put(anx7688->role_sw);
++
++	regulator_bulk_disable(ANX7688_NUM_ALWAYS_ON_SUPPLIES, anx7688->supplies);
++	i2c_unregister_device(anx7688->client_tcpc);
++
++	debugfs_remove(anx7688->debug_root);
++
++	mutex_unlock(&anx7688->lock);
++}
++
++static int __maybe_unused anx7688_suspend(struct device *dev)
++{
++	struct anx7688 *anx7688 = i2c_get_clientdata(to_i2c_client(dev));
++
++	del_timer_sync(&anx7688->work_timer);
++	cancel_delayed_work_sync(&anx7688->work);
++
++	regulator_disable(anx7688->supplies[ANX7688_I2C_INDEX].consumer);
++
++	return 0;
++}
++
++static int __maybe_unused anx7688_resume(struct device *dev)
++{
++	struct anx7688 *anx7688 = i2c_get_clientdata(to_i2c_client(dev));
++	int ret;
++
++	ret = regulator_enable(anx7688->supplies[ANX7688_I2C_INDEX].consumer);
++	if (ret)
++		dev_warn(anx7688->dev,
++			 "failed to enable I2C regulator (%d)\n", ret);
++
++	// check status right after resume, since it could have changed during
++	// sleep
++	schedule_delayed_work(&anx7688->work, msecs_to_jiffies(50));
++	mod_timer(&anx7688->work_timer, jiffies + msecs_to_jiffies(1000));
++
++	return 0;
++}
++
++static const struct dev_pm_ops anx7688_pm_ops = {
++	SET_SYSTEM_SLEEP_PM_OPS(anx7688_suspend, anx7688_resume)
++};
++
++static const struct i2c_device_id anx7688_ids[] = {
++	{ "anx7688", 0 },
++	{ }
++};
++MODULE_DEVICE_TABLE(i2c, anx7688_ids);
++
++static struct of_device_id anx7688_of_match_table[] = {
++	{ .compatible = "analogix,anx7688" },
++	{ },
++};
++MODULE_DEVICE_TABLE(of, anx7688_of_match_table);
++
++static struct i2c_driver anx7688_driver = {
++	.driver = {
++		.name = "anx7688",
++		.of_match_table = anx7688_of_match_table,
++		.pm = &anx7688_pm_ops,
++	},
++	.probe = anx7688_i2c_probe,
++	.remove = anx7688_i2c_remove,
++	.id_table = anx7688_ids,
++};
++
++module_i2c_driver(anx7688_driver);
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Martijn Braam <martijn@brixit.nl>");
++MODULE_AUTHOR("Ondrej Jirman <megi@xff.cz>");
++MODULE_DESCRIPTION("Analogix ANX7688 USB-C DisplayPort bridge");
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-anx7688-Port-to-Linux-6.10.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-anx7688-Port-to-Linux-6.10.patch
new file mode 100644
index 000000000000..ee6d63ef4996
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-anx7688-Port-to-Linux-6.10.patch
@@ -0,0 +1,28 @@
+From 2e0399dce5fedc6750458a4284bfb78db5d3f403 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Fri, 5 Jul 2024 23:25:25 +0200
+Subject: usb: typec: anx7688: Port to Linux 6.10
+
+devm_* variant of device_add_groups was dropped.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/typec/anx7688.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/usb/typec/anx7688.c b/drivers/usb/typec/anx7688.c
+index 77c154565340..448a6f48ab36 100644
+--- a/drivers/usb/typec/anx7688.c
++++ b/drivers/usb/typec/anx7688.c
+@@ -1975,7 +1975,7 @@ static int anx7688_i2c_probe(struct i2c_client *client)
+ 		return irq_cabledet;
+ 	}
+ 
+-	ret = devm_device_add_groups(&client->dev, anx7688_groups);
++	ret = device_add_groups(&client->dev, anx7688_groups);
+ 	if (ret)
+ 		return ret;
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-anx7688-Port-to-Linux-6.9.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-anx7688-Port-to-Linux-6.9.patch
new file mode 100644
index 000000000000..7785d8c8a696
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-anx7688-Port-to-Linux-6.9.patch
@@ -0,0 +1,110 @@
+From 4e782d0f529ea1f1ae6a5c01f21cacc3903395c6 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Fri, 15 Mar 2024 23:05:10 +0100
+Subject: usb: typec: anx7688: Port to Linux 6.9
+
+POWER_SUPPLY_PROP_USB_BC_ENABLED is no longer needed, nor supported
+by axp20x driver.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/typec/anx7688.c | 51 ++++---------------------------------
+ 1 file changed, 5 insertions(+), 46 deletions(-)
+
+diff --git a/drivers/usb/typec/anx7688.c b/drivers/usb/typec/anx7688.c
+index fa1d3496af73..77c154565340 100644
+--- a/drivers/usb/typec/anx7688.c
++++ b/drivers/usb/typec/anx7688.c
+@@ -636,14 +636,6 @@ static void anx7688_disconnect(struct anx7688 *anx7688)
+ 	if (ret)
+ 		dev_err(dev, "failed to offline vbus_in\n");
+ 
+-	val.intval = 1;
+-	dev_dbg(dev, "enabling USB BC 1.2 detection\n");
+-	ret = power_supply_set_property(anx7688->vbus_in_supply,
+-					POWER_SUPPLY_PROP_USB_BC_ENABLED,
+-					&val);
+-	if (ret)
+-		dev_err(dev, "failed to enabled USB BC1.2 detection\n");
+-
+ 	clear_bit(ANX7688_F_CONNECTED, anx7688->flags);
+ }
+ 
+@@ -1822,17 +1814,8 @@ static void anx7688_handle_current_update(struct anx7688* anx7688)
+ 
+ 	if (current_limit) {
+ 		/*
+-		 * Disable BC1.2 detection, because we'll be setting
+-		 * a current limit determined by USB-PD
++		 * Set a current limit determined by USB-PD
+ 		 */
+-		val.intval = 0;
+-		dev_dbg(dev, "disabling USB BC 1.2 detection\n");
+-		ret = power_supply_set_property(anx7688->vbus_in_supply,
+-						POWER_SUPPLY_PROP_USB_BC_ENABLED,
+-						&val);
+-		if (ret)
+-			dev_err(dev, "failed to disable USB BC1.2 detection\n");
+-
+ 		val.intval = current_limit * 1000;
+ 		dev_dbg(dev, "setting vbus_in current limit to %d mA\n", current_limit);
+ 		ret = power_supply_set_property(anx7688->vbus_in_supply,
+@@ -1846,27 +1829,13 @@ static void anx7688_handle_current_update(struct anx7688* anx7688)
+ 		 * Use the result of BC1.2 detection performed by PMIC.
+ 		 */
+ 		ret = power_supply_get_property(anx7688->vbus_in_supply,
+-						POWER_SUPPLY_PROP_USB_BC_ENABLED,
++						POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT,
+ 						&val);
+ 		if (ret)
+-			dev_err(dev, "failed to get USB BC1.2 detection status\n");
+-
+-		if (ret != 0 || val.intval == 0) {
+-			/*
+-			 * If BC is disabled or we can't get its status,
+-			 * set conservative 500mA limit. Otherwise leave
+-			 * the limit to BC1.2.
+-			 */
+-			val.intval = 500 * 1000;
+-			dev_dbg(dev, "setting vbus_in current limit to %d mA\n",
++			dev_err(dev, "failed to get vbus_in current limit\n");
++		if (ret == 0)
++			dev_dbg(dev, "vbus_in current limit is %d mA\n",
+ 				val.intval / 1000);
+-			ret = power_supply_set_property(anx7688->vbus_in_supply,
+-							POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT,
+-							&val);
+-			if (ret)
+-				dev_err(dev, "failed to set vbus_in current to %d mA\n",
+-					val.intval / 1000);
+-		}
+ 	}
+ 
+ 	/* Turn on VBUS power path inside PMIC. */
+@@ -1932,7 +1901,6 @@ static int anx7688_i2c_probe(struct i2c_client *client)
+ 	struct anx7688 *anx7688;
+ 	struct device *dev = &client->dev;
+ 	struct typec_capability typec_cap = { };
+-	union power_supply_propval psy_val;
+ 	int i, vid_h, vid_l;
+ 	int irq_cabledet;
+ 	int ret = 0;
+@@ -2087,15 +2055,6 @@ static int anx7688_i2c_probe(struct i2c_client *client)
+ 
+ 	// make sure BC1.2 detection in PMIC is enabled
+ 	anx7688->last_bc_result = -1;
+-	psy_val.intval = 1;
+-	dev_dbg(dev, "enabling USB BC 1.2 detection\n");
+-	ret = power_supply_set_property(anx7688->vbus_in_supply,
+-					POWER_SUPPLY_PROP_USB_BC_ENABLED,
+-					&psy_val);
+-	if (ret) {
+-		dev_err(anx7688->dev, "failed to enable BC1.2 detection\n");
+-		goto err_cport;
+-	}
+ 
+ 	ret = devm_request_irq(dev, irq_cabledet, anx7688_irq_plug_handler,
+ 			       IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-fusb302-Add-OF-extcon-support.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-fusb302-Add-OF-extcon-support.patch
new file mode 100644
index 000000000000..0e3fd9f9f0ae
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-fusb302-Add-OF-extcon-support.patch
@@ -0,0 +1,38 @@
+From 709e2922a1a3df25257575a268c61d76821ca1bc Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 14 Nov 2021 01:14:25 +0100
+Subject: usb: typec: fusb302: Add OF extcon support
+
+It's possible to create a dependency cycle between fusb302 and
+other drivers via extcon device, so we retrieve the device on
+demand after probe and not during probe.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/typec/tcpm/fusb302.c | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/drivers/usb/typec/tcpm/fusb302.c b/drivers/usb/typec/tcpm/fusb302.c
+index 16c3f8d94a9d..eb87fbad87fb 100644
+--- a/drivers/usb/typec/tcpm/fusb302.c
++++ b/drivers/usb/typec/tcpm/fusb302.c
+@@ -519,6 +519,16 @@ static int tcpm_get_current_limit(struct tcpc_dev *dev)
+ 	int current_limit = 0;
+ 	unsigned long timeout;
+ 
++	/*
++	 * To avoid cycles in OF dependencies, we get extcon when necessary
++	 * outside of probe function.
++	 */
++	if (of_property_read_bool(chip->dev->of_node, "extcon") && !chip->extcon) {
++		chip->extcon = extcon_get_edev_by_phandle(chip->dev, 0);
++		if (IS_ERR(chip->extcon))
++			chip->extcon = NULL;
++	}
++
+ 	if (!chip->extcon)
+ 		return 0;
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-fusb302-Clear-interrupts-before-we-start-toggling.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-fusb302-Clear-interrupts-before-we-start-toggling.patch
new file mode 100644
index 000000000000..2595cd232e01
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-fusb302-Clear-interrupts-before-we-start-toggling.patch
@@ -0,0 +1,40 @@
+From 4f7d79c40e49fd119dbd6ee104c1c881528ce595 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 20 Nov 2021 14:35:10 +0100
+Subject: usb: typec: fusb302: Clear interrupts before we start toggling
+
+This is recommended by the datasheet.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/typec/tcpm/fusb302.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/drivers/usb/typec/tcpm/fusb302.c b/drivers/usb/typec/tcpm/fusb302.c
+index eb87fbad87fb..734e87f7cb76 100644
+--- a/drivers/usb/typec/tcpm/fusb302.c
++++ b/drivers/usb/typec/tcpm/fusb302.c
+@@ -587,6 +587,7 @@ static int fusb302_set_toggling(struct fusb302_chip *chip,
+ 				enum toggling_mode mode)
+ {
+ 	int ret = 0;
++	u8 reg;
+ 
+ 	/* first disable toggling */
+ 	ret = fusb302_i2c_clear_bits(chip, FUSB_REG_CONTROL2,
+@@ -645,6 +646,12 @@ static int fusb302_set_toggling(struct fusb302_chip *chip,
+ 	} else {
+ 		/* Datasheet says vconn MUST be off when toggling */
+ 		WARN(chip->vconn_on, "Vconn is on during toggle start");
++
++		/* clear interrupts */
++                ret = fusb302_i2c_read(chip, FUSB_REG_INTERRUPT, &reg);
++		if (ret < 0)
++			return ret;
++
+ 		/* unmask TOGDONE interrupt */
+ 		ret = fusb302_i2c_clear_bits(chip, FUSB_REG_MASKA,
+ 					     FUSB_REG_MASKA_TOGDONE);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-fusb302-Extend-debugging-interface-with-driver-state-.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-fusb302-Extend-debugging-interface-with-driver-state-.patch
new file mode 100644
index 000000000000..8ba6789d2696
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-fusb302-Extend-debugging-interface-with-driver-state-.patch
@@ -0,0 +1,112 @@
+From e1b00df124f5b8feb982559b0cd5c31d18ebebae Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 7 Nov 2021 19:29:06 +0100
+Subject: usb: typec: fusb302: Extend debugging interface with driver state
+ dumps
+
+This is useful for debugging.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/typec/tcpm/fusb302.c | 78 ++++++++++++++++++++++++++++++++
+ 1 file changed, 78 insertions(+)
+
+diff --git a/drivers/usb/typec/tcpm/fusb302.c b/drivers/usb/typec/tcpm/fusb302.c
+index 53fa863dfa96..2ee7222e531a 100644
+--- a/drivers/usb/typec/tcpm/fusb302.c
++++ b/drivers/usb/typec/tcpm/fusb302.c
+@@ -208,6 +208,81 @@ static int fusb302_debug_show(struct seq_file *s, void *v)
+ }
+ DEFINE_SHOW_ATTRIBUTE(fusb302_debug);
+ 
++static const char * const typec_cc_status_name[];
++static const char * const cc_polarity_name[];
++static const char * const toggling_mode_name[] = {
++	[TOGGLING_MODE_OFF] = "Off",
++	[TOGGLING_MODE_DRP] = "DRP",
++	[TOGGLING_MODE_SNK] = "SNK",
++	[TOGGLING_MODE_SRC] = "SRC",
++};
++static const char * const src_current_status_name[] = {
++	[SRC_CURRENT_DEFAULT] = "Default",
++	[SRC_CURRENT_MEDIUM] = "Medium",
++	[SRC_CURRENT_HIGH] = "High",
++};
++
++#define FUSB_REG(n) { n, #n },
++struct fusb_reg {
++	u8 addr;
++	const char* name;
++} fusb_regs[] = {
++	FUSB_REG(FUSB_REG_DEVICE_ID)
++	FUSB_REG(FUSB_REG_SWITCHES0)
++	FUSB_REG(FUSB_REG_SWITCHES1)
++	FUSB_REG(FUSB_REG_MEASURE)
++	FUSB_REG(FUSB_REG_CONTROL0)
++	FUSB_REG(FUSB_REG_CONTROL1)
++	FUSB_REG(FUSB_REG_CONTROL2)
++	FUSB_REG(FUSB_REG_CONTROL3)
++	FUSB_REG(FUSB_REG_MASK)
++	FUSB_REG(FUSB_REG_POWER)
++	FUSB_REG(FUSB_REG_RESET)
++	FUSB_REG(FUSB_REG_MASKA)
++	FUSB_REG(FUSB_REG_MASKB)
++	FUSB_REG(FUSB_REG_STATUS0A)
++	FUSB_REG(FUSB_REG_STATUS1A)
++	FUSB_REG(FUSB_REG_INTERRUPTA)
++	FUSB_REG(FUSB_REG_INTERRUPTB)
++	FUSB_REG(FUSB_REG_STATUS0)
++	FUSB_REG(FUSB_REG_STATUS1)
++	FUSB_REG(FUSB_REG_INTERRUPT)
++};
++
++static int fusb302_i2c_read(struct fusb302_chip *chip,
++			    u8 address, u8 *data);
++
++static int fusb302_debug_regs_show(struct seq_file *s, void *v)
++{
++	struct fusb302_chip *chip = (struct fusb302_chip *)s->private;
++	int i, ret;
++
++	seq_printf(s, "chip->intr_togdone = %d\n", chip->intr_togdone);
++	seq_printf(s, "chip->intr_bc_lvl = %d\n", chip->intr_bc_lvl);
++	seq_printf(s, "chip->intr_comp_chng = %d\n", chip->intr_comp_chng);
++	seq_printf(s, "chip->vconn_on = %d\n", chip->vconn_on);
++	seq_printf(s, "chip->vbus_on = %d\n", chip->vbus_on);
++	seq_printf(s, "chip->charge_on = %d\n", chip->charge_on);
++	seq_printf(s, "chip->vbus_present = %d\n", chip->vbus_present);
++	seq_printf(s, "chip->cc_polarity = %s\n", cc_polarity_name[chip->cc_polarity]);
++	seq_printf(s, "chip->cc1 = %s\n", typec_cc_status_name[chip->cc1]);
++	seq_printf(s, "chip->cc2 = %s\n", typec_cc_status_name[chip->cc2]);
++	seq_printf(s, "chip->toggling_mode = %s\n", toggling_mode_name[chip->toggling_mode]);
++	seq_printf(s, "chip->src_current_status = %s\n", src_current_status_name[chip->src_current_status]);
++
++	seq_printf(s, "\nRegisters:\n");
++        for (i = 0; i < ARRAY_SIZE(fusb_regs); i++) {
++		u8 val = 0;
++
++		ret = fusb302_i2c_read(chip, fusb_regs[i].addr, &val);
++		if (ret >= 0)
++			seq_printf(s, "%s = %02hhx\n", fusb_regs[i].name, val);
++	}
++
++	return 0;
++}
++DEFINE_SHOW_ATTRIBUTE(fusb302_debug_regs);
++
+ static void fusb302_debugfs_init(struct fusb302_chip *chip)
+ {
+ 	char name[NAME_MAX];
+@@ -217,6 +292,9 @@ static void fusb302_debugfs_init(struct fusb302_chip *chip)
+ 	chip->dentry = debugfs_create_dir(name, usb_debug_root);
+ 	debugfs_create_file("log", S_IFREG | 0444, chip->dentry, chip,
+ 			    &fusb302_debug_fops);
++
++	debugfs_create_file("regs", S_IFREG | 0444, chip->dentry, chip,
++			    &fusb302_debug_regs_fops);
+ }
+ 
+ static void fusb302_debugfs_exit(struct fusb302_chip *chip)
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-fusb302-Fix-register-definitions.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-fusb302-Fix-register-definitions.patch
new file mode 100644
index 000000000000..8330ea2057ed
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-fusb302-Fix-register-definitions.patch
@@ -0,0 +1,49 @@
+From 147bad79f8711565de8231fb6763cadeac0e7eed Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sat, 20 Nov 2021 14:33:58 +0100
+Subject: usb: typec: fusb302: Fix register definitions
+
+MEASURE_VBUS bit is at position 6. MDAC bits are also wrong.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/typec/tcpm/fusb302_reg.h | 16 +++++++---------
+ 1 file changed, 7 insertions(+), 9 deletions(-)
+
+diff --git a/drivers/usb/typec/tcpm/fusb302_reg.h b/drivers/usb/typec/tcpm/fusb302_reg.h
+index edc0e4b0f1e6..f37d226c5027 100644
+--- a/drivers/usb/typec/tcpm/fusb302_reg.h
++++ b/drivers/usb/typec/tcpm/fusb302_reg.h
+@@ -27,14 +27,13 @@
+ #define FUSB_REG_SWITCHES1_TXCC2_EN		BIT(1)
+ #define FUSB_REG_SWITCHES1_TXCC1_EN		BIT(0)
+ #define FUSB_REG_MEASURE			0x04
+-#define FUSB_REG_MEASURE_MDAC5			BIT(7)
+-#define FUSB_REG_MEASURE_MDAC4			BIT(6)
+-#define FUSB_REG_MEASURE_MDAC3			BIT(5)
+-#define FUSB_REG_MEASURE_MDAC2			BIT(4)
+-#define FUSB_REG_MEASURE_MDAC1			BIT(3)
+-#define FUSB_REG_MEASURE_MDAC0			BIT(2)
+-#define FUSB_REG_MEASURE_VBUS			BIT(1)
+-#define FUSB_REG_MEASURE_XXXX5			BIT(0)
++#define FUSB_REG_MEASURE_VBUS			BIT(6)
++#define FUSB_REG_MEASURE_MDAC5			BIT(5)
++#define FUSB_REG_MEASURE_MDAC4			BIT(4)
++#define FUSB_REG_MEASURE_MDAC3			BIT(3)
++#define FUSB_REG_MEASURE_MDAC2			BIT(2)
++#define FUSB_REG_MEASURE_MDAC1			BIT(1)
++#define FUSB_REG_MEASURE_MDAC0			BIT(0)
+ #define FUSB_REG_CONTROL0			0x06
+ #define FUSB_REG_CONTROL0_TX_FLUSH		BIT(6)
+ #define FUSB_REG_CONTROL0_INT_MASK		BIT(5)
+@@ -105,7 +104,6 @@
+ #define FUSB_REG_STATUS0A_RX_SOFT_RESET		BIT(1)
+ #define FUSB_REG_STATUS0A_RX_HARD_RESET		BIT(0)
+ #define FUSB_REG_STATUS1A			0x3D
+-#define FUSB_REG_STATUS1A_TOGSS			BIT(3)
+ #define FUSB_REG_STATUS1A_TOGSS_RUNNING		0x0
+ #define FUSB_REG_STATUS1A_TOGSS_SRC1		0x1
+ #define FUSB_REG_STATUS1A_TOGSS_SRC2		0x2
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-fusb302-More-useful-of-logging-status-on-interrupt.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-fusb302-More-useful-of-logging-status-on-interrupt.patch
new file mode 100644
index 000000000000..375cbc7ec38b
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-fusb302-More-useful-of-logging-status-on-interrupt.patch
@@ -0,0 +1,189 @@
+From e678c93a59c3442d081762fcaaad8e5af760a5e5 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 23 Nov 2021 17:55:34 +0100
+Subject: usb: typec: fusb302: More useful of logging status on interrupt
+
+This is just for debugging. It prints more info that's useful to
+see how hardware state changes in time.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/typec/tcpm/fusb302.c | 121 ++++++++++++++++++++++++++-----
+ 1 file changed, 104 insertions(+), 17 deletions(-)
+
+diff --git a/drivers/usb/typec/tcpm/fusb302.c b/drivers/usb/typec/tcpm/fusb302.c
+index 808bcf4cb24d..c30f93ec78fa 100644
+--- a/drivers/usb/typec/tcpm/fusb302.c
++++ b/drivers/usb/typec/tcpm/fusb302.c
+@@ -69,7 +69,7 @@ static const u8 rd_mda_value[] = {
+ };
+ 
+ #define LOG_BUFFER_ENTRIES	1024
+-#define LOG_BUFFER_ENTRY_SIZE	128
++#define LOG_BUFFER_ENTRY_SIZE	256
+ 
+ struct fusb302_chip {
+ 	struct device *dev;
+@@ -1598,6 +1598,84 @@ static irqreturn_t fusb302_irq_intn(int irq, void *dev_id)
+ 	return IRQ_HANDLED;
+ }
+ 
++static void fusb302_print_state(struct fusb302_chip *chip)
++{
++	u8 ctl0, ctl2, measure, status0, status1a, sw0, mask;
++	int ret;
++
++	ret = fusb302_i2c_read(chip, FUSB_REG_CONTROL0, &ctl0);
++	if (ret < 0)
++		return;
++	ret = fusb302_i2c_read(chip, FUSB_REG_CONTROL2, &ctl2);
++	if (ret < 0)
++		return;
++	ret = fusb302_i2c_read(chip, FUSB_REG_MEASURE, &measure);
++	if (ret < 0)
++		return;
++	ret = fusb302_i2c_read(chip, FUSB_REG_STATUS0, &status0);
++	if (ret < 0)
++		return;
++	ret = fusb302_i2c_read(chip, FUSB_REG_STATUS1A, &status1a);
++	if (ret < 0)
++		return;
++	ret = fusb302_i2c_read(chip, FUSB_REG_SWITCHES0, &sw0);
++	if (ret < 0)
++		return;
++	ret = fusb302_i2c_read(chip, FUSB_REG_MASK, &mask);
++	if (ret < 0)
++		return;
++
++	//FUSB_REG(FUSB_REG_POWER) // power control
++
++	const char* host_cur = "?";
++	switch ((ctl0 >> 2) & 3) {
++	case 0: host_cur = "none"; break;
++	case 1: host_cur = "80uA"; break;
++	case 2: host_cur = "160uA"; break;
++	case 3: host_cur = "330uA"; break;
++	}
++
++	const char* bc_lvl = "?";
++	switch (status0 & 3) {
++	case 0: bc_lvl = "0-200mV"; break;
++	case 1: bc_lvl = "200-660mV"; break;
++	case 2: bc_lvl = "660-1230mV"; break;
++	case 3: bc_lvl = ">1230mV"; break;
++	}
++
++	// status0
++	unsigned vbusok = !!(status0 & BIT(7));
++	unsigned activity = !!(status0 & BIT(6));
++	unsigned comp = !!(status0 & BIT(5));
++	unsigned wake = !!(status0 & BIT(2));
++
++	// measure
++	unsigned mdac = ((measure & 0x3f) + 1) * 42 * (measure & BIT(6) ? 10 : 1);
++
++	// status1a
++	unsigned togss = (status1a >> 3) & 7;
++	const char* togss_s = "?";
++	switch (togss) {
++	case 0: togss_s = "running"; break;
++	case 1: togss_s = "src1"; break;
++	case 2: togss_s = "src2"; break;
++	case 5: togss_s = "snk1"; break;
++	case 6: togss_s = "snk2"; break;
++	case 7: togss_s = "audio"; break;
++	}
++
++	// ctl2 print as is
++
++#define SW(n) (!!(sw0 & BIT(n)))
++
++	fusb302_log(chip, "state: cc(puen=%u%u vconn=%u%u meas=%u%u pdwn=%u%u) "
++		    "host_cur=%s mdac=%umV comp=%u bc_lvl=%s vbusok=%u act=%u "
++		    "wake=%u togss=%s ctl2=0x%02x mask=0x%02x",
++		    SW(6), SW(7), SW(4), SW(5), SW(2), SW(3), SW(0), SW(1),
++		    host_cur, mdac, comp, bc_lvl, vbusok, activity,
++		    wake, togss_s, ctl2, mask);
++}
++
+ static void fusb302_irq_work(struct work_struct *work)
+ {
+ 	struct fusb302_chip *chip = container_of(work, struct fusb302_chip,
+@@ -1607,6 +1685,7 @@ static void fusb302_irq_work(struct work_struct *work)
+ 	u8 interrupta;
+ 	u8 interruptb;
+ 	u8 status0;
++	u8 mda;
+ 	bool vbus_present;
+ 	bool comp_result;
+ 	bool intr_togdone;
+@@ -1632,9 +1711,10 @@ static void fusb302_irq_work(struct work_struct *work)
+ 	ret = fusb302_i2c_read(chip, FUSB_REG_STATUS0, &status0);
+ 	if (ret < 0)
+ 		goto done;
+-	fusb302_log(chip,
+-		    "IRQ: 0x%02x, a: 0x%02x, b: 0x%02x, status0: 0x%02x",
+-		    interrupt, interrupta, interruptb, status0);
++	fusb302_log(chip, "IRQ: 0x%02x, a: 0x%02x, b: 0x%02x",
++		    interrupt, interrupta, interruptb);
++
++	fusb302_print_state(chip);
+ 
+ 	if (interrupt & FUSB_REG_INTERRUPT_VBUSOK) {
+ 		vbus_present = !!(status0 & FUSB_REG_STATUS0_VBUSOK);
+@@ -1646,32 +1726,39 @@ static void fusb302_irq_work(struct work_struct *work)
+ 		}
+ 	}
+ 
+-	if ((interrupta & FUSB_REG_INTERRUPTA_TOGDONE) && intr_togdone) {
++	if (interrupta & FUSB_REG_INTERRUPTA_TOGDONE) {
+ 		fusb302_log(chip, "IRQ: TOGDONE");
+-		ret = fusb302_handle_togdone(chip);
+-		if (ret < 0) {
+-			fusb302_log(chip,
+-				    "handle togdone error, ret=%d", ret);
+-			goto done;
++		if (intr_togdone) {
++			ret = fusb302_handle_togdone(chip);
++			if (ret < 0) {
++				fusb302_log(chip,
++					    "handle togdone error, ret=%d", ret);
++				goto done;
++			}
+ 		}
+ 	}
+ 
+-	if ((interrupt & FUSB_REG_INTERRUPT_BC_LVL) && intr_bc_lvl) {
++	if (interrupt & FUSB_REG_INTERRUPT_BC_LVL) {
+ 		fusb302_log(chip, "IRQ: BC_LVL, handler pending");
+ 		/*
+ 		 * as BC_LVL interrupt can be affected by PD activity,
+ 		 * apply delay to for the handler to wait for the PD
+ 		 * signaling to finish.
+ 		 */
+-		mod_delayed_work(chip->wq, &chip->bc_lvl_handler,
+-				 msecs_to_jiffies(T_BC_LVL_DEBOUNCE_DELAY_MS));
++		if (intr_bc_lvl)
++			mod_delayed_work(chip->wq, &chip->bc_lvl_handler,
++					 msecs_to_jiffies(T_BC_LVL_DEBOUNCE_DELAY_MS));
+ 	}
+ 
+-	if ((interrupt & FUSB_REG_INTERRUPT_COMP_CHNG) && intr_comp_chng) {
++	if (interrupt & FUSB_REG_INTERRUPT_COMP_CHNG) {
++		ret = fusb302_i2c_read(chip, FUSB_REG_MEASURE, &mda);
++		if (ret < 0)
++			goto done;
++
+ 		comp_result = !!(status0 & FUSB_REG_STATUS0_COMP);
+-		fusb302_log(chip, "IRQ: COMP_CHNG, comp=%s",
+-			    str_true_false(comp_result));
+-		if (comp_result) {
++		fusb302_log(chip, "IRQ: COMP_CHNG, cc* %s mdac (%u mV)",
++			    comp_result ? ">" : "<", ((mda & 0x3f) + 1) * 42 * (mda & BIT(6) ? 10 : 1));
++		if (comp_result && intr_comp_chng) {
+ 			/* cc level > Rd_threshold, detach */
+ 			chip->cc1 = TYPEC_CC_OPEN;
+ 			chip->cc2 = TYPEC_CC_OPEN;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-fusb302-Retry-reading-of-CC-pins-status-if-activity-i.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-fusb302-Retry-reading-of-CC-pins-status-if-activity-i.patch
new file mode 100644
index 000000000000..0fcc83ba5051
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-fusb302-Retry-reading-of-CC-pins-status-if-activity-i.patch
@@ -0,0 +1,76 @@
+From b4c45356612f9188c1cdd64419c60f262921410b Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 23 Nov 2021 17:53:27 +0100
+Subject: usb: typec: fusb302: Retry reading of CC pins status if activity is
+ detected
+
+This is just for testing, to see if this ever happens. It should
+also help when this happens.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/typec/tcpm/fusb302.c | 34 ++++++++++++++++++++++++++++++--
+ 1 file changed, 32 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/usb/typec/tcpm/fusb302.c b/drivers/usb/typec/tcpm/fusb302.c
+index 2ee7222e531a..808bcf4cb24d 100644
+--- a/drivers/usb/typec/tcpm/fusb302.c
++++ b/drivers/usb/typec/tcpm/fusb302.c
+@@ -1317,6 +1317,36 @@ static int fusb302_handle_togdone_snk(struct fusb302_chip *chip,
+ 	return ret;
+ }
+ 
++static int fusb302_get_status0_stable(struct fusb302_chip *chip, u8 *status0)
++{
++	int ret, tries = 0;
++	u8 reg;
++
++try_again:
++	ret = fusb302_i2c_read(chip, FUSB_REG_STATUS0, &reg);
++	if (ret < 0)
++		return ret;
++
++	if (reg & FUSB_REG_STATUS0_ACTIVITY) {
++		fusb302_log(chip, "activity reading CC status");
++		if (++tries == 5) {
++			fusb302_log(chip, "failed to read stable status0 value");
++
++			/*
++			 * The best we can do is to return at least something.
++			 */
++			*status0 = reg;
++			return 0;
++		}
++
++		usleep_range(50, 100);
++		goto try_again;
++	}
++
++	*status0 = reg;
++	return 0;
++}
++
+ /* On error returns < 0, otherwise a typec_cc_status value */
+ static int fusb302_get_src_cc_status(struct fusb302_chip *chip,
+ 				     enum typec_cc_polarity cc_polarity,
+@@ -1344,7 +1374,7 @@ static int fusb302_get_src_cc_status(struct fusb302_chip *chip,
+ 		return ret;
+ 
+ 	usleep_range(50, 100);
+-	ret = fusb302_i2c_read(chip, FUSB_REG_STATUS0, &status0);
++	ret = fusb302_get_status0_stable(chip, &status0);
+ 	if (ret < 0)
+ 		return ret;
+ 
+@@ -1360,7 +1390,7 @@ static int fusb302_get_src_cc_status(struct fusb302_chip *chip,
+ 		return ret;
+ 
+ 	usleep_range(50, 100);
+-	ret = fusb302_i2c_read(chip, FUSB_REG_STATUS0, &status0);
++	ret = fusb302_get_status0_stable(chip, &status0);
+ 	if (ret < 0)
+ 		return ret;
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-fusb302-Set-the-current-before-enabling-pullups.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-fusb302-Set-the-current-before-enabling-pullups.patch
new file mode 100644
index 000000000000..7fcb8731cc89
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-fusb302-Set-the-current-before-enabling-pullups.patch
@@ -0,0 +1,50 @@
+From 9e2282a1cf5c500f3805b1cbfbedc550ea74f921 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 7 Nov 2021 19:28:27 +0100
+Subject: usb: typec: fusb302: Set the current before enabling pullups
+
+This seems more reasonable and should avoid short period of incorrect
+current setting being applied to CC pin.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/typec/tcpm/fusb302.c | 16 ++++++++--------
+ 1 file changed, 8 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/usb/typec/tcpm/fusb302.c b/drivers/usb/typec/tcpm/fusb302.c
+index 5d5e1a1ffefc..53fa863dfa96 100644
+--- a/drivers/usb/typec/tcpm/fusb302.c
++++ b/drivers/usb/typec/tcpm/fusb302.c
+@@ -636,6 +636,14 @@ static int tcpm_set_cc(struct tcpc_dev *dev, enum typec_cc_status cc)
+ 		goto done;
+ 	}
+ 
++	/* adjust current for SRC */
++	ret = fusb302_set_src_current(chip, cc_src_current[cc]);
++	if (ret < 0) {
++		fusb302_log(chip, "cannot set src current %s, ret=%d",
++			    typec_cc_status_name[cc], ret);
++		goto done;
++	}
++
+ 	ret = fusb302_i2c_mask_write(chip, FUSB_REG_SWITCHES0,
+ 				     switches0_mask, switches0_data);
+ 	if (ret < 0) {
+@@ -646,14 +654,6 @@ static int tcpm_set_cc(struct tcpc_dev *dev, enum typec_cc_status cc)
+ 	chip->cc1 = TYPEC_CC_OPEN;
+ 	chip->cc2 = TYPEC_CC_OPEN;
+ 
+-	/* adjust current for SRC */
+-	ret = fusb302_set_src_current(chip, cc_src_current[cc]);
+-	if (ret < 0) {
+-		fusb302_log(chip, "cannot set src current %s, ret=%d",
+-			    typec_cc_status_name[cc], ret);
+-		goto done;
+-	}
+-
+ 	/* enable/disable interrupts, BC_LVL for SNK and COMP_CHNG for SRC */
+ 	switch (cc) {
+ 	case TYPEC_CC_RP_DEF:
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-fusb302-Slightly-increase-wait-time-for-BC1.2-result.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-fusb302-Slightly-increase-wait-time-for-BC1.2-result.patch
new file mode 100644
index 000000000000..9d28fb2866c8
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-fusb302-Slightly-increase-wait-time-for-BC1.2-result.patch
@@ -0,0 +1,33 @@
+From edb5ad67b7842d4fc9758e2cdb010a7835089d50 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 30 Jan 2022 23:46:37 +0100
+Subject: usb: typec: fusb302: Slightly increase wait time for BC1.2 result
+
+This is not strictly necessary, but it should not hurt. Looking at
+kernel log timing, the BC1.2 detection completion time and this
+timeout are quite tight. This adds some headspace just in case.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/typec/tcpm/fusb302.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/usb/typec/tcpm/fusb302.c b/drivers/usb/typec/tcpm/fusb302.c
+index f15c63d3a8f4..5d5e1a1ffefc 100644
+--- a/drivers/usb/typec/tcpm/fusb302.c
++++ b/drivers/usb/typec/tcpm/fusb302.c
+@@ -446,9 +446,9 @@ static int tcpm_get_current_limit(struct tcpc_dev *dev)
+ 
+ 	/*
+ 	 * USB2 Charger detection may still be in progress when we get here,
+-	 * this can take upto 600ms, wait 800ms max.
++	 * this can take upto 600ms, wait 1000ms max.
+ 	 */
+-	timeout = jiffies + msecs_to_jiffies(800);
++	timeout = jiffies + msecs_to_jiffies(1000);
+ 	do {
+ 		if (extcon_get_state(chip->extcon, EXTCON_CHG_USB_SDP) == 1)
+ 			current_limit = 500;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-fusb302-Update-VBUS-state-even-if-VBUS-interrupt-is-n.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-fusb302-Update-VBUS-state-even-if-VBUS-interrupt-is-n.patch
new file mode 100644
index 000000000000..b040b79cafb3
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-fusb302-Update-VBUS-state-even-if-VBUS-interrupt-is-n.patch
@@ -0,0 +1,43 @@
+From 190f76e5c4c74c2cff9dc8cec5158712638f68eb Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 23 Nov 2021 17:57:06 +0100
+Subject: usb: typec: fusb302: Update VBUS state even if VBUS interrupt is not
+ triggered
+
+This seems to improve robustness.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/typec/tcpm/fusb302.c | 14 ++++++++------
+ 1 file changed, 8 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/usb/typec/tcpm/fusb302.c b/drivers/usb/typec/tcpm/fusb302.c
+index c30f93ec78fa..16c3f8d94a9d 100644
+--- a/drivers/usb/typec/tcpm/fusb302.c
++++ b/drivers/usb/typec/tcpm/fusb302.c
+@@ -1716,14 +1716,16 @@ static void fusb302_irq_work(struct work_struct *work)
+ 
+ 	fusb302_print_state(chip);
+ 
+-	if (interrupt & FUSB_REG_INTERRUPT_VBUSOK) {
+-		vbus_present = !!(status0 & FUSB_REG_STATUS0_VBUSOK);
++	vbus_present = !!(status0 & FUSB_REG_STATUS0_VBUSOK);
++	if (interrupt & FUSB_REG_INTERRUPT_VBUSOK)
+ 		fusb302_log(chip, "IRQ: VBUS_OK, vbus=%s",
+ 			    str_on_off(vbus_present));
+-		if (vbus_present != chip->vbus_present) {
+-			chip->vbus_present = vbus_present;
+-			tcpm_vbus_change(chip->tcpm_port);
+-		}
++	if (vbus_present != chip->vbus_present) {
++		chip->vbus_present = vbus_present;
++		if (!(interrupt & FUSB_REG_INTERRUPT_VBUSOK))
++		fusb302_log(chip, "IRQ: VBUS changed without interrupt, vbus=%s",
++			    str_on_off(vbus_present));
++		tcpm_vbus_change(chip->tcpm_port);
+ 	}
+ 
+ 	if (interrupta & FUSB_REG_INTERRUPTA_TOGDONE) {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-tcpm-Fix-PD-devices-capabilities-registration.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-tcpm-Fix-PD-devices-capabilities-registration.patch
new file mode 100644
index 000000000000..958cd0d36768
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-tcpm-Fix-PD-devices-capabilities-registration.patch
@@ -0,0 +1,95 @@
+From 6330c7bba3992991c37f3204828293a3cda064a9 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sat, 18 Feb 2023 00:38:44 +0100
+Subject: usb: typec: tcpm: Fix PD devices/capabilities registration
+
+Unregister caps before registering them. Store NULL to the struct
+if registration fails, so that next attempt can succeed.
+
+Fixes "sysfs: cannot create duplicate filename
+'/devices/virtual/usb_power_delivery/pd1/source-capabilities'" error.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/typec/tcpm/tcpm.c | 37 +++++++++++++++++++++++++++--------
+ 1 file changed, 29 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/usb/typec/tcpm/tcpm.c b/drivers/usb/typec/tcpm/tcpm.c
+index 01e1a2c066c7..9f2e376aafd6 100644
+--- a/drivers/usb/typec/tcpm/tcpm.c
++++ b/drivers/usb/typec/tcpm/tcpm.c
+@@ -3057,15 +3057,22 @@ static int tcpm_register_source_caps(struct tcpm_port *port)
+ 	struct usb_power_delivery_desc desc = { port->negotiated_rev };
+ 	struct usb_power_delivery_capabilities_desc caps = { };
+ 	struct usb_power_delivery_capabilities *cap;
++	struct usb_power_delivery *partner_pd;
++
++	if (!port->partner_pd) {
++		partner_pd = usb_power_delivery_register(NULL, &desc);
++		if (IS_ERR(partner_pd))
++			return PTR_ERR(partner_pd);
+ 
+-	if (!port->partner_pd)
+-		port->partner_pd = usb_power_delivery_register(NULL, &desc);
+-	if (IS_ERR(port->partner_pd))
+-		return PTR_ERR(port->partner_pd);
++		port->partner_pd = partner_pd;
++	}
+ 
+ 	memcpy(caps.pdo, port->source_caps, sizeof(u32) * port->nr_source_caps);
+ 	caps.role = TYPEC_SOURCE;
+ 
++	usb_power_delivery_unregister_capabilities(port->partner_source_caps);
++	port->partner_source_caps = NULL;
++
+ 	cap = usb_power_delivery_register_capabilities(port->partner_pd, &caps);
+ 	if (IS_ERR(cap))
+ 		return PTR_ERR(cap);
+@@ -3080,15 +3087,22 @@ static int tcpm_register_sink_caps(struct tcpm_port *port)
+ 	struct usb_power_delivery_desc desc = { port->negotiated_rev };
+ 	struct usb_power_delivery_capabilities_desc caps = { };
+ 	struct usb_power_delivery_capabilities *cap;
++	struct usb_power_delivery *partner_pd;
++
++	if (!port->partner_pd) {
++		partner_pd = usb_power_delivery_register(NULL, &desc);
++		if (IS_ERR(partner_pd))
++			return PTR_ERR(partner_pd);
+ 
+-	if (!port->partner_pd)
+-		port->partner_pd = usb_power_delivery_register(NULL, &desc);
+-	if (IS_ERR(port->partner_pd))
+-		return PTR_ERR(port->partner_pd);
++		port->partner_pd = partner_pd;
++	}
+ 
+ 	memcpy(caps.pdo, port->sink_caps, sizeof(u32) * port->nr_sink_caps);
+ 	caps.role = TYPEC_SINK;
+ 
++	usb_power_delivery_unregister_capabilities(port->partner_sink_caps);
++	port->partner_sink_caps = NULL;
++
+ 	cap = usb_power_delivery_register_capabilities(port->partner_pd, &caps);
+ 	if (IS_ERR(cap))
+ 		return PTR_ERR(cap);
+@@ -7098,10 +7112,17 @@ static int tcpm_port_register_pd(struct tcpm_port *port)
+ 		port->pds[i] = usb_power_delivery_register(port->dev, &desc);
+ 		if (IS_ERR(port->pds[i])) {
+ 			ret = PTR_ERR(port->pds[i]);
++			port->pds[i] = NULL;
+ 			goto err_unregister;
+ 		}
+ 		port->pd_list[i]->pd = port->pds[i];
+ 
++		usb_power_delivery_unregister_capabilities(port->pd_list[i]->source_cap);
++		port->pd_list[i]->source_cap = NULL;
++
++		usb_power_delivery_unregister_capabilities(port->pd_list[i]->sink_cap);
++		port->pd_list[i]->sink_cap = NULL;
++
+ 		if (port->pd_list[i]->source_desc.pdo[0]) {
+ 			cap = usb_power_delivery_register_capabilities(port->pds[i],
+ 								&port->pd_list[i]->source_desc);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-tcpm-Improve-logs.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-tcpm-Improve-logs.patch
new file mode 100644
index 000000000000..d85ac5da37c7
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-tcpm-Improve-logs.patch
@@ -0,0 +1,64 @@
+From aa7b2907c1dd687c07d1a8245d7c01d1b05f4aa2 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 23 Nov 2021 17:58:05 +0100
+Subject: usb: typec: tcpm: Improve logs
+
+This adds clarity to debugging.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/typec/tcpm/tcpm.c | 15 +++++++++++----
+ 1 file changed, 11 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/usb/typec/tcpm/tcpm.c b/drivers/usb/typec/tcpm/tcpm.c
+index 9f2e376aafd6..d44e12fb2a53 100644
+--- a/drivers/usb/typec/tcpm/tcpm.c
++++ b/drivers/usb/typec/tcpm/tcpm.c
+@@ -986,10 +986,13 @@ static int tcpm_pd_transmit(struct tcpm_port *port,
+ 		break;
+ 	}
+ 
+-	if (msg)
++	if (msg) {
+ 		tcpm_log(port, "PD TX, header: %#x", le16_to_cpu(msg->header));
+-	else
++		for (ret = 0; ret < pd_header_cnt_le(msg->header); ret++)
++			tcpm_log(port, "  tx payload[%d]: %#x", ret, le32_to_cpu(msg->payload[ret]));
++	} else {
+ 		tcpm_log(port, "PD TX, type: %#x", tx_sop_type);
++	}
+ 
+ 	reinit_completion(&port->tx_complete);
+ 	ret = port->tcpc->pd_transmit(port->tcpc, tx_sop_type, msg, negotiated_rev);
+@@ -3740,6 +3743,10 @@ void tcpm_pd_receive(struct tcpm_port *port, const struct pd_message *msg,
+ 		     enum tcpm_transmit_type rx_sop_type)
+ {
+ 	struct pd_rx_event *event;
++	int ret;
++
++	for (ret = 0; ret < pd_header_cnt_le(msg->header); ret++)
++		tcpm_log(port, "  rx payload[%d]: %#x", ret, le32_to_cpu(msg->payload[ret]));
+ 
+ 	event = kzalloc(sizeof(*event), GFP_ATOMIC);
+ 	if (!event)
+@@ -6043,7 +6050,7 @@ static void _tcpm_cc_change(struct tcpm_port *port, enum typec_cc_status cc1,
+ 
+ static void _tcpm_pd_vbus_on(struct tcpm_port *port)
+ {
+-	tcpm_log_force(port, "VBUS on");
++	tcpm_log_force(port, "VBUS event received: on");
+ 	port->vbus_present = true;
+ 	/*
+ 	 * When vbus_present is true i.e. Voltage at VBUS is greater than VSAFE5V implicitly
+@@ -6133,7 +6140,7 @@ static void _tcpm_pd_vbus_on(struct tcpm_port *port)
+ 
+ static void _tcpm_pd_vbus_off(struct tcpm_port *port)
+ {
+-	tcpm_log_force(port, "VBUS off");
++	tcpm_log_force(port, "VBUS event received: off");
+ 	port->vbus_present = false;
+ 	port->vbus_never_low = false;
+ 	switch (port->state) {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-tcpm-Unregister-altmodes-before-registering-new-ones.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-tcpm-Unregister-altmodes-before-registering-new-ones.patch
new file mode 100644
index 000000000000..c7ace7157842
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-tcpm-Unregister-altmodes-before-registering-new-ones.patch
@@ -0,0 +1,52 @@
+From c02b2e7f1fc2126867ea3500684704c3a7006fd1 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sun, 14 Aug 2022 16:23:28 +0200
+Subject: usb: typec: tcpm: Unregister altmodes before registering new ones
+
+Just in case there are already altmodes registered. Otherwise the
+kernel will fail with:
+
+[50554.467172] sysfs: cannot create duplicate filename '/bus/typec/devices/port0-partner.0'
+[50554.467198] CPU: 2 PID: 897 Comm: 4-0022 Tainted: G         C        5.18.15-1-MANJARO-ARM #1
+[50554.467208] Hardware name: Pine64 PinePhonePro (DT)
+[50554.467214] Call trace:
+[50554.467218]  dump_backtrace.part.0+0xcc/0xe0
+[50554.467241]  show_stack+0x18/0x6c
+[50554.467249]  dump_stack_lvl+0x64/0x80
+[50554.467262]  dump_stack+0x18/0x34
+[50554.467270]  sysfs_warn_dup+0x60/0x7c
+[50554.467279]  sysfs_do_create_link_sd+0xf0/0x100
+[50554.467286]  sysfs_create_link+0x24/0x44
+[50554.467292]  bus_add_device+0x64/0x120
+[50554.467304]  device_add+0x320/0x890
+[50554.467312]  device_register+0x20/0x30
+[50554.467318]  typec_register_altmode+0x1e4/0x35c
+[50554.467330]  typec_partner_register_altmode+0x10/0x20
+[50554.467339]  tcpm_pd_rx_handler+0x1804/0x18e0
+[50554.467346]  kthread_worker_fn+0xa0/0x180
+[50554.467357]  kthread+0x108/0x10c
+[50554.467364]  ret_from_fork+0x10/0x20
+[50554.467528] typec port0-partner: failed to register alternate mode (-17)
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/typec/tcpm/tcpm.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/usb/typec/tcpm/tcpm.c b/drivers/usb/typec/tcpm/tcpm.c
+index 2c92996954b2..01e1a2c066c7 100644
+--- a/drivers/usb/typec/tcpm/tcpm.c
++++ b/drivers/usb/typec/tcpm/tcpm.c
+@@ -1798,6 +1798,9 @@ static void tcpm_register_partner_altmodes(struct tcpm_port *port)
+ 		return;
+ 
+ 	for (i = 0; i < modep->altmodes; i++) {
++		typec_unregister_altmode(port->partner_altmode[i]);
++		port->partner_altmode[i] = NULL;
++
+ 		altmode = typec_partner_register_altmode(port->partner,
+ 						&modep->altmode_desc[i]);
+ 		if (IS_ERR(altmode)) {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-typec-extcon-Add-typec-extcon-bridge-driver.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-typec-extcon-Add-typec-extcon-bridge-driver.patch
new file mode 100644
index 000000000000..9a3d19ff2c75
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-typec-extcon-Add-typec-extcon-bridge-driver.patch
@@ -0,0 +1,384 @@
+From c51b4cd25c8224ea7667def456cb55f18d8e5d5a Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Sun, 7 Nov 2021 19:24:40 +0100
+Subject: usb: typec: typec-extcon: Add typec -> extcon bridge driver
+
+This bridge connects standard Type C port interfaces for controling
+muxes, switches and usb roles to muxes, switches and usb role
+drivers controlled via extcon interface.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/typec/Kconfig        |   7 +
+ drivers/usb/typec/Makefile       |   1 +
+ drivers/usb/typec/typec-extcon.c | 330 +++++++++++++++++++++++++++++++
+ 3 files changed, 338 insertions(+)
+ create mode 100644 drivers/usb/typec/typec-extcon.c
+
+diff --git a/drivers/usb/typec/Kconfig b/drivers/usb/typec/Kconfig
+index 982b7c444a1f..9913435a0fd9 100644
+--- a/drivers/usb/typec/Kconfig
++++ b/drivers/usb/typec/Kconfig
+@@ -122,6 +122,13 @@ config TYPEC_WUSB3801
+ 	  If you choose to build this driver as a dynamically linked module, the
+ 	  module will be called wusb3801.ko.
+ 
++config TYPEC_EXTCON
++	tristate "Type-C switch/mux -> extcon interface bridge driver"
++	depends on USB_ROLE_SWITCH
++	help
++	  Say Y or M here if your system needs bridging between typec class
++	  and extcon interfaces.
++
+ source "drivers/usb/typec/mux/Kconfig"
+ 
+ source "drivers/usb/typec/altmodes/Kconfig"
+diff --git a/drivers/usb/typec/Makefile b/drivers/usb/typec/Makefile
+index 3f8ff94ad294..0b2d1d251c53 100644
+--- a/drivers/usb/typec/Makefile
++++ b/drivers/usb/typec/Makefile
+@@ -12,4 +12,5 @@ obj-$(CONFIG_TYPEC_HD3SS3220)	+= hd3ss3220.o
+ obj-$(CONFIG_TYPEC_STUSB160X) 	+= stusb160x.o
+ obj-$(CONFIG_TYPEC_RT1719)	+= rt1719.o
+ obj-$(CONFIG_TYPEC_WUSB3801)	+= wusb3801.o
++obj-$(CONFIG_TYPEC_EXTCON)	+= typec-extcon.o
+ obj-$(CONFIG_TYPEC)		+= mux/
+diff --git a/drivers/usb/typec/typec-extcon.c b/drivers/usb/typec/typec-extcon.c
+new file mode 100644
+index 000000000000..e09cd7a28c24
+--- /dev/null
++++ b/drivers/usb/typec/typec-extcon.c
+@@ -0,0 +1,330 @@
++/*
++ * typec -> extcon bridge
++ * Copyright (c) 2021 Ondřej Jirman <megi@xff.cz>
++ *
++ * This driver bridges standard type-c interfaces to drivers that
++ * expect extcon interface.
++ */
++
++#include <linux/delay.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/power_supply.h>
++#include <linux/platform_device.h>
++#include <linux/usb/pd.h>
++#include <linux/usb/role.h>
++#include <linux/usb/typec.h>
++#include <linux/usb/typec_dp.h>
++#include <linux/usb/typec_mux.h>
++#include <linux/extcon-provider.h>
++
++struct typec_extcon {
++        struct device *dev;
++
++	/* consumers */
++	struct usb_role_switch *role_sw;
++        struct typec_switch_dev *sw;
++        struct typec_mux_dev *mux;
++
++	/* providers */
++	struct extcon_dev *extcon;
++	struct notifier_block extcon_nb;
++
++	/* cached state from typec controller */
++	enum usb_role role;
++	enum typec_orientation orientation;
++	struct typec_altmode alt;
++	unsigned long mode;
++	bool has_alt;
++	struct mutex lock;
++};
++
++static const unsigned int typec_extcon_cable[] = {
++	EXTCON_DISP_DP,
++
++	EXTCON_USB,
++	EXTCON_USB_HOST,
++
++	EXTCON_CHG_USB_SDP,
++	EXTCON_CHG_USB_CDP,
++	EXTCON_CHG_USB_DCP,
++	EXTCON_CHG_USB_ACA,
++
++	EXTCON_NONE,
++};
++
++static void typec_extcon_set_cable(struct typec_extcon *tce, int id, bool on,
++				   union extcon_property_value prop_ss,
++				   union extcon_property_value prop_or)
++{
++	union extcon_property_value cur_ss, cur_or;
++	bool prop_diff = false;
++	int ret;
++
++	ret = extcon_get_property(tce->extcon, id,
++				  EXTCON_PROP_USB_SS, &cur_ss);
++	if (ret || cur_ss.intval != prop_ss.intval)
++		prop_diff = true;
++
++	ret = extcon_get_property(tce->extcon, id,
++				  EXTCON_PROP_USB_TYPEC_POLARITY, &cur_or);
++	if (ret || cur_or.intval != prop_or.intval)
++		prop_diff = true;
++
++	if (!on && extcon_get_state(tce->extcon, id)) {
++		extcon_set_state_sync(tce->extcon, id, false);
++	} else if (on && (!extcon_get_state(tce->extcon, id) || prop_diff)) {
++		extcon_set_state(tce->extcon, id, true);
++		extcon_set_property(tce->extcon, id,
++				    EXTCON_PROP_USB_SS, prop_ss);
++		extcon_set_property(tce->extcon, id,
++				    EXTCON_PROP_USB_TYPEC_POLARITY, prop_or);
++		extcon_sync(tce->extcon, id);
++	}
++}
++
++static int typec_extcon_sync_extcon(struct typec_extcon *tce)
++{
++	union extcon_property_value prop_ss, prop_or;
++	bool has_dp = false;
++
++        mutex_lock(&tce->lock);
++
++	/* connector is disconnected */
++	if (tce->orientation == TYPEC_ORIENTATION_NONE) {
++		typec_extcon_set_cable(tce, EXTCON_USB, false, prop_ss, prop_or);
++		typec_extcon_set_cable(tce, EXTCON_USB_HOST, false, prop_ss, prop_or);
++		typec_extcon_set_cable(tce, EXTCON_DISP_DP, false, prop_ss, prop_or);
++
++                goto out_unlock;
++	}
++
++	prop_or.intval = tce->orientation == TYPEC_ORIENTATION_NORMAL ? 0 : 1;
++	prop_ss.intval = 0;
++
++	if (tce->has_alt && tce->alt.svid == USB_TYPEC_DP_SID) {
++		switch (tce->mode) {
++		case TYPEC_STATE_SAFE:
++			break;
++		case TYPEC_DP_STATE_C:
++		case TYPEC_DP_STATE_E:
++			has_dp = true;
++			break;
++		case TYPEC_DP_STATE_D:
++			has_dp = true;
++			fallthrough;
++		case TYPEC_STATE_USB:
++			prop_ss.intval = 1;
++			break;
++		default:
++			dev_err(tce->dev, "unhandled mux mode=%lu\n", tce->mode);
++			break;
++		}
++	}
++
++	typec_extcon_set_cable(tce, EXTCON_USB,
++			tce->role == USB_ROLE_DEVICE, prop_ss, prop_or);
++	typec_extcon_set_cable(tce, EXTCON_USB_HOST,
++			tce->role == USB_ROLE_HOST, prop_ss, prop_or);
++
++	typec_extcon_set_cable(tce, EXTCON_DISP_DP, has_dp, prop_ss, prop_or);
++
++out_unlock:
++	mutex_unlock(&tce->lock);
++	return 0;
++}
++
++static int typec_extcon_sw_set(struct typec_switch_dev *sw,
++			       enum typec_orientation orientation)
++{
++        struct typec_extcon *tce = typec_switch_get_drvdata(sw);
++
++	dev_dbg(tce->dev, "SW SET: orientation=%d\n", orientation);
++
++        mutex_lock(&tce->lock);
++	tce->orientation = orientation;
++        mutex_unlock(&tce->lock);
++
++	typec_extcon_sync_extcon(tce);
++
++        return 0;
++}
++
++static int typec_extcon_mux_set(struct typec_mux_dev *mux,
++				struct typec_mux_state *state)
++{
++        struct typec_extcon *tce = typec_mux_get_drvdata(mux);
++	struct typec_altmode *alt = state->alt;
++
++	dev_dbg(tce->dev, "MUX SET: state->mode=%lu\n", state->mode);
++	if (alt)
++		dev_dbg(tce->dev, "      ...alt: svid=%04hx mode=%d vdo=%08x active=%u\n",
++			alt->svid, alt->mode, alt->vdo, alt->active);
++
++        mutex_lock(&tce->lock);
++	tce->mode = state->mode;
++	tce->has_alt = alt != NULL;
++        if (alt)
++		tce->alt = *alt;
++	mutex_unlock(&tce->lock);
++
++	typec_extcon_sync_extcon(tce);
++
++        return 0;
++}
++
++static int typec_extcon_usb_set_role(struct usb_role_switch *sw,
++				     enum usb_role role)
++{
++        struct typec_extcon *tce = usb_role_switch_get_drvdata(sw);
++
++	dev_dbg(tce->dev, "ROLE SET: role=%d\n", role);
++
++        mutex_lock(&tce->lock);
++	tce->role = role;
++	mutex_unlock(&tce->lock);
++
++	typec_extcon_sync_extcon(tce);
++
++        return 0;
++}
++
++static int typec_extcon_notifier(struct notifier_block *nb,
++					 unsigned long action, void *data)
++{
++	struct typec_extcon *tce = container_of(nb, struct typec_extcon, extcon_nb);
++
++	bool sdp = extcon_get_state(tce->extcon, EXTCON_CHG_USB_SDP);
++	bool cdp = extcon_get_state(tce->extcon, EXTCON_CHG_USB_CDP);
++	bool dcp = extcon_get_state(tce->extcon, EXTCON_CHG_USB_DCP);
++	bool usb = extcon_get_state(tce->extcon, EXTCON_USB);
++	bool usb_host = extcon_get_state(tce->extcon, EXTCON_USB_HOST);
++	bool dp = extcon_get_state(tce->extcon, EXTCON_DISP_DP);
++
++	dev_info(tce->dev, "extcon changed sdp=%d cdp=%d dcp=%d usb=%d usb_host=%d dp=%d\n",
++		 sdp, cdp, dcp, usb, usb_host, dp);
++
++	return NOTIFY_OK;
++}
++
++static int typec_extcon_probe(struct platform_device *pdev)
++{
++        struct typec_switch_desc sw_desc = { };
++        struct typec_mux_desc mux_desc = { };
++        struct usb_role_switch_desc role_desc = { };
++        struct device *dev = &pdev->dev;
++        struct typec_extcon *tce;
++        int ret = 0;
++
++        tce = devm_kzalloc(dev, sizeof(*tce), GFP_KERNEL);
++        if (!tce)
++                return -ENOMEM;
++
++        tce->dev = &pdev->dev;
++	mutex_init(&tce->lock);
++	tce->mode = TYPEC_STATE_SAFE;
++
++	sw_desc.drvdata = tce;
++	sw_desc.fwnode = dev->fwnode;
++	sw_desc.set = typec_extcon_sw_set;
++
++	tce->sw = typec_switch_register(dev, &sw_desc);
++	if (IS_ERR(tce->sw))
++		return dev_err_probe(dev, PTR_ERR(tce->sw),
++				     "Error registering typec switch\n");
++
++	mux_desc.drvdata = tce;
++	mux_desc.fwnode = dev->fwnode;
++	mux_desc.set = typec_extcon_mux_set;
++
++	tce->mux = typec_mux_register(dev, &mux_desc);
++	if (IS_ERR(tce->mux)) {
++		ret = dev_err_probe(dev, PTR_ERR(tce->mux),
++				    "Error registering typec mux\n");
++		goto err_sw;
++	}
++
++	role_desc.driver_data = tce;
++	role_desc.fwnode = dev->fwnode;
++	role_desc.name = fwnode_get_name(dev->fwnode);
++	role_desc.set = typec_extcon_usb_set_role;
++
++	tce->role_sw = usb_role_switch_register(dev, &role_desc);
++	if (IS_ERR(tce->role_sw)) {
++		ret = dev_err_probe(dev, PTR_ERR(tce->role_sw),
++				    "Error registering USB role switch\n");
++		goto err_mux;
++	}
++
++	tce->extcon = devm_extcon_dev_allocate(dev, typec_extcon_cable);
++	if (IS_ERR(tce->extcon)) {
++		ret = PTR_ERR(tce->extcon);
++		goto err_role;
++	}
++
++	ret = devm_extcon_dev_register(dev, tce->extcon);
++	if (ret) {
++		ret = dev_err_probe(dev, ret, "failed to register extcon device\n");
++		goto err_role;
++	}
++
++	extcon_set_property_capability(tce->extcon, EXTCON_USB,
++				       EXTCON_PROP_USB_SS);
++	extcon_set_property_capability(tce->extcon, EXTCON_USB,
++				       EXTCON_PROP_USB_TYPEC_POLARITY);
++	extcon_set_property_capability(tce->extcon, EXTCON_USB_HOST,
++				       EXTCON_PROP_USB_SS);
++	extcon_set_property_capability(tce->extcon, EXTCON_USB_HOST,
++				       EXTCON_PROP_USB_TYPEC_POLARITY);
++	extcon_set_property_capability(tce->extcon, EXTCON_DISP_DP,
++				       EXTCON_PROP_USB_SS);
++	extcon_set_property_capability(tce->extcon, EXTCON_DISP_DP,
++				       EXTCON_PROP_USB_TYPEC_POLARITY);
++
++	tce->extcon_nb.notifier_call = typec_extcon_notifier;
++	ret = devm_extcon_register_notifier_all(dev, tce->extcon, &tce->extcon_nb);
++	if (ret) {
++		dev_err_probe(dev, ret, "Failed to register extcon notifier\n");
++		goto err_role;
++	}
++
++	return 0;
++
++err_role:
++	usb_role_switch_unregister(tce->role_sw);
++err_mux:
++	typec_mux_unregister(tce->mux);
++err_sw:
++	typec_switch_unregister(tce->sw);
++	return ret;
++}
++
++static void typec_extcon_remove(struct platform_device *pdev)
++{
++        struct typec_extcon *tce = platform_get_drvdata(pdev);
++
++	usb_role_switch_unregister(tce->role_sw);
++	typec_mux_unregister(tce->mux);
++	typec_switch_unregister(tce->sw);
++}
++
++static struct of_device_id typec_extcon_of_match_table[] = {
++        { .compatible = "linux,typec-extcon-bridge" },
++        { },
++};
++MODULE_DEVICE_TABLE(of, typec_extcon_of_match_table);
++
++static struct platform_driver typec_extcon_driver = {
++        .driver = {
++                .name = "typec-extcon",
++                .of_match_table = typec_extcon_of_match_table,
++        },
++        .probe = typec_extcon_probe,
++        .remove = typec_extcon_remove,
++};
++
++module_platform_driver(typec_extcon_driver);
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Ondrej Jirman <megi@xff.cz>");
++MODULE_DESCRIPTION("typec -> extcon bridge driver");
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-typec-extcon-Allow-to-force-reset-on-each-mux-change.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-typec-extcon-Allow-to-force-reset-on-each-mux-change.patch
new file mode 100644
index 000000000000..d6fb880d0a1b
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-typec-extcon-Allow-to-force-reset-on-each-mux-change.patch
@@ -0,0 +1,48 @@
+From 0ef3b1cee239d5a9ae7bc7e8ad075ac1fef5ed84 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Thu, 9 Feb 2023 20:33:50 +0100
+Subject: usb: typec: typec-extcon: Allow to force reset on each mux change
+
+This may help with some Alt-DP USB adapters.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/typec/typec-extcon.c | 15 +++++++++++++++
+ 1 file changed, 15 insertions(+)
+
+diff --git a/drivers/usb/typec/typec-extcon.c b/drivers/usb/typec/typec-extcon.c
+index f617e90b71a0..81fc4114bc59 100644
+--- a/drivers/usb/typec/typec-extcon.c
++++ b/drivers/usb/typec/typec-extcon.c
+@@ -19,6 +19,10 @@
+ #include <linux/usb/typec_mux.h>
+ #include <linux/extcon-provider.h>
+ 
++static bool reset_on_mux;
++module_param(reset_on_mux, bool, S_IRUGO | S_IWUSR);
++MODULE_PARM_DESC(reset_on_mux, "Set DP=0 on each type-c mux change");
++
+ struct typec_extcon {
+         struct device *dev;
+ 
+@@ -162,6 +166,17 @@ static int typec_extcon_mux_set(struct typec_mux_dev *mux,
+ 		dev_dbg(tce->dev, "      ...alt: svid=%04hx mode=%d vdo=%08x active=%u\n",
+ 			alt->svid, alt->mode, alt->vdo, alt->active);
+ 
++        mutex_lock(&tce->lock);
++	if (reset_on_mux && alt != NULL && tce->has_alt) {
++		tce->mode = state->mode;
++		tce->has_alt = false;
++		mutex_unlock(&tce->lock);
++
++		typec_extcon_sync_extcon(tce);
++	} else {
++		mutex_unlock(&tce->lock);
++	}
++
+         mutex_lock(&tce->lock);
+ 	tce->mode = state->mode;
+ 	tce->has_alt = alt != NULL;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-typec-extcon-Enable-debugging-for-now.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-typec-extcon-Enable-debugging-for-now.patch
new file mode 100644
index 000000000000..2faaec70634e
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/usb-typec-typec-extcon-Enable-debugging-for-now.patch
@@ -0,0 +1,25 @@
+From 169c2c30b74c8ecb334823420b30da6030e48247 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Wed, 23 Mar 2022 14:21:34 +0100
+Subject: usb: typec: typec-extcon: Enable debugging for now
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/usb/typec/typec-extcon.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/usb/typec/typec-extcon.c b/drivers/usb/typec/typec-extcon.c
+index e09cd7a28c24..f617e90b71a0 100644
+--- a/drivers/usb/typec/typec-extcon.c
++++ b/drivers/usb/typec/typec-extcon.c
+@@ -5,6 +5,7 @@
+  * This driver bridges standard type-c interfaces to drivers that
+  * expect extcon interface.
+  */
++#define DEBUG
+ 
+ #include <linux/delay.h>
+ #include <linux/kernel.h>
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/video-fbdev-eInk-display-driver-for-A13-based-PocketBooks.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/video-fbdev-eInk-display-driver-for-A13-based-PocketBooks.patch
new file mode 100644
index 000000000000..7f9406459e29
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/video-fbdev-eInk-display-driver-for-A13-based-PocketBooks.patch
@@ -0,0 +1,1274 @@
+From 1a8de735c0b99b2d9aa538603431e63bf121bf0a Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Tue, 24 Sep 2019 17:53:02 +0200
+Subject: video: fbdev: eInk display driver for A13 based PocketBooks
+
+This driver uses DEBE and TCON0 to bitbang the ED060XD4 eInk panel
+protocol on LCD data pins. There's no other sane way to do it,
+as PocketBook e-book reader was designed this way.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/video/fbdev/Kconfig           |   12 +
+ drivers/video/fbdev/Makefile          |    4 +
+ drivers/video/fbdev/sun5i-eink-neon.c |   49 ++
+ drivers/video/fbdev/sun5i-eink.c      | 1156 +++++++++++++++++++++++++
+ 4 files changed, 1221 insertions(+)
+ create mode 100644 drivers/video/fbdev/sun5i-eink-neon.c
+ create mode 100644 drivers/video/fbdev/sun5i-eink.c
+
+diff --git a/drivers/video/fbdev/Kconfig b/drivers/video/fbdev/Kconfig
+index 55c6686f091e..5685c65da340 100644
+--- a/drivers/video/fbdev/Kconfig
++++ b/drivers/video/fbdev/Kconfig
+@@ -658,6 +658,18 @@ config FB_ATMEL
+ 	help
+ 	  This enables support for the AT91 LCD Controller.
+ 
++config FB_SUN5I_EINK
++	tristate "eInk display Framebuffer Support (A13 based eBook readers)"
++	depends on FB
++	select FB_MODE_HELPERS
++	select FB_CFB_FILLRECT
++	select FB_CFB_COPYAREA
++	select FB_CFB_IMAGEBLIT
++	select BITREVERSE
++	help
++	  This driver supports PocketBook Touch Lux 3 e-paper display.
++
++
+ config FB_NVIDIA
+ 	tristate "nVidia Framebuffer Support"
+ 	depends on FB && PCI
+diff --git a/drivers/video/fbdev/Makefile b/drivers/video/fbdev/Makefile
+index b3d12f977c06..36026f5adf6e 100644
+--- a/drivers/video/fbdev/Makefile
++++ b/drivers/video/fbdev/Makefile
+@@ -126,3 +126,7 @@ obj-$(CONFIG_FB_SIMPLE)           += simplefb.o
+ 
+ # the test framebuffer is last
+ obj-$(CONFIG_FB_VIRTUAL)          += vfb.o
++
++obj-$(CONFIG_FB_SUN5I_EINK)       += sun5ieink.o
++sun5ieink-objs = sun5i-eink.o sun5i-eink-neon.o
++CFLAGS_sun5i-eink-neon.o	  += -march=armv7-a -mfloat-abi=softfp -mfpu=neon -ffreestanding -isystem $(shell $(CC) -print-file-name=include)
+diff --git a/drivers/video/fbdev/sun5i-eink-neon.c b/drivers/video/fbdev/sun5i-eink-neon.c
+new file mode 100644
+index 000000000000..9e2386fd91ea
+--- /dev/null
++++ b/drivers/video/fbdev/sun5i-eink-neon.c
+@@ -0,0 +1,49 @@
++#include <linux/export.h>
++#include <linux/compiler.h>
++#include <linux/types.h>
++#include <arm_neon.h>
++
++void eink_ctlstream_fill_data_neon(u32* cmd, u8* fb, int stride,
++				   int sources, int gates, u32 masks[4])
++{
++	uint32x4_t mask;
++	int g, s;
++	int cutoff = sources / 4 / 8 / 3 * 2;
++
++	mask = vdupq_n_u32(0);
++
++	for (g = 0; g < gates; g++) {
++		if (unlikely(g == 0))
++			mask = vdupq_n_u32(masks[0]);
++		else
++			mask = vdupq_n_u32(masks[2]);
++
++		for (s = 0; s < sources / 4 / 8; s++) {
++			uint8x8_t src;
++			uint16x8_t dst;
++			uint32x4_t out;
++
++			if (unlikely(s == cutoff))
++				mask = vdupq_n_u32(g == 0 ? masks[1] : masks[3]);
++
++			src = vld1_u8(fb);
++			fb += 8;
++
++			dst = vshll_n_u8(src, 3);
++			dst = vsliq_n_u16(dst, vmovl_u8(vshr_n_u8(src, 3)), 8);
++
++			out = vmovl_u16(vget_low_u16(dst));
++			out = vorrq_u32(out, mask);
++			vst1q_u32(cmd, out);
++			cmd += 4;
++
++			out = vmovl_u16(vget_high_u16(dst));
++			out = vorrq_u32(out, mask);
++			vst1q_u32(cmd, out);
++			cmd += 4;
++		}
++
++		cmd += stride - sources / 4;
++	}
++}
++EXPORT_SYMBOL_GPL(eink_ctlstream_fill_data_neon);
+diff --git a/drivers/video/fbdev/sun5i-eink.c b/drivers/video/fbdev/sun5i-eink.c
+new file mode 100644
+index 000000000000..fbc2cbaedb22
+--- /dev/null
++++ b/drivers/video/fbdev/sun5i-eink.c
+@@ -0,0 +1,1156 @@
++/*
++ * Copyright Ondrej Jirman <megi@xff.cz>
++ */
++#include <linux/cdev.h>
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/device.h>
++#include <linux/dmaengine.h>
++#include <linux/dma-mapping.h>
++#include <linux/gpio/consumer.h>
++#include <linux/interrupt.h>
++#include <linux/iopoll.h>
++#include <linux/module.h>
++#include <linux/of_device.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++#include <linux/poll.h>
++#include <linux/regmap.h>
++#include <linux/regulator/consumer.h>
++#include <linux/iio/consumer.h>
++#include <linux/pinctrl/consumer.h>
++#include <linux/reset.h>
++#include <linux/slab.h>
++#include <linux/spinlock.h>
++#include <linux/wait.h>
++#include <linux/workqueue.h>
++#include <asm/neon.h>
++
++// {{{ Registry defines
++
++#define SUN4I_TCON_GCTL_REG			0x0
++#define SUN4I_TCON_GCTL_TCON_ENABLE			BIT(31)
++#define SUN4I_TCON_GCTL_IOMAP_MASK			BIT(0)
++#define SUN4I_TCON_GCTL_IOMAP_TCON1			(1 << 0)
++#define SUN4I_TCON_GCTL_IOMAP_TCON0			(0 << 0)
++
++#define SUN4I_TCON_GINT0_REG			0x4
++#define SUN4I_TCON_GINT0_VBLANK_ENABLE(pipe)		BIT(31 - (pipe))
++#define SUN4I_TCON_GINT0_VBLANK_INT(pipe)		BIT(15 - (pipe))
++#define SUN4I_TCON_GINT0_LINE_ENABLE(pipe)		BIT(29 - (pipe))
++#define SUN4I_TCON_GINT0_LINE_INT(pipe)			BIT(13 - (pipe))
++
++#define SUN4I_TCON_GINT1_REG			0x8
++
++#define SUN4I_TCON0_CTL_REG			0x40
++#define SUN4I_TCON0_CTL_TCON_ENABLE			BIT(31)
++#define SUN4I_TCON0_CTL_IF_MASK				GENMASK(25, 24)
++#define SUN4I_TCON0_CTL_IF_8080				(1 << 24)
++#define SUN4I_TCON0_CTL_CLK_DELAY_MASK			GENMASK(8, 4)
++#define SUN4I_TCON0_CTL_CLK_DELAY(delay)		((delay << 4) & SUN4I_TCON0_CTL_CLK_DELAY_MASK)
++#define SUN4I_TCON0_CTL_SRC_SEL_MASK			GENMASK(2, 0)
++
++#define SUN4I_TCON0_DCLK_REG			0x44
++#define SUN4I_TCON0_DCLK_GATE_BIT			(31)
++#define SUN4I_TCON0_DCLK_DIV_SHIFT			(0)
++#define SUN4I_TCON0_DCLK_DIV_WIDTH			(7)
++
++#define SUN4I_TCON0_BASIC0_REG			0x48
++#define SUN4I_TCON0_BASIC0_X(width)			((((width) - 1) & 0xfff) << 16)
++#define SUN4I_TCON0_BASIC0_Y(height)			(((height) - 1) & 0xfff)
++
++#define SUN4I_TCON0_BASIC1_REG			0x4c
++#define SUN4I_TCON0_BASIC1_H_TOTAL(total)		((((total) - 1) & 0x1fff) << 16)
++#define SUN4I_TCON0_BASIC1_H_BACKPORCH(bp)		(((bp) - 1) & 0xfff)
++
++#define SUN4I_TCON0_BASIC2_REG			0x50
++#define SUN4I_TCON0_BASIC2_V_TOTAL(total)		(((total) & 0x1fff) << 16)
++#define SUN4I_TCON0_BASIC2_V_BACKPORCH(bp)		(((bp) - 1) & 0xfff)
++
++#define SUN4I_TCON0_BASIC3_REG			0x54
++#define SUN4I_TCON0_BASIC3_H_SYNC(width)		((((width) - 1) & 0x7ff) << 16)
++#define SUN4I_TCON0_BASIC3_V_SYNC(height)		(((height) - 1) & 0x7ff)
++
++#define SUN4I_TCON0_HV_IF_REG			0x58
++
++#define SUN4I_TCON0_IO_POL_REG			0x88
++#define SUN4I_TCON0_IO_POL_DCLK_PHASE(phase)		((phase & 3) << 28)
++#define SUN4I_TCON0_IO_POL_DE_NEGATIVE			BIT(27)
++#define SUN4I_TCON0_IO_POL_DCLK_NEGATIVE		BIT(26)
++#define SUN4I_TCON0_IO_POL_HSYNC_POSITIVE		BIT(25)
++#define SUN4I_TCON0_IO_POL_VSYNC_POSITIVE		BIT(24)
++
++#define SUN4I_TCON0_IO_TRI_REG			0x8c
++#define SUN4I_TCON0_IO_TRI_HSYNC_DISABLE		BIT(25)
++#define SUN4I_TCON0_IO_TRI_VSYNC_DISABLE		BIT(24)
++#define SUN4I_TCON0_IO_TRI_DATA_PINS_DISABLE(pins)	GENMASK(pins, 0)
++
++#define SUN4I_BACKEND_MODCTL_REG		0x800
++#define SUN4I_BACKEND_MODCTL_LINE_SEL			BIT(29)
++#define SUN4I_BACKEND_MODCTL_ITLMOD_EN			BIT(28)
++#define SUN4I_BACKEND_MODCTL_OUT_SEL			GENMASK(22, 20)
++#define SUN4I_BACKEND_MODCTL_OUT_LCD0				(0 << 20)
++#define SUN4I_BACKEND_MODCTL_OUT_LCD1				(1 << 20)
++#define SUN4I_BACKEND_MODCTL_OUT_FE0				(6 << 20)
++#define SUN4I_BACKEND_MODCTL_OUT_FE1				(7 << 20)
++#define SUN4I_BACKEND_MODCTL_HWC_EN			BIT(16)
++#define SUN4I_BACKEND_MODCTL_LAY_EN(l)			BIT(8 + l)
++#define SUN4I_BACKEND_MODCTL_OCSC_EN			BIT(5)
++#define SUN4I_BACKEND_MODCTL_DFLK_EN			BIT(4)
++#define SUN4I_BACKEND_MODCTL_DLP_START_CTL		BIT(2)
++#define SUN4I_BACKEND_MODCTL_START_CTL			BIT(1)
++#define SUN4I_BACKEND_MODCTL_DEBE_EN			BIT(0)
++
++#define SUN4I_BACKEND_BACKCOLOR_REG		0x804
++#define SUN4I_BACKEND_BACKCOLOR(r, g, b)		(((r) << 16) | ((g) << 8) | (b))
++
++#define SUN4I_BACKEND_DISSIZE_REG		0x808
++#define SUN4I_BACKEND_DISSIZE(w, h)			(((((h) - 1) & 0xffff) << 16) | \
++							 (((w) - 1) & 0xffff))
++
++#define SUN4I_BACKEND_LAYSIZE_REG(l)		(0x810 + (0x4 * (l)))
++#define SUN4I_BACKEND_LAYSIZE(w, h)			(((((h) - 1) & 0x1fff) << 16) | \
++							 (((w) - 1) & 0x1fff))
++
++#define SUN4I_BACKEND_LAYCOOR_REG(l)		(0x820 + (0x4 * (l)))
++#define SUN4I_BACKEND_LAYCOOR(x, y)			((((u32)(y) & 0xffff) << 16) | \
++							 ((u32)(x) & 0xffff))
++
++#define SUN4I_BACKEND_LAYLINEWIDTH_REG(l)	(0x840 + (0x4 * (l)))
++
++#define SUN4I_BACKEND_LAYFB_L32ADD_REG(l)	(0x850 + (0x4 * (l)))
++
++#define SUN4I_BACKEND_LAYFB_H4ADD_REG		0x860
++#define SUN4I_BACKEND_LAYFB_H4ADD_MSK(l)		GENMASK(3 + ((l) * 8), (l) * 8)
++#define SUN4I_BACKEND_LAYFB_H4ADD(l, val)		((val) << ((l) * 8))
++
++#define SUN4I_BACKEND_REGBUFFCTL_REG		0x870
++#define SUN4I_BACKEND_REGBUFFCTL_AUTOLOAD_DIS		BIT(1)
++#define SUN4I_BACKEND_REGBUFFCTL_LOADCTL		BIT(0)
++
++#define SUN4I_BACKEND_CKMAX_REG			0x880
++#define SUN4I_BACKEND_CKMIN_REG			0x884
++#define SUN4I_BACKEND_CKCFG_REG			0x888
++#define SUN4I_BACKEND_ATTCTL_REG0(l)		(0x890 + (0x4 * (l)))
++#define SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA_MASK	GENMASK(31, 24)
++#define SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA(x)		((x) << 24)
++#define SUN4I_BACKEND_ATTCTL_REG0_LAY_PIPESEL_MASK	BIT(15)
++#define SUN4I_BACKEND_ATTCTL_REG0_LAY_PIPESEL(x)		((x) << 15)
++#define SUN4I_BACKEND_ATTCTL_REG0_LAY_PRISEL_MASK	GENMASK(11, 10)
++#define SUN4I_BACKEND_ATTCTL_REG0_LAY_PRISEL(x)			((x) << 10)
++#define SUN4I_BACKEND_ATTCTL_REG0_LAY_WORKMOD_MASK	GENMASK(23, 22)
++#define SUN4I_BACKEND_ATTCTL_REG0_LAY_WORKMOD(x)		((x) << 22)
++#define SUN4I_BACKEND_ATTCTL_REG0_LAY_YUVEN		BIT(2)
++#define SUN4I_BACKEND_ATTCTL_REG0_LAY_VDOEN		BIT(1)
++#define SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA_EN	BIT(0)
++
++#define SUN4I_BACKEND_ATTCTL_REG1(l)		(0x8a0 + (0x4 * (l)))
++#define SUN4I_BACKEND_ATTCTL_REG1_LAY_HSCAFCT		GENMASK(15, 14)
++#define SUN4I_BACKEND_ATTCTL_REG1_LAY_WSCAFCT		GENMASK(13, 12)
++#define SUN4I_BACKEND_ATTCTL_REG1_LAY_FBFMT		GENMASK(11, 8)
++#define SUN4I_BACKEND_LAY_FBFMT_1BPP				(0 << 8)
++#define SUN4I_BACKEND_LAY_FBFMT_2BPP				(1 << 8)
++#define SUN4I_BACKEND_LAY_FBFMT_4BPP				(2 << 8)
++#define SUN4I_BACKEND_LAY_FBFMT_8BPP				(3 << 8)
++#define SUN4I_BACKEND_LAY_FBFMT_RGB655				(4 << 8)
++#define SUN4I_BACKEND_LAY_FBFMT_RGB565				(5 << 8)
++#define SUN4I_BACKEND_LAY_FBFMT_RGB556				(6 << 8)
++#define SUN4I_BACKEND_LAY_FBFMT_ARGB1555			(7 << 8)
++#define SUN4I_BACKEND_LAY_FBFMT_RGBA5551			(8 << 8)
++#define SUN4I_BACKEND_LAY_FBFMT_XRGB8888			(9 << 8)
++#define SUN4I_BACKEND_LAY_FBFMT_ARGB8888			(10 << 8)
++#define SUN4I_BACKEND_LAY_FBFMT_RGB888				(11 << 8)
++#define SUN4I_BACKEND_LAY_FBFMT_ARGB4444			(12 << 8)
++#define SUN4I_BACKEND_LAY_FBFMT_RGBA4444			(13 << 8)
++
++// }}}
++
++#define EINK_IOCTL_UPDATE _IO('A', 0)
++//#define EINK_IOCTL_STATUS _IOR('A', 2, int)
++
++enum {
++	EINK_REQ_NONE = 0,
++	EINK_REQ_UPDATE,
++	EINK_REQ_POWERDOWN,
++};
++
++enum {
++	EINK_WORKING,
++	EINK_OPEN,
++	EINK_WAITING_INT,
++	EINK_BE_SETUP,
++};
++
++struct eink_dev {
++	struct device *dev;
++
++	// io
++	struct pinctrl* pinctrl;
++	struct pinctrl_state *pinctrl_active;
++	struct pinctrl_state *pinctrl_idle;
++	struct gpio_descs* gpios;
++
++	// power
++	struct regulator *panel_supply;
++	struct timer_list powerdown_timer;
++	bool powered;
++
++	// tcon0
++	struct clk_bulk_data *clks;
++	int num_clks;
++
++        struct reset_control *rstc;
++	struct regmap *tcon_regs;
++	struct regmap *be_regs;
++	int irq;
++
++	// framebuffers
++	u8* framebuffers[2];
++	u32* ctlstream;
++	dma_addr_t ctlstream_paddr;
++	size_t ctlstream_size; // byte size
++
++	// control device
++	struct cdev cdev;
++	dev_t major;
++	bool is_open; // device can be used by only one user
++
++	// rendering work
++	spinlock_t lock;
++	wait_queue_head_t waitqueue;
++	struct workqueue_struct *wq;
++	struct work_struct work;
++	unsigned long flags[1];
++	int last_request;
++
++	const struct eink_panel_config* panel;
++};
++
++struct eink_panel_config {
++	int sources;
++	int gates;
++	int h_lead;
++	int h_trail;
++	int v_extra;
++};
++
++static const struct eink_panel_config eink_ed060xd4_panel = {
++	.sources = 1024,
++	.gates = 758,
++	.h_lead = 40, // 1000ns (should be multiple of 8 for 256-bit alignment)
++	.h_trail = 8, // should be multiple of 8 for 256-bit alignment
++	.v_extra = 9,
++};
++
++// buf format is 1 byte per pixel, len needs to be multiple of 4 bytes
++
++/* PocketBook 626(2) (Touch Lux 3) port D <-> Panel pin map */
++
++#define	D0        BIT(3)
++#define	D1        BIT(4)
++#define	D2        BIT(5)
++#define	D3        BIT(6)
++#define	D4        BIT(7)
++
++#define	D5       BIT(10)
++#define	D6       BIT(11)
++#define	D7       BIT(12)
++#define	S_LE     BIT(13)
++#define	G_MODE1  BIT(15)
++
++#define	S_OE     BIT(20)
++#define	S_SP     BIT(21)
++#define	G_CLK    BIT(22)
++#define	G_SP     BIT(23)
++
++/*
++ * we need to encode stream of control signals for various operations
++ * into separate rows:
++ *
++ * - sequence for starting a frame
++ * - three leading G_CLK pulses
++ * - sequence for all data rows
++ *   - wait time with OE for previous row
++ * - wait time for the last row without shifting in more data
++ * - trailing row with a sequence for ending a frame
++ *
++ * So we have to have:
++ * - 6 special rows with no data + all the data rows
++ * - all of these have to have the same width
++ * - we want to use TCON to manage timing of the OE via HT/HBP settings
++ *
++ * Timings:
++ * - we use 20MHz clock (50ns period)
++ * - we have to spend 256 clocks per row, pushing data
++ * - we want to have 85Hz frame refresh rate
++ *   - 11765us budget per frame
++ *   - minimum G_CLK low time is 500ns, minimum G_CLK cycle time is 5us
++ *     - G_SP 100ns setup (to G_CLK H->L)/hold time(after G_CLK H->L)
++ *   - LE pulse width >150ns
++ *     - LE delay before more data 200ns
++ *   - 12us time the output reacts to LE (this should be hsync time/hbp)
++ *   - at 20MHz, time to load data is 13us (about 100 FPS)
++ */
++static void eink_ctlstream_prepare(struct eink_dev* eink)
++{
++	const struct eink_panel_config* pc = eink->panel;
++	u32* p = eink->ctlstream;
++	int row_width = pc->sources / 4 + pc->h_lead + pc->h_trail; // ~262
++	int i, j, t, r;
++	u32 base;
++
++#define SET_PINS(t, v) { \
++		for (i = 0; i < t; i++) \
++			*p++ = v; \
++		r -= t; \
++	}
++
++	// prepare a startup row
++	t = row_width / 3;
++
++	r = row_width;
++	SET_PINS(20, G_MODE1 | G_SP | S_SP            );
++	SET_PINS(2*t,G_MODE1 | G_SP | S_SP | G_CLK    );
++	SET_PINS(r,  G_MODE1 | G_SP | S_SP            );
++
++	r = row_width;
++	SET_PINS(t,  G_MODE1 | G_SP | S_SP | G_CLK    );
++	SET_PINS(t,  G_MODE1 |        S_SP | G_CLK    );
++	SET_PINS(r,  G_MODE1 |        S_SP            );
++
++	r = row_width;
++	SET_PINS(t,  G_MODE1 |        S_SP | G_CLK    );
++	SET_PINS(t,  G_MODE1 | G_SP | S_SP | G_CLK    );
++	SET_PINS(r,  G_MODE1 | G_SP | S_SP            );
++
++	// three empty rows
++	for (j = 0; j < 3; j++) {
++		r = row_width;
++
++		SET_PINS(2*t,  G_MODE1 | G_SP | S_SP | G_CLK    );
++		SET_PINS(r,    G_MODE1 | G_SP | S_SP            );
++	}
++
++	// extra row is there to keep S_OE high for the previous last data
++	// row that was shifted in
++	for (j = 0; j < pc->gates + 1; j++) {
++		base = G_MODE1 | G_SP;
++
++                // We have 40 periods here to work with here (h_lead).
++		r = pc->h_lead;
++
++		// S_SP goes high after the last data and there's 2us
++		// delay (it may even go high during the last data period?)
++		SET_PINS(20, base | S_SP); // 1000ns for tLEdly
++		base &= ~S_OE;
++		SET_PINS(2,  base | S_SP);
++		SET_PINS(6,  base | S_SP | (j > 0 ? S_LE : 0)); // 300ns for tLEw
++		if (j > 0)
++			base |= S_OE;
++		SET_PINS(2,  base | S_SP | (j > 0 ? S_LE : 0));  // S_OE goes high
++		SET_PINS(r-2,base | S_SP); // 400ns for tLEoff
++		SET_PINS(r,  base | S_SP | G_CLK); // 400ns for tLEoff
++
++		if (j >= pc->gates)
++			base |= S_SP;
++
++		// start loading data immediately at S_SP going low
++		r = pc->sources / 4;
++		t = r / 3;
++		SET_PINS(t,  base | G_CLK);
++		SET_PINS(r,  base);
++
++		r = pc->h_trail;
++		SET_PINS(r,  base | S_SP);
++	}
++
++	r = row_width;
++	SET_PINS(r,               G_SP | S_SP                   );
++
++	// this last row will be stopped by an interrupt before finishing
++	// completely, so it's a dummy one
++	r = row_width;
++	SET_PINS(r,               G_SP | S_SP                   );
++}
++
++void eink_ctlstream_fill_data_neon(u32* cmd, u8* fb, int stride,
++				   int sources, int gates, u32 masks[4]);
++
++static void eink_ctlstream_fill_data(struct eink_dev* eink, u8* fb)
++{
++	const struct eink_panel_config* pc = eink->panel;
++	int row_width = pc->sources / 4 + pc->h_lead + pc->h_trail;
++	u32 masks[4] = {
++		G_MODE1 | G_SP | G_CLK,
++		G_MODE1 | G_SP,
++		G_MODE1 | G_SP | S_OE | G_CLK,
++		G_MODE1 | G_SP | S_OE,
++	};
++
++	kernel_neon_begin();
++	eink_ctlstream_fill_data_neon(eink->ctlstream + 6 * row_width + pc->h_lead,
++				      fb, row_width, pc->sources,
++				      pc->gates, masks);
++	kernel_neon_end();
++}
++
++static int eink_set_power(struct eink_dev* eink, bool en)
++{
++	int ret;
++
++	if (!en != !eink->powered) {
++		dev_warn(eink->dev, "%sable power supply", en ? "en" : "dis");
++
++		if (en)
++			ret = regulator_enable(eink->panel_supply);
++		else
++			ret = regulator_disable(eink->panel_supply);
++		if (ret) {
++			dev_err(eink->dev, "can't %sable power supply (%d)",
++				en ? "en" : "dis", ret);
++			return ret;
++		}
++	}
++
++	if (en)
++		mod_timer(&eink->powerdown_timer,
++			  jiffies + msecs_to_jiffies(5000));
++	else
++		del_timer_sync(&eink->powerdown_timer);
++
++	eink->powered = en;
++	return 0;
++}
++
++__maybe_unused
++static void print_time(struct device* dev, u64 ts, char *buf)
++{
++	do_div(ts, 1000);
++	dev_info(dev, "[%s] %6lu us", buf, (unsigned long)ts);
++}
++
++// DCLK = 20MHz
++static int eink_update(struct eink_dev* eink)
++{
++	struct regmap *tcon = eink->tcon_regs;
++	struct regmap *be = eink->be_regs;
++	unsigned long sclk_rate;
++	u32 ddiv = 6, w, h;
++	u32 lo_paddr, hi_paddr;
++	u32 vbp = 1, hbp = 40;
++	int ret;
++
++	ret = eink_set_power(eink, 1);
++	if (ret)
++		return ret;
++
++	sclk_rate = clk_get_rate(eink->clks[1].clk);
++	if (sclk_rate == 0)
++		return -EINVAL;
++
++	spin_lock(&eink->lock);
++	eink_ctlstream_fill_data(eink, eink->framebuffers[0]);
++	spin_unlock(&eink->lock);
++
++	w = eink->panel->sources / 4 + eink->panel->h_lead + eink->panel->h_trail;
++	h = eink->panel->gates + eink->panel->v_extra;
++
++	// Setup DEBE
++
++	if (!test_bit(EINK_BE_SETUP, eink->flags)) {
++	regmap_write(be, SUN4I_BACKEND_DISSIZE_REG,
++		     SUN4I_BACKEND_DISSIZE(w, h));
++	regmap_write(be, SUN4I_BACKEND_LAYSIZE_REG(0),
++		     SUN4I_BACKEND_LAYSIZE(w, h));
++	regmap_write(be, SUN4I_BACKEND_LAYCOOR_REG(0),
++		     SUN4I_BACKEND_LAYCOOR(0, 0));
++	regmap_write(be, SUN4I_BACKEND_LAYLINEWIDTH_REG(0),
++		     w * 4 * 8); /* input format has 4 bytes per pixel */
++
++	lo_paddr = eink->ctlstream_paddr << 3;
++	hi_paddr = eink->ctlstream_paddr >> 29;
++	regmap_write(be, SUN4I_BACKEND_LAYFB_L32ADD_REG(0), lo_paddr);
++	regmap_update_bits(be, SUN4I_BACKEND_LAYFB_H4ADD_REG,
++			   SUN4I_BACKEND_LAYFB_H4ADD_MSK(0),
++			   SUN4I_BACKEND_LAYFB_H4ADD(0, hi_paddr));
++
++	regmap_write(be, SUN4I_BACKEND_ATTCTL_REG0(0),
++		     SUN4I_BACKEND_ATTCTL_REG0_LAY_WORKMOD(0) |
++		     SUN4I_BACKEND_ATTCTL_REG0_LAY_PIPESEL(0) |
++		     SUN4I_BACKEND_ATTCTL_REG0_LAY_PRISEL(3));
++
++	regmap_write(be, SUN4I_BACKEND_ATTCTL_REG1(0),
++		     SUN4I_BACKEND_LAY_FBFMT_XRGB8888);
++
++	/* load BE buffers */
++	regmap_write(be, SUN4I_BACKEND_REGBUFFCTL_REG,
++		     SUN4I_BACKEND_REGBUFFCTL_AUTOLOAD_DIS |
++		     SUN4I_BACKEND_REGBUFFCTL_LOADCTL);
++	set_bit(EINK_BE_SETUP, eink->flags);
++	}
++
++	// Setup TCON/TCON0
++	//
++	// TCON0 timings, allwinner style:
++	//
++	// ht - horizontal total time
++	//   - total number of clock cycles in a row
++	// hbp - horizontal back porch
++	//   - number of dclk cycles between start of hsync and data
++	// vt - vertical total time
++	//   - number of rows in two frames
++	// vbp - vertical back porch
++	//   - number of rows between vsync start and a valid data line
++	// hspw
++	//   - width of hsync signal (in # of dclk cycles)
++	// vspw
++	//   - width of vsync signal (in # of rows)
++	//
++	// Notes:
++	// hbp(aw)=hbp(panel)+hspw(panel) (same for vbp)
++
++	/* Enable tcon module */
++	regmap_write(tcon, SUN4I_TCON_GCTL_REG,
++		     SUN4I_TCON_GCTL_TCON_ENABLE |
++		     SUN4I_TCON_GCTL_IOMAP_TCON0);
++
++	/* Set the resolution */
++	regmap_write(tcon, SUN4I_TCON0_BASIC0_REG,
++		     SUN4I_TCON0_BASIC0_X(w) |
++		     SUN4I_TCON0_BASIC0_Y(h));
++
++	/* Set horizontal display timings */
++	regmap_write(tcon, SUN4I_TCON0_BASIC1_REG,
++		     SUN4I_TCON0_BASIC1_H_TOTAL(w + hbp + 2) |
++		     SUN4I_TCON0_BASIC1_H_BACKPORCH(hbp));
++
++	/* Set vertical display timings */
++	regmap_write(tcon, SUN4I_TCON0_BASIC2_REG,
++		     SUN4I_TCON0_BASIC2_V_TOTAL((h + vbp + 2) * 2) |
++		     SUN4I_TCON0_BASIC2_V_BACKPORCH(vbp));
++
++	/* Set Hsync and Vsync length */
++	regmap_write(tcon, SUN4I_TCON0_BASIC3_REG,
++		     SUN4I_TCON0_BASIC3_V_SYNC(1) |
++		     SUN4I_TCON0_BASIC3_H_SYNC(1));
++
++        /* Setup output mode/pins */
++	regmap_write(tcon, SUN4I_TCON0_HV_IF_REG, 0); // 24bit parallel mode
++        regmap_write(tcon, SUN4I_TCON0_IO_POL_REG, SUN4I_TCON0_IO_POL_DCLK_NEGATIVE);
++        regmap_write(tcon, SUN4I_TCON0_IO_TRI_REG, 0);
++
++	ret = pinctrl_select_state(eink->pinctrl, eink->pinctrl_active);
++	if (ret) {
++		dev_err(eink->dev, "can't switch to active pinctrl state (%d)",
++			ret);
++	}
++
++	set_bit(EINK_WAITING_INT, eink->flags);
++
++	/* Interrupt after h lines */
++	regmap_write(tcon, SUN4I_TCON_GINT0_REG, 0);
++        regmap_write(tcon, SUN4I_TCON_GINT1_REG, (h + vbp + 2) << 16);
++	//regmap_write(tcon, SUN4I_TCON_GINT0_REG,
++		     //SUN4I_TCON_GINT0_VBLANK_ENABLE(0));
++	regmap_write(tcon, SUN4I_TCON_GINT0_REG,
++		     SUN4I_TCON_GINT0_LINE_ENABLE(0));
++
++	/* Configure and enable the dot clock */
++	regmap_write(tcon, SUN4I_TCON0_DCLK_REG,
++		     BIT(SUN4I_TCON0_DCLK_GATE_BIT) |
++		     (ddiv << SUN4I_TCON0_DCLK_DIV_SHIFT));
++
++	/* Enable tcon 0, set clk delay */
++	regmap_write(tcon, SUN4I_TCON0_CTL_REG,
++		     SUN4I_TCON0_CTL_CLK_DELAY(3)); // up to 30
++
++	regmap_update_bits(tcon, SUN4I_TCON0_CTL_REG,
++			   SUN4I_TCON0_CTL_TCON_ENABLE,
++			   SUN4I_TCON0_CTL_TCON_ENABLE);
++
++	ret = wait_event_timeout(eink->waitqueue,
++				 !test_bit(EINK_WAITING_INT, eink->flags),
++				 msecs_to_jiffies(100));
++	if (ret == 0)
++		dev_warn(eink->dev, "Timeout waiting for TCON transfer\n");
++
++	// stop everything, cleanup
++        //regmap_write(tcon, SUN4I_TCON0_DCLK_REG, 0);
++	regmap_update_bits(tcon, SUN4I_TCON0_CTL_REG,
++			   SUN4I_TCON0_CTL_TCON_ENABLE,
++			   0);
++        //regmap_write(tcon, SUN4I_TCON_GCTL_REG, 0);
++        regmap_write(tcon, SUN4I_TCON_GINT0_REG, 0);
++        regmap_write(tcon, SUN4I_TCON_GINT1_REG, 0);
++
++	ret = pinctrl_select_state(eink->pinctrl, eink->pinctrl_idle);
++	if (ret) {
++		dev_err(eink->dev, "can't switch to idle pinctrl state (%d)",
++			ret);
++	}
++
++        regmap_write(tcon, SUN4I_TCON0_IO_TRI_REG, ~0);
++
++	return ret;
++}
++
++static void eink_supply_powerdown_timer(struct timer_list *t)
++{
++	struct eink_dev *eink = from_timer(eink, t, powerdown_timer);
++
++	//dev_info(eink->dev, "powering down");
++
++	spin_lock(&eink->lock);
++	eink->last_request = EINK_REQ_POWERDOWN;
++	spin_unlock(&eink->lock);
++
++	queue_work(eink->wq, &eink->work);
++}
++
++static void eink_work_handler(struct work_struct *work)
++{
++	struct eink_dev *eink = container_of(work, struct eink_dev, work);
++	int last_request;
++
++	spin_lock(&eink->lock);
++	last_request = eink->last_request;
++	eink->last_request = 0;
++	spin_unlock(&eink->lock);
++
++	if (last_request == EINK_REQ_UPDATE) {
++		eink_update(eink);
++	} else if (last_request == EINK_REQ_POWERDOWN) {
++		eink_set_power(eink, 0);
++	}
++
++	clear_bit(EINK_WORKING, eink->flags);
++	wake_up(&eink->waitqueue);
++}
++
++static ssize_t eink_read(struct file *fp, char __user *buf, size_t len,
++			 loff_t *off)
++{
++	struct eink_dev* eink = fp->private_data;
++	int ret, fb_size;
++
++	fb_size = eink->panel->sources / 4 * eink->panel->gates;
++	if (len != fb_size)
++		return -EINVAL;
++
++	spin_lock(&eink->lock);
++	if (copy_to_user(buf, eink->framebuffers[0], fb_size))
++		ret = -EFAULT;
++	else
++		ret = fb_size;
++	spin_unlock(&eink->lock);
++
++	return ret;
++}
++
++static ssize_t eink_write(struct file *fp, const char __user *buf,
++			  size_t len, loff_t *off)
++{
++	struct eink_dev* eink = fp->private_data;
++	int non_blocking = fp->f_flags & O_NONBLOCK;
++	int ret, fb_size;
++
++	fb_size = eink->panel->sources / 4 * eink->panel->gates;
++	if (len != fb_size)
++		return -EINVAL;
++
++	if (test_and_set_bit(EINK_WORKING, eink->flags))
++		return -EBUSY;
++
++	spin_lock(&eink->lock);
++	ret = copy_from_user(eink->framebuffers[0], buf, len);
++	if (ret) {
++		clear_bit(EINK_WORKING, eink->flags);
++		spin_unlock(&eink->lock);
++		return -EFAULT;
++	}
++
++	eink->last_request = EINK_REQ_UPDATE;
++	spin_unlock(&eink->lock);
++
++	queue_work(eink->wq, &eink->work);
++
++	// first handle non-blocking path
++	if (non_blocking && test_bit(EINK_WORKING, eink->flags))
++		return -EWOULDBLOCK;
++
++	// wait for availability of wakeup
++	wait_event(eink->waitqueue,
++		   !test_bit(EINK_WORKING, eink->flags));
++
++	//u64 ts = ktime_get_boottime_ns();
++	//print_time(eink->dev, ktime_get_boottime() - ts, "one frame");
++
++	return len;
++}
++
++static unsigned int eink_poll(struct file *fp, poll_table *wait)
++{
++	struct eink_dev* eink = fp->private_data;
++	int ret = 0;
++
++	poll_wait(fp, &eink->waitqueue, wait);
++
++	if (!test_bit(EINK_WORKING, eink->flags))
++		ret |= POLLIN | POLLRDNORM;
++
++	return ret;
++}
++
++static long eink_ioctl(struct file *fp, unsigned int cmd, unsigned long arg)
++{
++	struct eink_dev* eink = fp->private_data;
++	unsigned long flags;
++	int ret = -ENOSYS;
++	//void __user *parg = (void __user *)arg;
++
++	if (!capable(CAP_SYS_ADMIN))
++		return -EACCES;
++
++	if (test_and_set_bit(EINK_WORKING, eink->flags))
++		return -EBUSY;
++
++	spin_lock_irqsave(&eink->lock, flags);
++
++	switch (cmd) {
++	case EINK_IOCTL_UPDATE:
++		eink->last_request = EINK_REQ_UPDATE;
++		ret = 0;
++		break;
++		/*
++	case EINK_IOCTL_BLANK:
++		eink->last_request = EINK_REQ_BLANK;
++		ret = 0;
++		break;
++	case EINK_IOCTL_STATUS:
++		if (copy_to_user(parg, &powered, sizeof powered))
++			return -EFAULT;
++
++		return 0;
++		*/
++	}
++
++	spin_unlock_irqrestore(&eink->lock, flags);
++
++	if (ret == 0)
++		queue_work(eink->wq, &eink->work);
++	else
++		clear_bit(EINK_WORKING, eink->flags);
++
++	return ret;
++}
++
++static int eink_release(struct inode *ip, struct file *fp)
++{
++	struct eink_dev* eink = fp->private_data;
++
++	clear_bit(EINK_OPEN, eink->flags);
++	return 0;
++}
++
++static int eink_open(struct inode *ip, struct file *fp)
++{
++	struct eink_dev* eink = container_of(ip->i_cdev, struct eink_dev, cdev);
++
++	if (test_and_set_bit(EINK_OPEN, eink->flags))
++		return -EBUSY;
++
++	fp->private_data = eink;
++
++	nonseekable_open(ip, fp);
++	return 0;
++}
++
++static const struct file_operations eink_fops = {
++	.owner		= THIS_MODULE,
++	.read		= eink_read,
++	.write		= eink_write,
++	.poll		= eink_poll,
++	.unlocked_ioctl	= eink_ioctl,
++	.open		= eink_open,
++	.release	= eink_release,
++	.llseek		= noop_llseek,
++};
++
++static struct regmap_config eink_tcon_regmap_config = {
++	.name		= "tcon",
++        .reg_bits       = 32,
++        .val_bits       = 32,
++        .reg_stride     = 4,
++        .max_register   = 0x7ff,
++	.cache_type     = REGCACHE_NONE,
++};
++
++static struct regmap_config eink_be_regmap_config = {
++	.name		= "be",
++        .reg_bits       = 32,
++        .val_bits       = 32,
++        .reg_stride     = 4,
++        .max_register   = 0x57ff,
++	.cache_type     = REGCACHE_NONE,
++};
++
++static struct class* eink_class;
++
++static irqreturn_t eink_tcon0_irq_handler(int irq, void *private)
++{
++        struct eink_dev *eink = private;
++	struct regmap *tcon = eink->tcon_regs;
++        unsigned int status;
++
++        regmap_read(eink->tcon_regs, SUN4I_TCON_GINT0_REG, &status);
++
++        if (!(status & (SUN4I_TCON_GINT0_VBLANK_INT(0) |
++			SUN4I_TCON_GINT0_LINE_INT(0))))
++                return IRQ_NONE;
++
++	// stop everything
++        //regmap_write(tcon, SUN4I_TCON_GCTL_REG, 0);
++
++	regmap_update_bits(tcon, SUN4I_TCON0_CTL_REG,
++			   SUN4I_TCON0_CTL_TCON_ENABLE,
++			   0);
++
++        regmap_write(tcon, SUN4I_TCON_GINT0_REG, 0);
++        regmap_write(tcon, SUN4I_TCON_GINT1_REG, 0);
++        //regmap_write(tcon, SUN4I_TCON0_DCLK_REG, 0);
++        //regmap_write(tcon, SUN4I_TCON0_IO_TRI_REG, ~0);
++
++	clear_bit(EINK_WAITING_INT, eink->flags);
++	wake_up(&eink->waitqueue);
++
++	/*
++        regmap_update_bits(eink->tcon_regs, SUN4I_TCON_GINT0_REG,
++                           SUN4I_TCON_GINT0_VBLANK_INT(0) |
++                           SUN4I_TCON_GINT0_LINE_INT(0),
++                           0);
++          */
++
++        return IRQ_HANDLED;
++}
++
++static const struct clk_bulk_data eink_clocks[] = {
++	{ .id = "tcon_bus" },
++	{ .id = "tcon_mod" },
++	{ .id = "be_bus" },
++	{ .id = "be_mod" },
++	{ .id = "be_ram" },
++};
++
++static int eink_probe(struct platform_device *pdev)
++{
++	struct eink_dev *eink;
++	struct device *dev = &pdev->dev;
++	struct device_node *np = dev->of_node;
++	struct device *sdev;
++	const char* cdev_name = NULL;
++        void __iomem *tcon_regs, *be_regs;
++	int ret, i, fb_size, cs_size;
++
++	eink = devm_kzalloc(dev, sizeof(*eink), GFP_KERNEL);
++	if (!eink)
++		return -ENOMEM;
++
++	eink->panel = &eink_ed060xd4_panel;
++	fb_size = eink->panel->sources / 4 * eink->panel->gates;
++
++	// we shift four 2-bit source values per clock cycle
++	cs_size = ((eink->panel->sources / 4 + eink->panel->h_lead + eink->panel->h_trail) *
++		   (eink->panel->gates + eink->panel->v_extra)) * 4;
++
++	eink->framebuffers[0] = devm_kzalloc(dev, fb_size, GFP_KERNEL);
++	if (!eink->framebuffers[0])
++		return -ENOMEM;
++
++	eink->framebuffers[1] = devm_kzalloc(dev, fb_size, GFP_KERNEL);
++	if (!eink->framebuffers[1])
++		return -ENOMEM;
++
++	eink->dev = dev;
++	platform_set_drvdata(pdev, eink);
++	init_waitqueue_head(&eink->waitqueue);
++	spin_lock_init(&eink->lock);
++	INIT_WORK(&eink->work, &eink_work_handler);
++	timer_setup(&eink->powerdown_timer, eink_supply_powerdown_timer, 0);
++
++	ret = of_dma_configure(dev, dev->of_node, true);
++	if (ret) {
++		dev_err(dev, "failed to configure dma (%d)\n", ret);
++		return ret;
++	}
++
++	tcon_regs = devm_platform_ioremap_resource(pdev, 0);
++        if (IS_ERR(tcon_regs))
++                return PTR_ERR(tcon_regs);
++
++	be_regs = devm_platform_ioremap_resource(pdev, 1);
++        if (IS_ERR(be_regs))
++                return PTR_ERR(be_regs);
++
++	eink->pinctrl = devm_pinctrl_get(dev);
++	if (IS_ERR(eink->pinctrl)) {
++		ret = PTR_ERR(eink->pinctrl);
++		dev_err(dev, "can't get pinctrl (%d)\n", ret);
++		return ret;
++	}
++
++	eink->pinctrl_active = pinctrl_lookup_state(eink->pinctrl, "active");
++	if (!eink->pinctrl_active) {
++		dev_err(dev, "missing active pinctrl state");
++		return -EINVAL;
++	}
++
++	eink->pinctrl_idle = pinctrl_lookup_state(eink->pinctrl, "idle");
++	if (!eink->pinctrl_idle) {
++		dev_err(dev, "missing idle pinctrl state");
++		return -EINVAL;
++	}
++
++	ret = pinctrl_select_state(eink->pinctrl, eink->pinctrl_idle);
++	if (ret) {
++		dev_err(eink->dev, "can't switch to idle pinctrl state (%d)",
++			ret);
++		return ret;
++	}
++
++	eink->gpios = devm_gpiod_get_array(dev, "all", GPIOD_OUT_LOW);
++	if (IS_ERR(eink->gpios)) {
++		ret = PTR_ERR(eink->gpios);
++		dev_err(dev, "can't get all gpios (%d)\n", ret);
++		return ret;
++	}
++
++	eink->irq = platform_get_irq(pdev, 0);
++	if (eink->irq < 0) {
++                dev_err(dev, "Couldn't retrieve the TCON interrupt\n");
++		return eink->irq;
++	}
++
++	ret = of_property_read_string(np, "control-device-name", &cdev_name);
++	if (ret) {
++		dev_err(dev, "char-device-name is not configured (%d)\n", ret);
++		return ret;
++	}
++
++	eink->panel_supply = devm_regulator_get(dev, "panel");
++	if (IS_ERR(eink->panel_supply)) {
++		ret = PTR_ERR(eink->panel_supply);
++		dev_err(dev, "can't get panel supply (%d)\n", ret);
++		return ret;
++	}
++
++	eink->clks = devm_kmemdup(dev, eink_clocks, sizeof(eink_clocks),
++				  GFP_KERNEL);
++	if (!eink->clks)
++		return -ENOMEM;
++
++	eink->num_clks = ARRAY_SIZE(eink_clocks);
++	ret = devm_clk_bulk_get(dev, eink->num_clks, eink->clks);
++	if (ret)
++		return ret;
++
++        eink->rstc = devm_reset_control_array_get(dev, 0);
++        if (IS_ERR(eink->rstc)) {
++		ret = PTR_ERR(eink->rstc);
++                dev_err(dev, "Couldn't get our reset line (%d)\n", ret);
++                return ret;
++        }
++
++        eink->tcon_regs = devm_regmap_init_mmio(dev, tcon_regs, &eink_tcon_regmap_config);
++        if (IS_ERR(eink->tcon_regs)) {
++		ret = PTR_ERR(eink->tcon_regs);
++                dev_err(dev, "Couldn't create the TCON regmap (%d)\n", ret);
++                return ret;
++        }
++
++        eink->be_regs = devm_regmap_init_mmio(dev, be_regs, &eink_be_regmap_config);
++        if (IS_ERR(eink->be_regs)) {
++		ret = PTR_ERR(eink->be_regs);
++                dev_err(dev, "Couldn't create the BE regmap (%d)\n", ret);
++                return ret;
++        }
++
++	// init the actual hardware
++        ret = reset_control_deassert(eink->rstc);
++        if (ret) {
++                dev_err(dev, "Couldn't deassert our reset line (%d)\n", ret);
++                return ret;
++        }
++
++	// possible to set 27-381MHz in 3MHz steps
++	ret = clk_set_rate(eink->clks[1].clk, 120000000);
++	if (ret) {
++                dev_err(dev, "Couldn't set tcon0 rate to  (%d)\n", ret);
++                goto err_reset;
++	}
++
++	ret = clk_bulk_prepare_enable(eink->num_clks, eink->clks);
++	if (ret) {
++                dev_err(dev, "Couldn't enable clocks (%d)\n", ret);
++                goto err_reset;
++	}
++
++	/* Clear DEBE registers */
++	for (i = 0x800; i < 0x1000; i += 4)
++		regmap_write(eink->be_regs, i, 0);
++
++	/* Disable registers autoloading */
++	regmap_write(eink->be_regs,
++		     SUN4I_BACKEND_REGBUFFCTL_REG,
++		     SUN4I_BACKEND_REGBUFFCTL_AUTOLOAD_DIS);
++
++	regmap_write(eink->be_regs,
++		     SUN4I_BACKEND_MODCTL_REG,
++		     SUN4I_BACKEND_MODCTL_START_CTL);
++
++	/* Enable the backend */
++	regmap_write(eink->be_regs,
++		     SUN4I_BACKEND_MODCTL_REG,
++		     SUN4I_BACKEND_MODCTL_DEBE_EN |
++		     SUN4I_BACKEND_MODCTL_START_CTL |
++		     SUN4I_BACKEND_MODCTL_OUT_LCD0 |
++		     SUN4I_BACKEND_MODCTL_LAY_EN(0));
++
++        /* Make sure the TCON is disabled and all IRQs are off */
++        regmap_write(eink->tcon_regs, SUN4I_TCON_GCTL_REG, 0);
++        regmap_write(eink->tcon_regs, SUN4I_TCON_GINT0_REG, 0);
++        regmap_write(eink->tcon_regs, SUN4I_TCON_GINT1_REG, 0);
++
++        /* Disable IO lines and set them to tristate */
++        regmap_write(eink->tcon_regs, SUN4I_TCON0_IO_TRI_REG, ~0);
++
++        ret = devm_request_irq(dev, eink->irq, eink_tcon0_irq_handler, 0,
++                               dev_name(dev), eink);
++        if (ret) {
++                dev_err(dev, "Couldn't request the IRQ\n");
++                goto err_disable_hw;
++        }
++
++	// create char device
++	ret = alloc_chrdev_region(&eink->major, 0, 1, "eink");
++	if (ret) {
++		dev_err(dev, "can't allocate chrdev region");
++		goto err_disable_hw;
++	}
++
++	cdev_init(&eink->cdev, &eink_fops);
++	eink->cdev.owner = THIS_MODULE;
++	ret = cdev_add(&eink->cdev, eink->major, 1);
++	if (ret) {
++		dev_err(dev, "can't add cdev");
++		goto err_unreg_chrev_region;
++	}
++
++	sdev = device_create(eink_class, dev, eink->major, eink, cdev_name);
++	if (IS_ERR(sdev)) {
++		ret = PTR_ERR(sdev);
++		goto err_del_cdev;
++	}
++
++	eink->ctlstream_size = round_up(cs_size, PAGE_SIZE);
++	eink->ctlstream = dma_alloc_wc(dev, eink->ctlstream_size,
++				       &eink->ctlstream_paddr,
++				       GFP_KERNEL | __GFP_NOWARN);
++	if (!eink->ctlstream) {
++		ret = -ENOMEM;
++		dev_err(dev, "failed to allocate buffer with size %zu\n",
++			eink->ctlstream_size);
++		goto err_destroy_device;
++	}
++
++	eink_ctlstream_prepare(eink);
++
++	eink->wq = alloc_workqueue("eink", WQ_SYSFS | WQ_HIGHPRI, 0);
++	if (!eink->wq) {
++		ret = -ENOMEM;
++		dev_err(dev, "failed to allocate workqueue\n");
++		goto err_free_dma;
++	}
++
++	dev_info(dev, "eink-panel driver ready!\n");
++	return 0;
++
++err_free_dma:
++	dma_free_wc(eink->dev, eink->ctlstream_size, eink->ctlstream,
++		    eink->ctlstream_paddr);
++err_destroy_device:
++	device_destroy(eink_class, eink->major);
++err_del_cdev:
++	cdev_del(&eink->cdev);
++err_unreg_chrev_region:
++	unregister_chrdev(eink->major, "eink");
++err_disable_hw:
++	clk_bulk_disable_unprepare(eink->num_clks, eink->clks);
++err_reset:
++        reset_control_assert(eink->rstc);
++	cancel_work_sync(&eink->work);
++
++	return ret;
++}
++
++static void eink_remove(struct platform_device *pdev)
++{
++	struct eink_dev *eink = platform_get_drvdata(pdev);
++
++	eink_set_power(eink, 0);
++
++	del_timer_sync(&eink->powerdown_timer);
++	cancel_work_sync(&eink->work);
++	destroy_workqueue(eink->wq);
++
++	dma_free_wc(eink->dev, eink->ctlstream_size, eink->ctlstream,
++		    eink->ctlstream_paddr);
++
++	clk_bulk_disable_unprepare(eink->num_clks, eink->clks);
++        reset_control_assert(eink->rstc);
++
++	device_destroy(eink_class, eink->major);
++	cdev_del(&eink->cdev);
++	unregister_chrdev(eink->major, "eink");
++}
++
++static const struct of_device_id eink_of_match[] = {
++	{ .compatible = "custom,pocketbook-touch-lux-3-tcon0-ed060xd4-display" },
++	{},
++};
++MODULE_DEVICE_TABLE(of, eink_of_match);
++
++static struct platform_driver eink_platform_driver = {
++	.probe = eink_probe,
++	.remove = eink_remove,
++	.driver = {
++		.name = "eink_tcon0",
++		.of_match_table = eink_of_match,
++	},
++};
++
++static int __init eink_driver_init(void)
++{
++	int ret;
++
++	eink_class = class_create("eink-panel");
++
++	ret = platform_driver_register(&eink_platform_driver);
++	if (ret)
++		class_destroy(eink_class);
++
++	return ret;
++}
++
++static void __exit eink_driver_exit(void)
++{
++	platform_driver_unregister(&eink_platform_driver);
++	class_destroy(eink_class);
++}
++
++module_init(eink_driver_init);
++module_exit(eink_driver_exit);
++
++MODULE_VERSION("1.0.0");
++MODULE_DESCRIPTION("eInk display Allwinner TCON0 based bit-banging driver");
++MODULE_AUTHOR("Ondrej Jirman <megi@xff.cz>");
++MODULE_LICENSE("GPL v2");
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/video-pwm_bl-Allow-to-change-lth_brightness-via-sysfs.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/video-pwm_bl-Allow-to-change-lth_brightness-via-sysfs.patch
new file mode 100644
index 000000000000..c49c442432bf
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/video-pwm_bl-Allow-to-change-lth_brightness-via-sysfs.patch
@@ -0,0 +1,126 @@
+From 9f67fcbe0e78e9b63df2e687b0eea50633f9e79e Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
+Date: Mon, 7 Jun 2021 20:27:07 +0200
+Subject: video: pwm_bl: Allow to change lth_brightness via sysfs
+
+Read minimum duty cycle in % from DT, and allow to change it via
+sysfs.
+
+Minimum brightness calibration instructions:
+
+  echo 1 > /sys/class/backlight/backlight/brightness
+
+  echo 1 > /sys/class/backlight/backlight/device/lth_brightness
+  echo 2 > /sys/class/backlight/backlight/device/lth_brightness
+  echo 3 > /sys/class/backlight/backlight/device/lth_brightness
+
+  .... increase values until you like the minimum brightness
+
+Then make sure to restore this value after each boot by writing it to
+/sys/class/backlight/backlight/device/lth_brightness
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+---
+ drivers/video/backlight/pwm_bl.c | 72 +++++++++++++++++++++++++++++++-
+ 1 file changed, 70 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/video/backlight/pwm_bl.c b/drivers/video/backlight/pwm_bl.c
+index f7d9d8813d92..8a7a158dc1f6 100644
+--- a/drivers/video/backlight/pwm_bl.c
++++ b/drivers/video/backlight/pwm_bl.c
+@@ -437,6 +437,61 @@ static int pwm_backlight_initial_power_state(const struct pwm_bl_data *pb)
+ 	return active ? BACKLIGHT_POWER_ON : BACKLIGHT_POWER_OFF;
+ }
+ 
++static ssize_t lth_brightness_show(struct device *dev,
++				   struct device_attribute *attr, char *buf)
++{
++	struct backlight_device *bl = platform_get_drvdata(to_platform_device(dev));
++	struct pwm_bl_data *pb = bl ? bl_get_data(bl) : NULL;
++	struct pwm_state state;
++	unsigned val;
++
++	if (!pb)
++		return -EBUSY;
++
++	pwm_get_state(pb->pwm, &state);
++	val = div_u64(100 * pb->lth_brightness, state.period);
++
++	return scnprintf(buf, PAGE_SIZE, "%u\n", val);
++}
++
++static ssize_t lth_brightness_store(struct device *dev,
++				    struct device_attribute *attr,
++				    const char *buf, size_t len)
++{
++	struct backlight_device *bl = platform_get_drvdata(to_platform_device(dev));
++	struct pwm_bl_data *pb = bl ? bl_get_data(bl) : NULL;
++	struct pwm_state state;
++	unsigned val;
++	int ret;
++
++	if (!pb)
++		return -EBUSY;
++
++	ret = kstrtouint(buf, 10, &val);
++	if (ret)
++		return ret;
++
++        if (val > 100)
++		val = 100;
++
++	pwm_get_state(pb->pwm, &state);
++	pb->lth_brightness = div_u64(val * state.period, 100);
++	pwm_backlight_update_status(bl);
++
++	return len;
++}
++
++static DEVICE_ATTR_RW(lth_brightness);
++
++static struct attribute *pwm_bl_attrs[] = {
++	&dev_attr_lth_brightness.attr,
++	NULL,
++};
++
++static const struct attribute_group pwm_bl_group = {
++	.attrs = pwm_bl_attrs,
++};
++
+ static int pwm_backlight_probe(struct platform_device *pdev)
+ {
+ 	struct platform_pwm_backlight_data *data = dev_get_platdata(&pdev->dev);
+@@ -445,6 +500,7 @@ static int pwm_backlight_probe(struct platform_device *pdev)
+ 	struct backlight_device *bl;
+ 	struct pwm_bl_data *pb;
+ 	struct pwm_state state, state_real;
++	u32 lth_brightness;
+ 	unsigned int i;
+ 	int ret;
+ 
+@@ -584,8 +640,20 @@ static int pwm_backlight_probe(struct platform_device *pdev)
+ 		pb->scale = data->max_brightness;
+ 	}
+ 
+-	pb->lth_brightness = data->lth_brightness * (div_u64(state.period,
+-				pb->scale));
++	pb->lth_brightness = div_u64(data->lth_brightness * state.period, pb->scale);
++
++	ret = of_property_read_u32(pdev->dev.of_node, "lth-brightness",
++				   &lth_brightness);
++	if (ret == 0) {
++		if (lth_brightness > 100)
++			lth_brightness = 100;
++
++		pb->lth_brightness = div_u64(lth_brightness * state.period, 100);
++	}
++
++	ret = devm_device_add_group(&pdev->dev, &pwm_bl_group);
++	if (ret)
++		goto err_alloc;
+ 
+ 	props.type = BACKLIGHT_RAW;
+ 	props.max_brightness = data->max_brightness;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/series.conf b/patch/kernel/archive/sunxi-6.14/series.conf
new file mode 100644
index 000000000000..9b2f89584aa6
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/series.conf
@@ -0,0 +1,249 @@
+#
+#	This file is made manually by simply copying text
+#	from the target series.* files.
+#	Add (-) at the beginning of the line if the patch should not be applied.
+#	At the same time, the patch does not need to be deleted.
+#
+	patches.megous/media-ov5640-Experiment-Try-to-disable-denoising-sharpening.patch
+	patches.megous/media-ov5640-Sleep-after-poweroff-to-ensure-next-poweron-is-not.patch
+	patches.megous/media-ov5640-Don-t-powerup-the-sensor-during-driver-probe.patch
+	patches.megous/media-ov5640-set-default-ae-target-lower.patch
+	patches.megous/media-ov5640-Improve-error-reporting.patch
+	patches.megous/media-ov5640-Implement-autofocus.patch
+	patches.megous/media-ov5640-Improve-firmware-load-time.patch
+	patches.megous/media-ov5640-Fix-focus-commands-blocking-until-complete.patch
+	patches.megous/media-ov5640-Add-read-only-property-for-vblank.patch
+	patches.megous/media-ov5640-use-pm_runtime_force_suspend-resume-for-system-sus.patch
+	patches.megous/media-sun6i-csi-capture-Use-subdev-operation-to-access-bridge-f.patch
+	patches.megous/media-sun6i-csi-subdev-Use-subdev-active-state-to-store-active-.patch
+	patches.megous/media-sun6i-csi-merge-sun6i_csi_formats-and-sun6i_csi_formats_m.patch
+	patches.megous/media-sun6i-csi-add-V4L2_CAP_IO_MC-capability.patch
+	patches.megous/media-sun6i-csi-implement-vidioc_enum_framesizes.patch
+	patches.megous/media-sun6i-csi-Add-multicamera-support-for-parallel-bus.patch
+	patches.megous/nfc-pn544-Add-support-for-VBAT-PVDD-regulators.patch
+	patches.megous/bluetooth-bcm-Restore-drive_rts_on_open-true-behavior-on-bcm207.patch
+	patches.megous/mmc-add-delay-after-power-class-selection.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-PN544-NFC-support.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-powerup-down-support-for-the-3G.patch
+	patches.megous/ARM-dts-sun8i-a83t-Add-cedrus-video-codec-support-to-A83T-untes.patch
+	patches.megous/ARM-dts-suni-a83t-Add-i2s0-pins.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-sound-support-via-AC100-codec.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-regulators-to-the-accelerometer.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-camera-sensors-HM5065-GC2145.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-flash-led-support.patch
+	patches.megous/dt-bindings-input-gpio-vibrator-Don-t-require-enable-gpios.patch
+	patches.megous/input-gpio-vibra-Allow-to-use-vcc-supply-alone-to-control-the-v.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-support-for-the-vibrator-motor.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Increase-voltage-on-the-vibrator.patch
+	patches.megous/dt-bindings-leds-Add-a-binding-for-AXP813-charger-led.patch
+	patches.megous/leds-axp20x-Support-charger-LED-on-AXP20x-like-PMICs.patch
+	patches.megous/ARM-dts-axp813-Add-charger-LED.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Enable-charging-LED.patch
+	patches.megous/MAINTAINERS-Add-entry-for-Himax-HM5065.patch
+	patches.megous/dt-bindings-media-Add-bindings-for-Himax-HM5065-camera-sensor.patch
+	patches.megous/hm5065-yaml-bindings-wip.patch
+	patches.megous/media-hm5065-Add-subdev-driver-for-Himax-HM5065-camera-sensor.patch
+	patches.megous/media-i2c-gc2145-Move-upstream-driver-out-of-the-way.patch
+	patches.megous/media-gc2145-Galaxycore-camera-module-driver.patch
+	patches.megous/media-gc2145-Added-BGGR-bayer-mode.patch
+	patches.megous/media-gc2145-Disable-debug-output.patch
+	patches.megous/media-gc2145-Add-PIXEL_RATE-HBLANK-and-VBLANK-controls.patch
+	patches.megous/media-gc2145-implement-system-suspend.patch
+	patches.megous/media-gc2145-fix-white-balance-colors.patch
+	patches.megous/media-i2c-gc2145-Parse-and-register-properties.patch
+	patches.megous/mailbox-Allow-to-run-mailbox-while-timekeeping-is-suspended.patch
+	patches.megous/ARM-sunxi-Add-experimental-suspend-to-memory-implementation-for.patch
+	patches.megous/ARM-sunxi-sunxi_cpu0_hotplug_support_set-is-not-supported-on-A8.patch
+	patches.megous/firmware-scpi-Add-support-for-sending-a-SCPI_CMD_SET_SYS_PWR_ST.patch
+	patches.megous/ARM-sunxi-Use-SCPI-to-send-suspend-message-to-SCP-on-A83T.patch
+	patches.megous/gnss-ubx-Send-soft-powerdown-message-on-suspend.patch
+	patches.megous/clk-sunxi-ng-Export-CLK_DRAM-for-devfreq.patch
+	patches.megous/ARM-dts-sun8i-a83t-Add-MBUS-node.patch
+	patches.megous/clk-sunxi-ng-Set-maximum-P-and-M-factors-to-1-for-H3-pll-cpux-c.patch
+	patches.megous/clk-sunxi-ng-Don-t-use-CPU-PLL-gating-and-CPUX-reparenting-to-H.patch
+	patches.megous/ARM-dts-sun8i-h3-Use-my-own-more-aggressive-OPPs-on-H3.patch
+	patches.megous/arm64-dts-sun50i-h5-Use-my-own-more-aggressive-OPPs-on-H5.patch
+	patches.megous/ARM-dts-sun8i-h3-orange-pi-pc-Increase-max-CPUX-voltage-to-1.4V.patch
+	patches.megous/ARM-dts-sun8i-a83t-Improve-CPU-OPP-tables-go-up-to-1.8GHz.patch
+	patches.megous/cpufreq-sun50i-Show-detected-CPU-bin-for-easier-debugging.patch
+	patches.megous/net-stmmac-sun8i-Use-devm_regulator_get-for-PHY-regulator.patch
+	patches.megous/net-stmmac-sun8i-Rename-PHY-regulator-variable-to-regulator_phy.patch
+	patches.megous/net-stmmac-sun8i-Add-support-for-enabling-a-regulator-for-PHY-I.patch
+	patches.megous/arm64-dts-allwinner-orange-pi-3-Enable-ethernet.patch
+	patches.megous/Revert-Input-cyttsp4-remove-driver.patch
+	patches.megous/input-cyttsp4-De-obfuscate-platform-data-for-keys.patch
+	patches.megous/input-cyttsp4-Remove-useless-indirection-with-driver-platform-d.patch
+	patches.megous/input-cyttsp4-Remove-unused-enable_vkeys.patch
+	patches.megous/input-cyttsp4-De-obfuscate-MT-signals-setup-platform-data.patch
+	patches.megous/input-cyttsp4-Clear-the-ids-buffer-in-a-saner-way.patch
+	patches.megous/input-cyttsp4-ENOSYS-error-is-ok-when-powering-up.patch
+	patches.megous/input-cyttsp4-Faster-recovery-from-failed-wakeup-HACK.patch
+	patches.megous/input-cyttsp4-Use-i2c-spi-names-directly-in-the-driver.patch
+	patches.megous/input-cyttsp4-Port-the-driver-to-use-device-properties.patch
+	patches.megous/input-cyttsp4-Restart-on-wakeup-wakeup-by-I2C-read-doesn-t-work.patch
+	patches.megous/input-cyttsp4-Fix-warnings.patch
+	patches.megous/input-cyttsp4-Make-the-driver-not-hog-the-system-s-workqueue.patch
+	patches.megous/input-cyttsp4-Fix-probe-oops.patch
+	patches.megous/input-cyttsp4-Fix-compile-issue.patch
+	patches.megous/video-fbdev-eInk-display-driver-for-A13-based-PocketBooks.patch
+	patches.megous/regulator-Add-simple-driver-for-enabling-a-regulator-from-users.patch
+	patches.megous/regulator-tp65185x-Add-tp65185x-eInk-panel-regulator-driver.patch
+	patches.megous/regulator-tp65185-Add-hwmon-device-for-reading-temperature.patch
+	patches.megous/iio-adc-sun4i-gpadc-iio-Allow-to-use-sun5i-a13-gpadc-iio-from-D.patch
+	patches.megous/mtd-spi-nor-Add-vdd-regulator-support.patch
+	patches.megous/ARM-dts-sun5i-Add-soc-handle.patch
+	patches.megous/ARM-dts-sun5i-Add-PocketBook-Touch-Lux-3-display-ctp-support.patch
+	patches.megous/ARM-dts-sun5i-a13-pocketbook-touch-lux-3-Add-RTC-clock-cells.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-front-back-cameras.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-Type-C-support-for-all-PP-va.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-modem-power-manager.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Fix-BH-modem-manager-behavior.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-detailed-OCV-to-capactiy-con.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Shorten-post-power-on-delay-on-m.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Bluetooth-audio.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Enable-internal-HMIC-bias.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-modem-audio.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Bump-I2C-frequency-to-400kHz.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-interrupt-pin-for-WiFi.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Power-off-the-touch-controller-i.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Don-t-make-lradc-keys-a-wakeup-s.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Set-minimum-backlight-duty-cycle.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-supply-for-i2c-bus-to-anx768.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Workaround-broken-HDMI-HPD-signa.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Pinephone-keyboa.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Enable-Pinephone-Keyboard-power-.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Pinephone-1.2-be.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-power-supply-to-stk3311.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-reboot-mode-driver.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Use-newer-jack-detection-impleme.patch
+	patches.megous/arm64-dts-sun50i-Define-orientation-and-rotation-for-PinePhone-.patch
+	patches.megous/2-arm64-dts-sun50i-Define-orientation-and-rotation-for-PinePhone-.patch
+	patches.megous/arm64-dts-sun50-a64-pinephone-Define-jack-pins-in-DT.patch
+	patches.megous/dt-bindings-sound-Add-jack-type-property-to-sun8i-a33-codec.patch
+	patches.megous/ASoC-sun8i-codec-Allow-the-jack-type-to-be-set-via-device-tree.patch
+	patches.megous/ASoC-sun8i-codec-define-button-keycodes.patch
+	patches.megous/ASoC-sun8i-codec-Add-debug-output-for-jack-detection.patch
+	patches.megous/ASoC-sun8i-codec-Set-jack_type-from-DT-in-probe.patch
+	patches.megous/ASoC-simple-card-Allow-to-define-pins-for-aux-jack-devices.patch
+	patches.megous/clk-sunxi-ng-a64-Increase-PLL_AUDIO-base-frequency.patch
+	patches.megous/dt-bindings-mfd-Add-codec-related-properties-to-AC100-PMIC.patch
+	patches.megous/sound-soc-ac100-codec-Support-analog-part-of-X-Powers-AC100-cod.patch
+	patches.megous/sound-soc-sun8i-codec-Add-support-for-digital-part-of-the-AC100.patch
+	patches.megous/ASoC-ec25-New-codec-driver-for-the-EC25-modem.patch
+	patches.megous/ASOC-sun9i-hdmi-audio-Initial-implementation.patch
+	patches.megous/ARM-dts-sunxi-h3-h5-Add-hdmi-sound-card.patch
+	patches.megous/ARM-dts-sun8i-h3-Enable-hdmi-sound-card-on-boards-with-hdmi.patch
+	patches.megous/ARM-dts-sun8i-h2-plus-bananapi-m2-zero-Enable-HDMI-audio.patch
+	patches.megous/ARM-dts-sun8i-a83t-Add-hdmi-sound-card.patch
+	patches.megous/ARM-dts-sun8i-a83t-Enable-hdmi-sound-card-on-boards-with-hdmi.patch
+	patches.megous/ARM-dts-sun8i-r40-Add-hdmi-sound-card.patch
+	patches.megous/ARM-dts-sun8i-r40-bananapi-m2-ultra-Enable-HDMI-audio.patch
+	patches.megous/ARM-dts-sun8i-v40-bananapi-m2-berry-Enable-HDMI-audio.patch
+	patches.megous/arm64-dts-allwinner-h6-Add-hdmi-sound-card.patch
+	patches.megous/arm64-dts-allwinner-h6-Enable-hdmi-sound-card-on-boards-with-hd.patch
+	patches.megous/arm64-dts-allwinner-a64-Add-hdmi-sound-card.patch
+	patches.megous/arm64-dts-allwinner-a64-Enable-hdmi-sound-card-on-boards-with-h.patch
+	patches.megous/arm64-dts-allwinner-h5-Enable-hdmi-sound-card-on-boards-with-hd.patch
+	patches.megous/Move-a-node-to-avoid-merge-conflict.patch
+	patches.megous/arm64-dts-sun50i-a64-Set-fifo-size-for-uarts.patch
+	patches.megous/ARM-dts-sun8i-a83t-Set-fifo-size-for-uarts.patch
+	patches.megous/Mark-some-slow-drivers-for-async-probe-with-PROBE_PREFER_ASYNCH.patch
+	patches.megous/arm64-xor-Select-32regs-without-benchmark-to-speed-up-boot.patch
+	patches.megous/clk-sunxi-ng-Mark-TWD-clocks-as-critical.patch
+	patches.megous/firmware-arm_scpi-Support-unidirectional-mailbox-channels.patch
+	patches.megous/ARM-dts-sunxi-a83t-Add-SCPI-protocol.patch
+	patches.megous/ARM-dts-sunxi-h3-h5-Add-SCPI-protocol.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Give-Linux-more-privileges-over-SCP.patch
+	patches.megous/rtc-sun6i-Allow-RTC-wakeup-after-shutdown.patch
+	patches.megous/misc-modem-power-Power-manager-for-modems.patch
+	patches.megous/ARM-dts-sun8i-a83t-Add-missing-GPU-trip-point.patch
+	patches.megous/arm64-dts-sun50i-h5-Add-missing-GPU-trip-point.patch
+	patches.megous/arm64-dts-allwinner-a64-Fix-LRADC-compatible.patch
+	patches.megous/media-cedrus-Fix-failure-to-clean-up-hardware-on-probe-failure.patch
+	patches.megous/ASoC-rockchip-Fix-doubling-of-playback-speed-after-system-sleep.patch
+	patches.megous/usb-musb-sunxi-Avoid-enabling-host-side-code-on-SoCs-where-it-s.patch
+	patches.megous/arm64-dts-allwinner-Enforce-consistent-MMC-numbering.patch
+	patches.megous/ARM-dts-sunxi-Add-aliases-for-MMC.patch
+	patches.megous/drm-rockchip-Fix-panic-on-reboot-when-DRM-device-fails-to-bind.patch
+	patches.megous/usb-gadget-Fix-dangling-pointer-in-netdev-private-data.patch
+	patches.megous/mmc-dw-mmc-rockchip-fix-sdmmc-after-soft-reboot.patch
+	patches.megous/Revert-drm-sun4i-lvds-Invert-the-LVDS-polarity.patch
+	patches.megous/of-property-fw_devlink-Support-allwinner-sram-links.patch
+	patches.megous/Fix-broken-allwinner-sram-dependency-on-h616-h618.patch
+	patches.megous/arm64-dts-rockchip-rk356x-Fix-PCIe-register-map-and-ranges.patch
+	patches.megous/Fix-intptr_t-typedef.patch
+	patches.megous/mmc-sunxi-mmc-Remove-runtime-PM.patch
+	patches.megous/pci-Workaround-ITS-timeouts-on-poweroff-reboot-on-Orange-Pi-5-P.patch
+	patches.megous/usb-serial-option-add-reset_resume-callback-for-WWAN-devices.patch
+	patches.megous/media-ov5648-Fix-call-to-pm_runtime_set_suspended.patch
+	patches.megous/drm-rockchip-dw-mipi-dsi-rockchip-Fix-ISP1-PHY-initialization.patch
+	patches.megous/arm64-dts-rk3399-Add-dmc_opp_table.patch
+	patches.megous/arm64-dts-rockchip-rk3399-s-Add-DMC-table.patch
+	patches.megous/bluetooth-h5-Don-t-re-initialize-rtl8723cs-on-resume.patch
+	patches.megous/drm-sun4i-Mark-one-of-the-UI-planes-as-a-cursor-one.patch
+	patches.megous/drm-sun4i-Implement-gamma-correction.patch
+	patches.megous/drm-panel-st7703-Fix-xbd599-timings-to-make-refresh-rate-exactl.patch
+	patches.megous/drm-sun4i-Support-taking-over-display-pipeline-state-from-p-boo.patch
+	patches.megous/video-pwm_bl-Allow-to-change-lth_brightness-via-sysfs.patch
+	patches.megous/clk-sunxi-ng-sun50i-a64-Switch-parent-of-MIPI-DSI-to-periph0-1x.patch
+	patches.megous/drm-sun4i-tcon-Support-keeping-dclk-rate-upon-ancestor-clock-ch.patch
+	patches.megous/phy-allwinner-sun4i-usb-Add-support-for-usb_role_switch.patch
+	patches.megous/regulator-axp20x-Add-support-for-vin-supply-for-drivevbus.patch
+	patches.megous/regulator-axp20x-Turn-N_VBUSEN-to-input-on-x-powers-sense-vbus-.patch
+	patches.megous/drm-bridge-dw-hdmi-Allow-to-accept-HPD-status-from-other-driver.patch
+	patches.megous/drm-bridge-dw-hdmi-Report-HDMI-hotplug-events.patch
+	patches.megous/usb-typec-anx7688-Add-driver-for-ANX7688-USB-C-HDMI-bridge.patch
+	patches.megous/usb-typec-anx7688-Port-to-Linux-6.9.patch
+	patches.megous/usb-typec-anx7688-Port-to-Linux-6.10.patch
+	patches.megous/dt-bindings-axp20x-adc-allow-to-use-TS-pin-as-GPADC.patch
+	patches.megous/iio-adc-axp20x_adc-allow-to-set-TS-pin-to-GPADC-mode.patch
+	patches.megous/power-axp20x_battery-Allow-to-set-target-voltage-to-4.35V.patch
+	patches.megous/power-supply-axp20x_battery-Add-support-for-reporting-OCV.patch
+	patches.megous/regulator-axp20x-Enable-over-temperature-protection-and-16s-res.patch
+	patches.megous/power-supply-axp20x_battery-Setup-thermal-regulation-experiment.patch
+	patches.megous/power-supply-axp20x_battery-Fix-charging-done-detection.patch
+	patches.megous/mfd-axp20x-Add-battery-IRQ-resources.patch
+	patches.megous/power-supply-axp20x_battery-Send-uevents-for-status-changes.patch
+	patches.megous/power-supply-axp20x_battery-Monitor-battery-health.patch
+	patches.megous/power-supply-axp20x-usb-power-Change-Vbus-hold-voltage-to-4.5V.patch
+	patches.megous/power-axp803-Add-interrupts-for-low-battery-power-condition.patch
+	patches.megous/power-supply-axp20x-battery-Support-POWER_SUPPLY_PROP_CHARGE_BE.patch
+	patches.megous/power-supply-axp20x-battery-Enable-poweron-by-RTC-alarm.patch
+	patches.megous/power-supply-axp20x-battery-Add-support-for-POWER_SUPPLY_PROP_E.patch
+	patches.megous/power-supply-Add-support-for-USB_BC_ENABLED-and-USB_DCP_INPUT_C.patch
+	patches.megous/power-supply-axp20x-usb-power-Add-missing-interrupts.patch
+	patches.megous/power-supply-axp20x-battery-Improve-probe-error-reporting.patch
+	patches.megous/sunxi-Use-dev_err_probe-to-handle-EPROBE_DEFER-errors.patch
+	patches.megous/thermal-sun8i-Be-loud-when-probe-fails.patch
+	patches.megous/i2c-mv64xxx-Don-t-make-a-fuss-when-pinctrl-recovery-state-is-no.patch
+	patches.megous/iio-st_sensors-Don-t-report-error-when-the-device-is-not-presen.patch
+	patches.megous/opp-core-Avoid-confusing-error-when-no-regulator-is-defined-in-.patch
+	patches.megous/rtc-Print-which-error-caused-RTC-read-failure.patch
+	patches.megous/arm64-dts-allwinner-a64-pinetab-add-front-camera.patch
+	patches.megous/arm64-allwinner-dts-a64-enable-K101-IM2BYL02-panel-for-PineTab.patch
+	patches.megous/arm64-dts-sun50i-a64-pinetab-Name-sound-card-PineTab.patch
+	patches.megous/arm64-dts-sun50i-a64-pinetab-Add-accelerometer.patch
+	patches.megous/arm64-dts-sun50i-a64-pinetab-enable-RTL8723CS-bluetooth.patch
+	patches.megous/usb-typec-fusb302-Slightly-increase-wait-time-for-BC1.2-result.patch
+	patches.megous/usb-typec-fusb302-Set-the-current-before-enabling-pullups.patch
+	patches.megous/usb-typec-fusb302-Extend-debugging-interface-with-driver-state-.patch
+	patches.megous/usb-typec-fusb302-Retry-reading-of-CC-pins-status-if-activity-i.patch
+	patches.megous/usb-typec-fusb302-More-useful-of-logging-status-on-interrupt.patch
+	patches.megous/usb-typec-fusb302-Update-VBUS-state-even-if-VBUS-interrupt-is-n.patch
+	patches.megous/usb-typec-fusb302-Add-OF-extcon-support.patch
+	patches.megous/usb-typec-fusb302-Fix-register-definitions.patch
+	patches.megous/usb-typec-fusb302-Clear-interrupts-before-we-start-toggling.patch
+	patches.megous/usb-typec-typec-extcon-Add-typec-extcon-bridge-driver.patch
+	patches.megous/usb-typec-typec-extcon-Enable-debugging-for-now.patch
+	patches.megous/usb-typec-typec-extcon-Allow-to-force-reset-on-each-mux-change.patch
+	patches.megous/Revert-usb-typec-tcpm-unregister-existing-source-caps-before-re.patch
+	patches.megous/usb-typec-altmodes-displayport-Respect-DP_CAP_RECEPTACLE-bit.patch
+	patches.megous/usb-typec-tcpm-Unregister-altmodes-before-registering-new-ones.patch
+	patches.megous/usb-typec-tcpm-Fix-PD-devices-capabilities-registration.patch
+	patches.megous/usb-typec-tcpm-Improve-logs.patch
+	patches.megous/Make-microbuttons-on-Orange-Pi-PC-and-PC-2-work-as-power-off-bu.patch
+	patches.megous/Add-support-for-my-private-Sapomat-device.patch
+	patches.megous/ARM-dts-sun8i-h3-orange-pi-one-Enable-all-gpio-header-UARTs.patch
+	patches.megous/mtd-spi-nor-Add-Alliance-memory-support.patch
+	patches.megous/Add-README.md-with-information-and-u-boot-patches.patch
+	patches.megous/Defconfigs-for-all-my-devices.patch
diff --git a/patch/kernel/archive/sunxi-6.14/series.megous b/patch/kernel/archive/sunxi-6.14/series.megous
new file mode 100644
index 000000000000..1773cf5e27b9
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/series.megous
@@ -0,0 +1,248 @@
+#
+#	Automatically generated by the script mk_format_patch
+#
+#	git@github.com:The-going/linux-sf.git
+#
+	patches.megous/media-ov5640-Experiment-Try-to-disable-denoising-sharpening.patch
+	patches.megous/media-ov5640-Sleep-after-poweroff-to-ensure-next-poweron-is-not.patch
+	patches.megous/media-ov5640-Don-t-powerup-the-sensor-during-driver-probe.patch
+	patches.megous/media-ov5640-set-default-ae-target-lower.patch
+	patches.megous/media-ov5640-Improve-error-reporting.patch
+	patches.megous/media-ov5640-Implement-autofocus.patch
+	patches.megous/media-ov5640-Improve-firmware-load-time.patch
+	patches.megous/media-ov5640-Fix-focus-commands-blocking-until-complete.patch
+	patches.megous/media-ov5640-Add-read-only-property-for-vblank.patch
+	patches.megous/media-ov5640-use-pm_runtime_force_suspend-resume-for-system-sus.patch
+	patches.megous/media-sun6i-csi-capture-Use-subdev-operation-to-access-bridge-f.patch
+	patches.megous/media-sun6i-csi-subdev-Use-subdev-active-state-to-store-active-.patch
+	patches.megous/media-sun6i-csi-merge-sun6i_csi_formats-and-sun6i_csi_formats_m.patch
+	patches.megous/media-sun6i-csi-add-V4L2_CAP_IO_MC-capability.patch
+	patches.megous/media-sun6i-csi-implement-vidioc_enum_framesizes.patch
+	patches.megous/media-sun6i-csi-Add-multicamera-support-for-parallel-bus.patch
+	patches.megous/nfc-pn544-Add-support-for-VBAT-PVDD-regulators.patch
+	patches.megous/bluetooth-bcm-Restore-drive_rts_on_open-true-behavior-on-bcm207.patch
+	patches.megous/mmc-add-delay-after-power-class-selection.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-PN544-NFC-support.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-powerup-down-support-for-the-3G.patch
+	patches.megous/ARM-dts-sun8i-a83t-Add-cedrus-video-codec-support-to-A83T-untes.patch
+	patches.megous/ARM-dts-suni-a83t-Add-i2s0-pins.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-sound-support-via-AC100-codec.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-regulators-to-the-accelerometer.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-camera-sensors-HM5065-GC2145.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-flash-led-support.patch
+	patches.megous/dt-bindings-input-gpio-vibrator-Don-t-require-enable-gpios.patch
+	patches.megous/input-gpio-vibra-Allow-to-use-vcc-supply-alone-to-control-the-v.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Add-support-for-the-vibrator-motor.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Increase-voltage-on-the-vibrator.patch
+	patches.megous/dt-bindings-leds-Add-a-binding-for-AXP813-charger-led.patch
+	patches.megous/leds-axp20x-Support-charger-LED-on-AXP20x-like-PMICs.patch
+	patches.megous/ARM-dts-axp813-Add-charger-LED.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Enable-charging-LED.patch
+	patches.megous/MAINTAINERS-Add-entry-for-Himax-HM5065.patch
+	patches.megous/dt-bindings-media-Add-bindings-for-Himax-HM5065-camera-sensor.patch
+	patches.megous/hm5065-yaml-bindings-wip.patch
+	patches.megous/media-hm5065-Add-subdev-driver-for-Himax-HM5065-camera-sensor.patch
+	patches.megous/media-i2c-gc2145-Move-upstream-driver-out-of-the-way.patch
+	patches.megous/media-gc2145-Galaxycore-camera-module-driver.patch
+	patches.megous/media-gc2145-Added-BGGR-bayer-mode.patch
+	patches.megous/media-gc2145-Disable-debug-output.patch
+	patches.megous/media-gc2145-Add-PIXEL_RATE-HBLANK-and-VBLANK-controls.patch
+	patches.megous/media-gc2145-implement-system-suspend.patch
+	patches.megous/media-gc2145-fix-white-balance-colors.patch
+	patches.megous/media-i2c-gc2145-Parse-and-register-properties.patch
+	patches.megous/mailbox-Allow-to-run-mailbox-while-timekeeping-is-suspended.patch
+	patches.megous/ARM-sunxi-Add-experimental-suspend-to-memory-implementation-for.patch
+	patches.megous/ARM-sunxi-sunxi_cpu0_hotplug_support_set-is-not-supported-on-A8.patch
+	patches.megous/firmware-scpi-Add-support-for-sending-a-SCPI_CMD_SET_SYS_PWR_ST.patch
+	patches.megous/ARM-sunxi-Use-SCPI-to-send-suspend-message-to-SCP-on-A83T.patch
+	patches.megous/gnss-ubx-Send-soft-powerdown-message-on-suspend.patch
+	patches.megous/clk-sunxi-ng-Export-CLK_DRAM-for-devfreq.patch
+	patches.megous/ARM-dts-sun8i-a83t-Add-MBUS-node.patch
+	patches.megous/clk-sunxi-ng-Set-maximum-P-and-M-factors-to-1-for-H3-pll-cpux-c.patch
+	patches.megous/clk-sunxi-ng-Don-t-use-CPU-PLL-gating-and-CPUX-reparenting-to-H.patch
+	patches.megous/ARM-dts-sun8i-h3-Use-my-own-more-aggressive-OPPs-on-H3.patch
+	patches.megous/arm64-dts-sun50i-h5-Use-my-own-more-aggressive-OPPs-on-H5.patch
+	patches.megous/ARM-dts-sun8i-h3-orange-pi-pc-Increase-max-CPUX-voltage-to-1.4V.patch
+	patches.megous/ARM-dts-sun8i-a83t-Improve-CPU-OPP-tables-go-up-to-1.8GHz.patch
+	patches.megous/cpufreq-sun50i-Show-detected-CPU-bin-for-easier-debugging.patch
+	patches.megous/net-stmmac-sun8i-Use-devm_regulator_get-for-PHY-regulator.patch
+	patches.megous/net-stmmac-sun8i-Rename-PHY-regulator-variable-to-regulator_phy.patch
+	patches.megous/net-stmmac-sun8i-Add-support-for-enabling-a-regulator-for-PHY-I.patch
+	patches.megous/arm64-dts-allwinner-orange-pi-3-Enable-ethernet.patch
+	patches.megous/Revert-Input-cyttsp4-remove-driver.patch
+	patches.megous/input-cyttsp4-De-obfuscate-platform-data-for-keys.patch
+	patches.megous/input-cyttsp4-Remove-useless-indirection-with-driver-platform-d.patch
+	patches.megous/input-cyttsp4-Remove-unused-enable_vkeys.patch
+	patches.megous/input-cyttsp4-De-obfuscate-MT-signals-setup-platform-data.patch
+	patches.megous/input-cyttsp4-Clear-the-ids-buffer-in-a-saner-way.patch
+	patches.megous/input-cyttsp4-ENOSYS-error-is-ok-when-powering-up.patch
+	patches.megous/input-cyttsp4-Faster-recovery-from-failed-wakeup-HACK.patch
+	patches.megous/input-cyttsp4-Use-i2c-spi-names-directly-in-the-driver.patch
+	patches.megous/input-cyttsp4-Port-the-driver-to-use-device-properties.patch
+	patches.megous/input-cyttsp4-Restart-on-wakeup-wakeup-by-I2C-read-doesn-t-work.patch
+	patches.megous/input-cyttsp4-Fix-warnings.patch
+	patches.megous/input-cyttsp4-Make-the-driver-not-hog-the-system-s-workqueue.patch
+	patches.megous/input-cyttsp4-Fix-probe-oops.patch
+	patches.megous/input-cyttsp4-Fix-compile-issue.patch
+	patches.megous/video-fbdev-eInk-display-driver-for-A13-based-PocketBooks.patch
+	patches.megous/regulator-Add-simple-driver-for-enabling-a-regulator-from-users.patch
+	patches.megous/regulator-tp65185x-Add-tp65185x-eInk-panel-regulator-driver.patch
+	patches.megous/regulator-tp65185-Add-hwmon-device-for-reading-temperature.patch
+	patches.megous/iio-adc-sun4i-gpadc-iio-Allow-to-use-sun5i-a13-gpadc-iio-from-D.patch
+	patches.megous/mtd-spi-nor-Add-vdd-regulator-support.patch
+	patches.megous/ARM-dts-sun5i-Add-soc-handle.patch
+	patches.megous/ARM-dts-sun5i-Add-PocketBook-Touch-Lux-3-display-ctp-support.patch
+	patches.megous/ARM-dts-sun5i-a13-pocketbook-touch-lux-3-Add-RTC-clock-cells.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-front-back-cameras.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-Type-C-support-for-all-PP-va.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-modem-power-manager.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Fix-BH-modem-manager-behavior.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-detailed-OCV-to-capactiy-con.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Shorten-post-power-on-delay-on-m.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Bluetooth-audio.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Enable-internal-HMIC-bias.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-modem-audio.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Bump-I2C-frequency-to-400kHz.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-interrupt-pin-for-WiFi.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Power-off-the-touch-controller-i.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Don-t-make-lradc-keys-a-wakeup-s.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Set-minimum-backlight-duty-cycle.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-supply-for-i2c-bus-to-anx768.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Workaround-broken-HDMI-HPD-signa.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Pinephone-keyboa.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Enable-Pinephone-Keyboard-power-.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-support-for-Pinephone-1.2-be.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-power-supply-to-stk3311.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Add-reboot-mode-driver.patch
+	patches.megous/arm64-dts-sun50i-a64-pinephone-Use-newer-jack-detection-impleme.patch
+	patches.megous/arm64-dts-sun50i-Define-orientation-and-rotation-for-PinePhone-.patch
+	patches.megous/2-arm64-dts-sun50i-Define-orientation-and-rotation-for-PinePhone-.patch
+	patches.megous/arm64-dts-sun50-a64-pinephone-Define-jack-pins-in-DT.patch
+	patches.megous/dt-bindings-sound-Add-jack-type-property-to-sun8i-a33-codec.patch
+	patches.megous/ASoC-sun8i-codec-Allow-the-jack-type-to-be-set-via-device-tree.patch
+	patches.megous/ASoC-sun8i-codec-define-button-keycodes.patch
+	patches.megous/ASoC-sun8i-codec-Add-debug-output-for-jack-detection.patch
+	patches.megous/ASoC-sun8i-codec-Set-jack_type-from-DT-in-probe.patch
+	patches.megous/ASoC-simple-card-Allow-to-define-pins-for-aux-jack-devices.patch
+	patches.megous/clk-sunxi-ng-a64-Increase-PLL_AUDIO-base-frequency.patch
+	patches.megous/dt-bindings-mfd-Add-codec-related-properties-to-AC100-PMIC.patch
+	patches.megous/sound-soc-ac100-codec-Support-analog-part-of-X-Powers-AC100-cod.patch
+	patches.megous/sound-soc-sun8i-codec-Add-support-for-digital-part-of-the-AC100.patch
+	patches.megous/ASoC-ec25-New-codec-driver-for-the-EC25-modem.patch
+	patches.megous/ASOC-sun9i-hdmi-audio-Initial-implementation.patch
+	patches.megous/ARM-dts-sunxi-h3-h5-Add-hdmi-sound-card.patch
+	patches.megous/ARM-dts-sun8i-h3-Enable-hdmi-sound-card-on-boards-with-hdmi.patch
+	patches.megous/ARM-dts-sun8i-h2-plus-bananapi-m2-zero-Enable-HDMI-audio.patch
+	patches.megous/ARM-dts-sun8i-a83t-Add-hdmi-sound-card.patch
+	patches.megous/ARM-dts-sun8i-a83t-Enable-hdmi-sound-card-on-boards-with-hdmi.patch
+	patches.megous/ARM-dts-sun8i-r40-Add-hdmi-sound-card.patch
+	patches.megous/ARM-dts-sun8i-r40-bananapi-m2-ultra-Enable-HDMI-audio.patch
+	patches.megous/ARM-dts-sun8i-v40-bananapi-m2-berry-Enable-HDMI-audio.patch
+	patches.megous/arm64-dts-allwinner-h6-Add-hdmi-sound-card.patch
+	patches.megous/arm64-dts-allwinner-h6-Enable-hdmi-sound-card-on-boards-with-hd.patch
+	patches.megous/arm64-dts-allwinner-a64-Add-hdmi-sound-card.patch
+	patches.megous/arm64-dts-allwinner-a64-Enable-hdmi-sound-card-on-boards-with-h.patch
+	patches.megous/arm64-dts-allwinner-h5-Enable-hdmi-sound-card-on-boards-with-hd.patch
+	patches.megous/Move-a-node-to-avoid-merge-conflict.patch
+	patches.megous/arm64-dts-sun50i-a64-Set-fifo-size-for-uarts.patch
+	patches.megous/ARM-dts-sun8i-a83t-Set-fifo-size-for-uarts.patch
+	patches.megous/Mark-some-slow-drivers-for-async-probe-with-PROBE_PREFER_ASYNCH.patch
+	patches.megous/arm64-xor-Select-32regs-without-benchmark-to-speed-up-boot.patch
+	patches.megous/clk-sunxi-ng-Mark-TWD-clocks-as-critical.patch
+	patches.megous/firmware-arm_scpi-Support-unidirectional-mailbox-channels.patch
+	patches.megous/ARM-dts-sunxi-a83t-Add-SCPI-protocol.patch
+	patches.megous/ARM-dts-sunxi-h3-h5-Add-SCPI-protocol.patch
+	patches.megous/ARM-dts-sun8i-a83t-tbs-a711-Give-Linux-more-privileges-over-SCP.patch
+	patches.megous/rtc-sun6i-Allow-RTC-wakeup-after-shutdown.patch
+	patches.megous/misc-modem-power-Power-manager-for-modems.patch
+	patches.megous/ARM-dts-sun8i-a83t-Add-missing-GPU-trip-point.patch
+	patches.megous/arm64-dts-sun50i-h5-Add-missing-GPU-trip-point.patch
+	patches.megous/arm64-dts-allwinner-a64-Fix-LRADC-compatible.patch
+	patches.megous/media-cedrus-Fix-failure-to-clean-up-hardware-on-probe-failure.patch
+	patches.megous/ASoC-rockchip-Fix-doubling-of-playback-speed-after-system-sleep.patch
+	patches.megous/usb-musb-sunxi-Avoid-enabling-host-side-code-on-SoCs-where-it-s.patch
+	patches.megous/arm64-dts-allwinner-Enforce-consistent-MMC-numbering.patch
+	patches.megous/ARM-dts-sunxi-Add-aliases-for-MMC.patch
+	patches.megous/drm-rockchip-Fix-panic-on-reboot-when-DRM-device-fails-to-bind.patch
+	patches.megous/usb-gadget-Fix-dangling-pointer-in-netdev-private-data.patch
+	patches.megous/mmc-dw-mmc-rockchip-fix-sdmmc-after-soft-reboot.patch
+	patches.megous/Revert-drm-sun4i-lvds-Invert-the-LVDS-polarity.patch
+	patches.megous/of-property-fw_devlink-Support-allwinner-sram-links.patch
+	patches.megous/Fix-broken-allwinner-sram-dependency-on-h616-h618.patch
+	patches.megous/arm64-dts-rockchip-rk356x-Fix-PCIe-register-map-and-ranges.patch
+	patches.megous/Fix-intptr_t-typedef.patch
+	patches.megous/mmc-sunxi-mmc-Remove-runtime-PM.patch
+	patches.megous/pci-Workaround-ITS-timeouts-on-poweroff-reboot-on-Orange-Pi-5-P.patch
+	patches.megous/usb-serial-option-add-reset_resume-callback-for-WWAN-devices.patch
+	patches.megous/media-ov5648-Fix-call-to-pm_runtime_set_suspended.patch
+	patches.megous/drm-rockchip-dw-mipi-dsi-rockchip-Fix-ISP1-PHY-initialization.patch
+	patches.megous/arm64-dts-rk3399-Add-dmc_opp_table.patch
+	patches.megous/arm64-dts-rockchip-rk3399-s-Add-DMC-table.patch
+	patches.megous/bluetooth-h5-Don-t-re-initialize-rtl8723cs-on-resume.patch
+	patches.megous/drm-sun4i-Mark-one-of-the-UI-planes-as-a-cursor-one.patch
+	patches.megous/drm-sun4i-Implement-gamma-correction.patch
+	patches.megous/drm-panel-st7703-Fix-xbd599-timings-to-make-refresh-rate-exactl.patch
+	patches.megous/drm-sun4i-Support-taking-over-display-pipeline-state-from-p-boo.patch
+	patches.megous/video-pwm_bl-Allow-to-change-lth_brightness-via-sysfs.patch
+	patches.megous/clk-sunxi-ng-sun50i-a64-Switch-parent-of-MIPI-DSI-to-periph0-1x.patch
+	patches.megous/drm-sun4i-tcon-Support-keeping-dclk-rate-upon-ancestor-clock-ch.patch
+	patches.megous/phy-allwinner-sun4i-usb-Add-support-for-usb_role_switch.patch
+	patches.megous/regulator-axp20x-Add-support-for-vin-supply-for-drivevbus.patch
+	patches.megous/regulator-axp20x-Turn-N_VBUSEN-to-input-on-x-powers-sense-vbus-.patch
+	patches.megous/drm-bridge-dw-hdmi-Allow-to-accept-HPD-status-from-other-driver.patch
+	patches.megous/drm-bridge-dw-hdmi-Report-HDMI-hotplug-events.patch
+	patches.megous/usb-typec-anx7688-Add-driver-for-ANX7688-USB-C-HDMI-bridge.patch
+	patches.megous/usb-typec-anx7688-Port-to-Linux-6.9.patch
+	patches.megous/usb-typec-anx7688-Port-to-Linux-6.10.patch
+	patches.megous/dt-bindings-axp20x-adc-allow-to-use-TS-pin-as-GPADC.patch
+	patches.megous/iio-adc-axp20x_adc-allow-to-set-TS-pin-to-GPADC-mode.patch
+	patches.megous/power-axp20x_battery-Allow-to-set-target-voltage-to-4.35V.patch
+	patches.megous/power-supply-axp20x_battery-Add-support-for-reporting-OCV.patch
+	patches.megous/regulator-axp20x-Enable-over-temperature-protection-and-16s-res.patch
+	patches.megous/power-supply-axp20x_battery-Setup-thermal-regulation-experiment.patch
+	patches.megous/power-supply-axp20x_battery-Fix-charging-done-detection.patch
+	patches.megous/mfd-axp20x-Add-battery-IRQ-resources.patch
+	patches.megous/power-supply-axp20x_battery-Send-uevents-for-status-changes.patch
+	patches.megous/power-supply-axp20x_battery-Monitor-battery-health.patch
+	patches.megous/power-supply-axp20x-usb-power-Change-Vbus-hold-voltage-to-4.5V.patch
+	patches.megous/power-axp803-Add-interrupts-for-low-battery-power-condition.patch
+	patches.megous/power-supply-axp20x-battery-Support-POWER_SUPPLY_PROP_CHARGE_BE.patch
+	patches.megous/power-supply-axp20x-battery-Enable-poweron-by-RTC-alarm.patch
+	patches.megous/power-supply-axp20x-battery-Add-support-for-POWER_SUPPLY_PROP_E.patch
+	patches.megous/power-supply-Add-support-for-USB_BC_ENABLED-and-USB_DCP_INPUT_C.patch
+	patches.megous/power-supply-axp20x-usb-power-Add-missing-interrupts.patch
+	patches.megous/power-supply-axp20x-battery-Improve-probe-error-reporting.patch
+	patches.megous/sunxi-Use-dev_err_probe-to-handle-EPROBE_DEFER-errors.patch
+	patches.megous/thermal-sun8i-Be-loud-when-probe-fails.patch
+	patches.megous/i2c-mv64xxx-Don-t-make-a-fuss-when-pinctrl-recovery-state-is-no.patch
+	patches.megous/iio-st_sensors-Don-t-report-error-when-the-device-is-not-presen.patch
+	patches.megous/opp-core-Avoid-confusing-error-when-no-regulator-is-defined-in-.patch
+	patches.megous/rtc-Print-which-error-caused-RTC-read-failure.patch
+	patches.megous/arm64-dts-allwinner-a64-pinetab-add-front-camera.patch
+	patches.megous/arm64-allwinner-dts-a64-enable-K101-IM2BYL02-panel-for-PineTab.patch
+	patches.megous/arm64-dts-sun50i-a64-pinetab-Name-sound-card-PineTab.patch
+	patches.megous/arm64-dts-sun50i-a64-pinetab-Add-accelerometer.patch
+	patches.megous/arm64-dts-sun50i-a64-pinetab-enable-RTL8723CS-bluetooth.patch
+	patches.megous/usb-typec-fusb302-Slightly-increase-wait-time-for-BC1.2-result.patch
+	patches.megous/usb-typec-fusb302-Set-the-current-before-enabling-pullups.patch
+	patches.megous/usb-typec-fusb302-Extend-debugging-interface-with-driver-state-.patch
+	patches.megous/usb-typec-fusb302-Retry-reading-of-CC-pins-status-if-activity-i.patch
+	patches.megous/usb-typec-fusb302-More-useful-of-logging-status-on-interrupt.patch
+	patches.megous/usb-typec-fusb302-Update-VBUS-state-even-if-VBUS-interrupt-is-n.patch
+	patches.megous/usb-typec-fusb302-Add-OF-extcon-support.patch
+	patches.megous/usb-typec-fusb302-Fix-register-definitions.patch
+	patches.megous/usb-typec-fusb302-Clear-interrupts-before-we-start-toggling.patch
+	patches.megous/usb-typec-typec-extcon-Add-typec-extcon-bridge-driver.patch
+	patches.megous/usb-typec-typec-extcon-Enable-debugging-for-now.patch
+	patches.megous/usb-typec-typec-extcon-Allow-to-force-reset-on-each-mux-change.patch
+	patches.megous/Revert-usb-typec-tcpm-unregister-existing-source-caps-before-re.patch
+	patches.megous/usb-typec-altmodes-displayport-Respect-DP_CAP_RECEPTACLE-bit.patch
+	patches.megous/usb-typec-tcpm-Unregister-altmodes-before-registering-new-ones.patch
+	patches.megous/usb-typec-tcpm-Fix-PD-devices-capabilities-registration.patch
+	patches.megous/usb-typec-tcpm-Improve-logs.patch
+	patches.megous/Make-microbuttons-on-Orange-Pi-PC-and-PC-2-work-as-power-off-bu.patch
+	patches.megous/Add-support-for-my-private-Sapomat-device.patch
+	patches.megous/ARM-dts-sun8i-h3-orange-pi-one-Enable-all-gpio-header-UARTs.patch
+	patches.megous/mtd-spi-nor-Add-Alliance-memory-support.patch
+	patches.megous/Add-README.md-with-information-and-u-boot-patches.patch
+	patches.megous/Defconfigs-for-all-my-devices.patch

From a987fd3dbb11d451c834e7547cdda5c9f4302213 Mon Sep 17 00:00:00 2001
From: The-going <48602507+The-going@users.noreply.github.com>
Date: Wed, 30 Apr 2025 12:37:10 +0300
Subject: [PATCH 2/7] sunxi-6.14: Add drm patches

---
 ...global-control-reg-for-pad-selection.patch |  41 ++
 ...dts-allwinner-h616-Add-Mali-GPU-node.patch |  61 ++
 ...-add-Display-Engine-3.3-DE33-support.patch |  86 +++
 .../drm-panfrost-Add-PM-runtime-flags.patch   | 111 ++++
 ...-panfrost-add-h616-compatible-string.patch |  43 ++
 ...panfrost-reorder-pd-clk-rst-sequence.patch | 106 ++++
 ...n4i-add-sun50i-h616-hdmi-phy-support.patch | 108 ++++
 ...-de2-Initialize-layer-fields-earlier.patch |  75 +++
 ...rm-sun4i-de2-de3-Change-CSC-argument.patch | 178 ++++++
 ...de2-de3-Merge-CSC-functions-into-one.patch | 221 +++++++
 ...ic-blender-register-reference-functi.patch |  38 ++
 ...sun4i-de2-de3-add-mixer-version-enum.patch | 257 ++++++++
 ...de3-call-csc-setup-also-for-UI-layer.patch |  64 ++
 ...e2-de3-refactor-mixer-initialisation.patch | 121 ++++
 ...ic-register-reference-function-for-l.patch | 117 ++++
 ...m-sun4i-de3-Add-YUV-formatter-module.patch | 164 +++++
 ...drm-sun4i-de3-Implement-AFBC-support.patch | 569 ++++++++++++++++++
 ...de3-add-YUV-support-to-the-DE3-mixer.patch | 126 ++++
 ...un4i-de3-add-YUV-support-to-the-TCON.patch |  83 +++
 ...rt-to-the-color-space-correction-mod.patch | 225 +++++++
 ...ormat-enumeration-function-to-engine.patch |  63 ++
 ...3-add-formatter-flag-to-mixer-config.patch |  53 ++
 ...ine-reference-to-ccsc-setup-function.patch |  54 ++
 ...-add-Display-Engine-3.3-DE33-support.patch | 156 +++++
 ...-add-Display-Engine-3.3-DE33-support.patch |  75 +++
 ...-add-Display-Engine-3.3-DE33-support.patch | 302 ++++++++++
 ...-add-Display-Engine-3.3-DE33-support.patch |  77 +++
 ...n4i-support-YUV-formats-in-VI-scaler.patch | 140 +++++
 ...scaler-refactor-vi_scaler-enablement.patch | 100 +++
 ...-allwinner-add-H616-DE33-bus-binding.patch |  35 ++
 ...llwinner-add-H616-DE33-clock-binding.patch |  32 +
 ...llwinner-add-H616-DE33-mixer-binding.patch |  36 ++
 ...ifrost-Add-Allwinner-H616-compatible.patch |  30 +
 ...power-Add-Allwinner-H6-H616-PRCM-PPU.patch |  67 +++
 ...mdomain-sunxi-add-H6-PRCM-PPU-driver.patch | 249 ++++++++
 ...tch-parent-of-MIPI-DSI-to-periph0-1x.patch |  16 +-
 ...w-to-change-lth_brightness-via-sysfs.patch |  47 +-
 patch/kernel/archive/sunxi-6.14/series.conf   |  49 +-
 patch/kernel/archive/sunxi-6.14/series.drm    |  40 ++
 39 files changed, 4399 insertions(+), 16 deletions(-)
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.drm/add-TCON-global-control-reg-for-pad-selection.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.drm/arm64-dts-allwinner-h616-Add-Mali-GPU-node.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.drm/clk-sunxi-ng-ccu-add-Display-Engine-3.3-DE33-support.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.drm/drm-panfrost-Add-PM-runtime-flags.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.drm/drm-panfrost-add-h616-compatible-string.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.drm/drm-panfrost-reorder-pd-clk-rst-sequence.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-add-sun50i-h616-hdmi-phy-support.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de2-Initialize-layer-fields-earlier.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de2-de3-Change-CSC-argument.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de2-de3-Merge-CSC-functions-into-one.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de2-de3-add-generic-blender-register-reference-functi.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de2-de3-add-mixer-version-enum.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de2-de3-call-csc-setup-also-for-UI-layer.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de2-de3-refactor-mixer-initialisation.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de2-de3-use-generic-register-reference-function-for-l.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de3-Add-YUV-formatter-module.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de3-Implement-AFBC-support.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de3-add-YUV-support-to-the-DE3-mixer.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de3-add-YUV-support-to-the-TCON.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de3-add-YUV-support-to-the-color-space-correction-mod.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de3-add-format-enumeration-function-to-engine.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de3-add-formatter-flag-to-mixer-config.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de3-pass-engine-reference-to-ccsc-setup-function.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de33-csc-add-Display-Engine-3.3-DE33-support.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de33-fmt-add-Display-Engine-3.3-DE33-support.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de33-mixer-add-Display-Engine-3.3-DE33-support.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de33-vi_scaler-add-Display-Engine-3.3-DE33-support.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-support-YUV-formats-in-VI-scaler.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-vi_scaler-refactor-vi_scaler-enablement.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.drm/dt-bindings-allwinner-add-H616-DE33-bus-binding.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.drm/dt-bindings-allwinner-add-H616-DE33-clock-binding.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.drm/dt-bindings-allwinner-add-H616-DE33-mixer-binding.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.drm/dt-bindings-gpu-mali-bifrost-Add-Allwinner-H616-compatible.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.drm/dt-bindings-power-Add-Allwinner-H6-H616-PRCM-PPU.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.drm/pmdomain-sunxi-add-H6-PRCM-PPU-driver.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/series.drm

diff --git a/patch/kernel/archive/sunxi-6.14/patches.drm/add-TCON-global-control-reg-for-pad-selection.patch b/patch/kernel/archive/sunxi-6.14/patches.drm/add-TCON-global-control-reg-for-pad-selection.patch
new file mode 100644
index 000000000000..c1a25e9690ff
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.drm/add-TCON-global-control-reg-for-pad-selection.patch
@@ -0,0 +1,41 @@
+From 86ef31fcb116682d399b9723a7ab66c87e6f2cc5 Mon Sep 17 00:00:00 2001
+From: Stephen Graf <stephen.graf@gmail.com>
+Date: Tue, 18 Feb 2025 05:12:44 +0000
+Subject: add TCON global control reg for pad selection
+
+Signed-off-by: Stephen Graf <stephen.graf@gmail.com>
+---
+ drivers/gpu/drm/sun4i/sun4i_tcon.c | 4 ++++
+ drivers/gpu/drm/sun4i/sun4i_tcon.h | 1 +
+ 2 files changed, 5 insertions(+)
+
+diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
+index af67bf2e6e09..88984572f5c5 100644
+--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
++++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
+@@ -1308,6 +1308,10 @@ static int sun4i_tcon_bind(struct device *dev, struct device *master,
+ 		goto err_free_dclk;
+ 	}
+ 
++	regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG,
++		           SUN4I_TCON_GCTL_PAD_SEL,
++		           SUN4I_TCON_GCTL_PAD_SEL);
++
+ 	if (tcon->quirks->has_channel_0) {
+ 		/*
+ 		 * If we have an LVDS panel connected to the TCON, we should
+diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/sun4i_tcon.h
+index bd4abc90062b..e8d28bad4060 100644
+--- a/drivers/gpu/drm/sun4i/sun4i_tcon.h
++++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h
+@@ -19,6 +19,7 @@
+ 
+ #define SUN4I_TCON_GCTL_REG			0x0
+ #define SUN4I_TCON_GCTL_TCON_ENABLE			BIT(31)
++#define SUN4I_TCON_GCTL_PAD_SEL				BIT(1)
+ #define SUN4I_TCON_GCTL_IOMAP_MASK			BIT(0)
+ #define SUN4I_TCON_GCTL_IOMAP_TCON1			(1 << 0)
+ #define SUN4I_TCON_GCTL_IOMAP_TCON0			(0 << 0)
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.drm/arm64-dts-allwinner-h616-Add-Mali-GPU-node.patch b/patch/kernel/archive/sunxi-6.14/patches.drm/arm64-dts-allwinner-h616-Add-Mali-GPU-node.patch
new file mode 100644
index 000000000000..8a00dac93002
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.drm/arm64-dts-allwinner-h616-Add-Mali-GPU-node.patch
@@ -0,0 +1,61 @@
+From 02dc976a5f62b393f378c056888f121ba1880fc5 Mon Sep 17 00:00:00 2001
+From: Andre Przywara <andre.przywara@arm.com>
+Date: Fri, 21 Feb 2025 00:58:01 +0000
+Subject: arm64: dts: allwinner: h616: Add Mali GPU node
+
+The Allwinner H616 SoC contains a Mali-G31 MP2 GPU, which is of the Mali
+Bifrost family. There is a power domain specifically for that GPU, which
+needs to be enabled to make use of the it.
+
+Add the DT nodes for those two devices, and link them together through
+the "power-domains" property.
+Any board wishing to use the GPU would need to enable the GPU node and
+specify the "mali-supply" regulator.
+
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+---
+ .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 21 +++++++++++++++++++
+ 1 file changed, 21 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+index cdce3dcb8ec0..ceedae9e399b 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+@@ -150,6 +150,21 @@ soc {
+ 		#size-cells = <1>;
+ 		ranges = <0x0 0x0 0x0 0x40000000>;
+ 
++		gpu: gpu@1800000 {
++			compatible = "allwinner,sun50i-h616-mali",
++				     "arm,mali-bifrost";
++			reg = <0x1800000 0x40000>;
++			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
++				     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "job", "mmu", "gpu";
++			clocks = <&ccu CLK_GPU0>, <&ccu CLK_BUS_GPU>;
++			clock-names = "core", "bus";
++			power-domains = <&prcm_ppu 2>;
++			resets = <&ccu RST_BUS_GPU>;
++			status = "disabled";
++		};
++
+ 		crypto: crypto@1904000 {
+ 			compatible = "allwinner,sun50i-h616-crypto";
+ 			reg = <0x01904000 0x800>;
+@@ -874,6 +889,12 @@ r_ccu: clock@7010000 {
+ 			#reset-cells = <1>;
+ 		};
+ 
++		prcm_ppu: power-controller@7010250 {
++			compatible = "allwinner,sun50i-h616-prcm-ppu";
++			reg = <0x07010250 0x10>;
++			#power-domain-cells = <1>;
++		};
++
+ 		nmi_intc: interrupt-controller@7010320 {
+ 			compatible = "allwinner,sun50i-h616-nmi",
+ 				     "allwinner,sun9i-a80-nmi";
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.drm/clk-sunxi-ng-ccu-add-Display-Engine-3.3-DE33-support.patch b/patch/kernel/archive/sunxi-6.14/patches.drm/clk-sunxi-ng-ccu-add-Display-Engine-3.3-DE33-support.patch
new file mode 100644
index 000000000000..6bd5c7665c81
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.drm/clk-sunxi-ng-ccu-add-Display-Engine-3.3-DE33-support.patch
@@ -0,0 +1,86 @@
+From b41f5a9ec8841c0342f101585c64c292019543d2 Mon Sep 17 00:00:00 2001
+From: Ryan Walklin <ryan@testtoast.com>
+Date: Sun, 29 Sep 2024 22:04:54 +1300
+Subject: clk: sunxi-ng: ccu: add Display Engine 3.3 (DE33) support
+
+The DE33 is a newer version of the Allwinner Display Engine IP block,
+found in the H616, H618, H700 and T507 SoCs. DE2 and DE3 are already
+supported by the mainline driver.
+
+The DE33 in the H616 has mixer0 and writeback units. The clocks
+and resets required are identical to the H3 and H5 respectively, so use
+those existing structs for the H616 description.
+
+There are two additional 32-bit registers (at offsets 0x24 and 0x28)
+which require clearing and setting respectively to bring up the
+hardware. The function of these registers is currently unknown, and the
+values are taken from the out-of-tree driver.
+
+Add the required clock description struct and compatible string to the
+DE2 driver.
+
+Signed-off-by: Ryan Walklin <ryan@testtoast.com>
+---
+ drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 25 +++++++++++++++++++++++++
+ 1 file changed, 25 insertions(+)
+
+diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
+index 7683ea08d8e3..83eab6f132aa 100644
+--- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
++++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
+@@ -5,6 +5,7 @@
+ 
+ #include <linux/clk.h>
+ #include <linux/clk-provider.h>
++#include <linux/io.h>
+ #include <linux/module.h>
+ #include <linux/of.h>
+ #include <linux/platform_device.h>
+@@ -239,6 +240,16 @@ static const struct sunxi_ccu_desc sun50i_h5_de2_clk_desc = {
+ 	.num_resets	= ARRAY_SIZE(sun50i_h5_de2_resets),
+ };
+ 
++static const struct sunxi_ccu_desc sun50i_h616_de33_clk_desc = {
++	.ccu_clks	= sun8i_de2_ccu_clks,
++	.num_ccu_clks	= ARRAY_SIZE(sun8i_de2_ccu_clks),
++
++	.hw_clks	= &sun8i_h3_de2_hw_clks,
++
++	.resets		= sun50i_h5_de2_resets,
++	.num_resets	= ARRAY_SIZE(sun50i_h5_de2_resets),
++};
++
+ static int sunxi_de2_clk_probe(struct platform_device *pdev)
+ {
+ 	struct clk *bus_clk, *mod_clk;
+@@ -291,6 +302,16 @@ static int sunxi_de2_clk_probe(struct platform_device *pdev)
+ 		goto err_disable_mod_clk;
+ 	}
+ 
++	/*
++	 * The DE33 requires these additional (unknown) registers set
++	 * during initialisation.
++	 */
++	if (of_device_is_compatible(pdev->dev.of_node,
++				    "allwinner,sun50i-h616-de33-clk")) {
++		writel(0, reg + 0x24);
++		writel(0x0000a980, reg + 0x28);
++	}
++
+ 	ret = devm_sunxi_ccu_probe(&pdev->dev, reg, ccu_desc);
+ 	if (ret)
+ 		goto err_assert_reset;
+@@ -335,6 +356,10 @@ static const struct of_device_id sunxi_de2_clk_ids[] = {
+ 		.compatible = "allwinner,sun50i-h6-de3-clk",
+ 		.data = &sun50i_h5_de2_clk_desc,
+ 	},
++	{
++		.compatible = "allwinner,sun50i-h616-de33-clk",
++		.data = &sun50i_h616_de33_clk_desc,
++	},
+ 	{ }
+ };
+ MODULE_DEVICE_TABLE(of, sunxi_de2_clk_ids);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.drm/drm-panfrost-Add-PM-runtime-flags.patch b/patch/kernel/archive/sunxi-6.14/patches.drm/drm-panfrost-Add-PM-runtime-flags.patch
new file mode 100644
index 000000000000..7284fe0e0014
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.drm/drm-panfrost-Add-PM-runtime-flags.patch
@@ -0,0 +1,111 @@
+From ce56f3f385e0830a1e242f9fca9a82c3067ba03f Mon Sep 17 00:00:00 2001
+From: Philippe Simons <simons.philippe@gmail.com>
+Date: Thu, 13 Mar 2025 00:23:18 +0100
+Subject: drm/panfrost: Add PM runtime flags
+
+Allwinner H616 has a dedicated power domain for its Mali G31.
+
+Currently after probe, the GPU is put in runtime suspend which
+disable the power domain.
+On first usage of GPU, the power domain enable hangs the system.
+
+This series adds the necessary calls to enable the clocks and
+deasserting the reset line after the power domain enabling and
+asserting the reset line and disabling the clocks prior to the
+power domain disabling.
+
+This allows to use the Mali GPU on all Allwinner H616
+boards and devices.
+
+When the GPU is the only device attached to a single power domain,
+core genpd disable and enable it when gpu enter and leave runtime suspend.
+
+Some power-domain requires a sequence before disabled,
+and the reverse when enabled.
+
+Add GPU_PM_RT flag, and implement in
+panfrost_device_runtime_suspend/resume.
+
+Signed-off-by: Philippe Simons <simons.philippe@gmail.com>
+---
+ drivers/gpu/drm/panfrost/panfrost_device.c | 33 ++++++++++++++++++++++
+ drivers/gpu/drm/panfrost/panfrost_device.h |  3 ++
+ 2 files changed, 36 insertions(+)
+
+diff --git a/drivers/gpu/drm/panfrost/panfrost_device.c b/drivers/gpu/drm/panfrost/panfrost_device.c
+index a45e4addcc19..93d48e97ce10 100644
+--- a/drivers/gpu/drm/panfrost/panfrost_device.c
++++ b/drivers/gpu/drm/panfrost/panfrost_device.c
+@@ -406,11 +406,36 @@ void panfrost_device_reset(struct panfrost_device *pfdev)
+ static int panfrost_device_runtime_resume(struct device *dev)
+ {
+ 	struct panfrost_device *pfdev = dev_get_drvdata(dev);
++	int ret;
++
++	if (pfdev->comp->pm_features & BIT(GPU_PM_RT)) {
++		ret = reset_control_deassert(pfdev->rstc);
++		if (ret)
++			return ret;
++
++		ret = clk_enable(pfdev->clock);
++		if (ret)
++			goto err_clk;
++
++		if (pfdev->bus_clock) {
++			ret = clk_enable(pfdev->bus_clock);
++			if (ret)
++				goto err_bus_clk;
++		}
++	}
+ 
+ 	panfrost_device_reset(pfdev);
+ 	panfrost_devfreq_resume(pfdev);
+ 
+ 	return 0;
++
++err_bus_clk:
++	if (pfdev->comp->pm_features & BIT(GPU_PM_RT))
++		clk_disable(pfdev->clock);
++err_clk:
++	if (pfdev->comp->pm_features & BIT(GPU_PM_RT))
++		reset_control_assert(pfdev->rstc);
++	return ret;
+ }
+ 
+ static int panfrost_device_runtime_suspend(struct device *dev)
+@@ -426,6 +451,14 @@ static int panfrost_device_runtime_suspend(struct device *dev)
+ 	panfrost_gpu_suspend_irq(pfdev);
+ 	panfrost_gpu_power_off(pfdev);
+ 
++	if (pfdev->comp->pm_features & BIT(GPU_PM_RT)) {
++		if (pfdev->bus_clock)
++			clk_disable(pfdev->bus_clock);
++
++		clk_disable(pfdev->clock);
++		reset_control_assert(pfdev->rstc);
++	}
++
+ 	return 0;
+ }
+ 
+diff --git a/drivers/gpu/drm/panfrost/panfrost_device.h b/drivers/gpu/drm/panfrost/panfrost_device.h
+index cffcb0ac7c11..861555ceea65 100644
+--- a/drivers/gpu/drm/panfrost/panfrost_device.h
++++ b/drivers/gpu/drm/panfrost/panfrost_device.h
+@@ -36,10 +36,13 @@ enum panfrost_drv_comp_bits {
+  * enum panfrost_gpu_pm - Supported kernel power management features
+  * @GPU_PM_CLK_DIS:  Allow disabling clocks during system suspend
+  * @GPU_PM_VREG_OFF: Allow turning off regulators during system suspend
++ * @GPU_PM_RT: Allow disabling clocks and asserting the reset control during
++ *  system runtime suspend
+  */
+ enum panfrost_gpu_pm {
+ 	GPU_PM_CLK_DIS,
+ 	GPU_PM_VREG_OFF,
++	GPU_PM_RT
+ };
+ 
+ struct panfrost_features {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.drm/drm-panfrost-add-h616-compatible-string.patch b/patch/kernel/archive/sunxi-6.14/patches.drm/drm-panfrost-add-h616-compatible-string.patch
new file mode 100644
index 000000000000..57ea76e9a7fc
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.drm/drm-panfrost-add-h616-compatible-string.patch
@@ -0,0 +1,43 @@
+From 16e3a927918e0c6349c2bfcbe468ee1690eaaaca Mon Sep 17 00:00:00 2001
+From: Philippe Simons <simons.philippe@gmail.com>
+Date: Thu, 13 Mar 2025 00:23:19 +0100
+Subject: drm/panfrost: add h616 compatible string
+
+Tie the Allwinner compatible string to the GPU_PM_RT feature bits that will
+toggle the clocks and the reset line whenever the power domain is changing
+state.
+
+Signed-off-by: Philippe Simons <simons.philippe@gmail.com>
+---
+ drivers/gpu/drm/panfrost/panfrost_drv.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/drivers/gpu/drm/panfrost/panfrost_drv.c b/drivers/gpu/drm/panfrost/panfrost_drv.c
+index 0f3935556ac7..9470c04c5487 100644
+--- a/drivers/gpu/drm/panfrost/panfrost_drv.c
++++ b/drivers/gpu/drm/panfrost/panfrost_drv.c
+@@ -776,6 +776,13 @@ static const struct panfrost_compatible default_data = {
+ 	.pm_domain_names = NULL,
+ };
+ 
++static const struct panfrost_compatible allwinner_h616_data = {
++	.num_supplies = ARRAY_SIZE(default_supplies) - 1,
++	.supply_names = default_supplies,
++	.num_pm_domains = 1,
++	.pm_features = BIT(GPU_PM_RT),
++};
++
+ static const struct panfrost_compatible amlogic_data = {
+ 	.num_supplies = ARRAY_SIZE(default_supplies) - 1,
+ 	.supply_names = default_supplies,
+@@ -859,6 +866,7 @@ static const struct of_device_id dt_match[] = {
+ 	{ .compatible = "mediatek,mt8186-mali", .data = &mediatek_mt8186_data },
+ 	{ .compatible = "mediatek,mt8188-mali", .data = &mediatek_mt8188_data },
+ 	{ .compatible = "mediatek,mt8192-mali", .data = &mediatek_mt8192_data },
++	{ .compatible = "allwinner,sun50i-h616-mali", .data = &allwinner_h616_data },
+ 	{}
+ };
+ MODULE_DEVICE_TABLE(of, dt_match);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.drm/drm-panfrost-reorder-pd-clk-rst-sequence.patch b/patch/kernel/archive/sunxi-6.14/patches.drm/drm-panfrost-reorder-pd-clk-rst-sequence.patch
new file mode 100644
index 000000000000..a63c07fef4a8
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.drm/drm-panfrost-reorder-pd-clk-rst-sequence.patch
@@ -0,0 +1,106 @@
+From 37f8be7eaca786f85cf2a17dfd33227e2ff45780 Mon Sep 17 00:00:00 2001
+From: Philippe Simons <simons.philippe@gmail.com>
+Date: Thu, 3 Apr 2025 07:52:10 +0200
+Subject: drm/panfrost: reorder pd/clk/rst sequence
+
+According to Mali manuals, the powerup sequence should be
+enable pd, asserting the reset then enabling the clock and
+the reverse for powerdown.
+
+Signed-off-by: Philippe Simons <simons.philippe@gmail.com>
+---
+ drivers/gpu/drm/panfrost/panfrost_device.c | 38 +++++++++++-----------
+ 1 file changed, 19 insertions(+), 19 deletions(-)
+
+diff --git a/drivers/gpu/drm/panfrost/panfrost_device.c b/drivers/gpu/drm/panfrost/panfrost_device.c
+index 93d48e97ce10..5d35076b2e6d 100644
+--- a/drivers/gpu/drm/panfrost/panfrost_device.c
++++ b/drivers/gpu/drm/panfrost/panfrost_device.c
+@@ -209,10 +209,20 @@ int panfrost_device_init(struct panfrost_device *pfdev)
+ 
+ 	spin_lock_init(&pfdev->cycle_counter.lock);
+ 
++	err = panfrost_pm_domain_init(pfdev);
++	if (err)
++		return err;
++
++	err = panfrost_reset_init(pfdev);
++	if (err) {
++		dev_err(pfdev->dev, "reset init failed %d\n", err);
++		goto out_pm_domain;
++	}
++
+ 	err = panfrost_clk_init(pfdev);
+ 	if (err) {
+ 		dev_err(pfdev->dev, "clk init failed %d\n", err);
+-		return err;
++		goto out_reset;
+ 	}
+ 
+ 	err = panfrost_devfreq_init(pfdev);
+@@ -229,25 +239,15 @@ int panfrost_device_init(struct panfrost_device *pfdev)
+ 			goto out_devfreq;
+ 	}
+ 
+-	err = panfrost_reset_init(pfdev);
+-	if (err) {
+-		dev_err(pfdev->dev, "reset init failed %d\n", err);
+-		goto out_regulator;
+-	}
+-
+-	err = panfrost_pm_domain_init(pfdev);
+-	if (err)
+-		goto out_reset;
+-
+ 	pfdev->iomem = devm_platform_ioremap_resource(pfdev->pdev, 0);
+ 	if (IS_ERR(pfdev->iomem)) {
+ 		err = PTR_ERR(pfdev->iomem);
+-		goto out_pm_domain;
++		goto out_regulator;
+ 	}
+ 
+ 	err = panfrost_gpu_init(pfdev);
+ 	if (err)
+-		goto out_pm_domain;
++		goto out_regulator;
+ 
+ 	err = panfrost_mmu_init(pfdev);
+ 	if (err)
+@@ -268,16 +268,16 @@ int panfrost_device_init(struct panfrost_device *pfdev)
+ 	panfrost_mmu_fini(pfdev);
+ out_gpu:
+ 	panfrost_gpu_fini(pfdev);
+-out_pm_domain:
+-	panfrost_pm_domain_fini(pfdev);
+-out_reset:
+-	panfrost_reset_fini(pfdev);
+ out_regulator:
+ 	panfrost_regulator_fini(pfdev);
+ out_devfreq:
+ 	panfrost_devfreq_fini(pfdev);
+ out_clk:
+ 	panfrost_clk_fini(pfdev);
++out_reset:
++	panfrost_reset_fini(pfdev);
++out_pm_domain:
++	panfrost_pm_domain_fini(pfdev);
+ 	return err;
+ }
+ 
+@@ -287,11 +287,11 @@ void panfrost_device_fini(struct panfrost_device *pfdev)
+ 	panfrost_job_fini(pfdev);
+ 	panfrost_mmu_fini(pfdev);
+ 	panfrost_gpu_fini(pfdev);
+-	panfrost_pm_domain_fini(pfdev);
+-	panfrost_reset_fini(pfdev);
+ 	panfrost_devfreq_fini(pfdev);
+ 	panfrost_regulator_fini(pfdev);
+ 	panfrost_clk_fini(pfdev);
++	panfrost_reset_fini(pfdev);
++	panfrost_pm_domain_fini(pfdev);
+ }
+ 
+ #define PANFROST_EXCEPTION(id) \
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-add-sun50i-h616-hdmi-phy-support.patch b/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-add-sun50i-h616-hdmi-phy-support.patch
new file mode 100644
index 000000000000..d1e28132f06e
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-add-sun50i-h616-hdmi-phy-support.patch
@@ -0,0 +1,108 @@
+From 6c8bbaf43b8eaf62d4682ce66a35fc7f341f4a13 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Mon, 10 Feb 2025 15:45:13 +0300
+Subject: [PATCH] drm: sun4i: add sun50i-h616-hdmi-phy support
+
+---
+ drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 71 ++++++++++++++++++++++++++
+ 1 file changed, 71 insertions(+)
+
+diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
+index 4fa69c463dc4..8a07052037c3 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
++++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
+@@ -124,6 +124,66 @@ static const struct dw_hdmi_phy_config sun50i_h6_phy_config[] = {
+ 	{ ~0UL,	     0x0000, 0x0000, 0x0000}
+ };
+ 
++static const struct dw_hdmi_mpll_config sun50i_h616_mpll_cfg[] = {
++	{
++		27000000, {
++			{0x00b3, 0x0003},
++			{0x2153, 0x0003},
++			{0x40f3, 0x0003},
++		},
++	}, {
++		74250000, {
++			{0x0072, 0x0003},
++			{0x2145, 0x0003},
++			{0x4061, 0x0003},
++		},
++	}, {
++		148500000, {
++			{0x0051, 0x0003},
++			{0x214c, 0x0003},
++			{0x4064, 0x0003},
++		},
++	}, {
++		297000000, {
++			{0x0040, 0x0003},
++			{0x3b4c, 0x0003},
++			{0x5a64, 0x0003},
++		},
++	}, {
++		594000000, {
++			{0x1a40, 0x0003},
++			{0x3b4c, 0x0003},
++			{0x5a64, 0x0003},
++		},
++	}, {
++		~0UL, {
++			{0x0000, 0x0000},
++			{0x0000, 0x0000},
++			{0x0000, 0x0000},
++		},
++	}
++};
++
++static const struct dw_hdmi_curr_ctrl sun50i_h616_cur_ctr[] = {
++	/* pixelclk    bpp8    bpp10   bpp12 */
++	{ 27000000,  { 0x0012, 0x0000, 0x0000 }, },
++	{ 74250000,  { 0x0013, 0x0013, 0x0013 }, },
++	{ 148500000, { 0x0019, 0x0019, 0x0019 }, },
++	{ 297000000, { 0x0019, 0x001b, 0x0019 }, },
++	{ 594000000, { 0x0010, 0x0010, 0x0010 }, },
++	{ ~0UL,      { 0x0000, 0x0000, 0x0000 }, }
++};
++
++static const struct dw_hdmi_phy_config sun50i_h616_phy_config[] = {
++	/*pixelclk   symbol   term   vlev*/
++	{27000000,  0x8009, 0x0007, 0x02b0},
++	{74250000,  0x8019, 0x0004, 0x0290},
++	{148500000, 0x8019, 0x0004, 0x0290},
++	{297000000, 0x8039, 0x0004, 0x022b},
++	{594000000, 0x8029, 0x0000, 0x008a},
++	{~0UL,      0x0000, 0x0000, 0x0000}
++};
++
+ static void sun8i_hdmi_phy_set_polarity(struct sun8i_hdmi_phy *phy,
+ 					const struct drm_display_mode *mode)
+ {
+@@ -626,6 +686,13 @@ static const struct sun8i_hdmi_phy_variant sun50i_h6_hdmi_phy = {
+ 	.phy_init = &sun50i_hdmi_phy_init_h6,
+ };
+ 
++static const struct sun8i_hdmi_phy_variant sun50i_h616_hdmi_phy = {
++	.cur_ctr = sun50i_h616_cur_ctr,
++	.mpll_cfg = sun50i_h616_mpll_cfg,
++	.phy_cfg = sun50i_h616_phy_config,
++	.phy_init = &sun50i_hdmi_phy_init_h6,
++};
++
+ static const struct of_device_id sun8i_hdmi_phy_of_table[] = {
+ 	{
+ 		.compatible = "allwinner,sun8i-a83t-hdmi-phy",
+@@ -647,6 +714,10 @@ static const struct of_device_id sun8i_hdmi_phy_of_table[] = {
+ 		.compatible = "allwinner,sun50i-h6-hdmi-phy",
+ 		.data = &sun50i_h6_hdmi_phy,
+ 	},
++	{
++		.compatible = "allwinner,sun50i-h616-hdmi-phy",
++		.data = &sun50i_h616_hdmi_phy,
++	},
+ 	{ /* sentinel */ }
+ };
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de2-Initialize-layer-fields-earlier.patch b/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de2-Initialize-layer-fields-earlier.patch
new file mode 100644
index 000000000000..f5555d4b0d2e
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de2-Initialize-layer-fields-earlier.patch
@@ -0,0 +1,75 @@
+From 5c2859b3cccd1b1b3f1700fd70c06770f418247a Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sun, 29 Sep 2024 22:04:36 +1300
+Subject: drm: sun4i: de2: Initialize layer fields earlier
+
+drm_universal_plane_init() can already call some callbacks, like
+format_mod_supported, during initialization. Because of that, fields
+should be initialized beforehand.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+Co-developed-by: Ryan Walklin <ryan@testtoast.com>
+Signed-off-by: Ryan Walklin <ryan@testtoast.com>
+Reviewed-by: Chen-Yu Tsai <wens@csie.org>
+---
+ drivers/gpu/drm/sun4i/sun8i_ui_layer.c | 9 +++++----
+ drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 9 +++++----
+ 2 files changed, 10 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
+index aa987bca1dbb..cb9b694fef10 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
++++ b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
+@@ -295,6 +295,11 @@ struct sun8i_layer *sun8i_ui_layer_init_one(struct drm_device *drm,
+ 	if (!layer)
+ 		return ERR_PTR(-ENOMEM);
+ 
++	layer->mixer = mixer;
++	layer->type = SUN8I_LAYER_TYPE_UI;
++	layer->channel = channel;
++	layer->overlay = 0;
++
+ 	if (index == 0)
+ 		type = DRM_PLANE_TYPE_PRIMARY;
+ 
+@@ -325,10 +330,6 @@ struct sun8i_layer *sun8i_ui_layer_init_one(struct drm_device *drm,
+ 	}
+ 
+ 	drm_plane_helper_add(&layer->plane, &sun8i_ui_layer_helper_funcs);
+-	layer->mixer = mixer;
+-	layer->type = SUN8I_LAYER_TYPE_UI;
+-	layer->channel = channel;
+-	layer->overlay = 0;
+ 
+ 	return layer;
+ }
+diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
+index f3a5329351ca..3c657b069d1f 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
++++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
+@@ -478,6 +478,11 @@ struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_device *drm,
+ 	if (!layer)
+ 		return ERR_PTR(-ENOMEM);
+ 
++	layer->mixer = mixer;
++	layer->type = SUN8I_LAYER_TYPE_VI;
++	layer->channel = index;
++	layer->overlay = 0;
++
+ 	if (mixer->cfg->is_de3) {
+ 		formats = sun8i_vi_layer_de3_formats;
+ 		format_count = ARRAY_SIZE(sun8i_vi_layer_de3_formats);
+@@ -536,10 +541,6 @@ struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_device *drm,
+ 	}
+ 
+ 	drm_plane_helper_add(&layer->plane, &sun8i_vi_layer_helper_funcs);
+-	layer->mixer = mixer;
+-	layer->type = SUN8I_LAYER_TYPE_VI;
+-	layer->channel = index;
+-	layer->overlay = 0;
+ 
+ 	return layer;
+ }
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de2-de3-Change-CSC-argument.patch b/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de2-de3-Change-CSC-argument.patch
new file mode 100644
index 000000000000..9125e4fa06cb
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de2-de3-Change-CSC-argument.patch
@@ -0,0 +1,178 @@
+From 54669ac67e47835b8cc3eea215026385a0050567 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sun, 29 Sep 2024 22:04:33 +1300
+Subject: drm: sun4i: de2/de3: Change CSC argument
+
+Currently, CSC module takes care only for converting YUV to RGB.
+However, DE3 is more suited to work in YUV color space. Change CSC mode
+argument to format type to be more neutral. New argument only tells
+layer format type and doesn't imply output type.
+
+This commit doesn't make any functional change.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+Signed-off-by: Ryan Walklin <ryan@testtoast.com>
+Reviewed-by: Andre Przywara <andre.przywara@arm.com>
+---
+ drivers/gpu/drm/sun4i/sun8i_csc.c      | 22 +++++++++++-----------
+ drivers/gpu/drm/sun4i/sun8i_csc.h      | 10 +++++-----
+ drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 16 ++++++++--------
+ 3 files changed, 24 insertions(+), 24 deletions(-)
+
+diff --git a/drivers/gpu/drm/sun4i/sun8i_csc.c b/drivers/gpu/drm/sun4i/sun8i_csc.c
+index 58480d8e4f70..6ebd1c3aa3ab 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_csc.c
++++ b/drivers/gpu/drm/sun4i/sun8i_csc.c
+@@ -108,7 +108,7 @@ static const u32 yuv2rgb_de3[2][3][12] = {
+ };
+ 
+ static void sun8i_csc_set_coefficients(struct regmap *map, u32 base,
+-				       enum sun8i_csc_mode mode,
++				       enum format_type fmt_type,
+ 				       enum drm_color_encoding encoding,
+ 				       enum drm_color_range range)
+ {
+@@ -118,12 +118,12 @@ static void sun8i_csc_set_coefficients(struct regmap *map, u32 base,
+ 
+ 	table = yuv2rgb[range][encoding];
+ 
+-	switch (mode) {
+-	case SUN8I_CSC_MODE_YUV2RGB:
++	switch (fmt_type) {
++	case FORMAT_TYPE_YUV:
+ 		base_reg = SUN8I_CSC_COEFF(base, 0);
+ 		regmap_bulk_write(map, base_reg, table, 12);
+ 		break;
+-	case SUN8I_CSC_MODE_YVU2RGB:
++	case FORMAT_TYPE_YVU:
+ 		for (i = 0; i < 12; i++) {
+ 			if ((i & 3) == 1)
+ 				base_reg = SUN8I_CSC_COEFF(base, i + 1);
+@@ -141,7 +141,7 @@ static void sun8i_csc_set_coefficients(struct regmap *map, u32 base,
+ }
+ 
+ static void sun8i_de3_ccsc_set_coefficients(struct regmap *map, int layer,
+-					    enum sun8i_csc_mode mode,
++					    enum format_type fmt_type,
+ 					    enum drm_color_encoding encoding,
+ 					    enum drm_color_range range)
+ {
+@@ -151,12 +151,12 @@ static void sun8i_de3_ccsc_set_coefficients(struct regmap *map, int layer,
+ 
+ 	table = yuv2rgb_de3[range][encoding];
+ 
+-	switch (mode) {
+-	case SUN8I_CSC_MODE_YUV2RGB:
++	switch (fmt_type) {
++	case FORMAT_TYPE_YUV:
+ 		addr = SUN50I_MIXER_BLEND_CSC_COEFF(DE3_BLD_BASE, layer, 0);
+ 		regmap_bulk_write(map, addr, table, 12);
+ 		break;
+-	case SUN8I_CSC_MODE_YVU2RGB:
++	case FORMAT_TYPE_YVU:
+ 		for (i = 0; i < 12; i++) {
+ 			if ((i & 3) == 1)
+ 				addr = SUN50I_MIXER_BLEND_CSC_COEFF(DE3_BLD_BASE,
+@@ -206,7 +206,7 @@ static void sun8i_de3_ccsc_enable(struct regmap *map, int layer, bool enable)
+ }
+ 
+ void sun8i_csc_set_ccsc_coefficients(struct sun8i_mixer *mixer, int layer,
+-				     enum sun8i_csc_mode mode,
++				     enum format_type fmt_type,
+ 				     enum drm_color_encoding encoding,
+ 				     enum drm_color_range range)
+ {
+@@ -214,14 +214,14 @@ void sun8i_csc_set_ccsc_coefficients(struct sun8i_mixer *mixer, int layer,
+ 
+ 	if (mixer->cfg->is_de3) {
+ 		sun8i_de3_ccsc_set_coefficients(mixer->engine.regs, layer,
+-						mode, encoding, range);
++						fmt_type, encoding, range);
+ 		return;
+ 	}
+ 
+ 	base = ccsc_base[mixer->cfg->ccsc][layer];
+ 
+ 	sun8i_csc_set_coefficients(mixer->engine.regs, base,
+-				   mode, encoding, range);
++				   fmt_type, encoding, range);
+ }
+ 
+ void sun8i_csc_enable_ccsc(struct sun8i_mixer *mixer, int layer, bool enable)
+diff --git a/drivers/gpu/drm/sun4i/sun8i_csc.h b/drivers/gpu/drm/sun4i/sun8i_csc.h
+index 828b86fd0cab..7322770f39f0 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_csc.h
++++ b/drivers/gpu/drm/sun4i/sun8i_csc.h
+@@ -22,14 +22,14 @@ struct sun8i_mixer;
+ 
+ #define SUN8I_CSC_CTRL_EN		BIT(0)
+ 
+-enum sun8i_csc_mode {
+-	SUN8I_CSC_MODE_OFF,
+-	SUN8I_CSC_MODE_YUV2RGB,
+-	SUN8I_CSC_MODE_YVU2RGB,
++enum format_type {
++	FORMAT_TYPE_RGB,
++	FORMAT_TYPE_YUV,
++	FORMAT_TYPE_YVU,
+ };
+ 
+ void sun8i_csc_set_ccsc_coefficients(struct sun8i_mixer *mixer, int layer,
+-				     enum sun8i_csc_mode mode,
++				     enum format_type fmt_type,
+ 				     enum drm_color_encoding encoding,
+ 				     enum drm_color_range range);
+ void sun8i_csc_enable_ccsc(struct sun8i_mixer *mixer, int layer, bool enable);
+diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
+index 9c09d9c08496..8a80934e928f 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
++++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
+@@ -193,19 +193,19 @@ static int sun8i_vi_layer_update_coord(struct sun8i_mixer *mixer, int channel,
+ 	return 0;
+ }
+ 
+-static u32 sun8i_vi_layer_get_csc_mode(const struct drm_format_info *format)
++static u32 sun8i_vi_layer_get_format_type(const struct drm_format_info *format)
+ {
+ 	if (!format->is_yuv)
+-		return SUN8I_CSC_MODE_OFF;
++		return FORMAT_TYPE_RGB;
+ 
+ 	switch (format->format) {
+ 	case DRM_FORMAT_YVU411:
+ 	case DRM_FORMAT_YVU420:
+ 	case DRM_FORMAT_YVU422:
+ 	case DRM_FORMAT_YVU444:
+-		return SUN8I_CSC_MODE_YVU2RGB;
++		return FORMAT_TYPE_YVU;
+ 	default:
+-		return SUN8I_CSC_MODE_YUV2RGB;
++		return FORMAT_TYPE_YUV;
+ 	}
+ }
+ 
+@@ -213,7 +213,7 @@ static int sun8i_vi_layer_update_formats(struct sun8i_mixer *mixer, int channel,
+ 					 int overlay, struct drm_plane *plane)
+ {
+ 	struct drm_plane_state *state = plane->state;
+-	u32 val, ch_base, csc_mode, hw_fmt;
++	u32 val, ch_base, fmt_type, hw_fmt;
+ 	const struct drm_format_info *fmt;
+ 	int ret;
+ 
+@@ -231,9 +231,9 @@ static int sun8i_vi_layer_update_formats(struct sun8i_mixer *mixer, int channel,
+ 			   SUN8I_MIXER_CHAN_VI_LAYER_ATTR(ch_base, overlay),
+ 			   SUN8I_MIXER_CHAN_VI_LAYER_ATTR_FBFMT_MASK, val);
+ 
+-	csc_mode = sun8i_vi_layer_get_csc_mode(fmt);
+-	if (csc_mode != SUN8I_CSC_MODE_OFF) {
+-		sun8i_csc_set_ccsc_coefficients(mixer, channel, csc_mode,
++	fmt_type = sun8i_vi_layer_get_format_type(fmt);
++	if (fmt_type != FORMAT_TYPE_RGB) {
++		sun8i_csc_set_ccsc_coefficients(mixer, channel, fmt_type,
+ 						state->color_encoding,
+ 						state->color_range);
+ 		sun8i_csc_enable_ccsc(mixer, channel, true);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de2-de3-Merge-CSC-functions-into-one.patch b/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de2-de3-Merge-CSC-functions-into-one.patch
new file mode 100644
index 000000000000..a487d9d899f4
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de2-de3-Merge-CSC-functions-into-one.patch
@@ -0,0 +1,221 @@
+From 09744193cdcf400e5a4c54d9309acf5aea3a591c Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sun, 29 Sep 2024 22:04:34 +1300
+Subject: drm: sun4i: de2/de3: Merge CSC functions into one
+
+At the moment the colour space conversion is handled by two functions:
+one to setup the conversion parameters, and another one to enable the
+conversion. Merging both into one gives more flexibility for upcoming
+extensions to support whole YUV pipelines, in the DE33.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+Signed-off-by: Ryan Walklin <ryan@testtoast.com>
+Reviewed-by: Andre Przywara <andre.przywara@arm.com>
+---
+ drivers/gpu/drm/sun4i/sun8i_csc.c      | 89 ++++++++++----------------
+ drivers/gpu/drm/sun4i/sun8i_csc.h      |  9 ++-
+ drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 11 +---
+ 3 files changed, 40 insertions(+), 69 deletions(-)
+
+diff --git a/drivers/gpu/drm/sun4i/sun8i_csc.c b/drivers/gpu/drm/sun4i/sun8i_csc.c
+index 6ebd1c3aa3ab..0dcbc0866ae8 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_csc.c
++++ b/drivers/gpu/drm/sun4i/sun8i_csc.c
+@@ -107,23 +107,28 @@ static const u32 yuv2rgb_de3[2][3][12] = {
+ 	},
+ };
+ 
+-static void sun8i_csc_set_coefficients(struct regmap *map, u32 base,
+-				       enum format_type fmt_type,
+-				       enum drm_color_encoding encoding,
+-				       enum drm_color_range range)
++static void sun8i_csc_setup(struct regmap *map, u32 base,
++			    enum format_type fmt_type,
++			    enum drm_color_encoding encoding,
++			    enum drm_color_range range)
+ {
++	u32 base_reg, val;
+ 	const u32 *table;
+-	u32 base_reg;
+ 	int i;
+ 
+ 	table = yuv2rgb[range][encoding];
+ 
+ 	switch (fmt_type) {
++	case FORMAT_TYPE_RGB:
++		val = 0;
++		break;
+ 	case FORMAT_TYPE_YUV:
++		val = SUN8I_CSC_CTRL_EN;
+ 		base_reg = SUN8I_CSC_COEFF(base, 0);
+ 		regmap_bulk_write(map, base_reg, table, 12);
+ 		break;
+ 	case FORMAT_TYPE_YVU:
++		val = SUN8I_CSC_CTRL_EN;
+ 		for (i = 0; i < 12; i++) {
+ 			if ((i & 3) == 1)
+ 				base_reg = SUN8I_CSC_COEFF(base, i + 1);
+@@ -135,28 +140,37 @@ static void sun8i_csc_set_coefficients(struct regmap *map, u32 base,
+ 		}
+ 		break;
+ 	default:
++		val = 0;
+ 		DRM_WARN("Wrong CSC mode specified.\n");
+ 		return;
+ 	}
++
++	regmap_write(map, SUN8I_CSC_CTRL(base), val);
+ }
+ 
+-static void sun8i_de3_ccsc_set_coefficients(struct regmap *map, int layer,
+-					    enum format_type fmt_type,
+-					    enum drm_color_encoding encoding,
+-					    enum drm_color_range range)
++static void sun8i_de3_ccsc_setup(struct regmap *map, int layer,
++				 enum format_type fmt_type,
++				 enum drm_color_encoding encoding,
++				 enum drm_color_range range)
+ {
++	u32 addr, val, mask;
+ 	const u32 *table;
+-	u32 addr;
+ 	int i;
+ 
++	mask = SUN50I_MIXER_BLEND_CSC_CTL_EN(layer);
+ 	table = yuv2rgb_de3[range][encoding];
+ 
+ 	switch (fmt_type) {
++	case FORMAT_TYPE_RGB:
++		val = 0;
++		break;
+ 	case FORMAT_TYPE_YUV:
++		val = mask;
+ 		addr = SUN50I_MIXER_BLEND_CSC_COEFF(DE3_BLD_BASE, layer, 0);
+ 		regmap_bulk_write(map, addr, table, 12);
+ 		break;
+ 	case FORMAT_TYPE_YVU:
++		val = mask;
+ 		for (i = 0; i < 12; i++) {
+ 			if ((i & 3) == 1)
+ 				addr = SUN50I_MIXER_BLEND_CSC_COEFF(DE3_BLD_BASE,
+@@ -173,67 +187,30 @@ static void sun8i_de3_ccsc_set_coefficients(struct regmap *map, int layer,
+ 		}
+ 		break;
+ 	default:
++		val = 0;
+ 		DRM_WARN("Wrong CSC mode specified.\n");
+ 		return;
+ 	}
+-}
+-
+-static void sun8i_csc_enable(struct regmap *map, u32 base, bool enable)
+-{
+-	u32 val;
+-
+-	if (enable)
+-		val = SUN8I_CSC_CTRL_EN;
+-	else
+-		val = 0;
+-
+-	regmap_update_bits(map, SUN8I_CSC_CTRL(base), SUN8I_CSC_CTRL_EN, val);
+-}
+-
+-static void sun8i_de3_ccsc_enable(struct regmap *map, int layer, bool enable)
+-{
+-	u32 val, mask;
+-
+-	mask = SUN50I_MIXER_BLEND_CSC_CTL_EN(layer);
+-
+-	if (enable)
+-		val = mask;
+-	else
+-		val = 0;
+ 
+ 	regmap_update_bits(map, SUN50I_MIXER_BLEND_CSC_CTL(DE3_BLD_BASE),
+ 			   mask, val);
+ }
+ 
+-void sun8i_csc_set_ccsc_coefficients(struct sun8i_mixer *mixer, int layer,
+-				     enum format_type fmt_type,
+-				     enum drm_color_encoding encoding,
+-				     enum drm_color_range range)
+-{
+-	u32 base;
+-
+-	if (mixer->cfg->is_de3) {
+-		sun8i_de3_ccsc_set_coefficients(mixer->engine.regs, layer,
+-						fmt_type, encoding, range);
+-		return;
+-	}
+-
+-	base = ccsc_base[mixer->cfg->ccsc][layer];
+-
+-	sun8i_csc_set_coefficients(mixer->engine.regs, base,
+-				   fmt_type, encoding, range);
+-}
+-
+-void sun8i_csc_enable_ccsc(struct sun8i_mixer *mixer, int layer, bool enable)
++void sun8i_csc_set_ccsc(struct sun8i_mixer *mixer, int layer,
++			enum format_type fmt_type,
++			enum drm_color_encoding encoding,
++			enum drm_color_range range)
+ {
+ 	u32 base;
+ 
+ 	if (mixer->cfg->is_de3) {
+-		sun8i_de3_ccsc_enable(mixer->engine.regs, layer, enable);
++		sun8i_de3_ccsc_setup(mixer->engine.regs, layer,
++				     fmt_type, encoding, range);
+ 		return;
+ 	}
+ 
+ 	base = ccsc_base[mixer->cfg->ccsc][layer];
+ 
+-	sun8i_csc_enable(mixer->engine.regs, base, enable);
++	sun8i_csc_setup(mixer->engine.regs, base,
++			fmt_type, encoding, range);
+ }
+diff --git a/drivers/gpu/drm/sun4i/sun8i_csc.h b/drivers/gpu/drm/sun4i/sun8i_csc.h
+index 7322770f39f0..b7546e06e315 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_csc.h
++++ b/drivers/gpu/drm/sun4i/sun8i_csc.h
+@@ -28,10 +28,9 @@ enum format_type {
+ 	FORMAT_TYPE_YVU,
+ };
+ 
+-void sun8i_csc_set_ccsc_coefficients(struct sun8i_mixer *mixer, int layer,
+-				     enum format_type fmt_type,
+-				     enum drm_color_encoding encoding,
+-				     enum drm_color_range range);
+-void sun8i_csc_enable_ccsc(struct sun8i_mixer *mixer, int layer, bool enable);
++void sun8i_csc_set_ccsc(struct sun8i_mixer *mixer, int layer,
++			enum format_type fmt_type,
++			enum drm_color_encoding encoding,
++			enum drm_color_range range);
+ 
+ #endif
+diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
+index 8a80934e928f..f3a5329351ca 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
++++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
+@@ -232,14 +232,9 @@ static int sun8i_vi_layer_update_formats(struct sun8i_mixer *mixer, int channel,
+ 			   SUN8I_MIXER_CHAN_VI_LAYER_ATTR_FBFMT_MASK, val);
+ 
+ 	fmt_type = sun8i_vi_layer_get_format_type(fmt);
+-	if (fmt_type != FORMAT_TYPE_RGB) {
+-		sun8i_csc_set_ccsc_coefficients(mixer, channel, fmt_type,
+-						state->color_encoding,
+-						state->color_range);
+-		sun8i_csc_enable_ccsc(mixer, channel, true);
+-	} else {
+-		sun8i_csc_enable_ccsc(mixer, channel, false);
+-	}
++	sun8i_csc_set_ccsc(mixer, channel, fmt_type,
++			   state->color_encoding,
++			   state->color_range);
+ 
+ 	if (!fmt->is_yuv)
+ 		val = SUN8I_MIXER_CHAN_VI_LAYER_ATTR_RGB_MODE;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de2-de3-add-generic-blender-register-reference-functi.patch b/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de2-de3-add-generic-blender-register-reference-functi.patch
new file mode 100644
index 000000000000..2757ba5e21fd
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de2-de3-add-generic-blender-register-reference-functi.patch
@@ -0,0 +1,38 @@
+From 45d06599927825fe1fa3c374508d6d0c8c9f9f52 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sun, 29 Sep 2024 22:04:48 +1300
+Subject: drm: sun4i: de2/de3: add generic blender register reference function
+
+The DE2 and DE3 engines have a blender register range within the
+mixer engine register map, whereas the DE33 separates this out into
+a separate display group.
+
+Prepare for this by adding a function to look the blender reference up,
+with a subsequent patch to add a conditional based on the DE type.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+Signed-off-by: Ryan Walklin <ryan@testtoast.com>
+---
+ drivers/gpu/drm/sun4i/sun8i_mixer.h | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h
+index 82956cb97cfd..75facc7d1fa6 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_mixer.h
++++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h
+@@ -224,6 +224,12 @@ sun8i_blender_base(struct sun8i_mixer *mixer)
+ 	return mixer->cfg->de_type == sun8i_mixer_de3 ? DE3_BLD_BASE : DE2_BLD_BASE;
+ }
+ 
++static inline struct regmap *
++sun8i_blender_regmap(struct sun8i_mixer *mixer)
++{
++	return mixer->engine.regs;
++}
++
+ static inline u32
+ sun8i_channel_base(struct sun8i_mixer *mixer, int channel)
+ {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de2-de3-add-mixer-version-enum.patch b/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de2-de3-add-mixer-version-enum.patch
new file mode 100644
index 000000000000..0df4a242c2ee
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de2-de3-add-mixer-version-enum.patch
@@ -0,0 +1,257 @@
+From b49e4fb3439c50eb6effc559366b3e88e2ac2f27 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sun, 29 Sep 2024 22:04:45 +1300
+Subject: drm: sun4i: de2/de3: add mixer version enum
+
+The Allwinner DE2 and DE3 display engine mixers are currently identified
+by a simple boolean flag. This will not scale to support additional DE
+variants.
+
+Convert the boolean flag to an enum.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+Signed-off-by: Ryan Walklin <ryan@testtoast.com>
+Reviewed-by: Andre Przywara <andre.przywara@arm.com>
+---
+ drivers/gpu/drm/sun4i/sun8i_csc.c       |  2 +-
+ drivers/gpu/drm/sun4i/sun8i_mixer.c     | 14 ++++++++++++--
+ drivers/gpu/drm/sun4i/sun8i_mixer.h     | 11 ++++++++---
+ drivers/gpu/drm/sun4i/sun8i_ui_scaler.c |  2 +-
+ drivers/gpu/drm/sun4i/sun8i_vi_layer.c  |  8 ++++----
+ drivers/gpu/drm/sun4i/sun8i_vi_scaler.c |  4 ++--
+ 6 files changed, 28 insertions(+), 13 deletions(-)
+
+diff --git a/drivers/gpu/drm/sun4i/sun8i_csc.c b/drivers/gpu/drm/sun4i/sun8i_csc.c
+index e12a81fa9108..2d5a2cf7cba2 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_csc.c
++++ b/drivers/gpu/drm/sun4i/sun8i_csc.c
+@@ -365,7 +365,7 @@ void sun8i_csc_set_ccsc(struct sun8i_mixer *mixer, int layer,
+ {
+ 	u32 base;
+ 
+-	if (mixer->cfg->is_de3) {
++	if (mixer->cfg->de_type == sun8i_mixer_de3) {
+ 		sun8i_de3_ccsc_setup(&mixer->engine, layer,
+ 				     fmt_type, encoding, range);
+ 		return;
+diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
+index a50c583852ed..16e018aa4aae 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
++++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
+@@ -584,7 +584,7 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,
+ 	base = sun8i_blender_base(mixer);
+ 
+ 	/* Reset registers and disable unused sub-engines */
+-	if (mixer->cfg->is_de3) {
++	if (mixer->cfg->de_type == sun8i_mixer_de3) {
+ 		for (i = 0; i < DE3_MIXER_UNIT_SIZE; i += 4)
+ 			regmap_write(mixer->engine.regs, i, 0);
+ 
+@@ -675,6 +675,7 @@ static void sun8i_mixer_remove(struct platform_device *pdev)
+ 
+ static const struct sun8i_mixer_cfg sun8i_a83t_mixer0_cfg = {
+ 	.ccsc		= CCSC_MIXER0_LAYOUT,
++	.de_type	= sun8i_mixer_de2,
+ 	.scaler_mask	= 0xf,
+ 	.scanline_yuv	= 2048,
+ 	.ui_num		= 3,
+@@ -683,6 +684,7 @@ static const struct sun8i_mixer_cfg sun8i_a83t_mixer0_cfg = {
+ 
+ static const struct sun8i_mixer_cfg sun8i_a83t_mixer1_cfg = {
+ 	.ccsc		= CCSC_MIXER1_LAYOUT,
++	.de_type	= sun8i_mixer_de2,
+ 	.scaler_mask	= 0x3,
+ 	.scanline_yuv	= 2048,
+ 	.ui_num		= 1,
+@@ -691,6 +693,7 @@ static const struct sun8i_mixer_cfg sun8i_a83t_mixer1_cfg = {
+ 
+ static const struct sun8i_mixer_cfg sun8i_h3_mixer0_cfg = {
+ 	.ccsc		= CCSC_MIXER0_LAYOUT,
++	.de_type	= sun8i_mixer_de2,
+ 	.mod_rate	= 432000000,
+ 	.scaler_mask	= 0xf,
+ 	.scanline_yuv	= 2048,
+@@ -700,6 +703,7 @@ static const struct sun8i_mixer_cfg sun8i_h3_mixer0_cfg = {
+ 
+ static const struct sun8i_mixer_cfg sun8i_r40_mixer0_cfg = {
+ 	.ccsc		= CCSC_MIXER0_LAYOUT,
++	.de_type	= sun8i_mixer_de2,
+ 	.mod_rate	= 297000000,
+ 	.scaler_mask	= 0xf,
+ 	.scanline_yuv	= 2048,
+@@ -709,6 +713,7 @@ static const struct sun8i_mixer_cfg sun8i_r40_mixer0_cfg = {
+ 
+ static const struct sun8i_mixer_cfg sun8i_r40_mixer1_cfg = {
+ 	.ccsc		= CCSC_MIXER1_LAYOUT,
++	.de_type	= sun8i_mixer_de2,
+ 	.mod_rate	= 297000000,
+ 	.scaler_mask	= 0x3,
+ 	.scanline_yuv	= 2048,
+@@ -717,6 +722,7 @@ static const struct sun8i_mixer_cfg sun8i_r40_mixer1_cfg = {
+ };
+ 
+ static const struct sun8i_mixer_cfg sun8i_v3s_mixer_cfg = {
++	.de_type = sun8i_mixer_de2,
+ 	.vi_num = 2,
+ 	.ui_num = 1,
+ 	.scaler_mask = 0x3,
+@@ -727,6 +733,7 @@ static const struct sun8i_mixer_cfg sun8i_v3s_mixer_cfg = {
+ 
+ static const struct sun8i_mixer_cfg sun20i_d1_mixer0_cfg = {
+ 	.ccsc		= CCSC_D1_MIXER0_LAYOUT,
++	.de_type	= sun8i_mixer_de2,
+ 	.mod_rate	= 297000000,
+ 	.scaler_mask	= 0x3,
+ 	.scanline_yuv	= 2048,
+@@ -736,6 +743,7 @@ static const struct sun8i_mixer_cfg sun20i_d1_mixer0_cfg = {
+ 
+ static const struct sun8i_mixer_cfg sun20i_d1_mixer1_cfg = {
+ 	.ccsc		= CCSC_MIXER1_LAYOUT,
++	.de_type	= sun8i_mixer_de2,
+ 	.mod_rate	= 297000000,
+ 	.scaler_mask	= 0x1,
+ 	.scanline_yuv	= 1024,
+@@ -745,6 +753,7 @@ static const struct sun8i_mixer_cfg sun20i_d1_mixer1_cfg = {
+ 
+ static const struct sun8i_mixer_cfg sun50i_a64_mixer0_cfg = {
+ 	.ccsc		= CCSC_MIXER0_LAYOUT,
++	.de_type	= sun8i_mixer_de2,
+ 	.mod_rate	= 297000000,
+ 	.scaler_mask	= 0xf,
+ 	.scanline_yuv	= 4096,
+@@ -754,6 +763,7 @@ static const struct sun8i_mixer_cfg sun50i_a64_mixer0_cfg = {
+ 
+ static const struct sun8i_mixer_cfg sun50i_a64_mixer1_cfg = {
+ 	.ccsc		= CCSC_MIXER1_LAYOUT,
++	.de_type	= sun8i_mixer_de2,
+ 	.mod_rate	= 297000000,
+ 	.scaler_mask	= 0x3,
+ 	.scanline_yuv	= 2048,
+@@ -763,7 +773,7 @@ static const struct sun8i_mixer_cfg sun50i_a64_mixer1_cfg = {
+ 
+ static const struct sun8i_mixer_cfg sun50i_h6_mixer0_cfg = {
+ 	.ccsc		= CCSC_MIXER0_LAYOUT,
+-	.is_de3		= true,
++	.de_type	= sun8i_mixer_de3,
+ 	.has_formatter	= 1,
+ 	.mod_rate	= 600000000,
+ 	.scaler_mask	= 0xf,
+diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h
+index 8417b8fef2e1..82956cb97cfd 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_mixer.h
++++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h
+@@ -151,6 +151,11 @@ enum {
+ 	CCSC_D1_MIXER0_LAYOUT,
+ };
+ 
++enum sun8i_mixer_type {
++	sun8i_mixer_de2,
++	sun8i_mixer_de3,
++};
++
+ /**
+  * struct sun8i_mixer_cfg - mixer HW configuration
+  * @vi_num: number of VI channels
+@@ -172,7 +177,7 @@ struct sun8i_mixer_cfg {
+ 	int		scaler_mask;
+ 	int		ccsc;
+ 	unsigned long	mod_rate;
+-	unsigned int	is_de3 : 1;
++	unsigned int	de_type;
+ 	unsigned int    has_formatter : 1;
+ 	unsigned int	scanline_yuv;
+ };
+@@ -216,13 +221,13 @@ engine_to_sun8i_mixer(struct sunxi_engine *engine)
+ static inline u32
+ sun8i_blender_base(struct sun8i_mixer *mixer)
+ {
+-	return mixer->cfg->is_de3 ? DE3_BLD_BASE : DE2_BLD_BASE;
++	return mixer->cfg->de_type == sun8i_mixer_de3 ? DE3_BLD_BASE : DE2_BLD_BASE;
+ }
+ 
+ static inline u32
+ sun8i_channel_base(struct sun8i_mixer *mixer, int channel)
+ {
+-	if (mixer->cfg->is_de3)
++	if (mixer->cfg->de_type == sun8i_mixer_de3)
+ 		return DE3_CH_BASE + channel * DE3_CH_SIZE;
+ 	else
+ 		return DE2_CH_BASE + channel * DE2_CH_SIZE;
+diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_scaler.c b/drivers/gpu/drm/sun4i/sun8i_ui_scaler.c
+index ae0806bccac7..504ffa0971a4 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_ui_scaler.c
++++ b/drivers/gpu/drm/sun4i/sun8i_ui_scaler.c
+@@ -93,7 +93,7 @@ static u32 sun8i_ui_scaler_base(struct sun8i_mixer *mixer, int channel)
+ {
+ 	int vi_num = mixer->cfg->vi_num;
+ 
+-	if (mixer->cfg->is_de3)
++	if (mixer->cfg->de_type == sun8i_mixer_de3)
+ 		return DE3_VI_SCALER_UNIT_BASE +
+ 		       DE3_VI_SCALER_UNIT_SIZE * vi_num +
+ 		       DE3_UI_SCALER_UNIT_SIZE * (channel - vi_num);
+diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
+index 3c657b069d1f..4647e9bcccaa 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
++++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
+@@ -25,7 +25,7 @@ static void sun8i_vi_layer_update_alpha(struct sun8i_mixer *mixer, int channel,
+ 
+ 	ch_base = sun8i_channel_base(mixer, channel);
+ 
+-	if (mixer->cfg->is_de3) {
++	if (mixer->cfg->de_type >= sun8i_mixer_de3) {
+ 		mask = SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA_MASK |
+ 		       SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA_MODE_MASK;
+ 		val = SUN50I_MIXER_CHAN_VI_LAYER_ATTR_ALPHA
+@@ -483,7 +483,7 @@ struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_device *drm,
+ 	layer->channel = index;
+ 	layer->overlay = 0;
+ 
+-	if (mixer->cfg->is_de3) {
++	if (mixer->cfg->de_type >= sun8i_mixer_de3) {
+ 		formats = sun8i_vi_layer_de3_formats;
+ 		format_count = ARRAY_SIZE(sun8i_vi_layer_de3_formats);
+ 	} else {
+@@ -507,7 +507,7 @@ struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_device *drm,
+ 
+ 	plane_cnt = mixer->cfg->ui_num + mixer->cfg->vi_num;
+ 
+-	if (mixer->cfg->vi_num == 1 || mixer->cfg->is_de3) {
++	if (mixer->cfg->vi_num == 1 || mixer->cfg->de_type >= sun8i_mixer_de3) {
+ 		ret = drm_plane_create_alpha_property(&layer->plane);
+ 		if (ret) {
+ 			dev_err(drm->dev, "Couldn't add alpha property\n");
+@@ -524,7 +524,7 @@ struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_device *drm,
+ 
+ 	supported_encodings = BIT(DRM_COLOR_YCBCR_BT601) |
+ 			      BIT(DRM_COLOR_YCBCR_BT709);
+-	if (mixer->cfg->is_de3)
++	if (mixer->cfg->de_type >= sun8i_mixer_de3)
+ 		supported_encodings |= BIT(DRM_COLOR_YCBCR_BT2020);
+ 
+ 	supported_ranges = BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
+diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c b/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c
+index 2e49a6e5f1f1..aa346c3beb30 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c
++++ b/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c
+@@ -835,7 +835,7 @@ static const u32 bicubic4coefftab32[480] = {
+ 
+ static u32 sun8i_vi_scaler_base(struct sun8i_mixer *mixer, int channel)
+ {
+-	if (mixer->cfg->is_de3)
++	if (mixer->cfg->de_type == sun8i_mixer_de3)
+ 		return DE3_VI_SCALER_UNIT_BASE +
+ 		       DE3_VI_SCALER_UNIT_SIZE * channel;
+ 	else
+@@ -982,7 +982,7 @@ void sun8i_vi_scaler_setup(struct sun8i_mixer *mixer, int layer,
+ 		cvphase = vphase;
+ 	}
+ 
+-	if (mixer->cfg->is_de3) {
++	if (mixer->cfg->de_type >= sun8i_mixer_de3) {
+ 		u32 val;
+ 
+ 		if (format->hsub == 1 && format->vsub == 1)
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de2-de3-call-csc-setup-also-for-UI-layer.patch b/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de2-de3-call-csc-setup-also-for-UI-layer.patch
new file mode 100644
index 000000000000..96847a05dce8
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de2-de3-call-csc-setup-also-for-UI-layer.patch
@@ -0,0 +1,64 @@
+From 000c586a34ad82e4673e6dfda5457147b0d85606 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sun, 29 Sep 2024 22:04:35 +1300
+Subject: drm: sun4i: de2/de3: call csc setup also for UI layer
+
+Currently, only VI layer calls CSC setup function. This comes from DE2
+limitation, which doesn't have CSC unit for UI layers. However, DE3 has
+separate CSC units for each layer. This allows display pipeline to make
+output signal in different color spaces. To support both use cases, add
+a call to CSC setup function also in UI layer code. For DE2, this will
+be a no-op, but it will allow DE3 to output signal in multiple formats.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+Signed-off-by: Ryan Walklin <ryan@testtoast.com>
+---
+ drivers/gpu/drm/sun4i/sun8i_csc.c      | 8 +++++---
+ drivers/gpu/drm/sun4i/sun8i_ui_layer.c | 6 ++++++
+ 2 files changed, 11 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/sun4i/sun8i_csc.c b/drivers/gpu/drm/sun4i/sun8i_csc.c
+index 0dcbc0866ae8..68d955c63b05 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_csc.c
++++ b/drivers/gpu/drm/sun4i/sun8i_csc.c
+@@ -209,8 +209,10 @@ void sun8i_csc_set_ccsc(struct sun8i_mixer *mixer, int layer,
+ 		return;
+ 	}
+ 
+-	base = ccsc_base[mixer->cfg->ccsc][layer];
++	if (layer < mixer->cfg->vi_num) {
++		base = ccsc_base[mixer->cfg->ccsc][layer];
+ 
+-	sun8i_csc_setup(mixer->engine.regs, base,
+-			fmt_type, encoding, range);
++		sun8i_csc_setup(mixer->engine.regs, base,
++				fmt_type, encoding, range);
++	}
+ }
+diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
+index b90e5edef4e8..aa987bca1dbb 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
++++ b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
+@@ -20,6 +20,7 @@
+ #include <drm/drm_gem_dma_helper.h>
+ #include <drm/drm_probe_helper.h>
+ 
++#include "sun8i_csc.h"
+ #include "sun8i_mixer.h"
+ #include "sun8i_ui_layer.h"
+ #include "sun8i_ui_scaler.h"
+@@ -135,6 +136,11 @@ static int sun8i_ui_layer_update_formats(struct sun8i_mixer *mixer, int channel,
+ 			   SUN8I_MIXER_CHAN_UI_LAYER_ATTR(ch_base, overlay),
+ 			   SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_MASK, val);
+ 
++	/* Note: encoding and range arguments are ignored for RGB */
++	sun8i_csc_set_ccsc(mixer, channel, FORMAT_TYPE_RGB,
++			   DRM_COLOR_YCBCR_BT601,
++			   DRM_COLOR_YCBCR_FULL_RANGE);
++
+ 	return 0;
+ }
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de2-de3-refactor-mixer-initialisation.patch b/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de2-de3-refactor-mixer-initialisation.patch
new file mode 100644
index 000000000000..4357b5b775ab
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de2-de3-refactor-mixer-initialisation.patch
@@ -0,0 +1,121 @@
+From 18890b5c9dbf9270b7f0e42875d6b8bd14ee6624 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sun, 29 Sep 2024 22:04:46 +1300
+Subject: drm: sun4i: de2/de3: refactor mixer initialisation
+
+Now that the DE variant can be selected by enum, take the oppportunity
+to factor out some common initialisation code to a separate function.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+Signed-off-by: Ryan Walklin <ryan@testtoast.com>
+Reviewed-by: Andre Przywara <andre.przywara@arm.com>
+---
+ drivers/gpu/drm/sun4i/sun8i_mixer.c | 64 +++++++++++++++--------------
+ 1 file changed, 34 insertions(+), 30 deletions(-)
+
+diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
+index 16e018aa4aae..18745af08954 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
++++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
+@@ -468,6 +468,38 @@ static int sun8i_mixer_of_get_id(struct device_node *node)
+ 	return of_ep.id;
+ }
+ 
++static void sun8i_mixer_init(struct sun8i_mixer *mixer)
++{
++	unsigned int base = sun8i_blender_base(mixer);
++	int plane_cnt, i;
++
++	/* Enable the mixer */
++	regmap_write(mixer->engine.regs, SUN8I_MIXER_GLOBAL_CTL,
++		     SUN8I_MIXER_GLOBAL_CTL_RT_EN);
++
++	/* Set background color to black */
++	regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_BKCOLOR(base),
++		     SUN8I_MIXER_BLEND_COLOR_BLACK);
++
++	/*
++	 * Set fill color of bottom plane to black. Generally not needed
++	 * except when VI plane is at bottom (zpos = 0) and enabled.
++	 */
++	regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base),
++		     SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN(0));
++	regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_ATTR_FCOLOR(base, 0),
++		     SUN8I_MIXER_BLEND_COLOR_BLACK);
++
++	plane_cnt = mixer->cfg->vi_num + mixer->cfg->ui_num;
++	for (i = 0; i < plane_cnt; i++)
++		regmap_write(mixer->engine.regs,
++			     SUN8I_MIXER_BLEND_MODE(base, i),
++			     SUN8I_MIXER_BLEND_MODE_DEF);
++
++	regmap_update_bits(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base),
++			   SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK, 0);
++}
++
+ static int sun8i_mixer_bind(struct device *dev, struct device *master,
+ 			      void *data)
+ {
+@@ -476,8 +508,6 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,
+ 	struct sun4i_drv *drv = drm->dev_private;
+ 	struct sun8i_mixer *mixer;
+ 	void __iomem *regs;
+-	unsigned int base;
+-	int plane_cnt;
+ 	int i, ret;
+ 
+ 	/*
+@@ -581,8 +611,6 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,
+ 
+ 	list_add_tail(&mixer->engine.list, &drv->engine_list);
+ 
+-	base = sun8i_blender_base(mixer);
+-
+ 	/* Reset registers and disable unused sub-engines */
+ 	if (mixer->cfg->de_type == sun8i_mixer_de3) {
+ 		for (i = 0; i < DE3_MIXER_UNIT_SIZE; i += 4)
+@@ -598,7 +626,7 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,
+ 		regmap_write(mixer->engine.regs, SUN50I_MIXER_FMT_EN, 0);
+ 		regmap_write(mixer->engine.regs, SUN50I_MIXER_CDC0_EN, 0);
+ 		regmap_write(mixer->engine.regs, SUN50I_MIXER_CDC1_EN, 0);
+-	} else {
++	} else if (mixer->cfg->de_type == sun8i_mixer_de2) {
+ 		for (i = 0; i < DE2_MIXER_UNIT_SIZE; i += 4)
+ 			regmap_write(mixer->engine.regs, i, 0);
+ 
+@@ -611,31 +639,7 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,
+ 		regmap_write(mixer->engine.regs, SUN8I_MIXER_DCSC_EN, 0);
+ 	}
+ 
+-	/* Enable the mixer */
+-	regmap_write(mixer->engine.regs, SUN8I_MIXER_GLOBAL_CTL,
+-		     SUN8I_MIXER_GLOBAL_CTL_RT_EN);
+-
+-	/* Set background color to black */
+-	regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_BKCOLOR(base),
+-		     SUN8I_MIXER_BLEND_COLOR_BLACK);
+-
+-	/*
+-	 * Set fill color of bottom plane to black. Generally not needed
+-	 * except when VI plane is at bottom (zpos = 0) and enabled.
+-	 */
+-	regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base),
+-		     SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN(0));
+-	regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_ATTR_FCOLOR(base, 0),
+-		     SUN8I_MIXER_BLEND_COLOR_BLACK);
+-
+-	plane_cnt = mixer->cfg->vi_num + mixer->cfg->ui_num;
+-	for (i = 0; i < plane_cnt; i++)
+-		regmap_write(mixer->engine.regs,
+-			     SUN8I_MIXER_BLEND_MODE(base, i),
+-			     SUN8I_MIXER_BLEND_MODE_DEF);
+-
+-	regmap_update_bits(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base),
+-			   SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK, 0);
++	sun8i_mixer_init(mixer);
+ 
+ 	return 0;
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de2-de3-use-generic-register-reference-function-for-l.patch b/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de2-de3-use-generic-register-reference-function-for-l.patch
new file mode 100644
index 000000000000..ae503d937cb6
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de2-de3-use-generic-register-reference-function-for-l.patch
@@ -0,0 +1,117 @@
+From a756d6b4ac645ac3c18d5758faec068b3c8819a6 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sun, 29 Sep 2024 22:04:49 +1300
+Subject: drm: sun4i: de2/de3: use generic register reference function for
+ layer configuration
+
+Use the new blender register lookup function where required in the layer
+commit and update code.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+Signed-off-by: Ryan Walklin <ryan@testtoast.com>
+---
+ drivers/gpu/drm/sun4i/sun8i_mixer.c    | 5 +++--
+ drivers/gpu/drm/sun4i/sun8i_ui_layer.c | 7 +++++--
+ drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 6 ++++--
+ 3 files changed, 12 insertions(+), 6 deletions(-)
+
+diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
+index 18745af08954..600084286b39 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
++++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
+@@ -277,6 +277,7 @@ static void sun8i_mixer_commit(struct sunxi_engine *engine,
+ {
+ 	struct sun8i_mixer *mixer = engine_to_sun8i_mixer(engine);
+ 	u32 bld_base = sun8i_blender_base(mixer);
++	struct regmap *bld_regs = sun8i_blender_regmap(mixer);
+ 	struct drm_plane_state *plane_state;
+ 	struct drm_plane *plane;
+ 	u32 route = 0, pipe_en = 0;
+@@ -316,8 +317,8 @@ static void sun8i_mixer_commit(struct sunxi_engine *engine,
+ 		pipe_en |= SUN8I_MIXER_BLEND_PIPE_CTL_EN(zpos);
+ 	}
+ 
+-	regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_ROUTE(bld_base), route);
+-	regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(bld_base),
++	regmap_write(bld_regs, SUN8I_MIXER_BLEND_ROUTE(bld_base), route);
++	regmap_write(bld_regs, SUN8I_MIXER_BLEND_PIPE_CTL(bld_base),
+ 		     pipe_en | SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN(0));
+ 
+ 	regmap_write(engine->regs, SUN8I_MIXER_GLOBAL_DBUFF,
+diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
+index cb9b694fef10..7f1231cf0f01 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
++++ b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
+@@ -24,6 +24,7 @@
+ #include "sun8i_mixer.h"
+ #include "sun8i_ui_layer.h"
+ #include "sun8i_ui_scaler.h"
++#include "sun8i_vi_scaler.h"
+ 
+ static void sun8i_ui_layer_update_alpha(struct sun8i_mixer *mixer, int channel,
+ 					int overlay, struct drm_plane *plane)
+@@ -52,6 +53,7 @@ static int sun8i_ui_layer_update_coord(struct sun8i_mixer *mixer, int channel,
+ {
+ 	struct drm_plane_state *state = plane->state;
+ 	u32 src_w, src_h, dst_w, dst_h;
++	struct regmap *bld_regs;
+ 	u32 bld_base, ch_base;
+ 	u32 outsize, insize;
+ 	u32 hphase, vphase;
+@@ -60,6 +62,7 @@ static int sun8i_ui_layer_update_coord(struct sun8i_mixer *mixer, int channel,
+ 			 channel, overlay);
+ 
+ 	bld_base = sun8i_blender_base(mixer);
++	bld_regs = sun8i_blender_regmap(mixer);
+ 	ch_base = sun8i_channel_base(mixer, channel);
+ 
+ 	src_w = drm_rect_width(&state->src) >> 16;
+@@ -104,10 +107,10 @@ static int sun8i_ui_layer_update_coord(struct sun8i_mixer *mixer, int channel,
+ 	DRM_DEBUG_DRIVER("Layer destination coordinates X: %d Y: %d\n",
+ 			 state->dst.x1, state->dst.y1);
+ 	DRM_DEBUG_DRIVER("Layer destination size W: %d H: %d\n", dst_w, dst_h);
+-	regmap_write(mixer->engine.regs,
++	regmap_write(bld_regs,
+ 		     SUN8I_MIXER_BLEND_ATTR_COORD(bld_base, zpos),
+ 		     SUN8I_MIXER_COORD(state->dst.x1, state->dst.y1));
+-	regmap_write(mixer->engine.regs,
++	regmap_write(bld_regs,
+ 		     SUN8I_MIXER_BLEND_ATTR_INSIZE(bld_base, zpos),
+ 		     outsize);
+ 
+diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
+index e348fd0a3d81..d19349eecc9d 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
++++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
+@@ -55,6 +55,7 @@ static int sun8i_vi_layer_update_coord(struct sun8i_mixer *mixer, int channel,
+ 	struct drm_plane_state *state = plane->state;
+ 	const struct drm_format_info *format = state->fb->format;
+ 	u32 src_w, src_h, dst_w, dst_h;
++	struct regmap *bld_regs;
+ 	u32 bld_base, ch_base;
+ 	u32 outsize, insize;
+ 	u32 hphase, vphase;
+@@ -66,6 +67,7 @@ static int sun8i_vi_layer_update_coord(struct sun8i_mixer *mixer, int channel,
+ 			 channel, overlay);
+ 
+ 	bld_base = sun8i_blender_base(mixer);
++	bld_regs = sun8i_blender_regmap(mixer);
+ 	ch_base = sun8i_channel_base(mixer, channel);
+ 
+ 	src_w = drm_rect_width(&state->src) >> 16;
+@@ -182,10 +184,10 @@ static int sun8i_vi_layer_update_coord(struct sun8i_mixer *mixer, int channel,
+ 	DRM_DEBUG_DRIVER("Layer destination coordinates X: %d Y: %d\n",
+ 			 state->dst.x1, state->dst.y1);
+ 	DRM_DEBUG_DRIVER("Layer destination size W: %d H: %d\n", dst_w, dst_h);
+-	regmap_write(mixer->engine.regs,
++	regmap_write(bld_regs,
+ 		     SUN8I_MIXER_BLEND_ATTR_COORD(bld_base, zpos),
+ 		     SUN8I_MIXER_COORD(state->dst.x1, state->dst.y1));
+-	regmap_write(mixer->engine.regs,
++	regmap_write(bld_regs,
+ 		     SUN8I_MIXER_BLEND_ATTR_INSIZE(bld_base, zpos),
+ 		     outsize);
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de3-Add-YUV-formatter-module.patch b/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de3-Add-YUV-formatter-module.patch
new file mode 100644
index 000000000000..14f17b6d5d69
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de3-Add-YUV-formatter-module.patch
@@ -0,0 +1,164 @@
+From 8bdcc131fedb576a8db65bb6e87ca8742660add0 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sun, 29 Sep 2024 22:04:37 +1300
+Subject: drm: sun4i: de3: Add YUV formatter module
+
+The display engine formatter (FMT) module is present in the DE3 engine
+and provides YUV444 to YUV422/YUV420 conversion, format re-mapping and
+color depth conversion.
+
+Add support for this module.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+Signed-off-by: Ryan Walklin <ryan@testtoast.com>
+---
+ drivers/gpu/drm/sun4i/Makefile     |  3 +-
+ drivers/gpu/drm/sun4i/sun50i_fmt.c | 82 ++++++++++++++++++++++++++++++
+ drivers/gpu/drm/sun4i/sun50i_fmt.h | 32 ++++++++++++
+ 3 files changed, 116 insertions(+), 1 deletion(-)
+ create mode 100644 drivers/gpu/drm/sun4i/sun50i_fmt.c
+ create mode 100644 drivers/gpu/drm/sun4i/sun50i_fmt.h
+
+diff --git a/drivers/gpu/drm/sun4i/Makefile b/drivers/gpu/drm/sun4i/Makefile
+index bad7497a0d11..3f516329f51e 100644
+--- a/drivers/gpu/drm/sun4i/Makefile
++++ b/drivers/gpu/drm/sun4i/Makefile
+@@ -16,7 +16,8 @@ sun8i-drm-hdmi-y		+= sun8i_hdmi_phy_clk.o
+ 
+ sun8i-mixer-y			+= sun8i_mixer.o sun8i_ui_layer.o \
+ 				   sun8i_vi_layer.o sun8i_ui_scaler.o \
+-				   sun8i_vi_scaler.o sun8i_csc.o
++				   sun8i_vi_scaler.o sun8i_csc.o \
++				   sun50i_fmt.o
+ 
+ sun4i-tcon-y			+= sun4i_crtc.o
+ sun4i-tcon-y			+= sun4i_tcon_dclk.o
+diff --git a/drivers/gpu/drm/sun4i/sun50i_fmt.c b/drivers/gpu/drm/sun4i/sun50i_fmt.c
+new file mode 100644
+index 000000000000..050a8716ae86
+--- /dev/null
++++ b/drivers/gpu/drm/sun4i/sun50i_fmt.c
+@@ -0,0 +1,82 @@
++// SPDX-License-Identifier: GPL-2.0-or-later
++/*
++ * Copyright (C) Jernej Skrabec <jernej.skrabec@gmail.com>
++ */
++
++#include <uapi/linux/media-bus-format.h>
++
++#include "sun50i_fmt.h"
++
++static bool sun50i_fmt_is_10bit(u32 format)
++{
++	switch (format) {
++	case MEDIA_BUS_FMT_RGB101010_1X30:
++	case MEDIA_BUS_FMT_YUV10_1X30:
++	case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
++	case MEDIA_BUS_FMT_UYVY10_1X20:
++		return true;
++	default:
++		return false;
++	}
++}
++
++static u32 sun50i_fmt_get_colorspace(u32 format)
++{
++	switch (format) {
++	case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
++	case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
++		return SUN50I_FMT_CS_YUV420;
++	case MEDIA_BUS_FMT_UYVY8_1X16:
++	case MEDIA_BUS_FMT_UYVY10_1X20:
++		return SUN50I_FMT_CS_YUV422;
++	default:
++		return SUN50I_FMT_CS_YUV444RGB;
++	}
++}
++
++static void sun50i_fmt_de3_limits(u32 *limits, u32 colorspace, bool bit10)
++{
++	if (colorspace != SUN50I_FMT_CS_YUV444RGB) {
++		limits[0] = SUN50I_FMT_LIMIT(64, 940);
++		limits[1] = SUN50I_FMT_LIMIT(64, 960);
++		limits[2] = SUN50I_FMT_LIMIT(64, 960);
++	} else if (bit10) {
++		limits[0] = SUN50I_FMT_LIMIT(0, 1023);
++		limits[1] = SUN50I_FMT_LIMIT(0, 1023);
++		limits[2] = SUN50I_FMT_LIMIT(0, 1023);
++	} else {
++		limits[0] = SUN50I_FMT_LIMIT(0, 1021);
++		limits[1] = SUN50I_FMT_LIMIT(0, 1021);
++		limits[2] = SUN50I_FMT_LIMIT(0, 1021);
++	}
++}
++
++void sun50i_fmt_setup(struct sun8i_mixer *mixer, u16 width,
++		      u16 height, u32 format)
++{
++	u32 colorspace, limit[3], base;
++	struct regmap *regs;
++	bool bit10;
++
++	colorspace = sun50i_fmt_get_colorspace(format);
++	bit10 = sun50i_fmt_is_10bit(format);
++	base = SUN50I_FMT_DE3;
++	regs = sun8i_blender_regmap(mixer);
++
++	sun50i_fmt_de3_limits(limit, colorspace, bit10);
++
++	regmap_write(regs, SUN50I_FMT_CTRL(base), 0);
++
++	regmap_write(regs, SUN50I_FMT_SIZE(base),
++		     SUN8I_MIXER_SIZE(width, height));
++	regmap_write(regs, SUN50I_FMT_SWAP(base), 0);
++	regmap_write(regs, SUN50I_FMT_DEPTH(base), bit10);
++	regmap_write(regs, SUN50I_FMT_FORMAT(base), colorspace);
++	regmap_write(regs, SUN50I_FMT_COEF(base), 0);
++
++	regmap_write(regs, SUN50I_FMT_LMT_Y(base), limit[0]);
++	regmap_write(regs, SUN50I_FMT_LMT_C0(base), limit[1]);
++	regmap_write(regs, SUN50I_FMT_LMT_C1(base), limit[2]);
++
++	regmap_write(regs, SUN50I_FMT_CTRL(base), 1);
++}
+diff --git a/drivers/gpu/drm/sun4i/sun50i_fmt.h b/drivers/gpu/drm/sun4i/sun50i_fmt.h
+new file mode 100644
+index 000000000000..4127f7206aad
+--- /dev/null
++++ b/drivers/gpu/drm/sun4i/sun50i_fmt.h
+@@ -0,0 +1,32 @@
++/* SPDX-License-Identifier: GPL-2.0-or-later */
++/*
++ * Copyright (C) Jernej Skrabec <jernej.skrabec@gmail.com>
++ */
++
++#ifndef _SUN50I_FMT_H_
++#define _SUN50I_FMT_H_
++
++#include "sun8i_mixer.h"
++
++#define SUN50I_FMT_DE3 0xa8000
++
++#define SUN50I_FMT_CTRL(base)   ((base) + 0x00)
++#define SUN50I_FMT_SIZE(base)   ((base) + 0x04)
++#define SUN50I_FMT_SWAP(base)   ((base) + 0x08)
++#define SUN50I_FMT_DEPTH(base)  ((base) + 0x0c)
++#define SUN50I_FMT_FORMAT(base) ((base) + 0x10)
++#define SUN50I_FMT_COEF(base)   ((base) + 0x14)
++#define SUN50I_FMT_LMT_Y(base)  ((base) + 0x20)
++#define SUN50I_FMT_LMT_C0(base) ((base) + 0x24)
++#define SUN50I_FMT_LMT_C1(base) ((base) + 0x28)
++
++#define SUN50I_FMT_LIMIT(low, high) (((high) << 16) | (low))
++
++#define SUN50I_FMT_CS_YUV444RGB 0
++#define SUN50I_FMT_CS_YUV422    1
++#define SUN50I_FMT_CS_YUV420    2
++
++void sun50i_fmt_setup(struct sun8i_mixer *mixer, u16 width,
++		      u16 height, u32 format);
++
++#endif
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de3-Implement-AFBC-support.patch b/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de3-Implement-AFBC-support.patch
new file mode 100644
index 000000000000..e4d21564c020
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de3-Implement-AFBC-support.patch
@@ -0,0 +1,569 @@
+From 0788787d1240dba85ecbbdb559cb46d413975656 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sun, 29 Sep 2024 22:04:50 +1300
+Subject: drm: sun4i: de3: Implement AFBC support
+
+Buffers, compressed with AFBC, are supported by the DE3 and above, and
+are generally more efficient for memory transfers. Add support for them.
+
+Currently it's implemented only for VI layers, but vendor code and
+documentation suggest UI layers can have them too. However, I haven't
+observed any SoC with such feature.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+Signed-off-by: Ryan Walklin <ryan@testtoast.com>
+---
+ drivers/gpu/drm/sun4i/Makefile         |   2 +-
+ drivers/gpu/drm/sun4i/sun50i_afbc.c    | 250 +++++++++++++++++++++++++
+ drivers/gpu/drm/sun4i/sun50i_afbc.h    |  87 +++++++++
+ drivers/gpu/drm/sun4i/sun8i_vi_layer.c |  84 +++++++--
+ 4 files changed, 409 insertions(+), 14 deletions(-)
+ create mode 100644 drivers/gpu/drm/sun4i/sun50i_afbc.c
+ create mode 100644 drivers/gpu/drm/sun4i/sun50i_afbc.h
+
+diff --git a/drivers/gpu/drm/sun4i/Makefile b/drivers/gpu/drm/sun4i/Makefile
+index 3f516329f51e..78290f1660fb 100644
+--- a/drivers/gpu/drm/sun4i/Makefile
++++ b/drivers/gpu/drm/sun4i/Makefile
+@@ -17,7 +17,7 @@ sun8i-drm-hdmi-y		+= sun8i_hdmi_phy_clk.o
+ sun8i-mixer-y			+= sun8i_mixer.o sun8i_ui_layer.o \
+ 				   sun8i_vi_layer.o sun8i_ui_scaler.o \
+ 				   sun8i_vi_scaler.o sun8i_csc.o \
+-				   sun50i_fmt.o
++				   sun50i_fmt.o sun50i_afbc.o
+ 
+ sun4i-tcon-y			+= sun4i_crtc.o
+ sun4i-tcon-y			+= sun4i_tcon_dclk.o
+diff --git a/drivers/gpu/drm/sun4i/sun50i_afbc.c b/drivers/gpu/drm/sun4i/sun50i_afbc.c
+new file mode 100644
+index 000000000000..b55e1c553371
+--- /dev/null
++++ b/drivers/gpu/drm/sun4i/sun50i_afbc.c
+@@ -0,0 +1,250 @@
++// SPDX-License-Identifier: GPL-2.0-or-later
++/*
++ * Copyright (C) Jernej Skrabec <jernej.skrabec@gmail.com>
++ */
++
++#include <drm/drm_blend.h>
++#include <drm/drm_fb_dma_helper.h>
++#include <drm/drm_framebuffer.h>
++#include <drm/drm_gem_dma_helper.h>
++#include <drm/drm_plane.h>
++#include <uapi/drm/drm_fourcc.h>
++
++#include "sun50i_afbc.h"
++#include "sun8i_mixer.h"
++
++static u32 sun50i_afbc_get_base(struct sun8i_mixer *mixer, unsigned int channel)
++{
++	u32 base = sun8i_channel_base(mixer, channel);
++
++	if (mixer->cfg->de_type == sun8i_mixer_de3)
++		return base + SUN50I_AFBC_CH_OFFSET;
++
++	return base + 0x4000;
++}
++
++bool sun50i_afbc_format_mod_supported(struct sun8i_mixer *mixer,
++				      u32 format, u64 modifier)
++{
++	u64 mode;
++
++	if (modifier == DRM_FORMAT_MOD_INVALID)
++		return false;
++
++	if (modifier == DRM_FORMAT_MOD_LINEAR) {
++		if (format == DRM_FORMAT_YUV420_8BIT ||
++		    format == DRM_FORMAT_YUV420_10BIT ||
++		    format == DRM_FORMAT_Y210)
++			return false;
++		return true;
++	}
++
++	if (mixer->cfg->de_type == sun8i_mixer_de2)
++		return false;
++
++	mode = AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
++	       AFBC_FORMAT_MOD_SPARSE |
++	       AFBC_FORMAT_MOD_SPLIT;
++
++	switch (format) {
++	case DRM_FORMAT_RGBA8888:
++	case DRM_FORMAT_RGB888:
++	case DRM_FORMAT_RGB565:
++	case DRM_FORMAT_RGBA4444:
++	case DRM_FORMAT_RGBA5551:
++	case DRM_FORMAT_RGBA1010102:
++		mode |= AFBC_FORMAT_MOD_YTR;
++		break;
++	case DRM_FORMAT_YUYV:
++	case DRM_FORMAT_Y210:
++	case DRM_FORMAT_YUV420_8BIT:
++	case DRM_FORMAT_YUV420_10BIT:
++		break;
++	default:
++		return false;
++	}
++
++	return modifier == DRM_FORMAT_MOD_ARM_AFBC(mode);
++}
++
++void sun50i_afbc_atomic_update(struct sun8i_mixer *mixer, unsigned int channel,
++			       struct drm_plane *plane)
++{
++	struct drm_plane_state *state = plane->state;
++	struct drm_framebuffer *fb = state->fb;
++	const struct drm_format_info *format = fb->format;
++	struct drm_gem_dma_object *gem;
++	u32 base, val, src_w, src_h;
++	u32 def_color0, def_color1;
++	struct regmap *regs;
++	dma_addr_t dma_addr;
++
++	base = sun50i_afbc_get_base(mixer, channel);
++	regs = mixer->engine.regs;
++
++	src_w = drm_rect_width(&state->src) >> 16;
++	src_h = drm_rect_height(&state->src) >> 16;
++
++	val = SUN50I_FBD_SIZE_HEIGHT(src_h);
++	val |= SUN50I_FBD_SIZE_WIDTH(src_w);
++	regmap_write(regs, SUN50I_FBD_SIZE(base), val);
++
++	val = SUN50I_FBD_BLK_SIZE_HEIGHT(DIV_ROUND_UP(src_h, 16));
++	val = SUN50I_FBD_BLK_SIZE_WIDTH(DIV_ROUND_UP(src_w, 16));
++	regmap_write(regs, SUN50I_FBD_BLK_SIZE(base), val);
++
++	val = SUN50I_FBD_SRC_CROP_TOP(0);
++	val |= SUN50I_FBD_SRC_CROP_LEFT(0);
++	regmap_write(regs, SUN50I_FBD_SRC_CROP(base), val);
++
++	val = SUN50I_FBD_LAY_CROP_TOP(state->src.y1 >> 16);
++	val |= SUN50I_FBD_LAY_CROP_LEFT(state->src.x1 >> 16);
++	regmap_write(regs, SUN50I_FBD_LAY_CROP(base), val);
++
++	/*
++	 * Default color is always set to white, in colorspace and bitness
++	 * that coresponds to used format. If it is actually used or not
++	 * depends on AFBC buffer. At least in Cedrus it can be turned on
++	 * or off.
++	 * NOTE: G and B channels are off by 1 (up). It's unclear if this
++	 * is because HW need such value or it is due to good enough code
++	 * in vendor driver and HW clips the value anyway.
++	 */
++	def_color0 = 0;
++	def_color1 = 0;
++
++	val = 0;
++	switch (format->format) {
++	case DRM_FORMAT_YUYV:
++	case DRM_FORMAT_YUV420_10BIT:
++		val |= SUN50I_FBD_FMT_SBS1(2);
++		val |= SUN50I_FBD_FMT_SBS0(1);
++		break;
++	case DRM_FORMAT_Y210:
++		val |= SUN50I_FBD_FMT_SBS1(3);
++		val |= SUN50I_FBD_FMT_SBS0(2);
++		break;
++	default:
++		val |= SUN50I_FBD_FMT_SBS1(1);
++		val |= SUN50I_FBD_FMT_SBS0(1);
++		break;
++	}
++	switch (format->format) {
++	case DRM_FORMAT_RGBA8888:
++		val |= SUN50I_FBD_FMT_YUV_TRAN;
++		val |= SUN50I_FBD_FMT_IN_FMT(SUN50I_AFBC_RGBA_8888);
++		def_color0 = SUN50I_FBD_DEFAULT_COLOR0_ALPHA(255) |
++			     SUN50I_FBD_DEFAULT_COLOR0_YR(255);
++		def_color1 = SUN50I_FBD_DEFAULT_COLOR1_UG(256) |
++			     SUN50I_FBD_DEFAULT_COLOR1_VB(256);
++		break;
++	case DRM_FORMAT_RGB888:
++		val |= SUN50I_FBD_FMT_YUV_TRAN;
++		val |= SUN50I_FBD_FMT_IN_FMT(SUN50I_AFBC_RGB_888);
++		def_color0 = SUN50I_FBD_DEFAULT_COLOR0_ALPHA(0) |
++			     SUN50I_FBD_DEFAULT_COLOR0_YR(255);
++		def_color1 = SUN50I_FBD_DEFAULT_COLOR1_UG(256) |
++			     SUN50I_FBD_DEFAULT_COLOR1_VB(256);
++		break;
++	case DRM_FORMAT_RGB565:
++		val |= SUN50I_FBD_FMT_YUV_TRAN;
++		val |= SUN50I_FBD_FMT_IN_FMT(SUN50I_AFBC_RGB_565);
++		def_color0 = SUN50I_FBD_DEFAULT_COLOR0_ALPHA(0) |
++			     SUN50I_FBD_DEFAULT_COLOR0_YR(31);
++		def_color1 = SUN50I_FBD_DEFAULT_COLOR1_UG(64) |
++			     SUN50I_FBD_DEFAULT_COLOR1_VB(32);
++		break;
++	case DRM_FORMAT_RGBA4444:
++		val |= SUN50I_FBD_FMT_YUV_TRAN;
++		val |= SUN50I_FBD_FMT_IN_FMT(SUN50I_AFBC_RGBA_4444);
++		def_color0 = SUN50I_FBD_DEFAULT_COLOR0_ALPHA(15) |
++			     SUN50I_FBD_DEFAULT_COLOR0_YR(15);
++		def_color1 = SUN50I_FBD_DEFAULT_COLOR1_UG(16) |
++			     SUN50I_FBD_DEFAULT_COLOR1_VB(16);
++		break;
++	case DRM_FORMAT_RGBA5551:
++		val |= SUN50I_FBD_FMT_YUV_TRAN;
++		val |= SUN50I_FBD_FMT_IN_FMT(SUN50I_AFBC_RGBA_5551);
++		def_color0 = SUN50I_FBD_DEFAULT_COLOR0_ALPHA(1) |
++			     SUN50I_FBD_DEFAULT_COLOR0_YR(31);
++		def_color1 = SUN50I_FBD_DEFAULT_COLOR1_UG(32) |
++			     SUN50I_FBD_DEFAULT_COLOR1_VB(32);
++		break;
++	case DRM_FORMAT_RGBA1010102:
++		val |= SUN50I_FBD_FMT_YUV_TRAN;
++		val |= SUN50I_FBD_FMT_IN_FMT(SUN50I_AFBC_RGBA1010102);
++		def_color0 = SUN50I_FBD_DEFAULT_COLOR0_ALPHA(3) |
++			     SUN50I_FBD_DEFAULT_COLOR0_YR(1023);
++		def_color1 = SUN50I_FBD_DEFAULT_COLOR1_UG(1024) |
++			     SUN50I_FBD_DEFAULT_COLOR1_VB(1024);
++		break;
++	case DRM_FORMAT_YUV420_8BIT:
++		val |= SUN50I_FBD_FMT_IN_FMT(SUN50I_AFBC_YUV420);
++		def_color0 = SUN50I_FBD_DEFAULT_COLOR0_ALPHA(0) |
++			     SUN50I_FBD_DEFAULT_COLOR0_YR(255);
++		def_color1 = SUN50I_FBD_DEFAULT_COLOR1_UG(128) |
++			     SUN50I_FBD_DEFAULT_COLOR1_VB(128);
++		break;
++	case DRM_FORMAT_YUYV:
++		val |= SUN50I_FBD_FMT_IN_FMT(SUN50I_AFBC_YUV422);
++		def_color0 = SUN50I_FBD_DEFAULT_COLOR0_ALPHA(0) |
++			     SUN50I_FBD_DEFAULT_COLOR0_YR(255);
++		def_color1 = SUN50I_FBD_DEFAULT_COLOR1_UG(128) |
++			     SUN50I_FBD_DEFAULT_COLOR1_VB(128);
++		break;
++	case DRM_FORMAT_YUV420_10BIT:
++		val |= SUN50I_FBD_FMT_IN_FMT(SUN50I_AFBC_P010);
++		def_color0 = SUN50I_FBD_DEFAULT_COLOR0_ALPHA(0) |
++			     SUN50I_FBD_DEFAULT_COLOR0_YR(1023);
++		def_color1 = SUN50I_FBD_DEFAULT_COLOR1_UG(512) |
++			     SUN50I_FBD_DEFAULT_COLOR1_VB(512);
++		break;
++	case DRM_FORMAT_Y210:
++		val |= SUN50I_FBD_FMT_IN_FMT(SUN50I_AFBC_P210);
++		def_color0 = SUN50I_FBD_DEFAULT_COLOR0_ALPHA(0) |
++			     SUN50I_FBD_DEFAULT_COLOR0_YR(1023);
++		def_color1 = SUN50I_FBD_DEFAULT_COLOR1_UG(512) |
++			     SUN50I_FBD_DEFAULT_COLOR1_VB(512);
++		break;
++	}
++	regmap_write(regs, SUN50I_FBD_FMT(base), val);
++
++	/* Get the physical address of the buffer in memory */
++	gem = drm_fb_dma_get_gem_obj(fb, 0);
++
++	DRM_DEBUG_DRIVER("Using GEM @ %pad\n", &gem->dma_addr);
++
++	/* Compute the start of the displayed memory */
++	dma_addr = gem->dma_addr + fb->offsets[0];
++
++	regmap_write(regs, SUN50I_FBD_LADDR(base), lower_32_bits(dma_addr));
++	regmap_write(regs, SUN50I_FBD_HADDR(base), upper_32_bits(dma_addr));
++
++	val = SUN50I_FBD_OVL_SIZE_HEIGHT(src_h);
++	val |= SUN50I_FBD_OVL_SIZE_WIDTH(src_w);
++	regmap_write(regs, SUN50I_FBD_OVL_SIZE(base), val);
++
++	val = SUN50I_FBD_OVL_COOR_Y(0);
++	val |= SUN50I_FBD_OVL_COOR_X(0);
++	regmap_write(regs, SUN50I_FBD_OVL_COOR(base), val);
++
++	regmap_write(regs, SUN50I_FBD_OVL_BG_COLOR(base),
++		     SUN8I_MIXER_BLEND_COLOR_BLACK);
++	regmap_write(regs, SUN50I_FBD_DEFAULT_COLOR0(base), def_color0);
++	regmap_write(regs, SUN50I_FBD_DEFAULT_COLOR1(base), def_color1);
++
++	val = SUN50I_FBD_CTL_GLB_ALPHA(state->alpha >> 16);
++	val |= SUN50I_FBD_CTL_CLK_GATE;
++	val |= (state->alpha == DRM_BLEND_ALPHA_OPAQUE) ?
++		SUN50I_FBD_CTL_ALPHA_MODE_PIXEL :
++		SUN50I_FBD_CTL_ALPHA_MODE_COMBINED;
++	val |= SUN50I_FBD_CTL_FBD_EN;
++	regmap_write(regs, SUN50I_FBD_CTL(base), val);
++}
++
++void sun50i_afbc_disable(struct sun8i_mixer *mixer, unsigned int channel)
++{
++	u32 base = sun50i_afbc_get_base(mixer, channel);
++
++	regmap_write(mixer->engine.regs, SUN50I_FBD_CTL(base), 0);
++}
+diff --git a/drivers/gpu/drm/sun4i/sun50i_afbc.h b/drivers/gpu/drm/sun4i/sun50i_afbc.h
+new file mode 100644
+index 000000000000..cea685c86855
+--- /dev/null
++++ b/drivers/gpu/drm/sun4i/sun50i_afbc.h
+@@ -0,0 +1,87 @@
++/* SPDX-License-Identifier: GPL-2.0-or-later */
++/*
++ * Copyright (C) Jernej Skrabec <jernej.skrabec@gmail.com>
++ */
++
++#ifndef _SUN50I_AFBC_H_
++#define _SUN50I_AFBC_H_
++
++#include <linux/types.h>
++
++#define SUN50I_AFBC_CH_OFFSET 0x300
++
++#define SUN50I_AFBC_RGBA_8888	0x02
++#define SUN50I_AFBC_RGB_888	0x08
++#define SUN50I_AFBC_RGB_565	0x0a
++#define SUN50I_AFBC_RGBA_4444	0x0e
++#define SUN50I_AFBC_RGBA_5551	0x12
++#define SUN50I_AFBC_RGBA1010102	0x16
++#define SUN50I_AFBC_YUV422	0x26
++#define SUN50I_AFBC_YUV420	0x2a
++#define SUN50I_AFBC_P010	0x30
++#define SUN50I_AFBC_P210	0x32
++
++#define SUN50I_FBD_CTL(base)			((base) + 0x00)
++#define SUN50I_FBD_CTL_GLB_ALPHA(v)		((v) << 24)
++#define SUN50I_FBD_CTL_CLK_GATE			BIT(4)
++#define SUN50I_FBD_CTL_ALPHA_MODE_PIXEL		((0) << 2)
++#define SUN50I_FBD_CTL_ALPHA_MODE_LAYER		((1) << 2)
++#define SUN50I_FBD_CTL_ALPHA_MODE_COMBINED	((2) << 2)
++#define SUN50I_FBD_CTL_FBD_FCEN			BIT(1)
++#define SUN50I_FBD_CTL_FBD_EN			BIT(0)
++
++#define SUN50I_FBD_SIZE(base)			((base) + 0x08)
++#define SUN50I_FBD_SIZE_HEIGHT(v)		(((v) - 1) << 16)
++#define SUN50I_FBD_SIZE_WIDTH(v)		(((v) - 1) << 0)
++
++#define SUN50I_FBD_BLK_SIZE(base)		((base) + 0x0c)
++#define SUN50I_FBD_BLK_SIZE_HEIGHT(v)		((v) << 16)
++#define SUN50I_FBD_BLK_SIZE_WIDTH(v)		((v) << 0)
++
++#define SUN50I_FBD_SRC_CROP(base)		((base) + 0x10)
++#define SUN50I_FBD_SRC_CROP_TOP(v)		((v) << 16)
++#define SUN50I_FBD_SRC_CROP_LEFT(v)		((v) << 0)
++
++#define SUN50I_FBD_LAY_CROP(base)		((base) + 0x14)
++#define SUN50I_FBD_LAY_CROP_TOP(v)		((v) << 16)
++#define SUN50I_FBD_LAY_CROP_LEFT(v)		((v) << 0)
++
++#define SUN50I_FBD_FMT(base)			((base) + 0x18)
++#define SUN50I_FBD_FMT_SBS1(v)			((v) << 18)
++#define SUN50I_FBD_FMT_SBS0(v)			((v) << 16)
++#define SUN50I_FBD_FMT_YUV_TRAN			BIT(7)
++#define SUN50I_FBD_FMT_IN_FMT(v)		((v) << 0)
++
++#define SUN50I_FBD_LADDR(base)			((base) + 0x20)
++#define SUN50I_FBD_HADDR(base)			((base) + 0x24)
++
++#define SUN50I_FBD_OVL_SIZE(base)		((base) + 0x30)
++#define SUN50I_FBD_OVL_SIZE_HEIGHT(v)		(((v) - 1) << 16)
++#define SUN50I_FBD_OVL_SIZE_WIDTH(v)		(((v) - 1) << 0)
++
++#define SUN50I_FBD_OVL_COOR(base)		((base) + 0x34)
++#define SUN50I_FBD_OVL_COOR_Y(v)		((v) << 16)
++#define SUN50I_FBD_OVL_COOR_X(v)		((v) << 0)
++
++#define SUN50I_FBD_OVL_BG_COLOR(base)		((base) + 0x38)
++#define SUN50I_FBD_OVL_FILL_COLOR(base)		((base) + 0x3c)
++
++#define SUN50I_FBD_DEFAULT_COLOR0(base)		((base) + 0x50)
++#define SUN50I_FBD_DEFAULT_COLOR0_ALPHA(v)	((v) << 16)
++#define SUN50I_FBD_DEFAULT_COLOR0_YR(v)		((v) << 0)
++
++#define SUN50I_FBD_DEFAULT_COLOR1(base)		((base) + 0x54)
++#define SUN50I_FBD_DEFAULT_COLOR1_VB(v)		((v) << 16)
++#define SUN50I_FBD_DEFAULT_COLOR1_UG(v)		((v) << 0)
++
++struct sun8i_mixer;
++struct drm_plane;
++
++bool sun50i_afbc_format_mod_supported(struct sun8i_mixer *mixer,
++				      u32 format, u64 modifier);
++
++void sun50i_afbc_atomic_update(struct sun8i_mixer *mixer, unsigned int channel,
++			       struct drm_plane *plane);
++void sun50i_afbc_disable(struct sun8i_mixer *mixer, unsigned int channel);
++
++#endif
+diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
+index d19349eecc9d..84f8917e2dd8 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
++++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
+@@ -11,8 +11,10 @@
+ #include <drm/drm_framebuffer.h>
+ #include <drm/drm_gem_atomic_helper.h>
+ #include <drm/drm_gem_dma_helper.h>
++#include <drm/drm_gem_framebuffer_helper.h>
+ #include <drm/drm_probe_helper.h>
+ 
++#include "sun50i_afbc.h"
+ #include "sun8i_csc.h"
+ #include "sun8i_mixer.h"
+ #include "sun8i_vi_layer.h"
+@@ -50,7 +52,7 @@ static void sun8i_vi_layer_update_alpha(struct sun8i_mixer *mixer, int channel,
+ 
+ static int sun8i_vi_layer_update_coord(struct sun8i_mixer *mixer, int channel,
+ 				       int overlay, struct drm_plane *plane,
+-				       unsigned int zpos)
++				       unsigned int zpos, bool afbc)
+ {
+ 	struct drm_plane_state *state = plane->state;
+ 	const struct drm_format_info *format = state->fb->format;
+@@ -135,7 +137,7 @@ static int sun8i_vi_layer_update_coord(struct sun8i_mixer *mixer, int channel,
+ 
+ 		required = src_h * 100 / dst_h;
+ 
+-		if (ability < required) {
++		if (!afbc && ability < required) {
+ 			DRM_DEBUG_DRIVER("Using vertical coarse scaling\n");
+ 			vm = src_h;
+ 			vn = (u32)ability * dst_h / 100;
+@@ -145,7 +147,7 @@ static int sun8i_vi_layer_update_coord(struct sun8i_mixer *mixer, int channel,
+ 		/* it seems that every RGB scaler has buffer for 2048 pixels */
+ 		scanline = subsampled ? mixer->cfg->scanline_yuv : 2048;
+ 
+-		if (src_w > scanline) {
++		if (!afbc && src_w > scanline) {
+ 			DRM_DEBUG_DRIVER("Using horizontal coarse scaling\n");
+ 			hm = src_w;
+ 			hn = scanline;
+@@ -308,6 +310,15 @@ static int sun8i_vi_layer_update_buffer(struct sun8i_mixer *mixer, int channel,
+ 	return 0;
+ }
+ 
++static void sun8i_vi_layer_prepare_non_linear(struct sun8i_mixer *mixer,
++					      int channel, int overlay)
++{
++	u32 base = sun8i_channel_base(mixer, channel);
++
++	regmap_write(mixer->engine.regs,
++		     SUN8I_MIXER_CHAN_VI_LAYER_ATTR(base, overlay), 0);
++}
++
+ static int sun8i_vi_layer_atomic_check(struct drm_plane *plane,
+ 				       struct drm_atomic_state *state)
+ {
+@@ -348,18 +359,45 @@ static void sun8i_vi_layer_atomic_update(struct drm_plane *plane,
+ 	struct sun8i_layer *layer = plane_to_sun8i_layer(plane);
+ 	unsigned int zpos = new_state->normalized_zpos;
+ 	struct sun8i_mixer *mixer = layer->mixer;
++	struct drm_framebuffer *fb = plane->state->fb;
++	bool afbc = drm_is_afbc(fb->modifier);
+ 
+-	if (!new_state->crtc || !new_state->visible)
++	if (!new_state->crtc || !new_state->visible) {
++		if (mixer->cfg->de_type >= sun8i_mixer_de3)
++			sun50i_afbc_disable(mixer, layer->channel);
+ 		return;
++	}
+ 
+ 	sun8i_vi_layer_update_coord(mixer, layer->channel,
+-				    layer->overlay, plane, zpos);
+-	sun8i_vi_layer_update_alpha(mixer, layer->channel,
+-				    layer->overlay, plane);
+-	sun8i_vi_layer_update_formats(mixer, layer->channel,
+-				      layer->overlay, plane);
+-	sun8i_vi_layer_update_buffer(mixer, layer->channel,
+-				     layer->overlay, plane);
++				    layer->overlay, plane, zpos, afbc);
++
++	if (afbc) {
++		u32 fmt_type;
++
++		sun8i_vi_layer_prepare_non_linear(mixer, layer->channel,
++						  layer->overlay);
++		sun50i_afbc_atomic_update(mixer, layer->channel, plane);
++
++		fmt_type = sun8i_vi_layer_get_format_type(fb->format);
++		sun8i_csc_set_ccsc(mixer, layer->channel, fmt_type,
++				   plane->state->color_encoding,
++				   plane->state->color_range);
++	} else {
++		sun8i_vi_layer_update_alpha(mixer, layer->channel,
++					    layer->overlay, plane);
++		sun8i_vi_layer_update_formats(mixer, layer->channel,
++					      layer->overlay, plane);
++		sun8i_vi_layer_update_buffer(mixer, layer->channel,
++					     layer->overlay, plane);
++	}
++}
++
++static bool sun8i_vi_layer_format_mod_supported(struct drm_plane *plane,
++						u32 format, u64 modifier)
++{
++	struct sun8i_layer *layer = plane_to_sun8i_layer(plane);
++
++	return sun50i_afbc_format_mod_supported(layer->mixer, format, modifier);
+ }
+ 
+ static const struct drm_plane_helper_funcs sun8i_vi_layer_helper_funcs = {
+@@ -374,6 +412,7 @@ static const struct drm_plane_funcs sun8i_vi_layer_funcs = {
+ 	.disable_plane		= drm_atomic_helper_disable_plane,
+ 	.reset			= drm_atomic_helper_plane_reset,
+ 	.update_plane		= drm_atomic_helper_update_plane,
++	.format_mod_supported   = sun8i_vi_layer_format_mod_supported,
+ };
+ 
+ /*
+@@ -457,6 +496,11 @@ static const u32 sun8i_vi_layer_de3_formats[] = {
+ 	DRM_FORMAT_YVU411,
+ 	DRM_FORMAT_YVU420,
+ 	DRM_FORMAT_YVU422,
++
++	/* AFBC only formats */
++	DRM_FORMAT_YUV420_8BIT,
++	DRM_FORMAT_YUV420_10BIT,
++	DRM_FORMAT_Y210,
+ };
+ 
+ static const uint64_t sun8i_layer_modifiers[] = {
+@@ -464,6 +508,18 @@ static const uint64_t sun8i_layer_modifiers[] = {
+ 	DRM_FORMAT_MOD_INVALID
+ };
+ 
++static const uint64_t sun50i_layer_de3_modifiers[] = {
++	DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
++				AFBC_FORMAT_MOD_SPARSE |
++				AFBC_FORMAT_MOD_SPLIT),
++	DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
++				AFBC_FORMAT_MOD_YTR |
++				AFBC_FORMAT_MOD_SPARSE |
++				AFBC_FORMAT_MOD_SPLIT),
++	DRM_FORMAT_MOD_LINEAR,
++	DRM_FORMAT_MOD_INVALID
++};
++
+ struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_device *drm,
+ 					    struct sun8i_mixer *mixer,
+ 					    int index)
+@@ -472,6 +528,7 @@ struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_device *drm,
+ 	u32 supported_encodings, supported_ranges;
+ 	unsigned int plane_cnt, format_count;
+ 	struct sun8i_layer *layer;
++	const uint64_t *modifiers;
+ 	const u32 *formats;
+ 	int ret;
+ 
+@@ -487,9 +544,11 @@ struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_device *drm,
+ 	if (mixer->cfg->de_type >= sun8i_mixer_de3) {
+ 		formats = sun8i_vi_layer_de3_formats;
+ 		format_count = ARRAY_SIZE(sun8i_vi_layer_de3_formats);
++		modifiers = sun50i_layer_de3_modifiers;
+ 	} else {
+ 		formats = sun8i_vi_layer_formats;
+ 		format_count = ARRAY_SIZE(sun8i_vi_layer_formats);
++		modifiers = sun8i_layer_modifiers;
+ 	}
+ 
+ 	if (!mixer->cfg->ui_num && index == 0)
+@@ -499,8 +558,7 @@ struct sun8i_layer *sun8i_vi_layer_init_one(struct drm_device *drm,
+ 	ret = drm_universal_plane_init(drm, &layer->plane, 0,
+ 				       &sun8i_vi_layer_funcs,
+ 				       formats, format_count,
+-				       sun8i_layer_modifiers,
+-				       type, NULL);
++				       modifiers, type, NULL);
+ 	if (ret) {
+ 		dev_err(drm->dev, "Couldn't initialize layer\n");
+ 		return ERR_PTR(ret);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de3-add-YUV-support-to-the-DE3-mixer.patch b/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de3-add-YUV-support-to-the-DE3-mixer.patch
new file mode 100644
index 000000000000..8a814bcaf3db
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de3-add-YUV-support-to-the-DE3-mixer.patch
@@ -0,0 +1,126 @@
+From 3b6462ebad249f4762acfd8e262442bb0cda95b4 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sun, 29 Sep 2024 22:04:40 +1300
+Subject: drm: sun4i: de3: add YUV support to the DE3 mixer
+
+The mixer in the DE3 display engine supports YUV 8 and 10 bit
+formats in addition to 8-bit RGB. Add the required register
+configuration and format enumeration callback functions to the mixer,
+and store the in-use output format (defaulting to RGB) and color
+encoding in engine variables.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+Signed-off-by: Ryan Walklin <ryan@testtoast.com>
+---
+ drivers/gpu/drm/sun4i/sun8i_mixer.c  | 53 ++++++++++++++++++++++++++--
+ drivers/gpu/drm/sun4i/sunxi_engine.h |  5 +++
+ 2 files changed, 55 insertions(+), 3 deletions(-)
+
+diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
+index 252827715de1..a50c583852ed 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
++++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
+@@ -23,7 +23,10 @@
+ #include <drm/drm_gem_dma_helper.h>
+ #include <drm/drm_probe_helper.h>
+ 
++#include <uapi/linux/media-bus-format.h>
++
+ #include "sun4i_drv.h"
++#include "sun50i_fmt.h"
+ #include "sun8i_mixer.h"
+ #include "sun8i_ui_layer.h"
+ #include "sun8i_vi_layer.h"
+@@ -390,12 +393,52 @@ static void sun8i_mixer_mode_set(struct sunxi_engine *engine,
+ 
+ 	DRM_DEBUG_DRIVER("Switching display mixer interlaced mode %s\n",
+ 			 interlaced ? "on" : "off");
++
++	if (engine->format == MEDIA_BUS_FMT_RGB888_1X24)
++		val = SUN8I_MIXER_BLEND_COLOR_BLACK;
++	else
++		val = 0xff108080;
++
++	regmap_write(mixer->engine.regs,
++		     SUN8I_MIXER_BLEND_BKCOLOR(bld_base), val);
++	regmap_write(mixer->engine.regs,
++		     SUN8I_MIXER_BLEND_ATTR_FCOLOR(bld_base, 0), val);
++
++	if (mixer->cfg->has_formatter)
++		sun50i_fmt_setup(mixer, mode->hdisplay,
++				 mode->vdisplay, mixer->engine.format);
++}
++
++static u32 *sun8i_mixer_get_supported_fmts(struct sunxi_engine *engine, u32 *num)
++{
++	struct sun8i_mixer *mixer = engine_to_sun8i_mixer(engine);
++	u32 *formats, count;
++
++	count = 0;
++
++	formats = kcalloc(5, sizeof(*formats), GFP_KERNEL);
++	if (!formats)
++		return NULL;
++
++	if (mixer->cfg->has_formatter) {
++		formats[count++] = MEDIA_BUS_FMT_UYYVYY10_0_5X30;
++		formats[count++] = MEDIA_BUS_FMT_YUV8_1X24;
++		formats[count++] = MEDIA_BUS_FMT_UYVY8_1X16;
++		formats[count++] = MEDIA_BUS_FMT_UYYVYY8_0_5X24;
++	}
++
++	formats[count++] = MEDIA_BUS_FMT_RGB888_1X24;
++
++	*num = count;
++
++	return formats;
+ }
+ 
+ static const struct sunxi_engine_ops sun8i_engine_ops = {
+-	.commit		= sun8i_mixer_commit,
+-	.layers_init	= sun8i_layers_init,
+-	.mode_set	= sun8i_mixer_mode_set,
++	.commit			= sun8i_mixer_commit,
++	.layers_init		= sun8i_layers_init,
++	.mode_set		= sun8i_mixer_mode_set,
++	.get_supported_fmts	= sun8i_mixer_get_supported_fmts,
+ };
+ 
+ static const struct regmap_config sun8i_mixer_regmap_config = {
+@@ -456,6 +499,10 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,
+ 	dev_set_drvdata(dev, mixer);
+ 	mixer->engine.ops = &sun8i_engine_ops;
+ 	mixer->engine.node = dev->of_node;
++	/* default output format, supported by all mixers */
++	mixer->engine.format = MEDIA_BUS_FMT_RGB888_1X24;
++	/* default color encoding, ignored with RGB I/O */
++	mixer->engine.encoding = DRM_COLOR_YCBCR_BT601;
+ 
+ 	if (of_property_present(dev->of_node, "iommus")) {
+ 		/*
+diff --git a/drivers/gpu/drm/sun4i/sunxi_engine.h b/drivers/gpu/drm/sun4i/sunxi_engine.h
+index c48cbc1aceb8..ffafc29b3a0c 100644
+--- a/drivers/gpu/drm/sun4i/sunxi_engine.h
++++ b/drivers/gpu/drm/sun4i/sunxi_engine.h
+@@ -6,6 +6,8 @@
+ #ifndef _SUNXI_ENGINE_H_
+ #define _SUNXI_ENGINE_H_
+ 
++#include <drm/drm_color_mgmt.h>
++
+ struct drm_plane;
+ struct drm_crtc;
+ struct drm_device;
+@@ -151,6 +153,9 @@ struct sunxi_engine {
+ 
+ 	int id;
+ 
++	u32				format;
++	enum drm_color_encoding		encoding;
++
+ 	/* Engine list management */
+ 	struct list_head		list;
+ };
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de3-add-YUV-support-to-the-TCON.patch b/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de3-add-YUV-support-to-the-TCON.patch
new file mode 100644
index 000000000000..5fb39d4f07d6
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de3-add-YUV-support-to-the-TCON.patch
@@ -0,0 +1,83 @@
+From ff794822d56721795fec59dea66164cc19ba792c Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sun, 29 Sep 2024 22:04:43 +1300
+Subject: drm: sun4i: de3: add YUV support to the TCON
+
+Account for U/V channel subsampling by reducing the dot clock and
+resolution with a divider in the DE3 timing controller if a YUV format
+is selected.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+Signed-off-by: Ryan Walklin <ryan@testtoast.com>
+---
+ drivers/gpu/drm/sun4i/sun4i_tcon.c | 26 +++++++++++++++++++-------
+ 1 file changed, 19 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
+index 3675c87461e9..af67bf2e6e09 100644
+--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
++++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
+@@ -649,14 +649,26 @@ static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon,
+ static void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon,
+ 				 const struct drm_display_mode *mode)
+ {
+-	unsigned int bp, hsync, vsync, vtotal;
++	unsigned int bp, hsync, vsync, vtotal, div;
++	struct sun4i_crtc *scrtc = tcon->crtc;
++	struct sunxi_engine *engine = scrtc->engine;
+ 	u8 clk_delay;
+ 	u32 val;
+ 
+ 	WARN_ON(!tcon->quirks->has_channel_1);
+ 
++	switch (engine->format) {
++	case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
++	case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
++		div = 2;
++		break;
++	default:
++		div = 1;
++		break;
++	}
++
+ 	/* Configure the dot clock */
+-	clk_set_rate(tcon->sclk1, mode->crtc_clock * 1000);
++	clk_set_rate(tcon->sclk1, mode->crtc_clock * 1000 / div);
+ 
+ 	/* Adjust clock delay */
+ 	clk_delay = sun4i_tcon_get_clk_delay(mode, 1);
+@@ -675,17 +687,17 @@ static void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon,
+ 
+ 	/* Set the input resolution */
+ 	regmap_write(tcon->regs, SUN4I_TCON1_BASIC0_REG,
+-		     SUN4I_TCON1_BASIC0_X(mode->crtc_hdisplay) |
++		     SUN4I_TCON1_BASIC0_X(mode->crtc_hdisplay / div) |
+ 		     SUN4I_TCON1_BASIC0_Y(mode->crtc_vdisplay));
+ 
+ 	/* Set the upscaling resolution */
+ 	regmap_write(tcon->regs, SUN4I_TCON1_BASIC1_REG,
+-		     SUN4I_TCON1_BASIC1_X(mode->crtc_hdisplay) |
++		     SUN4I_TCON1_BASIC1_X(mode->crtc_hdisplay / div) |
+ 		     SUN4I_TCON1_BASIC1_Y(mode->crtc_vdisplay));
+ 
+ 	/* Set the output resolution */
+ 	regmap_write(tcon->regs, SUN4I_TCON1_BASIC2_REG,
+-		     SUN4I_TCON1_BASIC2_X(mode->crtc_hdisplay) |
++		     SUN4I_TCON1_BASIC2_X(mode->crtc_hdisplay / div) |
+ 		     SUN4I_TCON1_BASIC2_Y(mode->crtc_vdisplay));
+ 
+ 	/* Set horizontal display timings */
+@@ -693,8 +705,8 @@ static void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon,
+ 	DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n",
+ 			 mode->htotal, bp);
+ 	regmap_write(tcon->regs, SUN4I_TCON1_BASIC3_REG,
+-		     SUN4I_TCON1_BASIC3_H_TOTAL(mode->crtc_htotal) |
+-		     SUN4I_TCON1_BASIC3_H_BACKPORCH(bp));
++		     SUN4I_TCON1_BASIC3_H_TOTAL(mode->crtc_htotal / div) |
++		     SUN4I_TCON1_BASIC3_H_BACKPORCH(bp / div));
+ 
+ 	bp = mode->crtc_vtotal - mode->crtc_vsync_start;
+ 	DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n",
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de3-add-YUV-support-to-the-color-space-correction-mod.patch b/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de3-add-YUV-support-to-the-color-space-correction-mod.patch
new file mode 100644
index 000000000000..68774b67bf48
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de3-add-YUV-support-to-the-color-space-correction-mod.patch
@@ -0,0 +1,225 @@
+From a23ed976ee720c2445791716d975f040ef576c2b Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sun, 29 Sep 2024 22:04:42 +1300
+Subject: drm: sun4i: de3: add YUV support to the color space correction module
+
+Add coefficients and support for YUV formats to the display engine
+colorspace and dynamic range correction submodule.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+Signed-off-by: Ryan Walklin <ryan@testtoast.com>
+---
+ drivers/gpu/drm/sun4i/sun8i_csc.c | 164 +++++++++++++++++++++++++++++-
+ 1 file changed, 162 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/sun4i/sun8i_csc.c b/drivers/gpu/drm/sun4i/sun8i_csc.c
+index 8a336ccb27d3..e12a81fa9108 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_csc.c
++++ b/drivers/gpu/drm/sun4i/sun8i_csc.c
+@@ -5,6 +5,8 @@
+ 
+ #include <drm/drm_print.h>
+ 
++#include <uapi/linux/media-bus-format.h>
++
+ #include "sun8i_csc.h"
+ #include "sun8i_mixer.h"
+ 
+@@ -107,6 +109,135 @@ static const u32 yuv2rgb_de3[2][3][12] = {
+ 	},
+ };
+ 
++/* always convert to limited mode */
++static const u32 rgb2yuv_de3[3][12] = {
++	[DRM_COLOR_YCBCR_BT601] = {
++		0x0000837A, 0x0001021D, 0x00003221, 0x00000040,
++		0xFFFFB41C, 0xFFFF6B03, 0x0000E0E1, 0x00000200,
++		0x0000E0E1, 0xFFFF43B1, 0xFFFFDB6E, 0x00000200,
++	},
++	[DRM_COLOR_YCBCR_BT709] = {
++		0x00005D7C, 0x00013A7C, 0x00001FBF, 0x00000040,
++		0xFFFFCC78, 0xFFFF52A7, 0x0000E0E1, 0x00000200,
++		0x0000E0E1, 0xFFFF33BE, 0xFFFFEB61, 0x00000200,
++	},
++	[DRM_COLOR_YCBCR_BT2020] = {
++		0x00007384, 0x00012A21, 0x00001A13, 0x00000040,
++		0xFFFFC133, 0xFFFF5DEC, 0x0000E0E1, 0x00000200,
++		0x0000E0E1, 0xFFFF3135, 0xFFFFEDEA, 0x00000200,
++	},
++};
++
++/* always convert to limited mode */
++static const u32 yuv2yuv_de3[2][3][3][12] = {
++	[DRM_COLOR_YCBCR_LIMITED_RANGE] = {
++		[DRM_COLOR_YCBCR_BT601] = {
++			[DRM_COLOR_YCBCR_BT601] = {
++				0x00020000, 0x00000000, 0x00000000, 0x00000000,
++				0x00000000, 0x00020000, 0x00000000, 0x00000000,
++				0x00000000, 0x00000000, 0x00020000, 0x00000000,
++			},
++			[DRM_COLOR_YCBCR_BT709] = {
++				0x00020000, 0xFFFFC4D7, 0xFFFF9589, 0xFFC00040,
++				0x00000000, 0x0002098B, 0x00003AAF, 0xFE000200,
++				0x00000000, 0x0000266D, 0x00020CF8, 0xFE000200,
++			},
++			[DRM_COLOR_YCBCR_BT2020] = {
++				0x00020000, 0xFFFFBFCE, 0xFFFFC5FF, 0xFFC00040,
++				0x00000000, 0x00020521, 0x00001F89, 0xFE000200,
++				0x00000000, 0x00002C87, 0x00020F07, 0xFE000200,
++			},
++		},
++		[DRM_COLOR_YCBCR_BT709] = {
++			[DRM_COLOR_YCBCR_BT601] = {
++				0x00020000, 0x000032D9, 0x00006226, 0xFFC00040,
++				0x00000000, 0x0001FACE, 0xFFFFC759, 0xFE000200,
++				0x00000000, 0xFFFFDAE7, 0x0001F780, 0xFE000200,
++			},
++			[DRM_COLOR_YCBCR_BT709] = {
++				0x00020000, 0x00000000, 0x00000000, 0x00000000,
++				0x00000000, 0x00020000, 0x00000000, 0x00000000,
++				0x00000000, 0x00000000, 0x00020000, 0x00000000,
++			},
++			[DRM_COLOR_YCBCR_BT2020] = {
++				0x00020000, 0xFFFFF782, 0x00003036, 0xFFC00040,
++				0x00000000, 0x0001FD99, 0xFFFFE5CA, 0xFE000200,
++				0x00000000, 0x000005E4, 0x0002015A, 0xFE000200,
++			},
++		},
++		[DRM_COLOR_YCBCR_BT2020] = {
++			[DRM_COLOR_YCBCR_BT601] = {
++				0x00020000, 0x00003B03, 0x000034D2, 0xFFC00040,
++				0x00000000, 0x0001FD8C, 0xFFFFE183, 0xFE000200,
++				0x00000000, 0xFFFFD4F3, 0x0001F3FA, 0xFE000200,
++			},
++			[DRM_COLOR_YCBCR_BT709] = {
++				0x00020000, 0x00000916, 0xFFFFD061, 0xFFC00040,
++				0x00000000, 0x0002021C, 0x00001A40, 0xFE000200,
++				0x00000000, 0xFFFFFA19, 0x0001FE5A, 0xFE000200,
++			},
++			[DRM_COLOR_YCBCR_BT2020] = {
++				0x00020000, 0x00000000, 0x00000000, 0x00000000,
++				0x00000000, 0x00020000, 0x00000000, 0x00000000,
++				0x00000000, 0x00000000, 0x00020000, 0x00000000,
++			},
++		},
++	},
++	[DRM_COLOR_YCBCR_FULL_RANGE] = {
++		[DRM_COLOR_YCBCR_BT601] = {
++			[DRM_COLOR_YCBCR_BT601] = {
++				0x0001B7B8, 0x00000000, 0x00000000, 0x00000040,
++				0x00000000, 0x0001C1C2, 0x00000000, 0xFE000200,
++				0x00000000, 0x00000000, 0x0001C1C2, 0xFE000200,
++			},
++			[DRM_COLOR_YCBCR_BT709] = {
++				0x0001B7B8, 0xFFFFCC08, 0xFFFFA27B, 0x00000040,
++				0x00000000, 0x0001CA24, 0x0000338D, 0xFE000200,
++				0x00000000, 0x000021C1, 0x0001CD26, 0xFE000200,
++			},
++			[DRM_COLOR_YCBCR_BT2020] = {
++				0x0001B7B8, 0xFFFFC79C, 0xFFFFCD0C, 0x00000040,
++				0x00000000, 0x0001C643, 0x00001BB4, 0xFE000200,
++				0x00000000, 0x0000271D, 0x0001CEF5, 0xFE000200,
++			},
++		},
++		[DRM_COLOR_YCBCR_BT709] = {
++			[DRM_COLOR_YCBCR_BT601] = {
++				0x0001B7B8, 0x00002CAB, 0x00005638, 0x00000040,
++				0x00000000, 0x0001BD32, 0xFFFFCE3C, 0xFE000200,
++				0x00000000, 0xFFFFDF6A, 0x0001BA4A, 0xFE000200,
++			},
++			[DRM_COLOR_YCBCR_BT709] = {
++				0x0001B7B8, 0x00000000, 0x00000000, 0x00000040,
++				0x00000000, 0x0001C1C2, 0x00000000, 0xFE000200,
++				0x00000000, 0x00000000, 0x0001C1C2, 0xFE000200,
++			},
++			[DRM_COLOR_YCBCR_BT2020] = {
++				0x0001B7B8, 0xFFFFF88A, 0x00002A5A, 0x00000040,
++				0x00000000, 0x0001BFA5, 0xFFFFE8FA, 0xFE000200,
++				0x00000000, 0x0000052D, 0x0001C2F1, 0xFE000200,
++			},
++		},
++		[DRM_COLOR_YCBCR_BT2020] = {
++			[DRM_COLOR_YCBCR_BT601] = {
++				0x0001B7B8, 0x000033D6, 0x00002E66, 0x00000040,
++				0x00000000, 0x0001BF9A, 0xFFFFE538, 0xFE000200,
++				0x00000000, 0xFFFFDA2F, 0x0001B732, 0xFE000200,
++			},
++			[DRM_COLOR_YCBCR_BT709] = {
++				0x0001B7B8, 0x000007FB, 0xFFFFD62B, 0x00000040,
++				0x00000000, 0x0001C39D, 0x0000170F, 0xFE000200,
++				0x00000000, 0xFFFFFAD1, 0x0001C04F, 0xFE000200,
++			},
++			[DRM_COLOR_YCBCR_BT2020] = {
++				0x0001B7B8, 0x00000000, 0x00000000, 0x00000040,
++				0x00000000, 0x0001C1C2, 0x00000000, 0xFE000200,
++				0x00000000, 0x00000000, 0x0001C1C2, 0xFE000200,
++			},
++		},
++	},
++};
++
+ static void sun8i_csc_setup(struct regmap *map, u32 base,
+ 			    enum format_type fmt_type,
+ 			    enum drm_color_encoding encoding,
+@@ -148,12 +279,27 @@ static void sun8i_csc_setup(struct regmap *map, u32 base,
+ 	regmap_write(map, SUN8I_CSC_CTRL(base), val);
+ }
+ 
++static const u32 *sun8i_csc_get_de3_yuv_table(enum drm_color_encoding in_enc,
++					      enum drm_color_range in_range,
++					      u32 out_format,
++					      enum drm_color_encoding out_enc)
++{
++	if (out_format == MEDIA_BUS_FMT_RGB888_1X24)
++		return yuv2rgb_de3[in_range][in_enc];
++
++	/* check for identity transformation */
++	if (in_range == DRM_COLOR_YCBCR_LIMITED_RANGE && out_enc == in_enc)
++		return NULL;
++
++	return yuv2yuv_de3[in_range][in_enc][out_enc];
++}
++
+ static void sun8i_de3_ccsc_setup(struct sunxi_engine *engine, int layer,
+ 				 enum format_type fmt_type,
+ 				 enum drm_color_encoding encoding,
+ 				 enum drm_color_range range)
+ {
+-	u32 addr, val, mask;
++	u32 addr, val = 0, mask;
+ 	struct regmap *map;
+ 	const u32 *table;
+ 	int i;
+@@ -164,14 +310,28 @@ static void sun8i_de3_ccsc_setup(struct sunxi_engine *engine, int layer,
+ 
+ 	switch (fmt_type) {
+ 	case FORMAT_TYPE_RGB:
+-		val = 0;
++		if (engine->format == MEDIA_BUS_FMT_RGB888_1X24)
++			break;
++		val = mask;
++		addr = SUN50I_MIXER_BLEND_CSC_COEFF(DE3_BLD_BASE, layer, 0);
++		regmap_bulk_write(map, addr, rgb2yuv_de3[engine->encoding], 12);
+ 		break;
+ 	case FORMAT_TYPE_YUV:
++		table = sun8i_csc_get_de3_yuv_table(encoding, range,
++						    engine->format,
++						    engine->encoding);
++		if (!table)
++			break;
+ 		val = mask;
+ 		addr = SUN50I_MIXER_BLEND_CSC_COEFF(DE3_BLD_BASE, layer, 0);
+ 		regmap_bulk_write(map, addr, table, 12);
+ 		break;
+ 	case FORMAT_TYPE_YVU:
++		table = sun8i_csc_get_de3_yuv_table(encoding, range,
++						    engine->format,
++						    engine->encoding);
++		if (!table)
++			table = yuv2yuv_de3[range][encoding][encoding];
+ 		val = mask;
+ 		for (i = 0; i < 12; i++) {
+ 			if ((i & 3) == 1)
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de3-add-format-enumeration-function-to-engine.patch b/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de3-add-format-enumeration-function-to-engine.patch
new file mode 100644
index 000000000000..581242c382e9
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de3-add-format-enumeration-function-to-engine.patch
@@ -0,0 +1,63 @@
+From 99d327853acbc5d6c6d4140f004f82fcd5c40ea1 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sun, 29 Sep 2024 22:04:38 +1300
+Subject: drm: sun4i: de3: add format enumeration function to engine
+
+The DE3 display engine supports YUV formats in addition to RGB.
+
+Add an optional format enumeration function to the engine.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+Signed-off-by: Ryan Walklin <ryan@testtoast.com>
+---
+ drivers/gpu/drm/sun4i/sunxi_engine.h | 29 ++++++++++++++++++++++++++++
+ 1 file changed, 29 insertions(+)
+
+diff --git a/drivers/gpu/drm/sun4i/sunxi_engine.h b/drivers/gpu/drm/sun4i/sunxi_engine.h
+index ec0c4932f15c..c48cbc1aceb8 100644
+--- a/drivers/gpu/drm/sun4i/sunxi_engine.h
++++ b/drivers/gpu/drm/sun4i/sunxi_engine.h
+@@ -123,6 +123,17 @@ struct sunxi_engine_ops {
+ 	 */
+ 	void (*mode_set)(struct sunxi_engine *engine,
+ 			 const struct drm_display_mode *mode);
++
++	/**
++	 * @get_supported_fmts
++	 *
++	 * This callback is used to enumerate all supported output
++	 * formats by the engine. They are used for bridge format
++	 * negotiation.
++	 *
++	 * This function is optional.
++	 */
++	u32 *(*get_supported_fmts)(struct sunxi_engine *engine, u32 *num);
+ };
+ 
+ /**
+@@ -215,4 +226,22 @@ sunxi_engine_mode_set(struct sunxi_engine *engine,
+ 	if (engine->ops && engine->ops->mode_set)
+ 		engine->ops->mode_set(engine, mode);
+ }
++
++/**
++ * sunxi_engine_get_supported_formats - Provide array of supported formats
++ * @engine:	pointer to the engine
++ * @num:	pointer to variable, which will hold number of formats
++ *
++ * This list can be used for format negotiation by bridge.
++ */
++static inline u32 *
++sunxi_engine_get_supported_formats(struct sunxi_engine *engine, u32 *num)
++{
++	if (engine->ops && engine->ops->get_supported_fmts)
++		return engine->ops->get_supported_fmts(engine, num);
++
++	*num = 0;
++
++	return NULL;
++}
+ #endif /* _SUNXI_ENGINE_H_ */
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de3-add-formatter-flag-to-mixer-config.patch b/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de3-add-formatter-flag-to-mixer-config.patch
new file mode 100644
index 000000000000..90f86befd415
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de3-add-formatter-flag-to-mixer-config.patch
@@ -0,0 +1,53 @@
+From f9a39553dcf5e87eba968d2aac4f5acf52baa392 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sun, 29 Sep 2024 22:04:39 +1300
+Subject: drm: sun4i: de3: add formatter flag to mixer config
+
+Only the DE3 (and newer) display engines have a formatter module. This
+could be inferred from the is_de3 flag alone, however this will not
+scale with addition of future DE versions in subsequent patches.
+
+Add a separate flag to signal this in the mixer configuration.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+Signed-off-by: Ryan Walklin <ryan@testtoast.com>
+---
+ drivers/gpu/drm/sun4i/sun8i_mixer.c | 1 +
+ drivers/gpu/drm/sun4i/sun8i_mixer.h | 2 ++
+ 2 files changed, 3 insertions(+)
+
+diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
+index bd0fe2c6624e..252827715de1 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
++++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
+@@ -717,6 +717,7 @@ static const struct sun8i_mixer_cfg sun50i_a64_mixer1_cfg = {
+ static const struct sun8i_mixer_cfg sun50i_h6_mixer0_cfg = {
+ 	.ccsc		= CCSC_MIXER0_LAYOUT,
+ 	.is_de3		= true,
++	.has_formatter	= 1,
+ 	.mod_rate	= 600000000,
+ 	.scaler_mask	= 0xf,
+ 	.scanline_yuv	= 4096,
+diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h
+index d7898c9c9cc0..8417b8fef2e1 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_mixer.h
++++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h
+@@ -163,6 +163,7 @@ enum {
+  * @mod_rate: module clock rate that needs to be set in order to have
+  *	a functional block.
+  * @is_de3: true, if this is next gen display engine 3.0, false otherwise.
++ * @has_formatter: true, if mixer has formatter core, for 10-bit and YUV handling
+  * @scaline_yuv: size of a scanline for VI scaler for YUV formats.
+  */
+ struct sun8i_mixer_cfg {
+@@ -172,6 +173,7 @@ struct sun8i_mixer_cfg {
+ 	int		ccsc;
+ 	unsigned long	mod_rate;
+ 	unsigned int	is_de3 : 1;
++	unsigned int    has_formatter : 1;
+ 	unsigned int	scanline_yuv;
+ };
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de3-pass-engine-reference-to-ccsc-setup-function.patch b/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de3-pass-engine-reference-to-ccsc-setup-function.patch
new file mode 100644
index 000000000000..41bd023772e6
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de3-pass-engine-reference-to-ccsc-setup-function.patch
@@ -0,0 +1,54 @@
+From 2d7c88fc2af6d07ccadc99b157753638b4940293 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sun, 29 Sep 2024 22:04:41 +1300
+Subject: drm: sun4i: de3: pass engine reference to ccsc setup function
+
+Configuration of the DE3 colorspace and dynamic range correction module
+requires knowledge of the current video format and encoding.
+
+Pass the display engine by reference to the csc setup function, rather
+than the register map alone, to allow access to this information.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+Signed-off-by: Ryan Walklin <ryan@testtoast.com>
+---
+ drivers/gpu/drm/sun4i/sun8i_csc.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/sun4i/sun8i_csc.c b/drivers/gpu/drm/sun4i/sun8i_csc.c
+index 68d955c63b05..8a336ccb27d3 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_csc.c
++++ b/drivers/gpu/drm/sun4i/sun8i_csc.c
+@@ -148,17 +148,19 @@ static void sun8i_csc_setup(struct regmap *map, u32 base,
+ 	regmap_write(map, SUN8I_CSC_CTRL(base), val);
+ }
+ 
+-static void sun8i_de3_ccsc_setup(struct regmap *map, int layer,
++static void sun8i_de3_ccsc_setup(struct sunxi_engine *engine, int layer,
+ 				 enum format_type fmt_type,
+ 				 enum drm_color_encoding encoding,
+ 				 enum drm_color_range range)
+ {
+ 	u32 addr, val, mask;
++	struct regmap *map;
+ 	const u32 *table;
+ 	int i;
+ 
+ 	mask = SUN50I_MIXER_BLEND_CSC_CTL_EN(layer);
+ 	table = yuv2rgb_de3[range][encoding];
++	map = engine->regs;
+ 
+ 	switch (fmt_type) {
+ 	case FORMAT_TYPE_RGB:
+@@ -204,7 +206,7 @@ void sun8i_csc_set_ccsc(struct sun8i_mixer *mixer, int layer,
+ 	u32 base;
+ 
+ 	if (mixer->cfg->is_de3) {
+-		sun8i_de3_ccsc_setup(mixer->engine.regs, layer,
++		sun8i_de3_ccsc_setup(&mixer->engine, layer,
+ 				     fmt_type, encoding, range);
+ 		return;
+ 	}
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de33-csc-add-Display-Engine-3.3-DE33-support.patch b/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de33-csc-add-Display-Engine-3.3-DE33-support.patch
new file mode 100644
index 000000000000..3479d96ff100
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de33-csc-add-Display-Engine-3.3-DE33-support.patch
@@ -0,0 +1,156 @@
+From 0d003a88bcacf5f405f3922b0c56b7eecdb68386 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sun, 29 Sep 2024 22:04:58 +1300
+Subject: drm: sun4i: de33: csc: add Display Engine 3.3 (DE33) support
+
+Like earlier DE versions, the DE33 has a CSC (Color Space Correction)
+module. which provides color space conversion between BT2020/BT709, and
+dynamic range conversion between SDR/ST2084/HLG.
+
+Add support for the DE33.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+Signed-off-by: Ryan Walklin <ryan@testtoast.com>
+---
+ drivers/gpu/drm/sun4i/sun8i_csc.c | 96 +++++++++++++++++++++++++++++++
+ drivers/gpu/drm/sun4i/sun8i_csc.h |  3 +
+ 2 files changed, 99 insertions(+)
+
+diff --git a/drivers/gpu/drm/sun4i/sun8i_csc.c b/drivers/gpu/drm/sun4i/sun8i_csc.c
+index 2d5a2cf7cba2..45bd1ca06400 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_csc.c
++++ b/drivers/gpu/drm/sun4i/sun8i_csc.c
+@@ -238,6 +238,14 @@ static const u32 yuv2yuv_de3[2][3][3][12] = {
+ 	},
+ };
+ 
++static u32 sun8i_csc_base(struct sun8i_mixer *mixer, int layer)
++{
++	if (mixer->cfg->de_type == sun8i_mixer_de33)
++		return sun8i_channel_base(mixer, layer) - 0x800;
++	else
++		return ccsc_base[mixer->cfg->ccsc][layer];
++}
++
+ static void sun8i_csc_setup(struct regmap *map, u32 base,
+ 			    enum format_type fmt_type,
+ 			    enum drm_color_encoding encoding,
+@@ -358,6 +366,90 @@ static void sun8i_de3_ccsc_setup(struct sunxi_engine *engine, int layer,
+ 			   mask, val);
+ }
+ 
++/* extract constant from high word and invert sign if necessary */
++static u32 sun8i_de33_ccsc_get_constant(u32 value)
++{
++	value >>= 16;
++
++	if (value & BIT(15))
++		return 0x400 - (value & 0x3ff);
++
++	return value;
++}
++
++static void sun8i_de33_convert_table(const u32 *src, u32 *dst)
++{
++	dst[0] = sun8i_de33_ccsc_get_constant(src[3]);
++	dst[1] = sun8i_de33_ccsc_get_constant(src[7]);
++	dst[2] = sun8i_de33_ccsc_get_constant(src[11]);
++	memcpy(&dst[3], src, sizeof(u32) * 12);
++	dst[6] &= 0xffff;
++	dst[10] &= 0xffff;
++	dst[14] &= 0xffff;
++}
++
++static void sun8i_de33_ccsc_setup(struct sun8i_mixer *mixer, int layer,
++				  enum format_type fmt_type,
++				  enum drm_color_encoding encoding,
++				  enum drm_color_range range)
++{
++	u32 addr, val = 0, base, csc[15];
++	struct sunxi_engine *engine;
++	struct regmap *map;
++	const u32 *table;
++	int i;
++
++	table = yuv2rgb_de3[range][encoding];
++	base = sun8i_csc_base(mixer, layer);
++	engine = &mixer->engine;
++	map = engine->regs;
++
++	switch (fmt_type) {
++	case FORMAT_TYPE_RGB:
++		if (engine->format == MEDIA_BUS_FMT_RGB888_1X24)
++			break;
++		val = SUN8I_CSC_CTRL_EN;
++		sun8i_de33_convert_table(rgb2yuv_de3[engine->encoding], csc);
++		regmap_bulk_write(map, SUN50I_CSC_COEFF(base, 0), csc, 15);
++		break;
++	case FORMAT_TYPE_YUV:
++		table = sun8i_csc_get_de3_yuv_table(encoding, range,
++						    engine->format,
++						    engine->encoding);
++		if (!table)
++			break;
++		val = SUN8I_CSC_CTRL_EN;
++		sun8i_de33_convert_table(table, csc);
++		regmap_bulk_write(map, SUN50I_CSC_COEFF(base, 0), csc, 15);
++		break;
++	case FORMAT_TYPE_YVU:
++		table = sun8i_csc_get_de3_yuv_table(encoding, range,
++						    engine->format,
++						    engine->encoding);
++		if (!table)
++			table = yuv2yuv_de3[range][encoding][encoding];
++		val = SUN8I_CSC_CTRL_EN;
++		sun8i_de33_convert_table(table, csc);
++		for (i = 0; i < 15; i++) {
++			addr = SUN50I_CSC_COEFF(base, i);
++			if (i > 3) {
++				if (((i - 3) & 3) == 1)
++					addr = SUN50I_CSC_COEFF(base, i + 1);
++				else if (((i - 3) & 3) == 2)
++					addr = SUN50I_CSC_COEFF(base, i - 1);
++			}
++			regmap_write(map, addr, csc[i]);
++		}
++		break;
++	default:
++		val = 0;
++		DRM_WARN("Wrong CSC mode specified.\n");
++		return;
++	}
++
++	regmap_write(map, SUN8I_CSC_CTRL(base), val);
++}
++
+ void sun8i_csc_set_ccsc(struct sun8i_mixer *mixer, int layer,
+ 			enum format_type fmt_type,
+ 			enum drm_color_encoding encoding,
+@@ -369,6 +461,10 @@ void sun8i_csc_set_ccsc(struct sun8i_mixer *mixer, int layer,
+ 		sun8i_de3_ccsc_setup(&mixer->engine, layer,
+ 				     fmt_type, encoding, range);
+ 		return;
++	} else if (mixer->cfg->de_type == sun8i_mixer_de33) {
++		sun8i_de33_ccsc_setup(mixer, layer, fmt_type,
++				      encoding, range);
++		return;
+ 	}
+ 
+ 	if (layer < mixer->cfg->vi_num) {
+diff --git a/drivers/gpu/drm/sun4i/sun8i_csc.h b/drivers/gpu/drm/sun4i/sun8i_csc.h
+index b7546e06e315..2b762cb79f02 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_csc.h
++++ b/drivers/gpu/drm/sun4i/sun8i_csc.h
+@@ -20,6 +20,9 @@ struct sun8i_mixer;
+ #define SUN8I_CSC_CTRL(base)		((base) + 0x0)
+ #define SUN8I_CSC_COEFF(base, i)	((base) + 0x10 + 4 * (i))
+ 
++#define SUN50I_CSC_COEFF(base, i)	((base) + 0x04 + 4 * (i))
++#define SUN50I_CSC_ALPHA(base)		((base) + 0x40)
++
+ #define SUN8I_CSC_CTRL_EN		BIT(0)
+ 
+ enum format_type {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de33-fmt-add-Display-Engine-3.3-DE33-support.patch b/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de33-fmt-add-Display-Engine-3.3-DE33-support.patch
new file mode 100644
index 000000000000..cd060b36718e
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de33-fmt-add-Display-Engine-3.3-DE33-support.patch
@@ -0,0 +1,75 @@
+From 792b816c952bcf5dbf7c3ac7d90937bc71f0a7cd Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sun, 29 Sep 2024 22:04:57 +1300
+Subject: drm: sun4i: de33: fmt: add Display Engine 3.3 (DE33) support
+
+Like the DE3, the DE33 has a FMT (formatter) module, which
+provides YUV444 to YUV422/YUV420 conversion, format re-mapping and color
+depth conversion, although the DE33 module appears significantly more
+capable, including up to 4K video support.
+
+Add support for the DE33.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+Signed-off-by: Ryan Walklin <ryan@testtoast.com>
+---
+ drivers/gpu/drm/sun4i/sun50i_fmt.c | 21 +++++++++++++++++++--
+ drivers/gpu/drm/sun4i/sun50i_fmt.h |  1 +
+ 2 files changed, 20 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/gpu/drm/sun4i/sun50i_fmt.c b/drivers/gpu/drm/sun4i/sun50i_fmt.c
+index 050a8716ae86..39682d4e6d20 100644
+--- a/drivers/gpu/drm/sun4i/sun50i_fmt.c
++++ b/drivers/gpu/drm/sun4i/sun50i_fmt.c
+@@ -51,6 +51,19 @@ static void sun50i_fmt_de3_limits(u32 *limits, u32 colorspace, bool bit10)
+ 	}
+ }
+ 
++static void sun50i_fmt_de33_limits(u32 *limits, u32 colorspace)
++{
++	if (colorspace == SUN50I_FMT_CS_YUV444RGB) {
++		limits[0] = SUN50I_FMT_LIMIT(0, 4095);
++		limits[1] = SUN50I_FMT_LIMIT(0, 4095);
++		limits[2] = SUN50I_FMT_LIMIT(0, 4095);
++	} else {
++		limits[0] = SUN50I_FMT_LIMIT(256, 3840);
++		limits[1] = SUN50I_FMT_LIMIT(256, 3840);
++		limits[2] = SUN50I_FMT_LIMIT(256, 3840);
++	}
++}
++
+ void sun50i_fmt_setup(struct sun8i_mixer *mixer, u16 width,
+ 		      u16 height, u32 format)
+ {
+@@ -60,10 +73,14 @@ void sun50i_fmt_setup(struct sun8i_mixer *mixer, u16 width,
+ 
+ 	colorspace = sun50i_fmt_get_colorspace(format);
+ 	bit10 = sun50i_fmt_is_10bit(format);
+-	base = SUN50I_FMT_DE3;
++	base = mixer->cfg->de_type == sun8i_mixer_de3 ?
++		SUN50I_FMT_DE3 : SUN50I_FMT_DE33;
+ 	regs = sun8i_blender_regmap(mixer);
+ 
+-	sun50i_fmt_de3_limits(limit, colorspace, bit10);
++	if (mixer->cfg->de_type == sun8i_mixer_de3)
++		sun50i_fmt_de3_limits(limit, colorspace, bit10);
++	else
++		sun50i_fmt_de33_limits(limit, colorspace);
+ 
+ 	regmap_write(regs, SUN50I_FMT_CTRL(base), 0);
+ 
+diff --git a/drivers/gpu/drm/sun4i/sun50i_fmt.h b/drivers/gpu/drm/sun4i/sun50i_fmt.h
+index 4127f7206aad..3e60d5c788b3 100644
+--- a/drivers/gpu/drm/sun4i/sun50i_fmt.h
++++ b/drivers/gpu/drm/sun4i/sun50i_fmt.h
+@@ -9,6 +9,7 @@
+ #include "sun8i_mixer.h"
+ 
+ #define SUN50I_FMT_DE3 0xa8000
++#define SUN50I_FMT_DE33 0x5000
+ 
+ #define SUN50I_FMT_CTRL(base)   ((base) + 0x00)
+ #define SUN50I_FMT_SIZE(base)   ((base) + 0x04)
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de33-mixer-add-Display-Engine-3.3-DE33-support.patch b/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de33-mixer-add-Display-Engine-3.3-DE33-support.patch
new file mode 100644
index 000000000000..84e9458fb3fd
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de33-mixer-add-Display-Engine-3.3-DE33-support.patch
@@ -0,0 +1,302 @@
+From 66c111f3315d2c34c2f9bfb39de61bf3ec46a5f6 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sun, 29 Sep 2024 22:04:55 +1300
+Subject: drm: sun4i: de33: mixer: add Display Engine 3.3 (DE33) support
+
+The DE33 is a newer version of the Allwinner Display Engine IP block,
+found in the H616, H618, H700 and T507 SoCs. DE2 and DE3 are already
+supported by the mainline driver.
+
+Notable features (from the H616 datasheet and implemented):
+- 4096 x 2048 (4K) output support
+- AFBC ARM Frame Buffer Compression support
+- YUV420 input support
+
+The DE2 and DE3 engines have a blender register range within the
+mixer engine register map, whereas the DE33 separates this out into
+a separate display group, and adds a top register map.
+
+Extend the mixer to support the DE33.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+Signed-off-by: Ryan Walklin <ryan@testtoast.com>
+---
+ drivers/gpu/drm/sun4i/sun8i_mixer.c | 109 ++++++++++++++++++++++++----
+ drivers/gpu/drm/sun4i/sun8i_mixer.h |  16 +++-
+ 2 files changed, 108 insertions(+), 17 deletions(-)
+
+diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
+index 600084286b39..204fc8055b32 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
++++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
+@@ -321,8 +321,12 @@ static void sun8i_mixer_commit(struct sunxi_engine *engine,
+ 	regmap_write(bld_regs, SUN8I_MIXER_BLEND_PIPE_CTL(bld_base),
+ 		     pipe_en | SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN(0));
+ 
+-	regmap_write(engine->regs, SUN8I_MIXER_GLOBAL_DBUFF,
+-		     SUN8I_MIXER_GLOBAL_DBUFF_ENABLE);
++	if (mixer->cfg->de_type == sun8i_mixer_de33)
++		regmap_write(mixer->top_regs, SUN50I_MIXER_GLOBAL_DBUFF,
++			     SUN8I_MIXER_GLOBAL_DBUFF_ENABLE);
++	else
++		regmap_write(engine->regs, SUN8I_MIXER_GLOBAL_DBUFF,
++			     SUN8I_MIXER_GLOBAL_DBUFF_ENABLE);
+ }
+ 
+ static struct drm_plane **sun8i_layers_init(struct drm_device *drm,
+@@ -371,25 +375,33 @@ static void sun8i_mixer_mode_set(struct sunxi_engine *engine,
+ 				 const struct drm_display_mode *mode)
+ {
+ 	struct sun8i_mixer *mixer = engine_to_sun8i_mixer(engine);
++	struct regmap *bld_regs, *disp_regs;
+ 	u32 bld_base, size, val;
+ 	bool interlaced;
+ 
+ 	bld_base = sun8i_blender_base(mixer);
++	bld_regs = sun8i_blender_regmap(mixer);
+ 	interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
+ 	size = SUN8I_MIXER_SIZE(mode->hdisplay, mode->vdisplay);
+ 
+ 	DRM_DEBUG_DRIVER("Updating global size W: %u H: %u\n",
+ 			 mode->hdisplay, mode->vdisplay);
+ 
+-	regmap_write(engine->regs, SUN8I_MIXER_GLOBAL_SIZE, size);
+-	regmap_write(engine->regs, SUN8I_MIXER_BLEND_OUTSIZE(bld_base), size);
++	if (mixer->cfg->de_type == sun8i_mixer_de33) {
++		disp_regs = mixer->disp_regs;
++		regmap_write(mixer->top_regs, SUN50I_MIXER_GLOBAL_SIZE, size);
++	} else {
++		disp_regs = mixer->engine.regs;
++		regmap_write(mixer->engine.regs, SUN8I_MIXER_GLOBAL_SIZE, size);
++	}
++	regmap_write(bld_regs, SUN8I_MIXER_BLEND_OUTSIZE(bld_base), size);
+ 
+ 	if (interlaced)
+ 		val = SUN8I_MIXER_BLEND_OUTCTL_INTERLACED;
+ 	else
+ 		val = 0;
+ 
+-	regmap_update_bits(engine->regs, SUN8I_MIXER_BLEND_OUTCTL(bld_base),
++	regmap_update_bits(bld_regs, SUN8I_MIXER_BLEND_OUTCTL(bld_base),
+ 			   SUN8I_MIXER_BLEND_OUTCTL_INTERLACED, val);
+ 
+ 	DRM_DEBUG_DRIVER("Switching display mixer interlaced mode %s\n",
+@@ -400,10 +412,8 @@ static void sun8i_mixer_mode_set(struct sunxi_engine *engine,
+ 	else
+ 		val = 0xff108080;
+ 
+-	regmap_write(mixer->engine.regs,
+-		     SUN8I_MIXER_BLEND_BKCOLOR(bld_base), val);
+-	regmap_write(mixer->engine.regs,
+-		     SUN8I_MIXER_BLEND_ATTR_FCOLOR(bld_base, 0), val);
++	regmap_write(disp_regs, SUN8I_MIXER_BLEND_BKCOLOR(bld_base), val);
++	regmap_write(disp_regs, SUN8I_MIXER_BLEND_ATTR_FCOLOR(bld_base, 0), val);
+ 
+ 	if (mixer->cfg->has_formatter)
+ 		sun50i_fmt_setup(mixer, mode->hdisplay,
+@@ -443,12 +453,29 @@ static const struct sunxi_engine_ops sun8i_engine_ops = {
+ };
+ 
+ static const struct regmap_config sun8i_mixer_regmap_config = {
++	.name		= "layers",
+ 	.reg_bits	= 32,
+ 	.val_bits	= 32,
+ 	.reg_stride	= 4,
+ 	.max_register	= 0xffffc, /* guessed */
+ };
+ 
++static const struct regmap_config sun8i_top_regmap_config = {
++	.name		= "top",
++	.reg_bits	= 32,
++	.val_bits	= 32,
++	.reg_stride	= 4,
++	.max_register	= 0x3c,
++};
++
++static const struct regmap_config sun8i_disp_regmap_config = {
++	.name		= "display",
++	.reg_bits	= 32,
++	.val_bits	= 32,
++	.reg_stride	= 4,
++	.max_register	= 0x20000,
++};
++
+ static int sun8i_mixer_of_get_id(struct device_node *node)
+ {
+ 	struct device_node *ep, *remote;
+@@ -471,33 +498,45 @@ static int sun8i_mixer_of_get_id(struct device_node *node)
+ 
+ static void sun8i_mixer_init(struct sun8i_mixer *mixer)
+ {
++	struct regmap *top_regs, *disp_regs;
+ 	unsigned int base = sun8i_blender_base(mixer);
+ 	int plane_cnt, i;
+ 
++	if (mixer->cfg->de_type == sun8i_mixer_de33) {
++		top_regs = mixer->top_regs;
++		disp_regs = mixer->disp_regs;
++	} else {
++		top_regs = mixer->engine.regs;
++		disp_regs = mixer->engine.regs;
++	}
++
+ 	/* Enable the mixer */
+-	regmap_write(mixer->engine.regs, SUN8I_MIXER_GLOBAL_CTL,
++	regmap_write(top_regs, SUN8I_MIXER_GLOBAL_CTL,
+ 		     SUN8I_MIXER_GLOBAL_CTL_RT_EN);
+ 
++	if (mixer->cfg->de_type == sun8i_mixer_de33)
++		regmap_write(top_regs, SUN50I_MIXER_GLOBAL_CLK, 1);
++
+ 	/* Set background color to black */
+-	regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_BKCOLOR(base),
++	regmap_write(disp_regs, SUN8I_MIXER_BLEND_BKCOLOR(base),
+ 		     SUN8I_MIXER_BLEND_COLOR_BLACK);
+ 
+ 	/*
+ 	 * Set fill color of bottom plane to black. Generally not needed
+ 	 * except when VI plane is at bottom (zpos = 0) and enabled.
+ 	 */
+-	regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base),
++	regmap_write(disp_regs, SUN8I_MIXER_BLEND_PIPE_CTL(base),
+ 		     SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN(0));
+-	regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_ATTR_FCOLOR(base, 0),
++	regmap_write(disp_regs, SUN8I_MIXER_BLEND_ATTR_FCOLOR(base, 0),
+ 		     SUN8I_MIXER_BLEND_COLOR_BLACK);
+ 
+ 	plane_cnt = mixer->cfg->vi_num + mixer->cfg->ui_num;
+ 	for (i = 0; i < plane_cnt; i++)
+-		regmap_write(mixer->engine.regs,
++		regmap_write(disp_regs,
+ 			     SUN8I_MIXER_BLEND_MODE(base, i),
+ 			     SUN8I_MIXER_BLEND_MODE_DEF);
+ 
+-	regmap_update_bits(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base),
++	regmap_update_bits(disp_regs, SUN8I_MIXER_BLEND_PIPE_CTL(base),
+ 			   SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK, 0);
+ }
+ 
+@@ -573,6 +612,30 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,
+ 		return PTR_ERR(mixer->engine.regs);
+ 	}
+ 
++	if (mixer->cfg->de_type == sun8i_mixer_de33) {
++		regs = devm_platform_ioremap_resource(pdev, 1);
++		if (IS_ERR(regs))
++			return PTR_ERR(regs);
++
++		mixer->top_regs = devm_regmap_init_mmio(dev, regs,
++							&sun8i_top_regmap_config);
++		if (IS_ERR(mixer->top_regs)) {
++			dev_err(dev, "Couldn't create the top regmap\n");
++			return PTR_ERR(mixer->top_regs);
++		}
++
++		regs = devm_platform_ioremap_resource(pdev, 2);
++		if (IS_ERR(regs))
++			return PTR_ERR(regs);
++
++		mixer->disp_regs = devm_regmap_init_mmio(dev, regs,
++							 &sun8i_disp_regmap_config);
++		if (IS_ERR(mixer->disp_regs)) {
++			dev_err(dev, "Couldn't create the disp regmap\n");
++			return PTR_ERR(mixer->disp_regs);
++		}
++	}
++
+ 	mixer->reset = devm_reset_control_get(dev, NULL);
+ 	if (IS_ERR(mixer->reset)) {
+ 		dev_err(dev, "Couldn't get our reset line\n");
+@@ -787,6 +850,18 @@ static const struct sun8i_mixer_cfg sun50i_h6_mixer0_cfg = {
+ 	.vi_num		= 1,
+ };
+ 
++static const struct sun8i_mixer_cfg sun50i_h616_mixer0_cfg = {
++	.ccsc		= CCSC_MIXER0_LAYOUT,
++	.de_type	= sun8i_mixer_de33,
++	.has_formatter	= 1,
++	.mod_rate	= 600000000,
++	.scaler_mask	= 0xf,
++	.scanline_yuv	= 4096,
++	.ui_num		= 3,
++	.vi_num		= 1,
++	.map		= {0, 6, 7, 8},
++};
++
+ static const struct of_device_id sun8i_mixer_of_table[] = {
+ 	{
+ 		.compatible = "allwinner,sun8i-a83t-de2-mixer-0",
+@@ -832,6 +907,10 @@ static const struct of_device_id sun8i_mixer_of_table[] = {
+ 		.compatible = "allwinner,sun50i-h6-de3-mixer-0",
+ 		.data = &sun50i_h6_mixer0_cfg,
+ 	},
++	{
++		.compatible = "allwinner,sun50i-h616-de33-mixer-0",
++		.data = &sun50i_h616_mixer0_cfg,
++	},
+ 	{ }
+ };
+ MODULE_DEVICE_TABLE(of, sun8i_mixer_of_table);
+diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h
+index 75facc7d1fa6..26b001164647 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_mixer.h
++++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h
+@@ -21,6 +21,10 @@
+ #define SUN8I_MIXER_GLOBAL_DBUFF		0x8
+ #define SUN8I_MIXER_GLOBAL_SIZE			0xc
+ 
++#define SUN50I_MIXER_GLOBAL_SIZE		0x8
++#define SUN50I_MIXER_GLOBAL_CLK			0xc
++#define SUN50I_MIXER_GLOBAL_DBUFF		0x10
++
+ #define SUN8I_MIXER_GLOBAL_CTL_RT_EN		BIT(0)
+ 
+ #define SUN8I_MIXER_GLOBAL_DBUFF_ENABLE		BIT(0)
+@@ -154,6 +158,7 @@ enum {
+ enum sun8i_mixer_type {
+ 	sun8i_mixer_de2,
+ 	sun8i_mixer_de3,
++	sun8i_mixer_de33,
+ };
+ 
+ /**
+@@ -180,6 +185,7 @@ struct sun8i_mixer_cfg {
+ 	unsigned int	de_type;
+ 	unsigned int    has_formatter : 1;
+ 	unsigned int	scanline_yuv;
++	unsigned int	map[6];
+ };
+ 
+ struct sun8i_mixer {
+@@ -191,6 +197,9 @@ struct sun8i_mixer {
+ 
+ 	struct clk			*bus_clk;
+ 	struct clk			*mod_clk;
++
++	struct regmap			*top_regs;
++	struct regmap			*disp_regs;
+ };
+ 
+ enum {
+@@ -227,13 +236,16 @@ sun8i_blender_base(struct sun8i_mixer *mixer)
+ static inline struct regmap *
+ sun8i_blender_regmap(struct sun8i_mixer *mixer)
+ {
+-	return mixer->engine.regs;
++	return mixer->cfg->de_type == sun8i_mixer_de33 ?
++		mixer->disp_regs : mixer->engine.regs;
+ }
+ 
+ static inline u32
+ sun8i_channel_base(struct sun8i_mixer *mixer, int channel)
+ {
+-	if (mixer->cfg->de_type == sun8i_mixer_de3)
++	if (mixer->cfg->de_type == sun8i_mixer_de33)
++		return mixer->cfg->map[channel] * 0x20000 + DE2_CH_SIZE;
++	else if (mixer->cfg->de_type == sun8i_mixer_de3)
+ 		return DE3_CH_BASE + channel * DE3_CH_SIZE;
+ 	else
+ 		return DE2_CH_BASE + channel * DE2_CH_SIZE;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de33-vi_scaler-add-Display-Engine-3.3-DE33-support.patch b/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de33-vi_scaler-add-Display-Engine-3.3-DE33-support.patch
new file mode 100644
index 000000000000..9028d40a3256
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-de33-vi_scaler-add-Display-Engine-3.3-DE33-support.patch
@@ -0,0 +1,77 @@
+From 412294545ec91452cc3eccff746a4243879b4cde Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sun, 29 Sep 2024 22:04:56 +1300
+Subject: drm: sun4i: de33: vi_scaler: add Display Engine 3.3 (DE33) support
+
+The vi_scaler appears to be used in preference to the ui_scaler module
+for hardware video scaling in the DE33.
+
+Enable support for this scaler.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+Signed-off-by: Ryan Walklin <ryan@testtoast.com>
+---
+ drivers/gpu/drm/sun4i/sun8i_ui_layer.c  | 19 +++++++++++++++----
+ drivers/gpu/drm/sun4i/sun8i_vi_scaler.c |  7 ++++++-
+ 2 files changed, 21 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
+index 7f1231cf0f01..180be9d67d9c 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
++++ b/drivers/gpu/drm/sun4i/sun8i_ui_layer.c
+@@ -95,12 +95,23 @@ static int sun8i_ui_layer_update_coord(struct sun8i_mixer *mixer, int channel,
+ 		hscale = state->src_w / state->crtc_w;
+ 		vscale = state->src_h / state->crtc_h;
+ 
+-		sun8i_ui_scaler_setup(mixer, channel, src_w, src_h, dst_w,
+-				      dst_h, hscale, vscale, hphase, vphase);
+-		sun8i_ui_scaler_enable(mixer, channel, true);
++		if (mixer->cfg->de_type == sun8i_mixer_de33) {
++			sun8i_vi_scaler_setup(mixer, channel, src_w, src_h,
++					      dst_w, dst_h, hscale, vscale,
++					      hphase, vphase,
++					      state->fb->format);
++		} else {
++			sun8i_ui_scaler_setup(mixer, channel, src_w, src_h,
++					      dst_w, dst_h, hscale, vscale,
++					      hphase, vphase);
++			sun8i_ui_scaler_enable(mixer, channel, true);
++		}
+ 	} else {
+ 		DRM_DEBUG_DRIVER("HW scaling is not needed\n");
+-		sun8i_ui_scaler_enable(mixer, channel, false);
++		if (mixer->cfg->de_type == sun8i_mixer_de33)
++			sun8i_vi_scaler_disable(mixer, channel);
++		else
++			sun8i_ui_scaler_enable(mixer, channel, false);
+ 	}
+ 
+ 	/* Set base coordinates */
+diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c b/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c
+index e7242301b312..9c7f6e7d71d5 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c
++++ b/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c
+@@ -835,7 +835,9 @@ static const u32 bicubic4coefftab32[480] = {
+ 
+ static u32 sun8i_vi_scaler_base(struct sun8i_mixer *mixer, int channel)
+ {
+-	if (mixer->cfg->de_type == sun8i_mixer_de3)
++	if (mixer->cfg->de_type == sun8i_mixer_de33)
++		return sun8i_channel_base(mixer, channel) + 0x3000;
++	else if (mixer->cfg->de_type == sun8i_mixer_de3)
+ 		return DE3_VI_SCALER_UNIT_BASE +
+ 		       DE3_VI_SCALER_UNIT_SIZE * channel;
+ 	else
+@@ -845,6 +847,9 @@ static u32 sun8i_vi_scaler_base(struct sun8i_mixer *mixer, int channel)
+ 
+ static bool sun8i_vi_scaler_is_vi_plane(struct sun8i_mixer *mixer, int channel)
+ {
++	if (mixer->cfg->de_type == sun8i_mixer_de33)
++		return mixer->cfg->map[channel] < mixer->cfg->vi_num;
++
+ 	return true;
+ }
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-support-YUV-formats-in-VI-scaler.patch b/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-support-YUV-formats-in-VI-scaler.patch
new file mode 100644
index 000000000000..1aff0b4bcde5
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-support-YUV-formats-in-VI-scaler.patch
@@ -0,0 +1,140 @@
+From e0de25f60a3535d345b33dcc541c814499151788 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sun, 29 Sep 2024 22:04:44 +1300
+Subject: drm: sun4i: support YUV formats in VI scaler
+
+Now that YUV formats are available, enable support in the VI scaler.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+Signed-off-by: Ryan Walklin <ryan@testtoast.com>
+
+Changelog v4..v5:
+- Add commit description
+---
+ drivers/gpu/drm/sun4i/sun8i_vi_scaler.c | 85 +++++++++++++++++--------
+ 1 file changed, 58 insertions(+), 27 deletions(-)
+
+diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c b/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c
+index 7ba75011adf9..2e49a6e5f1f1 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c
++++ b/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c
+@@ -843,6 +843,11 @@ static u32 sun8i_vi_scaler_base(struct sun8i_mixer *mixer, int channel)
+ 		       DE2_VI_SCALER_UNIT_SIZE * channel;
+ }
+ 
++static bool sun8i_vi_scaler_is_vi_plane(struct sun8i_mixer *mixer, int channel)
++{
++	return true;
++}
++
+ static int sun8i_vi_scaler_coef_index(unsigned int step)
+ {
+ 	unsigned int scale, int_part, float_part;
+@@ -867,44 +872,65 @@ static int sun8i_vi_scaler_coef_index(unsigned int step)
+ 	}
+ }
+ 
+-static void sun8i_vi_scaler_set_coeff(struct regmap *map, u32 base,
+-				      u32 hstep, u32 vstep,
+-				      const struct drm_format_info *format)
++static void sun8i_vi_scaler_set_coeff_vi(struct regmap *map, u32 base,
++					 u32 hstep, u32 vstep,
++					 const struct drm_format_info *format)
+ {
+ 	const u32 *ch_left, *ch_right, *cy;
+-	int offset, i;
++	int offset;
+ 
+-	if (format->hsub == 1 && format->vsub == 1) {
+-		ch_left = lan3coefftab32_left;
+-		ch_right = lan3coefftab32_right;
+-		cy = lan2coefftab32;
+-	} else {
++	if (format->is_yuv) {
+ 		ch_left = bicubic8coefftab32_left;
+ 		ch_right = bicubic8coefftab32_right;
+ 		cy = bicubic4coefftab32;
++	} else {
++		ch_left = lan3coefftab32_left;
++		ch_right = lan3coefftab32_right;
++		cy = lan2coefftab32;
+ 	}
+ 
+ 	offset = sun8i_vi_scaler_coef_index(hstep) *
+ 			SUN8I_VI_SCALER_COEFF_COUNT;
+-	for (i = 0; i < SUN8I_VI_SCALER_COEFF_COUNT; i++) {
+-		regmap_write(map, SUN8I_SCALER_VSU_YHCOEFF0(base, i),
+-			     lan3coefftab32_left[offset + i]);
+-		regmap_write(map, SUN8I_SCALER_VSU_YHCOEFF1(base, i),
+-			     lan3coefftab32_right[offset + i]);
+-		regmap_write(map, SUN8I_SCALER_VSU_CHCOEFF0(base, i),
+-			     ch_left[offset + i]);
+-		regmap_write(map, SUN8I_SCALER_VSU_CHCOEFF1(base, i),
+-			     ch_right[offset + i]);
+-	}
++	regmap_bulk_write(map, SUN8I_SCALER_VSU_YHCOEFF0(base, 0),
++			  &lan3coefftab32_left[offset],
++			  SUN8I_VI_SCALER_COEFF_COUNT);
++	regmap_bulk_write(map, SUN8I_SCALER_VSU_YHCOEFF1(base, 0),
++			  &lan3coefftab32_right[offset],
++			  SUN8I_VI_SCALER_COEFF_COUNT);
++	regmap_bulk_write(map, SUN8I_SCALER_VSU_CHCOEFF0(base, 0),
++			  &ch_left[offset], SUN8I_VI_SCALER_COEFF_COUNT);
++	regmap_bulk_write(map, SUN8I_SCALER_VSU_CHCOEFF1(base, 0),
++			  &ch_right[offset], SUN8I_VI_SCALER_COEFF_COUNT);
+ 
+ 	offset = sun8i_vi_scaler_coef_index(hstep) *
+ 			SUN8I_VI_SCALER_COEFF_COUNT;
+-	for (i = 0; i < SUN8I_VI_SCALER_COEFF_COUNT; i++) {
+-		regmap_write(map, SUN8I_SCALER_VSU_YVCOEFF(base, i),
+-			     lan2coefftab32[offset + i]);
+-		regmap_write(map, SUN8I_SCALER_VSU_CVCOEFF(base, i),
+-			     cy[offset + i]);
+-	}
++	regmap_bulk_write(map, SUN8I_SCALER_VSU_YVCOEFF(base, 0),
++			  &lan2coefftab32[offset], SUN8I_VI_SCALER_COEFF_COUNT);
++	regmap_bulk_write(map, SUN8I_SCALER_VSU_CVCOEFF(base, 0),
++			  &cy[offset], SUN8I_VI_SCALER_COEFF_COUNT);
++}
++
++static void sun8i_vi_scaler_set_coeff_ui(struct regmap *map, u32 base,
++					 u32 hstep, u32 vstep,
++					 const struct drm_format_info *format)
++{
++	const u32 *table;
++	int offset;
++
++	offset = sun8i_vi_scaler_coef_index(hstep) *
++			SUN8I_VI_SCALER_COEFF_COUNT;
++	regmap_bulk_write(map, SUN8I_SCALER_VSU_YHCOEFF0(base, 0),
++			  &lan2coefftab32[offset], SUN8I_VI_SCALER_COEFF_COUNT);
++	offset = sun8i_vi_scaler_coef_index(vstep) *
++			SUN8I_VI_SCALER_COEFF_COUNT;
++	regmap_bulk_write(map, SUN8I_SCALER_VSU_YVCOEFF(base, 0),
++			  &lan2coefftab32[offset], SUN8I_VI_SCALER_COEFF_COUNT);
++
++	table = format->is_yuv ? bicubic4coefftab32 : lan2coefftab32;
++	offset = sun8i_vi_scaler_coef_index(hstep) *
++			SUN8I_VI_SCALER_COEFF_COUNT;
++	regmap_bulk_write(map, SUN8I_SCALER_VSU_CHCOEFF0(base, 0),
++			  &table[offset], SUN8I_VI_SCALER_COEFF_COUNT);
+ }
+ 
+ void sun8i_vi_scaler_enable(struct sun8i_mixer *mixer, int layer, bool enable)
+@@ -994,6 +1020,11 @@ void sun8i_vi_scaler_setup(struct sun8i_mixer *mixer, int layer,
+ 		     SUN8I_SCALER_VSU_CHPHASE(base), chphase);
+ 	regmap_write(mixer->engine.regs,
+ 		     SUN8I_SCALER_VSU_CVPHASE(base), cvphase);
+-	sun8i_vi_scaler_set_coeff(mixer->engine.regs, base,
+-				  hscale, vscale, format);
++
++	if (sun8i_vi_scaler_is_vi_plane(mixer, layer))
++		sun8i_vi_scaler_set_coeff_vi(mixer->engine.regs, base,
++					     hscale, vscale, format);
++	else
++		sun8i_vi_scaler_set_coeff_ui(mixer->engine.regs, base,
++					     hscale, vscale, format);
+ }
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-vi_scaler-refactor-vi_scaler-enablement.patch b/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-vi_scaler-refactor-vi_scaler-enablement.patch
new file mode 100644
index 000000000000..59a56dd02497
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.drm/drm-sun4i-vi_scaler-refactor-vi_scaler-enablement.patch
@@ -0,0 +1,100 @@
+From 0c10a80b8e37d9a7fc57d8bf968c70419423065a Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sun, 29 Sep 2024 22:04:47 +1300
+Subject: drm: sun4i: vi_scaler refactor vi_scaler enablement
+
+If the video scaler is required, then it is obligatory to set the
+relevant register to enable it, so move this to the
+sun8i_vi_scaler_setup() function.
+
+This simplifies the alternate case (scaler not required) so replace the
+vi_scaler_enable() function with a vi_scaler_disable() function.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+Signed-off-by: Ryan Walklin <ryan@testtoast.com>
+---
+ drivers/gpu/drm/sun4i/sun8i_vi_layer.c  |  3 +--
+ drivers/gpu/drm/sun4i/sun8i_vi_scaler.c | 21 +++++++++++----------
+ drivers/gpu/drm/sun4i/sun8i_vi_scaler.h |  2 +-
+ 3 files changed, 13 insertions(+), 13 deletions(-)
+
+diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
+index 4647e9bcccaa..e348fd0a3d81 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
++++ b/drivers/gpu/drm/sun4i/sun8i_vi_layer.c
+@@ -156,10 +156,9 @@ static int sun8i_vi_layer_update_coord(struct sun8i_mixer *mixer, int channel,
+ 		sun8i_vi_scaler_setup(mixer, channel, src_w, src_h, dst_w,
+ 				      dst_h, hscale, vscale, hphase, vphase,
+ 				      format);
+-		sun8i_vi_scaler_enable(mixer, channel, true);
+ 	} else {
+ 		DRM_DEBUG_DRIVER("HW scaling is not needed\n");
+-		sun8i_vi_scaler_enable(mixer, channel, false);
++		sun8i_vi_scaler_disable(mixer, channel);
+ 	}
+ 
+ 	regmap_write(mixer->engine.regs,
+diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c b/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c
+index aa346c3beb30..e7242301b312 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c
++++ b/drivers/gpu/drm/sun4i/sun8i_vi_scaler.c
+@@ -933,20 +933,13 @@ static void sun8i_vi_scaler_set_coeff_ui(struct regmap *map, u32 base,
+ 			  &table[offset], SUN8I_VI_SCALER_COEFF_COUNT);
+ }
+ 
+-void sun8i_vi_scaler_enable(struct sun8i_mixer *mixer, int layer, bool enable)
++void sun8i_vi_scaler_disable(struct sun8i_mixer *mixer, int layer)
+ {
+-	u32 val, base;
++	u32 base;
+ 
+ 	base = sun8i_vi_scaler_base(mixer, layer);
+ 
+-	if (enable)
+-		val = SUN8I_SCALER_VSU_CTRL_EN |
+-		      SUN8I_SCALER_VSU_CTRL_COEFF_RDY;
+-	else
+-		val = 0;
+-
+-	regmap_write(mixer->engine.regs,
+-		     SUN8I_SCALER_VSU_CTRL(base), val);
++	regmap_write(mixer->engine.regs, SUN8I_SCALER_VSU_CTRL(base), 0);
+ }
+ 
+ void sun8i_vi_scaler_setup(struct sun8i_mixer *mixer, int layer,
+@@ -982,6 +975,9 @@ void sun8i_vi_scaler_setup(struct sun8i_mixer *mixer, int layer,
+ 		cvphase = vphase;
+ 	}
+ 
++	regmap_write(mixer->engine.regs, SUN8I_SCALER_VSU_CTRL(base),
++		     SUN8I_SCALER_VSU_CTRL_EN);
++
+ 	if (mixer->cfg->de_type >= sun8i_mixer_de3) {
+ 		u32 val;
+ 
+@@ -1027,4 +1023,9 @@ void sun8i_vi_scaler_setup(struct sun8i_mixer *mixer, int layer,
+ 	else
+ 		sun8i_vi_scaler_set_coeff_ui(mixer->engine.regs, base,
+ 					     hscale, vscale, format);
++
++	if (mixer->cfg->de_type <= sun8i_mixer_de3)
++		regmap_write(mixer->engine.regs, SUN8I_SCALER_VSU_CTRL(base),
++			     SUN8I_SCALER_VSU_CTRL_EN |
++			     SUN8I_SCALER_VSU_CTRL_COEFF_RDY);
+ }
+diff --git a/drivers/gpu/drm/sun4i/sun8i_vi_scaler.h b/drivers/gpu/drm/sun4i/sun8i_vi_scaler.h
+index 68f6593b369a..e801bc7a4189 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_vi_scaler.h
++++ b/drivers/gpu/drm/sun4i/sun8i_vi_scaler.h
+@@ -69,7 +69,7 @@
+ #define SUN50I_SCALER_VSU_ANGLE_SHIFT(x)		(((x) << 16) & 0xF)
+ #define SUN50I_SCALER_VSU_ANGLE_OFFSET(x)		((x) & 0xFF)
+ 
+-void sun8i_vi_scaler_enable(struct sun8i_mixer *mixer, int layer, bool enable);
++void sun8i_vi_scaler_disable(struct sun8i_mixer *mixer, int layer);
+ void sun8i_vi_scaler_setup(struct sun8i_mixer *mixer, int layer,
+ 			   u32 src_w, u32 src_h, u32 dst_w, u32 dst_h,
+ 			   u32 hscale, u32 vscale, u32 hphase, u32 vphase,
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.drm/dt-bindings-allwinner-add-H616-DE33-bus-binding.patch b/patch/kernel/archive/sunxi-6.14/patches.drm/dt-bindings-allwinner-add-H616-DE33-bus-binding.patch
new file mode 100644
index 000000000000..86b0c0cb30ca
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.drm/dt-bindings-allwinner-add-H616-DE33-bus-binding.patch
@@ -0,0 +1,35 @@
+From b8344d8eb9d000bc2984a5fcafc25b527f361b5b Mon Sep 17 00:00:00 2001
+From: Ryan Walklin <ryan@testtoast.com>
+Date: Sun, 29 Sep 2024 22:04:51 +1300
+Subject: dt-bindings: allwinner: add H616 DE33 bus binding
+
+The Allwinner H616 and variants have a new display engine revision
+(DE33).
+
+Add a display engine bus binding for the DE33.
+
+Signed-off-by: Ryan Walklin <ryan@testtoast.com>
+Acked-by: Conor Dooley <conor.dooley@microchip.com>
+Reviewed-by: Chen-Yu Tsai <wens@csie.org>
+---
+ .../devicetree/bindings/bus/allwinner,sun50i-a64-de2.yaml     | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/Documentation/devicetree/bindings/bus/allwinner,sun50i-a64-de2.yaml b/Documentation/devicetree/bindings/bus/allwinner,sun50i-a64-de2.yaml
+index 9845a187bdf6..ea7ee89158c6 100644
+--- a/Documentation/devicetree/bindings/bus/allwinner,sun50i-a64-de2.yaml
++++ b/Documentation/devicetree/bindings/bus/allwinner,sun50i-a64-de2.yaml
+@@ -24,7 +24,9 @@ properties:
+     oneOf:
+       - const: allwinner,sun50i-a64-de2
+       - items:
+-          - const: allwinner,sun50i-h6-de3
++          - enum:
++              - allwinner,sun50i-h6-de3
++              - allwinner,sun50i-h616-de33
+           - const: allwinner,sun50i-a64-de2
+ 
+   reg:
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.drm/dt-bindings-allwinner-add-H616-DE33-clock-binding.patch b/patch/kernel/archive/sunxi-6.14/patches.drm/dt-bindings-allwinner-add-H616-DE33-clock-binding.patch
new file mode 100644
index 000000000000..65411eb517a8
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.drm/dt-bindings-allwinner-add-H616-DE33-clock-binding.patch
@@ -0,0 +1,32 @@
+From 58a606c8136c57d23b4e35f0f50cb140f1d65d9b Mon Sep 17 00:00:00 2001
+From: Ryan Walklin <ryan@testtoast.com>
+Date: Sun, 29 Sep 2024 22:04:52 +1300
+Subject: dt-bindings: allwinner: add H616 DE33 clock binding
+
+The Allwinner H616 and variants have a new display engine revision
+(DE33).
+
+Add a clock binding for the DE33.
+
+Signed-off-by: Ryan Walklin <ryan@testtoast.com>
+Acked-by: Conor Dooley <conor.dooley@microchip.com>
+Reviewed-by: Chen-Yu Tsai <wens@csie.org>
+---
+ .../devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml  | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml
+index 70369bd633e4..7fcd55d468d4 100644
+--- a/Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml
++++ b/Documentation/devicetree/bindings/clock/allwinner,sun8i-a83t-de2-clk.yaml
+@@ -25,6 +25,7 @@ properties:
+       - const: allwinner,sun50i-a64-de2-clk
+       - const: allwinner,sun50i-h5-de2-clk
+       - const: allwinner,sun50i-h6-de3-clk
++      - const: allwinner,sun50i-h616-de33-clk
+       - items:
+           - const: allwinner,sun8i-r40-de2-clk
+           - const: allwinner,sun8i-h3-de2-clk
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.drm/dt-bindings-allwinner-add-H616-DE33-mixer-binding.patch b/patch/kernel/archive/sunxi-6.14/patches.drm/dt-bindings-allwinner-add-H616-DE33-mixer-binding.patch
new file mode 100644
index 000000000000..d3a92736cc03
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.drm/dt-bindings-allwinner-add-H616-DE33-mixer-binding.patch
@@ -0,0 +1,36 @@
+From 12d7983166ed867dd72c023af036b1397aec66ba Mon Sep 17 00:00:00 2001
+From: Ryan Walklin <ryan@testtoast.com>
+Date: Sun, 29 Sep 2024 22:04:53 +1300
+Subject: dt-bindings: allwinner: add H616 DE33 mixer binding
+
+The Allwinner H616 and variants have a new display engine revision
+(DE33).
+
+The mixer configuration registers are significantly different to the DE3
+and DE2 revisions, being split into separate top and display blocks,
+therefore a fallback for the mixer compatible is not provided.
+
+Add a display engine mixer binding for the DE33.
+
+Signed-off-by: Ryan Walklin <ryan@testtoast.com>
+Acked-by: Conor Dooley <conor.dooley@microchip.com>
+Reviewed-by: Chen-Yu Tsai <wens@csie.org>
+---
+ .../bindings/display/allwinner,sun8i-a83t-de2-mixer.yaml         | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-de2-mixer.yaml b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-de2-mixer.yaml
+index b75c1ec686ad..c37eb8ae1b8e 100644
+--- a/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-de2-mixer.yaml
++++ b/Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-de2-mixer.yaml
+@@ -24,6 +24,7 @@ properties:
+       - allwinner,sun50i-a64-de2-mixer-0
+       - allwinner,sun50i-a64-de2-mixer-1
+       - allwinner,sun50i-h6-de3-mixer-0
++      - allwinner,sun50i-h616-de33-mixer-0
+ 
+   reg:
+     maxItems: 1
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.drm/dt-bindings-gpu-mali-bifrost-Add-Allwinner-H616-compatible.patch b/patch/kernel/archive/sunxi-6.14/patches.drm/dt-bindings-gpu-mali-bifrost-Add-Allwinner-H616-compatible.patch
new file mode 100644
index 000000000000..73e24e0afa40
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.drm/dt-bindings-gpu-mali-bifrost-Add-Allwinner-H616-compatible.patch
@@ -0,0 +1,30 @@
+From 7f350d05012873c129458241792d005ef1344d9a Mon Sep 17 00:00:00 2001
+From: Andre Przywara <andre.przywara@arm.com>
+Date: Fri, 21 Feb 2025 00:58:00 +0000
+Subject: dt-bindings: gpu: mali-bifrost: Add Allwinner H616 compatible
+
+The Allwinner H616 SoC has a Mali-G31 MP2 GPU, which is of the Mali
+Bifrost family.
+Add the SoC specific compatible string and pair it with the bifrost
+fallback compatible.
+
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+---
+ Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
+index 735c7f06c24e..439d5c59daa2 100644
+--- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
++++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml
+@@ -17,6 +17,7 @@ properties:
+     oneOf:
+       - items:
+           - enum:
++              - allwinner,sun50i-h616-mali
+               - amlogic,meson-g12a-mali
+               - mediatek,mt8183-mali
+               - mediatek,mt8183b-mali
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.drm/dt-bindings-power-Add-Allwinner-H6-H616-PRCM-PPU.patch b/patch/kernel/archive/sunxi-6.14/patches.drm/dt-bindings-power-Add-Allwinner-H6-H616-PRCM-PPU.patch
new file mode 100644
index 000000000000..87ec283f9e11
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.drm/dt-bindings-power-Add-Allwinner-H6-H616-PRCM-PPU.patch
@@ -0,0 +1,67 @@
+From af0be61ac5ff0f86567ddbf3924c46eaa211e07f Mon Sep 17 00:00:00 2001
+From: Andre Przywara <andre.przywara@arm.com>
+Date: Fri, 21 Feb 2025 00:57:58 +0000
+Subject: dt-bindings: power: Add Allwinner H6/H616 PRCM PPU
+
+The Allwinner H6 and some later SoCs contain some bits in the PRCM (Power
+Reset Clock Management) block that control some power domains.
+Those power domains include the one for the GPU, the PLLs and some
+analogue circuits.
+
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+---
+ .../power/allwinner,sun50i-h6-prcm-ppu.yaml   | 42 +++++++++++++++++++
+ 1 file changed, 42 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/power/allwinner,sun50i-h6-prcm-ppu.yaml
+
+diff --git a/Documentation/devicetree/bindings/power/allwinner,sun50i-h6-prcm-ppu.yaml b/Documentation/devicetree/bindings/power/allwinner,sun50i-h6-prcm-ppu.yaml
+new file mode 100644
+index 000000000000..7eaff9baf726
+--- /dev/null
++++ b/Documentation/devicetree/bindings/power/allwinner,sun50i-h6-prcm-ppu.yaml
+@@ -0,0 +1,42 @@
++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/power/allwinner,sun50i-h6-prcm-ppu.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Allwinner SoCs PRCM power domain controller
++
++maintainers:
++  - Andre Przywara <andre.przywara@arm.com>
++
++description:
++  The Allwinner Power Reset Clock Management (PRCM) unit contains bits to
++  control a few power domains.
++
++properties:
++  compatible:
++    enum:
++      - allwinner,sun50i-h6-prcm-ppu
++      - allwinner,sun50i-h616-prcm-ppu
++      - allwinner,sun55i-a523-prcm-ppu
++
++  reg:
++    maxItems: 1
++
++  '#power-domain-cells':
++    const: 1
++
++required:
++  - compatible
++  - reg
++  - '#power-domain-cells'
++
++additionalProperties: false
++
++examples:
++  - |
++    prcm_ppu: power-controller@7010210 {
++        compatible = "allwinner,sun50i-h616-prcm-ppu";
++        reg = <0x07010250 0x10>;
++        #power-domain-cells = <1>;
++    };
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.drm/pmdomain-sunxi-add-H6-PRCM-PPU-driver.patch b/patch/kernel/archive/sunxi-6.14/patches.drm/pmdomain-sunxi-add-H6-PRCM-PPU-driver.patch
new file mode 100644
index 000000000000..2e7eccbb339a
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.drm/pmdomain-sunxi-add-H6-PRCM-PPU-driver.patch
@@ -0,0 +1,249 @@
+From 9fb1314045a676823428efa503b581c2910169d7 Mon Sep 17 00:00:00 2001
+From: Andre Przywara <andre.przywara@arm.com>
+Date: Fri, 21 Feb 2025 00:57:59 +0000
+Subject: pmdomain: sunxi: add H6 PRCM PPU driver
+
+The Allwinner Power Reset Clock Management (RPCM) block contains a few
+bits that control some power domains. The most prominent one is the one
+for the Mali GPU. On the Allwinner H6 this domain is enabled at reset, so
+we didn't care about it so far, but the H616 defaults to it being disabled.
+
+Add a power domain driver for those bits. Some BSP code snippets and
+some spare documentation describe three bits, slightly different between
+the H6 and H616, so add three power domains for each SoC, connected to
+their compatible string.
+
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+---
+ drivers/pmdomain/sunxi/Kconfig              |  10 +
+ drivers/pmdomain/sunxi/Makefile             |   1 +
+ drivers/pmdomain/sunxi/sun50i-h6-prcm-ppu.c | 191 ++++++++++++++++++++
+ 3 files changed, 202 insertions(+)
+ create mode 100644 drivers/pmdomain/sunxi/sun50i-h6-prcm-ppu.c
+
+diff --git a/drivers/pmdomain/sunxi/Kconfig b/drivers/pmdomain/sunxi/Kconfig
+index 17781bf8d86d..43eecb3ea981 100644
+--- a/drivers/pmdomain/sunxi/Kconfig
++++ b/drivers/pmdomain/sunxi/Kconfig
+@@ -8,3 +8,13 @@ config SUN20I_PPU
+ 	help
+ 	  Say y to enable the PPU power domain driver. This saves power
+ 	  when certain peripherals, such as the video engine, are idle.
++
++config SUN50I_H6_PRCM_PPU
++	tristate "Allwinner H6 PRCM power domain driver"
++	depends on ARCH_SUNXI || COMPILE_TEST
++	depends on PM
++	select PM_GENERIC_DOMAINS
++	help
++	  Say y to enable the Allwinner H6/H616 PRCM power domain driver.
++	  This is required to enable the Mali GPU in the H616 SoC, it is
++	  optional for the H6.
+diff --git a/drivers/pmdomain/sunxi/Makefile b/drivers/pmdomain/sunxi/Makefile
+index ec1d7a2fb21d..c1343e123759 100644
+--- a/drivers/pmdomain/sunxi/Makefile
++++ b/drivers/pmdomain/sunxi/Makefile
+@@ -1,2 +1,3 @@
+ # SPDX-License-Identifier: GPL-2.0-only
+ obj-$(CONFIG_SUN20I_PPU)		+= sun20i-ppu.o
++obj-$(CONFIG_SUN50I_H6_PRCM_PPU)	+= sun50i-h6-prcm-ppu.o
+diff --git a/drivers/pmdomain/sunxi/sun50i-h6-prcm-ppu.c b/drivers/pmdomain/sunxi/sun50i-h6-prcm-ppu.c
+new file mode 100644
+index 000000000000..1c6b0c78b222
+--- /dev/null
++++ b/drivers/pmdomain/sunxi/sun50i-h6-prcm-ppu.c
+@@ -0,0 +1,191 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * Copyright (C) Arm Ltd. 2024
++ *
++ * Allwinner H6/H616 PRCM power domain driver.
++ * This covers a few registers inside the PRCM (Power Reset Clock Management)
++ * block that control some power rails, most prominently for the Mali GPU.
++ */
++
++#include <linux/bitfield.h>
++#include <linux/clk.h>
++#include <linux/io.h>
++#include <linux/iopoll.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++#include <linux/pm_domain.h>
++#include <linux/reset.h>
++
++/*
++ * The PRCM block covers multiple devices, starting with some clocks,
++ * then followed by the power rails.
++ * The clocks are covered by a different driver, so this driver's MMIO range
++ * starts later in the PRCM MMIO frame, not at the beginning of it.
++ * To keep the register offsets consistent with other PRCM documentation,
++ * express the registers relative to the beginning of the whole PRCM, and
++ * subtract the PPU offset this driver is bound to.
++ */
++#define PD_H6_PPU_OFFSET		0x250
++#define PD_H6_VDD_SYS_REG		0x250
++#define PD_H616_ANA_VDD_GATE			BIT(4)
++#define PD_H6_CPUS_VDD_GATE			BIT(3)
++#define PD_H6_AVCC_VDD_GATE			BIT(2)
++#define PD_H6_GPU_REG			0x254
++#define PD_H6_GPU_GATE				BIT(0)
++
++struct sun50i_h6_ppu_pd {
++	struct generic_pm_domain	genpd;
++	void __iomem			*reg;
++	u32				gate_mask;
++	bool				negated;
++};
++
++#define FLAG_PPU_ALWAYS_ON	BIT(0)
++#define FLAG_PPU_NEGATED	BIT(1)
++
++struct sun50i_h6_ppu_desc {
++	const char *name;
++	u32 offset;
++	u32 mask;
++	unsigned int flags;
++};
++
++struct sun50i_h6_ppu_desc sun50i_h6_ppus[] = {
++	{ "AVCC", PD_H6_VDD_SYS_REG, PD_H6_AVCC_VDD_GATE },
++	{ "CPUS", PD_H6_VDD_SYS_REG, PD_H6_CPUS_VDD_GATE },
++	{ "GPU", PD_H6_GPU_REG, PD_H6_GPU_GATE },
++	{}
++};
++
++struct sun50i_h6_ppu_desc sun50i_h616_ppus[] = {
++	{ "PLL", PD_H6_VDD_SYS_REG, PD_H6_AVCC_VDD_GATE,
++		FLAG_PPU_ALWAYS_ON | FLAG_PPU_NEGATED },
++	{ "ANA", PD_H6_VDD_SYS_REG, PD_H616_ANA_VDD_GATE, FLAG_PPU_ALWAYS_ON },
++	{ "GPU", PD_H6_GPU_REG, PD_H6_GPU_GATE, FLAG_PPU_NEGATED },
++	{}
++};
++#define to_sun50i_h6_ppu_pd(_genpd) \
++	container_of(_genpd, struct sun50i_h6_ppu_pd, genpd)
++
++static bool sun50i_h6_ppu_power_status(const struct sun50i_h6_ppu_pd *pd)
++{
++	bool bit = readl(pd->reg) & pd->gate_mask;
++
++	return bit ^ pd->negated;
++}
++
++static int sun50i_h6_ppu_pd_set_power(const struct sun50i_h6_ppu_pd *pd,
++				      bool set_bit)
++{
++	u32 reg = readl(pd->reg);
++
++	if (set_bit)
++		writel(reg | pd->gate_mask, pd->reg);
++	else
++		writel(reg & ~pd->gate_mask, pd->reg);
++
++	return 0;
++}
++
++static int sun50i_h6_ppu_pd_power_on(struct generic_pm_domain *genpd)
++{
++	const struct sun50i_h6_ppu_pd *pd = to_sun50i_h6_ppu_pd(genpd);
++
++	return sun50i_h6_ppu_pd_set_power(pd, !pd->negated);
++}
++
++static int sun50i_h6_ppu_pd_power_off(struct generic_pm_domain *genpd)
++{
++	const struct sun50i_h6_ppu_pd *pd = to_sun50i_h6_ppu_pd(genpd);
++
++	return sun50i_h6_ppu_pd_set_power(pd, pd->negated);
++}
++
++static int sun50i_h6_ppu_probe(struct platform_device *pdev)
++{
++	struct device *dev = &pdev->dev;
++	struct genpd_onecell_data *ppu;
++	struct sun50i_h6_ppu_pd *pds;
++	const struct sun50i_h6_ppu_desc *desc;
++	void __iomem *base;
++	int ret, i, count;
++
++	desc = of_device_get_match_data(dev);
++	if (!desc)
++		return -EINVAL;
++
++	for (count = 0; desc[count].name; count++)
++		;
++
++	pds = devm_kcalloc(dev, count, sizeof(*pds), GFP_KERNEL);
++	if (!pds)
++		return -ENOMEM;
++
++	ppu = devm_kzalloc(dev, sizeof(*ppu), GFP_KERNEL);
++	if (!ppu)
++		return -ENOMEM;
++
++	ppu->num_domains = count;
++	ppu->domains = devm_kcalloc(dev, count, sizeof(*ppu->domains),
++				    GFP_KERNEL);
++	if (!ppu->domains)
++		return -ENOMEM;
++
++	platform_set_drvdata(pdev, ppu);
++
++	base = devm_platform_ioremap_resource(pdev, 0);
++	if (IS_ERR(base))
++		return PTR_ERR(base);
++
++	for (i = 0; i < count; i++) {
++		struct sun50i_h6_ppu_pd *pd = &pds[i];
++
++		pd->genpd.name		= desc[i].name;
++		pd->genpd.power_off	= sun50i_h6_ppu_pd_power_off;
++		pd->genpd.power_on	= sun50i_h6_ppu_pd_power_on;
++		if (desc[i].flags & FLAG_PPU_ALWAYS_ON)
++			pd->genpd.flags = GENPD_FLAG_ALWAYS_ON;
++		pd->negated		= !!(desc[i].flags & FLAG_PPU_NEGATED);
++		pd->reg			= base + desc[i].offset - PD_H6_PPU_OFFSET;
++		pd->gate_mask		= desc[i].mask;
++
++		ret = pm_genpd_init(&pd->genpd, NULL,
++				    !sun50i_h6_ppu_power_status(pd));
++		if (ret) {
++			dev_warn(dev, "Failed to add GPU power domain: %d\n", ret);
++			return ret;
++		}
++		ppu->domains[i] = &pd->genpd;
++	}
++
++	ret = of_genpd_add_provider_onecell(dev->of_node, ppu);
++	if (ret)
++		dev_warn(dev, "Failed to add provider: %d\n", ret);
++
++	return 0;
++}
++
++static const struct of_device_id sun50i_h6_ppu_of_match[] = {
++	{ .compatible	= "allwinner,sun50i-h6-prcm-ppu",
++	  .data		= &sun50i_h6_ppus },
++	{ .compatible	= "allwinner,sun50i-h616-prcm-ppu",
++	  .data		= &sun50i_h616_ppus },
++	{ }
++};
++MODULE_DEVICE_TABLE(of, sun50i_h6_ppu_of_match);
++
++static struct platform_driver sun50i_h6_ppu_driver = {
++	.probe	= sun50i_h6_ppu_probe,
++	.driver	= {
++		.name			= "sun50i-h6-prcm-ppu",
++		.of_match_table		= sun50i_h6_ppu_of_match,
++		/* Power domains cannot be removed while they are in use. */
++		.suppress_bind_attrs	= true,
++	},
++};
++module_platform_driver(sun50i_h6_ppu_driver);
++
++MODULE_AUTHOR("Andre Przywara <andre.przywara@arm.com>");
++MODULE_DESCRIPTION("Allwinner H6 PRCM power domain driver");
++MODULE_LICENSE("GPL");
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/clk-sunxi-ng-sun50i-a64-Switch-parent-of-MIPI-DSI-to-periph0-1x.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/clk-sunxi-ng-sun50i-a64-Switch-parent-of-MIPI-DSI-to-periph0-1x.patch
index b7876a623520..b12fb911ef18 100644
--- a/patch/kernel/archive/sunxi-6.14/patches.megous/clk-sunxi-ng-sun50i-a64-Switch-parent-of-MIPI-DSI-to-periph0-1x.patch
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/clk-sunxi-ng-sun50i-a64-Switch-parent-of-MIPI-DSI-to-periph0-1x.patch
@@ -13,7 +13,7 @@ Signed-off-by: Ondrej Jirman <megi@xff.cz>
  1 file changed, 10 insertions(+), 1 deletion(-)
 
 diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
-index c8cdb342b1a0..e76a1c10f390 100644
+index 4b3068bdfdf2..e76a1c10f390 100644
 --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
 +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
 @@ -962,6 +962,8 @@ static struct ccu_mux_nb sun50i_a64_cpu_nb = {
@@ -25,24 +25,24 @@ index c8cdb342b1a0..e76a1c10f390 100644
  static int sun50i_a64_ccu_probe(struct platform_device *pdev)
  {
  	void __iomem *reg;
-@@ -981,9 +983,16 @@ static int sun50i_a64_ccu_probe(struct platform_device *pdev)
+@@ -980,7 +982,16 @@ static int sun50i_a64_ccu_probe(struct platform_device *pdev)
+ 	/* Decrease the PLL AUDIO bias current to reduce noise. */
  	writel(0x10040000, reg + SUN50I_A64_PLL_AUDIO_BIAS_REG);
  
- 	ret = of_property_read_u32_index(of_chosen, "p-boot,framebuffer-start", 0, &val);
--	if (ret)
+-	writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);
++	ret = of_property_read_u32_index(of_chosen, "p-boot,framebuffer-start", 0, &val);
 +	if (ret) {
- 		writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);
- 
++		writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);
++
 +		/* Set MIPI-DSI clock parent to periph0(1x), so that video0(1x) is free to change. */
 +		val = readl(reg + CCU_MIPI_DSI_CLK);
 +		val &= 0x30f;
 +		val |= (2 << 8) | ((4 - 1) << 0); /* M-1 */
 +		writel(val, reg + CCU_MIPI_DSI_CLK);
 +	}
-+
+ 
  	ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun50i_a64_ccu_desc);
  	if (ret)
- 		return ret;
 -- 
 2.35.3
 
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/video-pwm_bl-Allow-to-change-lth_brightness-via-sysfs.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/video-pwm_bl-Allow-to-change-lth_brightness-via-sysfs.patch
index c49c442432bf..8923f26425a9 100644
--- a/patch/kernel/archive/sunxi-6.14/patches.megous/video-pwm_bl-Allow-to-change-lth_brightness-via-sysfs.patch
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/video-pwm_bl-Allow-to-change-lth_brightness-via-sysfs.patch
@@ -25,7 +25,7 @@ Signed-off-by: Ondrej Jirman <megi@xff.cz>
  1 file changed, 70 insertions(+), 2 deletions(-)
 
 diff --git a/drivers/video/backlight/pwm_bl.c b/drivers/video/backlight/pwm_bl.c
-index f7d9d8813d92..8a7a158dc1f6 100644
+index 237d3d3f3bb1..9f96bdd82a87 100644
 --- a/drivers/video/backlight/pwm_bl.c
 +++ b/drivers/video/backlight/pwm_bl.c
 @@ -437,6 +437,61 @@ static int pwm_backlight_initial_power_state(const struct pwm_bl_data *pb)
@@ -90,15 +90,29 @@ index f7d9d8813d92..8a7a158dc1f6 100644
  static int pwm_backlight_probe(struct platform_device *pdev)
  {
  	struct platform_pwm_backlight_data *data = dev_get_platdata(&pdev->dev);
-@@ -445,6 +500,7 @@ static int pwm_backlight_probe(struct platform_device *pdev)
+@@ -444,7 +499,8 @@ static int pwm_backlight_probe(struct platform_device *pdev)
+ 	struct backlight_properties props;
  	struct backlight_device *bl;
  	struct pwm_bl_data *pb;
- 	struct pwm_state state, state_real;
+-	struct pwm_state state;
++	struct pwm_state state, state_real;
 +	u32 lth_brightness;
  	unsigned int i;
  	int ret;
  
-@@ -584,8 +640,20 @@ static int pwm_backlight_probe(struct platform_device *pdev)
+@@ -509,6 +565,11 @@ static int pwm_backlight_probe(struct platform_device *pdev)
+ 	/* Sync up PWM state. */
+ 	pwm_init_state(pb->pwm, &state);
+ 
++	/* Read real state, but only if the PWM is enabled. */
++	pwm_get_state(pb->pwm, &state_real);
++	if (state_real.enabled)
++		state = state_real;
++
+ 	/*
+ 	 * The DT case will set the pwm_period_ns field to 0 and store the
+ 	 * period, parsed from the DT, in the PWM device. For the non-DT case,
+@@ -579,8 +640,20 @@ static int pwm_backlight_probe(struct platform_device *pdev)
  		pb->scale = data->max_brightness;
  	}
  
@@ -121,6 +135,31 @@ index f7d9d8813d92..8a7a158dc1f6 100644
  
  	props.type = BACKLIGHT_RAW;
  	props.max_brightness = data->max_brightness;
+@@ -601,6 +674,24 @@ static int pwm_backlight_probe(struct platform_device *pdev)
+ 
+ 	bl->props.brightness = data->dft_brightness;
+ 	bl->props.power = pwm_backlight_initial_power_state(pb);
++	if (bl->props.power == FB_BLANK_UNBLANK && pb->levels) {
++		u64 level;
++
++		/* If the backlight is already on, determine the default
++		 * brightness from PWM duty cycle instead of forcing
++		 * the brightness determined by the driver
++		 */
++		pwm_get_state(pb->pwm, &state);
++		level = (u64)state.duty_cycle * pb->scale;
++		do_div(level, (u64)state.period);
++
++		for (i = 0; i <= data->max_brightness; i++) {
++			if (data->levels[i] > level) {
++				bl->props.brightness = i;
++				break;
++			}
++		}
++	}
+ 	backlight_update_status(bl);
+ 
+ 	platform_set_drvdata(pdev, bl);
 -- 
 2.35.3
 
diff --git a/patch/kernel/archive/sunxi-6.14/series.conf b/patch/kernel/archive/sunxi-6.14/series.conf
index 9b2f89584aa6..d21952e30b38 100644
--- a/patch/kernel/archive/sunxi-6.14/series.conf
+++ b/patch/kernel/archive/sunxi-6.14/series.conf
@@ -180,10 +180,10 @@
 	patches.megous/arm64-dts-rk3399-Add-dmc_opp_table.patch
 	patches.megous/arm64-dts-rockchip-rk3399-s-Add-DMC-table.patch
 	patches.megous/bluetooth-h5-Don-t-re-initialize-rtl8723cs-on-resume.patch
-	patches.megous/drm-sun4i-Mark-one-of-the-UI-planes-as-a-cursor-one.patch
-	patches.megous/drm-sun4i-Implement-gamma-correction.patch
+-	patches.megous/drm-sun4i-Mark-one-of-the-UI-planes-as-a-cursor-one.patch
+-	patches.megous/drm-sun4i-Implement-gamma-correction.patch
 	patches.megous/drm-panel-st7703-Fix-xbd599-timings-to-make-refresh-rate-exactl.patch
-	patches.megous/drm-sun4i-Support-taking-over-display-pipeline-state-from-p-boo.patch
+-	patches.megous/drm-sun4i-Support-taking-over-display-pipeline-state-from-p-boo.patch
 	patches.megous/video-pwm_bl-Allow-to-change-lth_brightness-via-sysfs.patch
 	patches.megous/clk-sunxi-ng-sun50i-a64-Switch-parent-of-MIPI-DSI-to-periph0-1x.patch
 	patches.megous/drm-sun4i-tcon-Support-keeping-dclk-rate-upon-ancestor-clock-ch.patch
@@ -245,5 +245,46 @@
 	patches.megous/Add-support-for-my-private-Sapomat-device.patch
 	patches.megous/ARM-dts-sun8i-h3-orange-pi-one-Enable-all-gpio-header-UARTs.patch
 	patches.megous/mtd-spi-nor-Add-Alliance-memory-support.patch
-	patches.megous/Add-README.md-with-information-and-u-boot-patches.patch
+-	patches.megous/Add-README.md-with-information-and-u-boot-patches.patch
 	patches.megous/Defconfigs-for-all-my-devices.patch
+
+################################################################################
+#
+#                  drivers/gpu/drm/sun4i/
+#
+################################################################################
+	patches.drm/drm-sun4i-de2-de3-Change-CSC-argument.patch
+	patches.drm/drm-sun4i-de2-de3-Merge-CSC-functions-into-one.patch
+	patches.drm/drm-sun4i-de2-de3-call-csc-setup-also-for-UI-layer.patch
+	patches.drm/drm-sun4i-de2-Initialize-layer-fields-earlier.patch
+	patches.drm/drm-sun4i-de3-Add-YUV-formatter-module.patch
+	patches.drm/drm-sun4i-de3-add-format-enumeration-function-to-engine.patch
+	patches.drm/drm-sun4i-de3-add-formatter-flag-to-mixer-config.patch
+	patches.drm/drm-sun4i-de3-add-YUV-support-to-the-DE3-mixer.patch
+	patches.drm/drm-sun4i-de3-pass-engine-reference-to-ccsc-setup-function.patch
+	patches.drm/drm-sun4i-de3-add-YUV-support-to-the-color-space-correction-mod.patch
+	patches.drm/drm-sun4i-de3-add-YUV-support-to-the-TCON.patch
+	patches.drm/drm-sun4i-support-YUV-formats-in-VI-scaler.patch
+	patches.drm/drm-sun4i-de2-de3-add-mixer-version-enum.patch
+	patches.drm/drm-sun4i-de2-de3-refactor-mixer-initialisation.patch
+	patches.drm/drm-sun4i-vi_scaler-refactor-vi_scaler-enablement.patch
+	patches.drm/drm-sun4i-de2-de3-add-generic-blender-register-reference-functi.patch
+	patches.drm/drm-sun4i-de2-de3-use-generic-register-reference-function-for-l.patch
+	patches.drm/drm-sun4i-de3-Implement-AFBC-support.patch
+	patches.drm/dt-bindings-allwinner-add-H616-DE33-bus-binding.patch
+	patches.drm/dt-bindings-allwinner-add-H616-DE33-clock-binding.patch
+	patches.drm/dt-bindings-allwinner-add-H616-DE33-mixer-binding.patch
+	patches.drm/clk-sunxi-ng-ccu-add-Display-Engine-3.3-DE33-support.patch
+	patches.drm/drm-sun4i-de33-mixer-add-Display-Engine-3.3-DE33-support.patch
+	patches.drm/drm-sun4i-de33-vi_scaler-add-Display-Engine-3.3-DE33-support.patch
+	patches.drm/drm-sun4i-de33-fmt-add-Display-Engine-3.3-DE33-support.patch
+	patches.drm/drm-sun4i-de33-csc-add-Display-Engine-3.3-DE33-support.patch
+	patches.drm/drm-sun4i-add-sun50i-h616-hdmi-phy-support.patch
+	patches.drm/add-TCON-global-control-reg-for-pad-selection.patch
+	patches.drm/dt-bindings-power-Add-Allwinner-H6-H616-PRCM-PPU.patch
+	patches.drm/pmdomain-sunxi-add-H6-PRCM-PPU-driver.patch
+	patches.drm/dt-bindings-gpu-mali-bifrost-Add-Allwinner-H616-compatible.patch
+	patches.drm/arm64-dts-allwinner-h616-Add-Mali-GPU-node.patch
+	patches.drm/drm-panfrost-Add-PM-runtime-flags.patch
+	patches.drm/drm-panfrost-add-h616-compatible-string.patch
+	patches.drm/drm-panfrost-reorder-pd-clk-rst-sequence.patch
diff --git a/patch/kernel/archive/sunxi-6.14/series.drm b/patch/kernel/archive/sunxi-6.14/series.drm
new file mode 100644
index 000000000000..f6693debad04
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/series.drm
@@ -0,0 +1,40 @@
+################################################################################
+#
+#                  drivers/gpu/drm/sun4i/
+#
+################################################################################
+	patches.drm/drm-sun4i-de2-de3-Change-CSC-argument.patch
+	patches.drm/drm-sun4i-de2-de3-Merge-CSC-functions-into-one.patch
+	patches.drm/drm-sun4i-de2-de3-call-csc-setup-also-for-UI-layer.patch
+	patches.drm/drm-sun4i-de2-Initialize-layer-fields-earlier.patch
+	patches.drm/drm-sun4i-de3-Add-YUV-formatter-module.patch
+	patches.drm/drm-sun4i-de3-add-format-enumeration-function-to-engine.patch
+	patches.drm/drm-sun4i-de3-add-formatter-flag-to-mixer-config.patch
+	patches.drm/drm-sun4i-de3-add-YUV-support-to-the-DE3-mixer.patch
+	patches.drm/drm-sun4i-de3-pass-engine-reference-to-ccsc-setup-function.patch
+	patches.drm/drm-sun4i-de3-add-YUV-support-to-the-color-space-correction-mod.patch
+	patches.drm/drm-sun4i-de3-add-YUV-support-to-the-TCON.patch
+	patches.drm/drm-sun4i-support-YUV-formats-in-VI-scaler.patch
+	patches.drm/drm-sun4i-de2-de3-add-mixer-version-enum.patch
+	patches.drm/drm-sun4i-de2-de3-refactor-mixer-initialisation.patch
+	patches.drm/drm-sun4i-vi_scaler-refactor-vi_scaler-enablement.patch
+	patches.drm/drm-sun4i-de2-de3-add-generic-blender-register-reference-functi.patch
+	patches.drm/drm-sun4i-de2-de3-use-generic-register-reference-function-for-l.patch
+	patches.drm/drm-sun4i-de3-Implement-AFBC-support.patch
+	patches.drm/dt-bindings-allwinner-add-H616-DE33-bus-binding.patch
+	patches.drm/dt-bindings-allwinner-add-H616-DE33-clock-binding.patch
+	patches.drm/dt-bindings-allwinner-add-H616-DE33-mixer-binding.patch
+	patches.drm/clk-sunxi-ng-ccu-add-Display-Engine-3.3-DE33-support.patch
+	patches.drm/drm-sun4i-de33-mixer-add-Display-Engine-3.3-DE33-support.patch
+	patches.drm/drm-sun4i-de33-vi_scaler-add-Display-Engine-3.3-DE33-support.patch
+	patches.drm/drm-sun4i-de33-fmt-add-Display-Engine-3.3-DE33-support.patch
+	patches.drm/drm-sun4i-de33-csc-add-Display-Engine-3.3-DE33-support.patch
+	patches.drm/drm-sun4i-add-sun50i-h616-hdmi-phy-support.patch
+	patches.drm/add-TCON-global-control-reg-for-pad-selection.patch
+	patches.drm/dt-bindings-power-Add-Allwinner-H6-H616-PRCM-PPU.patch
+	patches.drm/pmdomain-sunxi-add-H6-PRCM-PPU-driver.patch
+	patches.drm/dt-bindings-gpu-mali-bifrost-Add-Allwinner-H616-compatible.patch
+	patches.drm/arm64-dts-allwinner-h616-Add-Mali-GPU-node.patch
+	patches.drm/drm-panfrost-Add-PM-runtime-flags.patch
+	patches.drm/drm-panfrost-add-h616-compatible-string.patch
+	patches.drm/drm-panfrost-reorder-pd-clk-rst-sequence.patch

From 76eb5bb9e7fdf6e58ef556b1fc9a5ab96a439678 Mon Sep 17 00:00:00 2001
From: The-going <48602507+The-going@users.noreply.github.com>
Date: Wed, 30 Apr 2025 12:53:25 +0300
Subject: [PATCH 3/7] sunxi-6.14: Add media patches

---
 ...ma-sun6i-dma-add-sun50i-h616-support.patch |  53 ++++++
 ...V12-and-P010-AFBC-compressed-formats.patch |  45 +++++
 ...-cedrus-Don-t-CPU-map-source-buffers.patch |  29 +++
 ...plement-AFBC-YUV420-formats-for-H265.patch | 169 ++++++++++++++++++
 .../media-cedrus-Increase-H6-clock-rate.patch |  29 +++
 ...tering-based-on-depth-and-src-format.patch |  50 ++++++
 patch/kernel/archive/sunxi-6.14/series.conf   |  12 ++
 patch/kernel/archive/sunxi-6.14/series.media  |  11 ++
 8 files changed, 398 insertions(+)
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.media/dma-sun6i-dma-add-sun50i-h616-support.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.media/media-Add-NV12-and-P010-AFBC-compressed-formats.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.media/media-cedrus-Don-t-CPU-map-source-buffers.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.media/media-cedrus-Implement-AFBC-YUV420-formats-for-H265.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.media/media-cedrus-Increase-H6-clock-rate.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.media/media-cedrus-add-format-filtering-based-on-depth-and-src-format.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/series.media

diff --git a/patch/kernel/archive/sunxi-6.14/patches.media/dma-sun6i-dma-add-sun50i-h616-support.patch b/patch/kernel/archive/sunxi-6.14/patches.media/dma-sun6i-dma-add-sun50i-h616-support.patch
new file mode 100644
index 000000000000..ffedd6b0c354
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.media/dma-sun6i-dma-add-sun50i-h616-support.patch
@@ -0,0 +1,53 @@
+From f4671b6d4842701e71b6a1ba6a93fbfb9dabb188 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Mon, 7 Apr 2025 21:32:25 +0300
+Subject: dma: sun6i-dma: add sun50i-h616 support
+
+---
+ drivers/dma/sun6i-dma.c | 23 +++++++++++++++++++++++
+ 1 file changed, 23 insertions(+)
+
+diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c
+index 95ecb12caaa5..ae2b5509b5b4 100644
+--- a/drivers/dma/sun6i-dma.c
++++ b/drivers/dma/sun6i-dma.c
+@@ -1243,6 +1243,28 @@ static struct sun6i_dma_config sun50i_h6_dma_cfg = {
+ 	.has_mbus_clk = true,
+ };
+ 
++/*
++ * The H616 binding uses the number of dma channels from the
++ * device tree node.
++ */
++static struct sun6i_dma_config sun50i_h616_dma_cfg = {
++        .clock_autogate_enable = sun6i_enable_clock_autogate_h3,
++        .set_burst_length = sun6i_set_burst_length_h3,
++        .set_drq          = sun6i_set_drq_h6,
++        .set_mode         = sun6i_set_mode_h6,
++        .src_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
++        .dst_burst_lengths = BIT(1) | BIT(4) | BIT(8) | BIT(16),
++        .src_addr_widths   = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
++                             BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
++                             BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
++                             BIT(DMA_SLAVE_BUSWIDTH_8_BYTES),
++        .dst_addr_widths   = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |
++                             BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) |
++                             BIT(DMA_SLAVE_BUSWIDTH_4_BYTES) |
++                             BIT(DMA_SLAVE_BUSWIDTH_8_BYTES),
++        .has_mbus_clk = true,
++};
++
+ /*
+  * The V3s have only 8 physical channels, a maximum DRQ port id of 23,
+  * and a total of 24 usable source and destination endpoints.
+@@ -1276,6 +1298,7 @@ static const struct of_device_id sun6i_dma_match[] = {
+ 	{ .compatible = "allwinner,sun50i-a64-dma", .data = &sun50i_a64_dma_cfg },
+ 	{ .compatible = "allwinner,sun50i-a100-dma", .data = &sun50i_a100_dma_cfg },
+ 	{ .compatible = "allwinner,sun50i-h6-dma", .data = &sun50i_h6_dma_cfg },
++	{ .compatible = "allwinner,sun50i-h616-dma", .data = &sun50i_h616_dma_cfg },
+ 	{ /* sentinel */ }
+ };
+ MODULE_DEVICE_TABLE(of, sun6i_dma_match);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.media/media-Add-NV12-and-P010-AFBC-compressed-formats.patch b/patch/kernel/archive/sunxi-6.14/patches.media/media-Add-NV12-and-P010-AFBC-compressed-formats.patch
new file mode 100644
index 000000000000..113377c08405
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.media/media-Add-NV12-and-P010-AFBC-compressed-formats.patch
@@ -0,0 +1,45 @@
+From eae101ec576943cc34c4718b360bbe6091792e8b Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sat, 7 Oct 2023 09:43:35 +0200
+Subject: media: Add NV12 and P010 AFBC compressed formats
+
+Cedrus supports AFBC compressed NV12 and P010 formats, which
+considerably speed up H265 decoding. Add them.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ drivers/media/v4l2-core/v4l2-ioctl.c | 2 ++
+ include/uapi/linux/videodev2.h       | 4 ++++
+ 2 files changed, 6 insertions(+)
+
+diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c
+index 0304daa8471d..6c7f3abb4959 100644
+--- a/drivers/media/v4l2-core/v4l2-ioctl.c
++++ b/drivers/media/v4l2-core/v4l2-ioctl.c
+@@ -1546,6 +1546,8 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt)
+ 		case V4L2_PIX_FMT_PISP_COMP2_GBRG: descr = "PiSP 8b GBGB/RGRG mode2 compr"; break;
+ 		case V4L2_PIX_FMT_PISP_COMP2_BGGR: descr = "PiSP 8b BGBG/GRGR mode2 compr"; break;
+ 		case V4L2_PIX_FMT_PISP_COMP2_MONO: descr = "PiSP 8b monochrome mode2 compr"; break;
++		case V4L2_PIX_FMT_YUV420_8_AFBC_16X16_SPLIT:  descr = "YUV 4:2:0 (AFBC 16x16)"; break;
++		case V4L2_PIX_FMT_YUV420_10_AFBC_16X16_SPLIT: descr = "10-bit YUV 4:2:0 (AFBC 16x16)"; break;
+ 		default:
+ 			if (fmt->description[0])
+ 				return;
+diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h
+index e7c4dce39007..8d423df66f61 100644
+--- a/include/uapi/linux/videodev2.h
++++ b/include/uapi/linux/videodev2.h
+@@ -688,6 +688,10 @@ struct v4l2_pix_format {
+ #define V4L2_PIX_FMT_NV12M_8L128      v4l2_fourcc('N', 'A', '1', '2') /* Y/CbCr 4:2:0 8x128 tiles */
+ #define V4L2_PIX_FMT_NV12M_10BE_8L128 v4l2_fourcc_be('N', 'T', '1', '2') /* Y/CbCr 4:2:0 10-bit 8x128 tiles */
+ 
++/* AFBC YUV formats */
++#define V4L2_PIX_FMT_YUV420_8_AFBC_16X16_SPLIT v4l2_fourcc('A', 'S', '1', '2') /* YUV420 AFBC compressed, 16x16 macroblocks, split */
++#define V4L2_PIX_FMT_YUV420_10_AFBC_16X16_SPLIT v4l2_fourcc('A', 'S', '0', '1') /* YUV420 10-bit AFBC compressed, 16x16 macroblocks, split */
++
+ /* Bayer formats - see http://www.siliconimaging.com/RGB%20Bayer.htm */
+ #define V4L2_PIX_FMT_SBGGR8  v4l2_fourcc('B', 'A', '8', '1') /*  8  BGBG.. GRGR.. */
+ #define V4L2_PIX_FMT_SGBRG8  v4l2_fourcc('G', 'B', 'R', 'G') /*  8  GBGB.. RGRG.. */
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.media/media-cedrus-Don-t-CPU-map-source-buffers.patch b/patch/kernel/archive/sunxi-6.14/patches.media/media-cedrus-Don-t-CPU-map-source-buffers.patch
new file mode 100644
index 000000000000..15649d82c556
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.media/media-cedrus-Don-t-CPU-map-source-buffers.patch
@@ -0,0 +1,29 @@
+From 80b16fcddf1837c631796c25f3123b7adbbf815a Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Tue, 4 Oct 2022 20:36:18 +0200
+Subject: media: cedrus: Don't CPU map source buffers
+
+There is no need to access source buffers via CPU, so let's disable
+that. This will lower amount of virtual memory needed on 32-bit ARM
+SoCs.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ drivers/staging/media/sunxi/cedrus/cedrus_video.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_video.c b/drivers/staging/media/sunxi/cedrus/cedrus_video.c
+index 77f78266f406..7f5a6a2363a5 100644
+--- a/drivers/staging/media/sunxi/cedrus/cedrus_video.c
++++ b/drivers/staging/media/sunxi/cedrus/cedrus_video.c
+@@ -580,6 +580,7 @@ int cedrus_queue_init(void *priv, struct vb2_queue *src_vq,
+ 
+ 	src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
+ 	src_vq->io_modes = VB2_MMAP | VB2_DMABUF;
++	src_vq->dma_attrs = DMA_ATTR_NO_KERNEL_MAPPING;
+ 	src_vq->drv_priv = ctx;
+ 	src_vq->buf_struct_size = sizeof(struct cedrus_buffer);
+ 	src_vq->ops = &cedrus_qops;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.media/media-cedrus-Implement-AFBC-YUV420-formats-for-H265.patch b/patch/kernel/archive/sunxi-6.14/patches.media/media-cedrus-Implement-AFBC-YUV420-formats-for-H265.patch
new file mode 100644
index 000000000000..e9ca743f9e7b
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.media/media-cedrus-Implement-AFBC-YUV420-formats-for-H265.patch
@@ -0,0 +1,169 @@
+From 81241983ba12f281a839a530da460088170cca2e Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sun, 8 Oct 2023 12:44:59 +0200
+Subject: media: cedrus: Implement AFBC YUV420 formats for H265
+
+AFBC output formats are more performant, since they are optimized for
+more efficient memory operations and transfers.
+
+Add support for them.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ drivers/staging/media/sunxi/cedrus/cedrus.h   | 11 ++++++
+ .../staging/media/sunxi/cedrus/cedrus_h265.c  |  3 +-
+ .../staging/media/sunxi/cedrus/cedrus_hw.c    | 16 +++++++++
+ .../staging/media/sunxi/cedrus/cedrus_regs.h  |  6 ++++
+ .../staging/media/sunxi/cedrus/cedrus_video.c | 36 +++++++++++++++++++
+ 5 files changed, 71 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.h b/drivers/staging/media/sunxi/cedrus/cedrus.h
+index 522c184e2afc..c7ec4dee8630 100644
+--- a/drivers/staging/media/sunxi/cedrus/cedrus.h
++++ b/drivers/staging/media/sunxi/cedrus/cedrus.h
+@@ -268,6 +268,17 @@ cedrus_is_capable(struct cedrus_ctx *ctx, unsigned int capabilities)
+ 	return (ctx->dev->capabilities & capabilities) == capabilities;
+ }
+ 
++static inline bool is_afbc_format(u32 format)
++{
++	switch (format) {
++	case V4L2_PIX_FMT_YUV420_8_AFBC_16X16_SPLIT:
++	case V4L2_PIX_FMT_YUV420_10_AFBC_16X16_SPLIT:
++		return true;
++	default:
++		return false;
++	}
++}
++
+ void *cedrus_find_control_data(struct cedrus_ctx *ctx, u32 id);
+ u32 cedrus_get_num_of_controls(struct cedrus_ctx *ctx, u32 id);
+ 
+diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c
+index 780da4a8b5af..1a7b0600cc51 100644
+--- a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c
++++ b/drivers/staging/media/sunxi/cedrus/cedrus_h265.c
+@@ -120,7 +120,8 @@ static void cedrus_h265_frame_info_write_single(struct cedrus_ctx *ctx,
+ {
+ 	struct cedrus_dev *dev = ctx->dev;
+ 	dma_addr_t dst_luma_addr = cedrus_dst_buf_addr(ctx, buf, 0);
+-	dma_addr_t dst_chroma_addr = cedrus_dst_buf_addr(ctx, buf, 1);
++	dma_addr_t dst_chroma_addr = is_afbc_format(ctx->dst_fmt.pixelformat) ?
++				     0 : cedrus_dst_buf_addr(ctx, buf, 1);
+ 	dma_addr_t mv_col_buf_addr[2] = {
+ 		cedrus_h265_frame_info_mv_col_buf_addr(buf, 0),
+ 		cedrus_h265_frame_info_mv_col_buf_addr(buf, field_pic ? 1 : 0)
+diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c
+index 32af0e96e762..5d769a124439 100644
+--- a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c
++++ b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c
+@@ -65,6 +65,18 @@ int cedrus_engine_enable(struct cedrus_ctx *ctx)
+ 		reg |= VE_MODE_PIC_WIDTH_IS_4096;
+ 	if (ctx->src_fmt.width > 2048)
+ 		reg |= VE_MODE_PIC_WIDTH_MORE_2048;
++	/*
++	 * NOTE: Not sure if RGB default color feature is part of official
++	 * AFBC standard or not and if it is, which feature that is. However,
++	 * in order to render it properly with display engine, default color
++	 * has to be set to white there.
++	 */
++	if (is_afbc_format(ctx->dst_fmt.pixelformat))
++		reg |= VE_MODE_COMPRESS_EN |
++		       VE_MODE_MIN_VAL_WRAP_EN |
++		       VE_MODE_RGB_DEF_COLOR_EN |
++		       VE_MODE_BODYBUF_1K_ALIGNED |
++		       VE_MODE_COMPRESS_MODE_AFBC;
+ 
+ 	cedrus_write(ctx->dev, VE_MODE, reg);
+ 
+@@ -85,6 +97,10 @@ void cedrus_dst_format_set(struct cedrus_dev *dev,
+ 	u32 reg;
+ 
+ 	switch (fmt->pixelformat) {
++	case V4L2_PIX_FMT_YUV420_8_AFBC_16X16_SPLIT:
++	case V4L2_PIX_FMT_YUV420_10_AFBC_16X16_SPLIT:
++		/* format is already set in cedrus_engine_enable() */
++		break;
+ 	case V4L2_PIX_FMT_NV12:
+ 		chroma_size = ALIGN(width, 16) * ALIGN(height, 16) / 2;
+ 
+diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h
+index 05e6cbc548ab..c3dcd93a29eb 100644
+--- a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h
++++ b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h
+@@ -35,12 +35,18 @@
+ 
+ #define VE_MODE					0x00
+ 
++#define VE_MODE_COMPRESS_EN			BIT(29)
++#define VE_MODE_MIN_VAL_WRAP_EN			BIT(27)
++#define VE_MODE_RGB_DEF_COLOR_EN		BIT(26)
+ #define VE_MODE_PIC_WIDTH_IS_4096		BIT(22)
+ #define VE_MODE_PIC_WIDTH_MORE_2048		BIT(21)
+ #define VE_MODE_REC_WR_MODE_2MB			(0x01 << 20)
+ #define VE_MODE_REC_WR_MODE_1MB			(0x00 << 20)
+ #define VE_MODE_DDR_MODE_BW_128			(0x03 << 16)
+ #define VE_MODE_DDR_MODE_BW_256			(0x02 << 16)
++#define VE_MODE_BODYBUF_1K_ALIGNED		BIT(12)
++#define VE_MODE_COMPRESS_MODE_LOSSLESS		(0x00 << 4)
++#define VE_MODE_COMPRESS_MODE_AFBC		(0x01 << 4)
+ #define VE_MODE_DISABLED			(0x07 << 0)
+ #define VE_MODE_DEC_H265			(0x04 << 0)
+ #define VE_MODE_DEC_H264			(0x01 << 0)
+diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_video.c b/drivers/staging/media/sunxi/cedrus/cedrus_video.c
+index 53ec3066274d..99011066e7d3 100644
+--- a/drivers/staging/media/sunxi/cedrus/cedrus_video.c
++++ b/drivers/staging/media/sunxi/cedrus/cedrus_video.c
+@@ -55,6 +55,22 @@ static struct cedrus_format cedrus_formats[] = {
+ 		.directions	= CEDRUS_DECODE_SRC,
+ 		.capabilities	= CEDRUS_CAPABILITY_VP8_DEC,
+ 	},
++	{
++		.pixelformat	= V4L2_PIX_FMT_YUV420_10_AFBC_16X16_SPLIT,
++		.directions	= CEDRUS_DECODE_DST,
++		.capabilities	= CEDRUS_CAPABILITY_UNTILED |
++				  CEDRUS_CAPABILITY_H265_10_DEC,
++		.depth		= 10,
++		.src_format	= V4L2_PIX_FMT_HEVC_SLICE,
++	},
++	{
++		.pixelformat	= V4L2_PIX_FMT_YUV420_8_AFBC_16X16_SPLIT,
++		.directions	= CEDRUS_DECODE_DST,
++		.capabilities	= CEDRUS_CAPABILITY_UNTILED |
++				  CEDRUS_CAPABILITY_H265_10_DEC,
++		.depth		= 8,
++		.src_format	= V4L2_PIX_FMT_HEVC_SLICE,
++	},
+ 	{
+ 		.pixelformat	= V4L2_PIX_FMT_NV12,
+ 		.directions	= CEDRUS_DECODE_DST,
+@@ -160,6 +176,26 @@ void cedrus_prepare_format(struct v4l2_pix_format *pix_fmt)
+ 		sizeimage += bytesperline * height / 2;
+ 
+ 		break;
++
++	case V4L2_PIX_FMT_YUV420_10_AFBC_16X16_SPLIT:
++		/* Zero bytes per line for compressed destination. */
++		bytesperline = 0;
++
++		sizeimage = DIV_ROUND_UP(width, 16) *
++			    DIV_ROUND_UP(height + 4, 16) * (512 + 16) +
++			    32 + SZ_1K;
++
++		break;
++
++	case V4L2_PIX_FMT_YUV420_8_AFBC_16X16_SPLIT:
++		/* Zero bytes per line for compressed destination. */
++		bytesperline = 0;
++
++		sizeimage = DIV_ROUND_UP(width, 16) *
++			    DIV_ROUND_UP(height + 4, 16) * (384 + 16) +
++			    32 + SZ_1K;
++
++		break;
+ 	}
+ 
+ 	pix_fmt->width = width;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.media/media-cedrus-Increase-H6-clock-rate.patch b/patch/kernel/archive/sunxi-6.14/patches.media/media-cedrus-Increase-H6-clock-rate.patch
new file mode 100644
index 000000000000..1b6cdd1b8daa
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.media/media-cedrus-Increase-H6-clock-rate.patch
@@ -0,0 +1,29 @@
+From c0dffc32c3a65a1c25bf04f979faf8b6a82b88f8 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Mon, 9 Oct 2023 20:16:27 +0200
+Subject: media: cedrus: Increase H6 clock rate
+
+Vendor driver runs Cedrus at 648 MHz, supposedly to be able to decode
+4k HEVC at 60 fps.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ drivers/staging/media/sunxi/cedrus/cedrus.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.c b/drivers/staging/media/sunxi/cedrus/cedrus.c
+index b91174246e58..08f8d994c99c 100644
+--- a/drivers/staging/media/sunxi/cedrus/cedrus.c
++++ b/drivers/staging/media/sunxi/cedrus/cedrus.c
+@@ -648,7 +648,7 @@ static const struct cedrus_variant sun50i_h6_cedrus_variant = {
+ 			  CEDRUS_CAPABILITY_H265_DEC |
+ 			  CEDRUS_CAPABILITY_H265_10_DEC |
+ 			  CEDRUS_CAPABILITY_VP8_DEC,
+-	.mod_rate	= 600000000,
++	.mod_rate	= 648000000,
+ };
+ 
+ static const struct of_device_id cedrus_dt_match[] = {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.media/media-cedrus-add-format-filtering-based-on-depth-and-src-format.patch b/patch/kernel/archive/sunxi-6.14/patches.media/media-cedrus-add-format-filtering-based-on-depth-and-src-format.patch
new file mode 100644
index 000000000000..462e3d712544
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.media/media-cedrus-add-format-filtering-based-on-depth-and-src-format.patch
@@ -0,0 +1,50 @@
+From be75f442cae72a4e646e1f5d7374f579ee026c3d Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sat, 7 Oct 2023 09:45:25 +0200
+Subject: media: cedrus: add format filtering based on depth and src format
+
+Some Cedrus variant, like that found in H6, support special output
+formats only with specific codecs, like H265.
+
+Add extra filtering fields based on bit depth and source format.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ drivers/staging/media/sunxi/cedrus/cedrus_video.c | 7 +++++++
+ drivers/staging/media/sunxi/cedrus/cedrus_video.h | 2 ++
+ 2 files changed, 9 insertions(+)
+
+diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_video.c b/drivers/staging/media/sunxi/cedrus/cedrus_video.c
+index 7f5a6a2363a5..53ec3066274d 100644
+--- a/drivers/staging/media/sunxi/cedrus/cedrus_video.c
++++ b/drivers/staging/media/sunxi/cedrus/cedrus_video.c
+@@ -87,6 +87,13 @@ static struct cedrus_format *cedrus_find_format(struct cedrus_ctx *ctx,
+ 		    !(fmt->directions & directions))
+ 			continue;
+ 
++		if (fmt->depth && fmt->depth != ctx->bit_depth)
++			continue;
++
++		if (fmt->src_format &&
++		    fmt->src_format != ctx->src_fmt.pixelformat)
++			continue;
++
+ 		if (fmt->pixelformat == pixelformat)
+ 			break;
+ 
+diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_video.h b/drivers/staging/media/sunxi/cedrus/cedrus_video.h
+index 8e1afc16a6a1..c8e9909ecdee 100644
+--- a/drivers/staging/media/sunxi/cedrus/cedrus_video.h
++++ b/drivers/staging/media/sunxi/cedrus/cedrus_video.h
+@@ -20,6 +20,8 @@ struct cedrus_format {
+ 	u32		pixelformat;
+ 	u32		directions;
+ 	unsigned int	capabilities;
++	unsigned int	depth;
++	u32		src_format;
+ };
+ 
+ extern const struct v4l2_ioctl_ops cedrus_ioctl_ops;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/series.conf b/patch/kernel/archive/sunxi-6.14/series.conf
index d21952e30b38..01aee915e783 100644
--- a/patch/kernel/archive/sunxi-6.14/series.conf
+++ b/patch/kernel/archive/sunxi-6.14/series.conf
@@ -288,3 +288,15 @@
 	patches.drm/drm-panfrost-Add-PM-runtime-flags.patch
 	patches.drm/drm-panfrost-add-h616-compatible-string.patch
 	patches.drm/drm-panfrost-reorder-pd-clk-rst-sequence.patch
+
+################################################################################
+#
+#                  media patches
+#
+################################################################################
+	patches.media/media-cedrus-Don-t-CPU-map-source-buffers.patch
+	patches.media/media-Add-NV12-and-P010-AFBC-compressed-formats.patch
+	patches.media/media-cedrus-add-format-filtering-based-on-depth-and-src-format.patch
+	patches.media/media-cedrus-Implement-AFBC-YUV420-formats-for-H265.patch
+	patches.media/media-cedrus-Increase-H6-clock-rate.patch
+	patches.media/dma-sun6i-dma-add-sun50i-h616-support.patch
diff --git a/patch/kernel/archive/sunxi-6.14/series.media b/patch/kernel/archive/sunxi-6.14/series.media
new file mode 100644
index 000000000000..d93c20840b00
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/series.media
@@ -0,0 +1,11 @@
+#
+#	Automatically generated by the script mk_format_patch
+#
+#	git@github.com:The-going/linux-sf.git
+#
+	patches.media/media-cedrus-Don-t-CPU-map-source-buffers.patch
+	patches.media/media-Add-NV12-and-P010-AFBC-compressed-formats.patch
+	patches.media/media-cedrus-add-format-filtering-based-on-depth-and-src-format.patch
+	patches.media/media-cedrus-Implement-AFBC-YUV420-formats-for-H265.patch
+	patches.media/media-cedrus-Increase-H6-clock-rate.patch
+	patches.media/dma-sun6i-dma-add-sun50i-h616-support.patch

From 04c459244cc1ae82aac2ef32b94a2772e1d3a12f Mon Sep 17 00:00:00 2001
From: The-going <48602507+The-going@users.noreply.github.com>
Date: Wed, 30 Apr 2025 13:43:40 +0300
Subject: [PATCH 4/7] sunxi-6.14: Add armbian patches

---
 ...nanopiduo2-Use-key-0-as-power-button.patch |   31 +
 ...dts-sun8i-nanopiduo2-enable-ethernet.patch |   31 +
 ...0i-h616-BigTreeTech-CB1-Enable-EMAC1.patch |   42 +
 ...50i-h616-BigTreeTech-CB1-Enable-HDMI.patch |   57 +
 .../ASoC-AC200-Initial-driver.patch           |  842 +++
 .../Add-BananaPi-BPI-M4-Zero-overlays.patch   |  377 ++
 .../Add-BananaPi-BPI-M4-Zero-pinctrl.patch    |   81 +
 .../Add-FB_TFT-ST7796S-driver.patch           |  154 +
 .../Add-board-BananaPi-BPI-M4-Zero.patch      |  407 ++
 ...d-dump_reg-and-sunxi-sysinfo-drivers.patch | 1548 +++++
 ...to-fix-uwe5622-bluetooth-MAC-address.patch |  609 ++
 .../Add-wifi-nodes-for-Inovato-Quadra.patch   |   88 +
 ...ws2812-RGB-driver-for-allwinner-H616.patch |  273 +
 ...o-mode-adjustment-and-ws2812-rgb_val.patch |   58 +
 .../Compile-the-pwm-overlay.patch             |   24 +
 ...ce-number-as-referenced-in-the-Allwi.patch |   29 +
 ...ding-for-DWC3-controller-on-Allwinne.patch |   63 +
 ...Allwinner-A10-EMAC-which-already-exi.patch |   26 +
 .../Enable-creation-of-__symbols__-node.patch |   29 +
 ...-ghost-touches-on-tsc2007-tft-screen.patch |  211 +
 .../Fix-include-uapi-spi-spidev-module.patch  |   26 +
 ...p20x-pek-allow-wakeup-after-shutdown.patch |   48 +
 ...us_heartbeat-arch-arm64-boot-dts-all.patch |   39 +
 ...FIG_SHELL-fix-for-builddeb-packaging.patch |   27 +
 ...i-h6-pwm-settings-to-its-own-overlay.patch |   70 +
 ...C2007-touchscreen-add-polling-method.patch |  195 +
 ...sun4i-hdmi-switch-to-struct-drm_edid.patch |   49 +
 .../Sound-for-H616-H618-Allwinner-SOCs.patch  | 4239 ++++++++++++++
 ...-boot-dts-allwinner-sun50i-a64-pinep.patch |   53 +
 .../add-dtb-overlay-for-zero2w.patch          |  135 +
 ...dd-initial-support-for-orangepi3-lts.patch |  431 ++
 ...i-info-sunxi-addr-and-sunxi-dump-reg.patch |   73 +
 ...rm-arm64-dts-Add-leds-axp20x-charger.patch |   79 +
 ...-Add-sun8i-h2-plus-nanopi-duo-device.patch |  196 +
 ...Add-sun8i-h2-plus-sunvell-r69-device.patch |  257 +
 ...ubietruck-green-LED-mmc0-default-tri.patch |   38 +
 ...-orangepi-and-mini-fix-phy-mode-hdmi.patch |   86 +
 ...3-nanopi-neo-Add-regulator-leds-mmc2.patch |   80 +
 ...dd-regulator-camera-wifi-bluetooth-o.patch |  196 +
 ...-h3-orangepi-2-Add-regulator-vdd-cpu.patch |   59 +
 ...m-dts-overlay-Add-Overlays-for-sunxi.patch | 4964 +++++++++++++++++
 ...lay-sun8i-h3-cpu-clock-add-overclock.patch |  209 +
 ...-Add-panel-lcd-olinuxino-4.3-needed-.patch |  133 +
 ...no-micro-add-panel-lcd-olinuxino-4.3.patch |  106 +
 ...OB-IRQ-for-brcm-wifi-on-Cubietruck-a.patch |   99 +
 ...-a20-bananapro-add-AXP209-regulators.patch |   72 +
 ...-a20-bananapro-add-hdmi-connector-de.patch |   78 +
 ...sun7i-a20-cubietruck-add-alias-uart2.patch |   24 +
 ...m-204-evb-olinuxino-micro-decrease-d.patch |   55 +
 ...0-olinuxino-lime2-enable-audio-codec.patch |   27 +
 ...linuxino-lime2-enable-ldo3-always-on.patch |   28 +
 ...-olinuxino-micro-emmc-Add-vqmmc-node.patch |   24 +
 ...us-orangepi-zero-fix-usb_otg-dr_mode.patch |   25 +
 ...s-orangepi-zero-fix-xradio-interrupt.patch |   35 +
 .../arm-dts-sun8i-h3-add-thermal-zones.patch  |  104 +
 ...-h3-bananapi-m2-plus-add-wifi_pwrseq.patch |   25 +
 ...ts-sun8i-h3-nanopi-add-leds-pio-pins.patch |   60 +
 ...-h3-orangepi-pc-plus-add-wifi_pwrseq.patch |   33 +
 ...-microvolt-to-prevent-not-supported-.patch |   48 +
 ...-r40-add-clk_out_a-fix-bananam2ultra.patch |   40 +
 ...0-bananapi-m2-ultra-add-codec-analog.patch |   63 +
 ...i-v3s-s3-pinecube-enable-sound-codec.patch |   63 +
 ...arm-dts-sun9i-a80-add-thermal-sensor.patch |   41 +
 .../arm-dts-sun9i-a80-add-thermal-zone.patch  |   54 +
 ...-sunxi-h3-h5.dtsi-add-i2s0-i2s1-pins.patch |   33 +
 ...unxi-h3-h5.dtsi-force-mmc0-bus-width.patch |   24 +
 ...e-ASAP-after-writing-new-instruction.patch |   63 +
 ...un50i-h618-bananapi-m4-berry-support.patch |  353 ++
 ...-Add-sun50i-h5-nanopi-k1-plus-device.patch |  429 ++
 ...Add-sun50i-h5-nanopi-m1-plus2-device.patch |  272 +
 ...dd-sun50i-h5-nanopi-neo-core2-device.patch |  242 +
 ...dd-sun50i-h5-nanopi-neo2-v1.1-device.patch |  212 +
 ...64-olinuxino-add-regulator-audio-mmc.patch |   99 +
 ...64-dts-add-sun50i-h618-cpu-dvfs.dtsi.patch |  260 +
 ...arm64-dts-allwinner-Add-axp313a.dtsi.patch |   83 +
 ...ts-allwinner-h6-Add-AC200-EPHY-nodes.patch |  144 +
 ...s-allwinner-h6-add-AC200-codec-nodes.patch |   87 +
 ...-dts-allwinner-h6-enable-AC200-codec.patch |  142 +
 ...s-allwinner-h6-tanix-enable-Ethernet.patch |   97 +
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 ...dts-h616-8-Add-overlays-i2c-pwm-uart.patch |  369 ++
 ...add-hdmi-support-for-zero2-and-zero3.patch |  339 ++
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 ...s-sun50i-a64-pine64-enable-wifi-mmc1.patch |   52 +
 ...i-a64-sopine-baseboard-Add-i2s2-mmc1.patch |   44 +
 ...64-sopine-baseboard-enable-Bluetooth.patch |   44 +
 ...-a64.dtsi-adjust-thermal-trip-points.patch |   42 +
 .../arm64-dts-sun50i-h313-x96q-lpddr3.patch   |  441 ++
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 ...able-power-button-for-orangepi-prime.patch |   27 +
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 ...un50i-h6-pine-h64-add-wifi-rtl8723cs.patch |   82 +
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 ...ts-sun50i-h616-add-pwm-nodes-support.patch |  133 +
 ...-sun50i-h616-bigtreetech-cb1-sd-emmc.patch |  491 ++
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 ...angepi-zero2-reg_usb1_vbus-status-ok.patch |   24 +
 ...i-h616-x96-mate-T95-eth-sd-card-hack.patch |  103 +
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 ...6.dtsi-reserved-memory-512K-for-BL31.patch |   31 +
 ...18-orangepi-zero2w-Add-missing-nodes.patch |  434 ++
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 ...50i-h616-Add-i2c-2-3-4-uart-2-5-pins.patch |  107 +
 .../patches.armbian/cb1-overlay.patch         |  491 ++
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 ...gem-dma-Export-with-handle-allocator.patch |   51 +
 ...simple-Add-compability-olinuxino-lcd.patch |  169 +
 .../drv-gpu-drm-sun4i-Add-GEM-allocator.patch |  103 +
 ...4i-Add-HDMI-audio-sun4i-hdmi-encoder.patch |  633 +++
 ...rm-sun4i-sun8i_mixer.c-add-h3-mixer1.patch |   42 +
 ...rm64-dts-axp803-hwmon-enable-thermal.patch |  184 +
 ...-touchscreen-sun4i-ts-Enable-parsing.patch |   63 +
 ...dvb-frontends-si2168-fix-cmd-timeout.patch |   28 +
 .../drv-mfd-axp20x-add-sysfs-interface.patch  |  658 +++
 ...ble-DDR52-mode-on-all-A20-based-boar.patch |   27 +
 ...ost-sunxi-mmc-add-h5-emmc-compatible.patch |   38 +
 ...-nand_ids.c-add-H27UBG8T2BTR-BC-nand.patch |   27 +
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 ...-nvmem-sunxi_sid-Support-SID-on-H616.patch |   41 +
 ...vice-Tree-Overlay-ConfigFS-interface.patch |  343 ++
 ...4i-usb-Allow-reset-line-to-be-shared.patch |   36 +
 ...nctrl-sun50i-a64-disable_strict_mode.patch |   30 +
 ...sun50i-h6.c-GPIO-disable_strict_mode.patch |   24 +
 ...rtc-sun6i-Add-Allwinner-H616-support.patch |   45 +
 ...-support-RTCs-without-external-LOSCs.patch |   68 +
 ...sunxi-sram-Add-SRAM-C1-H616-handling.patch |   41 +
 ...v-spi-spi-sun4i.c-spi-bug-low-on-sck.patch |   36 +
 ...pidev-Add-armbian-spi-dev-compatible.patch |   37 +
 ...-media-sunxi-cedrus-add-H616-variant.patch |   44 +
 .../drv-staging-rtl8723bs-AP-bugfix.patch     |   25 +
 ...name-gadget-serial-console-manufactu.patch |   27 +
 ...nable-TV-Output-on-OrangePi-Zero-LTE.patch |  647 +++
 .../fix-cpu-opp-table-sun8i-a83t.patch        |  115 +
 ...fourcc-add-ARM-tiled-format-modifier.patch |   35 +
 ...pport-for-X-Powers-AC200-EPHY-syscon.patch |  373 ++
 .../mfd-Add-support-for-X-Powers-AC200.patch  |  266 +
 .../mmc-host-sunxi-mmc-Fix-H6-emmc.patch      |   43 +
 .../net-phy-Add-support-for-AC200-EPHY.patch  |  143 +
 ...-r8152-add-LED-configuration-from-OF.patch |   79 +
 ...unxi_get_soc_chipid-sunxi_get_serial.patch |   58 +
 ...ipts-add-overlay-compilation-support.patch |   86 +
 ...the-early-load-of-sun8i-codec-analog.patch |   27 +
 ...4i-codec-adcis-select-capture-source.patch |  120 +
 ...unxi-sun8i-codec-analog-enable-sound.patch |   31 +
 .../kernel/archive/sunxi-6.14/series.armbian  |  182 +
 patch/kernel/archive/sunxi-6.14/series.conf   |  183 +
 179 files changed, 40100 insertions(+)
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 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h5-orangepi-zero-plus-add-regulator.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6-Add-r_uart-uart2-3-pins.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6-orangepi-3-add-r_uart-aliase.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6-orangepi-3-delete-node-spi0.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6-orangepi-add-cpu-opp-refs.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6-orangepi-enable-higher-clock-regulator-max-.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6-orangepi-lite2-spi0-usb3phy-dwc3-enable.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6-orangepi.dtsi-Rollback-r_rsb-to-r_i2c.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6-pine-h64-add-dwc3-usb3phy.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6-pine-h64-add-wifi-rtl8723cs.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6.dtsi-add-pinctrl-pins-for-spi.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6.dtsi-improve-thermals.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h616-add-pwm-nodes-support.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h616-bigtreetech-cb1-sd-emmc.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h616-orangepi-zero2-Enable-GPU-mali.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h616-orangepi-zero2-reg_usb1_vbus-status-ok.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h616-x96-mate-T95-eth-sd-card-hack.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h616-x96-mate-add-hdmi.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h616.dtsi-reserved-memory-512K-for-BL31.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h618-orangepi-zero2w-Add-missing-nodes.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h618-orangepi-zero3-Enable-GPU-mali.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-sun50i-h616-Add-i2c-2-3-4-uart-2-5-pins.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/cb1-overlay.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/clk-gate-add-support-for-regmap-based-gates.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/driver-allwinner-h618-emac.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/drivers-devfreq-sun8i-a33-mbus-disable-autorefresh.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/drivers-pwm-Add-pwm-sunxi-enhance-driver-for-h616.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/drv-clocksource-arm_arch_timer-fix-a64-timejump.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/drv-gpu-drm-gem-dma-Export-with-handle-allocator.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/drv-gpu-drm-panel-simple-Add-compability-olinuxino-lcd.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/drv-gpu-drm-sun4i-Add-GEM-allocator.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/drv-gpu-drm-sun4i-Add-HDMI-audio-sun4i-hdmi-encoder.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/drv-gpu-drm-sun4i-sun8i_mixer.c-add-h3-mixer1.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/drv-iio-adc-axp20x_adc-arm64-dts-axp803-hwmon-enable-thermal.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/drv-input-touchscreen-sun4i-ts-Enable-parsing.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/drv-media-dvb-frontends-si2168-fix-cmd-timeout.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/drv-mfd-axp20x-add-sysfs-interface.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/drv-mmc-host-sunxi-mmc-Disable-DDR52-mode-on-all-A20-based-boar.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/drv-mmc-host-sunxi-mmc-add-h5-emmc-compatible.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/drv-mtd-nand-raw-nand_ids.c-add-H27UBG8T2BTR-BC-nand.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/drv-net-stmmac-dwmac-sun8i-second-EMAC-clock-register.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/drv-nvmem-sunxi_sid-Support-SID-on-H616.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/drv-of-Device-Tree-Overlay-ConfigFS-interface.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/drv-phy-sun4i-usb-Allow-reset-line-to-be-shared.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/drv-pinctrl-pinctrl-sun50i-a64-disable_strict_mode.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/drv-pinctrl-sunxi-pinctrl-sun50i-h6.c-GPIO-disable_strict_mode.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/drv-rtc-sun6i-Add-Allwinner-H616-support.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/drv-rtc-sun6i-support-RTCs-without-external-LOSCs.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/drv-soc-sunxi-sram-Add-SRAM-C1-H616-handling.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/drv-spi-spi-sun4i.c-spi-bug-low-on-sck.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/drv-spi-spidev-Add-armbian-spi-dev-compatible.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/drv-staging-media-sunxi-cedrus-add-H616-variant.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/drv-staging-rtl8723bs-AP-bugfix.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/drv-usb-gadget-composite-rename-gadget-serial-console-manufactu.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/enable-TV-Output-on-OrangePi-Zero-LTE.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/fix-cpu-opp-table-sun8i-a83t.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/include-uapi-drm_fourcc-add-ARM-tiled-format-modifier.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/mfd-Add-support-for-X-Powers-AC200-EPHY-syscon.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/mfd-Add-support-for-X-Powers-AC200.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/mmc-host-sunxi-mmc-Fix-H6-emmc.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/net-phy-Add-support-for-AC200-EPHY.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/net-usb-r8152-add-LED-configuration-from-OF.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/nvmem-sunxi_sid-add-sunxi_get_soc_chipid-sunxi_get_serial.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/scripts-add-overlay-compilation-support.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/sound-soc-sunxi-Provoke-the-early-load-of-sun8i-codec-analog.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/sound-soc-sunxi-sun4i-codec-adcis-select-capture-source.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/sound-soc-sunxi-sun8i-codec-analog-enable-sound.patch
 create mode 100644 patch/kernel/archive/sunxi-6.14/series.armbian

diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/ARM-dts-sun8i-nanopiduo2-Use-key-0-as-power-button.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/ARM-dts-sun8i-nanopiduo2-Use-key-0-as-power-button.patch
new file mode 100644
index 000000000000..efa313c9425a
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/ARM-dts-sun8i-nanopiduo2-Use-key-0-as-power-button.patch
@@ -0,0 +1,31 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Gunjan Gupta <viraniac@gmail.com>
+Date: Mon, 26 Jun 2023 13:29:46 +0000
+Subject: ARM: dts: sun8i: nanopiduo2: Use key-0 as power button
+
+The onboard button key-0 was not marked as power button. This meant
+that once the board was suspended, there was no way to bring it back
+to life. Mark key-0 as power button so that it can be used to bring
+the board back to life
+---
+ arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-duo2.dts | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-duo2.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-duo2.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-duo2.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-duo2.dts
+@@ -42,8 +42,9 @@ gpio-keys {
+ 
+ 		key-0 {
+ 			label = "k1";
+-			linux,code = <BTN_0>;
++			linux,code = <KEY_POWER>;
+ 			gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>; /* PL3 */
++			wakeup-source;
+ 		};
+ 	};
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/ARM-dts-sun8i-nanopiduo2-enable-ethernet.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/ARM-dts-sun8i-nanopiduo2-enable-ethernet.patch
new file mode 100644
index 000000000000..c60ef86c06e1
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/ARM-dts-sun8i-nanopiduo2-enable-ethernet.patch
@@ -0,0 +1,31 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Gunjan Gupta <viraniac@gmail.com>
+Date: Mon, 26 Jun 2023 13:53:14 +0000
+Subject: ARM: dts: sun8i: nanopiduo2: enable ethernet
+
+NanoPi Duo2 has pinout for ethernet. Lets enable the same in dts
+---
+ arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-duo2.dts | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-duo2.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-duo2.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-duo2.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-duo2.dts
+@@ -105,6 +105,13 @@ &ehci0 {
+ 	status = "okay";
+ };
+ 
++&emac {
++	phy-handle = <&int_mii_phy>;
++	phy-mode = "mii";
++	allwinner,leds-active-low;
++	status = "okay";
++};
++
+ &mmc0 {
+ 	bus-width = <4>;
+ 	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/ARM64-dts-sun50i-h616-BigTreeTech-CB1-Enable-EMAC1.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/ARM64-dts-sun50i-h616-BigTreeTech-CB1-Enable-EMAC1.patch
new file mode 100644
index 000000000000..3d9c87c93025
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/ARM64-dts-sun50i-h616-BigTreeTech-CB1-Enable-EMAC1.patch
@@ -0,0 +1,42 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: JohnTheCoolingFan <ivan8215145640@gmail.com>
+Date: Thu, 13 Jun 2024 11:50:55 +0000
+Subject: ARM64: dts: sun50i-h616: BigTreeTech CB1: Enable EMAC1
+
+Signed-off-by: JohnTheCoolingFan <ivan8215145640@gmail.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi | 18 ++++++++++
+ 1 file changed, 18 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi
+@@ -149,6 +149,24 @@ &cpu0 {
+ 	cpu-supply = <&reg_dcdc2>;
+ };
+ 
++&emac1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&rmii_pins>;
++	phy-mode = "rmii";
++	phy-handle = <&rmii_phy>;
++	phy-supply = <&reg_dldo1>;
++	allwinner,rx-delay-ps = <3100>;
++	allwinner,tx-delay-ps = <700>;
++	status = "okay";
++};
++
++&mdio1 {
++	rmii_phy: ethernet-phy@1 {
++		compatible = "ethernet-phy-ieee802.3-c22";
++		reg = <1>;
++	};
++};
++
+ &mmc0 {
+ 	vmmc-supply = <&reg_dldo1>;
+ 	broken-cd;
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/ARM64-dts-sun50i-h616-BigTreeTech-CB1-Enable-HDMI.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/ARM64-dts-sun50i-h616-BigTreeTech-CB1-Enable-HDMI.patch
new file mode 100644
index 000000000000..895e4563401a
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/ARM64-dts-sun50i-h616-BigTreeTech-CB1-Enable-HDMI.patch
@@ -0,0 +1,57 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: JohnTheCoolingFan <ivan8215145640@gmail.com>
+Date: Thu, 13 Jun 2024 11:07:35 +0000
+Subject: ARM64: dts: sun50i-h616: BigTreeTech CB1: Enable HDMI
+
+Signed-off-by: JohnTheCoolingFan <ivan8215145640@gmail.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi | 26 ++++++++++
+ 1 file changed, 26 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi
+@@ -26,6 +26,17 @@ chosen {
+ 		stdout-path = "serial0:115200n8";
+ 	};
+ 
++	connector {
++		compatible = "hdmi-connector";
++		type = "d";
++
++		port {
++			hdmi_con_in: endpoint {
++				remote-endpoint = <&hdmi_out_con>;
++			};
++		};
++	};
++
+ 	leds {
+ 		compatible = "gpio-leds";
+ 
+@@ -262,6 +273,21 @@ reg_dldo1: dldo1 {
+ 	};
+ };
+ 
++&de {
++	status = "okay";
++};
++
++&hdmi {
++	hvcc-supply = <&reg_aldo1>;
++	status = "okay";
++};
++
++&hdmi_out {
++	hdmi_out_con: endpoint {
++		remote-endpoint = <&hdmi_con_in>;
++	};
++};
++
+ &cpu0 {
+ 	cpu-supply = <&reg_dcdc2>;
+ 	status = "okay";
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/ASoC-AC200-Initial-driver.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/ASoC-AC200-Initial-driver.patch
new file mode 100644
index 000000000000..b634e51426f3
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/ASoC-AC200-Initial-driver.patch
@@ -0,0 +1,842 @@
+From 2ace8ce7a3eb989f415186c74e6fbec9d2196c20 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Thu, 1 Sep 2022 17:36:53 +0200
+Subject: ASoC: AC200: Initial driver
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ sound/soc/codecs/Kconfig  |  10 +
+ sound/soc/codecs/Makefile |   2 +
+ sound/soc/codecs/ac200.c  | 772 ++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 784 insertions(+)
+ create mode 100644 sound/soc/codecs/ac200.c
+
+diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
+index 45737cfc5966..1b7b38e3b5b9 100644
+--- a/sound/soc/codecs/Kconfig
++++ b/sound/soc/codecs/Kconfig
+@@ -16,6 +16,7 @@ config SND_SOC_ALL_CODECS
+ 	depends on COMPILE_TEST
+ 	imply SND_SOC_88PM860X
+ 	imply SND_SOC_AB8500_CODEC
++	imply SND_SOC_AC200_CODEC
+ 	imply SND_SOC_AC97_CODEC
+ 	imply SND_SOC_AD1836
+ 	imply SND_SOC_AD193X_SPI
+@@ -417,6 +418,15 @@ config SND_SOC_AB8500_CODEC
+ 	tristate
+ 	depends on ABX500_CORE
+ 
++config SND_SOC_AC200_CODEC
++	tristate "AC200 Codec"
++	depends on MFD_AC200
++	help
++	  Enable support for X-Powers AC200 analog audio codec.
++
++	  To compile this driver as a module, choose M here: the module
++	  will be called snd-soc-ac200.
++
+ config SND_SOC_AC97_CODEC
+ 	tristate "Build generic ASoC AC97 CODEC driver"
+ 	select SND_AC97_CODEC
+diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
+index 7e12f3ae4f7d..eaae2fc19fbd 100644
+--- a/sound/soc/codecs/Makefile
++++ b/sound/soc/codecs/Makefile
+@@ -1,6 +1,7 @@
+ # SPDX-License-Identifier: GPL-2.0
+ snd-soc-88pm860x-y := 88pm860x-codec.o
+ snd-soc-ab8500-codec-y := ab8500-codec.o
++snd-soc-ac200-y := ac200.o
+ snd-soc-ac97-y := ac97.o
+ snd-soc-ad1836-y := ad1836.o
+ snd-soc-ad193x-y := ad193x.o
+@@ -418,6 +419,7 @@ snd-soc-simple-mux-y := simple-mux.o
+ 
+ obj-$(CONFIG_SND_SOC_88PM860X)	+= snd-soc-88pm860x.o
+ obj-$(CONFIG_SND_SOC_AB8500_CODEC)	+= snd-soc-ab8500-codec.o
++obj-$(CONFIG_SND_SOC_AC200_CODEC)	+= snd-soc-ac200.o
+ obj-$(CONFIG_SND_SOC_AC97_CODEC)	+= snd-soc-ac97.o
+ obj-$(CONFIG_SND_SOC_AD1836)	+= snd-soc-ad1836.o
+ obj-$(CONFIG_SND_SOC_AD193X)	+= snd-soc-ad193x.o
+diff --git a/sound/soc/codecs/ac200.c b/sound/soc/codecs/ac200.c
+new file mode 100644
+index 000000000000..662de230dc83
+--- /dev/null
++++ b/sound/soc/codecs/ac200.c
+@@ -0,0 +1,772 @@
++// SPDX-License-Identifier: GPL-2.0-or-later
++/*
++ * X-Powers AC200 Codec Driver
++ *
++ * Copyright (C) 2022 Jernej Skrabec <jernej.skrabec@gmail.com>
++ */
++
++#include <linux/module.h>
++#include <linux/regmap.h>
++#include <sound/core.h>
++#include <sound/pcm.h>
++#include <sound/pcm_params.h>
++#include <sound/soc.h>
++#include <sound/tlv.h>
++
++#define AC200_CODEC_RATES (SNDRV_PCM_RATE_8000 | \
++			   SNDRV_PCM_RATE_11025 | \
++			   SNDRV_PCM_RATE_16000 | \
++			   SNDRV_PCM_RATE_22050 | \
++			   SNDRV_PCM_RATE_32000 | \
++			   SNDRV_PCM_RATE_44100 | \
++			   SNDRV_PCM_RATE_48000 | \
++			   SNDRV_PCM_RATE_96000 | \
++			   SNDRV_PCM_RATE_192000 | \
++			   SNDRV_PCM_RATE_KNOT)
++
++#define AC200_CODEC_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
++			     SNDRV_PCM_FMTBIT_S16_LE | \
++			     SNDRV_PCM_FMTBIT_S20_LE | \
++			     SNDRV_PCM_FMTBIT_S24_LE | \
++			     SNDRV_PCM_FMTBIT_S32_LE)
++
++#define AC200_SYS_AUDIO_CTL0			0x0010
++#define AC200_SYS_AUDIO_CTL0_MCLK_GATING	BIT(1)
++#define AC200_SYS_AUDIO_CTL0_RST_INVALID	BIT(0)
++#define AC200_SYS_AUDIO_CTL1			0x0012
++#define AC200_SYS_AUDIO_CTL1_I2S_IO_EN		BIT(0)
++
++#define AC200_SYS_CLK_CTL			0x2000
++#define AC200_SYS_CLK_CTL_I2S			15
++#define AC200_SYS_CLK_CTL_ADC			3
++#define AC200_SYS_CLK_CTL_DAC			2
++#define AC200_SYS_MOD_RST			0x2002
++#define AC200_SYS_MOD_RST_I2S			15
++#define AC200_SYS_MOD_RST_ADC			3
++#define AC200_SYS_MOD_RST_DAC			2
++#define AC200_SYS_SR_CTL			0x2004
++#define AC200_SYS_SR_CTL_SR_MASK		GENMASK(3, 0)
++#define AC200_SYS_SR_CTL_SR(x)			(x)
++#define AC200_I2S_CTL				0x2100
++#define AC200_I2S_CTL_SDO_EN			3
++#define AC200_I2S_CTL_TX_EN			2
++#define AC200_I2S_CTL_RX_EN			1
++#define AC200_I2S_CTL_GEN			0
++#define AC200_I2S_CLK				0x2102
++#define AC200_I2S_CLK_BCLK_OUT			BIT(15)
++#define AC200_I2S_CLK_LRCK_OUT			BIT(14)
++#define AC200_I2S_CLK_BCLKDIV_MASK		GENMASK(13, 10)
++#define AC200_I2S_CLK_BCLKDIV(x)		((x) << 10)
++#define AC200_I2S_CLK_LRCK_MASK			GENMASK(9, 0)
++#define AC200_I2S_CLK_LRCK(x)			((x) - 1)
++#define AC200_I2S_FMT0				0x2104
++#define AC200_I2S_FMT0_MODE_MASK		GENMASK(15, 14)
++#define AC200_I2S_FMT0_MODE(x)			((x) << 14)
++#define AC200_I2S_FMT0_MODE_PCM			0
++#define AC200_I2S_FMT0_MODE_LEFT		1
++#define AC200_I2S_FMT0_MODE_RIGHT		2
++#define AC200_I2S_FMT0_TX_OFFSET_MASK		GENMASK(11, 10)
++#define AC200_I2S_FMT0_TX_OFFSET(x)		((x) << 10)
++#define AC200_I2S_FMT0_RX_OFFSET_MASK		GENMASK(9, 8)
++#define AC200_I2S_FMT0_RX_OFFSET(x)		((x) << 8)
++#define AC200_I2S_FMT0_SR_MASK			GENMASK(6, 4)
++#define AC200_I2S_FMT0_SR(x)			((x) << 4)
++#define AC200_I2S_FMT0_SW_MASK			GENMASK(3, 1)
++#define AC200_I2S_FMT0_SW(x)			((x) << 1)
++#define AC200_I2S_FMT1				0x2108
++#define AC200_I2S_FMT1_BCLK_POL_INVERT		BIT(15)
++#define AC200_I2S_FMT1_LRCK_POL_INVERT		BIT(14)
++#define AC200_I2S_MIX_SRC			0x2114
++#define AC200_I2S_MIX_SRC_LMIX_DAC		13
++#define AC200_I2S_MIX_SRC_LMIX_ADC		12
++#define AC200_I2S_MIX_SRC_RMIX_DAC		9
++#define AC200_I2S_MIX_SRC_RMIX_ADC		8
++#define AC200_I2S_MIX_GAIN			0x2116
++#define AC200_I2S_MIX_GAIN_LMIX_DAC		13
++#define AC200_I2S_MIX_GAIN_LMIX_ADC		12
++#define AC200_I2S_MIX_GAIN_RMIX_DAC		9
++#define AC200_I2S_MIX_GAIN_RMIX_ADC		8
++#define AC200_I2S_DAC_VOL			0x2118
++#define AC200_I2S_DAC_VOL_LEFT			8
++#define AC200_I2S_DAC_VOL_RIGHT			0
++#define AC200_I2S_ADC_VOL			0x211A
++#define AC200_I2S_ADC_VOL_LEFT			8
++#define AC200_I2S_ADC_VOL_RIGHT			0
++#define AC200_DAC_CTL				0x2200
++#define AC200_DAC_CTL_DAC_EN			15
++#define AC200_DAC_MIX_SRC			0x2202
++#define AC200_DAC_MIX_SRC_LMIX_DAC		13
++#define AC200_DAC_MIX_SRC_LMIX_ADC		12
++#define AC200_DAC_MIX_SRC_RMIX_DAC		9
++#define AC200_DAC_MIX_SRC_RMIX_ADC		8
++#define AC200_DAC_MIX_GAIN			0x2204
++#define AC200_DAC_MIX_GAIN_LMIX_DAC		13
++#define AC200_DAC_MIX_GAIN_LMIX_ADC		12
++#define AC200_DAC_MIX_GAIN_RMIX_DAC		9
++#define AC200_DAC_MIX_GAIN_RMIX_ADC		8
++#define AC200_OUT_MIX_CTL			0x2220
++#define AC200_OUT_MIX_CTL_RDAC_EN		15
++#define AC200_OUT_MIX_CTL_LDAC_EN		14
++#define AC200_OUT_MIX_CTL_RMIX_EN		13
++#define AC200_OUT_MIX_CTL_LMIX_EN		12
++#define AC200_OUT_MIX_CTL_MIC1_VOL		4
++#define AC200_OUT_MIX_CTL_MIC2_VOL		0
++#define AC200_OUT_MIX_SRC			0x2222
++#define AC200_OUT_MIX_SRC_RMIX_MIC1		14
++#define AC200_OUT_MIX_SRC_RMIX_MIC2		13
++#define AC200_OUT_MIX_SRC_RMIX_RDAC		9
++#define AC200_OUT_MIX_SRC_RMIX_LDAC		8
++#define AC200_OUT_MIX_SRC_LMIX_MIC1		6
++#define AC200_OUT_MIX_SRC_LMIX_MIC2		5
++#define AC200_OUT_MIX_SRC_LMIX_RDAC		1
++#define AC200_OUT_MIX_SRC_LMIX_LDAC		0
++#define AC200_LINEOUT_CTL			0x2224
++#define AC200_LINEOUT_CTL_EN			15
++#define AC200_LINEOUT_CTL_LEN			14
++#define AC200_LINEOUT_CTL_REN			13
++#define AC200_LINEOUT_CTL_LMONO			12
++#define AC200_LINEOUT_CTL_RMONO			11
++#define AC200_LINEOUT_CTL_VOL			0
++#define AC200_ADC_CTL				0x2300
++#define AC200_ADC_CTL_ADC_EN			15
++#define AC200_MBIAS_CTL				0x2310
++#define AC200_MBIAS_CTL_MBIAS_EN		15
++#define AC200_MBIAS_CTL_ADDA_BIAS_EN		3
++#define AC200_ADC_MIC_CTL			0x2320
++#define AC200_ADC_MIC_CTL_RADC_EN		15
++#define AC200_ADC_MIC_CTL_LADC_EN		14
++#define AC200_ADC_MIC_CTL_ADC_VOL		8
++#define AC200_ADC_MIC_CTL_MIC1_GAIN_EN		7
++#define AC200_ADC_MIC_CTL_MIC1_BOOST		4
++#define AC200_ADC_MIC_CTL_MIC2_GAIN_EN		3
++#define AC200_ADC_MIC_CTL_MIC2_BOOST		0
++#define AC200_ADC_MIX_SRC			0x2322
++#define AC200_ADC_MIX_SRC_RMIX_MIC1		14
++#define AC200_ADC_MIX_SRC_RMIX_MIC2		13
++#define AC200_ADC_MIX_SRC_RMIX_RMIX		9
++#define AC200_ADC_MIX_SRC_RMIX_LMIX		8
++#define AC200_ADC_MIX_SRC_LMIX_MIC1		6
++#define AC200_ADC_MIX_SRC_LMIX_MIC2		5
++#define AC200_ADC_MIX_SRC_LMIX_LMIX		1
++#define AC200_ADC_MIX_SRC_LMIX_RMIX		0
++
++struct ac200_codec {
++	struct regmap *regmap;
++	unsigned int format;
++};
++
++struct ac200_map {
++	int match;
++	int value;
++};
++
++static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(mixer_scale, -600, 600, 0);
++static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(gain_scale, -450, 150, 0);
++static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(lineout_scale, -4650, 150, 1);
++static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(codec_scale, -12000, 75, 1);
++static const unsigned int mic_scale[] = {
++	TLV_DB_RANGE_HEAD(2),
++	0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
++	1, 7, TLV_DB_SCALE_ITEM(2400, 300, 0),
++};
++
++static const struct snd_kcontrol_new ac200_codec_controls[] = {
++	SOC_DOUBLE_TLV("Master Playback Volume", AC200_I2S_DAC_VOL,
++		       AC200_I2S_DAC_VOL_LEFT, AC200_I2S_DAC_VOL_RIGHT,
++		       0xff, 0, codec_scale),
++	SOC_DOUBLE_TLV("Master Capture Volume", AC200_I2S_ADC_VOL,
++		       AC200_I2S_ADC_VOL_LEFT, AC200_I2S_ADC_VOL_RIGHT,
++		       0xff, 0, codec_scale),
++	SOC_DOUBLE_TLV("I2S ADC Capture Volume", AC200_I2S_MIX_GAIN,
++		       AC200_I2S_MIX_GAIN_LMIX_ADC, AC200_I2S_MIX_GAIN_RMIX_ADC,
++		       0x1, 1, mixer_scale),
++	SOC_DOUBLE_TLV("I2S DAC Capture Volume", AC200_I2S_MIX_GAIN,
++		       AC200_I2S_MIX_GAIN_LMIX_DAC, AC200_I2S_MIX_GAIN_RMIX_DAC,
++		       0x1, 1, mixer_scale),
++	SOC_DOUBLE_TLV("DAC I2S Playback Volume", AC200_DAC_MIX_GAIN,
++		       AC200_DAC_MIX_GAIN_LMIX_DAC, AC200_DAC_MIX_GAIN_RMIX_DAC,
++		       0x1, 1, mixer_scale),
++	SOC_DOUBLE_TLV("ADC Playback Volume", AC200_DAC_MIX_GAIN,
++		       AC200_DAC_MIX_GAIN_LMIX_ADC, AC200_DAC_MIX_GAIN_RMIX_ADC,
++		       0x1, 1, mixer_scale),
++	SOC_SINGLE_TLV("MIC1 Playback Volume", AC200_OUT_MIX_CTL,
++		       AC200_OUT_MIX_CTL_MIC1_VOL, 0x7, 0, gain_scale),
++	SOC_SINGLE_TLV("MIC2 Playback Volume", AC200_OUT_MIX_CTL,
++		       AC200_OUT_MIX_CTL_MIC2_VOL, 0x7, 0, gain_scale),
++	SOC_SINGLE_TLV("ADC Volume", AC200_ADC_MIC_CTL,
++		       AC200_ADC_MIC_CTL_ADC_VOL, 0x07, 0, gain_scale),
++	SOC_SINGLE_TLV("Line Out Playback Volume", AC200_LINEOUT_CTL,
++		       AC200_LINEOUT_CTL_VOL, 0x1f, 0, lineout_scale),
++	SOC_SINGLE_TLV("MIC1 Boost Volume", AC200_ADC_MIC_CTL,
++		       AC200_ADC_MIC_CTL_MIC1_BOOST, 0x07, 0, mic_scale),
++	SOC_SINGLE_TLV("MIC2 Boost Volume", AC200_ADC_MIC_CTL,
++		       AC200_ADC_MIC_CTL_MIC2_BOOST, 0x07, 0, mic_scale),
++	SOC_DOUBLE("Line Out Playback Switch", AC200_LINEOUT_CTL,
++		   AC200_LINEOUT_CTL_LEN, AC200_LINEOUT_CTL_REN, 1, 0),
++};
++
++static const struct snd_kcontrol_new i2s_mixer[] = {
++	SOC_DAPM_DOUBLE("I2S DAC Capture Switch", AC200_I2S_MIX_SRC,
++			AC200_I2S_MIX_SRC_LMIX_DAC,
++			AC200_I2S_MIX_SRC_RMIX_DAC, 1, 0),
++	SOC_DAPM_DOUBLE("I2S ADC Capture Switch", AC200_I2S_MIX_SRC,
++			AC200_I2S_MIX_SRC_LMIX_ADC,
++			AC200_I2S_MIX_SRC_RMIX_ADC, 1, 0),
++};
++
++static const struct snd_kcontrol_new dac_mixer[] = {
++	SOC_DAPM_DOUBLE("DAC I2S Playback Switch", AC200_DAC_MIX_SRC,
++			AC200_DAC_MIX_SRC_LMIX_DAC,
++			AC200_DAC_MIX_SRC_RMIX_DAC, 1, 0),
++	SOC_DAPM_DOUBLE("ADC Playback Switch", AC200_DAC_MIX_SRC,
++			AC200_DAC_MIX_SRC_LMIX_ADC,
++			AC200_DAC_MIX_SRC_RMIX_ADC, 1, 0),
++};
++
++static const struct snd_kcontrol_new output_mixer[] = {
++	SOC_DAPM_DOUBLE("MIC1 Playback Switch", AC200_OUT_MIX_SRC,
++			AC200_OUT_MIX_SRC_LMIX_MIC1,
++			AC200_OUT_MIX_SRC_RMIX_MIC1, 1, 0),
++	SOC_DAPM_DOUBLE("MIC2 Playback Switch", AC200_OUT_MIX_SRC,
++			AC200_OUT_MIX_SRC_LMIX_MIC2,
++			AC200_OUT_MIX_SRC_RMIX_MIC2, 1, 0),
++	SOC_DAPM_DOUBLE("DAC Playback Switch", AC200_OUT_MIX_SRC,
++			AC200_OUT_MIX_SRC_LMIX_LDAC,
++			AC200_OUT_MIX_SRC_RMIX_RDAC, 1, 0),
++	SOC_DAPM_DOUBLE("DAC Reversed Playback Switch", AC200_OUT_MIX_SRC,
++			AC200_OUT_MIX_SRC_LMIX_RDAC,
++			AC200_OUT_MIX_SRC_RMIX_LDAC, 1, 0),
++};
++
++static const struct snd_kcontrol_new input_mixer[] = {
++	SOC_DAPM_DOUBLE("MIC1 Capture Switch", AC200_ADC_MIX_SRC,
++			AC200_ADC_MIX_SRC_LMIX_MIC1,
++			AC200_ADC_MIX_SRC_RMIX_MIC1, 1, 0),
++	SOC_DAPM_DOUBLE("MIC2 Capture Switch", AC200_ADC_MIX_SRC,
++			AC200_ADC_MIX_SRC_LMIX_MIC2,
++			AC200_ADC_MIX_SRC_RMIX_MIC2, 1, 0),
++	SOC_DAPM_DOUBLE("Output Mixer Capture Switch", AC200_ADC_MIX_SRC,
++			AC200_ADC_MIX_SRC_LMIX_LMIX,
++			AC200_ADC_MIX_SRC_RMIX_RMIX, 1, 0),
++	SOC_DAPM_DOUBLE("Output Mixer Reverse Capture Switch",
++			AC200_ADC_MIX_SRC,
++			AC200_ADC_MIX_SRC_LMIX_RMIX,
++			AC200_ADC_MIX_SRC_RMIX_LMIX, 1, 0),
++};
++
++const char * const lineout_mux_enum_text[] = {
++	"Stereo", "Mono",
++};
++
++static SOC_ENUM_DOUBLE_DECL(lineout_mux_enum, AC200_LINEOUT_CTL,
++			    AC200_LINEOUT_CTL_LMONO, AC200_LINEOUT_CTL_RMONO,
++			    lineout_mux_enum_text);
++
++static const struct snd_kcontrol_new lineout_mux =
++	SOC_DAPM_ENUM("Line Out Source Playback Route", lineout_mux_enum);
++
++static const struct snd_soc_dapm_widget ac200_codec_dapm_widgets[] = {
++	/* Regulator */
++	SND_SOC_DAPM_REGULATOR_SUPPLY("avcc", 0, 0),
++
++	/* System clocks */
++	SND_SOC_DAPM_SUPPLY("CLK SYS I2S", AC200_SYS_CLK_CTL,
++			    AC200_SYS_CLK_CTL_I2S, 0, NULL, 0),
++	SND_SOC_DAPM_SUPPLY("CLK SYS DAC", AC200_SYS_CLK_CTL,
++			    AC200_SYS_CLK_CTL_DAC, 0, NULL, 0),
++	SND_SOC_DAPM_SUPPLY("CLK SYS ADC", AC200_SYS_CLK_CTL,
++			    AC200_SYS_CLK_CTL_ADC, 0, NULL, 0),
++
++	/* Module resets */
++	SND_SOC_DAPM_SUPPLY("RST SYS I2S", AC200_SYS_MOD_RST,
++			    AC200_SYS_MOD_RST_I2S, 0, NULL, 0),
++	SND_SOC_DAPM_SUPPLY("RST SYS DAC", AC200_SYS_MOD_RST,
++			    AC200_SYS_MOD_RST_DAC, 0, NULL, 0),
++	SND_SOC_DAPM_SUPPLY("RST SYS ADC", AC200_SYS_MOD_RST,
++			    AC200_SYS_MOD_RST_DAC, 0, NULL, 0),
++
++	/* I2S gates */
++	SND_SOC_DAPM_SUPPLY("CLK I2S GEN", AC200_I2S_CTL,
++			    AC200_I2S_CTL_GEN, 0, NULL, 0),
++	SND_SOC_DAPM_SUPPLY("CLK I2S SDO", AC200_I2S_CTL,
++			    AC200_I2S_CTL_SDO_EN, 0, NULL, 0),
++	SND_SOC_DAPM_SUPPLY("CLK I2S TX", AC200_I2S_CTL,
++			    AC200_I2S_CTL_TX_EN, 0, NULL, 0),
++	SND_SOC_DAPM_SUPPLY("CLK I2S RX", AC200_I2S_CTL,
++			    AC200_I2S_CTL_RX_EN, 0, NULL, 0),
++
++	/* Module supplies */
++	SND_SOC_DAPM_SUPPLY("ADC Enable", AC200_ADC_CTL,
++			    AC200_ADC_CTL_ADC_EN, 0, NULL, 0),
++	SND_SOC_DAPM_SUPPLY("DAC Enable", AC200_DAC_CTL,
++			    AC200_DAC_CTL_DAC_EN, 0, NULL, 0),
++	SND_SOC_DAPM_SUPPLY("Line Out Enable", AC200_LINEOUT_CTL,
++			    AC200_LINEOUT_CTL_EN, 0, NULL, 0),
++
++	/* Bias */
++	SND_SOC_DAPM_SUPPLY("MIC Bias", AC200_MBIAS_CTL,
++			    AC200_MBIAS_CTL_MBIAS_EN, 0, NULL, 0),
++	SND_SOC_DAPM_SUPPLY("ADDA Bias", AC200_MBIAS_CTL,
++			    AC200_MBIAS_CTL_ADDA_BIAS_EN, 0, NULL, 0),
++
++	/* DAC */
++	SND_SOC_DAPM_DAC("Left DAC", "Playback", AC200_OUT_MIX_CTL,
++			 AC200_OUT_MIX_CTL_LDAC_EN, 0),
++	SND_SOC_DAPM_DAC("Right DAC", "Playback", AC200_OUT_MIX_CTL,
++			 AC200_OUT_MIX_CTL_RDAC_EN, 0),
++
++	/* ADC */
++	SND_SOC_DAPM_ADC("Left ADC", "Capture", AC200_ADC_MIC_CTL,
++			 AC200_ADC_MIC_CTL_LADC_EN, 0),
++	SND_SOC_DAPM_ADC("Right ADC", "Capture", AC200_ADC_MIC_CTL,
++			 AC200_ADC_MIC_CTL_RADC_EN, 0),
++
++	/* Mixers */
++	SND_SOC_DAPM_MIXER("Left Output Mixer", AC200_OUT_MIX_CTL,
++			   AC200_OUT_MIX_CTL_LMIX_EN, 0,
++			   output_mixer, ARRAY_SIZE(output_mixer)),
++	SND_SOC_DAPM_MIXER("Right Output Mixer", AC200_OUT_MIX_CTL,
++			   AC200_OUT_MIX_CTL_RMIX_EN, 0,
++			   output_mixer, ARRAY_SIZE(output_mixer)),
++
++	SND_SOC_DAPM_MIXER("Left Input Mixer", SND_SOC_NOPM, 0, 0,
++			   input_mixer, ARRAY_SIZE(input_mixer)),
++	SND_SOC_DAPM_MIXER("Right Input Mixer", SND_SOC_NOPM, 0, 0,
++			   input_mixer, ARRAY_SIZE(input_mixer)),
++
++	SND_SOC_DAPM_MIXER("Left DAC Mixer", SND_SOC_NOPM, 0, 0,
++			   dac_mixer, ARRAY_SIZE(dac_mixer)),
++	SND_SOC_DAPM_MIXER("Right DAC Mixer", SND_SOC_NOPM, 0, 0,
++			   dac_mixer, ARRAY_SIZE(dac_mixer)),
++
++	SND_SOC_DAPM_MIXER("Left I2S Mixer", SND_SOC_NOPM, 0, 0,
++			   i2s_mixer, ARRAY_SIZE(i2s_mixer)),
++	SND_SOC_DAPM_MIXER("Right I2S Mixer", SND_SOC_NOPM, 0, 0,
++			   i2s_mixer, ARRAY_SIZE(i2s_mixer)),
++
++	/* Muxes */
++	SND_SOC_DAPM_MUX("Line Out Source Playback Route",
++			 SND_SOC_NOPM, 0, 0, &lineout_mux),
++
++	/* Gain/attenuation */
++	SND_SOC_DAPM_PGA("MIC1 Amplifier", AC200_ADC_MIC_CTL,
++			 AC200_ADC_MIC_CTL_MIC1_GAIN_EN, 0, NULL, 0),
++	SND_SOC_DAPM_PGA("MIC2 Amplifier", AC200_ADC_MIC_CTL,
++			 AC200_ADC_MIC_CTL_MIC2_GAIN_EN, 0, NULL, 0),
++
++	/* Inputs */
++	SND_SOC_DAPM_INPUT("MIC1"),
++	SND_SOC_DAPM_INPUT("MIC2"),
++
++	/* Outputs */
++	SND_SOC_DAPM_OUTPUT("LINEOUT"),
++};
++
++static const struct snd_soc_dapm_route ac200_codec_dapm_routes[] = {
++	{ "RST SYS I2S", NULL, "CLK SYS I2S" },
++	{ "RST SYS ADC", NULL, "CLK SYS ADC" },
++	{ "RST SYS DAC", NULL, "CLK SYS DAC" },
++
++	{ "CLK I2S GEN", NULL, "RST SYS I2S" },
++	{ "CLK I2S SDO", NULL, "CLK I2S GEN" },
++	{ "CLK I2S TX", NULL, "CLK I2S SDO" },
++	{ "CLK I2S RX", NULL, "CLK I2S SDO" },
++
++	{ "ADC Enable", NULL, "RST SYS ADC" },
++	{ "ADC Enable", NULL, "ADDA Bias" },
++	{ "ADC Enable", NULL, "avcc" },
++	{ "DAC Enable", NULL, "RST SYS DAC" },
++	{ "DAC Enable", NULL, "ADDA Bias" },
++	{ "DAC Enable", NULL, "avcc" },
++
++	{ "Left DAC", NULL,  "DAC Enable" },
++	{ "Left DAC", NULL,  "CLK I2S RX" },
++	{ "Right DAC", NULL,  "DAC Enable" },
++	{ "Right DAC", NULL,  "CLK I2S RX" },
++
++	{ "Left ADC", NULL,  "ADC Enable" },
++	{ "Left ADC", NULL,  "CLK I2S TX" },
++	{ "Right ADC", NULL,  "ADC Enable" },
++	{ "Right ADC", NULL,  "CLK I2S TX" },
++
++	{ "Left Output Mixer", "MIC1 Playback Switch", "MIC1 Amplifier" },
++	{ "Left Output Mixer", "MIC2 Playback Switch", "MIC2 Amplifier" },
++	{ "Left Output Mixer", "DAC Playback Switch", "Left DAC Mixer" },
++	{ "Left Output Mixer", "DAC Reversed Playback Switch", "Right DAC Mixer" },
++
++	{ "Right Output Mixer", "MIC1 Playback Switch", "MIC1 Amplifier" },
++	{ "Right Output Mixer", "MIC2 Playback Switch", "MIC2 Amplifier" },
++	{ "Right Output Mixer", "DAC Playback Switch", "Right DAC Mixer" },
++	{ "Right Output Mixer", "DAC Reversed Playback Switch", "Left DAC Mixer" },
++
++	{ "Left Input Mixer", "MIC1 Capture Switch", "MIC1 Amplifier" },
++	{ "Left Input Mixer", "MIC2 Capture Switch", "MIC2 Amplifier" },
++	{ "Left Input Mixer", "Output Mixer Capture Switch", "Left Output Mixer" },
++	{ "Left Input Mixer", "Output Mixer Reverse Capture Switch", "Right Output Mixer" },
++
++	{ "Right Input Mixer", "MIC1 Capture Switch", "MIC1 Amplifier" },
++	{ "Right Input Mixer", "MIC2 Capture Switch", "MIC2 Amplifier" },
++	{ "Right Input Mixer", "Output Mixer Capture Switch", "Right Output Mixer" },
++	{ "Right Input Mixer", "Output Mixer Reverse Capture Switch", "Left Output Mixer" },
++
++	{ "Left I2S Mixer", "I2S DAC Capture Switch", "Left DAC" },
++	{ "Left I2S Mixer", "I2S ADC Capture Switch", "Left Input Mixer" },
++	{ "Right I2S Mixer", "I2S DAC Capture Switch", "Right DAC" },
++	{ "Right I2S Mixer", "I2S ADC Capture Switch", "Right Input Mixer" },
++
++	{ "Left DAC Mixer", "DAC I2S Playback Switch", "Left DAC" },
++	{ "Left DAC Mixer", "ADC Playback Switch", "Left Input Mixer" },
++	{ "Right DAC Mixer", "DAC I2S Playback Switch", "Right DAC" },
++	{ "Right DAC Mixer", "ADC Playback Switch", "Right Input Mixer" },
++
++	{ "Line Out Source Playback Route", "Stereo", "Left Output Mixer" },
++	{ "Line Out Source Playback Route", "Stereo", "Right Output Mixer" },
++	{ "Line Out Source Playback Route", "Mono", "Right Output Mixer" },
++	{ "Line Out Source Playback Route", "Mono", "Left Output Mixer" },
++
++	{ "Left ADC", NULL, "Left I2S Mixer" },
++	{ "Right ADC", NULL, "Right I2S Mixer" },
++
++	{ "LINEOUT", NULL, "Line Out Enable", },
++	{ "LINEOUT", NULL, "Line Out Source Playback Route" },
++
++	{ "MIC1", NULL, "MIC Bias" },
++	{ "MIC2", NULL, "MIC Bias" },
++	{ "MIC1 Amplifier", NULL, "MIC1" },
++	{ "MIC2 Amplifier", NULL, "MIC2" },
++};
++
++static int ac200_get_sr_sw(unsigned int width)
++{
++	switch (width) {
++	case 8:
++		return 1;
++	case 12:
++		return 2;
++	case 16:
++		return 3;
++	case 20:
++		return 4;
++	case 24:
++		return 5;
++	case 28:
++		return 6;
++	case 32:
++		return 7;
++	}
++
++	return -EINVAL;
++}
++
++static const struct ac200_map ac200_bclk_div_map[] = {
++	{ .match = 1,	.value = 1 },
++	{ .match = 2,	.value = 2 },
++	{ .match = 4,	.value = 3 },
++	{ .match = 6,	.value = 4 },
++	{ .match = 8,	.value = 5 },
++	{ .match = 12,	.value = 6 },
++	{ .match = 16,	.value = 7 },
++	{ .match = 24,	.value = 8 },
++	{ .match = 32,	.value = 9 },
++	{ .match = 48,	.value = 10 },
++	{ .match = 64,	.value = 11 },
++	{ .match = 96,	.value = 12 },
++	{ .match = 128,	.value = 13 },
++	{ .match = 176,	.value = 14 },
++	{ .match = 192,	.value = 15 },
++};
++
++static int ac200_get_bclk_div(unsigned int sample_rate, unsigned int period)
++{
++	unsigned int sysclk_rate = (sample_rate % 4000) ? 22579200 : 24576000;
++	unsigned int div = sysclk_rate / sample_rate / period;
++	int i;
++
++	for (i = 0; i < ARRAY_SIZE(ac200_bclk_div_map); i++) {
++		const struct ac200_map *bdiv = &ac200_bclk_div_map[i];
++
++		if (bdiv->match == div)
++			return bdiv->value;
++	}
++
++	return -EINVAL;
++}
++
++static const struct ac200_map ac200_ssr_map[] = {
++	{ .match = 8000,	.value = 0 },
++	{ .match = 11025,	.value = 1 },
++	{ .match = 12000,	.value = 2 },
++	{ .match = 16000,	.value = 3 },
++	{ .match = 22050,	.value = 4 },
++	{ .match = 24000,	.value = 5 },
++	{ .match = 32000,	.value = 6 },
++	{ .match = 44100,	.value = 7 },
++	{ .match = 48000,	.value = 8 },
++	{ .match = 96000,	.value = 9 },
++	{ .match = 192000,	.value = 10 },
++};
++
++static int ac200_get_ssr(unsigned int sample_rate)
++{
++	int i;
++
++	for (i = 0; i < ARRAY_SIZE(ac200_ssr_map); i++) {
++		const struct ac200_map *ssr = &ac200_ssr_map[i];
++
++		if (ssr->match == sample_rate)
++			return ssr->value;
++	}
++
++	return -EINVAL;
++}
++
++static int ac200_codec_hw_params(struct snd_pcm_substream *substream,
++				 struct snd_pcm_hw_params *params,
++				 struct snd_soc_dai *dai)
++{
++	struct ac200_codec *priv = snd_soc_dai_get_drvdata(dai);
++	unsigned int slot_width = params_physical_width(params);
++	unsigned int sample_rate = params_rate(params);
++	int sr, period, sw, bclkdiv, ssr;
++
++	sr = ac200_get_sr_sw(params_width(params));
++	if (sr < 0)
++		return sr;
++
++	sw = ac200_get_sr_sw(slot_width);
++	if (sw < 0)
++		return sw;
++
++	regmap_update_bits(priv->regmap, AC200_I2S_FMT0,
++			   AC200_I2S_FMT0_SR_MASK |
++			   AC200_I2S_FMT0_SW_MASK,
++			   AC200_I2S_FMT0_SR(sr) |
++			   AC200_I2S_FMT0_SW(sw));
++
++	switch (priv->format & SND_SOC_DAIFMT_FORMAT_MASK) {
++	case SND_SOC_DAIFMT_I2S:
++	case SND_SOC_DAIFMT_RIGHT_J:
++	case SND_SOC_DAIFMT_LEFT_J:
++		period = slot_width;
++		break;
++	case SND_SOC_DAIFMT_DSP_A:
++	case SND_SOC_DAIFMT_DSP_B:
++		period = slot_width * 2;
++		break;
++	}
++
++	bclkdiv = ac200_get_bclk_div(sample_rate, period);
++	if (bclkdiv < 0)
++		return bclkdiv;
++
++	regmap_update_bits(priv->regmap, AC200_I2S_CLK,
++			   AC200_I2S_CLK_LRCK_MASK |
++			   AC200_I2S_CLK_BCLKDIV_MASK,
++			   AC200_I2S_CLK_LRCK(period) |
++			   AC200_I2S_CLK_BCLKDIV(bclkdiv));
++
++	ssr = ac200_get_ssr(sample_rate);
++	if (ssr < 0)
++		return ssr;
++
++	regmap_update_bits(priv->regmap, AC200_SYS_SR_CTL,
++			   AC200_SYS_SR_CTL_SR_MASK,
++			   AC200_SYS_SR_CTL_SR(ssr));
++
++	return 0;
++}
++
++static int ac200_codec_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
++{
++	struct ac200_codec *priv = snd_soc_dai_get_drvdata(dai);
++	unsigned long offset, mode, value;
++
++	priv->format = fmt;
++
++	switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
++	case SND_SOC_DAIFMT_CBP_CFP:
++		value = AC200_I2S_CLK_BCLK_OUT | AC200_I2S_CLK_LRCK_OUT;
++		break;
++	case SND_SOC_DAIFMT_CBC_CFP:
++		value = AC200_I2S_CLK_LRCK_OUT;
++		break;
++	case SND_SOC_DAIFMT_CBP_CFC:
++		value = AC200_I2S_CLK_BCLK_OUT;
++		break;
++	case SND_SOC_DAIFMT_CBC_CFC:
++		value = 0;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	regmap_update_bits(priv->regmap, AC200_I2S_CLK,
++			   AC200_I2S_CLK_BCLK_OUT |
++			   AC200_I2S_CLK_LRCK_OUT, value);
++
++	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
++	case SND_SOC_DAIFMT_I2S:
++		mode = AC200_I2S_FMT0_MODE_LEFT;
++		offset = 1;
++		break;
++	case SND_SOC_DAIFMT_RIGHT_J:
++		mode = AC200_I2S_FMT0_MODE_RIGHT;
++		offset = 0;
++		break;
++	case SND_SOC_DAIFMT_LEFT_J:
++		mode = AC200_I2S_FMT0_MODE_LEFT;
++		offset = 0;
++		break;
++	case SND_SOC_DAIFMT_DSP_A:
++		mode = AC200_I2S_FMT0_MODE_PCM;
++		offset = 1;
++		break;
++	case SND_SOC_DAIFMT_DSP_B:
++		mode = AC200_I2S_FMT0_MODE_PCM;
++		offset = 0;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	regmap_update_bits(priv->regmap, AC200_I2S_FMT0,
++			   AC200_I2S_FMT0_MODE_MASK |
++			   AC200_I2S_FMT0_TX_OFFSET_MASK |
++			   AC200_I2S_FMT0_RX_OFFSET_MASK,
++			   AC200_I2S_FMT0_MODE(mode) |
++			   AC200_I2S_FMT0_TX_OFFSET(offset) |
++			   AC200_I2S_FMT0_RX_OFFSET(offset));
++
++	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
++	case SND_SOC_DAIFMT_NB_NF:
++		value = 0;
++		break;
++	case SND_SOC_DAIFMT_NB_IF:
++		value = AC200_I2S_FMT1_LRCK_POL_INVERT;
++		break;
++	case SND_SOC_DAIFMT_IB_NF:
++		value = AC200_I2S_FMT1_BCLK_POL_INVERT;
++		break;
++	case SND_SOC_DAIFMT_IB_IF:
++		value = AC200_I2S_FMT1_BCLK_POL_INVERT |
++			AC200_I2S_FMT1_LRCK_POL_INVERT;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	regmap_update_bits(priv->regmap, AC200_I2S_FMT1,
++			   AC200_I2S_FMT1_BCLK_POL_INVERT |
++			   AC200_I2S_FMT1_LRCK_POL_INVERT, value);
++
++
++	return 0;
++}
++
++static const struct snd_soc_dai_ops ac200_codec_dai_ops = {
++	.hw_params	= ac200_codec_hw_params,
++	.set_fmt	= ac200_codec_set_fmt,
++};
++
++static struct snd_soc_dai_driver ac200_codec_dai = {
++	.name = "ac200-dai",
++	.playback = {
++		.stream_name = "Playback",
++		.channels_min = 2,
++		.channels_max = 2,
++		.rates = AC200_CODEC_RATES,
++		.formats = AC200_CODEC_FORMATS,
++	},
++	.capture = {
++		.stream_name = "Capture",
++		.channels_min = 1,
++		.channels_max = 2,
++		.rates = AC200_CODEC_RATES,
++		.formats = AC200_CODEC_FORMATS,
++	},
++	.ops = &ac200_codec_dai_ops,
++	.symmetric_rate = 1,
++	.symmetric_sample_bits = 1,
++};
++
++static int ac200_codec_component_probe(struct snd_soc_component *component)
++{
++	struct ac200_codec *priv = snd_soc_component_get_drvdata(component);
++
++	snd_soc_component_init_regmap(component, priv->regmap);
++
++	return 0;
++}
++
++static struct snd_soc_component_driver ac200_soc_component = {
++	.controls		= ac200_codec_controls,
++	.num_controls		= ARRAY_SIZE(ac200_codec_controls),
++	.dapm_widgets		= ac200_codec_dapm_widgets,
++	.num_dapm_widgets	= ARRAY_SIZE(ac200_codec_dapm_widgets),
++	.dapm_routes		= ac200_codec_dapm_routes,
++	.num_dapm_routes	= ARRAY_SIZE(ac200_codec_dapm_routes),
++	.probe			= ac200_codec_component_probe,
++};
++
++static int ac200_codec_probe(struct platform_device *pdev)
++{
++	struct ac200_codec *priv;
++	int ret;
++
++	priv = devm_kzalloc(&pdev->dev, sizeof(struct ac200_codec), GFP_KERNEL);
++	if (!priv)
++		return -ENOMEM;
++
++	priv->regmap = dev_get_regmap(pdev->dev.parent, NULL);
++	if (!priv->regmap)
++		return -EPROBE_DEFER;
++
++	platform_set_drvdata(pdev, priv);
++
++	ret = regmap_write(priv->regmap, AC200_SYS_AUDIO_CTL0,
++			   AC200_SYS_AUDIO_CTL0_RST_INVALID |
++			   AC200_SYS_AUDIO_CTL0_MCLK_GATING);
++	if (ret)
++		return ret;
++
++	ret = regmap_write(priv->regmap, AC200_SYS_AUDIO_CTL1,
++			   AC200_SYS_AUDIO_CTL1_I2S_IO_EN);
++	if (ret)
++		return ret;
++
++	ret = devm_snd_soc_register_component(&pdev->dev, &ac200_soc_component,
++					      &ac200_codec_dai, 1);
++
++	if (ret)
++		dev_err(&pdev->dev, "Failed to register codec: %d\n", ret);
++
++	return ret;
++}
++
++static void ac200_codec_remove(struct platform_device *pdev)
++{
++	struct ac200_codec *priv =  dev_get_drvdata(&pdev->dev);
++
++	regmap_write(priv->regmap, AC200_SYS_AUDIO_CTL0, 0);
++	regmap_write(priv->regmap, AC200_SYS_AUDIO_CTL1, 0);
++}
++
++static const struct of_device_id ac200_codec_match[] = {
++	{ .compatible = "x-powers,ac200-codec" },
++	{ }
++};
++MODULE_DEVICE_TABLE(of, ac200_codec_match);
++
++static struct platform_driver ac200_codec_driver = {
++	.driver = {
++		.name = "ac200-codec",
++		.of_match_table = ac200_codec_match,
++	},
++	.probe = ac200_codec_probe,
++	.remove = ac200_codec_remove,
++};
++module_platform_driver(ac200_codec_driver);
++
++MODULE_DESCRIPTION("X-Powers AC200 Codec Driver");
++MODULE_AUTHOR("Jernej Skrabec <jernej.skrabec@gmail.com>");
++MODULE_LICENSE("GPL");
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/Add-BananaPi-BPI-M4-Zero-overlays.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/Add-BananaPi-BPI-M4-Zero-overlays.patch
new file mode 100644
index 000000000000..00642052e852
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/Add-BananaPi-BPI-M4-Zero-overlays.patch
@@ -0,0 +1,377 @@
+From 43a7177563683a1e7d192138f65073d687ed068b Mon Sep 17 00:00:00 2001
+From: Patrick Yavitz <pyavitz@armbian.com>
+Date: Tue, 7 Jan 2025 06:39:30 -0500
+Subject: Add BananaPi BPI-M4-Zero overlays
+
+Signed-off-by: Patrick Yavitz <pyavitz@armbian.com>
+---
+ .../arm64/boot/dts/allwinner/overlay/Makefile | 13 ++++++
+ ...sun50i-h616-bananapi-m4-pg-15-16-i2c4.dtso | 13 ++++++
+ ...sun50i-h616-bananapi-m4-pg-17-18-i2c3.dtso | 13 ++++++
+ .../sun50i-h616-bananapi-m4-pg-6-7-uart1.dtso | 13 ++++++
+ ...h616-bananapi-m4-pg-8-9-rts-cts-uart1.dtso | 16 +++++++
+ .../sun50i-h616-bananapi-m4-ph-2-3-uart5.dtso | 13 ++++++
+ ...un50i-h616-bananapi-m4-pi-13-14-uart4.dtso | 13 ++++++
+ ...16-bananapi-m4-pi-15-16-rts-cts-uart4.dtso | 16 +++++++
+ .../sun50i-h616-bananapi-m4-pi-5-6-i2c0.dtso  | 13 ++++++
+ .../sun50i-h616-bananapi-m4-pi-7-8-i2c1.dtso  | 13 ++++++
+ .../sun50i-h616-bananapi-m4-sdio-wifi-bt.dtso | 44 +++++++++++++++++++
+ ...-h616-bananapi-m4-spi1-cs0-cs1-spidev.dtso | 32 ++++++++++++++
+ ...n50i-h616-bananapi-m4-spi1-cs0-spidev.dtso | 24 ++++++++++
+ ...n50i-h616-bananapi-m4-spi1-cs1-spidev.dtso | 13 ++++++
+ 14 files changed, 249 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-bananapi-m4-pg-15-16-i2c4.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-bananapi-m4-pg-17-18-i2c3.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-bananapi-m4-pg-6-7-uart1.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-bananapi-m4-pg-8-9-rts-cts-uart1.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-bananapi-m4-ph-2-3-uart5.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-bananapi-m4-pi-13-14-uart4.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-bananapi-m4-pi-15-16-rts-cts-uart4.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-bananapi-m4-pi-5-6-i2c0.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-bananapi-m4-pi-7-8-i2c1.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-bananapi-m4-sdio-wifi-bt.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-bananapi-m4-spi1-cs0-cs1-spidev.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-bananapi-m4-spi1-cs0-spidev.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-bananapi-m4-spi1-cs1-spidev.dtso
+
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/Makefile b/arch/arm64/boot/dts/allwinner/overlay/Makefile
+index ccb89b5bf495..3e87d21c9d14 100644
+--- a/arch/arm64/boot/dts/allwinner/overlay/Makefile
++++ b/arch/arm64/boot/dts/allwinner/overlay/Makefile
+@@ -49,6 +49,19 @@ dtb-$(CONFIG_ARCH_SUNXI) += \
+ 	sun50i-h6-uart2.dtbo \
+ 	sun50i-h6-uart3.dtbo \
+ 	sun50i-h6-w1-gpio.dtbo \
++	sun50i-h616-bananapi-m4-pg-6-7-uart1.dtbo \
++	sun50i-h616-bananapi-m4-pg-8-9-rts-cts-uart1.dtbo \
++	sun50i-h616-bananapi-m4-pg-15-16-i2c4.dtbo \
++	sun50i-h616-bananapi-m4-pg-17-18-i2c3.dtbo \
++	sun50i-h616-bananapi-m4-ph-2-3-uart5.dtbo \
++	sun50i-h616-bananapi-m4-pi-13-14-uart4.dtbo \
++	sun50i-h616-bananapi-m4-pi-15-16-rts-cts-uart4.dtbo \
++	sun50i-h616-bananapi-m4-pi-5-6-i2c0.dtbo \
++	sun50i-h616-bananapi-m4-pi-7-8-i2c1.dtbo \
++	sun50i-h616-bananapi-m4-sdio-wifi-bt.dtbo \
++	sun50i-h616-bananapi-m4-spi1-cs0-cs1-spidev.dtbo \
++	sun50i-h616-bananapi-m4-spi1-cs0-spidev.dtbo \
++	sun50i-h616-bananapi-m4-spi1-cs1-spidev.dtbo \
+ 	sun50i-h616-gpu.dtbo \
+ 	sun50i-h616-i2c0-pi.dtbo \
+ 	sun50i-h616-i2c1-pi.dtbo \
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-bananapi-m4-pg-15-16-i2c4.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-bananapi-m4-pg-15-16-i2c4.dtso
+new file mode 100644
+index 000000000000..4e78aa8f1f27
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-bananapi-m4-pg-15-16-i2c4.dtso
+@@ -0,0 +1,13 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "sinovoip,bpi-m4-zero", "allwinner,sun50i-h616", "allwinner,sun50i-h618";
++
++	fragment@0 {
++		target = <&i2c4>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-bananapi-m4-pg-17-18-i2c3.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-bananapi-m4-pg-17-18-i2c3.dtso
+new file mode 100644
+index 000000000000..3419eee0b70b
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-bananapi-m4-pg-17-18-i2c3.dtso
+@@ -0,0 +1,13 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "sinovoip,bpi-m4-zero", "allwinner,sun50i-h616", "allwinner,sun50i-h618";
++
++	fragment@0 {
++		target = <&i2c3>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-bananapi-m4-pg-6-7-uart1.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-bananapi-m4-pg-6-7-uart1.dtso
+new file mode 100644
+index 000000000000..7001781f42d2
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-bananapi-m4-pg-6-7-uart1.dtso
+@@ -0,0 +1,13 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "sinovoip,bpi-m4-zero", "allwinner,sun50i-h616", "allwinner,sun50i-h618";
++
++	fragment@0 {
++		target = <&uart1>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-bananapi-m4-pg-8-9-rts-cts-uart1.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-bananapi-m4-pg-8-9-rts-cts-uart1.dtso
+new file mode 100644
+index 000000000000..1317a9b3b52f
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-bananapi-m4-pg-8-9-rts-cts-uart1.dtso
+@@ -0,0 +1,16 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "sinovoip,bpi-m4-zero", "allwinner,sun50i-h616", "allwinner,sun50i-h618";
++
++	fragment@0 {
++		target = <&uart1>;
++		__overlay__ {
++			status = "okay";
++			pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
++			pinctrl-names = "default";
++			uart-has-rtscts;
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-bananapi-m4-ph-2-3-uart5.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-bananapi-m4-ph-2-3-uart5.dtso
+new file mode 100644
+index 000000000000..aaa96e46d708
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-bananapi-m4-ph-2-3-uart5.dtso
+@@ -0,0 +1,13 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "sinovoip,bpi-m4-zero", "allwinner,sun50i-h616", "allwinner,sun50i-h618";
++
++	fragment@0 {
++		target = <&uart5>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-bananapi-m4-pi-13-14-uart4.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-bananapi-m4-pi-13-14-uart4.dtso
+new file mode 100644
+index 000000000000..0373f7d25449
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-bananapi-m4-pi-13-14-uart4.dtso
+@@ -0,0 +1,13 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "sinovoip,bpi-m4-zero", "allwinner,sun50i-h616", "allwinner,sun50i-h618";
++
++	fragment@0 {
++		target = <&uart4>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-bananapi-m4-pi-15-16-rts-cts-uart4.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-bananapi-m4-pi-15-16-rts-cts-uart4.dtso
+new file mode 100644
+index 000000000000..ef9394c8519c
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-bananapi-m4-pi-15-16-rts-cts-uart4.dtso
+@@ -0,0 +1,16 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "sinovoip,bpi-m4-zero", "allwinner,sun50i-h616", "allwinner,sun50i-h618";
++
++	fragment@0 {
++		target = <&uart4>;
++		__overlay__ {
++			status = "okay";
++			pinctrl-0 = <&uart4_pi_pins>, <&uart4_pi_rts_cts_pins>;
++			pinctrl-names = "default";
++			uart-has-rtscts;
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-bananapi-m4-pi-5-6-i2c0.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-bananapi-m4-pi-5-6-i2c0.dtso
+new file mode 100644
+index 000000000000..60c75e4d61b5
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-bananapi-m4-pi-5-6-i2c0.dtso
+@@ -0,0 +1,13 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "sinovoip,bpi-m4-zero", "allwinner,sun50i-h616", "allwinner,sun50i-h618";
++
++	fragment@0 {
++		target = <&i2c0>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-bananapi-m4-pi-7-8-i2c1.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-bananapi-m4-pi-7-8-i2c1.dtso
+new file mode 100644
+index 000000000000..99c7e2b8c5f6
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-bananapi-m4-pi-7-8-i2c1.dtso
+@@ -0,0 +1,13 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "sinovoip,bpi-m4-zero", "allwinner,sun50i-h616", "allwinner,sun50i-h618";
++
++	fragment@0 {
++		target = <&i2c1>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-bananapi-m4-sdio-wifi-bt.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-bananapi-m4-sdio-wifi-bt.dtso
+new file mode 100644
+index 000000000000..307f6e5e921c
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-bananapi-m4-sdio-wifi-bt.dtso
+@@ -0,0 +1,44 @@
++/dts-v1/;
++/plugin/;
++
++#include <dt-bindings/gpio/gpio.h>
++
++/ {
++	compatible = "sinovoip,bpi-m4-zero", "allwinner,sun50i-h616", "allwinner,sun50i-h618";
++
++	fragment@0 {
++		target-path = "/";
++		__overlay__ {
++			model = "BananaPi BPI-M4-Zero v2";
++		};
++	};
++
++	/* SDIO WIFI */
++	fragment@1 {
++		target = <&mmc1>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++
++	/* BLUETOOTH */
++	fragment@2 {
++		target = <&uart1>;
++		__overlay__ {
++			status = "okay";
++			pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
++			pinctrl-names = "default";
++			uart-has-rtscts;
++
++			bluetooth {
++				compatible = "brcm,bcm43540-bt";
++				host-wakeup-gpios = <&pio 6 16 GPIO_ACTIVE_HIGH>;
++				device-wakeup-gpios = <&pio 6 17 GPIO_ACTIVE_HIGH>;
++				shutdown-gpios = <&pio 6 19 GPIO_ACTIVE_HIGH>;
++				max-speed = <1500000>;
++				vbat-supply = <&reg_vcc3v3>;
++				vddio-supply = <&reg_vcc1v8>;
++			};
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-bananapi-m4-spi1-cs0-cs1-spidev.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-bananapi-m4-spi1-cs0-cs1-spidev.dtso
+new file mode 100644
+index 000000000000..7fa3b94bcc8d
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-bananapi-m4-spi1-cs0-cs1-spidev.dtso
+@@ -0,0 +1,32 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "sinovoip,bpi-m4-zero", "allwinner,sun50i-h616", "allwinner,sun50i-h618";
++
++	fragment@0 {
++		target = <&spi1>;
++		__overlay__ {
++			status = "okay";
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			pinctrl-names = "default";
++			pinctrl-0 = <&spi1_pins>, <&spi1_cs0_pin>, <&spi1_cs1_pin>;
++
++			spidev@0 {
++				compatible = "rohm,dh2228fv";
++				status = "okay";
++				reg = <0>;
++				spi-max-frequency = <50000000>;
++			};
++
++			spidev@1 {
++				compatible = "rohm,dh2228fv";
++				status = "okay";
++				reg = <1>;
++				spi-max-frequency = <50000000>;
++			};
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-bananapi-m4-spi1-cs0-spidev.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-bananapi-m4-spi1-cs0-spidev.dtso
+new file mode 100644
+index 000000000000..fef73f1afa52
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-bananapi-m4-spi1-cs0-spidev.dtso
+@@ -0,0 +1,24 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "sinovoip,bpi-m4-zero", "allwinner,sun50i-h616", "allwinner,sun50i-h618";
++
++	fragment@0 {
++		target = <&spi1>;
++		__overlay__ {
++			status = "okay";
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++                        pinctrl-names = "default";
++                        pinctrl-0 = <&spi1_pins>, <&spi1_cs0_pin>;
++			spidev@0 {
++				compatible = "rohm,dh2228fv";
++				status = "okay";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-bananapi-m4-spi1-cs1-spidev.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-bananapi-m4-spi1-cs1-spidev.dtso
+new file mode 100644
+index 000000000000..840357f2e9e0
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-bananapi-m4-spi1-cs1-spidev.dtso
+@@ -0,0 +1,13 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "sinovoip,bpi-m4-zero", "allwinner,sun50i-h616", "allwinner,sun50i-h618";
++
++	fragment@0 {
++		target = <&spi1>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/Add-BananaPi-BPI-M4-Zero-pinctrl.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/Add-BananaPi-BPI-M4-Zero-pinctrl.patch
new file mode 100644
index 000000000000..42e2ef571923
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/Add-BananaPi-BPI-M4-Zero-pinctrl.patch
@@ -0,0 +1,81 @@
+From 78a53cd64db4002e9c9a4f46406e7182b3f3b934 Mon Sep 17 00:00:00 2001
+From: Patrick Yavitz <pyavitz@armbian.com>
+Date: Thu, 12 Dec 2024 06:49:59 -0500
+Subject: Add BananaPi BPI-M4-Zero pinctrl
+
+Signed-off-by: Patrick Yavitz <pyavitz@armbian.com>
+---
+ .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 36 +++++++++++++++++++
+ 1 file changed, 36 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+index 954c8eab2c44..004e824dfe0b 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+@@ -409,6 +409,12 @@ i2c0_pins: i2c0-pins {
+ 				function = "i2c0";
+ 			};
+ 
++			/omit-if-no-ref/
++			i2c1_pi_pins: i2c1-pi-pins {
++				pins = "PI7", "PI8";
++				function = "i2c1";
++			};
++
+ 			/omit-if-no-ref/
+ 			i2c2_ph_pins: i2c2-ph-pins {
+ 				pins = "PH2", "PH3";
+@@ -571,6 +577,12 @@ spi1_cs0_pin: spi1-cs0-pin {
+ 				function = "spi1";
+ 			};
+ 
++			/omit-if-no-ref/
++			spi1_cs1_pin: spi1-cs1-pin {
++				pins = "PH9";
++				function = "spi1";
++			};
++
+ 			spdif_tx_pin: spdif-tx-pin {
+ 				pins = "PH4";
+ 				function = "spdif";
+@@ -593,6 +605,12 @@ uart1_rts_cts_pins: uart1-rts-cts-pins {
+ 				function = "uart1";
+ 			};
+ 
++			/omit-if-no-ref/
++			uart2_pi_pins: uart2-pi-pins {
++				pins = "PI5", "PI6";
++				function = "uart2";
++			};
++
+ 			/omit-if-no-ref/
+ 			uart2_pg_pins: uart2-pg-pins {
+ 				pins = "PG15", "PG16";
+@@ -617,6 +635,24 @@ uart2_ph_rts_cts_pins: uart2-ph-rts-cts-pins {
+ 				function = "uart2";
+ 			};
+ 
++			/omit-if-no-ref/
++			uart3_pi_pins: uart3-pi-pins {
++				pins = "PI9", "PI10";
++				function = "uart3";
++			};
++
++			/omit-if-no-ref/
++			uart4_pi_pins: uart4-pi-pins {
++				pins = "PI13", "PI14";
++				function = "uart4";
++			};
++
++			/omit-if-no-ref/
++			uart4_pi_rts_cts_pins: uart4-pi-rts-cts-pins {
++				pins = "PI15", "PI16";
++				function = "uart4";
++			};
++
+ 			/omit-if-no-ref/
+ 			uart5_pins: uart5-pins {
+ 				pins = "PH2", "PH3";
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/Add-FB_TFT-ST7796S-driver.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/Add-FB_TFT-ST7796S-driver.patch
new file mode 100644
index 000000000000..7abbc213124b
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/Add-FB_TFT-ST7796S-driver.patch
@@ -0,0 +1,154 @@
+From 0987e0158d63711b01a2435fa515d80a5b540422 Mon Sep 17 00:00:00 2001
+From: Alan <Alan>
+Date: Sat, 20 May 2023 14:33:52 +0800
+Subject: Add: FB_TFT ST7796S driver
+
+---
+ drivers/staging/fbtft/Kconfig      |  10 +++
+ drivers/staging/fbtft/Makefile     |   1 +
+ drivers/staging/fbtft/fb_st7796s.c | 100 +++++++++++++++++++++++++++++
+ 3 files changed, 111 insertions(+)
+ create mode 100644 drivers/staging/fbtft/fb_st7796s.c
+
+diff --git a/drivers/staging/fbtft/Kconfig b/drivers/staging/fbtft/Kconfig
+index dcf6a70455cc..42fe4b73aa3f 100644
+--- a/drivers/staging/fbtft/Kconfig
++++ b/drivers/staging/fbtft/Kconfig
+@@ -169,6 +169,16 @@ config FB_TFT_ST7789V
+ 
+ 	  Say Y if you have such a display that utilizes this controller.
+ 
++config FB_TFT_ST7796S
++	tristate "FB driver for the ST7796S LCD Controller"
++	depends on FB_TFT
++	help
++	  This enables generic framebuffer support for the Sitronix ST7796S
++	  display controller. The controller is intended for small color
++	  displays with a resolution of up to 480x320 pixels.
++
++	  Say Y if you have such a display that utilizes this controller.
++
+ config FB_TFT_TINYLCD
+ 	tristate "FB driver for tinylcd.com display"
+ 	depends on FB_TFT
+diff --git a/drivers/staging/fbtft/Makefile b/drivers/staging/fbtft/Makefile
+index e9cdf0f0a7da..7b2098b8a1bd 100644
+--- a/drivers/staging/fbtft/Makefile
++++ b/drivers/staging/fbtft/Makefile
+@@ -31,6 +31,7 @@ obj-$(CONFIG_FB_TFT_SSD1331)     += fb_ssd1331.o
+ obj-$(CONFIG_FB_TFT_SSD1351)     += fb_ssd1351.o
+ obj-$(CONFIG_FB_TFT_ST7735R)     += fb_st7735r.o
+ obj-$(CONFIG_FB_TFT_ST7789V)     += fb_st7789v.o
++obj-$(CONFIG_FB_TFT_ST7796S)     += fb_st7796s.o
+ obj-$(CONFIG_FB_TFT_TINYLCD)     += fb_tinylcd.o
+ obj-$(CONFIG_FB_TFT_TLS8204)     += fb_tls8204.o
+ obj-$(CONFIG_FB_TFT_UC1611)      += fb_uc1611.o
+diff --git a/drivers/staging/fbtft/fb_st7796s.c b/drivers/staging/fbtft/fb_st7796s.c
+new file mode 100644
+index 000000000000..cad489cef595
+--- /dev/null
++++ b/drivers/staging/fbtft/fb_st7796s.c
+@@ -0,0 +1,100 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * FB driver for the ST7796S LCD Controller
++ *
++ * Copyright (c) 2023 Alan Ma
++ * Copyright (c) 2014 Petr Olivka
++ * Copyright (c) 2013 Noralf Tronnes
++ */
++
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/init.h>
++#include <linux/delay.h>
++#include <video/mipi_display.h>
++
++#include "fbtft.h"
++
++#define DRVNAME	"fb_st7796s"
++#define WIDTH		480
++#define HEIGHT		320
++
++static const s16 default_init_sequence[] = {
++	-1, 0xC0, 0x0C, 0x02,
++	-1, 0xC1, 0x44,
++	-1, 0xC5, 0x00, 0x16, 0x80,
++	-1, 0x36, 0x28,
++	/* Interface Mode Control */
++	-1, 0x3A, 0x55,
++	-1, 0XB0, 0x00,
++	/* Frame rate 70HZ */
++	-1, 0xB1, 0xB0,
++	-1, 0xB4, 0x02,
++	/* RGB/MCU Interface Control */
++	-1, 0xB6, 0x02, 0x02,
++	-1, 0xE9, 0x00,
++	-1, 0XF7, 0xA9, 0x51, 0x2C, 0x82,
++	/* SLP_OUT - Sleep out */
++	-1, MIPI_DCS_EXIT_SLEEP_MODE,
++	-2, 50,
++	/* DISP_ON */
++	-1, MIPI_DCS_SET_DISPLAY_ON,
++	-3
++};
++
++static void set_addr_win(struct fbtft_par *par, int xs, int ys, int xe, int ye)
++{
++	write_reg(par, MIPI_DCS_SET_COLUMN_ADDRESS,
++		  xs >> 8, xs & 0xff, xe >> 8, xe & 0xff);
++
++	write_reg(par, MIPI_DCS_SET_PAGE_ADDRESS,
++		  ys >> 8, ys & 0xff, ye >> 8, ye & 0xff);
++
++	write_reg(par, MIPI_DCS_WRITE_MEMORY_START);
++}
++
++static int set_var(struct fbtft_par *par)
++{
++	switch (par->info->var.rotate) {
++	case 270:
++		write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
++			  0x80 | (par->bgr << 3));
++		break;
++	case 180:
++		write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
++			  0xE0 | (par->bgr << 3));
++		break;
++	case 90:
++		write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
++			  0x40 | (par->bgr << 3));
++		break;
++	default:
++		write_reg(par, MIPI_DCS_SET_ADDRESS_MODE,
++			  0x20 | (par->bgr << 3));
++		break;
++	}
++
++	return 0;
++}
++
++static struct fbtft_display display = {
++	.regwidth = 8,
++	.width = WIDTH,
++	.height = HEIGHT,
++	.init_sequence = default_init_sequence,
++	.fbtftops = {
++		.set_addr_win = set_addr_win,
++		.set_var = set_var,
++	},
++};
++
++FBTFT_REGISTER_DRIVER(DRVNAME, "sitronix,st7796s", &display);
++
++MODULE_ALIAS("spi:" DRVNAME);
++MODULE_ALIAS("platform:" DRVNAME);
++MODULE_ALIAS("spi:st7796s");
++MODULE_ALIAS("platform:st7796s");
++
++MODULE_DESCRIPTION("FB driver for the ST7796S LCD Controller");
++MODULE_AUTHOR("Alan Ma");
++MODULE_LICENSE("GPL");
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/Add-board-BananaPi-BPI-M4-Zero.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/Add-board-BananaPi-BPI-M4-Zero.patch
new file mode 100644
index 000000000000..65bfb914773f
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/Add-board-BananaPi-BPI-M4-Zero.patch
@@ -0,0 +1,407 @@
+From 4c92bf1cdc05ee6b7426c2450e9dcd6ffebad533 Mon Sep 17 00:00:00 2001
+From: Patrick Yavitz <pyavitz@armbian.com>
+Date: Tue, 7 Jan 2025 06:58:55 -0500
+Subject: Add board BananaPi BPI-M4-Zero
+
+Signed-off-by: Patrick Yavitz <pyavitz@armbian.com>
+---
+ arch/arm64/boot/dts/allwinner/Makefile        |   1 +
+ .../sun50i-h618-bananapi-m4-zero.dts          | 110 ++++++++
+ .../allwinner/sun50i-h618-bananapi-m4.dtsi    | 256 ++++++++++++++++++
+ 3 files changed, 367 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h618-bananapi-m4-zero.dts
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h618-bananapi-m4.dtsi
+
+diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
+index 67f738f9b513..a676c57aad1d 100644
+--- a/arch/arm64/boot/dts/allwinner/Makefile
++++ b/arch/arm64/boot/dts/allwinner/Makefile
+@@ -59,6 +59,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-bigtreetech-cb1-emmc.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-bigtreetech-pi.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-orangepi-zero2.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-x96-mate.dtb
++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-bananapi-m4-zero.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-longanpi-3h.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-orangepi-zero2w.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-orangepi-zero3.dtb
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-bananapi-m4-zero.dts b/arch/arm64/boot/dts/allwinner/sun50i-h618-bananapi-m4-zero.dts
+new file mode 100644
+index 000000000000..46e07893c653
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-bananapi-m4-zero.dts
+@@ -0,0 +1,110 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2024 Patrick Yavitz <pyavitz@armbian.com>
++ */
++
++/dts-v1/;
++
++#include "sun50i-h618-bananapi-m4.dtsi"
++
++/ {
++	model = "BananaPi BPI-M4-Zero";
++	compatible = "sinovoip,bpi-m4-zero", "allwinner,sun50i-h618";
++
++	aliases {
++		ethernet0 = &emac1;
++		i2c0 = &i2c0;
++		i2c1 = &i2c1;
++		i2c3 = &i2c3;
++		i2c4 = &i2c4;
++		serial4 = &uart4;
++		serial5 = &uart5;
++		spi1 = &spi1;
++	};
++
++	leds {
++		compatible = "gpio-leds";
++
++		led-0 {
++			color = <LED_COLOR_ID_RED>;
++			function = LED_FUNCTION_STATUS;
++			gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>;	/* PC12 */
++			linux,default-trigger = "heartbeat";
++		};
++	};
++};
++
++/* Connected to an on-board RTL8821CU USB WiFi chip. */
++&ehci1 {
++	status = "okay";
++};
++
++&ehci2 {
++	status = "okay";
++};
++
++&ehci3 {
++	status = "okay";
++};
++
++&emac1 {
++	status = "disabled";
++	pinctrl-0 = <&ext_rgmii_pins>;
++	pinctrl-names = "default";
++	phy-mode = "rgmii";
++	phy-handle = <&ext_rgmii_phy>;
++	phy-supply = <&reg_dldo1>;
++	allwinner,rx-delay-ps = <3100>;
++	allwinner,tx-delay-ps = <700>;
++};
++
++&mdio1 {
++	ext_rgmii_phy: ethernet-phy@1 {
++		compatible = "ethernet-phy-ieee802.3-c22";
++		reg = <1>;
++	};
++};
++
++/* SDIO */
++&mmc1 {
++	status = "disabled";
++	bus-width = <4>;
++	max-frequency = <100000000>;
++
++	non-removable;
++	disable-wp;
++
++	/* WiFi firmware requires power to be kept while in suspend */
++	keep-power-in-suspend;
++
++	mmc-pwrseq = <&wifi_pwrseq>;
++
++	cd-gpios = <&pio 6 15 GPIO_ACTIVE_HIGH>; /* PG15 */
++	vmmc-supply = <&reg_vcc3v3>;
++
++	sdio: wifi@1 {
++		reg = <1>;
++		compatible = "brcm,bcm4329-fmac";
++	};
++};
++
++&ohci1 {
++	status = "okay";
++};
++
++&ohci2 {
++	status = "okay";
++};
++
++&ohci3 {
++	status = "okay";
++};
++
++&usbotg {
++	status = "okay";
++	dr_mode = "peripheral";
++};
++
++&usbphy {
++	status = "okay";
++};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-bananapi-m4.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h618-bananapi-m4.dtsi
+new file mode 100644
+index 000000000000..e9640439e02c
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-bananapi-m4.dtsi
+@@ -0,0 +1,256 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2024 Patrick Yavitz <pyavitz@armbian.com>
++ */
++
++/dts-v1/;
++
++#include "sun50i-h616.dtsi"
++#include "sun50i-h616-cpu-opp.dtsi"
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/linux-event-codes.h>
++#include <dt-bindings/interrupt-controller/arm-gic.h>
++#include <dt-bindings/leds/common.h>
++
++/ {
++	aliases {
++		serial0 = &uart0;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	connector {
++		compatible = "hdmi-connector";
++		type = "d";
++
++		port {
++			hdmi_con_in: endpoint {
++				remote-endpoint = <&hdmi_out_con>;
++			};
++		};
++	};
++
++	reg_usb_vbus: regulator-usb-vbus {
++		/* Separate discrete regulator for the USB ports */
++		compatible = "regulator-fixed";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		regulator-name = "usb-vbus";
++		vin-supply = <&reg_vcc5v>;
++	};
++
++	reg_vcc5v: regulator-vcc5v {
++		/* Board wide 5V supply directly from the USB-C socket */
++		compatible = "regulator-fixed";
++		regulator-always-on;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		regulator-name = "vcc-5v";
++	};
++
++	reg_vcc3v3: regulator-vcc3v3 {
++		compatible = "regulator-fixed";
++		regulator-always-on;
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		regulator-name = "vcc-3v3";
++		vin-supply = <&reg_vcc5v>;
++	};
++
++	reg_vcc1v8: regulator-vcc1v8 {
++		compatible = "regulator-fixed";
++		regulator-always-on;
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		regulator-name = "vcc-1v8";
++		vin-supply = <&reg_vcc3v3>;
++	};
++
++	wifi_pwrseq: wifi-pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		clocks = <&rtc CLK_OSC32K_FANOUT>;
++		clock-names = "ext_clock";
++		pinctrl-0 = <&x32clk_fanout_pin>;
++		pinctrl-names = "default";
++		post-power-on-delay-ms = <200>;
++		reset-gpios = <&pio 6 18 GPIO_ACTIVE_LOW>; /* PG18 */
++	};
++};
++
++&cpu0 {
++	cpu-supply = <&reg_dcdc2>;
++};
++
++&de {
++	status = "okay";
++};
++
++&gpu {
++	status = "disabled";
++	mali-supply = <&reg_dcdc1>;
++};
++
++&hdmi {
++	status = "okay";
++};
++
++&hdmi_out {
++	hdmi_out_con: endpoint {
++		remote-endpoint = <&hdmi_con_in>;
++	};
++};
++
++&i2c0 {
++	status = "disabled";
++	pinctrl-0 = <&i2c0_pins>;
++	pinctrl-names = "default";
++};
++
++&i2c1 {
++	status = "disabled";
++	pinctrl-0 = <&i2c1_pi_pins>;
++	pinctrl-names = "default";
++};
++
++&i2c3 {
++	status = "disabled";
++	pinctrl-0 = <&i2c3_pg_pins>;
++	pinctrl-names = "default";
++};
++
++&i2c4 {
++	status = "disabled";
++	pinctrl-0 = <&i2c4_pg_pins>;
++	pinctrl-names = "default";
++};
++
++&ir {
++	status = "disabled";
++	pinctrl-0 = <&ir_rx_pin>;
++	pinctrl-names = "default";
++};
++
++/* SD card */
++&mmc0 {
++	status = "okay";
++	bus-width = <4>;
++	max-frequency = <50000000>;
++
++	disable-wp;
++
++	cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;	/* PF6 */
++	vmmc-supply = <&reg_vcc3v3>;
++};
++
++/* eMMC */
++&mmc2 {
++	status = "okay";
++	bus-width = <8>;
++	cap-mmc-hw-reset;
++	mmc-hs200-1_8v;
++
++	non-removable;
++	disable-wp;
++
++	vmmc-supply = <&reg_vcc3v3>;
++	vqmmc-supply = <&reg_vcc1v8>;
++};
++
++&pio {
++	vcc-pc-supply = <&reg_aldo1>;
++	vcc-pf-supply = <&reg_dldo1>;
++	vcc-pg-supply = <&reg_dldo1>;
++	vcc-ph-supply = <&reg_dldo1>;
++	vcc-pi-supply = <&reg_dldo1>;
++};
++
++&r_i2c {
++	status = "okay";
++	axp313: pmic@36 {
++		compatible = "x-powers,axp313a";
++		reg = <0x36>;
++		#interrupt-cells = <1>;
++		interrupt-controller;
++		interrupt-parent = <&pio>;
++
++		vin1-supply = <&reg_vcc5v>;
++		vin2-supply = <&reg_vcc5v>;
++		vin3-supply = <&reg_vcc5v>;
++
++		regulators {
++			reg_aldo1: aldo1 {
++				regulator-always-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-name = "vcc-1v8-pll";
++			};
++
++			reg_dldo1: dldo1 {
++				regulator-always-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-name = "vcc-3v3-io";
++			};
++
++			reg_dcdc1: dcdc1 {
++				regulator-always-on;
++				regulator-min-microvolt = <810000>;
++				regulator-max-microvolt = <990000>;
++				regulator-name = "vdd-gpu-sys";
++			};
++
++			reg_dcdc2: dcdc2 {
++				regulator-always-on;
++				regulator-min-microvolt = <810000>;
++				regulator-max-microvolt = <1100000>;
++				regulator-name = "vdd-cpu";
++			};
++
++			reg_dcdc3: dcdc3 {
++				regulator-always-on;
++				regulator-min-microvolt = <1100000>;
++				regulator-max-microvolt = <1100000>;
++				regulator-name = "vdd-dram";
++			};
++		};
++	};
++};
++
++&spi1 {
++	status = "disabled";
++	pinctrl-0 = <&spi1_pins>, <&spi1_cs1_pin>;
++	pinctrl-names = "default";
++
++	spidev@1 {
++		compatible = "rohm,dh2228fv";
++		reg = <1>;
++		spi-max-frequency = <1000000>;
++	};
++};
++
++&uart0 {
++	status = "okay";
++	pinctrl-0 = <&uart0_ph_pins>;
++	pinctrl-names = "default";
++};
++
++&uart1 {
++	status = "disabled";
++	pinctrl-0 = <&uart1_pins>;
++	pinctrl-names = "default";
++};
++
++&uart4 {
++	status = "disabled";
++	pinctrl-0 = <&uart4_pi_pins>;
++	pinctrl-names = "default";
++};
++
++&uart5 {
++	status = "disabled";
++	pinctrl-0 = <&uart5_pins>;
++	pinctrl-names = "default";
++};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/Add-dump_reg-and-sunxi-sysinfo-drivers.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/Add-dump_reg-and-sunxi-sysinfo-drivers.patch
new file mode 100644
index 000000000000..3eebddb5a3ae
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/Add-dump_reg-and-sunxi-sysinfo-drivers.patch
@@ -0,0 +1,1548 @@
+From 0ebd4ab1a25d17cb321499d1ab328cd7d0efa033 Mon Sep 17 00:00:00 2001
+From: afaulkner420 <afaulkner420@gmail.com>
+Date: Fri, 25 Mar 2022 19:28:00 +0000
+Subject: Add dump_reg and sunxi-sysinfo drivers
+
+---
+ drivers/char/Kconfig                       |   2 +
+ drivers/char/Makefile                      |   2 +
+ drivers/char/dump_reg/Kconfig              |  21 +
+ drivers/char/dump_reg/Makefile             |   2 +
+ drivers/char/dump_reg/dump_reg.c           | 887 +++++++++++++++++++++
+ drivers/char/dump_reg/dump_reg.h           | 132 +++
+ drivers/char/dump_reg/dump_reg_misc.c      | 209 +++++
+ drivers/char/sunxi-sysinfo/Kconfig         |  10 +
+ drivers/char/sunxi-sysinfo/Makefile        |   5 +
+ drivers/char/sunxi-sysinfo/sunxi-sysinfo.c | 175 ++++
+ 10 files changed, 1445 insertions(+)
+ create mode 100644 drivers/char/dump_reg/Kconfig
+ create mode 100644 drivers/char/dump_reg/Makefile
+ create mode 100644 drivers/char/dump_reg/dump_reg.c
+ create mode 100644 drivers/char/dump_reg/dump_reg.h
+ create mode 100644 drivers/char/dump_reg/dump_reg_misc.c
+ create mode 100644 drivers/char/sunxi-sysinfo/Kconfig
+ create mode 100644 drivers/char/sunxi-sysinfo/Makefile
+ create mode 100644 drivers/char/sunxi-sysinfo/sunxi-sysinfo.c
+
+diff --git a/drivers/char/Kconfig b/drivers/char/Kconfig
+index 7c8dd0abcfdf..aaa164708947 100644
+--- a/drivers/char/Kconfig
++++ b/drivers/char/Kconfig
+@@ -133,6 +133,8 @@ config POWERNV_OP_PANEL
+ 	  If unsure, say M here to build it as a module called powernv-op-panel.
+ 
+ source "drivers/char/ipmi/Kconfig"
++source "drivers/char/sunxi-sysinfo/Kconfig"
++source "drivers/char/dump_reg/Kconfig"
+ 
+ config DS1620
+ 	tristate "NetWinder thermometer support"
+diff --git a/drivers/char/Makefile b/drivers/char/Makefile
+index e9b360cdc99a..3000e4bbde4e 100644
+--- a/drivers/char/Makefile
++++ b/drivers/char/Makefile
+@@ -10,6 +10,7 @@ obj-$(CONFIG_ATARI_DSP56K)	+= dsp56k.o
+ obj-$(CONFIG_VIRTIO_CONSOLE)	+= virtio_console.o
+ obj-$(CONFIG_UV_MMTIMER)	+= uv_mmtimer.o
+ obj-$(CONFIG_IBM_BSR)		+= bsr.o
++obj-$(CONFIG_ARCH_SUNXI)        += sunxi-sysinfo/
+ 
+ obj-$(CONFIG_PRINTER)		+= lp.o
+ 
+@@ -43,3 +44,4 @@ obj-$(CONFIG_PS3_FLASH)		+= ps3flash.o
+ obj-$(CONFIG_XILLYBUS_CLASS)	+= xillybus/
+ obj-$(CONFIG_POWERNV_OP_PANEL)	+= powernv-op-panel.o
+ obj-$(CONFIG_ADI)		+= adi.o
++obj-$(CONFIG_DUMP_REG)          += dump_reg/
+diff --git a/drivers/char/dump_reg/Kconfig b/drivers/char/dump_reg/Kconfig
+new file mode 100644
+index 000000000000..dbf24c59fd40
+--- /dev/null
++++ b/drivers/char/dump_reg/Kconfig
+@@ -0,0 +1,21 @@
++#
++# dump reg config.
++#
++
++config DUMP_REG
++	tristate "dump reg driver for sunxi platform"
++	default y
++	help
++	  Say y here if you want to support dump regs module.
++	  The dump regs module is used to dump regs of any devices
++	  if you want it, When in doubt, say "Y".
++
++config DUMP_REG_MISC
++	tristate "dump reg misc driver"
++	depends on DUMP_REG
++	default y
++	help
++	  Add misc driver support, you can use dump regs function
++	  via ("/sys/class/...") sysfs interface.
++	  When in doubt, say "Y".
++
+diff --git a/drivers/char/dump_reg/Makefile b/drivers/char/dump_reg/Makefile
+new file mode 100644
+index 000000000000..e953f413b128
+--- /dev/null
++++ b/drivers/char/dump_reg/Makefile
+@@ -0,0 +1,2 @@
++obj-$(CONFIG_DUMP_REG) += dump_reg.o
++obj-$(CONFIG_DUMP_REG_MISC) += dump_reg_misc.o
+diff --git a/drivers/char/dump_reg/dump_reg.c b/drivers/char/dump_reg/dump_reg.c
+new file mode 100644
+index 000000000000..f5d64c4af036
+--- /dev/null
++++ b/drivers/char/dump_reg/dump_reg.c
+@@ -0,0 +1,887 @@
++/*
++ * dump registers sysfs driver
++ *
++ * Copyright(c) 2015-2018 Allwinnertech Co., Ltd.
++ *      http://www.allwinnertech.com
++ *
++ * Author: Liugang <liugang@allwinnertech.com>
++ *         Xiafeng <xiafeng@allwinnertech.com>
++ *         Martin <wuyan@allwinnertech.com>
++ *         Lewis  <liuyu@allwinnertech.com>
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/device.h>
++#include <linux/err.h>
++#include <linux/kdev_t.h>
++#include <linux/clk.h>
++#include <linux/io.h>
++#include <linux/slab.h>
++#include <linux/miscdevice.h>
++#include <linux/seq_file.h>
++#include <linux/platform_device.h>
++#include <linux/sysfs.h>
++#include <linux/mod_devicetable.h>
++#include "dump_reg.h"
++
++/* the register and vaule to be test by dump_reg */
++static u32 test_addr;
++static u32 test_size;
++static struct class *dump_class;
++
++/* Access in byte mode ? 1: byte-mode, 0: word-mode */
++static unsigned int rw_byte_mode;
++
++/* for dump_reg class */
++static struct dump_addr dump_para;
++static struct write_group *wt_group;
++static struct compare_group *cmp_group;
++
++static u32 _read(void __iomem *vaddr)
++{
++	if (rw_byte_mode)
++		return (u32)readb(vaddr);
++	else
++		return readl(vaddr);
++}
++
++static void _write(u32 val, void __iomem *vaddr)
++{
++	if (rw_byte_mode)
++		writeb((u8)val, vaddr);
++	else
++		writel(val, vaddr);
++}
++
++static void __iomem *_io_remap(unsigned long paddr, size_t size)
++{
++	return ioremap(paddr, size);
++}
++
++static void _io_unmap(void __iomem *vaddr)
++{
++	iounmap(vaddr);
++}
++
++static void __iomem *_mem_remap(unsigned long paddr, size_t size)
++{
++	return (void __iomem *)phys_to_virt(paddr);
++}
++
++/*
++ * Convert a physical address (which is already mapped) to virtual address
++ */
++static void __iomem *_get_vaddr(struct dump_addr *dump_addr, unsigned long uaddr)
++{
++	unsigned long offset = uaddr - dump_addr->uaddr_start;
++	return (void __iomem *)(dump_addr->vaddr_start + offset);
++}
++
++const struct dump_struct dump_table[] = {
++	{
++		.addr_start = SUNXI_IO_PHYS_START,
++		.addr_end   = SUNXI_IO_PHYS_END,
++		.remap = _io_remap,
++		.unmap = _io_unmap,
++		.get_vaddr = _get_vaddr,
++		.read  = _read,
++		.write = _write,
++	},
++	{
++		.addr_start = SUNXI_PLAT_PHYS_START,
++		.addr_end   = SUNXI_PLAT_PHYS_END,
++		.remap = _mem_remap,
++		.unmap = NULL,
++		.get_vaddr = _get_vaddr,
++		.read  = _read,
++		.write = _write,
++	},
++#if defined(SUNXI_IOMEM_START)
++	{
++		.addr_start = SUNXI_IOMEM_START,
++		.addr_end   = SUNXI_IOMEM_END,
++		.remap = NULL,  /* .remap = NULL: uaddr is a virtual address */
++		.unmap = NULL,
++		.get_vaddr = _get_vaddr,
++		.read  = _read,
++		.write = _write,
++	},
++#endif
++	{
++		.addr_start = SUNXI_MEM_PHYS_START,
++		.addr_end   = SUNXI_MEM_PHYS_END,
++		.remap = NULL,  /* .remap = NULL: uaddr is a virtual address */
++		.unmap = NULL,
++		.get_vaddr = _get_vaddr,
++		.read  = _read,
++		.write = _write,
++	},
++};
++EXPORT_SYMBOL(dump_table);
++
++/**
++ * __addr_valid - check if @uaddr is valid.
++ * @uaddr: addr to judge.
++ *
++ * return index if @addr is valid, -ENXIO if not.
++ */
++int __addr_valid(unsigned long uaddr)
++{
++	int i;
++
++	for (i = 0; i < ARRAY_SIZE(dump_table); i++)
++		if (uaddr >= dump_table[i].addr_start &&
++		    uaddr <= dump_table[i].addr_end)
++			return i;
++	return -ENXIO;
++}
++EXPORT_SYMBOL(__addr_valid);
++
++/**
++ * __dump_regs_ex - dump a range of registers' value, copy to buf.
++ * @dump_addr: start and end address of registers.
++ * @buf: store the dump info.
++ * @buf_size: buf size
++ *
++ * return bytes written to buf, <=0 indicate err
++ */
++ssize_t __dump_regs_ex(struct dump_addr *dump_addr, char *buf, ssize_t buf_size)
++{
++	int index;
++	ssize_t cnt = 0;
++	unsigned long uaddr;
++	unsigned long remap_size;
++	const struct dump_struct *dump;
++
++	/* Make the address 4-bytes aligned */
++	dump_addr->uaddr_start &= (~0x3UL);
++	dump_addr->uaddr_end &= (~0x3UL);
++	remap_size = dump_addr->uaddr_end - dump_addr->uaddr_start + 4;
++
++	index = __addr_valid(dump_addr->uaddr_start);
++	if ((index < 0) || (index != __addr_valid(dump_addr->uaddr_end)) ||
++	    (buf == NULL)) {
++		pr_err("%s(): Invalid para: index=%d, start=0x%lx, end=0x%lx, buf=0x%p\n",
++		       __func__, index, dump_addr->uaddr_start, dump_addr->uaddr_end, buf);
++		return -EIO;
++	}
++
++	dump = &dump_table[index];
++	if (dump->remap) {
++		dump_addr->vaddr_start = dump->remap(dump_addr->uaddr_start, remap_size);
++		if (!dump_addr->vaddr_start) {
++			pr_err("%s(): remap failed\n", __func__);
++			return -EIO;
++		}
++	} else  /* if (dump->remap = NULL), then treat uaddr as a virtual address */
++		dump_addr->vaddr_start = (void __iomem *)dump_addr->uaddr_start;
++
++	if (dump_addr->uaddr_start == dump_addr->uaddr_end) {
++		cnt = sprintf(buf, "0x%08x\n", dump->read(dump_addr->vaddr_start));
++		goto out;
++	}
++
++	for (uaddr = (dump_addr->uaddr_start & ~0x0F); uaddr <= dump_addr->uaddr_end;
++	     uaddr += 4) {
++		if (!(uaddr & 0x0F))
++			cnt += snprintf(buf + cnt, buf_size - cnt,
++				     "\n" PRINT_ADDR_FMT ":", uaddr);
++
++		if (cnt >= buf_size) {
++			pr_warn("Range too large, strings buffer overflow\n");
++			cnt = buf_size;
++			goto out;
++		}
++
++		if (uaddr < dump_addr->uaddr_start)  /* Don't show unused uaddr */
++			/* "0x12345678 ", 11 space */
++			cnt += snprintf(buf + cnt, buf_size - cnt, "           ");
++		else
++			cnt += snprintf(buf + cnt, buf_size - cnt, " 0x%08x",
++				dump->read(dump->get_vaddr(dump_addr, uaddr)));
++	}
++	cnt += snprintf(buf + cnt, buf_size - cnt, "\n");
++
++	pr_debug("%s(): start=0x%lx, end=0x%lx, return=%zd\n", __func__,
++		 dump_addr->uaddr_start, dump_addr->uaddr_end, cnt);
++
++out:
++	if (dump->unmap)
++		dump->unmap(dump_addr->vaddr_start);
++
++	return cnt;
++}
++EXPORT_SYMBOL(__dump_regs_ex);
++
++/**
++ * __parse_dump_str - parse the input string for dump attri.
++ * @buf: the input string, eg: "0x01c20000,0x01c20300".
++ * @size: buf size.
++ * @start: store the start reg's addr parsed from buf, eg 0x01c20000.
++ * @end: store the end reg's addr parsed from buf, eg 0x01c20300.
++ *
++ * return 0 if success, otherwise failed.
++ */
++int __parse_dump_str(const char *buf, size_t size,
++			    unsigned long *start, unsigned long *end)
++{
++	char *ptr = NULL;
++	char *ptr2 = (char *)buf;
++	int ret = 0, times = 0;
++
++	/* Support single address mode, some time it haven't ',' */
++next:
++	/*
++	 * Default dump only one register(*start =*end).
++	 * If ptr is not NULL, we will cover the default value of end.
++	 */
++	if (times == 1)
++		*start = *end;
++
++	if (!ptr2 || (ptr2 - buf) >= size)
++		goto out;
++
++	ptr = ptr2;
++	ptr2 = strnchr(ptr, size - (ptr - buf), ',');
++	if (ptr2) {
++		*ptr2 = '\0';
++		ptr2++;
++	}
++
++	ptr = strim(ptr);
++	if (!strlen(ptr))
++		goto next;
++
++	ret = kstrtoul(ptr, 16, end);
++	if (!ret) {
++		times++;
++		goto next;
++	} else
++		pr_warn("String syntax errors: \"%s\"\n", ptr);
++
++out:
++	return ret;
++}
++EXPORT_SYMBOL(__parse_dump_str);
++
++/**
++ * __write_show - dump a register's value, copy to buf.
++ * @pgroup: the addresses to read.
++ * @buf: store the dump info.
++ *
++ * return bytes written to buf, <=0 indicate err.
++ */
++ssize_t __write_show(struct write_group *pgroup, char *buf, ssize_t len)
++{
++#define WR_DATA_FMT PRINT_ADDR_FMT"  0x%08x  %s"
++
++	int i = 0;
++	ssize_t cnt = 0;
++	unsigned long reg = 0;
++	u32 val;
++	u8 rval_buf[16];
++	struct dump_addr dump_addr;
++
++	if (!pgroup) {
++		pr_err("%s,%d err, pgroup is NULL!\n", __func__, __LINE__);
++		goto end;
++	}
++
++	cnt += snprintf(buf, len - cnt, WR_PRINT_FMT);
++	if (cnt > len) {
++		cnt = -EINVAL;
++		goto end;
++	}
++
++	for (i = 0; i < pgroup->num; i++) {
++		reg = pgroup->pitem[i].reg_addr;
++		val = pgroup->pitem[i].val;
++		dump_addr.uaddr_start = reg;
++		dump_addr.uaddr_end = reg;
++		if (__dump_regs_ex(&dump_addr, rval_buf, sizeof(rval_buf)) < 0)
++			return -EINVAL;
++
++		cnt +=
++		    snprintf(buf + cnt, len - cnt, WR_DATA_FMT, reg, val,
++			     rval_buf);
++		if (cnt > len) {
++			cnt = len;
++			goto end;
++		}
++	}
++
++end:
++	return cnt;
++}
++EXPORT_SYMBOL(__write_show);
++
++/**
++ * __parse_write_str - parse the input string for write attri.
++ * @str: string to be parsed, eg: "0x01c20818 0x55555555".
++ * @reg_addr: store the reg address. eg: 0x01c20818.
++ * @val: store the expect value. eg: 0x55555555.
++ *
++ * return 0 if success, otherwise failed.
++ */
++static int __parse_write_str(char *str, unsigned long *reg_addr, u32 *val)
++{
++	char *ptr = str;
++	char *tstr = NULL;
++	int ret = 0;
++
++	/*
++	 * Skip the leading whitespace, find the true split symbol.
++	 * And it must be 'address value'.
++	 */
++	tstr = strim(str);
++	ptr = strchr(tstr, ' ');
++	if (!ptr)
++		return -EINVAL;
++
++	/*
++	 * Replaced split symbol with a %NUL-terminator temporary.
++	 * Will be fixed at end.
++	 */
++	*ptr = '\0';
++	ret = kstrtoul(tstr, 16, reg_addr);
++	if (ret)
++		goto out;
++
++	ret = kstrtou32(skip_spaces(ptr + 1), 16, val);
++
++out:
++	return ret;
++}
++
++/**
++ * __write_item_init - init for write attri. parse input string,
++ *                     and construct write struct.
++ * @ppgroup: store the struct allocated, the struct contains items parsed from
++ *           input buf.
++ * @buf: input string, eg: "0x01c20800 0x00000031,0x01c20818 0x55555555,...".
++ * @size: buf size.
++ *
++ * return 0 if success, otherwise failed.
++ */
++int __write_item_init(struct write_group **ppgroup, const char *buf,
++			     size_t size)
++{
++	char *ptr, *ptr2;
++	unsigned long addr = 0;
++	u32 val;
++	struct write_group *pgroup;
++
++	/* alloc item buffer */
++	pgroup = kmalloc(sizeof(struct write_group), GFP_KERNEL);
++	if (!pgroup)
++		return -ENOMEM;
++
++	pgroup->pitem = kmalloc(sizeof(struct write_item) * MAX_WRITE_ITEM,
++				GFP_KERNEL);
++	if (!pgroup->pitem) {
++		kfree(pgroup);
++		return -ENOMEM;
++	}
++
++	pgroup->num = 0;
++	ptr = (char *)buf;
++	do {
++		ptr2 = strchr(ptr, ',');
++		if (ptr2)
++			*ptr2 = '\0';
++
++		if (!__parse_write_str(ptr, &addr, &val)) {
++			pgroup->pitem[pgroup->num].reg_addr = addr;
++			pgroup->pitem[pgroup->num].val = val;
++			pgroup->num++;
++		} else
++			pr_err("%s: Failed to parse string: %s\n", __func__,
++			       ptr);
++
++		if (!ptr2)
++			break;
++
++		ptr = ptr2 + 1;
++		*ptr2 = ',';
++
++	} while (pgroup->num <= MAX_WRITE_ITEM);
++
++	/* free buffer if no valid item */
++	if (pgroup->num == 0) {
++		kfree(pgroup->pitem);
++		kfree(pgroup);
++		return -EINVAL;
++	}
++
++	*ppgroup = pgroup;
++	return 0;
++}
++EXPORT_SYMBOL(__write_item_init);
++
++/**
++ * __write_item_deinit - reled_addrse memory that cred_addrted by
++ *                       __write_item_init.
++ * @pgroup: the write struct allocated in __write_item_init.
++ */
++void __write_item_deinit(struct write_group *pgroup)
++{
++	if (pgroup != NULL) {
++		if (pgroup->pitem != NULL)
++			kfree(pgroup->pitem);
++		kfree(pgroup);
++	}
++}
++EXPORT_SYMBOL(__write_item_deinit);
++
++/**
++ * __compare_regs_ex - dump a range of registers' value, copy to buf.
++ * @pgroup: addresses of registers.
++ * @buf: store the dump info.
++ *
++ * return bytes written to buf, <= 0 indicate err.
++ */
++ssize_t __compare_regs_ex(struct compare_group *pgroup, char *buf,
++				 ssize_t len)
++{
++#define CMP_DATAO_FMT PRINT_ADDR_FMT"  0x%08x  0x%08x  0x%08x  OK\n"
++#define CMP_DATAE_FMT PRINT_ADDR_FMT"  0x%08x  0x%08x  0x%08x  ERR\n"
++
++	int i;
++	ssize_t cnt = 0;
++	unsigned long reg;
++	u32 expect, actual, mask;
++	u8 actualb[16];
++	struct dump_addr dump_addr;
++
++	if (!pgroup) {
++		pr_err("%s,%d err, pgroup is NULL!\n", __func__, __LINE__);
++		goto end;
++	}
++
++	cnt += snprintf(buf, len - cnt, CMP_PRINT_FMT);
++	if (cnt > len) {
++		cnt = -EINVAL;
++		goto end;
++	}
++
++	for (i = 0; i < pgroup->num; i++) {
++		reg = pgroup->pitem[i].reg_addr;
++		expect = pgroup->pitem[i].val_expect;
++		dump_addr.uaddr_start = reg;
++		dump_addr.uaddr_end = reg;
++		if (__dump_regs_ex(&dump_addr, actualb, sizeof(actualb)) < 0)
++			return -EINVAL;
++
++		if (kstrtou32(actualb, 16, &actual))
++			return -EINVAL;
++
++		mask = pgroup->pitem[i].val_mask;
++		if ((actual & mask) == (expect & mask))
++			cnt +=
++			    snprintf(buf + cnt, len - cnt, CMP_DATAO_FMT, reg,
++				     expect, actual, mask);
++		else
++			cnt +=
++			    snprintf(buf + cnt, len - cnt, CMP_DATAE_FMT, reg,
++				     expect, actual, mask);
++		if (cnt > len) {
++			cnt = -EINVAL;
++			goto end;
++		}
++	}
++
++end:
++	return cnt;
++}
++EXPORT_SYMBOL(__compare_regs_ex);
++
++/**
++ * __parse_compare_str - parse the input string for compare attri.
++ * @str: string to be parsed, eg: "0x01c20000 0x80000011 0x00000011".
++ * @reg_addr: store the reg address. eg: 0x01c20000.
++ * @val_expect: store the expect value. eg: 0x80000011.
++ * @val_mask: store the mask value. eg: 0x00000011.
++ *
++ * return 0 if success, otherwise failed.
++ */
++static int __parse_compare_str(char *str, unsigned long *reg_addr,
++			       u32 *val_expect, u32 *val_mask)
++{
++	unsigned long result_addr[3] = { 0 };
++	char *ptr = str;
++	char *ptr2 = NULL;
++	int i, ret = 0;
++
++	for (i = 0; i < ARRAY_SIZE(result_addr); i++) {
++		ptr = skip_spaces(ptr);
++		ptr2 = strchr(ptr, ' ');
++		if (ptr2)
++			*ptr2 = '\0';
++
++		ret = kstrtoul(ptr, 16, &result_addr[i]);
++		if (!ptr2)
++			break;
++
++		*ptr2 = ' ';
++
++		if (ret)
++			break;
++
++		ptr = ptr2 + 1;
++	}
++
++	*reg_addr = result_addr[0];
++	*val_expect = (u32) result_addr[1];
++	*val_mask = (u32) result_addr[2];
++
++	return ret;
++}
++
++/**
++ * __compare_item_init - init for compare attri. parse input string,
++ *                       and construct compare struct.
++ * @ppgroup: store the struct allocated, the struct contains items parsed from
++ *           input buf.
++ * @buf: input string,
++ *  eg: "0x01c20000 0x80000011 0x00000011,0x01c20004 0x0000c0a4 0x0000c0a0,...".
++ * @size: buf size.
++ *
++ * return 0 if success, otherwise failed.
++ */
++int __compare_item_init(struct compare_group **ppgroup,
++			       const char *buf, size_t size)
++{
++	char *ptr, *ptr2;
++	unsigned long addr = 0;
++	u32 val_expect = 0, val_mask = 0;
++	struct compare_group *pgroup = NULL;
++
++	/* alloc item buffer */
++	pgroup = kmalloc(sizeof(struct compare_group), GFP_KERNEL);
++	if (pgroup == NULL)
++		return -EINVAL;
++
++	pgroup->pitem = kmalloc(sizeof(struct compare_item) * MAX_COMPARE_ITEM,
++				GFP_KERNEL);
++	if (pgroup->pitem == NULL) {
++		kfree(pgroup);
++		return -EINVAL;
++	}
++
++	pgroup->num = 0;
++
++	/* get item from buf */
++	ptr = (char *)buf;
++	do {
++		ptr2 = strchr(ptr, ',');
++		if (ptr2)
++			*ptr2 = '\0';
++
++		if (!__parse_compare_str(ptr, &addr, &val_expect, &val_mask)) {
++			pgroup->pitem[pgroup->num].reg_addr = addr;
++			pgroup->pitem[pgroup->num].val_expect = val_expect;
++			pgroup->pitem[pgroup->num].val_mask = val_mask;
++			pgroup->num++;
++		} else
++			pr_err("%s: Failed to parse string: %s\n", __func__,
++			       ptr);
++
++		if (!ptr2)
++			break;
++
++		*ptr2 = ',';
++		ptr = ptr2 + 1;
++
++	} while (pgroup->num <= MAX_COMPARE_ITEM);
++
++	/* free buffer if no valid item */
++	if (pgroup->num == 0) {
++		kfree(pgroup->pitem);
++		kfree(pgroup);
++		return -EINVAL;
++	}
++	*ppgroup = pgroup;
++
++	return 0;
++}
++EXPORT_SYMBOL(__compare_item_init);
++
++/**
++ * __compare_item_deinit - reled_addrse memory that cred_addrted by
++ *                         __compare_item_init.
++ * @pgroup: the compare struct allocated in __compare_item_init.
++ */
++void __compare_item_deinit(struct compare_group *pgroup)
++{
++	if (pgroup) {
++		kfree(pgroup->pitem);
++		kfree(pgroup);
++	}
++}
++EXPORT_SYMBOL(__compare_item_deinit);
++
++/**
++ * dump_show - show func of dump attribute.
++ * @dev: class ptr.
++ * @attr: attribute ptr.
++ * @buf: the input buf which contain the start and end reg.
++ *       eg: "0x01c20000,0x01c20100\n".
++ *
++ * return size written to the buf, otherwise failed.
++ */
++static ssize_t
++dump_show(const struct class *class, const struct class_attribute *attr, char *buf)
++{
++	return __dump_regs_ex(&dump_para, buf, PAGE_SIZE);
++}
++
++static ssize_t
++dump_store(const struct class *class, const struct class_attribute *attr,
++	   const char *buf, size_t count)
++{
++	int index;
++	unsigned long start_reg = 0;
++	unsigned long end_reg = 0;
++
++	if (__parse_dump_str(buf, count, &start_reg, &end_reg)) {
++		pr_err("%s,%d err, invalid para!\n", __func__, __LINE__);
++		goto err;
++	}
++
++	index = __addr_valid(start_reg);
++	if ((index < 0) || (index != __addr_valid(end_reg))) {
++		pr_err("%s,%d err, invalid para!\n", __func__, __LINE__);
++		goto err;
++	}
++
++	dump_para.uaddr_start = start_reg;
++	dump_para.uaddr_end = end_reg;
++	pr_debug("%s,%d, start_reg:" PRINT_ADDR_FMT ", end_reg:" PRINT_ADDR_FMT
++		 "\n", __func__, __LINE__, start_reg, end_reg);
++
++	return count;
++
++err:
++	dump_para.uaddr_start = 0;
++	dump_para.uaddr_end = 0;
++
++	return -EINVAL;
++}
++
++static ssize_t
++write_show(const struct class *class, const struct class_attribute *attr, char *buf)
++{
++	/* display write result */
++	return __write_show(wt_group, buf, PAGE_SIZE);
++}
++
++static ssize_t
++write_store(const struct class *class, const struct class_attribute *attr,
++	    const char *buf, size_t count)
++{
++	int i;
++	int index;
++	unsigned long reg;
++	u32 val;
++	const struct dump_struct *dump;
++	struct dump_addr dump_addr;
++
++	/* free if not NULL */
++	if (wt_group) {
++		__write_item_deinit(wt_group);
++		wt_group = NULL;
++	}
++
++	/* parse input buf for items that will be dumped */
++	if (__write_item_init(&wt_group, buf, count) < 0)
++		return -EINVAL;
++
++	/**
++	 * write reg
++	 * it is better if the regs been remaped and unmaped only once,
++	 * but we map everytime for the range between min and max address
++	 * maybe too large.
++	 */
++	for (i = 0; i < wt_group->num; i++) {
++		reg = wt_group->pitem[i].reg_addr;
++		dump_addr.uaddr_start = reg;
++		val = wt_group->pitem[i].val;
++		index = __addr_valid(reg);
++		dump = &dump_table[index];
++		if (dump->remap)
++			dump_addr.vaddr_start = dump->remap(reg, 4);
++		else
++			dump_addr.vaddr_start = (void __iomem *)reg;
++		dump->write(val, dump->get_vaddr(&dump_addr, reg));
++		if (dump->unmap)
++			dump->unmap(dump_addr.vaddr_start);
++	}
++
++	return count;
++}
++
++static ssize_t
++compare_show(const struct class *class, const struct class_attribute *attr, char *buf)
++{
++	/* dump the items */
++	return __compare_regs_ex(cmp_group, buf, PAGE_SIZE);
++}
++
++static ssize_t
++compare_store(const struct class *class, const struct class_attribute *attr,
++	      const char *buf, size_t count)
++{
++	/* free if struct not null */
++	if (cmp_group) {
++		__compare_item_deinit(cmp_group);
++		cmp_group = NULL;
++	}
++
++	/* parse input buf for items that will be dumped */
++	if (__compare_item_init(&cmp_group, buf, count) < 0)
++		return -EINVAL;
++
++	return count;
++}
++
++static ssize_t
++rw_byte_show(const struct class *class, const struct class_attribute *attr, char *buf)
++{
++	return sprintf(buf, "read/write mode: %u(%s)\n", rw_byte_mode,
++		       rw_byte_mode ? "byte" : "word");
++}
++
++static ssize_t
++rw_byte_store(const struct class *class, const struct class_attribute *attr,
++	      const char *buf, size_t count)
++{
++	unsigned long value;
++	int ret;
++
++	ret = kstrtoul(buf, 10, &value);
++	if (!ret && (value > 1)) {
++		pr_err("%s,%d err, invalid para!\n", __func__, __LINE__);
++		goto out;
++	}
++	rw_byte_mode = value;
++out:
++	return count;
++}
++
++static ssize_t
++test_show(const struct class *class, const struct class_attribute *attr, char *buf)
++{
++	return sprintf(buf, "addr:0x%08x\nsize:0x%08x\n", test_addr, test_size);
++}
++
++static ssize_t
++help_show(const struct class *class, const struct class_attribute *attr, char *buf)
++{
++	const char *info =
++		"dump single register:          echo {addr} > dump; cat dump\n"
++		"dump multi  registers:         echo {start-addr},{end-addr} > dump; cat dump\n"
++		"write single register:         echo {addr} {val} > write; cat write\n"
++		"write multi  registers:        echo {addr1} {val1},{addr2} {val2},... > write; cat write\n"
++		"compare single register:       echo {addr} {expect-val} {mask} > compare; cat compare\n"
++		"compare multi  registers:      echo {addr1} {expect-val1} {mask1},{addr2} {expect-val2} {mask2},... > compare; cat compare\n"
++		"byte-access mode:              echo 1 > rw_byte\n"
++		"word-access mode (default):    echo 0 > rw_byte\n"
++		"show test address info:        cat test\n";
++	return sprintf(buf, info);
++}
++
++static struct class_attribute dump_class_attrs[] = {
++	__ATTR(dump,     S_IWUSR | S_IRUGO, dump_show,     dump_store),
++	__ATTR(write,    S_IWUSR | S_IRUGO, write_show,    write_store),
++	__ATTR(compare,  S_IWUSR | S_IRUGO, compare_show,  compare_store),
++	__ATTR(rw_byte,  S_IWUSR | S_IRUGO, rw_byte_show,  rw_byte_store),
++	__ATTR(test,     S_IRUGO,           test_show, NULL),
++	__ATTR(help,     S_IRUGO,           help_show, NULL),
++};
++
++static const struct of_device_id sunxi_dump_reg_match[] = {
++	{.compatible = "allwinner,sunxi-dump-reg", },
++	{}
++};
++MODULE_DEVICE_TABLE(of, sunxi_dump_reg_match);
++
++static int sunxi_dump_reg_probe(struct platform_device *pdev)
++{
++	struct resource *res;
++	struct device *dev = &pdev->dev;
++
++	int err;
++	int i;
++
++	/* sys/class/sunxi_dump */
++	dump_class = class_create("sunxi_dump");
++	if (IS_ERR(dump_class)) {
++		pr_err("%s:%u class_create() failed\n", __func__, __LINE__);
++		return PTR_ERR(dump_class);
++	}
++
++	/* sys/class/sunxi_dump/xxx */
++	for (i = 0; i < ARRAY_SIZE(dump_class_attrs); i++) {
++		err = class_create_file(dump_class, &dump_class_attrs[i]);
++		if (err) {
++			pr_err("%s:%u class_create_file() failed. err=%d\n", __func__, __LINE__, err);
++			while (i--) {
++				class_remove_file(dump_class, &dump_class_attrs[i]);
++			}
++			class_destroy(dump_class);
++			dump_class = NULL;
++			return err;
++		}
++	}
++
++	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++	if (!res) {
++		dev_err(dev, "Fail to get IORESOURCE_MEM \n");
++		goto error;
++	}
++
++	test_addr = res->start;
++	test_size = resource_size(res);
++
++	return 0;
++error:
++	dev_err(dev, "sunxi_dump_reg probe error\n");
++	return -1;
++}
++
++static void sunxi_dump_reg_remove(struct platform_device *pdev)
++{
++	int i;
++
++	for (i = 0; i < ARRAY_SIZE(dump_class_attrs); i++) {
++		class_remove_file(dump_class, &dump_class_attrs[i]);
++	}
++
++	class_destroy(dump_class);
++}
++
++static struct platform_driver sunxi_dump_reg_driver = {
++	.probe  = sunxi_dump_reg_probe,
++	.remove = sunxi_dump_reg_remove,
++	.driver = {
++		.name   = "dump_reg",
++		.owner  = THIS_MODULE,
++		.of_match_table = sunxi_dump_reg_match,
++	},
++};
++
++module_platform_driver(sunxi_dump_reg_driver);
++
++MODULE_ALIAS("dump reg driver");
++MODULE_ALIAS("platform:dump reg");
++MODULE_LICENSE("GPL v2");
++MODULE_VERSION("1.0.3");
++MODULE_AUTHOR("xiafeng <xiafeng@allwinnertech.com>");
++MODULE_AUTHOR("Martin <wuyan@allwinnertech.com>");
++MODULE_AUTHOR("liuyu <SWCliuyus@allwinnertech.com>");
++MODULE_DESCRIPTION("dump registers driver");
+diff --git a/drivers/char/dump_reg/dump_reg.h b/drivers/char/dump_reg/dump_reg.h
+new file mode 100644
+index 000000000000..85af5c96ed50
+--- /dev/null
++++ b/drivers/char/dump_reg/dump_reg.h
+@@ -0,0 +1,132 @@
++/*
++ * dump registers head file
++ *
++ * (C) Copyright 2015-2018
++ * Reuuimlla Technology Co., Ltd. <www.reuuimllatech.com>
++ * Liugang <liugang@reuuimllatech.com>
++ * Xiafeng <xiafeng@allwinnertech.com>
++ * Martin  <wuyan@allwinnertech.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ */
++#ifndef _DUMP_REG_H_
++#define _DUMP_REG_H_
++
++/* BROM/SRAM/peripheral-registers space */
++#define SUNXI_IO_PHYS_START		(0x01000000UL)
++#define SUNXI_IO_PHYS_END		(SUNXI_IO_PHYS_START + SZ_128M + SZ_16M -1)
++
++/* DRAM space (Only map the first 1GB) */
++#define SUNXI_PLAT_PHYS_START		(0x40000000UL)
++#define SUNXI_PLAT_PHYS_END		(SUNXI_PLAT_PHYS_START + SZ_1G - 1)
++
++#if IS_ENABLED(CONFIG_ARM64)
++/* Virtual address space 1 */
++#define SUNXI_IOMEM_START		(0xffffff8000000000UL)
++#define SUNXI_IOMEM_END			(SUNXI_IOMEM_START + SZ_2G)
++/* Virtual address space 2 */
++#define SUNXI_MEM_PHYS_START		(0xffffffc000000000UL)
++#define SUNXI_MEM_PHYS_END		(SUNXI_MEM_PHYS_START + SZ_2G)
++/* Print format */
++#define PRINT_ADDR_FMT			"0x%016lx"
++#define CMP_PRINT_FMT                   "reg                 expect      actual      mask        result\n"
++#define WR_PRINT_FMT                    "reg                 to_write    after_write\n"
++#else
++/* Virtual address space 2 */
++#define SUNXI_MEM_PHYS_START		PAGE_OFFSET
++#define SUNXI_MEM_PHYS_END		(SUNXI_MEM_PHYS_START + SZ_1G - 1)
++/* Print format */
++#define PRINT_ADDR_FMT			"0x%08lx"
++#define CMP_PRINT_FMT                   "reg         expect      actual      mask        result\n"
++#define WR_PRINT_FMT                    "reg         to_write    after_write\n"
++#endif
++
++/* Item count */
++#define MAX_COMPARE_ITEM		64
++#define MAX_WRITE_ITEM			64
++
++struct dump_addr {
++	/* User specified address. Maybe physical or virtual address */
++	unsigned long uaddr_start;
++	unsigned long uaddr_end;
++	/* Virtual address */
++	void __iomem *vaddr_start;
++};
++
++struct dump_struct {
++	unsigned long addr_start;
++	unsigned long addr_end;
++	/* some registers' operate method maybe different */
++	void __iomem *(*remap)(unsigned long paddr, size_t size);
++	void (*unmap)(void __iomem *vaddr);
++	void __iomem *(*get_vaddr)(struct dump_addr *dump_addr, unsigned long uaddr);
++	 u32 (*read)(void __iomem *vaddr);
++	void (*write)(u32 val, void __iomem *vaddr);
++};
++
++/**
++ * compare_item - reg compare item struct
++ * @reg_addr:	reg address.
++ * @val_expect: expected value, provided by caller.
++ * @val_mask:   mask value, provided by caller. only mask bits will be compared.
++ */
++struct compare_item {
++	unsigned long reg_addr;
++	u32	val_expect;
++	u32	val_mask;
++};
++
++/**
++ * compare_group - reg compare group struct
++ * @num:	pitem element count. cannot exceed MAX_COMPARE_ITEM.
++ * @pitem:	items that will be compared, provided by caller.
++ */
++struct compare_group {
++	u32	num;
++	u32	reserve;
++	struct compare_item *pitem;
++};
++
++/**
++ * write_item - reg write item struct
++ * @reg_addr:	reg address.
++ * @val:	value to write
++ */
++struct write_item {
++	unsigned long reg_addr;
++	u32	val;
++	u32	reserve;
++};
++
++/**
++ * write_group - reg write group struct
++ * @num:	pitem element count. cannot exceed MAX_WRITE_ITEM.
++ * @pitem:	items that will be write, provided by caller.
++ */
++struct write_group {
++	u32	num;
++	u32	reserve;
++	struct write_item *pitem;
++};
++
++extern const struct dump_struct dump_table[4];
++
++int __addr_valid(unsigned long addr);
++ssize_t __dump_regs_ex(struct dump_addr *reg, char *buf, ssize_t len);
++int __parse_dump_str(const char *buf, size_t size,
++						unsigned long *start, unsigned long *end);
++ssize_t __write_show(struct write_group *pgroup, char *buf, ssize_t len);
++int  __write_item_init(struct write_group **ppgroup, const char *buf,
++						size_t size);
++void __write_item_deinit(struct write_group *pgroup);
++ssize_t __compare_regs_ex(struct compare_group *pgroup, char *buf,
++							ssize_t len);
++int  __compare_item_init(struct compare_group **ppgroup,
++						const char *buf, size_t size);
++void __compare_item_deinit(struct compare_group *pgroup);
++
++#endif /* _DUMP_REG_H_ */
+diff --git a/drivers/char/dump_reg/dump_reg_misc.c b/drivers/char/dump_reg/dump_reg_misc.c
+new file mode 100644
+index 000000000000..238ddd147533
+--- /dev/null
++++ b/drivers/char/dump_reg/dump_reg_misc.c
+@@ -0,0 +1,209 @@
++/*
++ * misc dump registers driver -
++ * User space application could use dump-reg functions through file operations
++ * (open/read/write/close) to the sysfs node created by this driver.
++ *
++ * Copyright(c) 2015-2018 Allwinnertech Co., Ltd.
++ *      http://www.allwinnertech.com
++ *
++ * Author: Liugang <liugang@allwinnertech.com>
++ *         Xiafeng <xiafeng@allwinnertech.com>
++ *         Martin  <wuyan@allwinnertech.com>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/device.h>
++#include <linux/err.h>
++#include <linux/kdev_t.h>
++#include <linux/clk.h>
++#include <linux/io.h>
++#include <linux/slab.h>
++#include <linux/miscdevice.h>
++#include <linux/seq_file.h>
++#include "dump_reg.h"
++
++/* for dump_reg misc driver */
++static struct dump_addr misc_dump_para;
++static struct write_group *misc_wt_group;
++static struct compare_group *misc_cmp_group;
++
++static ssize_t
++misc_dump_show(struct device *dev, struct device_attribute *attr, char *buf)
++{
++	return __dump_regs_ex(&misc_dump_para, buf, PAGE_SIZE);
++}
++
++static ssize_t
++misc_dump_store(struct device *dev, struct device_attribute *attr,
++		const char *buf, size_t size)
++{
++	int index;
++	unsigned long start_reg = 0;
++	unsigned long end_reg = 0;
++
++	if (__parse_dump_str(buf, size, &start_reg, &end_reg)) {
++		pr_err("%s,%d err, invalid para!\n", __func__, __LINE__);
++		goto err;
++	}
++
++	index = __addr_valid(start_reg);
++	if ((index < 0) || (index != __addr_valid(end_reg))) {
++		pr_err("%s,%d err, invalid para!\n", __func__, __LINE__);
++		goto err;
++	}
++
++	misc_dump_para.uaddr_start = start_reg;
++	misc_dump_para.uaddr_end = end_reg;
++	pr_debug("%s,%d, start_reg:" PRINT_ADDR_FMT ", end_reg:" PRINT_ADDR_FMT
++		 "\n", __func__, __LINE__, start_reg, end_reg);
++
++	return size;
++
++err:
++	misc_dump_para.uaddr_start = 0;
++	misc_dump_para.uaddr_end = 0;
++
++	return -EINVAL;
++}
++
++static ssize_t
++misc_write_show(struct device *dev, struct device_attribute *attr, char *buf)
++{
++	/* display write result */
++	return __write_show(misc_wt_group, buf, PAGE_SIZE);
++}
++
++static ssize_t
++misc_write_store(struct device *dev, struct device_attribute *attr,
++		 const char *buf, size_t size)
++{
++	int i;
++	int index;
++	unsigned long reg;
++	u32 val;
++	const struct dump_struct *dump;
++	struct dump_addr dump_addr;
++
++	/* free if not NULL */
++	if (misc_wt_group) {
++		__write_item_deinit(misc_wt_group);
++		misc_wt_group = NULL;
++	}
++
++	/* parse input buf for items that will be dumped */
++	if (__write_item_init(&misc_wt_group, buf, size) < 0)
++		return -EINVAL;
++
++	/**
++	 * write reg
++	 * it is better if the regs been remaped and unmaped only once,
++	 * but we map everytime for the range between min and max address
++	 * maybe too large.
++	 */
++	for (i = 0; i < misc_wt_group->num; i++) {
++		reg = misc_wt_group->pitem[i].reg_addr;
++		dump_addr.uaddr_start = reg;
++		val = misc_wt_group->pitem[i].val;
++		index = __addr_valid(reg);
++		dump = &dump_table[index];
++		if (dump->remap)
++			dump_addr.vaddr_start = dump->remap(reg, 4);
++		else
++			dump_addr.vaddr_start = (void __iomem *)reg;
++		dump->write(val, dump->get_vaddr(&dump_addr, reg));
++		if (dump->unmap)
++			dump->unmap(dump_addr.vaddr_start);
++	}
++
++	return size;
++}
++
++static ssize_t
++misc_compare_show(struct device *dev, struct device_attribute *attr, char *buf)
++{
++	/* dump the items */
++	return __compare_regs_ex(misc_cmp_group, buf, PAGE_SIZE);
++}
++
++static ssize_t
++misc_compare_store(struct device *dev, struct device_attribute *attr,
++		   const char *buf, size_t size)
++{
++	/* free if struct not null */
++	if (misc_cmp_group) {
++		__compare_item_deinit(misc_cmp_group);
++		misc_cmp_group = NULL;
++	}
++
++	/* parse input buf for items that will be dumped */
++	if (__compare_item_init(&misc_cmp_group, buf, size) < 0)
++		return -EINVAL;
++
++	return size;
++}
++
++static DEVICE_ATTR(dump, S_IWUSR | S_IRUGO, misc_dump_show, misc_dump_store);
++static DEVICE_ATTR(write, S_IWUSR | S_IRUGO, misc_write_show, misc_write_store);
++static DEVICE_ATTR(compare, S_IWUSR | S_IRUGO, misc_compare_show,
++		   misc_compare_store);
++
++static struct attribute *misc_attributes[] = {  /* files under '/sys/devices/virtual/misc/sunxi-reg/rw/' */
++	&dev_attr_dump.attr,
++	&dev_attr_write.attr,
++	&dev_attr_compare.attr,
++	NULL,
++};
++
++static struct attribute_group misc_attribute_group = {
++	.name = "rw",  /* directory: '/sys/devices/virtual/misc/sunxi-reg/rw/' */
++	.attrs = misc_attributes,
++};
++
++static struct miscdevice dump_reg_dev = {
++	.minor = MISC_DYNAMIC_MINOR,
++	.name = "sunxi-reg",  /* device node: '/dev/sunxi-reg' */
++};
++
++static int __init misc_dump_reg_init(void)
++{
++	int err;
++
++	pr_info("misc dump reg init\n");
++	err = misc_register(&dump_reg_dev);
++	if (err) {
++		pr_err("dump register driver as misc device error!\n");
++		goto exit;
++	}
++
++	err = sysfs_create_group(&dump_reg_dev.this_device->kobj,
++				 &misc_attribute_group);
++	if (err)
++		pr_err("dump register sysfs create group failed!\n");
++
++exit:
++	return err;
++}
++
++static void __exit misc_dump_reg_exit(void)
++{
++	pr_info("misc dump reg exit\n");
++
++	sysfs_remove_group(&(dump_reg_dev.this_device->kobj),
++			   &misc_attribute_group);
++	misc_deregister(&dump_reg_dev);
++}
++
++module_init(misc_dump_reg_init);
++module_exit(misc_dump_reg_exit);
++
++MODULE_ALIAS("misc dump reg driver");
++MODULE_LICENSE("GPL v2");
++MODULE_VERSION("1.0.1");
++MODULE_AUTHOR("xiafeng <xiafeng@allwinnertech.com>");
++MODULE_DESCRIPTION("misc dump registers driver");
+diff --git a/drivers/char/sunxi-sysinfo/Kconfig b/drivers/char/sunxi-sysinfo/Kconfig
+new file mode 100644
+index 000000000000..9b6e2f06d708
+--- /dev/null
++++ b/drivers/char/sunxi-sysinfo/Kconfig
+@@ -0,0 +1,10 @@
++#
++# sunxi system information driver.
++#
++
++config SUNXI_SYS_INFO
++	tristate "sunxi system info driver"
++	default y
++	help
++	  This driver is used for query system information.
++	  If you don't know whether need it, please select y.
+diff --git a/drivers/char/sunxi-sysinfo/Makefile b/drivers/char/sunxi-sysinfo/Makefile
+new file mode 100644
+index 000000000000..188696592114
+--- /dev/null
++++ b/drivers/char/sunxi-sysinfo/Makefile
+@@ -0,0 +1,5 @@
++#
++# Makefile for sunxi system information driver
++#
++
++obj-$(CONFIG_SUNXI_SYS_INFO) += sunxi-sysinfo.o
+diff --git a/drivers/char/sunxi-sysinfo/sunxi-sysinfo.c b/drivers/char/sunxi-sysinfo/sunxi-sysinfo.c
+new file mode 100644
+index 000000000000..21f59363cabf
+--- /dev/null
++++ b/drivers/char/sunxi-sysinfo/sunxi-sysinfo.c
+@@ -0,0 +1,175 @@
++/*
++ * Based on drivers/char/sunxi-sysinfo/sunxi-sysinfo.c
++ *
++ * Copyright (C) 2015 Allwinnertech Ltd.
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License version 2 as
++ * published by the Free Software Foundation.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
++ */
++
++#include <linux/module.h>
++#include <linux/printk.h>
++#include <linux/kernel.h>
++#include <linux/device.h>
++#include <linux/vmalloc.h>
++#include <linux/uaccess.h>
++#include <linux/fs.h>
++#include <linux/miscdevice.h>
++#include <linux/compat.h>
++#include <linux/platform_device.h>
++#include <linux/of_platform.h>
++#include <linux/of.h>
++
++extern int sunxi_get_soc_chipid(unsigned char *chipid);
++extern int sunxi_get_serial(unsigned  char *serial);
++
++struct sunxi_info_quirks {
++	char * platform_name;
++};
++
++static const struct sunxi_info_quirks sun5i_h6_info_quirks = {
++	.platform_name  = "sun50i-h6",
++};
++
++static const struct sunxi_info_quirks sun5i_h616_info_quirks = {
++	.platform_name  = "sun50i-h616",
++};
++
++struct sunxi_info_quirks *quirks;
++
++static int soc_info_open(struct inode *inode, struct file *file)
++{
++	return 0;
++}
++
++static int soc_info_release(struct inode *inode, struct file *file)
++{
++	return 0;
++}
++
++static const struct file_operations soc_info_ops = {
++	.owner   = THIS_MODULE,
++	.open    = soc_info_open,
++	.release = soc_info_release,
++};
++
++struct miscdevice soc_info_device = {
++	.minor = MISC_DYNAMIC_MINOR,
++	.name  = "sunxi_soc_info",
++	.fops  = &soc_info_ops,
++};
++
++static ssize_t sys_info_show(const struct class *class,
++			     const struct class_attribute *attr, char *buf)
++{
++	int i;
++	int databuf[4] = {0};
++	char tmpbuf[129] = {0};
++	size_t size = 0;
++
++	/* platform */
++	size += sprintf(buf + size, "sunxi_platform    : %s\n", quirks->platform_name);
++
++	/* chipid */
++	sunxi_get_soc_chipid((u8 *)databuf);
++
++	for (i = 0; i < 4; i++)
++		sprintf(tmpbuf + i*8, "%08x", databuf[i]);
++	tmpbuf[128] = 0;
++	size += sprintf(buf + size, "sunxi_chipid      : %s\n", tmpbuf);
++
++	/* serial */
++	sunxi_get_serial((u8 *)databuf);
++	for (i = 0; i < 4; i++)
++		sprintf(tmpbuf + i*8, "%08x", databuf[i]);
++	tmpbuf[128] = 0;
++	size += sprintf(buf + size, "sunxi_serial      : %s\n", tmpbuf);
++
++	return size;
++}
++
++static struct class_attribute info_class_attrs[] = {
++	__ATTR(sys_info, 0644, sys_info_show, NULL),
++};
++
++static struct class info_class = {
++	.name           = "sunxi_info",
++};
++
++static const struct of_device_id sunxi_info_match[] = {
++        {
++		.compatible = "allwinner,sun50i-h6-sys-info",
++		.data = &sun5i_h6_info_quirks,
++        },
++        {
++		.compatible = "allwinner,sun50i-h616-sys-info",
++		.data = &sun5i_h616_info_quirks,
++        },
++        {}
++};
++
++static int sunxi_info_probe(struct platform_device *pdev)
++{
++	int i, ret = 0;
++
++	quirks = of_device_get_match_data(&pdev->dev);
++	if (quirks == NULL) {
++		dev_err(&pdev->dev, "Failed to determine the quirks to use\n");
++		return -ENODEV;
++	}
++
++	ret = class_register(&info_class);
++	if (ret != 0)
++		return ret;
++
++	/* need some class specific sysfs attributes */
++	for (i = 0; i < ARRAY_SIZE(info_class_attrs); i++) {
++		ret = class_create_file(&info_class, &info_class_attrs[i]);
++		if (ret)
++			goto out_class_create_file_failed;
++	}
++
++	ret = misc_register(&soc_info_device);
++	if (ret != 0) {
++		pr_err("%s: misc_register() failed!(%d)\n", __func__, ret);
++		class_unregister(&info_class);
++		return ret;
++	}
++
++	return ret;
++
++out_class_create_file_failed:
++	class_unregister(&info_class);
++
++	return ret;
++}
++
++static void sunxi_info_remove(struct platform_device *pdev)
++{
++	misc_deregister(&soc_info_device);
++	class_unregister(&info_class);
++}
++
++static struct platform_driver sunxi_info_driver = {
++        .probe  = sunxi_info_probe,
++        .remove = sunxi_info_remove,
++        .driver = {
++                .name   = "sunxi_info",
++                .owner  = THIS_MODULE,
++                .of_match_table = sunxi_info_match,
++        },
++};
++module_platform_driver(sunxi_info_driver);
++
++MODULE_LICENSE("GPL v2");
++MODULE_AUTHOR("xiafeng<xiafeng@allwinnertech.com>");
++MODULE_DESCRIPTION("sunxi sys info.");
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/Add-sunxi-addr-driver-Used-to-fix-uwe5622-bluetooth-MAC-address.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/Add-sunxi-addr-driver-Used-to-fix-uwe5622-bluetooth-MAC-address.patch
new file mode 100644
index 000000000000..e0e84561d038
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/Add-sunxi-addr-driver-Used-to-fix-uwe5622-bluetooth-MAC-address.patch
@@ -0,0 +1,609 @@
+From a69f9a8b101b90606e01282a52262b129156f329 Mon Sep 17 00:00:00 2001
+From: afaulkner420 <afaulkner420@gmail.com>
+Date: Fri, 25 Mar 2022 20:18:18 +0000
+Subject: Add sunxi-addr driver - Used to fix uwe5622 bluetooth MAC addresses
+
+---
+ drivers/misc/Kconfig                 |   1 +
+ drivers/misc/Makefile                |   1 +
+ drivers/misc/sunxi-addr/Kconfig      |   6 +
+ drivers/misc/sunxi-addr/Makefile     |   5 +
+ drivers/misc/sunxi-addr/sha256.c     | 178 ++++++++++++++
+ drivers/misc/sunxi-addr/sunxi-addr.c | 356 +++++++++++++++++++++++++++
+ 6 files changed, 547 insertions(+)
+ create mode 100644 drivers/misc/sunxi-addr/Kconfig
+ create mode 100644 drivers/misc/sunxi-addr/Makefile
+ create mode 100644 drivers/misc/sunxi-addr/sha256.c
+ create mode 100644 drivers/misc/sunxi-addr/sunxi-addr.c
+
+diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
+index c0efb3129661..7a7a8eaba0ef 100644
+--- a/drivers/misc/Kconfig
++++ b/drivers/misc/Kconfig
+@@ -656,4 +656,5 @@ source "drivers/misc/uacce/Kconfig"
+ source "drivers/misc/pvpanic/Kconfig"
+ source "drivers/misc/mchp_pci1xxxx/Kconfig"
+ source "drivers/misc/keba/Kconfig"
++source "drivers/misc/sunxi-addr/Kconfig"
+ endmenu
+diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
+index 9b20ffa44835..cd8ba3232581 100644
+--- a/drivers/misc/Makefile
++++ b/drivers/misc/Makefile
+@@ -76,3 +76,4 @@ lan966x-pci-objs		+= lan966x_pci.dtbo.o
+ obj-$(CONFIG_MCHP_LAN966X_PCI)	+= lan966x-pci.o
+ obj-y				+= keba/
+ obj-$(CONFIG_MODEM_POWER)	+= modem-power.o
++obj-$(CONFIG_SUNXI_ADDR_MGT)    += sunxi-addr/
+diff --git a/drivers/misc/sunxi-addr/Kconfig b/drivers/misc/sunxi-addr/Kconfig
+new file mode 100644
+index 000000000000..801dd2c02a56
+--- /dev/null
++++ b/drivers/misc/sunxi-addr/Kconfig
+@@ -0,0 +1,6 @@
++config SUNXI_ADDR_MGT
++  tristate "Allwinner Network MAC Addess Manager"
++  depends on BT || ETHERNET || WLAN
++  depends on NVMEM_SUNXI_SID
++  help
++    allwinner network mac address management
+diff --git a/drivers/misc/sunxi-addr/Makefile b/drivers/misc/sunxi-addr/Makefile
+new file mode 100644
+index 000000000000..f01fd4783566
+--- /dev/null
++++ b/drivers/misc/sunxi-addr/Makefile
+@@ -0,0 +1,5 @@
++#
++# Makefile for wifi mac addr manager drivers
++#
++sunxi_addr-objs := sunxi-addr.o sha256.o
++obj-$(CONFIG_SUNXI_ADDR_MGT)   += sunxi_addr.o
+diff --git a/drivers/misc/sunxi-addr/sha256.c b/drivers/misc/sunxi-addr/sha256.c
+new file mode 100644
+index 000000000000..78825810c53f
+--- /dev/null
++++ b/drivers/misc/sunxi-addr/sha256.c
+@@ -0,0 +1,178 @@
++/*
++ * Local implement of sha256.
++ *
++ * Copyright (C) 2013 Allwinner.
++ *
++ * This file is licensed under the terms of the GNU General Public
++ * License version 2.  This program is licensed "as is" without any
++ * warranty of any kind, whether express or implied.
++ */
++#include <linux/kernel.h>
++#include <linux/string.h>
++
++/****************************** MACROS ******************************/
++#define ROTRIGHT(a, b) (((a) >> (b)) | ((a) << (32 - (b))))
++#define CH(x, y, z)    (((x) & (y)) ^ (~(x) & (z)))
++#define MAJ(x, y, z)   (((x) & (y)) ^  ((x) & (z)) ^ ((y) & (z)))
++#define EP0(x)         (ROTRIGHT(x,  2) ^ ROTRIGHT(x, 13) ^ ROTRIGHT(x, 22))
++#define EP1(x)         (ROTRIGHT(x,  6) ^ ROTRIGHT(x, 11) ^ ROTRIGHT(x, 25))
++#define SIG0(x)        (ROTRIGHT(x,  7) ^ ROTRIGHT(x, 18) ^ ((x) >> 3))
++#define SIG1(x)        (ROTRIGHT(x, 17) ^ ROTRIGHT(x, 19) ^ ((x) >> 10))
++
++/**************************** VARIABLES *****************************/
++static const uint32_t k[64] = {
++	0x428a2f98, 0x71374491, 0xb5c0fbcf, 0xe9b5dba5,
++	0x3956c25b, 0x59f111f1, 0x923f82a4, 0xab1c5ed5,
++	0xd807aa98, 0x12835b01, 0x243185be, 0x550c7dc3,
++	0x72be5d74, 0x80deb1fe, 0x9bdc06a7, 0xc19bf174,
++	0xe49b69c1, 0xefbe4786, 0x0fc19dc6, 0x240ca1cc,
++	0x2de92c6f, 0x4a7484aa, 0x5cb0a9dc, 0x76f988da,
++	0x983e5152, 0xa831c66d, 0xb00327c8, 0xbf597fc7,
++	0xc6e00bf3, 0xd5a79147, 0x06ca6351, 0x14292967,
++	0x27b70a85, 0x2e1b2138, 0x4d2c6dfc, 0x53380d13,
++	0x650a7354, 0x766a0abb, 0x81c2c92e, 0x92722c85,
++	0xa2bfe8a1, 0xa81a664b, 0xc24b8b70, 0xc76c51a3,
++	0xd192e819, 0xd6990624, 0xf40e3585, 0x106aa070,
++	0x19a4c116, 0x1e376c08, 0x2748774c, 0x34b0bcb5,
++	0x391c0cb3, 0x4ed8aa4a, 0x5b9cca4f, 0x682e6ff3,
++	0x748f82ee, 0x78a5636f, 0x84c87814, 0x8cc70208,
++	0x90befffa, 0xa4506ceb, 0xbef9a3f7, 0xc67178f2
++};
++
++struct sha256_ctx {
++	uint8_t data[64];   /* current 512-bit chunk of message data, just like a buffer */
++	uint32_t datalen;   /* sign the data length of current chunk */
++	uint64_t bitlen;    /* the bit length of the total message */
++	uint32_t state[8];  /* store the middle state of hash abstract */
++};
++
++/*********************** FUNCTION DEFINITIONS ***********************/
++static void sha256_transform(struct sha256_ctx *ctx, const uint8_t *data)
++{
++	uint32_t a, b, c, d, e, f, g, h, i, j, t1, t2, m[64];
++
++	/* initialization */
++	for (i = 0, j = 0; i < 16; ++i, j += 4)
++		m[i] = (data[j] << 24) | (data[j + 1] << 16) |
++			(data[j + 2] << 8) | (data[j + 3]);
++	for ( ; i < 64; ++i)
++		m[i] = SIG1(m[i - 2]) + m[i - 7] + SIG0(m[i - 15]) + m[i - 16];
++
++	a = ctx->state[0];
++	b = ctx->state[1];
++	c = ctx->state[2];
++	d = ctx->state[3];
++	e = ctx->state[4];
++	f = ctx->state[5];
++	g = ctx->state[6];
++	h = ctx->state[7];
++
++	for (i = 0; i < 64; ++i) {
++		t1 = h + EP1(e) + CH(e, f, g) + k[i] + m[i];
++		t2 = EP0(a) + MAJ(a, b, c);
++		h = g;
++		g = f;
++		f = e;
++		e = d + t1;
++		d = c;
++		c = b;
++		b = a;
++		a = t1 + t2;
++	}
++
++	ctx->state[0] += a;
++	ctx->state[1] += b;
++	ctx->state[2] += c;
++	ctx->state[3] += d;
++	ctx->state[4] += e;
++	ctx->state[5] += f;
++	ctx->state[6] += g;
++	ctx->state[7] += h;
++}
++
++static void sha256_init(struct sha256_ctx *ctx)
++{
++	ctx->datalen = 0;
++	ctx->bitlen = 0;
++	ctx->state[0] = 0x6a09e667;
++	ctx->state[1] = 0xbb67ae85;
++	ctx->state[2] = 0x3c6ef372;
++	ctx->state[3] = 0xa54ff53a;
++	ctx->state[4] = 0x510e527f;
++	ctx->state[5] = 0x9b05688c;
++	ctx->state[6] = 0x1f83d9ab;
++	ctx->state[7] = 0x5be0cd19;
++}
++
++static void sha256_update(struct sha256_ctx *ctx, const uint8_t *data, size_t len)
++{
++	uint32_t i;
++
++	for (i = 0; i < len; ++i) {
++		ctx->data[ctx->datalen] = data[i];
++		ctx->datalen++;
++		if (ctx->datalen == 64) {
++			/* 64 byte = 512 bit  means the buffer ctx->data has
++			 * fully stored one chunk of message,
++			 * so do the sha256 hash map for the current chunk.
++			 */
++			sha256_transform(ctx, ctx->data);
++			ctx->bitlen += 512;
++			ctx->datalen = 0;
++		}
++	}
++}
++
++static void sha256_final(struct sha256_ctx *ctx, uint8_t *hash)
++{
++	uint32_t i;
++
++	i = ctx->datalen;
++
++	/* Pad whatever data is left in the buffer. */
++	if (ctx->datalen < 56) {
++		ctx->data[i++] = 0x80;  /* pad 10000000 = 0x80 */
++		while (i < 56)
++			ctx->data[i++] = 0x00;
++	} else {
++		ctx->data[i++] = 0x80;
++		while (i < 64)
++			ctx->data[i++] = 0x00;
++		sha256_transform(ctx, ctx->data);
++		memset(ctx->data, 0, 56);
++	}
++
++	/* Append to the padding the total message's length in bits and transform. */
++	ctx->bitlen += ctx->datalen * 8;
++	ctx->data[63] = ctx->bitlen;
++	ctx->data[62] = ctx->bitlen >> 8;
++	ctx->data[61] = ctx->bitlen >> 16;
++	ctx->data[60] = ctx->bitlen >> 24;
++	ctx->data[59] = ctx->bitlen >> 32;
++	ctx->data[58] = ctx->bitlen >> 40;
++	ctx->data[57] = ctx->bitlen >> 48;
++	ctx->data[56] = ctx->bitlen >> 56;
++	sha256_transform(ctx, ctx->data);
++
++	/* copying the final state to the output hash(use big endian). */
++	for (i = 0; i < 4; ++i) {
++		hash[i]      = (ctx->state[0] >> (24 - i * 8)) & 0x000000ff;
++		hash[i + 4]  = (ctx->state[1] >> (24 - i * 8)) & 0x000000ff;
++		hash[i + 8]  = (ctx->state[2] >> (24 - i * 8)) & 0x000000ff;
++		hash[i + 12] = (ctx->state[3] >> (24 - i * 8)) & 0x000000ff;
++		hash[i + 16] = (ctx->state[4] >> (24 - i * 8)) & 0x000000ff;
++		hash[i + 20] = (ctx->state[5] >> (24 - i * 8)) & 0x000000ff;
++		hash[i + 24] = (ctx->state[6] >> (24 - i * 8)) & 0x000000ff;
++		hash[i + 28] = (ctx->state[7] >> (24 - i * 8)) & 0x000000ff;
++	}
++}
++
++int hmac_sha256(const uint8_t *plaintext, ssize_t psize, uint8_t *output)
++{
++	struct sha256_ctx ctx;
++
++	sha256_init(&ctx);
++	sha256_update(&ctx, plaintext, psize);
++	sha256_final(&ctx, output);
++	return 0;
++}
+diff --git a/drivers/misc/sunxi-addr/sunxi-addr.c b/drivers/misc/sunxi-addr/sunxi-addr.c
+new file mode 100644
+index 000000000000..c8a50c8dbac6
+--- /dev/null
++++ b/drivers/misc/sunxi-addr/sunxi-addr.c
+@@ -0,0 +1,356 @@
++/*
++ * The driver of SUNXI NET MAC ADDR Manager.
++ *
++ * Copyright (C) 2013 Allwinner.
++ *
++ * This file is licensed under the terms of the GNU General Public
++ * License version 2.  This program is licensed "as is" without any
++ * warranty of any kind, whether express or implied.
++ */
++#define DEBUG
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/miscdevice.h>
++#include <linux/of.h>
++#include <linux/platform_device.h>
++
++#define ADDR_MGT_DBG(fmt, arg...) printk(KERN_DEBUG "[ADDR_MGT] %s: " fmt "\n",\
++				__func__, ## arg)
++#define ADDR_MGT_ERR(fmt, arg...) printk(KERN_ERR "[ADDR_MGT] %s: " fmt "\n",\
++				__func__, ## arg)
++
++#define MODULE_CUR_VERSION  "v1.0.9"
++
++#define MATCH_STR_LEN       20
++#define ADDR_VAL_LEN        6
++#define ADDR_STR_LEN        18
++#define ID_LEN              16
++#define HASH_LEN            32
++
++#define TYPE_ANY            0
++#define TYPE_BURN           1
++#define TYPE_IDGEN          2
++#define TYPE_USER           3
++#define TYPE_RAND           4
++
++#define ADDR_FMT_STR        0
++#define ADDR_FMT_VAL        1
++
++#define IS_TYPE_INVALID(x)  ((x < TYPE_ANY) || (x > TYPE_RAND))
++
++#define ADDR_CLASS_ATTR_ADD(name) \
++static ssize_t addr_##name##_show(const struct class *class, \
++		const struct class_attribute *attr, char *buffer) \
++{ \
++	char addr[ADDR_STR_LEN]; \
++	if (IS_TYPE_INVALID(get_addr_by_name(ADDR_FMT_STR, addr, #name))) \
++		return 0; \
++	return sprintf(buffer, "%.17s\n", addr); \
++} \
++static ssize_t addr_##name##_store(const struct class *class, \
++		const struct class_attribute *attr, \
++		const char *buffer, size_t count) \
++{ \
++	if (count != ADDR_STR_LEN) { \
++		ADDR_MGT_ERR("Length wrong."); \
++		return -EINVAL; \
++	} \
++	set_addr_by_name(TYPE_USER, ADDR_FMT_STR, buffer, #name); \
++	return count; \
++} \
++static CLASS_ATTR_RW(addr_##name);
++
++struct addr_mgt_info {
++	unsigned int type_def;
++	unsigned int type_cur;
++	unsigned int flag;
++	char *addr;
++	char *name;
++};
++
++static struct addr_mgt_info info[] = {
++	{TYPE_ANY, TYPE_ANY, 1, NULL, "wifi"},
++	{TYPE_ANY, TYPE_ANY, 0, NULL, "bt"  },
++	{TYPE_ANY, TYPE_ANY, 1, NULL, "eth" },
++};
++
++extern int hmac_sha256(const uint8_t *plaintext, ssize_t psize, uint8_t *output);
++extern int sunxi_get_soc_chipid(unsigned char *chipid);
++
++static int addr_parse(int fmt, const char *addr, int check)
++{
++	char val_buf[ADDR_VAL_LEN];
++	char cmp_buf[ADDR_VAL_LEN];
++	int  ret = ADDR_VAL_LEN;
++
++	if (fmt == ADDR_FMT_STR)
++		ret = sscanf(addr, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
++					&val_buf[0], &val_buf[1], &val_buf[2],
++					&val_buf[3], &val_buf[4], &val_buf[5]);
++	else
++		memcpy(val_buf, addr, ADDR_VAL_LEN);
++
++	if (ret != ADDR_VAL_LEN)
++		return -1;
++
++	if (check && (val_buf[0] & 0x3))
++		return -1;
++
++	memset(cmp_buf, 0x00, ADDR_VAL_LEN);
++	if (memcmp(val_buf, cmp_buf, ADDR_VAL_LEN) == 0)
++		return -1;
++
++	memset(cmp_buf, 0xFF, ADDR_VAL_LEN);
++	if (memcmp(val_buf, cmp_buf, ADDR_VAL_LEN) == 0)
++		return -1;
++
++	return 0;
++}
++
++static struct addr_mgt_info *addr_find_by_name(char *name)
++{
++	int i = 0;
++	for (i = 0; i < ARRAY_SIZE(info); i++) {
++		if (strcmp(info[i].name, name) == 0)
++			return &info[i];
++	}
++	return NULL;
++}
++
++static int get_addr_by_name(int fmt, char *addr, char *name)
++{
++	struct addr_mgt_info *t;
++
++	t = addr_find_by_name(name);
++	if (t == NULL) {
++		ADDR_MGT_ERR("can't find addr named: %s", name);
++		return -1;
++	}
++
++	if (IS_TYPE_INVALID(t->type_cur)) {
++		ADDR_MGT_ERR("addr type invalid");
++		return -1;
++	}
++
++	if (addr_parse(ADDR_FMT_VAL, t->addr, t->flag)) {
++		ADDR_MGT_ERR("addr parse fail(%s)", t->addr);
++		return -1;
++	}
++
++	if (fmt == ADDR_FMT_STR)
++		sprintf(addr, "%02X:%02X:%02X:%02X:%02X:%02X",
++				t->addr[0], t->addr[1], t->addr[2],
++				t->addr[3], t->addr[4], t->addr[5]);
++	else
++		memcpy(addr, t->addr, ADDR_VAL_LEN);
++
++	return t->type_cur;
++}
++
++static int set_addr_by_name(int type, int fmt, const char *addr, char *name)
++{
++	struct addr_mgt_info *t;
++
++	t = addr_find_by_name(name);
++	if (t == NULL) {
++		ADDR_MGT_ERR("can't find addr named: %s", name);
++		return -1;
++	}
++
++	if (addr_parse(fmt, addr, t->flag)) {
++		ADDR_MGT_ERR("addr parse fail(%s)", addr);
++		return -1;
++	}
++
++	t->type_cur = type;
++	if (fmt == ADDR_FMT_STR)
++		sscanf(addr, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
++				&t->addr[0], &t->addr[1], &t->addr[2],
++				&t->addr[3], &t->addr[4], &t->addr[5]);
++	else
++		memcpy(t->addr, addr, ADDR_VAL_LEN);
++
++	return 0;
++}
++
++int get_custom_mac_address(int fmt, char *name, char *addr)
++{
++	return get_addr_by_name(fmt, addr, name);
++}
++EXPORT_SYMBOL_GPL(get_custom_mac_address);
++
++static int addr_factory(struct device_node *np,
++			int idx, int type, char *mac, char *name)
++{
++	int  ret, i;
++	char match[MATCH_STR_LEN];
++	const char *p;
++	char id[ID_LEN], hash[HASH_LEN], cmp_buf[ID_LEN];
++	struct timespec64 curtime;
++
++	switch (type) {
++	case TYPE_BURN:
++		sprintf(match, "addr_%s", name);
++		ret = of_property_read_string_index(np, match, 0, &p);
++		if (ret)
++			return -1;
++
++		ret = sscanf(p, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
++			&mac[0], &mac[1], &mac[2],
++			&mac[3], &mac[4], &mac[5]);
++
++		if (ret != ADDR_VAL_LEN)
++			return -1;
++		break;
++	case TYPE_IDGEN:
++		if (idx > HASH_LEN / ADDR_VAL_LEN - 1)
++			return -1;
++		if (sunxi_get_soc_chipid(id))
++			return -1;
++		memset(cmp_buf, 0x00, ID_LEN);
++		if (memcmp(id, cmp_buf, ID_LEN) == 0)
++			return -1;
++		if (hmac_sha256(id, ID_LEN, hash))
++			return -1;
++		memcpy(mac, &hash[idx * ADDR_VAL_LEN], ADDR_VAL_LEN);
++		break;
++	case TYPE_RAND:
++		for (i = 0; i < ADDR_VAL_LEN; i++) {
++			ktime_get_real_ts64(&curtime);
++			mac[i] = (char)curtime.tv_nsec;
++		}
++		break;
++	default:
++		ADDR_MGT_ERR("unsupport type: %d", type);
++		return -1;
++	}
++	return 0;
++}
++
++static int addr_init(struct platform_device *pdev)
++{
++	struct device_node *np = pdev->dev.of_node;
++	int  type, i, j;
++	char match[MATCH_STR_LEN];
++	char addr[ADDR_VAL_LEN];
++	int  type_tab[] = {TYPE_BURN, TYPE_IDGEN, TYPE_RAND};
++
++	/* init addr type and value */
++	for (i = 0; i < ARRAY_SIZE(info); i++) {
++		sprintf(match, "type_addr_%s", info[i].name);
++		if (of_property_read_u32(np, match, &type)) {
++			ADDR_MGT_DBG("Failed to get type_def_%s, use default: %d",
++						info[i].name, info[i].type_def);
++		} else {
++			info[i].type_def = type;
++			info[i].type_cur = type;
++		}
++
++		if (IS_TYPE_INVALID(info[i].type_def))
++			return -1;
++		if (info[i].type_def != TYPE_ANY) {
++			if (addr_factory(np, i, info[i].type_def, addr, info[i].name))
++				return -1;
++		} else {
++			for (j = 0; j < ARRAY_SIZE(type_tab); j++) {
++				if (!addr_factory(np, i, type_tab[j], addr, info[i].name)) {
++					info[i].type_cur = type_tab[j];
++					break;
++				}
++			}
++		}
++
++		if (info[i].flag)
++			addr[0] &= 0xFC;
++
++		if (addr_parse(ADDR_FMT_VAL, addr, info[i].flag))
++			return -1;
++		else {
++			info[i].addr = devm_kzalloc(&pdev->dev, ADDR_VAL_LEN, GFP_KERNEL);
++			memcpy(info[i].addr, addr, ADDR_VAL_LEN);
++		}
++	}
++	return 0;
++}
++
++static ssize_t summary_show(const struct class *class,
++				const struct class_attribute *attr, char *buffer)
++{
++	int i = 0, ret = 0;
++
++	ret += sprintf(&buffer[ret], "name cfg cur address\n");
++	for (i = 0; i < ARRAY_SIZE(info); i++) {
++		ret += sprintf(&buffer[ret],
++			"%4s  %d   %d  %02X:%02X:%02X:%02X:%02X:%02X\n",
++			info[i].name,   info[i].type_def, info[i].type_cur,
++			info[i].addr[0], info[i].addr[1], info[i].addr[2],
++			info[i].addr[3], info[i].addr[4], info[i].addr[5]);
++	}
++	return ret;
++}
++static CLASS_ATTR_RO(summary);
++
++ADDR_CLASS_ATTR_ADD(wifi);
++ADDR_CLASS_ATTR_ADD(bt);
++ADDR_CLASS_ATTR_ADD(eth);
++
++static struct attribute *addr_class_attrs[] = {
++	&class_attr_summary.attr,
++	&class_attr_addr_wifi.attr,
++	&class_attr_addr_bt.attr,
++	&class_attr_addr_eth.attr,
++	NULL
++};
++ATTRIBUTE_GROUPS(addr_class);
++
++static struct class addr_class = {
++	.name = "addr_mgt",
++	.class_groups = addr_class_groups,
++};
++
++static const struct of_device_id addr_mgt_ids[] = {
++	{ .compatible = "allwinner,sunxi-addr_mgt" },
++	{ /* Sentinel */ }
++};
++
++static int addr_mgt_probe(struct platform_device *pdev)
++{
++	int status;
++
++	ADDR_MGT_DBG("module version: %s", MODULE_CUR_VERSION);
++	status = class_register(&addr_class);
++	if (status < 0) {
++		ADDR_MGT_ERR("class register error, status: %d.", status);
++		return -1;
++	}
++
++	if (addr_init(pdev)) {
++		ADDR_MGT_ERR("failed to init addr.");
++		class_unregister(&addr_class);
++		return -1;
++	}
++	ADDR_MGT_DBG("success.");
++	return 0;
++}
++
++static void addr_mgt_remove(struct platform_device *pdev)
++{
++	class_unregister(&addr_class);
++}
++
++static struct platform_driver addr_mgt_driver = {
++	.probe  = addr_mgt_probe,
++	.remove = addr_mgt_remove,
++	.driver = {
++		.owner = THIS_MODULE,
++		.name  = "sunxi-addr-mgt",
++		.of_match_table = addr_mgt_ids,
++	},
++};
++
++module_platform_driver_probe(addr_mgt_driver, addr_mgt_probe);
++
++MODULE_AUTHOR("Allwinnertech");
++MODULE_DESCRIPTION("Network MAC Addess Manager");
++MODULE_LICENSE("GPL");
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/Add-wifi-nodes-for-Inovato-Quadra.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/Add-wifi-nodes-for-Inovato-Quadra.patch
new file mode 100644
index 000000000000..3442bfe56be6
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/Add-wifi-nodes-for-Inovato-Quadra.patch
@@ -0,0 +1,88 @@
+From d10d89d8f6a6737fae866e636bbbcc0741a8cc11 Mon Sep 17 00:00:00 2001
+From: Gunjan Gupta <viraniac@gmail.com>
+Date: Tue, 19 Sep 2023 11:06:01 +0000
+Subject: Add wifi nodes for Inovato Quadra
+
+---
+ arch/arm64/boot/dts/allwinner/Makefile        |  1 +
+ .../allwinner/sun50i-h6-inovato-quadra.dts    | 56 +++++++++++++++++++
+ 2 files changed, 57 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-inovato-quadra.dts
+
+diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
+index dc922a71cfc1..95d2886defc8 100644
+--- a/arch/arm64/boot/dts/allwinner/Makefile
++++ b/arch/arm64/boot/dts/allwinner/Makefile
+@@ -49,6 +49,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-one-plus.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64-model-b.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb
++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-inovato-quadra.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6-mini.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h313-tanix-tx1.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-bigtreetech-cb1-manta.dtb
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-inovato-quadra.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-inovato-quadra.dts
+new file mode 100644
+index 000000000000..551ad69f18a6
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-inovato-quadra.dts
+@@ -0,0 +1,56 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++// Copyright (c) 2023 Gunjan Gupta <gunjan@armbian.com>
++
++/dts-v1/;
++
++#include "sun50i-h6-tanix.dtsi"
++
++/ {
++	model = "Inovato Quadra";
++	compatible = "oranth,inovato-quadra", "allwinner,sun50i-h6";
++
++	aliases {
++		ethernet1 = &xr819;
++	};
++
++	leds {
++		compatible = "gpio-leds";
++
++		led-0 {
++			label = "red";
++			gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */
++		};
++
++		led-1 {
++			label = "blue";
++			gpios = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */
++			default-state = "on";
++		};
++	};
++};
++
++&i2s1 {
++	status = "okay";
++};
++
++&mmc1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&mmc1_pins>;
++
++	xr819: sdio_wifi@1 {
++		compatible = "xradio,xr819";
++		interrupt-names = "host-wake";
++		interrupt-parent = <&r_pio>;
++		interrupts = <1 0 IRQ_TYPE_EDGE_RISING>;
++		local-mac-address = [dc 44 6d c0 ff ee];
++		reg = <1>;
++	};
++};
++
++&sound_hdmi {
++	status = "okay";
++};
++
++&wifi_pwrseq {
++	post-power-on-delay-ms = <0xc8>;
++};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/Add-ws2812-RGB-driver-for-allwinner-H616.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/Add-ws2812-RGB-driver-for-allwinner-H616.patch
new file mode 100644
index 000000000000..e755c234cf33
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/Add-ws2812-RGB-driver-for-allwinner-H616.patch
@@ -0,0 +1,273 @@
+From 4546be7fd3812ee3a733beececa504bf7cb4bfac Mon Sep 17 00:00:00 2001
+From: Alan <Alan>
+Date: Sat, 20 May 2023 17:26:21 +0800
+Subject: Add: ws2812 RGB driver for allwinner H616
+
+---
+ drivers/leds/rgb/Kconfig       |   7 +
+ drivers/leds/rgb/Makefile      |   1 +
+ drivers/leds/rgb/leds-ws2812.c | 227 +++++++++++++++++++++++++++++++++
+ 3 files changed, 235 insertions(+)
+ create mode 100644 drivers/leds/rgb/leds-ws2812.c
+
+diff --git a/drivers/leds/rgb/Kconfig b/drivers/leds/rgb/Kconfig
+index 222d943d826a..3b7761f39f44 100644
+--- a/drivers/leds/rgb/Kconfig
++++ b/drivers/leds/rgb/Kconfig
+@@ -76,3 +76,10 @@ config LEDS_MT6370_RGB
+ 	  will be called "leds-mt6370-rgb".
+ 
+ endif # LEDS_CLASS_MULTICOLOR
++
++config LEDS_WS2812
++	tristate "WS2812 RGB support for allwinner H616"
++	depends on PINCTRL_SUN50I_H616
++
++	help
++	  Say Y here if you want to use the WS2812.
+\ No newline at end of file
+diff --git a/drivers/leds/rgb/Makefile b/drivers/leds/rgb/Makefile
+index a501fd27f179..8f7646ead3c1 100644
+--- a/drivers/leds/rgb/Makefile
++++ b/drivers/leds/rgb/Makefile
+@@ -6,3 +6,4 @@ obj-$(CONFIG_LEDS_NCP5623)		+= leds-ncp5623.o
+ obj-$(CONFIG_LEDS_PWM_MULTICOLOR)	+= leds-pwm-multicolor.o
+ obj-$(CONFIG_LEDS_QCOM_LPG)		+= leds-qcom-lpg.o
+ obj-$(CONFIG_LEDS_MT6370_RGB)		+= leds-mt6370-rgb.o
++obj-$(CONFIG_LEDS_WS2812)		+= leds-ws2812.o
+diff --git a/drivers/leds/rgb/leds-ws2812.c b/drivers/leds/rgb/leds-ws2812.c
+new file mode 100644
+index 000000000000..c9981724bba9
+--- /dev/null
++++ b/drivers/leds/rgb/leds-ws2812.c
+@@ -0,0 +1,227 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * Copyright (c) 2023, The Linux Foundation. All rights reserved.
++ */
++#include <linux/init.h>
++#include <linux/types.h>
++#include <linux/cdev.h>
++#include <linux/fs.h>
++#include <linux/device.h>
++#include <asm/uaccess.h>
++#include <linux/moduleparam.h>
++#include <linux/ioctl.h>
++#include <linux/version.h>
++#include <linux/errno.h>
++#include <linux/rbtree.h>
++#include <linux/ktime.h>
++#include <linux/string.h>
++#include <linux/mutex.h>
++#include <linux/time.h>
++#include <linux/hrtimer.h>
++#include <linux/pci.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/input.h>
++#include <linux/delay.h>
++#include <linux/slab.h>
++#include <linux/interrupt.h>
++#include <linux/irq.h>
++#include <linux/gpio.h>
++#include <linux/of_gpio.h>
++#include <linux/platform_device.h>
++#include <linux/miscdevice.h>
++#include <linux/uaccess.h>
++
++#define GPIO_BASE 0x0300B000
++#define GPIO_DAT_OFFSET(n) ((n)*0x0024 + 0x10)
++
++static uint32_t ws2812_pin = 0;
++static volatile uint32_t *ws2812_gpio_port;
++static volatile uint32_t ws2812_gpio_bit;
++static volatile uint32_t ws2812_set_val = 0;
++static volatile uint32_t ws2812_reset_val = 0;
++
++DEFINE_SPINLOCK(lock);
++
++// ws2812 reset
++static void ws2812_rst(void)
++{
++	*ws2812_gpio_port &= ~ws2812_gpio_bit;
++	udelay(200);// RES low voltage time, Above 50µs
++}
++
++static void ws2812_Write_24Bits(uint32_t grb)
++{
++	uint8_t i;
++	for (i = 0; i < 24; i++)
++	{
++		if (grb & 0x800000)
++		{
++			// loop for delay about 700ns
++			*ws2812_gpio_port = ws2812_set_val;
++			*ws2812_gpio_port = ws2812_set_val;
++			*ws2812_gpio_port = ws2812_set_val;
++			*ws2812_gpio_port = ws2812_set_val;
++			*ws2812_gpio_port = ws2812_set_val;
++			*ws2812_gpio_port = ws2812_set_val;
++			*ws2812_gpio_port = ws2812_set_val;
++			// loop for delay about 600ns
++			*ws2812_gpio_port = ws2812_reset_val;
++			*ws2812_gpio_port = ws2812_reset_val;
++			*ws2812_gpio_port = ws2812_reset_val;
++			*ws2812_gpio_port = ws2812_reset_val;
++			*ws2812_gpio_port = ws2812_reset_val;
++			*ws2812_gpio_port = ws2812_reset_val;
++		}
++		else
++		{
++			// loop for delay about 200ns
++			*ws2812_gpio_port = ws2812_set_val;
++			*ws2812_gpio_port = ws2812_set_val;
++			// loop for delay about 800ns
++			*ws2812_gpio_port = ws2812_reset_val;
++			*ws2812_gpio_port = ws2812_reset_val;
++			*ws2812_gpio_port = ws2812_reset_val;
++			*ws2812_gpio_port = ws2812_reset_val;
++			*ws2812_gpio_port = ws2812_reset_val;
++			*ws2812_gpio_port = ws2812_reset_val;
++			*ws2812_gpio_port = ws2812_reset_val;
++			*ws2812_gpio_port = ws2812_reset_val;
++		}
++		grb <<= 1;
++	}
++}
++
++static void ws2812_write_array(uint32_t *rgb, uint32_t cnt)
++{
++	uint32_t i = 0;
++	unsigned long flags;
++
++	for (i = 0; i < cnt; i++)
++	{
++		// rgb -> grb
++		rgb[i] = (((rgb[i] >> 16) & 0xff) << 8) | (((rgb[i] >> 8) & 0xff) << 16) | ((rgb[i]) & 0xff);
++	}
++
++	spin_lock_irqsave(&lock, flags);
++	ws2812_set_val = *ws2812_gpio_port | ws2812_gpio_bit;
++	ws2812_reset_val = *ws2812_gpio_port & (~ws2812_gpio_bit);
++	ws2812_rst();
++	for (i = 0; i < cnt; i++)
++	{
++		ws2812_Write_24Bits(rgb[i]);
++	}
++	spin_unlock_irqrestore(&lock, flags);
++}
++
++ssize_t ws2812_read(struct file *file, char __user *user, size_t bytesize, loff_t *this_loff_t)
++{
++	return 0;
++}
++
++ssize_t ws2812_write(struct file *file, const char __user *user_buf, size_t count, loff_t *ppos)
++{
++	uint32_t rgb[255];
++	unsigned long ret = 0;
++
++	if (count > 255 * 4) count = 255 * 4;
++	ret = copy_from_user(&rgb[0], user_buf, count);
++	if (ret < 0)
++	{
++		printk("copy_from_user fail!!!\n");
++		return -1;
++	}
++
++	ws2812_write_array((uint32_t *)rgb, count / 4);
++
++	return 0;
++}
++
++int ws2812_open(struct inode *inode, struct file *file)
++{
++	return 0;
++}
++
++int ws2812_close(struct inode *inode, struct file *file)
++{
++	return 0;
++}
++
++static struct file_operations ws2812_ops = {
++	.owner = THIS_MODULE,
++	.open = ws2812_open,
++	.release = ws2812_close,
++	.write = ws2812_write,
++};
++
++static struct miscdevice ws2812_misc_dev = {
++	.minor = MISC_DYNAMIC_MINOR,
++	.name = "ws2812-led",
++	.fops = &ws2812_ops,
++};
++
++static int ws2812_probe(struct platform_device *pdev)
++{
++	int ret;
++	struct device_node *ws2812_gpio_node = pdev->dev.of_node;
++	uint32_t rgb_cnt = 0;
++	uint32_t rgb[255];
++
++	of_property_read_u32(ws2812_gpio_node, "rgb_cnt", &rgb_cnt);
++	if (rgb_cnt > 255)
++		rgb_cnt = 255;
++
++	of_property_read_u32_array(ws2812_gpio_node, "rgb_value", rgb, rgb_cnt);
++	ws2812_pin = of_get_named_gpio(ws2812_gpio_node, "gpios", 0);
++	if (!gpio_is_valid(ws2812_pin))
++	{
++		printk(KERN_ERR "ws2812: gpio: %d is invalid\n", ws2812_pin);
++		return -ENODEV;
++	}
++
++	ws2812_gpio_port = ioremap(GPIO_BASE + GPIO_DAT_OFFSET((ws2812_pin >> 5)), 4);
++	ws2812_gpio_bit = 1 << (ws2812_pin & 0x001F);
++
++	if (gpio_request(ws2812_pin, "ws2812-gpio"))
++	{
++		printk(KERN_ERR "ws2812: gpio %d request failed!\n", ws2812_pin);
++		gpio_free(ws2812_pin);
++		return -ENODEV;
++	}
++	gpio_direction_output(ws2812_pin, 0);
++
++	ret = misc_register(&ws2812_misc_dev);
++	msleep(50);
++
++	ws2812_write_array(rgb, rgb_cnt);
++
++	return 0;
++}
++
++static void ws2812_remove(struct platform_device *pdev)
++{
++	misc_deregister(&ws2812_misc_dev);
++	gpio_free(ws2812_pin);
++}
++
++static const struct of_device_id ws2812_of_match[] = {
++	{.compatible = "rgb-ws2812"},
++	{/* sentinel */}};
++
++MODULE_DEVICE_TABLE(of, ws2812_of_match);
++
++static struct platform_driver ws2812_driver = {
++	.probe		= ws2812_probe,
++	.remove		= ws2812_remove,
++	.driver		= {
++		.name	= "ws2812_ctl",
++		.of_match_table = ws2812_of_match,
++	},
++};
++
++module_platform_driver(ws2812_driver);
++
++MODULE_AUTHOR("MacLodge, Alan Ma <tech@biqu3d.com>");
++MODULE_DESCRIPTION("WS2812 RGB driver for Allwinner");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:ws2812_ctl");
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/BigTreeTech-CB1-dts-i2c-gpio-mode-adjustment-and-ws2812-rgb_val.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/BigTreeTech-CB1-dts-i2c-gpio-mode-adjustment-and-ws2812-rgb_val.patch
new file mode 100644
index 000000000000..deb579f87ad8
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/BigTreeTech-CB1-dts-i2c-gpio-mode-adjustment-and-ws2812-rgb_val.patch
@@ -0,0 +1,58 @@
+From 20dc0b0f3da7895d50f2824b4608c5e44729f892 Mon Sep 17 00:00:00 2001
+From: JohnTheCoolingFan <ivan8215145640@gmail.com>
+Date: Sat, 25 Jan 2025 11:30:04 +0000
+Subject: BigTreeTech CB1: dts: i2c gpio mode adjustment and ws2812 rgb_value
+
+Signed-off-by: JohnTheCoolingFan <ivan8215145640@gmail.com>
+---
+ .../boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-emmc.dts   | 4 ++--
+ .../boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-sd.dts     | 4 ++--
+ .../arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi | 2 +-
+ 3 files changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-emmc.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-emmc.dts
+index f878c23f1d90..b059ea08fec0 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-emmc.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-emmc.dts
+@@ -21,8 +21,8 @@ &ws2812 {
+ };
+ 
+ &i2c_gpio {
+-	gpios = <&pio 8 6 GPIO_ACTIVE_HIGH>, /* SDA PI6 */
+-			<&pio 8 4 GPIO_ACTIVE_HIGH>; /* SCL PI4 */
++	gpios = <&pio 8 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>, /* SDA PI6 */
++			<&pio 8 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; /* SCL PI4 */
+ };
+ 
+ &can0_pin_irq {
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-sd.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-sd.dts
+index e18dd854d74b..cc10be714676 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-sd.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-sd.dts
+@@ -12,8 +12,8 @@ &ws2812 {
+ };
+ 
+ &i2c_gpio {
+-	gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>, /* SDA PC12 */
+-			<&pio 2 10 GPIO_ACTIVE_HIGH>; /* SCL PC10 */
++	gpios = <&pio 2 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>, /* SDA PC12 */
++			<&pio 2 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; /* SCL PC10 */
+ };
+ 
+ &can0_pin_irq {
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi
+index 3b3a196eaa93..d18695148ef5 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi
+@@ -108,7 +108,7 @@ ws2812: ws2812 {
+ 		compatible = "rgb-ws2812";
+ 		pinctrl-names = "default";
+ 		rgb_cnt = <2>;
+-		rgb_value = <0x010000 0x010000>;
++		rgb_value = <0x000001 0x010000>;
+ 		status = "disabled";
+ 	};
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/Compile-the-pwm-overlay.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/Compile-the-pwm-overlay.patch
new file mode 100644
index 000000000000..211a6118a14f
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/Compile-the-pwm-overlay.patch
@@ -0,0 +1,24 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: afaulkner420 <afaulkner420@gmail.com>
+Date: Fri, 25 Mar 2022 19:26:16 +0000
+Subject: Compile the pwm overlay
+
+---
+ arch/arm64/boot/dts/allwinner/overlay/Makefile | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/Makefile b/arch/arm64/boot/dts/allwinner/overlay/Makefile
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/allwinner/overlay/Makefile
++++ b/arch/arm64/boot/dts/allwinner/overlay/Makefile
+@@ -38,6 +38,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += \
+ 	sun50i-h6-i2c0.dtbo \
+ 	sun50i-h6-i2c1.dtbo \
+ 	sun50i-h6-i2c2.dtbo \
++	sun50i-h6-pwm.dtbo \
+ 	sun50i-h6-ruart.dtbo \
+ 	sun50i-h6-spi-add-cs1.dtbo \
+ 	sun50i-h6-spi-jedec-nor.dtbo \
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/Correct-perf-interrupt-source-number-as-referenced-in-the-Allwi.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/Correct-perf-interrupt-source-number-as-referenced-in-the-Allwi.patch
new file mode 100644
index 000000000000..e53231b7c50f
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/Correct-perf-interrupt-source-number-as-referenced-in-the-Allwi.patch
@@ -0,0 +1,29 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Ryzer58 <ryestar101@gmail.com>
+Date: Sat, 30 Nov 2024 20:40:29 +0000
+Subject: Correct perf interrupt source number as referenced in the Allwinner
+ A10 User manual
+
+to resolve conflict with UART2.
+
+Signed-off-by: Ryzer58 <ryestar101@gmail.com>
+---
+ arch/arm/boot/dts/allwinner/sun4i-a10.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun4i-a10.dtsi b/arch/arm/boot/dts/allwinner/sun4i-a10.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/allwinner/sun4i-a10.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun4i-a10.dtsi
+@@ -185,7 +185,7 @@ de: display-engine {
+ 
+ 	pmu {
+ 		compatible = "arm,cortex-a8-pmu";
+-		interrupts = <3>;
++		interrupts = <66>;
+ 	};
+ 
+ 	reserved-memory {
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/Doc-dt-bindings-usb-add-binding-for-DWC3-controller-on-Allwinne.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/Doc-dt-bindings-usb-add-binding-for-DWC3-controller-on-Allwinne.patch
new file mode 100644
index 000000000000..9e2045e1e31b
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/Doc-dt-bindings-usb-add-binding-for-DWC3-controller-on-Allwinne.patch
@@ -0,0 +1,63 @@
+From 846209f909c9cf9d7a29a72328ed27b9ee504ac1 Mon Sep 17 00:00:00 2001
+From: Icenowy Zheng <icenowy@aosc.io>
+Date: Mon, 25 Dec 2017 12:08:01 +0800
+Subject: Doc:dt-bindings:usb: add binding for DWC3 controller on Allwinner SoC
+
+The Allwinner H6 SoC uses DWC3 controller for USB3.
+
+Add its device tree binding document.
+
+Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
+---
+ .../bindings/usb/allwinner,dwc3.txt           | 39 +++++++++++++++++++
+ 1 file changed, 39 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/usb/allwinner,dwc3.txt
+
+diff --git a/Documentation/devicetree/bindings/usb/allwinner,dwc3.txt b/Documentation/devicetree/bindings/usb/allwinner,dwc3.txt
+new file mode 100644
+index 000000000000..3f7714636785
+--- /dev/null
++++ b/Documentation/devicetree/bindings/usb/allwinner,dwc3.txt
+@@ -0,0 +1,39 @@
++Allwinner SuperSpeed DWC3 USB SoC controller
++
++Required properties:
++- compatible:	should contain "allwinner,sun50i-h6-dwc3" for H6 SoC
++- clocks:	A list of phandle + clock-specifier pairs for the
++		clocks listed in clock-names
++- clock-names:	Should contain the following:
++  "bus"		The bus clock of the DWC3 part
++- resets:	A list of phandle + reset-specifier pairs for the
++		resets listed in reset-names
++- reset-names:	Should contain the following:
++  "bus"		The bus reset of the DWC3 part
++
++Required child node:
++A child node must exist to represent the core DWC3 IP block. The name of
++the node is not important. The content of the node is defined in dwc3.txt.
++
++Phy documentation is provided in the following places:
++Documentation/devicetree/bindings/phy/sun50i-usb3-phy.txt
++
++Example device nodes:
++	usb3: usb@5200000 {
++		compatible = "allwinner,sun50i-h6-dwc3";
++		#address-cells = <1>;
++		#size-cells = <1>;
++		ranges;
++		clocks = <&ccu CLK_BUS_XHCI>;
++		clock-names = "bus";
++		resets = <&ccu RST_BUS_XHCI>;
++		reset-names = "bus";
++
++		dwc3: dwc3 {
++			compatible = "snps,dwc3";
++			reg = <0x5200000 0x10000>;
++			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
++			phys = <&usb3phy>;
++			phy-names = "usb3-phy";
++		};
++	};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/Enable-DMA-support-for-the-Allwinner-A10-EMAC-which-already-exi.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/Enable-DMA-support-for-the-Allwinner-A10-EMAC-which-already-exi.patch
new file mode 100644
index 000000000000..dfd4ba94ed5a
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/Enable-DMA-support-for-the-Allwinner-A10-EMAC-which-already-exi.patch
@@ -0,0 +1,26 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Ryzer58 <ryestar101@gmail.com>
+Date: Sat, 30 Nov 2024 22:29:50 +0000
+Subject: Enable DMA support for the Allwinner A10 EMAC, which already exist in
+ the sun4i-emac driver
+
+---
+ arch/arm/boot/dts/allwinner/sun4i-a10.dtsi | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun4i-a10.dtsi b/arch/arm/boot/dts/allwinner/sun4i-a10.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/allwinner/sun4i-a10.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun4i-a10.dtsi
+@@ -315,6 +315,8 @@ emac: ethernet@1c0b000 {
+ 			interrupts = <55>;
+ 			clocks = <&ccu CLK_AHB_EMAC>;
+ 			allwinner,sram = <&emac_sram 1>;
++			dmas = <&dma SUN4I_DMA_DEDICATED 7>;
++			dma-names = "rx";
+ 			pinctrl-names = "default";
+ 			pinctrl-0 = <&emac_pins>;
+ 			status = "disabled";
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/Enable-creation-of-__symbols__-node.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/Enable-creation-of-__symbols__-node.patch
new file mode 100644
index 000000000000..7e2f0454c0a6
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/Enable-creation-of-__symbols__-node.patch
@@ -0,0 +1,29 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Patrick Yavitz <pyavitz@gmail.com>
+Date: Mon, 23 Dec 2024 10:14:57 -0500
+Subject: Enable creation of __symbols__ node
+
+Signed-off-by: Patrick Yavitz <pyavitz@gmail.com>
+---
+ scripts/Makefile.dtbs | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/scripts/Makefile.dtbs b/scripts/Makefile.dtbs
+index 111111111111..222222222222 100644
+--- a/scripts/Makefile.dtbs
++++ b/scripts/Makefile.dtbs
+@@ -102,6 +102,11 @@ else
+ DTC_FLAGS += -Wunique_unit_address_if_enabled
+ endif
+ 
++ifeq ($(CONFIG_OF_OVERLAY),y)
++# enable creation of __symbols__ node
++DTC_FLAGS += -@
++endif
++
+ ifneq ($(findstring 2,$(KBUILD_EXTRA_WARN)),)
+ DTC_FLAGS += -Wnode_name_chars_strict \
+              -Wproperty_name_chars_strict \
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/Fix-ghost-touches-on-tsc2007-tft-screen.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/Fix-ghost-touches-on-tsc2007-tft-screen.patch
new file mode 100644
index 000000000000..e3c7015d4a14
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/Fix-ghost-touches-on-tsc2007-tft-screen.patch
@@ -0,0 +1,211 @@
+From 5607ccab3192a2cc9d70c6072f83d9b9060295c8 Mon Sep 17 00:00:00 2001
+From: JohnTheCoolingFan <ivan8215145640@gmail.com>
+Date: Sat, 25 Jan 2025 12:54:16 +0000
+Subject: Fix ghost touches on tsc2007 tft screen
+
+Signed-off-by: JohnTheCoolingFan <ivan8215145640@gmail.com>
+---
+ .../sun50i-h616-bigtreetech-cb1.dtsi          |  1 +
+ drivers/input/touchscreen/tsc2007.h           |  1 +
+ drivers/input/touchscreen/tsc2007_core.c      | 96 +++++++++----------
+ include/linux/platform_data/tsc2007.h         |  1 +
+ 4 files changed, 49 insertions(+), 50 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi
+index 2022990e4bc0..3b3a196eaa93 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi
+@@ -125,6 +125,7 @@ tft_tp: ns2009@48 {
+ 			reg = <0x48>;
+ 			status = "disabled";
+ 			ti,x-plate-ohms = <660>;
++			ti,y-plate-ohms = <660>;
+ 			ti,rt-thr = <3000>;
+ 			ti,fuzzx = <32>;
+ 			ti,fuzzy = <16>;
+diff --git a/drivers/input/touchscreen/tsc2007.h b/drivers/input/touchscreen/tsc2007.h
+index 5252b6c6daeb..7411b8bce99c 100644
+--- a/drivers/input/touchscreen/tsc2007.h
++++ b/drivers/input/touchscreen/tsc2007.h
+@@ -65,6 +65,7 @@ struct tsc2007 {
+ 
+ 	u16			model;
+ 	u16			x_plate_ohms;
++	u16			y_plate_ohms;
+ 	u16			max_rt;
+ 	u16			rt_thr;
+ 	u8			touched;
+diff --git a/drivers/input/touchscreen/tsc2007_core.c b/drivers/input/touchscreen/tsc2007_core.c
+index 08bbbafbbae1..1ae1b1a3e367 100644
+--- a/drivers/input/touchscreen/tsc2007_core.c
++++ b/drivers/input/touchscreen/tsc2007_core.c
+@@ -70,22 +70,20 @@ static void tsc2007_read_values(struct tsc2007 *tsc, struct ts_event *tc)
+ 
+ u32 tsc2007_calculate_resistance(struct tsc2007 *tsc, struct ts_event *tc)
+ {
+-	u32 rt = 0;
+-
+-	/* range filtering */
+-	if (tc->x == MAX_12BIT)
++	if (tc->x == MAX_12BIT){
+ 		tc->x = 0;
++	}
+ 
+-	if (likely(tc->x && tc->z1)) {
+-		/* compute touch resistance using equation #1 */
+-		rt = tc->z2 - tc->z1;
+-		rt *= tc->x;
+-		rt *= tsc->x_plate_ohms;
+-		rt /= tc->z1;
+-		rt = (rt + 2047) >> 12;
++	if (tc->y == MAX_12BIT){
++		tc->y = 0;
+ 	}
+ 
+-	return rt;
++
++	if (likely(tc->x && tc->y && tc->z1)) {
++		return (tsc->x_plate_ohms * tc->x / 4096) * ((4096 / tc->z1) - 1) - tsc->y_plate_ohms * (1 - tc->y / 4096);
++	} else{
++		return 0;
++	}
+ }
+ 
+ bool tsc2007_is_pen_down(struct tsc2007 *ts)
+@@ -180,6 +178,7 @@ static irqreturn_t tsc2007_soft_poll(int irq, void *handle)
+ 	struct input_dev *input = ts->input;
+ 	struct ts_event tc;
+ 	u32 rt;
++	bool skipSync = false;
+ 
+ 	if(!ts->stopped) {
+ 
+@@ -189,45 +188,31 @@ static irqreturn_t tsc2007_soft_poll(int irq, void *handle)
+ 
+ 		rt = tsc2007_calculate_resistance(ts, &tc);
+ 
+-		if (rt == 0 || rt == 256) {
+-
+-			/*
+-				* Sample found inconsistent by debouncing or pressure is
+-				* beyond the maximum. Don't report it to user space,
+-				* repeat at least once more the measurement.
+-				*/
+-			dev_dbg(&ts->client->dev, "ignored pressure %d\n", rt);
+-
+-		} else {
+-
+-			if (rt < ts->rt_thr) {
+-
+-				dev_dbg(&ts->client->dev,
+-					"DOWN point(%4d,%4d), resistance (%4u)\n",
+-					tc.x, tc.y, rt);
+-
+-				rt = ts->max_rt - rt;
++		if (likely(rt)) {
+ 
+-				input_report_key(input, BTN_TOUCH, 1);
+-				input_report_abs(input, ABS_X, tc.y);
+-				input_report_abs(input, ABS_Y, 4096 - tc.x);
+-				input_report_abs(input, ABS_PRESSURE, rt);
++			/* range >= 0 && <= 4096 */
++			if (rt > 0 && rt <= ts->max_rt) {
++					rt = ts->max_rt - rt;
++					input_report_key(input, BTN_TOUCH, 1);
++					input_report_abs(input, ABS_X, tc.y);
++					input_report_abs(input, ABS_Y, 4096 - tc.x);
++					input_report_abs(input, ABS_PRESSURE, rt);
++					input_sync(input);
+ 
+-				input_sync(input);
+-				ts->touched = 1;
+-
+-			} else if (ts->touched == 1) {
+-
+-				dev_dbg(&ts->client->dev, "UP\n");
+-
+-				input_report_key(input, BTN_TOUCH, 0);
+-				input_report_abs(input, ABS_PRESSURE, 0);
+-				input_sync(input);
+-				ts->touched = 0;
++			} else {
++				//Discard Input Ghost or inconsistent
++				skipSync= true;
+ 			}
++		}else{
++           // No touch event or missing data for rt calculation
++           skipSync= true;
+ 		}
++	}
+ 
+-
++	if(skipSync){
++		input_report_key(input, BTN_TOUCH, 0);
++		input_report_abs(input, ABS_PRESSURE, 0);
++		input_sync(input);
+ 	}
+ 
+ 	return IRQ_HANDLED;
+@@ -329,6 +314,13 @@ static int tsc2007_probe_properties(struct device *dev, struct tsc2007 *ts)
+ 		return -EINVAL;
+ 	}
+ 
++	if (!device_property_read_u32(dev, "ti,y-plate-ohms", &val32)) {
++		ts->y_plate_ohms = val32;
++	} else {
++		dev_err(dev, "Missing ti,y-plate-ohms device property\n");
++		return -EINVAL;
++	}
++
+ 	ts->gpiod = devm_gpiod_get_optional(dev, NULL, GPIOD_IN);
+ 	if (IS_ERR(ts->gpiod))
+ 		return PTR_ERR(ts->gpiod);
+@@ -347,6 +339,7 @@ static int tsc2007_probe_pdev(struct device *dev, struct tsc2007 *ts,
+ {
+ 	ts->model             = pdata->model;
+ 	ts->x_plate_ohms      = pdata->x_plate_ohms;
++	ts->y_plate_ohms      = pdata->y_plate_ohms;
+ 	ts->max_rt            = pdata->max_rt ? : MAX_12BIT;
+ 	ts->poll_period       = msecs_to_jiffies(pdata->poll_period ? : 1);
+ 	ts->get_pendown_state = pdata->get_pendown_state;
+@@ -360,6 +353,11 @@ static int tsc2007_probe_pdev(struct device *dev, struct tsc2007 *ts,
+ 		return -EINVAL;
+ 	}
+ 
++	if (pdata->y_plate_ohms == 0) {
++		dev_err(dev, "y_plate_ohms is not set up in platform data\n");
++		return -EINVAL;
++	}
++
+ 	return 0;
+ }
+ 
+@@ -458,11 +456,9 @@ static int tsc2007_probe(struct i2c_client *client)
+ 			return err;
+ 		}
+ 	} else {
+-		INIT_WORK(&ts->work_i2c_poll,
+-			  tsc2007_ts_work_i2c_poll);
++		INIT_WORK(&ts->work_i2c_poll, tsc2007_ts_work_i2c_poll);
+ 		timer_setup(&ts->timer, tsc2007_ts_irq_poll_timer, 0);
+-		ts->timer.expires = jiffies +
+-					msecs_to_jiffies(POLL_INTERVAL_MS);
++		ts->timer.expires = jiffies + msecs_to_jiffies(POLL_INTERVAL_MS);
+ 		add_timer(&ts->timer);
+ 	}
+ 
+diff --git a/include/linux/platform_data/tsc2007.h b/include/linux/platform_data/tsc2007.h
+index a0ca52c41ccb..f88e580322f0 100644
+--- a/include/linux/platform_data/tsc2007.h
++++ b/include/linux/platform_data/tsc2007.h
+@@ -7,6 +7,7 @@
+ struct tsc2007_platform_data {
+ 	u16	model;				/* 2007. */
+ 	u16	x_plate_ohms;	/* must be non-zero value */
++	u16	y_plate_ohms;	/* must be non-zero value */
+ 	u16	max_rt; /* max. resistance above which samples are ignored */
+ 	unsigned long poll_period; /* time (in ms) between samples */
+ 	int	fuzzx; /* fuzz factor for X, Y and pressure axes */
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/Fix-include-uapi-spi-spidev-module.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/Fix-include-uapi-spi-spidev-module.patch
new file mode 100644
index 000000000000..1dc26e554159
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/Fix-include-uapi-spi-spidev-module.patch
@@ -0,0 +1,26 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Thu, 28 Apr 2022 15:45:14 +0300
+Subject: Fix include uapi spi spidev module
+
+---
+ drivers/spi/spidev.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c
+index 111111111111..222222222222 100644
+--- a/drivers/spi/spidev.c
++++ b/drivers/spi/spidev.c
+@@ -21,8 +21,7 @@
+ #include <linux/slab.h>
+ #include <linux/compat.h>
+ 
+-#include <linux/spi/spi.h>
+-#include <linux/spi/spidev.h>
++#include <uapi/linux/spi/spidev.h>
+ 
+ #include <linux/uaccess.h>
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/Input-axp20x-pek-allow-wakeup-after-shutdown.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/Input-axp20x-pek-allow-wakeup-after-shutdown.patch
new file mode 100644
index 000000000000..8df09f1b4ec7
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/Input-axp20x-pek-allow-wakeup-after-shutdown.patch
@@ -0,0 +1,48 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Samuel Holland <samuel@sholland.org>
+Date: Sat, 2 Jan 2021 15:52:27 -0600
+Subject: Input: axp20x-pek - allow wakeup after shutdown
+
+While the AXP20x PMIC handles the power button itself after shutting
+down, it is not always possible to use the PMIC's built-in shutdown
+feature, such as when other wakeup sources are needed (for example, an
+IR remote or wake-on-LAN) that require firmware support. In that case,
+the PMIC remains on, but suspended, until the board is powered back on.
+
+During this "fake" off state, IRQ configuration is similar to system
+sleep, where enable_irq_wake() must be call on an IRQ for it to be
+wakeup capable. Run the suspend callback to arm the power button IRQs
+during the shutdown process, so the power button works in this state.
+
+Signed-off-by: Samuel Holland <samuel@sholland.org>
+---
+ drivers/input/misc/axp20x-pek.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/drivers/input/misc/axp20x-pek.c b/drivers/input/misc/axp20x-pek.c
+index 111111111111..222222222222 100644
+--- a/drivers/input/misc/axp20x-pek.c
++++ b/drivers/input/misc/axp20x-pek.c
+@@ -384,6 +384,11 @@ static const struct dev_pm_ops axp20x_pek_pm_ops = {
+ 	.resume_noirq = pm_sleep_ptr(axp20x_pek_resume_noirq),
+ };
+ 
++static void axp20x_pek_shutdown(struct platform_device *pdev)
++{
++	axp20x_pek_suspend(&pdev->dev);
++}
++
+ static const struct platform_device_id axp_pek_id_match[] = {
+ 	{
+ 		.name = "axp20x-pek",
+@@ -399,6 +404,7 @@ MODULE_DEVICE_TABLE(platform, axp_pek_id_match);
+ 
+ static struct platform_driver axp20x_pek_driver = {
+ 	.probe		= axp20x_pek_probe,
++	.shutdown	= axp20x_pek_shutdown,
+ 	.id_table	= axp_pek_id_match,
+ 	.driver		= {
+ 		.name		= "axp20x-pek",
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/LED-green_power_on-red_status_heartbeat-arch-arm64-boot-dts-all.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/LED-green_power_on-red_status_heartbeat-arch-arm64-boot-dts-all.patch
new file mode 100644
index 000000000000..1d1b9bc36139
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/LED-green_power_on-red_status_heartbeat-arch-arm64-boot-dts-all.patch
@@ -0,0 +1,39 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: AGM1968 <AGM1968@users.noreply.github.com>
+Date: Wed, 31 May 2023 08:12:00 +0000
+Subject: LED-green_power_on-red_status_heartbeat
+ arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
+
+Signed-off-by: AGM1968 <AGM1968@users.noreply.github.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi | 7 ++++---
+ 1 file changed, 4 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
+@@ -27,16 +27,17 @@ leds {
+ 		compatible = "gpio-leds";
+ 
+ 		led-0 {
+-			function = LED_FUNCTION_POWER;
++			function = LED_FUNCTION_STATUS;
+ 			color = <LED_COLOR_ID_RED>;
+ 			gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */
+-			default-state = "on";
++			linux,default-trigger = "heartbeat";
+ 		};
+ 
+ 		led-1 {
+-			function = LED_FUNCTION_STATUS;
++			function = LED_FUNCTION_POWER;
+ 			color = <LED_COLOR_ID_GREEN>;
+ 			gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */
++			default-state = "on";
+ 		};
+ 	};
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/Makefile-CONFIG_SHELL-fix-for-builddeb-packaging.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/Makefile-CONFIG_SHELL-fix-for-builddeb-packaging.patch
new file mode 100644
index 000000000000..c30677d637e7
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/Makefile-CONFIG_SHELL-fix-for-builddeb-packaging.patch
@@ -0,0 +1,27 @@
+From a0d572eb612278a969beebead69eeba250c8f74f Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Wed, 2 Feb 2022 11:28:14 +0300
+Subject: Makefile: CONFIG_SHELL fix for builddeb packaging
+
+---
+ Makefile | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/Makefile b/Makefile
+index f49182f3bae1..b121106a8cef 100644
+--- a/Makefile
++++ b/Makefile
+@@ -439,7 +439,9 @@ KCONFIG_CONFIG	?= .config
+ export KCONFIG_CONFIG
+ 
+ # SHELL used by kbuild
+-CONFIG_SHELL := sh
++CONFIG_SHELL := $(shell if [ -x "$$BASH" ]; then echo $$BASH; \
++	  else if [ -x /bin/bash ]; then echo /bin/bash; \
++	  else echo sh; fi ; fi)
+ 
+ HOST_LFS_CFLAGS := $(shell getconf LFS_CFLAGS 2>/dev/null)
+ HOST_LFS_LDFLAGS := $(shell getconf LFS_LDFLAGS 2>/dev/null)
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/Move-sun50i-h6-pwm-settings-to-its-own-overlay.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/Move-sun50i-h6-pwm-settings-to-its-own-overlay.patch
new file mode 100644
index 000000000000..47f03ffb39d6
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/Move-sun50i-h6-pwm-settings-to-its-own-overlay.patch
@@ -0,0 +1,70 @@
+From 17c23b36efb63cd249c5cfc8ce4a6b790f1dfeda Mon Sep 17 00:00:00 2001
+From: afaulkner420 <afaulkner420@gmail.com>
+Date: Fri, 25 Mar 2022 19:23:56 +0000
+Subject: Move sun50i-h6-pwm settings to its own overlay
+
+---
+ .../allwinner/overlay/sun50i-h6-fixup.scr-cmd | 14 -----------
+ .../dts/allwinner/overlay/sun50i-h6-pwm.dtso  | 25 +++++++++++++++++++
+ 2 files changed, 25 insertions(+), 14 deletions(-)
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-pwm.dtso
+
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-fixup.scr-cmd b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-fixup.scr-cmd
+index d8e79ba4531b..f757db7aa4ad 100644
+--- a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-fixup.scr-cmd
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-fixup.scr-cmd
+@@ -54,20 +54,6 @@ if test "${param_pps_falling_edge}" = "1"; then
+ 	fdt set /pps@0 assert-falling-edge
+ fi
+ 
+-for f in ${overlays}; do
+-	if test "${f}" = "pwm"; then
+-		setenv bootargs_new ""
+-		for arg in ${bootargs}; do
+-			if test "${arg}" = "console=ttyS0,115200"; then
+-				echo "Warning: Disabling ttyS0 console due to enabled PWM overlay"
+-			else
+-				setenv bootargs_new "${bootargs_new} ${arg}"
+-			fi
+-		done
+-		setenv bootargs "${bootargs_new}"
+-	fi
+-done
+-
+ if test -n "${param_w1_pin}"; then
+ 	setenv tmp_bank "${param_w1_pin}"
+ 	setenv tmp_pin "${param_w1_pin}"
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-pwm.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-pwm.dtso
+new file mode 100644
+index 000000000000..a8aa74ed1988
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-pwm.dtso
+@@ -0,0 +1,25 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h6-pwm";
++
++	fragment@0 {
++		target = <&pio>;
++		__overlay__ {
++			pwm_pin: pwm-pin {
++				pins = "PD22";
++				function = "pwm";
++			};
++		};
++	};
++
++	fragment@1 {
++		target = <&pwm>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&pwm_pin>;
++			status = "okay";
++		};
++	};
++};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/Optimize-TSC2007-touchscreen-add-polling-method.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/Optimize-TSC2007-touchscreen-add-polling-method.patch
new file mode 100644
index 000000000000..7ab9da466e9b
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/Optimize-TSC2007-touchscreen-add-polling-method.patch
@@ -0,0 +1,195 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Alan <Alan>
+Date: Sat, 20 May 2023 14:44:07 +0800
+Subject: Optimize: TSC2007 touchscreen add polling method
+
+---
+ drivers/input/touchscreen/tsc2007.h      |   6 +
+ drivers/input/touchscreen/tsc2007_core.c | 110 +++++++++-
+ 2 files changed, 108 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/input/touchscreen/tsc2007.h b/drivers/input/touchscreen/tsc2007.h
+index 111111111111..222222222222 100644
+--- a/drivers/input/touchscreen/tsc2007.h
++++ b/drivers/input/touchscreen/tsc2007.h
+@@ -66,10 +66,13 @@ struct tsc2007 {
+ 	u16			model;
+ 	u16			x_plate_ohms;
+ 	u16			max_rt;
++	u16			rt_thr;
++	u8			touched;
+ 	unsigned long		poll_period; /* in jiffies */
+ 	int			fuzzx;
+ 	int			fuzzy;
+ 	int			fuzzz;
++	bool			ignore_nak;
+ 
+ 	struct gpio_desc	*gpiod;
+ 	int			irq;
+@@ -81,6 +84,9 @@ struct tsc2007 {
+ 	void			(*clear_penirq)(void);
+ 
+ 	struct mutex		mlock;
++
++	struct timer_list timer;
++	struct work_struct work_i2c_poll;
+ };
+ 
+ int tsc2007_xfer(struct tsc2007 *tsc, u8 cmd);
+diff --git a/drivers/input/touchscreen/tsc2007_core.c b/drivers/input/touchscreen/tsc2007_core.c
+index 111111111111..222222222222 100644
+--- a/drivers/input/touchscreen/tsc2007_core.c
++++ b/drivers/input/touchscreen/tsc2007_core.c
+@@ -28,6 +28,8 @@
+ #include <linux/platform_data/tsc2007.h>
+ #include "tsc2007.h"
+ 
++#define POLL_INTERVAL_MS 17 /* 17ms = 60fps */
++
+ int tsc2007_xfer(struct tsc2007 *tsc, u8 cmd)
+ {
+ 	s32 data;
+@@ -172,6 +174,65 @@ static irqreturn_t tsc2007_soft_irq(int irq, void *handle)
+ 	return IRQ_HANDLED;
+ }
+ 
++static irqreturn_t tsc2007_soft_poll(int irq, void *handle)
++{
++	struct tsc2007 *ts = handle;
++	struct input_dev *input = ts->input;
++	struct ts_event tc;
++	u32 rt;
++
++	if(!ts->stopped) {
++
++		mutex_lock(&ts->mlock);
++		tsc2007_read_values(ts, &tc);
++		mutex_unlock(&ts->mlock);
++
++		rt = tsc2007_calculate_resistance(ts, &tc);
++
++		if (rt == 0 || rt == 256) {
++
++			/*
++				* Sample found inconsistent by debouncing or pressure is
++				* beyond the maximum. Don't report it to user space,
++				* repeat at least once more the measurement.
++				*/
++			dev_dbg(&ts->client->dev, "ignored pressure %d\n", rt);
++
++		} else {
++
++			if (rt < ts->rt_thr) {
++
++				dev_dbg(&ts->client->dev,
++					"DOWN point(%4d,%4d), resistance (%4u)\n",
++					tc.x, tc.y, rt);
++
++				rt = ts->max_rt - rt;
++
++				input_report_key(input, BTN_TOUCH, 1);
++				input_report_abs(input, ABS_X, tc.y);
++				input_report_abs(input, ABS_Y, 4096 - tc.x);
++				input_report_abs(input, ABS_PRESSURE, rt);
++
++				input_sync(input);
++				ts->touched = 1;
++
++			} else if (ts->touched == 1) {
++
++				dev_dbg(&ts->client->dev, "UP\n");
++
++				input_report_key(input, BTN_TOUCH, 0);
++				input_report_abs(input, ABS_PRESSURE, 0);
++				input_sync(input);
++				ts->touched = 0;
++			}
++		}
++
++
++	}
++
++	return IRQ_HANDLED;
++}
++
+ static void tsc2007_stop(struct tsc2007 *ts)
+ {
+ 	ts->stopped = true;
+@@ -216,11 +277,32 @@ static int tsc2007_get_pendown_state_gpio(struct device *dev)
+ 	return gpiod_get_value_cansleep(ts->gpiod);
+ }
+ 
++static void tsc2007_ts_irq_poll_timer(struct timer_list *t)
++{
++	struct tsc2007 *ts = from_timer(ts, t, timer);
++
++	schedule_work(&ts->work_i2c_poll);
++	mod_timer(&ts->timer, jiffies + msecs_to_jiffies(POLL_INTERVAL_MS));
++}
++
++static void tsc2007_ts_work_i2c_poll(struct work_struct *work)
++{
++	struct tsc2007 *ts = container_of(work,
++			struct tsc2007, work_i2c_poll);
++
++	tsc2007_soft_poll(0, ts);
++}
++
+ static int tsc2007_probe_properties(struct device *dev, struct tsc2007 *ts)
+ {
+ 	u32 val32;
+ 	u64 val64;
+ 
++	ts->ignore_nak = device_property_read_bool(dev, "i2c,ignore-nak");
++
++	if (!device_property_read_u32(dev, "ti,rt-thr", &val32))
++		ts->rt_thr = val32;
++
+ 	if (!device_property_read_u32(dev, "ti,max-rt", &val32))
+ 		ts->max_rt = val32;
+ 	else
+@@ -317,6 +399,9 @@ static int tsc2007_probe(struct i2c_client *client)
+ 	if (!input_dev)
+ 		return -ENOMEM;
+ 
++	if (ts->ignore_nak)
++		client->flags |= I2C_M_IGNORE_NAK;
++
+ 	i2c_set_clientdata(client, ts);
+ 
+ 	ts->client = client;
+@@ -362,14 +447,23 @@ static int tsc2007_probe(struct i2c_client *client)
+ 			pdata->init_platform_hw();
+ 	}
+ 
+-	err = devm_request_threaded_irq(&client->dev, ts->irq,
+-					NULL, tsc2007_soft_irq,
+-					IRQF_ONESHOT,
+-					client->dev.driver->name, ts);
+-	if (err) {
+-		dev_err(&client->dev, "Failed to request irq %d: %d\n",
+-			ts->irq, err);
+-		return err;
++	if (ts->gpiod) {
++		err = devm_request_threaded_irq(&client->dev, ts->irq,
++						NULL, tsc2007_soft_irq,
++						IRQF_ONESHOT,
++						client->dev.driver->name, ts);
++		if (err) {
++			dev_err(&client->dev, "Failed to request irq %d: %d\n",
++				ts->irq, err);
++			return err;
++		}
++	} else {
++		INIT_WORK(&ts->work_i2c_poll,
++			  tsc2007_ts_work_i2c_poll);
++		timer_setup(&ts->timer, tsc2007_ts_irq_poll_timer, 0);
++		ts->timer.expires = jiffies +
++					msecs_to_jiffies(POLL_INTERVAL_MS);
++		add_timer(&ts->timer);
+ 	}
+ 
+ 	tsc2007_stop(ts);
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/Revert-drm-sun4i-hdmi-switch-to-struct-drm_edid.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/Revert-drm-sun4i-hdmi-switch-to-struct-drm_edid.patch
new file mode 100644
index 000000000000..3052f76cddb4
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/Revert-drm-sun4i-hdmi-switch-to-struct-drm_edid.patch
@@ -0,0 +1,49 @@
+From aec6c912e969a433916d8f40b663fb3bef57cdf3 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Mon, 9 Sep 2024 14:40:49 +0300
+Subject: Revert "drm/sun4i: hdmi: switch to struct drm_edid"
+
+This reverts commit bd730c77fa37fe2dda4b6e23f6921ef8a9b1bb97.
+---
+ drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c | 18 +++++++-----------
+ 1 file changed, 7 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c b/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
+index ab0938ba61f7..22024fd34b2b 100644
+--- a/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
++++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
+@@ -190,24 +190,20 @@ sun4i_hdmi_connector_clock_valid(const struct drm_connector *connector,
+ static int sun4i_hdmi_get_modes(struct drm_connector *connector)
+ {
+ 	struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector);
+-	const struct drm_edid *drm_edid;
++	struct edid *edid;
+ 	int ret;
+ 
+-	drm_edid = drm_edid_read_ddc(connector, hdmi->ddc_i2c ?: hdmi->i2c);
+-
+-	drm_edid_connector_update(connector, drm_edid);
+-	cec_s_phys_addr(hdmi->cec_adap,
+-			connector->display_info.source_physical_address, false);
+-
+-	if (!drm_edid)
++	edid = drm_get_edid(connector, hdmi->ddc_i2c ?: hdmi->i2c);
++	if (!edid)
+ 		return 0;
+ 
+ 	DRM_DEBUG_DRIVER("Monitor is %s monitor\n",
+ 			 connector->display_info.is_hdmi ? "an HDMI" : "a DVI");
+ 
+-
+-	ret = drm_edid_connector_add_modes(connector);
+-	drm_edid_free(drm_edid);
++	drm_connector_update_edid_property(connector, edid);
++	cec_s_phys_addr_from_edid(hdmi->cec_adap, edid);
++	ret = drm_add_edid_modes(connector, edid);
++	kfree(edid);
+ 
+ 	return ret;
+ }
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/Sound-for-H616-H618-Allwinner-SOCs.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/Sound-for-H616-H618-Allwinner-SOCs.patch
new file mode 100644
index 000000000000..73bc7abf29bc
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/Sound-for-H616-H618-Allwinner-SOCs.patch
@@ -0,0 +1,4239 @@
+From f49aad9da6e2829c87f3d87c2f983aec0f111a6a Mon Sep 17 00:00:00 2001
+From: Stephen Graf <stephen.graf@gmail.com>
+Date: Wed, 26 Mar 2025 17:06:51 +0000
+Subject: Sound for H616, H618 Allwinner SOCs
+
+The Linux kernel now (v6.13) provides an analog codec
+for H616 SoCs in sun41.codec.c. We will use it.
+
+ arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
+ arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi include/sound/soc-dai.h
+ sound/soc/Kconfig sound/soc/Makefile sound/soc/soc-core.c
+ sound/soc/sunxi_v2/Kconfig sound/soc/sunxi_v2/Makefile
+ sound/soc/sunxi_v2/drv_hdmi.h sound/soc/sunxi_v2/snd_sunxi_ahub.c
+ sound/soc/sunxi_v2/snd_sunxi_ahub.h sound/soc/sunxi_v2/snd_sunxi_ahub_dam.c
+ sound/soc/sunxi_v2/snd_sunxi_ahub_dam.h sound/soc/sunxi_v2/snd_sunxi_common.c
+ sound/soc/sunxi_v2/snd_sunxi_common.h sound/soc/sunxi_v2/snd_sunxi_log.h
+ sound/soc/sunxi_v2/snd_sunxi_mach.c sound/soc/sunxi_v2/snd_sunxi_mach.h
+ sound/soc/sunxi_v2/snd_sunxi_mach_utils.c
+ sound/soc/sunxi_v2/snd_sunxi_mach_utils.h
+
+Signed-off-by: Stephen Graf <stephen.graf@gmail.com>
+---
+ .../allwinner/sun50i-h616-orangepi-zero.dtsi  |   12 +
+ .../arm64/boot/dts/allwinner/sun50i-h616.dtsi |   60 +-
+ include/sound/soc-dai.h                       |   13 +
+ sound/soc/Kconfig                             |    1 +
+ sound/soc/Makefile                            |    1 +
+ sound/soc/soc-core.c                          |   25 +
+ sound/soc/sunxi_v2/Kconfig                    |   45 +
+ sound/soc/sunxi_v2/Makefile                   |   11 +
+ sound/soc/sunxi_v2/drv_hdmi.h                 |   63 +
+ sound/soc/sunxi_v2/snd_sunxi_ahub.c           | 1475 +++++++++++++++++
+ sound/soc/sunxi_v2/snd_sunxi_ahub.h           |   74 +
+ sound/soc/sunxi_v2/snd_sunxi_ahub_dam.c       |  532 ++++++
+ sound/soc/sunxi_v2/snd_sunxi_ahub_dam.h       |  294 ++++
+ sound/soc/sunxi_v2/snd_sunxi_common.c         |  267 +++
+ sound/soc/sunxi_v2/snd_sunxi_common.h         |   67 +
+ sound/soc/sunxi_v2/snd_sunxi_log.h            |   29 +
+ sound/soc/sunxi_v2/snd_sunxi_mach.c           |  479 ++++++
+ sound/soc/sunxi_v2/snd_sunxi_mach.h           |   20 +
+ sound/soc/sunxi_v2/snd_sunxi_mach_utils.c     |  422 +++++
+ sound/soc/sunxi_v2/snd_sunxi_mach_utils.h     |  116 ++
+ 20 files changed, 4005 insertions(+), 1 deletion(-)
+ create mode 100644 sound/soc/sunxi_v2/Kconfig
+ create mode 100644 sound/soc/sunxi_v2/Makefile
+ create mode 100644 sound/soc/sunxi_v2/drv_hdmi.h
+ create mode 100644 sound/soc/sunxi_v2/snd_sunxi_ahub.c
+ create mode 100644 sound/soc/sunxi_v2/snd_sunxi_ahub.h
+ create mode 100644 sound/soc/sunxi_v2/snd_sunxi_ahub_dam.c
+ create mode 100644 sound/soc/sunxi_v2/snd_sunxi_ahub_dam.h
+ create mode 100644 sound/soc/sunxi_v2/snd_sunxi_common.c
+ create mode 100644 sound/soc/sunxi_v2/snd_sunxi_common.h
+ create mode 100644 sound/soc/sunxi_v2/snd_sunxi_log.h
+ create mode 100644 sound/soc/sunxi_v2/snd_sunxi_mach.c
+ create mode 100644 sound/soc/sunxi_v2/snd_sunxi_mach.h
+ create mode 100644 sound/soc/sunxi_v2/snd_sunxi_mach_utils.c
+ create mode 100644 sound/soc/sunxi_v2/snd_sunxi_mach_utils.h
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
+index 60f643abb3eb..109c33c6558f 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
+@@ -110,6 +110,18 @@ &de {
+ 	status = "okay";
+ };
+ 
++&ahub_dam_plat {
++	status = "okay";
++};
++
++&ahub1_plat {
++	status = "okay";
++};
++
++&ahub1_mach {
++	status = "okay";
++};
++
+ &ehci1 {
+ 	status = "okay";
+ };
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+index 6c1f1087f199..954c8eab2c44 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+@@ -642,7 +642,8 @@ gic: interrupt-controller@3021000 {
+ 		};
+ 
+ 		iommu: iommu@30f0000 {
+-			compatible = "allwinner,sun50i-h616-iommu";
++			compatible = "allwinner,sun50i-h616-iommu",
++			             "allwinner,sun50i-h6-iommu";
+ 			reg = <0x030f0000 0x10000>;
+ 			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&ccu CLK_BUS_IOMMU>;
+@@ -1009,6 +1010,63 @@ codec: codec@5096000 {
+ 			status = "disabled";
+ 		};
+ 
++		ahub_dam_plat:ahub_dam_plat@5097000 {
++			#sound-dai-cells = <0>;
++			/* sound card without pcm for hardware mix setting */
++			compatible = "allwinner,sunxi-snd-plat-ahub_dam";
++			reg        = <0x05097000 0x1000>;
++			resets     = <&ccu RST_BUS_AUDIO_HUB>;
++			clocks     = <&ccu CLK_AUDIO_CODEC_1X>,
++				     <&ccu CLK_AUDIO_CODEC_4X>,
++				     <&ccu CLK_AUDIO_HUB>,
++				     <&ccu CLK_BUS_AUDIO_HUB>;
++                        clock-names =   "clk_pll_audio",
++					"clk_pll_audio_4x",
++					"clk_audio_hub",
++					"clk_bus_audio_hub";
++			status = "disabled";
++		};
++
++		ahub1_plat:ahub1_plat {
++			#sound-dai-cells = <0>;
++			compatible      = "allwinner,sunxi-snd-plat-ahub";
++			apb_num         = <1>;  /* for dma port 4 */
++			dmas            = <&dma 4>, <&dma 4>;
++			dma-names       = "tx", "rx";
++			playback_cma    = <128>;
++			capture_cma     = <128>;
++			tx_fifo_size    = <128>;
++			rx_fifo_size    = <128>;
++
++			tdm_num         = <1>;
++			tx_pin          = <0>;
++			rx_pin          = <0>;
++			status          = "disabled";
++		};
++
++		ahub1_mach:ahub1_mach {
++			compatible = "allwinner,sunxi-snd-mach";
++			soundcard-mach,name = "HDMI";
++
++			soundcard-mach,format           = "i2s";
++			soundcard-mach,frame-master     = <&ahub1_cpu>;
++			soundcard-mach,bitclock-master  = <&ahub1_cpu>;
++			/* soundcard-mach,frame-inversion; */
++			/* soundcard-mach,bitclock-inversion; */
++			soundcard-mach,slot-num         = <2>;
++			soundcard-mach,slot-width       = <32>;
++			status          = "disabled";
++			ahub1_cpu: soundcard-mach,cpu {
++				sound-dai = <&ahub1_plat>;
++				soundcard-mach,pll-fs   = <4>;
++				soundcard-mach,mclk-fs  = <0>;
++			};
++
++			ahub1_codec: soundcard-mach,codec {
++				sound-dai = <&hdmi>;
++			};
++		};
++
+ 		usbotg: usb@5100000 {
+ 			compatible = "allwinner,sun50i-h616-musb",
+ 				     "allwinner,sun8i-h3-musb";
+diff --git a/include/sound/soc-dai.h b/include/sound/soc-dai.h
+index a11501752637..eb1eb56a4a6d 100644
+--- a/include/sound/soc-dai.h
++++ b/include/sound/soc-dai.h
+@@ -413,6 +413,15 @@ struct snd_soc_dai_driver {
+ 	struct snd_soc_dobj dobj;
+ 	const struct of_phandle_args *dai_args;
+ 
++	/* DAI driver callbacks */
++	int (*probe)(struct snd_soc_dai *dai);
++	int (*remove)(struct snd_soc_dai *dai);
++	/* compress dai */
++	int (*compress_new)(struct snd_soc_pcm_runtime *rtd);
++	/* Optional Callback used at pcm creation*/
++	int (*pcm_new)(struct snd_soc_pcm_runtime *rtd,
++		       struct snd_soc_dai *dai);
++
+ 	/* ops */
+ 	const struct snd_soc_dai_ops *ops;
+ 	const struct snd_soc_cdai_ops *cops;
+@@ -423,6 +432,10 @@ struct snd_soc_dai_driver {
+ 	unsigned int symmetric_rate:1;
+ 	unsigned int symmetric_channels:1;
+ 	unsigned int symmetric_sample_bits:1;
++
++	/* probe ordering - for components with runtime dependencies */
++	int probe_order;
++	int remove_order;
+ };
+ 
+ /* for Playback/Capture */
+diff --git a/sound/soc/Kconfig b/sound/soc/Kconfig
+index 5efba76abb31..b1b4693ca49b 100644
+--- a/sound/soc/Kconfig
++++ b/sound/soc/Kconfig
+@@ -117,6 +117,7 @@ source "sound/soc/starfive/Kconfig"
+ source "sound/soc/sti/Kconfig"
+ source "sound/soc/stm/Kconfig"
+ source "sound/soc/sunxi/Kconfig"
++source "sound/soc/sunxi_v2/Kconfig"
+ source "sound/soc/tegra/Kconfig"
+ source "sound/soc/ti/Kconfig"
+ source "sound/soc/uniphier/Kconfig"
+diff --git a/sound/soc/Makefile b/sound/soc/Makefile
+index 08baaa11d813..ca53a0853e0f 100644
+--- a/sound/soc/Makefile
++++ b/sound/soc/Makefile
+@@ -70,6 +70,7 @@ obj-$(CONFIG_SND_SOC)	+= starfive/
+ obj-$(CONFIG_SND_SOC)	+= sti/
+ obj-$(CONFIG_SND_SOC)	+= stm/
+ obj-$(CONFIG_SND_SOC)	+= sunxi/
++obj-$(CONFIG_SND_SOC)	+= sunxi_v2/
+ obj-$(CONFIG_SND_SOC)	+= tegra/
+ obj-$(CONFIG_SND_SOC)	+= ti/
+ obj-$(CONFIG_SND_SOC)	+= uniphier/
+diff --git a/sound/soc/soc-core.c b/sound/soc/soc-core.c
+index 3c6d8aef4130..e81e3b32569c 100644
+--- a/sound/soc/soc-core.c
++++ b/sound/soc/soc-core.c
+@@ -2632,6 +2632,7 @@ struct snd_soc_dai *snd_soc_register_dai(struct snd_soc_component *component,
+ {
+ 	struct device *dev = component->dev;
+ 	struct snd_soc_dai *dai;
++        struct snd_soc_dai_ops *ops; /* REMOVE ME */
+ 
+ 	lockdep_assert_held(&client_mutex);
+ 
+@@ -2660,6 +2661,30 @@ struct snd_soc_dai *snd_soc_register_dai(struct snd_soc_component *component,
+ 	if (!dai->name)
+ 		return NULL;
+ 
++        /* REMOVE ME */
++        if (dai_drv->probe              ||
++            dai_drv->remove             ||
++            dai_drv->compress_new       ||
++            dai_drv->pcm_new            ||
++            dai_drv->probe_order        ||
++            dai_drv->remove_order) {
++
++                ops = devm_kzalloc(dev, sizeof(struct snd_soc_dai_ops), GFP_KERNEL);
++                if (!ops)
++                        return NULL;
++                if (dai_drv->ops)
++                        memcpy(ops, dai_drv->ops, sizeof(struct snd_soc_dai_ops));
++
++                ops->probe              = dai_drv->probe;
++                ops->remove             = dai_drv->remove;
++                ops->compress_new       = dai_drv->compress_new;
++                ops->pcm_new            = dai_drv->pcm_new;
++                ops->probe_order        = dai_drv->probe_order;
++                ops->remove_order       = dai_drv->remove_order;
++
++                dai_drv->ops = ops;
++        }
++
+ 	dai->component = component;
+ 	dai->dev = dev;
+ 	dai->driver = dai_drv;
+diff --git a/sound/soc/sunxi_v2/Kconfig b/sound/soc/sunxi_v2/Kconfig
+new file mode 100644
+index 000000000000..e5d4aff7e6ca
+--- /dev/null
++++ b/sound/soc/sunxi_v2/Kconfig
+@@ -0,0 +1,45 @@
++# common
++config SND_SOC_SUNXI_MACH
++	tristate
++
++# ahub dam
++config SND_SOC_SUNXI_AHUB_DAM
++	tristate
++
++config SND_SOC_SUNXI_INTERNALCODEC
++	tristate
++
++# menu select
++menu "Allwinner SoC Audio support V2"
++	depends on ARCH_SUNXI
++
++# aaudio
++config SND_SOC_SUNXI_AAUDIO
++	tristate "Allwinner AAUDIO support"
++	select REGMAP_MMIO
++	select SND_SOC_GENERIC_DMAENGINE_PCM
++	select SND_SOC_SUNXI_MACH
++	select SND_SOC_SUNXI_INTERNALCODEC
++	select SND_SUN4I_CODEC
++	depends on ARCH_SUNXI
++	help
++	    Select Y or M to support analog-audio Module in the Allwinner SoCs.
++
++# ahub
++config SND_SOC_SUNXI_AHUB
++	tristate "Allwinner AHUB Support"
++	select REGMAP_MMIO
++	select SND_SOC_GENERIC_DMAENGINE_PCM
++	select SND_SOC_SUNXI_MACH
++	select SND_SOC_SUNXI_AHUB_DAM
++	depends on ARCH_SUNXI
++	help
++	    Select Y or M to support audio-hub Module in Allwinner SoCs.
++
++config SND_SOC_SUNXI_DEBUG
++	tristate "Components Debug"
++	depends on SND_SOC_SUNXI_COMPONENTS
++	help
++	    Select Y or M to support debug components.
++
++endmenu
+diff --git a/sound/soc/sunxi_v2/Makefile b/sound/soc/sunxi_v2/Makefile
+new file mode 100644
+index 000000000000..c7c2ef8f9fe9
+--- /dev/null
++++ b/sound/soc/sunxi_v2/Makefile
+@@ -0,0 +1,11 @@
++# platform -> ahub
++snd_soc_sunxi_ahub_dam-objs			+= snd_sunxi_ahub_dam.o
++obj-$(CONFIG_SND_SOC_SUNXI_AHUB_DAM)		+= snd_soc_sunxi_ahub_dam.o
++
++snd_soc_sunxi_ahub-objs				+= snd_sunxi_ahub.o
++obj-$(CONFIG_SND_SOC_SUNXI_AHUB)		+= snd_soc_sunxi_ahub.o
++
++# common -> machine (note: Finally compile, save system startup time)
++snd_soc_sunxi_machine-objs			+= snd_sunxi_mach.o
++snd_soc_sunxi_machine-objs			+= snd_sunxi_mach_utils.o
++obj-$(CONFIG_SND_SOC_SUNXI_MACH)		+= snd_soc_sunxi_machine.o
+diff --git a/sound/soc/sunxi_v2/drv_hdmi.h b/sound/soc/sunxi_v2/drv_hdmi.h
+new file mode 100644
+index 000000000000..2e05489b01e1
+--- /dev/null
++++ b/sound/soc/sunxi_v2/drv_hdmi.h
+@@ -0,0 +1,63 @@
++/*
++ * Allwinner SoCs hdmi driver.
++ *
++ * Copyright (C) 2016 Allwinner.
++ *
++ * This file is licensed under the terms of the GNU General Public
++ * License version 2.  This program is licensed "as is" without any
++ * warranty of any kind, whether express or implied.
++ */
++
++#ifndef __DRV_HDMI_H__
++#define __DRV_HDMI_H__
++
++typedef struct {
++	__u8    hw_intf;        /* 0:iis  1:spdif 2:pcm */
++	__u16	fs_between;     /* fs */
++	__u32   sample_rate;    /*sample rate*/
++	__u8    clk_edge;       /* 0:*/
++	__u8    ch0_en;         /* 1 */
++	__u8    ch1_en;         /* 0 */
++	__u8	ch2_en;         /* 0 */
++	__u8	ch3_en;         /* 0 */
++	__u8	word_length;    /* 32 */
++	__u8    shift_ctl;      /* 0 */
++	__u8    dir_ctl;        /* 0 */
++	__u8    ws_pol;
++	__u8    just_pol;
++	__u8    channel_num;
++	__u8	data_raw;
++	__u8    sample_bit;
++	__u8    ca;     /* channel allocation */
++} hdmi_audio_t;
++
++typedef struct {
++	__s32 (*hdmi_audio_enable)(__u8 mode, __u8 channel);
++	__s32 (*hdmi_set_audio_para)(hdmi_audio_t *audio_para);
++	__s32 (*hdmi_is_playback)(void);
++} __audio_hdmi_func;
++
++enum hdmi_hpd_status {
++	STATUE_CLOSE = 0,
++	STATUE_OPEN = 1,
++};
++
++void audio_set_hdmi_func(__audio_hdmi_func *hdmi_func);
++#if defined(CONFIG_SND_SUNXI_SOC_AUDIOHUB_INTERFACE)
++void audio_set_muti_hdmi_func(__audio_hdmi_func *hdmi_func);
++#endif
++
++/******************** SND_HDMI for sunxi_v2 begain ***************************/
++#if IS_ENABLED(CONFIG_HDMI2_DISP2_SUNXI)
++extern int snd_hdmi_get_func(__audio_hdmi_func *hdmi_func);
++#else
++static inline int snd_hdmi_get_func(__audio_hdmi_func *hdmi_func)
++{
++		pr_err("HDMI Audio API is disable\n");
++
++			return -1;
++}
++#endif
++/******************** SND_HDMI for sunxi_v2 end ******************************/
++
++#endif
+diff --git a/sound/soc/sunxi_v2/snd_sunxi_ahub.c b/sound/soc/sunxi_v2/snd_sunxi_ahub.c
+new file mode 100644
+index 000000000000..6d4a847a928f
+--- /dev/null
++++ b/sound/soc/sunxi_v2/snd_sunxi_ahub.c
+@@ -0,0 +1,1475 @@
++/*
++ * sound\soc\sunxi\snd_sunxi_ahub.c
++ * (C) Copyright 2021-2025
++ * AllWinner Technology Co., Ltd. <www.allwinnertech.com>
++ * Dby <dby@allwinnertech.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ */
++
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/regulator/consumer.h>
++#include <linux/of.h>
++#include <linux/clk.h>
++#include <linux/reset.h>
++#include <linux/device.h>
++#include <linux/pinctrl/consumer.h>
++#include <linux/ioport.h>
++#include <linux/regmap.h>
++#include <linux/of_address.h>
++#include <linux/of_gpio.h>
++#include <sound/soc.h>
++#include <sound/pcm_params.h>
++#include <sound/dmaengine_pcm.h>
++
++#include "snd_sunxi_log.h"
++#include "snd_sunxi_ahub.h"
++
++#define HLOG           "AHUB"
++#define DRV_NAME       "sunxi-snd-plat-ahub"
++
++static int sunxi_ahub_dai_startup(struct snd_pcm_substream *substream,
++                                 struct snd_soc_dai *dai)
++{
++       struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai);
++       struct regmap *regmap = NULL;
++       unsigned int apb_num, tdm_num;
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       regmap = ahub_info->mem_info.regmap;
++       apb_num = ahub_info->dts_info.apb_num;
++       tdm_num = ahub_info->dts_info.tdm_num;
++
++       if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++               snd_soc_dai_set_dma_data(dai, substream,
++                                        &ahub_info->playback_dma_param);
++       } else {
++               snd_soc_dai_set_dma_data(dai, substream,
++                                        &ahub_info->capture_dma_param);
++       }
++
++       /* APBIF & I2S of RST and GAT */
++       if (tdm_num > 3 || apb_num > 2) {
++               SND_LOG_ERR(HLOG, "unspport tdm num or apbif num\n");
++               return -EINVAL;
++       }
++
++       if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++               regmap_update_bits(regmap, SUNXI_AHUB_RST,
++                                  0x1 << (APBIF_TXDIF0_RST - apb_num),
++                                  0x1 << (APBIF_TXDIF0_RST - apb_num));
++               regmap_update_bits(regmap, SUNXI_AHUB_GAT,
++                                  0x1 << (APBIF_TXDIF0_GAT - apb_num),
++                                  0x1 << (APBIF_TXDIF0_GAT - apb_num));
++       } else {
++               regmap_update_bits(regmap, SUNXI_AHUB_RST,
++                                  0x1 << (APBIF_RXDIF0_RST - apb_num),
++                                  0x1 << (APBIF_RXDIF0_RST - apb_num));
++               regmap_update_bits(regmap, SUNXI_AHUB_GAT,
++                                  0x1 << (APBIF_RXDIF0_GAT - apb_num),
++                                  0x1 << (APBIF_RXDIF0_GAT - apb_num));
++       }
++
++       return 0;
++}
++
++static int sunxi_ahub_dai_set_pll(struct snd_soc_dai *dai,
++                                 int pll_id, int source,
++                                 unsigned int freq_in, unsigned int freq_out)
++{
++       struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai);
++       struct sunxi_ahub_clk_info *clk_info = NULL;
++
++       SND_LOG_DEBUG(HLOG, "stream -> %s, freq_in ->%u, freq_out ->%u\n",
++                     pll_id ? "IN" : "OUT", freq_in, freq_out);
++
++       if (IS_ERR_OR_NULL(ahub_info)) {
++               SND_LOG_ERR(HLOG, "ahub_info is null.\n");
++               return -ENOMEM;
++       }
++       clk_info = &ahub_info->clk_info;
++
++       if (freq_in > 24576000) {
++               //if (clk_set_parent(clk_info->clk_module, clk_info->clk_pllx4)) {
++               //      SND_LOG_ERR(HLOG, "set parent of clk_module to pllx4 failed\n");
++               //      return -EINVAL;
++               //}
++
++               if (clk_set_rate(clk_info->clk_pll, freq_in)) {
++                       SND_LOG_ERR(HLOG, "freq : %u pllx4 clk unsupport\n", freq_in);
++                       return -EINVAL;
++               }
++       } else {
++               //if (clk_set_parent(clk_info->clk_module, clk_info->clk_pll)) {
++               //      SND_LOG_ERR(HLOG, "set parent of clk_module to pll failed\n");
++               //      return -EINVAL;
++               //}
++               if (clk_set_rate(clk_info->clk_pll, freq_in)) {
++                       SND_LOG_ERR(HLOG, "freq : %u pll clk unsupport\n", freq_in);
++                       return -EINVAL;
++               }
++       }
++       if (clk_set_rate(clk_info->clk_module, freq_out / 2)) {
++               SND_LOG_ERR(HLOG, "freq : %u module clk unsupport\n", freq_out);
++               return -EINVAL;
++       }
++
++       ahub_info->pllclk_freq = freq_in;
++       ahub_info->mclk_freq = freq_out;
++
++       return 0;
++}
++
++static int sunxi_ahub_dai_set_sysclk(struct snd_soc_dai *dai, int clk_id,
++                                    unsigned int freq, int dir)
++{
++       struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai);
++       struct regmap *regmap = NULL;
++       unsigned int tdm_num;
++       unsigned int mclk_ratio, mclk_ratio_map;
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       if (IS_ERR_OR_NULL(ahub_info)) {
++               SND_LOG_ERR(HLOG, "ahub_info is null.\n");
++               return -ENOMEM;
++       }
++       regmap = ahub_info->mem_info.regmap;
++       tdm_num = ahub_info->dts_info.tdm_num;
++
++       if (freq == 0) {
++               regmap_update_bits(regmap, SUNXI_AHUB_I2S_CLKD(tdm_num),
++                                  0x1 << I2S_CLKD_MCLK, 0x0 << I2S_CLKD_MCLK);
++               SND_LOG_DEBUG(HLOG, "mclk freq: 0\n");
++               return 0;
++       }
++       if (ahub_info->pllclk_freq == 0) {
++               SND_LOG_ERR(HLOG, "pllclk freq is invalid\n");
++               return -ENOMEM;
++       }
++       mclk_ratio = ahub_info->pllclk_freq / freq;
++
++       switch (mclk_ratio) {
++       case 1:
++               mclk_ratio_map = 1;
++               break;
++       case 2:
++               mclk_ratio_map = 2;
++               break;
++       case 4:
++               mclk_ratio_map = 3;
++               break;
++       case 6:
++               mclk_ratio_map = 4;
++               break;
++       case 8:
++               mclk_ratio_map = 5;
++               break;
++       case 12:
++               mclk_ratio_map = 6;
++               break;
++       case 16:
++               mclk_ratio_map = 7;
++               break;
++       case 24:
++               mclk_ratio_map = 8;
++               break;
++       case 32:
++               mclk_ratio_map = 9;
++               break;
++       case 48:
++               mclk_ratio_map = 10;
++               break;
++       case 64:
++               mclk_ratio_map = 11;
++               break;
++       case 96:
++               mclk_ratio_map = 12;
++               break;
++       case 128:
++               mclk_ratio_map = 13;
++               break;
++       case 176:
++               mclk_ratio_map = 14;
++               break;
++       case 192:
++               mclk_ratio_map = 15;
++               break;
++       default:
++               regmap_update_bits(regmap, SUNXI_AHUB_I2S_CLKD(tdm_num),
++                                  0x1 << I2S_CLKD_MCLK, 0x0 << I2S_CLKD_MCLK);
++               SND_LOG_ERR(HLOG, "mclk freq div unsupport\n");
++               return -EINVAL;
++       }
++
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_CLKD(tdm_num),
++                          0xf << I2S_CLKD_MCLKDIV,
++                          mclk_ratio_map << I2S_CLKD_MCLKDIV);
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_CLKD(tdm_num),
++                          0x1 << I2S_CLKD_MCLK, 0x1 << I2S_CLKD_MCLK);
++
++       return 0;
++}
++
++static int sunxi_ahub_dai_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
++{
++       struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai);
++       struct regmap *regmap = NULL;
++       unsigned int tdm_num;
++       unsigned int bclk_ratio;
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       if (IS_ERR_OR_NULL(ahub_info)) {
++               SND_LOG_ERR(HLOG, "ahub_info is null.\n");
++               return -ENOMEM;
++       }
++       regmap = ahub_info->mem_info.regmap;
++       tdm_num = ahub_info->dts_info.tdm_num;
++
++       /* ratio -> cpudai pllclk / pcm rate */
++       switch (ratio) {
++       case 1:
++               bclk_ratio = 1;
++               break;
++       case 2:
++               bclk_ratio = 2;
++               break;
++       case 4:
++               bclk_ratio = 3;
++               break;
++       case 6:
++               bclk_ratio = 4;
++               break;
++       case 8:
++               bclk_ratio = 5;
++               break;
++       case 12:
++               bclk_ratio = 6;
++               break;
++       case 16:
++               bclk_ratio = 7;
++               break;
++       case 24:
++               bclk_ratio = 8;
++               break;
++       case 32:
++               bclk_ratio = 9;
++               break;
++       case 48:
++               bclk_ratio = 10;
++               break;
++       case 64:
++               bclk_ratio = 11;
++               break;
++       case 96:
++               bclk_ratio = 12;
++               break;
++       case 128:
++               bclk_ratio = 13;
++               break;
++       case 176:
++               bclk_ratio = 14;
++               break;
++       case 192:
++               bclk_ratio = 15;
++               break;
++       default:
++               SND_LOG_ERR(HLOG, "bclk freq div unsupport\n");
++               return -EINVAL;
++       }
++
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_CLKD(tdm_num),
++                          0xf << I2S_CLKD_BCLKDIV,
++                          (bclk_ratio - 2) << I2S_CLKD_BCLKDIV);
++
++       return 0;
++}
++
++static int sunxi_ahub_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
++{
++       struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai);
++       struct regmap *regmap = NULL;
++       unsigned int tdm_num, tx_pin, rx_pin;
++       unsigned int mode, offset;
++       unsigned int lrck_polarity, brck_polarity;
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       ahub_info->fmt = fmt;
++
++       if (IS_ERR_OR_NULL(ahub_info)) {
++               SND_LOG_ERR(HLOG, "ahub_info is null.\n");
++               return -ENOMEM;
++       }
++       regmap = ahub_info->mem_info.regmap;
++       tdm_num = ahub_info->dts_info.tdm_num;
++       tx_pin = ahub_info->dts_info.tx_pin;
++       rx_pin = ahub_info->dts_info.rx_pin;
++
++       /* set TDM format */
++       switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
++       case    SND_SOC_DAIFMT_I2S:
++               mode = 1;
++               offset = 1;
++               break;
++       case    SND_SOC_DAIFMT_RIGHT_J:
++               mode = 2;
++               offset = 0;
++               break;
++       case    SND_SOC_DAIFMT_LEFT_J:
++               mode = 1;
++               offset = 0;
++               break;
++       case    SND_SOC_DAIFMT_DSP_A:
++               mode = 0;
++               offset = 1;
++               /* L data MSB after FRM LRC (short frame) */
++               regmap_update_bits(regmap, SUNXI_AHUB_I2S_FMT0(tdm_num),
++                                  0x1 << I2S_FMT0_LRCK_WIDTH,
++                                  0x0 << I2S_FMT0_LRCK_WIDTH);
++               break;
++       case    SND_SOC_DAIFMT_DSP_B:
++               mode = 0;
++               offset = 0;
++               /* L data MSB during FRM LRC (long frame) */
++               regmap_update_bits(regmap, SUNXI_AHUB_I2S_FMT0(tdm_num),
++                                  0x1 << I2S_FMT0_LRCK_WIDTH,
++                                  0x1 << I2S_FMT0_LRCK_WIDTH);
++               break;
++       default:
++               SND_LOG_ERR(HLOG, "format setting failed\n");
++               return -EINVAL;
++       }
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num),
++                          0x3 << I2S_CTL_MODE, mode << I2S_CTL_MODE);
++       /* regmap_update_bits(regmap, SUNXI_AHUB_I2S_OUT_SLOT(tdm_num, tx_pin),
++        *                 0x3 << I2S_OUT_OFFSET, offset << I2S_OUT_OFFSET);
++        */
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_OUT_SLOT(tdm_num, 0),
++                          0x3 << I2S_OUT_OFFSET, offset << I2S_OUT_OFFSET);
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_OUT_SLOT(tdm_num, 1),
++                          0x3 << I2S_OUT_OFFSET, offset << I2S_OUT_OFFSET);
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_OUT_SLOT(tdm_num, 2),
++                          0x3 << I2S_OUT_OFFSET, offset << I2S_OUT_OFFSET);
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_OUT_SLOT(tdm_num, 3),
++                          0x3 << I2S_OUT_OFFSET, offset << I2S_OUT_OFFSET);
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_IN_SLOT(tdm_num),
++                          0x3 << I2S_IN_OFFSET, offset << I2S_IN_OFFSET);
++
++       /* set lrck & bclk polarity */
++       switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
++       case    SND_SOC_DAIFMT_NB_NF:
++               lrck_polarity = 0;
++               brck_polarity = 0;
++               break;
++       case    SND_SOC_DAIFMT_NB_IF:
++               lrck_polarity = 1;
++               brck_polarity = 0;
++               break;
++       case    SND_SOC_DAIFMT_IB_NF:
++               lrck_polarity = 0;
++               brck_polarity = 1;
++               break;
++       case    SND_SOC_DAIFMT_IB_IF:
++               lrck_polarity = 1;
++               brck_polarity = 1;
++               break;
++       default:
++               SND_LOG_ERR(HLOG, "invert clk setting failed\n");
++               return -EINVAL;
++       }
++       if (((fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_DSP_A) ||
++           ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_DSP_B))
++               regmap_update_bits(regmap, SUNXI_AHUB_I2S_FMT0(tdm_num),
++                                  0x1 << I2S_FMT0_LRCK_POLARITY,
++                                  (lrck_polarity^1) << I2S_FMT0_LRCK_POLARITY);
++       else
++               regmap_update_bits(regmap, SUNXI_AHUB_I2S_FMT0(tdm_num),
++                                  0x1 << I2S_FMT0_LRCK_POLARITY,
++                                  lrck_polarity << I2S_FMT0_LRCK_POLARITY);
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_FMT0(tdm_num),
++                          0x1 << I2S_FMT0_BCLK_POLARITY,
++                          brck_polarity << I2S_FMT0_BCLK_POLARITY);
++
++       /* set master/slave */
++       switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
++       case    SND_SOC_DAIFMT_CBM_CFM:
++               /* lrck & bclk dir output */
++               regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num),
++                                  0x1 << I2S_CTL_CLK_OUT, 0x0 << I2S_CTL_CLK_OUT);
++               break;
++       case    SND_SOC_DAIFMT_CBS_CFS:
++               /* lrck & bclk dir input */
++               regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num),
++                                  0x1 << I2S_CTL_CLK_OUT, 0x1 << I2S_CTL_CLK_OUT);
++               break;
++       default:
++               SND_LOG_ERR(HLOG, "unknown master/slave format\n");
++               return -EINVAL;
++       }
++
++       return 0;
++}
++
++static int sunxi_ahub_dai_set_tdm_slot(struct snd_soc_dai *dai,
++                                      unsigned int tx_mask, unsigned int rx_mask,
++                                      int slots, int slot_width)
++{
++       struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai);
++       struct regmap *regmap = NULL;
++       unsigned int tdm_num, tx_pin, rx_pin;
++       unsigned int slot_width_map, lrck_width_map;
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       if (IS_ERR_OR_NULL(ahub_info)) {
++               SND_LOG_ERR(HLOG, "ahub_info is null\n");
++               return -ENOMEM;
++       }
++       regmap = ahub_info->mem_info.regmap;
++       tdm_num = ahub_info->dts_info.tdm_num;
++       tx_pin = ahub_info->dts_info.tx_pin;
++       rx_pin = ahub_info->dts_info.rx_pin;
++
++       switch (slot_width) {
++       case 8:
++               slot_width_map = 1;
++               break;
++       case 12:
++               slot_width_map = 2;
++               break;
++       case 16:
++               slot_width_map = 3;
++               break;
++       case 20:
++               slot_width_map = 4;
++               break;
++       case 24:
++               slot_width_map = 5;
++               break;
++       case 28:
++               slot_width_map = 6;
++               break;
++       case 32:
++               slot_width_map = 7;
++               break;
++       default:
++               SND_LOG_ERR(HLOG, "unknown slot width\n");
++               return -EINVAL;
++       }
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_FMT0(tdm_num),
++                          0x7 << I2S_FMT0_SW, slot_width_map << I2S_FMT0_SW);
++
++       /* bclk num of per channel
++        * I2S/RIGHT_J/LEFT_J   -> lrck long total is lrck_width_map * 2
++        * DSP_A/DAP_B          -> lrck long total is lrck_width_map * 1
++        */
++       switch (ahub_info->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
++       case    SND_SOC_DAIFMT_I2S:
++       case    SND_SOC_DAIFMT_RIGHT_J:
++       case    SND_SOC_DAIFMT_LEFT_J:
++               slots /= 2;
++               break;
++       case    SND_SOC_DAIFMT_DSP_A:
++       case    SND_SOC_DAIFMT_DSP_B:
++               break;
++       default:
++               SND_LOG_ERR(HLOG, "unsupoort format\n");
++               return -EINVAL;
++       }
++       lrck_width_map = slots * slot_width - 1;
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_FMT0(tdm_num),
++                          0x3ff << I2S_FMT0_LRCK_PERIOD,
++                          lrck_width_map << I2S_FMT0_LRCK_PERIOD);
++
++       return 0;
++}
++
++static int sunxi_ahub_dai_hw_params(struct snd_pcm_substream *substream,
++                                   struct snd_pcm_hw_params *params,
++                                   struct snd_soc_dai *dai)
++{
++       struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai);
++       struct regmap *regmap = NULL;
++       unsigned int apb_num, tdm_num, tx_pin, rx_pin;
++       unsigned int channels;
++       unsigned int channels_en[16] = {
++               0x0001, 0x0003, 0x0007, 0x000f, 0x001f, 0x003f, 0x007f, 0x00ff,
++               0x01ff, 0x03ff, 0x07ff, 0x0fff, 0x1fff, 0x3fff, 0x7fff, 0xffff
++       };
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       if (IS_ERR_OR_NULL(ahub_info)) {
++               SND_LOG_ERR(HLOG, "ahub_info is null.\n");
++               return -ENOMEM;
++       }
++       regmap = ahub_info->mem_info.regmap;
++       apb_num = ahub_info->dts_info.apb_num;
++       tdm_num = ahub_info->dts_info.tdm_num;
++       tx_pin = ahub_info->dts_info.tx_pin;
++       rx_pin = ahub_info->dts_info.rx_pin;
++
++       /* configure DMA */
++       switch (params_physical_width(params)) {
++       case 16:
++               ahub_info->playback_dma_param.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
++               ahub_info->capture_dma_param.addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
++               break;
++       case 24:
++       case 32:
++               ahub_info->playback_dma_param.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
++               ahub_info->capture_dma_param.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
++               break;
++       default:
++               dev_err(dai->dev, "Unsupported physical sample width: %d\n",
++                       params_physical_width(params));
++               return -EINVAL;
++       }
++
++       /* set bits */
++       switch (params_format(params)) {
++       case SNDRV_PCM_FORMAT_S16_LE:
++               /* apbifn bits */
++               if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++                       regmap_update_bits(regmap,
++                                          SUNXI_AHUB_APBIF_TX_CTL(apb_num),
++                                          0x7 << APBIF_TX_WS,
++                                          0x3 << APBIF_TX_WS);
++                       regmap_update_bits(regmap,
++                                          SUNXI_AHUB_APBIF_TXFIFO_CTL(apb_num),
++                                          0x1 << APBIF_TX_TXIM,
++                                          0x1 << APBIF_TX_TXIM);
++               } else {
++                       regmap_update_bits(regmap,
++                                          SUNXI_AHUB_APBIF_RX_CTL(apb_num),
++                                          0x7 << APBIF_RX_WS,
++                                          0x3 << APBIF_RX_WS);
++                       regmap_update_bits(regmap,
++                                          SUNXI_AHUB_APBIF_RXFIFO_CTL(apb_num),
++                                          0x3 << APBIF_RX_RXOM,
++                                          0x1 << APBIF_RX_RXOM);
++               }
++
++               regmap_update_bits(regmap,
++                                  SUNXI_AHUB_I2S_FMT0(tdm_num),
++                                  0x7 << I2S_FMT0_SR,
++                                  0x3 << I2S_FMT0_SR);
++               break;
++       case SNDRV_PCM_FORMAT_S20_3LE:
++       case SNDRV_PCM_FORMAT_S24_LE:
++               if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++                       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TX_CTL(apb_num),
++                                          0x7 << APBIF_TX_WS, 0x5 << APBIF_TX_WS);
++                       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TXFIFO_CTL(apb_num),
++                                          0x1 << APBIF_TX_TXIM, 0x1 << APBIF_TX_TXIM);
++               } else {
++                       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RX_CTL(apb_num),
++                                          0x7 << APBIF_RX_WS, 0x5 << APBIF_RX_WS);
++                       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RXFIFO_CTL(apb_num),
++                                          0x3 << APBIF_RX_RXOM, 0x1 << APBIF_RX_RXOM);
++               }
++               regmap_update_bits(regmap, SUNXI_AHUB_I2S_FMT0(tdm_num),
++                                  0x7 << I2S_FMT0_SR, 0x5 << I2S_FMT0_SR);
++               break;
++       case SNDRV_PCM_FORMAT_S32_LE:
++               if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++                       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TX_CTL(apb_num),
++                                          0x7 << APBIF_TX_WS, 0x7 << APBIF_TX_WS);
++                       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TXFIFO_CTL(apb_num),
++                                          0x1 << APBIF_TX_TXIM, 0x1 << APBIF_TX_TXIM);
++               } else {
++                       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RX_CTL(apb_num),
++                                          0x7 << APBIF_RX_WS, 0x7 << APBIF_RX_WS);
++                       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RXFIFO_CTL(apb_num),
++                                          0x3 << APBIF_RX_RXOM, 0x1 << APBIF_RX_RXOM);
++               }
++               regmap_update_bits(regmap, SUNXI_AHUB_I2S_FMT0(tdm_num),
++                                  0x7 << I2S_FMT0_SR, 0x7 << I2S_FMT0_SR);
++               break;
++       default:
++               SND_LOG_ERR(HLOG, "unrecognized format bits\n");
++               return -EINVAL;
++       }
++
++       /* set channels */
++       channels = params_channels(params);
++       if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++               /* apbifn channels */
++               regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TX_CTL(apb_num),
++                                  0xf << APBIF_TX_CHAN_NUM,
++                                  (channels - 1) << APBIF_TX_CHAN_NUM);
++               /* tdmn channels */
++               regmap_update_bits(regmap, SUNXI_AHUB_I2S_CHCFG(tdm_num),
++                                  0xf << I2S_CHCFG_TX_CHANNUM,
++                                  (channels - 1) << I2S_CHCFG_TX_CHANNUM);
++
++               regmap_update_bits(regmap,
++                                  SUNXI_AHUB_I2S_OUT_SLOT(tdm_num, tx_pin),
++                                  0xf << I2S_OUT_SLOT_NUM,
++                                  (channels - 1) << I2S_OUT_SLOT_NUM);
++               regmap_update_bits(regmap,
++                                  SUNXI_AHUB_I2S_OUT_SLOT(tdm_num, tx_pin),
++                                  0xffff << I2S_OUT_SLOT_EN,
++                                  channels_en[channels - 1] << I2S_OUT_SLOT_EN);
++       } else {
++               /* apbifn channels */
++               regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RX_CTL(apb_num),
++                                  0xf << APBIF_RX_CHAN_NUM,
++                                  (channels - 1) << APBIF_RX_CHAN_NUM);
++               /* tdmn channels */
++               regmap_update_bits(regmap, SUNXI_AHUB_I2S_CHCFG(tdm_num),
++                                  0xf << I2S_CHCFG_RX_CHANNUM,
++                                  (channels - 1) << I2S_CHCFG_RX_CHANNUM);
++               regmap_update_bits(regmap, SUNXI_AHUB_I2S_IN_SLOT(tdm_num),
++                                  0xf << I2S_IN_SLOT_NUM,
++                                  (channels - 1) << I2S_IN_SLOT_NUM);
++       }
++
++       return 0;
++}
++
++static void sunxi_ahub_dai_tx_route(struct sunxi_ahub_info *ahub_info,
++                                   bool enable)
++{
++       struct regmap *regmap = NULL;
++       unsigned int tdm_num, tx_pin;
++       unsigned int apb_num;
++
++       SND_LOG_DEBUG(HLOG, "%s\n", enable ? "on" : "off");
++
++       regmap = ahub_info->mem_info.regmap;
++       tdm_num = ahub_info->dts_info.tdm_num;
++       tx_pin = ahub_info->dts_info.tx_pin;
++       apb_num = ahub_info->dts_info.apb_num;
++
++       if (enable)
++               goto tx_route_enable;
++       else
++               goto tx_route_disable;
++
++tx_route_enable:
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num),
++                          0x1 << (I2S_CTL_SDO0_EN + tx_pin),
++                          0x1 << (I2S_CTL_SDO0_EN + tx_pin));
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num),
++                          0x1 << I2S_CTL_TXEN, 0x1 << I2S_CTL_TXEN);
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num),
++                          0x1 << I2S_CTL_OUT_MUTE, 0x0 << I2S_CTL_OUT_MUTE);
++       /* start apbif tx */
++       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TX_CTL(apb_num),
++                          0x1 << APBIF_TX_START, 0x1 << APBIF_TX_START);
++       /* enable tx drq */
++       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TX_IRQ_CTL(apb_num),
++                          0x1 << APBIF_TX_DRQ, 0x1 << APBIF_TX_DRQ);
++       return;
++
++tx_route_disable:
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num),
++                          0x1 << I2S_CTL_OUT_MUTE, 0x1 << I2S_CTL_OUT_MUTE);
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num),
++                          0x1 << I2S_CTL_TXEN, 0x0 << I2S_CTL_TXEN);
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num),
++                          0x1 << (I2S_CTL_SDO0_EN + tx_pin),
++                          0x0 << (I2S_CTL_SDO0_EN + tx_pin));
++       /* stop apbif tx */
++       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TX_CTL(apb_num),
++                          0x1 << APBIF_TX_START, 0x0 << APBIF_TX_START);
++       /* disable tx drq */
++       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TX_IRQ_CTL(apb_num),
++                          0x1 << APBIF_TX_DRQ, 0x0 << APBIF_TX_DRQ);
++       return;
++}
++
++static void sunxi_ahub_dai_rx_route(struct sunxi_ahub_info *ahub_info,
++                                   bool enable)
++{
++       struct regmap *regmap = NULL;
++       unsigned int tdm_num, rx_pin;
++       unsigned int apb_num;
++
++       SND_LOG_DEBUG(HLOG, "%s\n", enable ? "on" : "off");
++
++       regmap = ahub_info->mem_info.regmap;
++       tdm_num = ahub_info->dts_info.tdm_num;
++       rx_pin = ahub_info->dts_info.rx_pin;
++       apb_num = ahub_info->dts_info.apb_num;
++
++       if (enable)
++               goto rx_route_enable;
++       else
++               goto rx_route_disable;
++
++rx_route_enable:
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num),
++                          0x1 << (I2S_CTL_SDI0_EN + rx_pin),
++                          0x1 << (I2S_CTL_SDI0_EN + rx_pin));
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num),
++                          0x1 << I2S_CTL_RXEN, 0x1 << I2S_CTL_RXEN);
++       /* start apbif rx */
++       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RX_CTL(apb_num),
++                          0x1 << APBIF_RX_START, 0x1 << APBIF_RX_START);
++       /* enable rx drq */
++       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RX_IRQ_CTL(apb_num),
++                          0x1 << APBIF_RX_DRQ, 0x1 << APBIF_RX_DRQ);
++       return;
++
++rx_route_disable:
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num),
++                          0x1 << I2S_CTL_RXEN, 0x0 << I2S_CTL_RXEN);
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num),
++                          0x1 << (I2S_CTL_SDI0_EN + rx_pin),
++                          0x0 << (I2S_CTL_SDI0_EN + rx_pin));
++       /* stop apbif rx */
++       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RX_CTL(apb_num),
++                          0x1 << APBIF_RX_START, 0x0 << APBIF_RX_START);
++       /* disable rx drq */
++       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RX_IRQ_CTL(apb_num),
++                          0x1 << APBIF_RX_DRQ, 0x0 << APBIF_RX_DRQ);
++       return;
++}
++
++static int sunxi_ahub_dai_trigger(struct snd_pcm_substream *substream,
++                                 int cmd,
++                                 struct snd_soc_dai *dai)
++{
++       struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai);
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       if (IS_ERR_OR_NULL(ahub_info)) {
++               SND_LOG_ERR(HLOG, "ahub_info is null.\n");
++               return -ENOMEM;
++       }
++
++       switch (cmd) {
++       case    SNDRV_PCM_TRIGGER_START:
++       case    SNDRV_PCM_TRIGGER_RESUME:
++       case    SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
++               if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++                       sunxi_ahub_dai_tx_route(ahub_info, true);
++               } else {
++                       sunxi_ahub_dai_rx_route(ahub_info, true);
++               }
++               break;
++       case    SNDRV_PCM_TRIGGER_STOP:
++       case    SNDRV_PCM_TRIGGER_SUSPEND:
++       case    SNDRV_PCM_TRIGGER_PAUSE_PUSH:
++               if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++                       sunxi_ahub_dai_tx_route(ahub_info, false);
++               } else {
++                       sunxi_ahub_dai_rx_route(ahub_info, false);
++               }
++               break;
++       default:
++               return -EINVAL;
++       }
++
++       return 0;
++}
++
++static int sunxi_ahub_dai_prepare(struct snd_pcm_substream *substream,
++                                 struct snd_soc_dai *dai)
++{
++       struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai);
++       struct regmap *regmap = NULL;
++       unsigned int apb_num;
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       if (IS_ERR_OR_NULL(ahub_info)) {
++               SND_LOG_ERR(HLOG, "ahub_info is null.\n");
++               return -ENOMEM;
++       }
++       regmap = ahub_info->mem_info.regmap;
++       apb_num = ahub_info->dts_info.apb_num;
++
++       if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++               /* clear txfifo */
++               regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TXFIFO_CTL(apb_num),
++                                  0x1 << APBIF_TX_FTX, 0x1 << APBIF_TX_FTX);
++               /* clear tx o/u irq */
++               regmap_write(regmap, SUNXI_AHUB_APBIF_TX_IRQ_STA(apb_num),
++                            (0x1 << APBIF_TX_OV_PEND) | (0x1 << APBIF_TX_EM_PEND));
++               /* clear tx fifo cnt */
++               regmap_write(regmap, SUNXI_AHUB_APBIF_TXFIFO_CNT(apb_num), 0);
++       } else {
++               /* clear rxfifo */
++               regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RXFIFO_CTL(apb_num),
++                                  0x1 << APBIF_RX_FRX, 0x1 << APBIF_RX_FRX);
++               /* clear rx o/u irq */
++               regmap_write(regmap, SUNXI_AHUB_APBIF_RX_IRQ_STA(apb_num),
++                            (0x1 << APBIF_RX_UV_PEND) | (0x1 << APBIF_RX_AV_PEND));
++               /* clear rx fifo cnt */
++               regmap_write(regmap, SUNXI_AHUB_APBIF_RXFIFO_CNT(apb_num), 0);
++       }
++
++       return 0;
++}
++
++static void sunxi_ahub_dai_shutdown(struct snd_pcm_substream *substream,
++                                   struct snd_soc_dai *dai)
++{
++       struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai);
++       struct regmap *regmap = NULL;
++       unsigned int apb_num, tdm_num;
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       regmap = ahub_info->mem_info.regmap;
++       apb_num = ahub_info->dts_info.apb_num;
++       tdm_num = ahub_info->dts_info.tdm_num;
++
++       /* APBIF & I2S of RST and GAT */
++       if (tdm_num > 3 || apb_num > 2) {
++               SND_LOG_ERR(HLOG, "unspport tdm num or apbif num\n");
++               return;
++       }
++
++       if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
++               regmap_update_bits(regmap, SUNXI_AHUB_RST,
++                                  0x1 << (APBIF_TXDIF0_RST - apb_num),
++                                  0x0 << (APBIF_TXDIF0_RST - apb_num));
++               regmap_update_bits(regmap, SUNXI_AHUB_GAT,
++                                  0x1 << (APBIF_TXDIF0_GAT - apb_num),
++                                  0x0 << (APBIF_TXDIF0_GAT - apb_num));
++       } else {
++               regmap_update_bits(regmap, SUNXI_AHUB_RST,
++                                  0x1 << (APBIF_RXDIF0_RST - apb_num),
++                                  0x0 << (APBIF_RXDIF0_RST - apb_num));
++               regmap_update_bits(regmap, SUNXI_AHUB_GAT,
++                                  0x1 << (APBIF_RXDIF0_GAT - apb_num),
++                                  0x0 << (APBIF_RXDIF0_GAT - apb_num));
++       }
++}
++
++static const struct snd_soc_dai_ops sunxi_ahub_dai_ops = {
++        /* call by machine */
++        .set_pll        = sunxi_ahub_dai_set_pll,       // set pllclk
++        .set_sysclk     = sunxi_ahub_dai_set_sysclk,    // set mclk
++        .set_bclk_ratio = sunxi_ahub_dai_set_bclk_ratio,// set bclk freq
++        .set_tdm_slot   = sunxi_ahub_dai_set_tdm_slot,  // set slot num and width
++        .set_fmt        = sunxi_ahub_dai_set_fmt,       // set tdm fmt
++        /* call by asoc */
++        .startup        = sunxi_ahub_dai_startup,
++        .hw_params      = sunxi_ahub_dai_hw_params,     // set hardware params
++        .prepare        = sunxi_ahub_dai_prepare,       // clean irq and fifo
++        .trigger        = sunxi_ahub_dai_trigger,       // set drq
++        .shutdown       = sunxi_ahub_dai_shutdown,
++};
++
++static void snd_soc_sunxi_ahub_init(struct sunxi_ahub_info *ahub_info)
++{
++       struct regmap *regmap = NULL;
++       unsigned int apb_num, tdm_num, tx_pin, rx_pin;
++       unsigned int reg_val = 0;
++       unsigned int rx_pin_map = 0;
++       unsigned int tdm_to_apb = 0;
++       unsigned int apb_to_tdm = 0;
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       regmap = ahub_info->mem_info.regmap;
++       apb_num = ahub_info->dts_info.apb_num;
++       tdm_num = ahub_info->dts_info.tdm_num;
++       tx_pin = ahub_info->dts_info.tx_pin;
++       rx_pin = ahub_info->dts_info.rx_pin;
++
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num),
++                          0x1 << I2S_CTL_GEN, 0x1 << I2S_CTL_GEN);
++       regmap_update_bits(regmap, SUNXI_AHUB_RST,
++                          0x1 << (I2S0_RST - tdm_num),
++                          0x1 << (I2S0_RST - tdm_num));
++       regmap_update_bits(regmap, SUNXI_AHUB_GAT,
++                          0x1 << (I2S0_GAT - tdm_num),
++                          0x1 << (I2S0_GAT - tdm_num));
++
++       /* tdm tx channels map */
++       regmap_write(regmap, SUNXI_AHUB_I2S_OUT_CHMAP0(tdm_num, tx_pin), 0x76543210);
++       regmap_write(regmap, SUNXI_AHUB_I2S_OUT_CHMAP1(tdm_num, tx_pin), 0xFEDCBA98);
++
++       /* tdm rx channels map */
++       rx_pin_map = (rx_pin << 4) | (rx_pin << 12) | (rx_pin << 20) | (rx_pin << 28);
++       reg_val = 0x03020100 | rx_pin_map;
++       regmap_write(regmap, SUNXI_AHUB_I2S_IN_CHMAP0(tdm_num), reg_val);
++       reg_val = 0x07060504 | rx_pin_map;
++       regmap_write(regmap, SUNXI_AHUB_I2S_IN_CHMAP1(tdm_num), reg_val);
++       reg_val = 0x0B0A0908 | rx_pin_map;
++       regmap_write(regmap, SUNXI_AHUB_I2S_IN_CHMAP2(tdm_num), reg_val);
++       reg_val = 0x0F0E0D0C | rx_pin_map;
++       regmap_write(regmap, SUNXI_AHUB_I2S_IN_CHMAP3(tdm_num), reg_val);
++
++       /* tdm tx & rx data fmt
++        * 1. MSB first
++        * 2. transfer 0 after each sample in each slot
++        * 3. linear PCM
++        */
++       regmap_write(regmap, SUNXI_AHUB_I2S_FMT1(tdm_num), 0x30);
++
++       /* apbif tx & rx data fmt
++        * 1. MSB first
++        * 2. trigger level tx -> 0x20, rx -> 0x40
++        */
++       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TXFIFO_CTL(apb_num),
++                          0x1 << APBIF_TX_TXIM, 0x0 << APBIF_TX_TXIM);
++       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_TXFIFO_CTL(apb_num),
++                          0x3f << APBIF_TX_LEVEL, 0x20 << APBIF_TX_LEVEL);
++       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RXFIFO_CTL(apb_num),
++                          0x3 << APBIF_RX_RXOM, 0x0 << APBIF_RX_RXOM);
++       regmap_update_bits(regmap, SUNXI_AHUB_APBIF_RXFIFO_CTL(apb_num),
++                          0x7f << APBIF_RX_LEVEL, 0x40 << APBIF_RX_LEVEL);
++
++       /* apbif <-> tdm */
++       switch (tdm_num)
++       {
++       case 0:
++               tdm_to_apb = APBIF_RX_I2S0_TXDIF;
++               break;
++       case 1:
++               tdm_to_apb = APBIF_RX_I2S1_TXDIF;
++               break;
++       case 2:
++               tdm_to_apb = APBIF_RX_I2S2_TXDIF;
++               break;
++       case 3:
++               tdm_to_apb = APBIF_RX_I2S3_TXDIF;
++               break;
++       default:
++               SND_LOG_ERR(HLOG, "unspport tdm num\n");
++               return;
++       }
++       regmap_write(regmap, SUNXI_AHUB_APBIF_RXFIFO_CONT(apb_num), 0x1 << tdm_to_apb);
++
++       switch (apb_num)
++       {
++       case 0:
++               apb_to_tdm = I2S_RX_APBIF_TXDIF0;
++               break;
++       case 1:
++               apb_to_tdm = I2S_RX_APBIF_TXDIF1;
++               break;
++       case 2:
++               apb_to_tdm = I2S_RX_APBIF_TXDIF2;
++               break;
++       default:
++               SND_LOG_ERR(HLOG, "unspport apb num\n");
++               return;
++       }
++       regmap_write(regmap, SUNXI_AHUB_I2S_RXCONT(tdm_num), 0x1 << apb_to_tdm);
++
++       return;
++}
++
++static int sunxi_ahub_dai_probe(struct snd_soc_dai *dai)
++{
++       struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai);
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       /* pcm_new will using the dma_param about the cma and fifo params. */
++       snd_soc_dai_init_dma_data(dai,
++                                 &ahub_info->playback_dma_param,
++                                 &ahub_info->capture_dma_param);
++
++       snd_soc_sunxi_ahub_init(ahub_info);
++
++       return 0;
++}
++
++static int sunxi_ahub_dai_remove(struct snd_soc_dai *dai)
++{
++       struct sunxi_ahub_info *ahub_info = snd_soc_dai_get_drvdata(dai);
++       struct regmap *regmap = NULL;
++       unsigned int tdm_num;
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       regmap = ahub_info->mem_info.regmap;
++       tdm_num = ahub_info->dts_info.tdm_num;
++
++       regmap_update_bits(regmap, SUNXI_AHUB_I2S_CTL(tdm_num),
++                          0x1 << I2S_CTL_GEN, 0x0 << I2S_CTL_GEN);
++       regmap_update_bits(regmap, SUNXI_AHUB_RST,
++                          0x1 << (I2S0_RST - tdm_num),
++                          0x0 << (I2S0_RST - tdm_num));
++       regmap_update_bits(regmap, SUNXI_AHUB_GAT,
++                          0x1 << (I2S0_GAT - tdm_num),
++                          0x0 << (I2S0_GAT - tdm_num));
++
++       return 0;
++}
++
++static struct snd_soc_dai_driver sunxi_ahub_dai = {
++       .name           = "ahub_plat",
++       .probe          = sunxi_ahub_dai_probe,
++       .remove         = sunxi_ahub_dai_remove,
++       .playback = {
++               .stream_name    = "Playback",
++               .channels_min   = 1,
++               .channels_max   = 2,
++               .rates          = SNDRV_PCM_RATE_8000_192000
++                               | SNDRV_PCM_RATE_KNOT,
++               .formats        = SNDRV_PCM_FMTBIT_S16_LE
++                               | SNDRV_PCM_FMTBIT_S24_LE
++                               | SNDRV_PCM_FMTBIT_S32_LE,
++       },
++       .capture = {
++               .stream_name    = "Capture",
++               .channels_min   = 1,
++               .channels_max   = 2,
++               .rates          = SNDRV_PCM_RATE_8000_192000
++                               | SNDRV_PCM_RATE_KNOT,
++               .formats        = SNDRV_PCM_FMTBIT_S16_LE
++                               | SNDRV_PCM_FMTBIT_S24_LE
++                               | SNDRV_PCM_FMTBIT_S32_LE,
++       },
++       .ops = &sunxi_ahub_dai_ops,
++};
++
++static int sunxi_ahub_probe(struct snd_soc_component *component)
++{
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       return 0;
++}
++
++static int sunxi_ahub_suspend(struct snd_soc_component *component)
++{
++       struct sunxi_ahub_info *ahub_info = snd_soc_component_get_drvdata(component);
++       struct regmap *regmap = NULL;
++       unsigned int apb_num, tdm_num;
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       regmap = ahub_info->mem_info.regmap;
++       apb_num = ahub_info->dts_info.apb_num;
++       tdm_num = ahub_info->dts_info.tdm_num;
++
++       return 0;
++}
++
++static int sunxi_ahub_resume(struct snd_soc_component *component)
++{
++       struct sunxi_ahub_info *ahub_info = snd_soc_component_get_drvdata(component);
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       snd_soc_sunxi_ahub_init(ahub_info);
++
++       return 0;
++}
++
++int sunxi_loopback_debug_get(struct snd_kcontrol *kcontrol,
++                            struct snd_ctl_elem_value *ucontrol)
++{
++       unsigned int reg_val;
++       struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
++       struct sunxi_ahub_info *ahub_info = snd_soc_component_get_drvdata(component);
++       struct sunxi_ahub_mem_info *mem_info = &ahub_info->mem_info;
++       struct sunxi_ahub_dts_info *dts_info = &ahub_info->dts_info;
++
++       regmap_read(mem_info->regmap, SUNXI_AHUB_I2S_CTL(dts_info->tdm_num), &reg_val);
++       ucontrol->value.integer.value[0] = ((reg_val & (1 << I2S_CTL_LOOP0)) ? 1 : 0);
++
++       return 0;
++}
++
++int sunxi_loopback_debug_set(struct snd_kcontrol *kcontrol,
++                            struct snd_ctl_elem_value *ucontrol)
++{
++       struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
++       struct sunxi_ahub_info *ahub_info = snd_soc_component_get_drvdata(component);
++       struct sunxi_ahub_mem_info *mem_info = &ahub_info->mem_info;
++       struct sunxi_ahub_dts_info *dts_info = &ahub_info->dts_info;
++
++       switch (ucontrol->value.integer.value[0]) {
++       case    0:
++               regmap_update_bits(mem_info->regmap,
++                                  SUNXI_AHUB_I2S_CTL(dts_info->tdm_num),
++                                  1 << I2S_CTL_LOOP0, 0 << I2S_CTL_LOOP0);
++               break;
++       case    1:
++               regmap_update_bits(mem_info->regmap,
++                                  SUNXI_AHUB_I2S_CTL(dts_info->tdm_num),
++                                  1 << I2S_CTL_LOOP0, 1 << I2S_CTL_LOOP0);
++               break;
++       default:
++               return -EINVAL;
++       }
++
++       return 0;
++}
++
++static const struct snd_kcontrol_new sunxi_ahub_controls[] = {
++       SOC_SINGLE_EXT("loopback debug", SND_SOC_NOPM, 0, 1, 0,
++                      sunxi_loopback_debug_get, sunxi_loopback_debug_set),
++};
++
++static struct snd_soc_component_driver sunxi_ahub_component = {
++       .name           = DRV_NAME,
++       .probe          = sunxi_ahub_probe,
++       .suspend        = sunxi_ahub_suspend,
++       .resume         = sunxi_ahub_resume,
++       .controls       = sunxi_ahub_controls,
++       .num_controls   = ARRAY_SIZE(sunxi_ahub_controls),
++};
++
++/*******************************************************************************
++ * for kernel source
++ ******************************************************************************/
++static int snd_soc_sunxi_ahub_pin_init(struct platform_device *pdev,
++                                      struct device_node *np,
++                                      struct sunxi_ahub_pinctl_info *pin_info)
++{
++       int ret = 0;
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       if (of_property_read_bool(np, "pinctrl_used")) {
++               pin_info->pinctrl_used = 1;
++       } else {
++               pin_info->pinctrl_used = 0;
++               SND_LOG_DEBUG(HLOG, "unused pinctrl\n");
++               return 0;
++       }
++
++       pin_info->pinctrl = devm_pinctrl_get(&pdev->dev);
++       if (IS_ERR_OR_NULL(pin_info->pinctrl)) {
++               SND_LOG_ERR(HLOG, "pinctrl get failed\n");
++               ret = -EINVAL;
++               return ret;
++       }
++       pin_info->pinstate = pinctrl_lookup_state(pin_info->pinctrl,
++                                                 PINCTRL_STATE_DEFAULT);
++       if (IS_ERR_OR_NULL(pin_info->pinstate)) {
++               SND_LOG_ERR(HLOG, "pinctrl default state get fail\n");
++               ret = -EINVAL;
++               goto err_loopup_pinstate;
++       }
++       pin_info->pinstate_sleep = pinctrl_lookup_state(pin_info->pinctrl,
++                                                       PINCTRL_STATE_SLEEP);
++       if (IS_ERR_OR_NULL(pin_info->pinstate_sleep)) {
++               SND_LOG_ERR(HLOG, "pinctrl sleep state get failed\n");
++               ret = -EINVAL;
++               goto err_loopup_pin_sleep;
++       }
++       ret = pinctrl_select_state(pin_info->pinctrl, pin_info->pinstate);
++       if (ret < 0) {
++               SND_LOG_ERR(HLOG, "daudio set pinctrl default state fail\n");
++               ret = -EBUSY;
++               goto err_pinctrl_select_default;
++       }
++
++       return 0;
++
++err_pinctrl_select_default:
++err_loopup_pin_sleep:
++err_loopup_pinstate:
++       devm_pinctrl_put(pin_info->pinctrl);
++       return ret;
++}
++
++static int snd_soc_sunxi_ahub_dts_params_init(struct platform_device *pdev,
++                                             struct device_node *np,
++                                             struct sunxi_ahub_dts_info *dts_info)
++{
++       int ret = 0;
++       unsigned int temp_val = 0;
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       /* get tdm fmt of apb_num & tdm_num & tx/rx_pin */
++       ret = of_property_read_u32(np, "apb_num", &temp_val);
++       if (ret < 0) {
++               SND_LOG_WARN(HLOG, "apb_num config missing\n");
++               dts_info->apb_num = 0;
++       } else {
++               if (temp_val > 2) {     /* APBIFn (n = 0~2) */
++                       dts_info->apb_num = 0;
++                       SND_LOG_WARN(HLOG, "apb_num config invalid\n");
++               } else {
++                       dts_info->apb_num = temp_val;
++               }
++       }
++       ret = of_property_read_u32(np, "tdm_num", &temp_val);
++       if (ret < 0) {
++               SND_LOG_WARN(HLOG, "tdm_num config missing\n");
++               dts_info->tdm_num = 0;
++       } else {
++               if (temp_val > 3) {     /* I2Sn (n = 0~3) */
++                       dts_info->tdm_num = 0;
++                       SND_LOG_WARN(HLOG, "tdm_num config invalid\n");
++               } else {
++                       dts_info->tdm_num = temp_val;
++               }
++       }
++       ret = of_property_read_u32(np, "tx_pin", &temp_val);
++       if (ret < 0) {
++               SND_LOG_WARN(HLOG, "tx_pin config missing\n");
++               dts_info->tx_pin = 0;
++       } else {
++               if (temp_val > 3) {     /* I2S_DOUTn (n = 0~3) */
++                       dts_info->tx_pin = 0;
++                       SND_LOG_WARN(HLOG, "tx_pin config invalid\n");
++               } else {
++                       dts_info->tx_pin = temp_val;
++               }
++       }
++       ret = of_property_read_u32(np, "rx_pin", &temp_val);
++       if (ret < 0) {
++               SND_LOG_WARN(HLOG, "rx_pin config missing\n");
++               dts_info->rx_pin = 0;
++       } else {
++               if (temp_val > 3) {     /* I2S_DINTn (n = 0~3) */
++                       dts_info->rx_pin = 0;
++                       SND_LOG_WARN(HLOG, "rx_pin config invalid\n");
++               } else {
++                       dts_info->rx_pin = temp_val;
++               }
++       }
++
++       SND_LOG_DEBUG(HLOG, "playback_cma : %lu\n", dts_info->playback_cma);
++       SND_LOG_DEBUG(HLOG, "capture_cma  : %lu\n", dts_info->capture_cma);
++       SND_LOG_DEBUG(HLOG, "tx_fifo_size : %lu\n", dts_info->playback_fifo_size);
++       SND_LOG_DEBUG(HLOG, "rx_fifo_size : %lu\n", dts_info->capture_fifo_size);
++       SND_LOG_DEBUG(HLOG, "apb_num      : %u\n", dts_info->apb_num);
++       SND_LOG_DEBUG(HLOG, "tdm_num      : %u\n", dts_info->tdm_num);
++       SND_LOG_DEBUG(HLOG, "tx_pin       : %u\n", dts_info->tx_pin);
++       SND_LOG_DEBUG(HLOG, "rx_pin       : %u\n", dts_info->rx_pin);
++
++       return 0;
++};
++
++static int snd_soc_sunxi_ahub_regulator_init(struct platform_device *pdev,
++                                            struct device_node *np,
++                                            struct sunxi_ahub_regulator_info *regulator_info)
++{
++       int ret = 0;
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       regulator_info->regulator_name = NULL;
++       if (of_property_read_string(np, "ahub_regulator", &regulator_info->regulator_name)) {
++               SND_LOG_DEBUG(HLOG, "regulator missing\n");
++               regulator_info->regulator = NULL;
++               return 0;
++       }
++
++       regulator_info->regulator = regulator_get(NULL, regulator_info->regulator_name);
++       if (IS_ERR_OR_NULL(regulator_info->regulator)) {
++               SND_LOG_ERR(HLOG, "get duaido vcc-pin failed\n");
++               ret = -EFAULT;
++               goto err_regulator_get;
++       }
++       ret = regulator_set_voltage(regulator_info->regulator, 3300000, 3300000);
++       if (ret < 0) {
++               SND_LOG_ERR(HLOG, "set duaido voltage failed\n");
++               ret = -EFAULT;
++               goto err_regulator_set_vol;
++       }
++       ret = regulator_enable(regulator_info->regulator);
++       if (ret < 0) {
++               SND_LOG_ERR(HLOG, "enable duaido vcc-pin failed\n");
++               ret = -EFAULT;
++               goto err_regulator_enable;
++       }
++
++       return 0;
++
++err_regulator_enable:
++err_regulator_set_vol:
++       if (regulator_info->regulator)
++               regulator_put(regulator_info->regulator);
++err_regulator_get:
++       return ret;
++};
++
++static void snd_soc_sunxi_dma_params_init(struct sunxi_ahub_info *ahub_info)
++{
++       struct resource *res = ahub_info->mem_info.res;
++       struct sunxi_ahub_dts_info *dts_info = &ahub_info->dts_info;
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       ahub_info->playback_dma_param.addr =
++               res->start + SUNXI_AHUB_APBIF_TXFIFO(dts_info->apb_num);
++       ahub_info->playback_dma_param.maxburst = 8;
++       //ahub_info->playback_dma_param.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
++
++       ahub_info->capture_dma_param.addr =
++               res->start + SUNXI_AHUB_APBIF_RXFIFO(dts_info->apb_num);
++       ahub_info->capture_dma_param.maxburst = 8;
++       //ahub_info->capture_dma_param.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
++};
++
++static int sunxi_ahub_dev_probe(struct platform_device *pdev)
++{
++       int ret;
++       struct device_node *np = pdev->dev.of_node;
++       struct sunxi_ahub_info *ahub_info = NULL;
++       struct sunxi_ahub_mem_info *mem_info = NULL;
++       struct sunxi_ahub_clk_info *clk_info = NULL;
++       struct sunxi_ahub_pinctl_info *pin_info = NULL;
++       struct sunxi_ahub_dts_info *dts_info = NULL;
++       struct sunxi_ahub_regulator_info *regulator_info = NULL;
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       ahub_info = devm_kzalloc(&pdev->dev,
++                                 sizeof(struct sunxi_ahub_info),
++                                 GFP_KERNEL);
++       if (IS_ERR_OR_NULL(ahub_info)) {
++               SND_LOG_ERR(HLOG, "alloc sunxi_ahub_info failed\n");
++               ret = -ENOMEM;
++               goto err_devm_malloc_sunxi_daudio;
++       }
++       dev_set_drvdata(&pdev->dev, ahub_info);
++       ahub_info->dev = &pdev->dev;
++       mem_info = &ahub_info->mem_info;
++       clk_info = &ahub_info->clk_info;
++       pin_info = &ahub_info->pin_info;
++       dts_info = &ahub_info->dts_info;
++       regulator_info = &ahub_info->regulator_info;
++
++       ret = snd_soc_sunxi_ahub_mem_get(mem_info);
++       if (ret) {
++               SND_LOG_ERR(HLOG, "remap get failed\n");
++               ret = -EINVAL;
++               goto err_snd_soc_sunxi_ahub_mem_get;
++       }
++
++       ret = snd_soc_sunxi_ahub_clk_get(clk_info);
++       if (ret) {
++               SND_LOG_ERR(HLOG, "clk get failed\n");
++               ret = -EINVAL;
++               goto err_snd_soc_sunxi_ahub_clk_get;
++       }
++
++       ret = snd_soc_sunxi_ahub_dts_params_init(pdev, np, dts_info);
++       if (ret) {
++               SND_LOG_ERR(HLOG, "dts init failed\n");
++               ret = -EINVAL;
++               goto err_snd_soc_sunxi_ahub_dts_params_init;
++       }
++
++       ret = snd_soc_sunxi_ahub_pin_init(pdev, np, pin_info);
++       if (ret) {
++               SND_LOG_ERR(HLOG, "pinctrl init failed\n");
++               ret = -EINVAL;
++               goto err_snd_soc_sunxi_ahub_pin_init;
++       }
++
++       ret = snd_soc_sunxi_ahub_regulator_init(pdev, np, regulator_info);
++       if (ret) {
++               SND_LOG_ERR(HLOG, "regulator_info init failed\n");
++               ret = -EINVAL;
++               goto err_snd_soc_sunxi_ahub_regulator_init;
++       }
++
++       snd_soc_sunxi_dma_params_init(ahub_info);
++
++       ret = snd_soc_register_component(&pdev->dev,
++                                        &sunxi_ahub_component,
++                                        &sunxi_ahub_dai, 1);
++       if (ret) {
++               SND_LOG_ERR(HLOG, "component register failed\n");
++               ret = -ENOMEM;
++               goto err_snd_soc_register_component;
++       }
++
++        ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
++        if (ret) {
++               SND_LOG_ERR(HLOG, "register ASoC platform failed\n");
++               ret = -ENOMEM;
++               goto err_snd_soc_sunxi_dma_platform_register;
++        }
++
++       SND_LOG_DEBUG(HLOG, "register ahub platform success\n");
++
++       return 0;
++
++err_snd_soc_sunxi_dma_platform_register:
++       snd_soc_unregister_component(&pdev->dev);
++err_snd_soc_register_component:
++err_snd_soc_sunxi_ahub_regulator_init:
++err_snd_soc_sunxi_ahub_dts_params_init:
++err_snd_soc_sunxi_ahub_pin_init:
++err_snd_soc_sunxi_ahub_clk_get:
++err_snd_soc_sunxi_ahub_mem_get:
++       devm_kfree(&pdev->dev, ahub_info);
++err_devm_malloc_sunxi_daudio:
++       of_node_put(np);
++       return ret;
++}
++
++static void sunxi_ahub_dev_remove(struct platform_device *pdev)
++{
++       struct sunxi_ahub_info *ahub_info = dev_get_drvdata(&pdev->dev);
++       struct sunxi_ahub_pinctl_info *pin_info = &ahub_info->pin_info;
++       struct sunxi_ahub_regulator_info *regulator_info = &ahub_info->regulator_info;
++
++       SND_LOG_DEBUG(HLOG, "\n");
++
++       snd_soc_unregister_component(&pdev->dev);
++
++       if (regulator_info->regulator) {
++               if (!IS_ERR_OR_NULL(regulator_info->regulator)) {
++                       regulator_disable(regulator_info->regulator);
++                       regulator_put(regulator_info->regulator);
++               }
++       }
++       if (pin_info->pinctrl_used) {
++               devm_pinctrl_put(pin_info->pinctrl);
++       }
++
++       devm_kfree(&pdev->dev, ahub_info);
++
++       SND_LOG_DEBUG(HLOG, "unregister ahub platform success\n");
++}
++
++static const struct of_device_id sunxi_ahub_of_match[] = {
++       { .compatible = "allwinner," DRV_NAME, },
++       {},
++};
++MODULE_DEVICE_TABLE(of, sunxi_ahub_of_match);
++
++static struct platform_driver sunxi_ahub_driver = {
++       .driver = {
++               .name           = DRV_NAME,
++               .owner          = THIS_MODULE,
++               .of_match_table = sunxi_ahub_of_match,
++       },
++       .probe  = sunxi_ahub_dev_probe,
++       .remove = sunxi_ahub_dev_remove,
++};
++
++int __init sunxi_ahub_dev_init(void)
++{
++       int ret;
++
++       ret = platform_driver_register(&sunxi_ahub_driver);
++       if (ret != 0) {
++               SND_LOG_ERR(HLOG, "platform driver register failed\n");
++               return -EINVAL;
++       }
++
++       return ret;
++}
++
++void __exit sunxi_ahub_dev_exit(void)
++{
++       platform_driver_unregister(&sunxi_ahub_driver);
++}
++
++late_initcall(sunxi_ahub_dev_init);
++module_exit(sunxi_ahub_dev_exit);
++
++MODULE_AUTHOR("Dby@allwinnertech.com");
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("sunxi soundcard platform of ahub");
+diff --git a/sound/soc/sunxi_v2/snd_sunxi_ahub.h b/sound/soc/sunxi_v2/snd_sunxi_ahub.h
+new file mode 100644
+index 000000000000..cd4be46b6ebf
+--- /dev/null
++++ b/sound/soc/sunxi_v2/snd_sunxi_ahub.h
+@@ -0,0 +1,74 @@
++/* sound\soc\sunxi\snd_sunxi_ahub.h
++ * (C) Copyright 2021-2025
++ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
++ * Dby <dby@allwinnertech.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ */
++
++#ifndef __SND_SUNXI_AHUB_H
++#define __SND_SUNXI_AHUB_H
++
++#include "snd_sunxi_ahub_dam.h"
++
++struct sunxi_ahub_pinctl_info {
++       struct pinctrl *pinctrl;
++       struct pinctrl_state *pinstate;
++       struct pinctrl_state *pinstate_sleep;
++
++       bool pinctrl_used;
++};
++
++struct sunxi_ahub_dts_info {
++       unsigned int dai_type;
++       unsigned int apb_num;
++       unsigned int tdm_num;
++       unsigned int tx_pin;
++       unsigned int rx_pin;
++
++       /* value must be (2^n)Kbyte */
++       size_t playback_cma;
++       size_t playback_fifo_size;
++       size_t capture_cma;
++       size_t capture_fifo_size;
++};
++
++struct sunxi_ahub_regulator_info {
++       struct regulator *regulator;
++       const char *regulator_name;
++};
++
++struct sunxi_ahub_info {
++       struct device *dev;
++
++       struct sunxi_ahub_mem_info mem_info;
++       struct sunxi_ahub_clk_info clk_info;
++       struct sunxi_ahub_pinctl_info pin_info;
++       struct sunxi_ahub_dts_info dts_info;
++       struct sunxi_ahub_regulator_info regulator_info;
++
++       //struct sunxi_dma_params playback_dma_param;
++       //struct sunxi_dma_params capture_dma_param;
++        struct snd_dmaengine_dai_dma_data playback_dma_param;
++        struct snd_dmaengine_dai_dma_data capture_dma_param;
++
++       /* for Hardware param setting */
++       unsigned int fmt;
++       unsigned int pllclk_freq;
++       unsigned int moduleclk_freq;
++       unsigned int mclk_freq;
++       unsigned int lrck_freq;
++       unsigned int bclk_freq;
++};
++
++int sunxi_loopback_debug_get(struct snd_kcontrol *kcontrol,
++                            struct snd_ctl_elem_value *ucontrol);
++int sunxi_loopback_debug_set(struct snd_kcontrol *kcontrol,
++                            struct snd_ctl_elem_value *ucontrol);
++int __init sunxi_ahub_dev_init(void);
++void __exit sunxi_ahub_dev_exit(void);
++
++#endif /* __SND_SUNXI_AHUB_H */
+diff --git a/sound/soc/sunxi_v2/snd_sunxi_ahub_dam.c b/sound/soc/sunxi_v2/snd_sunxi_ahub_dam.c
+new file mode 100644
+index 000000000000..f3c7bb3c7cd2
+--- /dev/null
++++ b/sound/soc/sunxi_v2/snd_sunxi_ahub_dam.c
+@@ -0,0 +1,532 @@
++/*
++ * sound\soc\sunxi\snd_sunxi_ahub_dam.c
++ * (C) Copyright 2021-2025
++ * AllWinner Technology Co., Ltd. <www.allwinnertech.com>
++ * Dby <dby@allwinnertech.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ */
++
++#include <linux/module.h>
++#include <sound/soc.h>
++#include <linux/regulator/consumer.h>
++#include <linux/of.h>
++#include <linux/clk.h>
++#include <linux/reset.h>
++#include <linux/device.h>
++#include <linux/ioport.h>
++#include <linux/regmap.h>
++#include <linux/of_address.h>
++#include <linux/of_gpio.h>
++#include <sound/soc.h>
++
++#include "snd_sunxi_log.h"
++#include "snd_sunxi_ahub_dam.h"
++
++#define HLOG		"AHUB_DAM"
++#define DRV_NAME	"sunxi-snd-plat-ahub_dam"
++
++static struct resource g_res;
++struct sunxi_ahub_mem_info g_mem_info = {
++	.res = &g_res,
++};
++static struct sunxi_ahub_clk_info g_clk_info;
++static struct regmap_config g_regmap_config = {
++	.reg_bits = 32,
++	.reg_stride = 4,
++	.val_bits = 32,
++	.max_register = SUNXI_AHUB_MAX_REG,
++	.cache_type = REGCACHE_NONE,
++};
++
++static struct snd_soc_dai_driver sunxi_ahub_dam_dai = {
++	.name           = "ahub_dam",
++};
++
++static int sunxi_ahub_dam_probe(struct snd_soc_component *component)
++{
++	SND_LOG_DEBUG(HLOG, "\n");
++
++	return 0;
++}
++
++static int sunxi_ahub_dam_suspend(struct snd_soc_component *component)
++{
++	struct sunxi_ahub_clk_info *clk_info = &g_clk_info;
++
++	SND_LOG_DEBUG(HLOG, "\n");
++
++	clk_disable_unprepare(clk_info->clk_module);
++	clk_disable_unprepare(clk_info->clk_pll);
++	//clk_disable_unprepare(clk_info->clk_pllx4);
++	clk_disable_unprepare(clk_info->clk_bus);
++	reset_control_assert(clk_info->clk_rst);
++
++	return 0;
++}
++
++static int sunxi_ahub_dam_resume(struct snd_soc_component *component)
++{
++	struct sunxi_ahub_clk_info *clk_info = &g_clk_info;
++
++	SND_LOG_DEBUG(HLOG, "\n");
++
++	if (reset_control_deassert(clk_info->clk_rst)) {
++		SND_LOG_ERR(HLOG, "clk rst deassert failed\n");
++		return -EINVAL;
++	}
++	if (clk_prepare_enable(clk_info->clk_bus)) {
++		SND_LOG_ERR(HLOG, "clk bus enable failed\n");
++		return -EBUSY;
++	}
++	if (clk_prepare_enable(clk_info->clk_pll)) {
++		SND_LOG_ERR(HLOG, "clk_pll enable failed\n");
++		return -EBUSY;
++	}
++	//if (clk_prepare_enable(clk_info->clk_pllx4)) {
++	//	SND_LOG_ERR(HLOG, "clk_pllx4 enable failed\n");
++	//	return -EBUSY;
++	//}
++	if (clk_prepare_enable(clk_info->clk_module)) {
++		SND_LOG_ERR(HLOG, "clk_module enable failed\n");
++		return -EBUSY;
++	}
++
++	return 0;
++}
++
++struct str_conv {
++	char *str;
++	unsigned int reg;
++};
++static struct str_conv ahub_mux_name[] = {
++	{"APBIF0 Src Select",	SUNXI_AHUB_APBIF_RXFIFO_CONT(0)},
++	{"APBIF1 Src Select",	SUNXI_AHUB_APBIF_RXFIFO_CONT(1)},
++	{"APBIF2 Src Select",	SUNXI_AHUB_APBIF_RXFIFO_CONT(2)},
++	{"I2S0 Src Select",	SUNXI_AHUB_I2S_RXCONT(0)},
++	{"I2S1 Src Select",	SUNXI_AHUB_I2S_RXCONT(1)},
++	{"I2S2 Src Select",	SUNXI_AHUB_I2S_RXCONT(2)},
++	{"I2S3 Src Select",	SUNXI_AHUB_I2S_RXCONT(3)},
++	{"DAM0C0 Src Select",	SUNXI_AHUB_DAM_RX0_SRC(0)},
++	{"DAM0C1 Src Select",	SUNXI_AHUB_DAM_RX1_SRC(0)},
++	{"DAM0C2 Src Select",	SUNXI_AHUB_DAM_RX2_SRC(0)},
++	{"DAM1C0 Src Select",	SUNXI_AHUB_DAM_RX0_SRC(1)},
++	{"DAM1C1 Src Select",	SUNXI_AHUB_DAM_RX1_SRC(1)},
++	{"DAM1C2 Src Select",	SUNXI_AHUB_DAM_RX2_SRC(1)},
++};
++static const char *ahub_mux_text[] = {
++	"NONE",
++	"APBIF_TXDIF0",
++	"APBIF_TXDIF1",
++	"APBIF_TXDIF2",
++	"I2S0_TXDIF",
++	"I2S1_TXDIF",
++	"I2S2_TXDIF",
++	"I2S3_TXDIF",
++	"DAM0_TXDIF",
++	"DAM1_TXDIF",
++};
++static const unsigned int ahub_mux_values[] = {
++	0,
++	1 << I2S_RX_APBIF_TXDIF0,
++	1 << I2S_RX_APBIF_TXDIF1,
++	1 << I2S_RX_APBIF_TXDIF2,
++	1 << I2S_RX_I2S0_TXDIF,
++	1 << I2S_RX_I2S1_TXDIF,
++	1 << I2S_RX_I2S2_TXDIF,
++	1 << I2S_RX_I2S3_TXDIF,
++	1 << I2S_RX_DAM0_TXDIF,
++	1 << I2S_RX_DAM1_TXDIF,
++};
++static SOC_ENUM_SINGLE_EXT_DECL(ahub_mux, ahub_mux_text);
++
++static int sunxi_ahub_mux_get(struct snd_kcontrol *kcontrol,
++			      struct snd_ctl_elem_value *ucontrol)
++{
++	int i;
++	unsigned int reg_val;
++	unsigned int src_reg;
++	struct regmap *regmap = g_mem_info.regmap;
++
++	for (i = 0; i < ARRAY_SIZE(ahub_mux_name); i++) {
++		if (!strncmp(ahub_mux_name[i].str, kcontrol->id.name,
++			     strlen(ahub_mux_name[i].str))) {
++			src_reg = ahub_mux_name[i].reg;
++			regmap_read(regmap, src_reg, &reg_val);
++			reg_val &= 0xffffc000;
++			break;
++		}
++	}
++
++	for (i = 1; i < ARRAY_SIZE(ahub_mux_values); i++) {
++		if (reg_val & ahub_mux_values[i]) {
++			ucontrol->value.integer.value[0] = i;
++			return 0;
++		}
++	}
++	ucontrol->value.integer.value[0] = 0;
++
++	return 0;
++}
++
++static int sunxi_ahub_mux_set(struct snd_kcontrol *kcontrol,
++			      struct snd_ctl_elem_value *ucontrol)
++{
++	int i;
++	unsigned int src_reg, src_regbit;
++	struct regmap *regmap = g_mem_info.regmap;
++
++	if (ucontrol->value.integer.value[0] > ARRAY_SIZE(ahub_mux_name))
++		return -EINVAL;
++
++	src_regbit = ahub_mux_values[ucontrol->value.integer.value[0]];
++	for (i = 0; i < ARRAY_SIZE(ahub_mux_name); i++) {
++		if (!strncmp(ahub_mux_name[i].str, kcontrol->id.name,
++			     strlen(ahub_mux_name[i].str))) {
++			src_reg = ahub_mux_name[i].reg;
++			regmap_update_bits(regmap, src_reg, 0xffffc000, src_regbit);
++			break;
++		}
++	}
++
++	return 0;
++}
++
++static const struct snd_kcontrol_new sunxi_ahub_dam_controls[] = {
++	SOC_ENUM_EXT("APBIF0 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set),
++	SOC_ENUM_EXT("APBIF1 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set),
++	SOC_ENUM_EXT("APBIF2 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set),
++	SOC_ENUM_EXT("I2S0 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set),
++	SOC_ENUM_EXT("I2S1 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set),
++	SOC_ENUM_EXT("I2S2 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set),
++	SOC_ENUM_EXT("I2S3 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set),
++	SOC_ENUM_EXT("DAM0C0 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set),
++	SOC_ENUM_EXT("DAM0C1 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set),
++	SOC_ENUM_EXT("DAM0C2 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set),
++	SOC_ENUM_EXT("DAM1C0 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set),
++	SOC_ENUM_EXT("DAM1C1 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set),
++	SOC_ENUM_EXT("DAM1C2 Src Select", ahub_mux, sunxi_ahub_mux_get, sunxi_ahub_mux_set),
++};
++
++static struct snd_soc_component_driver sunxi_ahub_dam_dev = {
++	.name		= DRV_NAME,
++	.probe		= sunxi_ahub_dam_probe,
++	.suspend	= sunxi_ahub_dam_suspend,
++	.resume		= sunxi_ahub_dam_resume,
++	.controls	= sunxi_ahub_dam_controls,
++	.num_controls	= ARRAY_SIZE(sunxi_ahub_dam_controls),
++};
++
++/*******************************************************************************
++ * for kernel source
++ ******************************************************************************/
++int snd_soc_sunxi_ahub_mem_get(struct sunxi_ahub_mem_info *mem_info)
++{
++	SND_LOG_DEBUG(HLOG, "\n");
++
++	if (IS_ERR_OR_NULL(g_mem_info.regmap)) {
++		SND_LOG_ERR(HLOG, "regmap is invalid\n");
++		return -EINVAL;
++	}
++	if (IS_ERR_OR_NULL(g_mem_info.res)) {
++		SND_LOG_ERR(HLOG, "res is invalid\n");
++		return -EINVAL;
++	}
++
++	mem_info->regmap = g_mem_info.regmap;
++	mem_info->res = g_mem_info.res;
++
++	return 0;
++}
++EXPORT_SYMBOL_GPL(snd_soc_sunxi_ahub_mem_get);
++
++int snd_soc_sunxi_ahub_clk_get(struct sunxi_ahub_clk_info *clk_info)
++{
++	SND_LOG_DEBUG(HLOG, "\n");
++
++	if (IS_ERR_OR_NULL(g_clk_info.clk_pll)) {
++		SND_LOG_ERR(HLOG, "clk_pll is invalid\n");
++		return -EINVAL;
++	}
++	//if (IS_ERR_OR_NULL(g_clk_info.clk_pllx4)) {
++	//	SND_LOG_ERR(HLOG, "clk_pllx4 is invalid\n");
++	//	return -EINVAL;
++	//}
++	if (IS_ERR_OR_NULL(g_clk_info.clk_module)) {
++		SND_LOG_ERR(HLOG, "clk_module is invalid\n");
++		return -EINVAL;
++	}
++
++	clk_info->clk_pll = g_clk_info.clk_pll;
++	//clk_info->clk_pllx4 = g_clk_info.clk_pllx4;
++	clk_info->clk_module = g_clk_info.clk_module;
++
++	return 0;
++}
++EXPORT_SYMBOL_GPL(snd_soc_sunxi_ahub_clk_get);
++
++static int snd_soc_sunxi_ahub_mem_init(struct platform_device *pdev,
++				       struct device_node *np,
++				       struct sunxi_ahub_mem_info *mem_info)
++{
++	int ret = 0;
++
++	SND_LOG_DEBUG(HLOG, "\n");
++
++	ret = of_address_to_resource(np, 0, mem_info->res);
++	if (ret) {
++		SND_LOG_ERR(HLOG, "parse device node resource failed\n");
++		ret = -EINVAL;
++		goto err_of_addr_to_resource;
++	}
++
++	mem_info->memregion = devm_request_mem_region(&pdev->dev,
++					mem_info->res->start,
++					resource_size(mem_info->res),
++					DRV_NAME);
++	if (IS_ERR_OR_NULL(mem_info->memregion)) {
++		SND_LOG_ERR(HLOG, "memory region already claimed\n");
++		ret = -EBUSY;
++		goto err_devm_request_region;
++	}
++
++	mem_info->membase = devm_ioremap(&pdev->dev,
++					 mem_info->memregion->start,
++					 resource_size(mem_info->memregion));
++	if (IS_ERR_OR_NULL(mem_info->membase)) {
++		SND_LOG_ERR(HLOG, "ioremap failed\n");
++		ret = -EBUSY;
++		goto err_devm_ioremap;
++	}
++
++	mem_info->regmap = devm_regmap_init_mmio(&pdev->dev,
++						 mem_info->membase,
++						 &g_regmap_config);
++	if (IS_ERR_OR_NULL(mem_info->regmap)) {
++		SND_LOG_ERR(HLOG, "regmap init failed\n");
++		ret = -EINVAL;
++		goto err_devm_regmap_init;
++	}
++
++	return 0;
++
++err_devm_regmap_init:
++	devm_iounmap(&pdev->dev, mem_info->membase);
++err_devm_ioremap:
++	devm_release_mem_region(&pdev->dev, mem_info->memregion->start,
++				resource_size(mem_info->memregion));
++err_devm_request_region:
++err_of_addr_to_resource:
++	return ret;
++};
++
++static int snd_soc_sunxi_ahub_clk_init(struct platform_device *pdev,
++				       struct device_node *np,
++				       struct sunxi_ahub_clk_info *clk_info)
++{
++	int ret = 0;
++
++	SND_LOG_DEBUG(HLOG, "\n");
++
++	/* deassert rst clk */
++	clk_info->clk_rst = devm_reset_control_get(&pdev->dev, NULL);
++	if (IS_ERR_OR_NULL(clk_info->clk_rst)) {
++		SND_LOG_ERR(HLOG, "clk rst get failed\n");
++		ret = -EBUSY;
++		goto err_rst_clk;
++	}
++	if (reset_control_deassert(clk_info->clk_rst)) {
++		SND_LOG_ERR(HLOG, "deassert reset clk failed\n");
++		ret = -EBUSY;
++		goto err_rst_clk;
++	}
++
++	/* enable ahub bus clk */
++	clk_info->clk_bus = of_clk_get_by_name(np, "clk_bus_audio_hub");
++	if (IS_ERR_OR_NULL(clk_info->clk_bus)) {
++		SND_LOG_ERR(HLOG, "clk bus get failed\n");
++		ret = -EBUSY;
++		goto err_bus_clk;
++	}
++	if (clk_prepare_enable(clk_info->clk_bus)) {
++		SND_LOG_ERR(HLOG, "ahub clk bus enable failed\n");
++		ret = -EBUSY;
++		goto err_bus_clk;
++	}
++
++	/* get clk of ahub */
++	clk_info->clk_module = of_clk_get_by_name(np, "clk_audio_hub");
++	if (IS_ERR_OR_NULL(clk_info->clk_module)) {
++		SND_LOG_ERR(HLOG, "clk module get failed\n");
++		ret = -EBUSY;
++		goto err_module_clk;
++	}
++	clk_info->clk_pll = of_clk_get_by_name(np, "clk_pll_audio");
++	if (IS_ERR_OR_NULL(clk_info->clk_pll)) {
++		SND_LOG_ERR(HLOG, "clk pll get failed\n");
++		ret = -EBUSY;
++		goto err_pll_clk;
++	}
++	//clk_info->clk_pllx4 = of_clk_get_by_name(np, "clk_pll_audio_4x");
++	//if (IS_ERR_OR_NULL(clk_info->clk_pllx4)) {
++	//	SND_LOG_ERR(HLOG, "clk pllx4 get failed\n");
++	//	ret = -EBUSY;
++	//	goto err_pllx4_clk;
++	//}
++
++	/* set ahub clk parent */
++	//if (clk_set_parent(clk_info->clk_module, clk_info->clk_pllx4)) {
++	//	SND_LOG_ERR(HLOG, "set parent of clk_module to pllx4 failed\n");
++	//	ret = -EINVAL;
++	//	goto err_set_parent_clk;
++	//}
++
++	/* enable clk of ahub */
++	if (clk_prepare_enable(clk_info->clk_pll)) {
++		SND_LOG_ERR(HLOG, "clk_pll enable failed\n");
++		ret = -EBUSY;
++		goto err_pll_clk_enable;
++	}
++	//if (clk_prepare_enable(clk_info->clk_pllx4)) {
++	//	SND_LOG_ERR(HLOG, "clk_pllx4 enable failed\n");
++	//	ret = -EBUSY;
++	//	goto err_pllx4_clk_enable;
++	//}
++	if (clk_prepare_enable(clk_info->clk_module)) {
++		SND_LOG_ERR(HLOG, "clk_module enable failed\n");
++		ret = -EBUSY;
++		goto err_module_clk_enable;
++	}
++
++	return 0;
++
++err_module_clk_enable:
++//	clk_disable_unprepare(clk_info->clk_pllx4);
++//err_pllx4_clk_enable:
++	clk_disable_unprepare(clk_info->clk_pll);
++err_pll_clk_enable:
++//err_set_parent_clk:
++//	clk_put(clk_info->clk_pllx4);
++//err_pllx4_clk:
++//	clk_put(clk_info->clk_pll);
++err_pll_clk:
++	clk_put(clk_info->clk_module);
++err_module_clk:
++	clk_disable_unprepare(clk_info->clk_bus);
++	clk_put(clk_info->clk_bus);
++err_bus_clk:
++	reset_control_assert(clk_info->clk_rst);
++err_rst_clk:
++	return ret;
++}
++
++static int sunxi_ahub_dam_dev_probe(struct platform_device *pdev)
++{
++	int ret;
++	struct device_node *np = pdev->dev.of_node;
++
++	SND_LOG_DEBUG(HLOG, "\n");
++
++	ret = snd_soc_sunxi_ahub_mem_init(pdev, np, &g_mem_info);
++	if (ret) {
++		SND_LOG_ERR(HLOG, "remap init failed\n");
++		ret = -EINVAL;
++		goto err_snd_soc_sunxi_ahub_mem_init;
++	}
++
++	ret = snd_soc_sunxi_ahub_clk_init(pdev, np, &g_clk_info);
++	if (ret) {
++		SND_LOG_ERR(HLOG, "clk init failed\n");
++		ret = -EINVAL;
++		goto err_snd_soc_sunxi_ahub_clk_init;
++	}
++
++	ret = snd_soc_register_component(&pdev->dev,
++					 &sunxi_ahub_dam_dev,
++					 &sunxi_ahub_dam_dai, 1);
++	if (ret) {
++		SND_LOG_ERR(HLOG, "component register failed\n");
++		ret = -ENOMEM;
++		goto err_snd_soc_register_component;
++	}
++
++	SND_LOG_DEBUG(HLOG, "register ahub_dam platform success\n");
++
++	return 0;
++
++err_snd_soc_register_component:
++err_snd_soc_sunxi_ahub_clk_init:
++err_snd_soc_sunxi_ahub_mem_init:
++	of_node_put(np);
++	return ret;
++}
++
++static void sunxi_ahub_dam_dev_remove(struct platform_device *pdev)
++{
++	struct sunxi_ahub_mem_info *mem_info = &g_mem_info;
++	struct sunxi_ahub_clk_info *clk_info = &g_clk_info;
++
++	SND_LOG_DEBUG(HLOG, "\n");
++
++	snd_soc_unregister_component(&pdev->dev);
++
++	devm_iounmap(&pdev->dev, mem_info->membase);
++	devm_release_mem_region(&pdev->dev, mem_info->memregion->start,
++				resource_size(mem_info->memregion));
++
++	clk_disable_unprepare(clk_info->clk_module);
++	clk_put(clk_info->clk_module);
++	clk_disable_unprepare(clk_info->clk_pll);
++	clk_put(clk_info->clk_pll);
++	//clk_disable_unprepare(clk_info->clk_pllx4);
++	//clk_put(clk_info->clk_pllx4);
++	clk_disable_unprepare(clk_info->clk_bus);
++	clk_put(clk_info->clk_bus);
++	reset_control_assert(clk_info->clk_rst);
++
++	SND_LOG_DEBUG(HLOG, "unregister ahub_dam platform success\n");
++}
++
++static const struct of_device_id sunxi_ahub_dam_of_match[] = {
++	{ .compatible = "allwinner," DRV_NAME, },
++	{},
++};
++MODULE_DEVICE_TABLE(of, sunxi_ahub_dam_of_match);
++
++static struct platform_driver sunxi_ahub_dam_driver = {
++	.driver	= {
++		.name		= DRV_NAME,
++		.owner		= THIS_MODULE,
++		.of_match_table	= sunxi_ahub_dam_of_match,
++	},
++	.probe	= sunxi_ahub_dam_dev_probe,
++	.remove	= sunxi_ahub_dam_dev_remove,
++};
++
++int __init sunxi_ahub_dam_dev_init(void)
++{
++	int ret;
++
++	ret = platform_driver_register(&sunxi_ahub_dam_driver);
++	if (ret != 0) {
++		SND_LOG_ERR(HLOG, "platform driver register failed\n");
++		return -EINVAL;
++	}
++
++	return ret;
++}
++
++void __exit sunxi_ahub_dam_dev_exit(void)
++{
++	platform_driver_unregister(&sunxi_ahub_dam_driver);
++}
++
++late_initcall(sunxi_ahub_dam_dev_init);
++module_exit(sunxi_ahub_dam_dev_exit);
++
++MODULE_AUTHOR("Dby@allwinnertech.com");
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("sunxi soundcard platform of ahub_dam");
+diff --git a/sound/soc/sunxi_v2/snd_sunxi_ahub_dam.h b/sound/soc/sunxi_v2/snd_sunxi_ahub_dam.h
+new file mode 100644
+index 000000000000..436742d87e8f
+--- /dev/null
++++ b/sound/soc/sunxi_v2/snd_sunxi_ahub_dam.h
+@@ -0,0 +1,294 @@
++/* sound\soc\sunxi\snd_sunxi_ahub_dam.h
++ * (C) Copyright 2021-2025
++ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
++ * Dby <dby@allwinnertech.com>
++ *
++ * some simple description for this code
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ */
++#ifndef __SND_SUNXI_AHUB_DAM_H
++#define __SND_SUNXI_AHUB_DAM_H
++
++/* SUNXI Audio Hub registers list */
++#define SUNXI_AHUB_CTL				0x00
++#define SUNXI_AHUB_VER				0x04
++#define SUNXI_AHUB_RST				0x08
++#define SUNXI_AHUB_GAT				0x0c
++
++#define SUNXI_AHUB_APBIF_TX_CTL(n)		(0x10 + ((n) * 0x30))
++#define SUNXI_AHUB_APBIF_TX_IRQ_CTL(n)		(0x14 + ((n) * 0x30))
++#define SUNXI_AHUB_APBIF_TX_IRQ_STA(n)		(0x18 + ((n) * 0x30))
++
++#define SUNXI_AHUB_APBIF_TXFIFO_CTL(n)		(0x20 + ((n) * 0x30))
++#define SUNXI_AHUB_APBIF_TXFIFO_STA(n)		(0x24 + ((n) * 0x30))
++
++#define SUNXI_AHUB_APBIF_TXFIFO(n)		(0x30 + ((n) * 0x30))
++#define SUNXI_AHUB_APBIF_TXFIFO_CNT(n)		(0x34 + ((n) * 0x30))
++
++#define SUNXI_AHUB_APBIF_RX_CTL(n)		(0x100 + ((n) * 0x30))
++#define SUNXI_AHUB_APBIF_RX_IRQ_CTL(n)		(0x104 + ((n) * 0x30))
++#define SUNXI_AHUB_APBIF_RX_IRQ_STA(n)		(0x108 + ((n) * 0x30))
++
++#define SUNXI_AHUB_APBIF_RXFIFO_CTL(n)		(0x110 + ((n) * 0x30))
++#define SUNXI_AHUB_APBIF_RXFIFO_STA(n)		(0x114 + ((n) * 0x30))
++#define SUNXI_AHUB_APBIF_RXFIFO_CONT(n)		(0x118 + ((n) * 0x30))
++
++#define SUNXI_AHUB_APBIF_RXFIFO(n)		(0x120 + ((n) * 0x30))
++#define SUNXI_AHUB_APBIF_RXFIFO_CNT(n)		(0x124 + ((n) * 0x30))
++
++#define SUNXI_AHUB_I2S_CTL(n)			(0x200 + ((n) << 8))
++#define SUNXI_AHUB_I2S_FMT0(n)			(0x204 + ((n) << 8))
++#define SUNXI_AHUB_I2S_FMT1(n)			(0x208 + ((n) << 8))
++#define SUNXI_AHUB_I2S_CLKD(n)			(0x20c + ((n) << 8))
++
++#define SUNXI_AHUB_I2S_RXCONT(n)		(0x220 + ((n) << 8))
++#define SUNXI_AHUB_I2S_CHCFG(n)			(0x224 + ((n) << 8))
++#define SUNXI_AHUB_I2S_IRQ_CTL(n)		(0x228 + ((n) << 8))
++#define SUNXI_AHUB_I2S_IRQ_STA(n)		(0x22C + ((n) << 8))
++#define SUNXI_AHUB_I2S_OUT_SLOT(n, m)		(0x230 + ((n) << 8) + ((m) << 4))
++#define SUNXI_AHUB_I2S_OUT_CHMAP0(n, m)		(0x234 + ((n) << 8) + ((m) << 4))
++#define SUNXI_AHUB_I2S_OUT_CHMAP1(n, m)		(0x238 + ((n) << 8) + ((m) << 4))
++
++#define SUNXI_AHUB_I2S_IN_SLOT(n)		(0x270 + ((n) << 8))
++#define SUNXI_AHUB_I2S_IN_CHMAP0(n)		(0x274 + ((n) << 8))
++#define SUNXI_AHUB_I2S_IN_CHMAP1(n)		(0x278 + ((n) << 8))
++#define SUNXI_AHUB_I2S_IN_CHMAP2(n)		(0x27C + ((n) << 8))
++#define SUNXI_AHUB_I2S_IN_CHMAP3(n)		(0x280 + ((n) << 8))
++
++#define SUNXI_AHUB_DAM_CTL(n)			(0xA00 + ((n) << 7))
++
++#define SUNXI_AHUB_DAM_RX0_SRC(n)		(0xA10 + ((n) << 7))
++#define SUNXI_AHUB_DAM_RX1_SRC(n)		(0xA14 + ((n) << 7))
++#define SUNXI_AHUB_DAM_RX2_SRC(n)		(0xA18 + ((n) << 7))
++
++#define SUNXI_AHUB_DAM_MIX_CTL0(n)		(0xA30 + ((n) << 7))
++#define SUNXI_AHUB_DAM_MIX_CTL1(n)		(0xA34 + ((n) << 7))
++#define SUNXI_AHUB_DAM_MIX_CTL2(n)		(0xA38 + ((n) << 7))
++#define SUNXI_AHUB_DAM_MIX_CTL3(n)		(0xA3C + ((n) << 7))
++#define SUNXI_AHUB_DAM_MIX_CTL4(n)		(0xA40 + ((n) << 7))
++#define SUNXI_AHUB_DAM_MIX_CTL5(n)		(0xA44 + ((n) << 7))
++#define SUNXI_AHUB_DAM_MIX_CTL6(n)		(0xA48 + ((n) << 7))
++#define SUNXI_AHUB_DAM_MIX_CTL7(n)		(0xA4C + ((n) << 7))
++#define SUNXI_AHUB_DAM_GAIN_CTL0(n)		(0xA50 + ((n) << 7))
++#define SUNXI_AHUB_DAM_GAIN_CTL1(n)		(0xA54 + ((n) << 7))
++#define SUNXI_AHUB_DAM_GAIN_CTL2(n)		(0xA58 + ((n) << 7))
++#define SUNXI_AHUB_DAM_GAIN_CTL3(n)		(0xA5C + ((n) << 7))
++#define SUNXI_AHUB_DAM_GAIN_CTL4(n)		(0xA60 + ((n) << 7))
++#define SUNXI_AHUB_DAM_GAIN_CTL5(n)		(0xA64 + ((n) << 7))
++#define SUNXI_AHUB_DAM_GAIN_CTL6(n)		(0xA68 + ((n) << 7))
++#define SUNXI_AHUB_DAM_GAIN_CTL7(n)		(0xA6C + ((n) << 7))
++
++#define SUNXI_AHUB_MAX_REG			SUNXI_AHUB_DAM_GAIN_CTL7(1)
++
++/* SUNXI_AHUB_CTL */
++#define HDMI_SRC_SEL			0x04
++
++/* SUNXI_AHUB_RST */
++#define APBIF_TXDIF0_RST		31
++#define APBIF_TXDIF1_RST		30
++#define APBIF_TXDIF2_RST		29
++#define APBIF_RXDIF0_RST		27
++#define APBIF_RXDIF1_RST		26
++#define APBIF_RXDIF2_RST		25
++#define I2S0_RST			23
++#define I2S1_RST			22
++#define I2S2_RST			21
++#define I2S3_RST			20
++#define DAM0_RST			15
++#define DAM1_RST			14
++
++/* SUNXI_AHUB_GAT */
++#define APBIF_TXDIF0_GAT		31
++#define APBIF_TXDIF1_GAT		30
++#define APBIF_TXDIF2_GAT		29
++#define APBIF_RXDIF0_GAT		27
++#define APBIF_RXDIF1_GAT		26
++#define APBIF_RXDIF2_GAT		25
++#define I2S0_GAT			23
++#define I2S1_GAT			22
++#define I2S2_GAT			21
++#define I2S3_GAT			20
++#define DAM0_GAT			15
++#define DAM1_GAT			14
++
++/* SUNXI_AHUB_APBIF_TX_CTL */
++#define APBIF_TX_WS			16
++#define APBIF_TX_CHAN_NUM		8
++#define	APBIF_TX_START			4
++
++/* SUNXI_AHUB_APBIF_TX_IRQ_CTL */
++#define APBIF_TX_DRQ			3
++#define APBIF_TX_OVEN			1
++#define APBIF_TX_EMEN			0
++
++/* SUNXI_AHUB_APBIF_TX_IRQ_STA */
++#define APBIF_TX_OV_PEND		2
++#define APBIF_TX_EM_PEND		0
++
++/* SUNXI_AHUB_APBIF_TXFIFO_CTL */
++#define APBIF_TX_FTX			12
++#define APBIF_TX_LEVEL			4
++#define APBIF_TX_TXIM			0
++
++/* SUNXI_AHUB_APBIF_TXFIFO_STA */
++#define APBIF_TX_EMPTY			8
++#define APBIF_TX_EMCNT			0
++
++/* SUNXI_AHUB_APBIF_RX_CTL */
++#define APBIF_RX_WS			16
++#define APBIF_RX_CHAN_NUM		8
++#define	APBIF_RX_START			4
++
++/* SUNXI_AHUB_APBIF_RX_IRQ_CTL */
++#define APBIF_RX_DRQ			3
++#define APBIF_RX_UVEN			2
++#define APBIF_RX_AVEN			0
++
++/* SUNXI_AHUB_APBIF_RX_IRQ_STA */
++#define APBIF_RX_UV_PEND		2
++#define APBIF_RX_AV_PEND		0
++
++/* SUNXI_AHUB_APBIF_RXFIFO_CTL */
++#define APBIF_RX_FRX			12
++#define APBIF_RX_LEVEL			4
++#define APBIF_RX_RXOM			0
++
++/* SUNXI_AHUB_APBIF_RXFIFO_STA */
++#define APBIF_RX_AVAIL			8
++#define APBIF_RX_AVCNT			0
++
++/* SUNXI_AHUB_APBIF_RXFIFO_CONT */
++#define APBIF_RX_APBIF_TXDIF0		31
++#define APBIF_RX_APBIF_TXDIF1		30
++#define APBIF_RX_APBIF_TXDIF2		29
++#define APBIF_RX_I2S0_TXDIF		27
++#define APBIF_RX_I2S1_TXDIF		26
++#define APBIF_RX_I2S2_TXDIF		25
++#define APBIF_RX_I2S3_TXDIF		23
++#define APBIF_RX_DAM0_TXDIF		19
++#define APBIF_RX_DAM1_TXDIF		15
++
++/* SUNXI_AHUB_I2S_CTL */
++#define I2S_CTL_LOOP3			23
++#define I2S_CTL_LOOP2			22
++#define I2S_CTL_LOOP1			21
++#define I2S_CTL_LOOP0			20
++#define I2S_CTL_SDI3_EN			15
++#define I2S_CTL_SDI2_EN			14
++#define I2S_CTL_SDI1_EN			13
++#define I2S_CTL_SDI0_EN			12
++#define I2S_CTL_CLK_OUT			18
++#define I2S_CTL_SDO3_EN			11
++#define I2S_CTL_SDO2_EN			10
++#define I2S_CTL_SDO1_EN			9
++#define I2S_CTL_SDO0_EN			8
++#define I2S_CTL_OUT_MUTE		6
++#define I2S_CTL_MODE			4
++#define I2S_CTL_TXEN			2
++#define I2S_CTL_RXEN			1
++#define I2S_CTL_GEN			0
++
++/* SUNXI_AHUB_I2S_FMT0 */
++#define I2S_FMT0_LRCK_WIDTH		30
++#define I2S_FMT0_LRCK_POLARITY		19
++#define I2S_FMT0_LRCK_PERIOD		8
++#define I2S_FMT0_BCLK_POLARITY		7
++#define I2S_FMT0_SR			4
++#define I2S_FMT0_EDGE			3
++#define I2S_FMT0_SW			0
++
++/* SUNXI_AHUB_I2S_FMT1 */
++#define I2S_FMT1_RX_LSB			7
++#define I2S_FMT1_TX_LSB			6
++#define I2S_FMT1_EXT			4
++#define I2S_FMT1_RX_PDM			2
++#define I2S_FMT1_TX_PDM			0
++
++/* SUNXI_AHUB_I2S_CLKD */
++#define I2S_CLKD_MCLK			8
++#define	I2S_CLKD_BCLKDIV		4
++#define I2S_CLKD_MCLKDIV		0
++
++/* SUNXI_AHUB_I2S_RXCONT */
++#define I2S_RX_APBIF_TXDIF0		31
++#define I2S_RX_APBIF_TXDIF1		30
++#define I2S_RX_APBIF_TXDIF2		29
++#define I2S_RX_I2S0_TXDIF		27
++#define I2S_RX_I2S1_TXDIF		26
++#define I2S_RX_I2S2_TXDIF		25
++#define I2S_RX_I2S3_TXDIF		23
++#define I2S_RX_DAM0_TXDIF		19
++#define I2S_RX_DAM1_TXDIF		15
++
++/* SUNXI_AHUB_I2S_CHCFG */
++#define I2S_CHCFG_HIZ			9
++#define	I2S_CHCFG_TX_STATE		8
++#define I2S_CHCFG_RX_CHANNUM		4
++#define I2S_CHCFG_TX_CHANNUM		0
++
++/* SUNXI_AHUB_I2S_IRQ_CTL */
++#define I2S_IRQ_RXOV_EN			1
++#define I2S_IRQ_TXUV_EN			0
++
++/* SUNXI_AHUB_I2S_IRQ_STA */
++#define I2S_IRQ_RXOV_PEND		1
++#define I2S_IRQ_TXUV_PEND		0
++
++/* SUNXI_AHUB_I2S_OUT_SLOT */
++#define I2S_OUT_OFFSET			20
++#define I2S_OUT_SLOT_NUM		16
++#define I2S_OUT_SLOT_EN			0
++
++/* SUNXI_AHUB_I2S_IN_SLOT */
++#define I2S_IN_OFFSET			20
++#define I2S_IN_SLOT_NUM			16
++
++/* SUNXI_AHUB_DAM_CTL */
++#define DAM_CTL_RX2_NUM			24
++#define DAM_CTL_RX1_NUM			20
++#define DAM_CTL_RX0_NUM			16
++#define DAM_CTL_TX_NUM			8
++#define DAM_CTL_RX2EN			6
++#define DAM_CTL_RX1EN			5
++#define DAM_CTL_RX0EN			4
++#define DAM_CTL_TXEN			0
++
++/* SUNXI_AHUB_DAM_RX##chan##_SRC */
++#define DAM_RX_APBIF_TXDIF0		31
++#define DAM_RX_APBIF_TXDIF1		30
++#define DAM_RX_APBIF_TXDIF2		29
++#define DAM_RX_I2S0_TXDIF		27
++#define DAM_RX_I2S1_TXDIF		26
++#define DAM_RX_I2S2_TXDIF		25
++#define DAM_RX_I2S3_TXDIF		23
++#define DAM_RX_DAM0_TXDIF		19
++#define DAM_RX_DAM1_TXDIF		15
++
++struct sunxi_ahub_mem_info {
++	char *dev_name;
++	struct resource *res;
++	void __iomem *membase;
++	struct resource *memregion;
++	struct regmap *regmap;
++};
++
++struct sunxi_ahub_clk_info {
++	struct clk *clk_pll;
++	struct clk *clk_pllx4;
++	struct clk *clk_module;
++	struct clk *clk_bus;
++	struct reset_control *clk_rst;
++};
++
++extern int snd_soc_sunxi_ahub_mem_get(struct sunxi_ahub_mem_info *mem_info);
++extern int snd_soc_sunxi_ahub_clk_get(struct sunxi_ahub_clk_info *clk_info);
++
++int __init sunxi_ahub_dam_dev_init(void);
++void __exit sunxi_ahub_dam_dev_exit(void);
++
++#endif /* __SND_SUNXI_AHUB_DAM_H */
+diff --git a/sound/soc/sunxi_v2/snd_sunxi_common.c b/sound/soc/sunxi_v2/snd_sunxi_common.c
+new file mode 100644
+index 000000000000..410ab75aea5a
+--- /dev/null
++++ b/sound/soc/sunxi_v2/snd_sunxi_common.c
+@@ -0,0 +1,267 @@
++/*
++ * sound\soc\sunxi\snd_sunxi_common.c
++ * (C) Copyright 2021-2025
++ * AllWinner Technology Co., Ltd. <www.allwinnertech.com>
++ * Dby <dby@allwinnertech.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ */
++
++#include <linux/module.h>
++#include <linux/platform_device.h>
++#include <linux/slab.h>
++#include <linux/regulator/consumer.h>
++#include <linux/of.h>
++#include <linux/clk.h>
++#include <linux/reset.h>
++#include <linux/device.h>
++#include <linux/ioport.h>
++#include <linux/regmap.h>
++#include <linux/of_address.h>
++#include <linux/of_gpio.h>
++
++#include "snd_sunxi_log.h"
++#include "snd_sunxi_common.h"
++
++#define HLOG		"COMMON"
++
++/* for regmap */
++int snd_sunxi_mem_init(struct platform_device *pdev,
++		       struct sunxi_mem_info *mem_info)
++{
++	int ret = 0;
++	struct device_node *np = pdev->dev.of_node;
++
++	SND_LOG_DEBUG(HLOG, "\n");
++
++	ret = of_address_to_resource(np, 0, mem_info->res);
++	if (ret) {
++		SND_LOG_ERR(HLOG, "parse device node resource failed\n");
++		ret = -EINVAL;
++		goto err_of_addr_to_resource;
++	}
++
++	mem_info->memregion = devm_request_mem_region(&pdev->dev,
++					mem_info->res->start,
++					resource_size(mem_info->res),
++					mem_info->dev_name);
++	if (IS_ERR_OR_NULL(mem_info->memregion)) {
++		SND_LOG_ERR(HLOG, "memory region already claimed\n");
++		ret = -EBUSY;
++		goto err_devm_request_region;
++	}
++
++	mem_info->membase = devm_ioremap(&pdev->dev,
++					 mem_info->memregion->start,
++					 resource_size(mem_info->memregion));
++	if (IS_ERR_OR_NULL(mem_info->membase)) {
++		SND_LOG_ERR(HLOG, "ioremap failed\n");
++		ret = -EBUSY;
++		goto err_devm_ioremap;
++	}
++
++	mem_info->regmap = devm_regmap_init_mmio(&pdev->dev,
++						 mem_info->membase,
++						 mem_info->regmap_config);
++	if (IS_ERR_OR_NULL(mem_info->regmap)) {
++		SND_LOG_ERR(HLOG, "regmap init failed\n");
++		ret = -EINVAL;
++		goto err_devm_regmap_init;
++	}
++
++	return 0;
++
++err_devm_regmap_init:
++	devm_iounmap(&pdev->dev, mem_info->membase);
++err_devm_ioremap:
++	devm_release_mem_region(&pdev->dev, mem_info->memregion->start,
++				resource_size(mem_info->memregion));
++err_devm_request_region:
++err_of_addr_to_resource:
++	return ret;
++}
++
++void snd_sunxi_mem_exit(struct platform_device *pdev,
++			struct sunxi_mem_info *mem_info)
++{
++	SND_LOG_DEBUG(HLOG, "\n");
++
++	devm_iounmap(&pdev->dev, mem_info->membase);
++	devm_release_mem_region(&pdev->dev, mem_info->memregion->start,
++				resource_size(mem_info->memregion));
++}
++
++/* for reg labels */
++int snd_sunxi_save_reg(struct regmap *regmap, struct reg_label *reg_labels)
++{
++	int i = 0;
++
++	SND_LOG_DEBUG(HLOG, "\n");
++
++	while (reg_labels[i].name != NULL) {
++		regmap_read(regmap,
++			    reg_labels[i].address, &(reg_labels[i].value));
++		i++;
++	}
++
++	return i;
++}
++
++int snd_sunxi_echo_reg(struct regmap *regmap, struct reg_label *reg_labels)
++{
++	int i = 0;
++
++	SND_LOG_DEBUG(HLOG, "\n");
++
++	while (reg_labels[i].name != NULL) {
++		regmap_write(regmap,
++			     reg_labels[i].address, reg_labels[i].value);
++		i++;
++	}
++
++	return i;
++}
++
++/* for pa config */
++struct pa_config *snd_sunxi_pa_pin_init(struct platform_device *pdev,
++					u32 *pa_pin_max)
++{
++	int ret, i;
++	u32 pin_max;
++	u32 gpio_tmp;
++	u32 temp_val;
++	char str[20] = {0};
++	struct pa_config *pa_cfg;
++	struct device_node *np = pdev->dev.of_node;
++
++	SND_LOG_DEBUG(HLOG, "\n");
++
++	*pa_pin_max = 0;
++	ret = of_property_read_u32(np, "pa_pin_max", &temp_val);
++	if (ret < 0) {
++		SND_LOG_WARN(HLOG, "pa_pin_max get failed, default 0\n");
++		return NULL;
++	} else {
++		pin_max = temp_val;
++	}
++
++	pa_cfg = kzalloc(sizeof(struct pa_config) * pin_max, GFP_KERNEL);
++	if (!pa_cfg) {
++		SND_LOG_ERR(HLOG, "can't pa_config memory\n");
++		return NULL;
++	}
++
++	for (i = 0; i < pin_max; i++) {
++		sprintf(str, "pa_pin_%d", i);
++		ret = of_get_named_gpio(np, str, 0);
++		if (ret < 0) {
++			SND_LOG_ERR(HLOG, "pa_pin_%u get failed\n", i);
++			pa_cfg[i].used = 0;
++			continue;
++		}
++		gpio_tmp = ret;
++		if (!gpio_is_valid(gpio_tmp)) {
++			SND_LOG_ERR(HLOG, "pa_pin_%u (%u) is invalid\n",
++				    i, gpio_tmp);
++			pa_cfg[i].used = 0;
++			continue;
++		}
++		ret = devm_gpio_request(&pdev->dev, gpio_tmp, str);
++		if (ret) {
++			SND_LOG_ERR(HLOG, "pa_pin_%u (%u) request failed\n",
++				    i, gpio_tmp);
++			pa_cfg[i].used = 0;
++			continue;
++		}
++		pa_cfg[i].used = 1;
++		pa_cfg[i].pin = gpio_tmp;
++
++		sprintf(str, "pa_pin_level_%d", i);
++		ret = of_property_read_u32(np, str, &temp_val);
++		if (ret < 0) {
++			SND_LOG_WARN(HLOG, "%s get failed, default low\n", str);
++			pa_cfg[i].level = 0;
++		} else {
++			if (temp_val > 0)
++				pa_cfg[i].level = 1;
++		}
++		sprintf(str, "pa_pin_msleep_%d", i);
++		ret = of_property_read_u32(np, str, &temp_val);
++		if (ret < 0) {
++			SND_LOG_WARN(HLOG, "%s get failed, default 0\n", str);
++			pa_cfg[i].msleep = 0;
++		} else {
++			pa_cfg[i].msleep = temp_val;
++		}
++	}
++
++	*pa_pin_max = pin_max;
++	snd_sunxi_pa_pin_disable(pa_cfg, pin_max);
++
++	return pa_cfg;
++}
++
++void snd_sunxi_pa_pin_exit(struct platform_device *pdev,
++			   struct pa_config *pa_cfg, u32 pa_pin_max)
++{
++	int i;
++
++	SND_LOG_DEBUG(HLOG, "\n");
++
++	snd_sunxi_pa_pin_disable(pa_cfg, pa_pin_max);
++
++	for (i = 0; i < pa_pin_max; i++) {
++		if (!pa_cfg[i].used)
++			continue;
++
++		gpio_free(pa_cfg[i].pin);
++	}
++
++	if (pa_cfg)
++		kfree(pa_cfg);
++}
++
++int snd_sunxi_pa_pin_enable(struct pa_config *pa_cfg, u32 pa_pin_max)
++{
++	int i;
++
++	SND_LOG_DEBUG(HLOG, "\n");
++
++	if (pa_pin_max < 1) {
++		SND_LOG_DEBUG(HLOG, "no pa pin config\n");
++		return 0;
++	}
++
++	for (i = 0; i < pa_pin_max; i++) {
++		if (!pa_cfg[i].used)
++			continue;
++
++		gpio_direction_output(pa_cfg[i].pin, 1);
++		gpio_set_value(pa_cfg[i].pin, pa_cfg[i].level);
++	}
++
++	return 0;
++}
++
++void snd_sunxi_pa_pin_disable(struct pa_config *pa_cfg, u32 pa_pin_max)
++{
++	int i;
++
++	SND_LOG_DEBUG(HLOG, "\n");
++
++	if (pa_pin_max < 1) {
++		SND_LOG_DEBUG(HLOG, "no pa pin config\n");
++		return;
++	}
++
++	for (i = 0; i < pa_pin_max; i++) {
++		if (!pa_cfg[i].used)
++			continue;
++
++		gpio_direction_output(pa_cfg[i].pin, 1);
++		gpio_set_value(pa_cfg[i].pin, !pa_cfg[i].level);
++	}
++}
+diff --git a/sound/soc/sunxi_v2/snd_sunxi_common.h b/sound/soc/sunxi_v2/snd_sunxi_common.h
+new file mode 100644
+index 000000000000..7b88d20c25e0
+--- /dev/null
++++ b/sound/soc/sunxi_v2/snd_sunxi_common.h
+@@ -0,0 +1,67 @@
++/* sound\soc\sunxi\snd_sunxi_common.h
++ * (C) Copyright 2021-2025
++ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
++ * Dby <dby@allwinnertech.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ */
++
++#ifndef __SND_SUNXI_COMMON_H
++#define __SND_SUNXI_COMMON_H
++
++/* for regmap */
++struct sunxi_mem_info {
++	char *dev_name;
++	struct resource *res;
++	struct regmap_config *regmap_config;
++
++	void __iomem *membase;
++	struct resource *memregion;
++	struct regmap *regmap;
++};
++
++int snd_sunxi_mem_init(struct platform_device *pdev,
++		       struct sunxi_mem_info *mem_info);
++void snd_sunxi_mem_exit(struct platform_device *pdev,
++			struct sunxi_mem_info *mem_info);
++
++/* for reg debug */
++#define REG_LABEL(constant)	{#constant, constant, 0}
++#define REG_LABEL_END		{NULL, 0, 0}
++
++struct reg_label {
++	const char *name;
++	const unsigned int address;
++	unsigned int value;
++};
++
++/* EX:
++ * static struct reg_label reg_labels[] = {
++ * 	REG_LABEL(SUNXI_REG_0),
++ * 	REG_LABEL(SUNXI_REG_1),
++ * 	REG_LABEL(SUNXI_REG_n),
++ * 	REG_LABEL_END,
++ * };
++ */
++int snd_sunxi_save_reg(struct regmap *regmap, struct reg_label *reg_labels);
++int snd_sunxi_echo_reg(struct regmap *regmap, struct reg_label *reg_labels);
++
++/* for pa config */
++struct pa_config {
++	u32 pin;
++	u32 msleep;
++	bool used;
++	bool level;
++};
++
++struct pa_config *snd_sunxi_pa_pin_init(struct platform_device *pdev,
++					u32 *pa_pin_max);
++void snd_sunxi_pa_pin_exit(struct platform_device *pdev,
++			   struct pa_config *pa_cfg, u32 pa_pin_max);
++int snd_sunxi_pa_pin_enable(struct pa_config *pa_cfg, u32 pa_pin_max);
++void snd_sunxi_pa_pin_disable(struct pa_config *pa_cfg, u32 pa_pin_max);
++
++#endif /* __SND_SUNXI_COMMON_H */
+\ No newline at end of file
+diff --git a/sound/soc/sunxi_v2/snd_sunxi_log.h b/sound/soc/sunxi_v2/snd_sunxi_log.h
+new file mode 100644
+index 000000000000..89ad9fe71936
+--- /dev/null
++++ b/sound/soc/sunxi_v2/snd_sunxi_log.h
+@@ -0,0 +1,29 @@
++/*
++ * sound\soc\sunxi\snd_sunxi_log.h
++ * (C) Copyright 2021-2025
++ * allwinner Technology Co., Ltd. <www.allwinnertech.com>
++ * Dby <dby@allwinnertech.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ */
++
++#ifndef __SND_SUNXI_LOG_H
++#define __SND_SUNXI_LOG_H
++#include <linux/kernel.h>
++
++#define SND_LOG_ERR(head, fmt, arg...) \
++	pr_err("[sound %4d][" head " %s] " fmt, __LINE__, __func__, ##arg)
++
++#define SND_LOG_WARN(head, fmt, arg...) \
++	pr_warn("[sound %4d][" head " %s] " fmt, __LINE__, __func__, ##arg)
++
++#define SND_LOG_INFO(head, fmt, arg...) \
++	pr_info("[sound %4d][" head " %s] " fmt, __LINE__, __func__, ##arg)
++
++#define SND_LOG_DEBUG(head, fmt, arg...) \
++	pr_debug("[sound %4d][" head " %s] " fmt, __LINE__, __func__, ##arg)
++
++#endif /* __SND_SUNXI_LOG_H */
+diff --git a/sound/soc/sunxi_v2/snd_sunxi_mach.c b/sound/soc/sunxi_v2/snd_sunxi_mach.c
+new file mode 100644
+index 000000000000..74d276a2da92
+--- /dev/null
++++ b/sound/soc/sunxi_v2/snd_sunxi_mach.c
+@@ -0,0 +1,479 @@
++/*
++ * sound\soc\sunxi\snd_sunxi_mach.c
++ * (C) Copyright 2021-2025
++ * AllWinner Technology Co., Ltd. <www.allwinnertech.com>
++ * Dby <dby@allwinnertech.com>
++ *
++ * based on ${LINUX}/sound/soc/generic/simple-card.c
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ */
++
++#include <linux/module.h>
++#include <sound/soc.h>
++
++#include "snd_sunxi_log.h"
++#include "snd_sunxi_mach.h"
++
++#define HLOG		"MACH"
++#define DAI		"sound-dai"
++#define CELL		"#sound-dai-cells"
++#define PREFIX		"soundcard-mach,"
++
++#define DRV_NAME	"sunxi-snd-mach"
++
++static void asoc_simple_shutdown(struct snd_pcm_substream *substream)
++{
++}
++
++static int asoc_simple_startup(struct snd_pcm_substream *substream)
++{
++	return 0;
++}
++
++static int asoc_simple_hw_params(struct snd_pcm_substream *substream,
++				 struct snd_pcm_hw_params *params)
++{
++	struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
++
++	struct snd_soc_dai *codec_dai = snd_soc_rtd_to_codec(rtd, 0);
++	struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
++
++	struct asoc_simple_priv *priv = snd_soc_card_get_drvdata(rtd->card);
++	struct snd_soc_dai_link *dai_link = simple_priv_to_link(priv, rtd->id);
++	struct simple_dai_props *dai_props = simple_priv_to_props(priv, rtd->id);
++	struct asoc_simple_dai *dais = priv->dais;
++	unsigned int mclk;
++	unsigned int cpu_pll_clk, codec_pll_clk;
++	unsigned int cpu_bclk_ratio, codec_bclk_ratio;
++	unsigned int freq_point;
++	int cpu_clk_div, codec_clk_div;
++	int ret = 0;
++
++	switch (params_rate(params)) {
++	case 8000:
++	case 12000:
++	case 16000:
++	case 24000:
++	case 32000:
++	case 48000:
++	case 64000:
++	case 96000:
++	case 192000:
++		freq_point = 24576000;
++		break;
++	case 11025:
++	case 22050:
++	case 44100:
++	case 88200:
++	case 176400:
++		freq_point = 22579200;
++		break;
++	default:
++		SND_LOG_ERR(HLOG, "Invalid rate %d\n", params_rate(params));
++		return -EINVAL;
++	}
++
++	/* for cpudai pll clk */
++	cpu_pll_clk	= freq_point * dai_props->cpu_pll_fs;
++	codec_pll_clk	= freq_point * dai_props->codec_pll_fs;
++	cpu_clk_div	= cpu_pll_clk / params_rate(params);
++	codec_clk_div	= codec_pll_clk / params_rate(params);
++	SND_LOG_DEBUG(HLOG, "freq point   : %u\n", freq_point);
++	SND_LOG_DEBUG(HLOG, "cpu pllclk   : %u\n", cpu_pll_clk);
++	SND_LOG_DEBUG(HLOG, "codec pllclk : %u\n", codec_pll_clk);
++	SND_LOG_DEBUG(HLOG, "cpu clk_div  : %u\n", cpu_clk_div);
++	SND_LOG_DEBUG(HLOG, "codec clk_div: %u\n", codec_clk_div);
++
++	if (cpu_dai->driver->ops->set_pll) {
++		ret = snd_soc_dai_set_pll(cpu_dai, substream->stream, 0,
++					  cpu_pll_clk, cpu_pll_clk);
++		if (ret) {
++			SND_LOG_ERR(HLOG, "cpu_dai set pllclk failed\n");
++			return ret;
++		}
++	}
++	if (codec_dai->driver->ops->set_pll) {
++		ret = snd_soc_dai_set_pll(codec_dai, substream->stream, 0,
++					  codec_pll_clk, codec_pll_clk);
++		if (ret) {
++			SND_LOG_ERR(HLOG, "codec_dai set pllclk failed\n");
++			return ret;
++		}
++	}
++
++	if (cpu_dai->driver->ops->set_clkdiv) {
++		ret = snd_soc_dai_set_clkdiv(cpu_dai, 0, cpu_clk_div);
++		if (ret) {
++			SND_LOG_ERR(HLOG, "cpu_dai set clk_div failed\n");
++			return ret;
++		}
++	}
++	if (codec_dai->driver->ops->set_clkdiv) {
++		ret = snd_soc_dai_set_clkdiv(codec_dai, 0, codec_clk_div);
++		if (ret) {
++			SND_LOG_ERR(HLOG, "cadec_dai set clk_div failed.\n");
++			return ret;
++		}
++	}
++
++	/* use for tdm only */
++	if (!(dais->slots && dais->slot_width))
++		return 0;
++
++	/* for cpudai & codecdai mclk */
++	if (dai_props->mclk_fp)
++		mclk = (freq_point >> 1) * dai_props->mclk_fs;
++	else
++		mclk = params_rate(params) * dai_props->mclk_fs;
++	cpu_bclk_ratio = cpu_pll_clk / (params_rate(params) * dais->slot_width * dais->slots);
++	codec_bclk_ratio = codec_pll_clk / (params_rate(params) * dais->slot_width * dais->slots);
++	SND_LOG_DEBUG(HLOG, "mclk            : %u\n", mclk);
++	SND_LOG_DEBUG(HLOG, "cpu_bclk_ratio  : %u\n", cpu_bclk_ratio);
++	SND_LOG_DEBUG(HLOG, "codec_bclk_ratio: %u\n", codec_bclk_ratio);
++
++	if (cpu_dai->driver->ops->set_sysclk) {
++		ret = snd_soc_dai_set_sysclk(cpu_dai, 0, mclk, SND_SOC_CLOCK_OUT);
++		if (ret) {
++			SND_LOG_ERR(HLOG, "cpu_dai set sysclk(mclk) failed\n");
++			return ret;
++		}
++	}
++	if (codec_dai->driver->ops->set_sysclk) {
++		ret = snd_soc_dai_set_sysclk(codec_dai, 0, mclk, SND_SOC_CLOCK_IN);
++		if (ret) {
++			SND_LOG_ERR(HLOG, "cadec_dai set sysclk(mclk) failed\n");
++			return ret;
++		}
++	}
++
++	if (cpu_dai->driver->ops->set_bclk_ratio) {
++		ret = snd_soc_dai_set_bclk_ratio(cpu_dai, cpu_bclk_ratio);
++		if (ret) {
++			SND_LOG_ERR(HLOG, "cpu_dai set bclk failed\n");
++			return ret;
++		}
++	}
++	if (codec_dai->driver->ops->set_bclk_ratio) {
++		ret = snd_soc_dai_set_bclk_ratio(codec_dai, codec_bclk_ratio);
++		if (ret) {
++			SND_LOG_ERR(HLOG, "codec_dai set bclk failed\n");
++			return ret;
++		}
++	}
++
++	if (cpu_dai->driver->ops->set_fmt) {
++		ret = snd_soc_dai_set_fmt(cpu_dai, dai_link->dai_fmt);
++		if (ret) {
++			SND_LOG_ERR(HLOG, "cpu dai set fmt failed\n");
++			return ret;
++		}
++	}
++	if (codec_dai->driver->ops->set_fmt) {
++		ret = snd_soc_dai_set_fmt(codec_dai, dai_link->dai_fmt);
++		if (ret) {
++			SND_LOG_ERR(HLOG, "codec dai set fmt failed\n");
++			return ret;
++		}
++	}
++
++	if (cpu_dai->driver->ops->set_tdm_slot) {
++		ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, 0, dais->slots, dais->slot_width);
++		if (ret) {
++			SND_LOG_ERR(HLOG, "cpu dai set tdm slot failed\n");
++			return ret;
++		}
++	}
++	if (codec_dai->driver->ops->set_tdm_slot) {
++		ret = snd_soc_dai_set_tdm_slot(codec_dai, 0, 0, dais->slots, dais->slot_width);
++		if (ret) {
++			SND_LOG_ERR(HLOG, "codec dai set tdm slot failed\n");
++			return ret;
++		}
++	}
++
++	return 0;
++}
++
++static struct snd_soc_ops simple_ops = {
++	.startup = asoc_simple_startup,
++	.shutdown = asoc_simple_shutdown,
++	.hw_params = asoc_simple_hw_params,
++};
++
++static int asoc_simple_dai_init(struct snd_soc_pcm_runtime *rtd)
++{
++	int i;
++	struct snd_soc_card *card = rtd->card;
++	struct snd_soc_dapm_context *dapm = &card->dapm;
++
++	const struct snd_kcontrol_new *controls = card->controls;
++
++	for (i = 0; i < card->num_controls; i++)
++		if (controls[i].info == snd_soc_dapm_info_pin_switch)
++			snd_soc_dapm_disable_pin(dapm,
++				(const char *)controls[i].private_value);
++
++	if (card->num_controls)
++		snd_soc_dapm_sync(dapm);
++
++	/* snd_soc_dai_set_sysclk(); */
++	/* snd_soc_dai_set_tdm_slot(); */
++
++	return 0;
++}
++
++static int simple_dai_link_of(struct device_node *node,
++			      struct asoc_simple_priv *priv)
++{
++	struct device *dev = simple_priv_to_dev(priv);
++	struct snd_soc_dai_link *dai_link = simple_priv_to_link(priv, 0);
++	struct simple_dai_props *dai_props = simple_priv_to_props(priv, 0);
++	struct device_node *top_np = NULL;
++	struct device_node *cpu = NULL;
++	struct device_node *plat = NULL;
++	struct device_node *codec = NULL;
++	char prop[128];
++	char *prefix = "";
++	int ret, single_cpu;
++
++	prefix = PREFIX;
++	top_np = node;
++
++	snprintf(prop, sizeof(prop), "%scpu", prefix);
++	cpu = of_get_child_by_name(top_np, prop);
++	if (!cpu) {
++		ret = -EINVAL;
++		SND_LOG_ERR(HLOG, "Can't find %s DT node\n", prop);
++		goto dai_link_of_err;
++	}
++	snprintf(prop, sizeof(prop), "%splat", prefix);
++	plat = of_get_child_by_name(top_np, prop);
++
++	snprintf(prop, sizeof(prop), "%scodec", prefix);
++	codec = of_get_child_by_name(top_np, prop);
++	if (!codec) {
++		ret = -EINVAL;
++		SND_LOG_ERR(HLOG, "Can't find %s DT node\n", prop);
++		goto dai_link_of_err;
++	}
++
++	ret = asoc_simple_parse_daifmt(top_np, codec, prefix, &dai_link->dai_fmt);
++	if (ret < 0)
++		goto dai_link_of_err;
++	/* sunxi: parse stream direction
++	 * ex1)
++	 * top_node {
++	 *	PREFIXplayback-only;
++	 * }
++	 * ex2)
++	 * top_node {
++	 *	PREFIXcapture-only;
++	 * }
++	 */
++	ret = asoc_simple_parse_daistream(top_np, prefix, dai_link);
++	if (ret < 0)
++		goto dai_link_of_err;
++	/* sunxi: parse slot-num & slot-width
++	 * ex)
++	 * top_node {
++	 *	PREFIXplayslot-num	= <x>;
++	 *	PREFIXplayslot-width	= <x>;
++	 * }
++	 */
++	ret = asoc_simple_parse_tdm_slot(top_np, prefix, priv->dais);
++	if (ret < 0)
++		goto dai_link_of_err;
++
++	ret = asoc_simple_parse_cpu(cpu, dai_link, DAI, CELL, &single_cpu);
++	if (ret < 0)
++		goto dai_link_of_err;
++	ret = asoc_simple_parse_codec(codec, dai_link, DAI, CELL);
++	if (ret < 0) {
++		if (ret == -EPROBE_DEFER)
++			goto dai_link_of_err;
++		dai_link->codecs->name = "snd-soc-dummy";
++		dai_link->codecs->dai_name = "snd-soc-dummy-dai";
++		/* dai_link->codecs->name = "sunxi-dummy-codec"; */
++		/* dai_link->codecs->dai_name = "sunxi-dummy-codec-dai"; */
++		SND_LOG_DEBUG(HLOG, "use dummy codec for simple card.\n");
++	}
++	ret = asoc_simple_parse_platform(plat, dai_link, DAI, CELL);
++	if (ret < 0)
++		goto dai_link_of_err;
++
++	/* sunxi: parse pll-fs & mclk-fs
++	 * ex)
++	 * top_node {
++	 *	PREFIXcpu {
++	 *		PREFIXpll-fs	= <x>;
++	 *		PREFIXmclk-fs	= <x>;
++	 *	}
++	 * }
++	 */
++	ret = asoc_simple_parse_tdm_clk(cpu, codec, prefix, dai_props);
++	if (ret < 0)
++		goto dai_link_of_err;
++
++	ret = asoc_simple_set_dailink_name(dev, dai_link,
++					   "%s-%s",
++					   dai_link->cpus->dai_name,
++					   dai_link->codecs->dai_name);
++	if (ret < 0)
++		goto dai_link_of_err;
++
++	dai_link->ops = &simple_ops;
++	dai_link->init = asoc_simple_dai_init;
++
++	SND_LOG_DEBUG(HLOG, "name   : %s\n", dai_link->stream_name);
++	SND_LOG_DEBUG(HLOG, "format : %x\n", dai_link->dai_fmt);
++	SND_LOG_DEBUG(HLOG, "cpu    : %s\n", dai_link->cpus->name);
++	SND_LOG_DEBUG(HLOG, "codec  : %s\n", dai_link->codecs->name);
++
++	asoc_simple_canonicalize_cpu(dai_link, single_cpu);
++	asoc_simple_canonicalize_platform(dai_link);
++
++dai_link_of_err:
++	of_node_put(cpu);
++	of_node_put(plat);
++	of_node_put(codec);
++
++	return ret;
++}
++
++static int simple_parse_of(struct asoc_simple_priv *priv)
++{
++	int ret;
++	struct device *dev = simple_priv_to_dev(priv);
++	struct snd_soc_card *card = simple_priv_to_card(priv);
++	struct device_node *top_np = dev->of_node;
++
++	SND_LOG_DEBUG(HLOG, "\n");
++
++	if (!top_np)
++		return -EINVAL;
++
++	/* DAPM widgets */
++	ret = asoc_simple_parse_widgets(card, PREFIX);
++	if (ret < 0)
++		return ret;
++
++	/* DAPM routes */
++	ret = asoc_simple_parse_routing(card, PREFIX);
++	if (ret < 0)
++		return ret;
++
++	/* DAPM pin_switches */
++	ret = asoc_simple_parse_pin_switches(card, PREFIX);
++	if (ret < 0)
++		return ret;
++
++	/* For single DAI link & old style of DT node */
++	ret = simple_dai_link_of(top_np, priv);
++	if (ret < 0)
++		return ret;
++
++	ret = asoc_simple_parse_card_name(card, PREFIX);
++	return ret;
++}
++
++static int simple_soc_probe(struct snd_soc_card *card)
++{
++	return 0;
++}
++
++static int asoc_simple_probe(struct platform_device *pdev)
++{
++	struct device *dev = &pdev->dev;
++	struct device_node *top_np = dev->of_node;
++	struct asoc_simple_priv *priv;
++	struct snd_soc_card *card;
++	int ret;
++
++	/* Allocate the private data and the DAI link array */
++	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
++	if (!priv)
++		return -ENOMEM;
++
++	card = simple_priv_to_card(priv);
++	card->owner		= THIS_MODULE;
++	card->dev		= dev;
++	card->probe		= simple_soc_probe;
++
++	ret = asoc_simple_init_priv(priv);
++	if (ret < 0)
++		return ret;
++
++	if (top_np && of_device_is_available(top_np)) {
++		ret = simple_parse_of(priv);
++		if (ret < 0) {
++			if (ret != -EPROBE_DEFER)
++				SND_LOG_ERR(HLOG, "parse error %d\n", ret);
++			goto err;
++		}
++	} else {
++		SND_LOG_ERR(HLOG, "simple card dts available\n");
++	}
++
++	snd_soc_card_set_drvdata(card, priv);
++
++	/* asoc_simple_debug_info(priv); */
++	ret = devm_snd_soc_register_card(dev, card);
++	if (ret >= 0)
++		return ret;
++err:
++	asoc_simple_clean_reference(card);
++
++	return ret;
++}
++
++static void asoc_simple_remove(struct platform_device *pdev)
++{
++	struct snd_soc_card *card = platform_get_drvdata(pdev);
++
++	asoc_simple_clean_reference(card);
++}
++
++static const struct of_device_id snd_soc_sunxi_of_match[] = {
++	{ .compatible = "allwinner," DRV_NAME, },
++	{},
++};
++MODULE_DEVICE_TABLE(of, snd_soc_sunxi_of_match);
++
++static struct platform_driver sunxi_soundcard_machine_driver = {
++	.driver	= {
++		.name		= DRV_NAME,
++		.pm		= &snd_soc_pm_ops,
++		.of_match_table	= snd_soc_sunxi_of_match,
++	},
++	.probe	= asoc_simple_probe,
++	.remove	= asoc_simple_remove,
++};
++
++int __init sunxi_soundcard_machine_dev_init(void)
++{
++	int ret;
++
++	ret = platform_driver_register(&sunxi_soundcard_machine_driver);
++	if (ret != 0) {
++		SND_LOG_ERR(HLOG, "platform driver register failed\n");
++		return -EINVAL;
++	}
++
++	return ret;
++}
++
++void __exit sunxi_soundcard_machine_dev_exit(void)
++{
++	platform_driver_unregister(&sunxi_soundcard_machine_driver);
++}
++
++late_initcall(sunxi_soundcard_machine_dev_init);
++module_exit(sunxi_soundcard_machine_dev_exit);
++
++MODULE_AUTHOR("Dby@allwinnertech.com");
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("sunxi soundcard machine");
+diff --git a/sound/soc/sunxi_v2/snd_sunxi_mach.h b/sound/soc/sunxi_v2/snd_sunxi_mach.h
+new file mode 100644
+index 000000000000..6f9ea8ccf8b5
+--- /dev/null
++++ b/sound/soc/sunxi_v2/snd_sunxi_mach.h
+@@ -0,0 +1,20 @@
++/* sound\soc\sunxi\snd_sunxi_mach.h
++ * (C) Copyright 2021-2025
++ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
++ * Dby <dby@allwinnertech.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ */
++
++#ifndef __SND_SUNXI_MACH_H
++#define __SND_SUNXI_MACH_H
++
++#include "snd_sunxi_mach_utils.h"
++
++int __init sunxi_soundcard_machine_dev_init(void);
++void __exit sunxi_soundcard_machine_dev_exit(void);
++
++#endif /* __SND_SUNXI_MACH_H */
+diff --git a/sound/soc/sunxi_v2/snd_sunxi_mach_utils.c b/sound/soc/sunxi_v2/snd_sunxi_mach_utils.c
+new file mode 100644
+index 000000000000..15f474e5cbeb
+--- /dev/null
++++ b/sound/soc/sunxi_v2/snd_sunxi_mach_utils.c
+@@ -0,0 +1,422 @@
++/*
++ * sound\soc\sunxi\snd_sunxi_mach_utils.c
++ * (C) Copyright 2021-2025
++ * AllWinner Technology Co., Ltd. <www.allwinnertech.com>
++ * Dby <dby@allwinnertech.com>
++ *
++ * based on ${LINUX}/sound/soc/generic/simple-card.c
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ */
++
++#include <linux/module.h>
++#include <linux/of.h>
++#include <sound/soc.h>
++
++#include "snd_sunxi_log.h"
++#include "snd_sunxi_mach_utils.h"
++
++#define HLOG           "mach_utils"
++
++int asoc_simple_clean_reference(struct snd_soc_card *card)
++{
++       struct snd_soc_dai_link *dai_link;
++       int i;
++
++       for_each_card_prelinks(card, i, dai_link) {
++               of_node_put(dai_link->cpus->of_node);
++               of_node_put(dai_link->codecs->of_node);
++       }
++       return 0;
++}
++
++int asoc_simple_init_priv(struct asoc_simple_priv *priv)
++{
++       struct snd_soc_card *card = simple_priv_to_card(priv);
++       struct device *dev = simple_priv_to_dev(priv);
++       struct snd_soc_dai_link *dai_link;
++       struct simple_dai_props *dai_props;
++       struct asoc_simple_dai *dais;
++       struct snd_soc_codec_conf *cconf = NULL;
++
++       dai_props = devm_kcalloc(dev, 1, sizeof(*dai_props), GFP_KERNEL);
++       dai_link  = devm_kcalloc(dev, 1, sizeof(*dai_link),  GFP_KERNEL);
++       dais      = devm_kcalloc(dev, 1, sizeof(*dais),      GFP_KERNEL);
++       if (!dai_props || !dai_link || !dais)
++               return -ENOMEM;
++
++       /*
++       if (li->conf) {
++               cconf = devm_kcalloc(dev, li->conf, sizeof(*cconf), GFP_KERNEL);
++               if (!cconf)
++                       return -ENOMEM;
++       }
++       */
++
++       /*
++        * Use snd_soc_dai_link_component instead of legacy style
++        * It is codec only. but cpu/platform will be supported in the future.
++        * see
++        *      soc-core.c :: snd_soc_init_multicodec()
++        *
++        * "platform" might be removed
++        * see
++        *      simple-card-utils.c :: asoc_simple_canonicalize_platform()
++        */
++       dai_link->cpus          = &dai_props->cpus;
++       dai_link->num_cpus      = 1;
++       dai_link->codecs        = &dai_props->codecs;
++       dai_link->num_codecs    = 1;
++       dai_link->platforms     = &dai_props->platforms;
++       dai_link->num_platforms = 1;
++
++       priv->dai_props         = dai_props;
++       priv->dai_link          = dai_link;
++       priv->dais              = dais;
++       priv->codec_conf        = cconf;
++
++       card->dai_link          = priv->dai_link;
++       card->num_links         = 1;
++       card->codec_conf        = cconf;
++       card->num_configs       = 0;
++
++       return 0;
++}
++
++int asoc_simple_parse_widgets(struct snd_soc_card *card, char *prefix)
++{
++       struct device_node *node = card->dev->of_node;
++       char prop[128];
++
++       if (!prefix)
++               prefix = "";
++
++       snprintf(prop, sizeof(prop), "%s%s", prefix, "widgets");
++
++       if (of_property_read_bool(node, prop))
++               return snd_soc_of_parse_audio_simple_widgets(card, prop);
++
++       /* no widgets is not error */
++       return 0;
++}
++
++int asoc_simple_parse_routing(struct snd_soc_card *card, char *prefix)
++{
++       struct device_node *node = card->dev->of_node;
++       char prop[128];
++
++       if (!prefix)
++               prefix = "";
++
++       snprintf(prop, sizeof(prop), "%s%s", prefix, "routing");
++
++       if (!of_property_read_bool(node, prop))
++               return 0;
++
++       return snd_soc_of_parse_audio_routing(card, prop);
++}
++
++int asoc_simple_parse_pin_switches(struct snd_soc_card *card, char *prefix)
++{
++       const unsigned int nb_controls_max = 16;
++       const char **strings, *control_name;
++       struct snd_kcontrol_new *controls;
++       struct device *dev = card->dev;
++       unsigned int i, nb_controls;
++       char prop[128];
++       int ret;
++
++       if (!prefix)
++               prefix = "";
++
++       snprintf(prop, sizeof(prop), "%s%s", prefix, "pin-switches");
++
++       if (!of_property_read_bool(dev->of_node, prop))
++               return 0;
++
++       strings = devm_kcalloc(dev, nb_controls_max,
++                              sizeof(*strings), GFP_KERNEL);
++       if (!strings)
++               return -ENOMEM;
++
++       ret = of_property_read_string_array(dev->of_node, prop,
++                                           strings, nb_controls_max);
++       if (ret < 0)
++               return ret;
++
++       nb_controls = (unsigned int)ret;
++
++       controls = devm_kcalloc(dev, nb_controls,
++                               sizeof(*controls), GFP_KERNEL);
++       if (!controls)
++               return -ENOMEM;
++
++       for (i = 0; i < nb_controls; i++) {
++               control_name = devm_kasprintf(dev, GFP_KERNEL,
++                                             "%s Switch", strings[i]);
++               if (!control_name)
++                       return -ENOMEM;
++
++               controls[i].iface = SNDRV_CTL_ELEM_IFACE_MIXER;
++               controls[i].name = control_name;
++               controls[i].info = snd_soc_dapm_info_pin_switch;
++               controls[i].get = snd_soc_dapm_get_pin_switch;
++               controls[i].put = snd_soc_dapm_put_pin_switch;
++               controls[i].private_value = (unsigned long)strings[i];
++       }
++
++       card->controls = controls;
++       card->num_controls = nb_controls;
++
++       return 0;
++}
++
++int asoc_simple_parse_daifmt(struct device_node *node,
++                            struct device_node *codec,
++                            char *prefix,
++                            unsigned int *retfmt)
++{
++       struct device_node *bitclkmaster = NULL;
++       struct device_node *framemaster = NULL;
++       unsigned int daifmt;
++
++       daifmt = snd_soc_daifmt_parse_format(node, prefix);
++
++       snd_soc_daifmt_parse_clock_provider_as_phandle(node, prefix, &bitclkmaster, &framemaster);
++       if (!bitclkmaster && !framemaster) {
++               /*
++                * No dai-link level and master setting was not found from
++                * sound node level, revert back to legacy DT parsing and
++                * take the settings from codec node.
++                */
++               SND_LOG_DEBUG(HLOG, "Revert to legacy daifmt parsing\n");
++
++               daifmt |= snd_soc_daifmt_parse_clock_provider_as_flag(codec, NULL);
++       } else {
++               daifmt |= snd_soc_daifmt_clock_provider_from_bitmap(
++                       ((codec == bitclkmaster) << 4) | (codec == framemaster));
++       }
++
++       of_node_put(bitclkmaster);
++       of_node_put(framemaster);
++
++       *retfmt = daifmt;
++
++       return 0;
++}
++
++int asoc_simple_parse_daistream(struct device_node *node, char *prefix,
++                               struct snd_soc_dai_link *dai_link)
++{
++       char prop[128];
++
++       if (!prefix)
++               prefix = "";
++
++       /* check "[prefix]playback-only" */
++       snprintf(prop, sizeof(prop), "%splayback-only", prefix);
++       if (of_property_read_bool(node, prop))
++               dai_link->playback_only = 1;
++
++       /* check "[prefix]capture-only" */
++       snprintf(prop, sizeof(prop), "%scapture-only", prefix);
++       if (of_property_read_bool(node, prop))
++               dai_link->capture_only = 1;
++
++       return 0;
++}
++
++int asoc_simple_parse_tdm_slot(struct device_node *node, char *prefix,
++                              struct asoc_simple_dai *dais)
++{
++       int ret;
++       char prop[128];
++       unsigned int val;
++
++       if (!prefix)
++               prefix = "";
++
++       snprintf(prop, sizeof(prop), "%sslot-num", prefix);
++       ret = of_property_read_u32(node, prop, &val);
++       if (!ret)
++               dais->slots = val;
++
++       snprintf(prop, sizeof(prop), "%sslot-width", prefix);
++       ret = of_property_read_u32(node, prop, &val);
++       if (!ret)
++               dais->slot_width = val;
++
++       return 0;
++}
++
++int asoc_simple_parse_tdm_clk(struct device_node *cpu,
++                             struct device_node *codec,
++                             char *prefix,
++                             struct simple_dai_props *dai_props)
++{
++       int ret;
++       char prop[128];
++       unsigned int val;
++
++       if (!prefix)
++               prefix = "";
++
++       snprintf(prop, sizeof(prop), "%spll-fs", prefix);
++       ret = of_property_read_u32(cpu, prop, &val);
++       if (ret)
++               dai_props->cpu_pll_fs = 1;      /* default sysclk 24.576 or 22.5792MHz * 1 */
++       else
++               dai_props->cpu_pll_fs = val;
++
++       ret = of_property_read_u32(codec, prop, &val);
++       if (ret)
++               dai_props->codec_pll_fs = 1;    /* default sysclk 24.576 or 22.5792MHz * 1 */
++       else
++               dai_props->codec_pll_fs = val;
++
++       snprintf(prop, sizeof(prop), "%smclk-fp", prefix);
++       dai_props->mclk_fp = of_property_read_bool(cpu, prop);
++
++       snprintf(prop, sizeof(prop), "%smclk-fs", prefix);
++       ret = of_property_read_u32(cpu, prop, &val);
++       if (ret)
++               dai_props->mclk_fs = 0;         /* default mclk 0Hz(un output) */
++       else
++               dai_props->mclk_fs = val;
++
++       return 0;
++}
++
++int asoc_simple_parse_card_name(struct snd_soc_card *card,
++                               char *prefix)
++{
++       int ret;
++
++       if (!prefix)
++               prefix = "";
++
++       /* Parse the card name from DT */
++       ret = snd_soc_of_parse_card_name(card, "label");
++       if (ret < 0 || !card->name) {
++               char prop[128];
++
++               snprintf(prop, sizeof(prop), "%sname", prefix);
++               ret = snd_soc_of_parse_card_name(card, prop);
++               if (ret < 0)
++                       return ret;
++       }
++
++       if (!card->name && card->dai_link)
++               card->name = card->dai_link->name;
++
++       return 0;
++}
++
++int asoc_simple_parse_dai(struct device_node *node,
++                         struct snd_soc_dai_link_component *dlc,
++                         const char *list_name, const char *cells_name,
++                         int *is_single_link)
++{
++       struct of_phandle_args args;
++       int ret;
++
++       if (!node)
++               return 0;
++
++       /*
++        * Get node via "sound-dai = <&phandle port>"
++        * it will be used as xxx_of_node on soc_bind_dai_link()
++        */
++       ret = of_parse_phandle_with_args(node, list_name, cells_name, 0, &args);
++       if (ret)
++               return ret;
++
++       /*
++        * FIXME
++        *
++        * Here, dlc->dai_name is pointer to CPU/Codec DAI name.
++        * If user unbinded CPU or Codec driver, but not for Sound Card,
++        * dlc->dai_name is keeping unbinded CPU or Codec
++        * driver's pointer.
++        *
++        * If user re-bind CPU or Codec driver again, ALSA SoC will try
++        * to rebind Card via snd_soc_try_rebind_card(), but because of
++        * above reason, it might can't bind Sound Card.
++        * Because Sound Card is pointing to released dai_name pointer.
++        *
++        * To avoid this rebind Card issue,
++        * 1) It needs to alloc memory to keep dai_name eventhough
++        *    CPU or Codec driver was unbinded, or
++        * 2) user need to rebind Sound Card everytime
++        *    if he unbinded CPU or Codec.
++        */
++       ret = snd_soc_of_get_dai_name(node, &dlc->dai_name, 0);
++       if (ret < 0)
++               return ret;
++
++       dlc->of_node = args.np;
++
++       if (is_single_link)
++               *is_single_link = !args.args_count;
++
++       return 0;
++}
++
++int asoc_simple_set_dailink_name(struct device *dev,
++                                struct snd_soc_dai_link *dai_link,
++                                const char *fmt, ...)
++{
++       va_list ap;
++       char *name = NULL;
++       int ret = -ENOMEM;
++
++       va_start(ap, fmt);
++       name = devm_kvasprintf(dev, GFP_KERNEL, fmt, ap);
++       va_end(ap);
++
++       if (name) {
++               ret = 0;
++
++               dai_link->name          = name;
++               dai_link->stream_name   = name;
++       }
++
++       return ret;
++}
++
++void asoc_simple_canonicalize_platform(struct snd_soc_dai_link *dai_link)
++{
++       /* Assumes platform == cpu */
++       if (!dai_link->platforms->of_node)
++               dai_link->platforms->of_node = dai_link->cpus->of_node;
++
++       /*
++        * DPCM BE can be no platform.
++        * Alloced memory will be waste, but not leak.
++        */
++       if (!dai_link->platforms->of_node)
++               dai_link->num_platforms = 0;
++}
++
++void asoc_simple_canonicalize_cpu(struct snd_soc_dai_link *dai_link,
++                                 int is_single_links)
++{
++       /*
++        * In soc_bind_dai_link() will check cpu name after
++        * of_node matching if dai_link has cpu_dai_name.
++        * but, it will never match if name was created by
++        * fmt_single_name() remove cpu_dai_name if cpu_args
++        * was 0. See:
++        *      fmt_single_name()
++        *      fmt_multiple_name()
++        */
++       if (is_single_links)
++               dai_link->cpus->dai_name = NULL;
++}
++
++MODULE_AUTHOR("Dby@allwinnertech.com");
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("sunxi soundcard machine utils");
+diff --git a/sound/soc/sunxi_v2/snd_sunxi_mach_utils.h b/sound/soc/sunxi_v2/snd_sunxi_mach_utils.h
+new file mode 100644
+index 000000000000..a9cffa0d859b
+--- /dev/null
++++ b/sound/soc/sunxi_v2/snd_sunxi_mach_utils.h
+@@ -0,0 +1,116 @@
++/* sound\soc\sunxi\snd_sunxi_mach_utils.h
++ * (C) Copyright 2021-2025
++ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
++ * Dby <dby@allwinnertech.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ */
++
++#ifndef __SND_SUNXI_MACH_UTILS_H
++#define __SND_SUNXI_MACH_UTILS_H
++
++#define simple_priv_to_card(priv)      (&(priv)->snd_card)
++#define simple_priv_to_props(priv, i)  ((priv)->dai_props + (i))
++#define simple_priv_to_dev(priv)       (simple_priv_to_card(priv)->dev)
++#define simple_priv_to_link(priv, i)   (simple_priv_to_card(priv)->dai_link + (i))
++
++#define asoc_simple_parse_cpu(node, dai_link,                          \
++                             list_name, cells_name, is_single_link)    \
++       asoc_simple_parse_dai(node, dai_link->cpus,                     \
++                             list_name, cells_name, is_single_link)
++
++#define asoc_simple_parse_codec(node, dai_link,                                \
++                               list_name, cells_name)                  \
++       asoc_simple_parse_dai(node, dai_link->codecs,                   \
++                             list_name, cells_name, NULL)
++
++#define asoc_simple_parse_platform(node, dai_link,                     \
++                                  list_name, cells_name)               \
++       asoc_simple_parse_dai(node, dai_link->platforms,                \
++                             list_name, cells_name, NULL)
++
++struct asoc_simple_dai {
++       const char *name;
++       unsigned int sysclk;
++       int clk_direction;
++       int slots;
++       int slot_width;
++       unsigned int tx_slot_mask;
++       unsigned int rx_slot_mask;
++       struct clk *clk;
++};
++
++struct asoc_simple_data {
++       u32 convert_rate;
++       u32 convert_channels;
++};
++
++struct asoc_simple_jack {
++       struct snd_soc_jack jack;
++       struct snd_soc_jack_pin pin;
++       struct snd_soc_jack_gpio gpio;
++};
++
++struct asoc_simple_priv {
++       struct snd_soc_card snd_card;
++       struct simple_dai_props {
++               struct asoc_simple_dai *cpu_dai;
++               struct asoc_simple_dai *codec_dai;
++               struct snd_soc_dai_link_component cpus;   /* single cpu */
++               struct snd_soc_dai_link_component codecs; /* single codec */
++               struct snd_soc_dai_link_component platforms;
++               struct asoc_simple_data adata;
++               struct snd_soc_codec_conf *codec_conf;
++               bool mclk_fp;
++               unsigned int mclk_fs;
++               unsigned int cpu_pll_fs;
++               unsigned int codec_pll_fs;
++       } *dai_props;
++       struct asoc_simple_jack hp_jack;
++       struct asoc_simple_jack mic_jack;
++       struct snd_soc_dai_link *dai_link;
++       struct asoc_simple_dai *dais;
++       struct snd_soc_codec_conf *codec_conf;
++       struct gpio_desc *pa_gpio;
++};
++
++int asoc_simple_clean_reference(struct snd_soc_card *card);
++int asoc_simple_init_priv(struct asoc_simple_priv *priv);
++
++int asoc_simple_parse_widgets(struct snd_soc_card *card, char *prefix);
++int asoc_simple_parse_routing(struct snd_soc_card *card, char *prefix);
++int asoc_simple_parse_pin_switches(struct snd_soc_card *card, char *prefix);
++
++int asoc_simple_parse_daistream(struct device_node *node,
++                               char *prefix,
++                               struct snd_soc_dai_link *dai_link);
++int asoc_simple_parse_daifmt(struct device_node *node,
++                            struct device_node *codec,
++                            char *prefix,
++                            unsigned int *retfmt);
++int asoc_simple_parse_tdm_slot(struct device_node *node,
++                              char *prefix,
++                              struct asoc_simple_dai *dais);
++int asoc_simple_parse_tdm_clk(struct device_node *cpu,
++                             struct device_node *codec,
++                             char *prefix,
++                             struct simple_dai_props *dai_props);
++
++int asoc_simple_parse_card_name(struct snd_soc_card *card, char *prefix);
++int asoc_simple_parse_dai(struct device_node *node,
++                         struct snd_soc_dai_link_component *dlc,
++                         const char *list_name,
++                         const char *cells_name,
++                         int *is_single_link);
++
++int asoc_simple_set_dailink_name(struct device *dev,
++                                struct snd_soc_dai_link *dai_link,
++                                const char *fmt, ...);
++void asoc_simple_canonicalize_platform(struct snd_soc_dai_link *dai_link);
++void asoc_simple_canonicalize_cpu(struct snd_soc_dai_link *dai_link,
++                                 int is_single_links);
++
++#endif /* __SND_SUNXI_MACH_UTILS_H */
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/Temp_fix-mailbox-arch-arm64-boot-dts-allwinner-sun50i-a64-pinep.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/Temp_fix-mailbox-arch-arm64-boot-dts-allwinner-sun50i-a64-pinep.patch
new file mode 100644
index 000000000000..6a4110acb825
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/Temp_fix-mailbox-arch-arm64-boot-dts-allwinner-sun50i-a64-pinep.patch
@@ -0,0 +1,53 @@
+From ef5deb15a48bd970f378ae63a058ecd70bf42834 Mon Sep 17 00:00:00 2001
+From: AGM1968 <AGM1968@users.noreply.github.com>
+Date: Mon, 26 Jun 2023 14:29:56 +0000
+Subject: Temp_fix mailbox
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+
+Signed-off-by: AGM1968 <AGM1968@users.noreply.github.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi | 7 ++++---
+ 1 file changed, 4 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+index d502c1392b8e..5c986e66ab6d 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pinephone.dtsi
+@@ -42,7 +42,7 @@ bat: battery {
+                 resistance-temp-table = <20 150>;
+                 ocv-capacity-celsius = <20>;
+                 ocv-capacity-table-0 =
+-                	<4334000 100>,
++			<4334000 100>,
+ 			<4319700 99>,
+ 			<4304300 98>,
+ 			<4292200 97>,
+@@ -144,7 +144,7 @@ bat: battery {
+ 			<3393500 1>,
+ 			<3256000 0>;
+                 x-powers,ocv-capacity-table =
+-                	<0xc0 0>,
++			<0xc0 0>,
+ 			<0xc1 1>,
+ 			<0xc2 1>,
+ 			<0xc3 2>,
+@@ -191,7 +191,7 @@ ppkb_battery: keyboard-battery {
+                 factory-internal-resistance-micro-ohms = <120000>;
+                 ocv-capacity-celsius = <20>;
+                 ocv-capacity-table-0 =
+-                	<4147328 100>,
++			<4147328 100>,
+ 			<4132636 99>,
+ 			<4121720 98>,
+ 			<4110905 97>,
+@@ -778,6 +778,7 @@ &mmc1 {
+ 	non-removable;
+ 	post-power-on-delay-ms = <1>; /* wifi power is always on */
+ 	status = "okay";
++	keep-power-in-suspend;
+ 
+ 	rtl8723cs: wifi@1 {
+ 		reg = <1>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/add-dtb-overlay-for-zero2w.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/add-dtb-overlay-for-zero2w.patch
new file mode 100644
index 000000000000..10f44c45d1f7
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/add-dtb-overlay-for-zero2w.patch
@@ -0,0 +1,135 @@
+From 4b2f43e4e23c5e6184568a6b0bf0e85fce4aefb3 Mon Sep 17 00:00:00 2001
+From: chraac <chraac@gmail.com>
+Date: Fri, 5 Apr 2024 10:57:18 +0800
+Subject: add dtb overlay for zero2w
+
+---
+ .../arm64/boot/dts/allwinner/overlay/Makefile |  4 ++++
+ .../allwinner/overlay/sun50i-h616-gpu.dtso    | 14 +++++++++++
+ .../overlay/sun50i-h616-i2c0-pi.dtso          | 23 +++++++++++++++++++
+ .../overlay/sun50i-h616-i2c1-pi.dtso          | 16 +++++++++++++
+ .../overlay/sun50i-h616-i2c2-pi.dtso          | 23 +++++++++++++++++++
+ 5 files changed, 80 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-gpu.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c0-pi.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c1-pi.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c2-pi.dtso
+
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/Makefile b/arch/arm64/boot/dts/allwinner/overlay/Makefile
+index 718909b607a6..ccb89b5bf495 100644
+--- a/arch/arm64/boot/dts/allwinner/overlay/Makefile
++++ b/arch/arm64/boot/dts/allwinner/overlay/Makefile
+@@ -49,6 +49,10 @@ dtb-$(CONFIG_ARCH_SUNXI) += \
+ 	sun50i-h6-uart2.dtbo \
+ 	sun50i-h6-uart3.dtbo \
+ 	sun50i-h6-w1-gpio.dtbo \
++	sun50i-h616-gpu.dtbo \
++	sun50i-h616-i2c0-pi.dtbo \
++	sun50i-h616-i2c1-pi.dtbo \
++	sun50i-h616-i2c2-pi.dtbo \
+ 	sun50i-h616-i2c2-ph.dtbo \
+ 	sun50i-h616-i2c3-pg.dtbo \
+ 	sun50i-h616-i2c3-ph.dtbo \
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-gpu.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-gpu.dtso
+new file mode 100644
+index 000000000000..ac8846ac7d27
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-gpu.dtso
+@@ -0,0 +1,14 @@
++/dts-v1/;
++/plugin/;
++
++
++/ {
++	compatible = "allwinner,sun50i-h616";
++
++	fragment@0 {
++		target = <&gpu>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c0-pi.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c0-pi.dtso
+new file mode 100644
+index 000000000000..b5003934c895
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c0-pi.dtso
+@@ -0,0 +1,23 @@
++/dts-v1/;
++/plugin/;
++
++
++/ {
++	compatible = "allwinner,sun50i-h616";
++
++	fragment@0 {
++		target = <&i2c0>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&i2c0_pi_pins>;
++			status = "okay";
++		};
++	};
++
++	fragment@1 {
++		target = <&uart2>;
++		__overlay__ {
++			status = "disabled";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c1-pi.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c1-pi.dtso
+new file mode 100644
+index 000000000000..05f3100967ff
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c1-pi.dtso
+@@ -0,0 +1,16 @@
++/dts-v1/;
++/plugin/;
++
++
++/ {
++	compatible = "allwinner,sun50i-h616";
++
++	fragment@0 {
++		target = <&i2c1>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&i2c1_pi_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c2-pi.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c2-pi.dtso
+new file mode 100644
+index 000000000000..0f7d7e9968d6
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c2-pi.dtso
+@@ -0,0 +1,23 @@
++/dts-v1/;
++/plugin/;
++
++
++/ {
++	compatible = "allwinner,sun50i-h616";
++
++	fragment@0 {
++		target = <&i2c2>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&i2c2_pi_pins>;
++			status = "okay";
++		};
++	};
++
++	fragment@1 {
++		target = <&uart3>;
++		__overlay__ {
++			status = "disabled";
++		};
++	};
++};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/add-initial-support-for-orangepi3-lts.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/add-initial-support-for-orangepi3-lts.patch
new file mode 100644
index 000000000000..ce4b04b6795f
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/add-initial-support-for-orangepi3-lts.patch
@@ -0,0 +1,431 @@
+From a2b3cc507ed489b1f6cf497d61df30e080881ad8 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Sat, 16 Apr 2022 11:51:35 +0300
+Subject: add initial support for orangepi3-lts
+
+---
+ arch/arm64/boot/dts/allwinner/Makefile        |   1 +
+ .../allwinner/sun50i-h6-orangepi-3-lts.dts    | 399 ++++++++++++++++++
+ 2 files changed, 400 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts
+
+diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
+index 54665bbb468d..dc922a71cfc1 100644
+--- a/arch/arm64/boot/dts/allwinner/Makefile
++++ b/arch/arm64/boot/dts/allwinner/Makefile
+@@ -43,6 +43,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus2.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-beelink-gs1.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-3.dtb
++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-3-lts.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-lite2.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-orangepi-one-plus.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts
+new file mode 100644
+index 000000000000..dd6b4e15263e
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3-lts.dts
+@@ -0,0 +1,399 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++// Copyright (C) 2023 Jernej Skrabec <jernej.skrabec@gmail.com>
++// Copyright (C) 2019 Ondřej Jirman <megous@megous.com>
++
++/dts-v1/;
++
++#include "sun50i-h6.dtsi"
++#include "sun50i-h6-cpu-opp.dtsi"
++
++#include <dt-bindings/gpio/gpio.h>
++
++/ {
++	model = "OrangePi 3 LTS";
++	compatible = "xunlong,orangepi-3-lts", "allwinner,sun50i-h6";
++
++	aliases {
++		ethernet0 = &emac;
++		serial0 = &uart0;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	connector {
++		compatible = "hdmi-connector";
++		ddc-en-gpios = <&pio 7 2 GPIO_ACTIVE_HIGH>; /* PH2 */
++		type = "a";
++
++		port {
++			hdmi_con_in: endpoint {
++				remote-endpoint = <&hdmi_out_con>;
++			};
++		};
++	};
++
++	ext_osc32k: ext_osc32k_clk {
++		#clock-cells = <0>;
++		compatible = "fixed-clock";
++		clock-frequency = <32768>;
++		clock-output-names = "ext_osc32k";
++	};
++
++	leds {
++		compatible = "gpio-leds";
++
++		status {
++			label = "green-led";
++			gpios = <&r_pio 0 7 GPIO_ACTIVE_HIGH>; /* PL7 */
++			default-state = "on";
++		};
++
++		power {
++			label = "red-led";
++			gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */
++		};
++	};
++
++	reg_vcc5v: vcc5v {
++		/* board wide 5V supply directly from the DC jack */
++		compatible = "regulator-fixed";
++		regulator-name = "vcc-5v";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		regulator-always-on;
++	};
++
++	reg_gmac_3v3: gmac-3v3 {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc-gmac-3v3";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		startup-delay-us = <150000>;
++		gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
++		enable-active-high;
++	};
++
++	reg_vcc33_wifi: vcc33-wifi {
++		/* Always on 3.3V regulator for WiFi and BT */
++		compatible = "regulator-fixed";
++		regulator-name = "vcc33-wifi";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		enable-active-high;
++		gpio = <&pio 7 7 GPIO_ACTIVE_HIGH>; /* PH7 */
++	};
++
++	reg_vcc_wifi_io: vcc-wifi-io {
++		/* Always on 1.8V/300mA regulator for WiFi and BT IO */
++		compatible = "regulator-fixed";
++		regulator-name = "vcc-wifi-io";
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		regulator-always-on;
++		vin-supply = <&reg_vcc33_wifi>;
++	};
++
++	wifi_pwrseq: wifi-pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		clocks = <&rtc 1>;
++		clock-names = "ext_clock";
++		reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */
++		post-power-on-delay-ms = <200>;
++	};
++};
++
++&ac200_codec {
++	avcc-supply = <&reg_aldo2>;
++	status = "okay";
++};
++
++&ac200_pwm_clk {
++	status = "okay";
++};
++
++&analog {
++	status = "okay";
++};
++
++&cpu0 {
++	cpu-supply = <&reg_dcdca>;
++};
++
++&de {
++	status = "okay";
++};
++
++&dwc3 {
++	status = "okay";
++};
++
++&ehci0 {
++	status = "okay";
++};
++
++&ehci3 {
++	status = "okay";
++};
++
++&emac {
++	pinctrl-names = "default";
++	pinctrl-0 = <&ext_rgmii_pins>;
++	phy-mode = "rgmii-id";
++	phy-handle = <&ext_rgmii_phy>;
++	phy-supply = <&reg_gmac_3v3>;
++	allwinner,rx-delay-ps = <200>;
++	allwinner,tx-delay-ps = <300>;
++	status = "okay";
++};
++
++&gpu {
++	mali-supply = <&reg_dcdcc>;
++	status = "okay";
++};
++
++&hdmi {
++	hvcc-supply = <&reg_bldo2>;
++	status = "okay";
++};
++
++&hdmi_out {
++	hdmi_out_con: endpoint {
++		remote-endpoint = <&hdmi_con_in>;
++	};
++};
++
++&i2c3 {
++	status = "okay";
++};
++
++&i2s1 {
++	status = "okay";
++};
++
++&i2s3 {
++	status = "okay";
++};
++
++&mdio {
++	ext_rgmii_phy: ethernet-phy@1 {
++		compatible = "ethernet-phy-ieee802.3-c22";
++		reg = <1>;
++		motorcomm,clk-out-frequency-hz = <125000000>;
++		reset-gpios = <&pio 3 14 GPIO_ACTIVE_LOW>; /* PD14 */
++		reset-assert-us = <15000>;
++		reset-deassert-us = <40000>;
++	};
++};
++
++&mmc0 {
++	vmmc-supply = <&reg_cldo1>;
++	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
++	bus-width = <4>;
++	status = "okay";
++};
++
++&mmc1 {
++	vmmc-supply = <&reg_vcc33_wifi>;
++	vqmmc-supply = <&reg_vcc_wifi_io>;
++	mmc-pwrseq = <&wifi_pwrseq>;
++	bus-width = <4>;
++	non-removable;
++	status = "okay";
++};
++
++&mmc2 {
++	vmmc-supply = <&reg_cldo1>;
++	vqmmc-supply = <&reg_bldo2>;
++	bus-width = <8>;
++	non-removable;
++	cap-mmc-hw-reset;
++	mmc-hs200-1_8v;
++	status = "okay";
++};
++
++&ohci0 {
++	status = "okay";
++};
++
++&ohci3 {
++	status = "okay";
++};
++
++&pio {
++	vcc-pc-supply = <&reg_bldo2>;
++	vcc-pd-supply = <&reg_cldo1>;
++	vcc-pg-supply = <&reg_vcc_wifi_io>;
++};
++
++&pwm {
++	status = "okay";
++};
++
++&r_ir {
++	status = "okay";
++};
++
++&r_i2c {
++	status = "okay";
++
++	axp805: pmic@36 {
++		compatible = "x-powers,axp805", "x-powers,axp806";
++		reg = <0x36>;
++		interrupt-parent = <&r_intc>;
++		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
++		interrupt-controller;
++		#interrupt-cells = <1>;
++		x-powers,self-working-mode;
++		vina-supply = <&reg_vcc5v>;
++		vinb-supply = <&reg_vcc5v>;
++		vinc-supply = <&reg_vcc5v>;
++		vind-supply = <&reg_vcc5v>;
++		vine-supply = <&reg_vcc5v>;
++		aldoin-supply = <&reg_vcc5v>;
++		bldoin-supply = <&reg_vcc5v>;
++		cldoin-supply = <&reg_vcc5v>;
++
++		regulators {
++			reg_aldo1: aldo1 {
++				regulator-always-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-name = "vcc-pl-led-ir";
++			};
++
++			reg_aldo2: aldo2 {
++				regulator-always-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-name = "vcc33-audio-tv-ephy-mac";
++				regulator-enable-ramp-delay = <100000>;
++			};
++
++			/* ALDO3 is shorted to CLDO1 */
++			reg_aldo3: aldo3 {
++				regulator-always-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-name = "vcc33-io-pd-emmc-sd-usb-uart-1";
++			};
++
++			reg_bldo1: bldo1 {
++				regulator-always-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-name = "vcc18-dram-bias-pll";
++			};
++
++			reg_bldo2: bldo2 {
++				regulator-always-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-name = "vcc-efuse-pcie-hdmi-pc";
++			};
++
++			reg_bldo3: bldo3 {
++				regulator-always-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-name = "vcc-pm-pg-dcxoio-wifi";
++			};
++
++			bldo4 {
++				/* unused */
++			};
++
++			reg_cldo1: cldo1 {
++				regulator-always-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-name = "vcc33-io-pd-emmc-sd-usb-uart-2";
++			};
++
++			cldo2 {
++				/* unused */
++			};
++
++			cldo3 {
++				/* unused */
++			};
++
++			reg_dcdca: dcdca {
++				regulator-always-on;
++				regulator-min-microvolt = <800000>;
++				regulator-max-microvolt = <1160000>;
++				regulator-ramp-delay = <2500>;
++				regulator-name = "vdd-cpu";
++			};
++
++			reg_dcdcc: dcdcc {
++				regulator-enable-ramp-delay = <32000>;
++				regulator-min-microvolt = <810000>;
++				regulator-max-microvolt = <1080000>;
++				regulator-ramp-delay = <2500>;
++				regulator-name = "vdd-gpu";
++			};
++
++			reg_dcdcd: dcdcd {
++				regulator-always-on;
++				regulator-min-microvolt = <960000>;
++				regulator-max-microvolt = <960000>;
++				regulator-name = "vdd-sys";
++			};
++
++			reg_dcdce: dcdce {
++				regulator-always-on;
++				regulator-min-microvolt = <1200000>;
++				regulator-max-microvolt = <1200000>;
++				regulator-name = "vcc-dram";
++			};
++
++			sw {
++				/* unused */
++			};
++		};
++	};
++};
++
++&rtc {
++	clocks = <&ext_osc32k>;
++};
++
++&sound_hdmi {
++	status = "okay";
++};
++
++&uart0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart0_ph_pins>;
++	status = "okay";
++};
++
++&uart1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
++	uart-has-rtscts;
++	status = "disabled";
++};
++
++&usb2otg {
++	/*
++	 * This board doesn't have a controllable VBUS even though it
++	 * does have an ID pin. Using it as anything but a USB host is
++	 * unsafe.
++	 */
++	dr_mode = "host";
++	status = "okay";
++};
++
++&usb2phy {
++	usb0_id_det-gpios = <&pio 2 15 GPIO_ACTIVE_HIGH>; /* PC15 */
++	usb0_vbus-supply = <&reg_vcc5v>;
++	usb3_vbus-supply = <&reg_vcc5v>;
++	status = "okay";
++};
++
++&usb3phy {
++	status = "okay";
++};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/add-nodes-for-sunxi-info-sunxi-addr-and-sunxi-dump-reg.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/add-nodes-for-sunxi-info-sunxi-addr-and-sunxi-dump-reg.patch
new file mode 100644
index 000000000000..b99dd2dfcab3
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/add-nodes-for-sunxi-info-sunxi-addr-and-sunxi-dump-reg.patch
@@ -0,0 +1,73 @@
+From a01e21420bdfad0ed47a29dbae243090b2e02928 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Sat, 16 Apr 2022 11:51:35 +0300
+Subject: add nodes for sunxi-info, sunxi-addr and sunxi-dump-reg
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi  | 19 +++++++++++++++++++
+ .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 19 +++++++++++++++++++
+ 2 files changed, 38 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+index 0e7f44cf90c6..342dd620126c 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+@@ -1256,6 +1256,25 @@ ths: thermal-sensor@5070400 {
+ 			nvmem-cell-names = "calibration";
+ 			#thermal-sensor-cells = <1>;
+ 		};
++
++		sunxi-info {
++			compatible = "allwinner,sun50i-h6-sys-info";
++			status = "okay";
++		};
++
++		addr_mgt: addr-mgt {
++			compatible = "allwinner,sunxi-addr_mgt";
++			type_addr_wifi = <0x2>;
++			type_addr_bt = <0x2>;
++			type_addr_eth = <0x2>;
++			status = "okay";
++		};
++
++		dump_reg: dump_reg@20000 {
++			compatible = "allwinner,sunxi-dump-reg";
++			reg = <0x0 0x03001000 0x0 0x0f20>;
++			status = "okay";
++		};
+ 	};
+ 
+ 	thermal-zones {
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+index 72e46c263485..5c1e2dc77268 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+@@ -1020,6 +1020,25 @@ r_rsb: rsb@7083000 {
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+ 		};
++
++		dump_reg: dump_reg@20000 {
++			compatible = "allwinner,sunxi-dump-reg";
++			reg = <0x0 0x03001000 0x0 0x0f20>;
++			status = "okay";
++		};
++
++		sunxi-info {
++			compatible = "allwinner,sun50i-h616-sys-info";
++			status = "okay";
++		};
++
++		addr_mgt: addr-mgt {
++			compatible = "allwinner,sunxi-addr_mgt";
++			type_addr_wifi = <0x2>;
++			type_addr_bt = <0x2>;
++			type_addr_eth = <0x2>;
++			status = "okay";
++		};
+ 	};
+ 
+ 	thermal-zones {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-arm64-dts-Add-leds-axp20x-charger.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-arm64-dts-Add-leds-axp20x-charger.patch
new file mode 100644
index 000000000000..2f8cedb58bfc
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-arm64-dts-Add-leds-axp20x-charger.patch
@@ -0,0 +1,79 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Sun, 23 Jan 2022 16:43:53 +0300
+Subject: arm:arm64:dts: Add leds axp20x charger
+
+---
+ arch/arm/boot/dts/allwinner/axp209.dtsi   | 5 +++++
+ arch/arm/boot/dts/allwinner/axp22x.dtsi   | 5 +++++
+ arch/arm/boot/dts/allwinner/axp81x.dtsi   | 5 +++++
+ arch/arm64/boot/dts/allwinner/axp803.dtsi | 5 +++++
+ 4 files changed, 20 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/axp209.dtsi b/arch/arm/boot/dts/allwinner/axp209.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/allwinner/axp209.dtsi
++++ b/arch/arm/boot/dts/allwinner/axp209.dtsi
+@@ -76,6 +76,11 @@ axp_gpio: gpio {
+ 		#gpio-cells = <2>;
+ 	};
+ 
++	axp_led: led {
++		compatible = "x-powers,axp20x-led";
++		status = "disabled";
++	};
++
+ 	battery_power_supply: battery-power {
+ 		compatible = "x-powers,axp209-battery-power-supply";
+ 		status = "disabled";
+diff --git a/arch/arm/boot/dts/allwinner/axp22x.dtsi b/arch/arm/boot/dts/allwinner/axp22x.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/allwinner/axp22x.dtsi
++++ b/arch/arm/boot/dts/allwinner/axp22x.dtsi
+@@ -62,6 +62,11 @@ axp_adc: adc {
+ 		#io-channel-cells = <1>;
+ 	};
+ 
++	axp_led: led {
++		compatible = "x-powers,axp20x-led";
++		status = "disabled";
++	};
++
+ 	battery_power_supply: battery-power {
+ 		compatible = "x-powers,axp221-battery-power-supply";
+ 		status = "disabled";
+diff --git a/arch/arm/boot/dts/allwinner/axp81x.dtsi b/arch/arm/boot/dts/allwinner/axp81x.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/allwinner/axp81x.dtsi
++++ b/arch/arm/boot/dts/allwinner/axp81x.dtsi
+@@ -64,6 +64,11 @@ axp_gpio: gpio {
+ 		#gpio-cells = <2>;
+ 	};
+ 
++	axp_led: led {
++		compatible = "x-powers,axp20x-led";
++		status = "disabled";
++	};
++
+ 	battery_power_supply: battery-power {
+ 		compatible = "x-powers,axp813-battery-power-supply";
+ 		status = "disabled";
+diff --git a/arch/arm64/boot/dts/allwinner/axp803.dtsi b/arch/arm64/boot/dts/allwinner/axp803.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/allwinner/axp803.dtsi
++++ b/arch/arm64/boot/dts/allwinner/axp803.dtsi
+@@ -28,6 +28,11 @@ axp_gpio: gpio {
+ 		#gpio-cells = <2>;
+ 	};
+ 
++	axp_led: led {
++		compatible = "x-powers,axp20x-led";
++		status = "disabled";
++	};
++
+ 	battery_power_supply: battery-power {
+ 		compatible = "x-powers,axp803-battery-power-supply",
+ 			     "x-powers,axp813-battery-power-supply";
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-Add-sun8i-h2-plus-nanopi-duo-device.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-Add-sun8i-h2-plus-nanopi-duo-device.patch
new file mode 100644
index 000000000000..3f86d152ef6b
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-Add-sun8i-h2-plus-nanopi-duo-device.patch
@@ -0,0 +1,196 @@
+From 165e8af0db38e2880c067355f5153ec6ca880b32 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Mon, 24 Jan 2022 15:00:36 +0300
+Subject: arm:dts: Add sun8i-h2-plus-nanopi-duo device
+
+---
+ arch/arm/boot/dts/allwinner/Makefile          |   1 +
+ .../allwinner/sun8i-h2-plus-nanopi-duo.dts    | 164 ++++++++++++++++++
+ 2 files changed, 165 insertions(+)
+ create mode 100644 arch/arm/boot/dts/allwinner/sun8i-h2-plus-nanopi-duo.dts
+
+diff --git a/arch/arm/boot/dts/allwinner/Makefile b/arch/arm/boot/dts/allwinner/Makefile
+index 1356e9553bd6..803bc88fccd6 100644
+--- a/arch/arm/boot/dts/allwinner/Makefile
++++ b/arch/arm/boot/dts/allwinner/Makefile
+@@ -222,6 +222,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
+ 	sun8i-a83t-tbs-a711.dtb \
+ 	sun8i-h2-plus-bananapi-m2-zero.dtb \
+ 	sun8i-h2-plus-libretech-all-h3-cc.dtb \
++	sun8i-h2-plus-nanopi-duo.dtb \
+ 	sun8i-h2-plus-orangepi-r1.dtb \
+ 	sun8i-h2-plus-orangepi-zero.dtb \
+ 	sun8i-h3-bananapi-m2-plus.dtb \
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h2-plus-nanopi-duo.dts b/arch/arm/boot/dts/allwinner/sun8i-h2-plus-nanopi-duo.dts
+new file mode 100644
+index 000000000000..2b31b8fddbf3
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/sun8i-h2-plus-nanopi-duo.dts
+@@ -0,0 +1,164 @@
++/*
++ * adapted by karabek, 2018 , based on
++ *   Copyright (C) 2016 James Pettigrew <james@innovum.com.au>
++ *   Copyright (C) 2016 Milo Kim <woogyom.kim@gmail.com>
++ *
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPL or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ *  a) This file is free software; you can redistribute it and/or
++ *     modify it under the terms of the GNU General Public License as
++ *     published by the Free Software Foundation; either version 2 of the
++ *     License, or (at your option) any later version.
++ *
++ *     This file is distributed in the hope that it will be useful,
++ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *     GNU General Public License for more details.
++ *
++ * Or, alternatively,
++ *
++ *  b) Permission is hereby granted, free of charge, to any person
++ *     obtaining a copy of this software and associated documentation
++ *     files (the "Software"), to deal in the Software without
++ *     restriction, including without limitation the rights to use,
++ *     copy, modify, merge, publish, distribute, sublicense, and/or
++ *     sell copies of the Software, and to permit persons to whom the
++ *     Software is furnished to do so, subject to the following
++ *     conditions:
++ *
++ *     The above copyright notice and this permission notice shall be
++ *     included in all copies or substantial portions of the Software.
++ *
++ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ *     OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++/dts-v1/;
++#include "sun8i-h3-nanopi.dtsi"
++#include <dt-bindings/pinctrl/sun4i-a10.h>
++
++/ {
++	model = "FriendlyARM NanoPi DUO";
++	compatible = "friendlyarm,nanopi-duo", "allwinner,sun8i-h3";
++
++	aliases {
++		ethernet0 = &emac;
++		ethernet1 = &xr819;
++	};
++
++	reg_sy8113b: gpio-regulator {
++		compatible = "regulator-gpio";
++		regulator-name = "vdd-cpux";
++		regulator-type = "voltage";
++		regulator-boot-on;
++		regulator-always-on;
++		regulator-min-microvolt = <1100000>;
++		regulator-max-microvolt = <1300000>;
++		regulator-ramp-delay = <50>; 		// 50=4ms check
++
++		gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; 	// PL6 check
++		enable-active-high;
++		gpios-states = <0x1>;
++		states = <1100000 0x0
++			  1300000 0x1>;
++	};
++
++	reg_vcc_wifi: reg_vcc_wifi {
++		compatible = "regulator-fixed";
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		regulator-name = "vcc-wifi";
++		gpio = <&r_pio 0 7 GPIO_ACTIVE_HIGH>;	// PL7 WIFI_POWER_EN
++	        startup-delay-us = <70000>;
++        	enable-active-high;
++	};
++
++	wifi_pwrseq: wifi_pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		pinctrl-names = "default";
++		pinctrl-0 = <&wifi_en_npi>;
++		reset-gpios = <&pio 6 13 GPIO_ACTIVE_LOW>;  // PG13 WL_RESTN
++		post-power-on-delay-ms = <200>;
++	};
++};
++
++&cpu0 {
++	cpu-supply = <&reg_sy8113b>;
++};
++
++&ehci0 {
++	status = "okay";
++};
++
++&emac {
++	phy-handle = <&int_mii_phy>;
++	phy-mode = "mii";
++	allwinner,leds-active-low;
++	status = "okay";
++};
++
++&mmc1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&mmc1_pins>;
++	vqmmc-supply = <&reg_vcc_wifi>;
++	vmmc-supply = <&reg_vcc3v3>;
++	mmc-pwrseq = <&wifi_pwrseq>;
++	bus-width = <4>;
++	non-removable;
++	status = "okay";
++
++	xr819: sdio_wifi@1 {
++		reg = <1>;
++		compatible = "xradio,xr819";
++		pinctrl-names = "default";
++		pinctrl-0 = <&wifi_wake>;
++		interrupt-parent = <&pio>;
++		interrupts = <6 10 IRQ_TYPE_EDGE_RISING>;
++		interrupt-names = "host-wake";
++	};
++};
++
++&mmc1_pins {
++	bias-pull-up;
++};
++
++&ohci0 {
++	status = "okay";
++};
++
++&pio {
++	wifi_en_npi: wifi_en_pin {
++		pins = "PG13";
++		function = "gpio_out";
++	};
++	wifi_wake: wifi_wake@0 {
++		pins = "PG10";
++		function = "irq";
++		pull = <SUN4I_PINCTRL_NO_PULL>;
++	};
++};
++
++&usb_otg {
++	dr_mode = "peripheral";
++	status = "okay";
++};
++
++&usbphy {
++	/*
++	 * USB Type-A port VBUS is always on. However, MicroUSB VBUS can only
++	 * power up the board; when it's used as OTG port, this VBUS is
++	 * always off even if the board is powered via GPIO pins.
++	 */
++	status = "okay";
++	usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
++};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-Add-sun8i-h2-plus-sunvell-r69-device.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-Add-sun8i-h2-plus-sunvell-r69-device.patch
new file mode 100644
index 000000000000..820c80cda3d9
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-Add-sun8i-h2-plus-sunvell-r69-device.patch
@@ -0,0 +1,257 @@
+From a0710275bb42a34ca0b8d2e62d1a39dfce4f00c7 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Mon, 24 Jan 2022 15:23:33 +0300
+Subject: arm:dts: Add sun8i-h2-plus-sunvell-r69 device
+
+---
+ arch/arm/boot/dts/allwinner/Makefile          |   1 +
+ .../allwinner/sun8i-h2-plus-sunvell-r69.dts   | 225 ++++++++++++++++++
+ 2 files changed, 226 insertions(+)
+ create mode 100644 arch/arm/boot/dts/allwinner/sun8i-h2-plus-sunvell-r69.dts
+
+diff --git a/arch/arm/boot/dts/allwinner/Makefile b/arch/arm/boot/dts/allwinner/Makefile
+index 803bc88fccd6..2e8615538458 100644
+--- a/arch/arm/boot/dts/allwinner/Makefile
++++ b/arch/arm/boot/dts/allwinner/Makefile
+@@ -225,6 +225,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
+ 	sun8i-h2-plus-nanopi-duo.dtb \
+ 	sun8i-h2-plus-orangepi-r1.dtb \
+ 	sun8i-h2-plus-orangepi-zero.dtb \
++	sun8i-h2-plus-sunvell-r69.dtb \
+ 	sun8i-h3-bananapi-m2-plus.dtb \
+ 	sun8i-h3-bananapi-m2-plus-v1.2.dtb \
+ 	sun8i-h3-beelink-x2.dtb \
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h2-plus-sunvell-r69.dts b/arch/arm/boot/dts/allwinner/sun8i-h2-plus-sunvell-r69.dts
+new file mode 100644
+index 000000000000..bb0c2f72b723
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/sun8i-h2-plus-sunvell-r69.dts
+@@ -0,0 +1,225 @@
++// SPDX-License-Identifier: (GPL-2.0+ or MIT)
++/*
++ * Based original Sunvell R69 FEX file (2019 karabek)
++ */
++
++/dts-v1/;
++#include "sun8i-h3.dtsi"
++#include "sunxi-common-regulators.dtsi"
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/input.h>
++#include <dt-bindings/pinctrl/sun4i-a10.h>
++
++/ {
++	model = "Sunvell R69";
++	compatible = "sunvell,sunvell-r69", "allwinner,sun8i-h2-plus";
++
++	aliases {
++		ethernet0 = &emac;
++		ethernet1 = &xr819;
++		serial0 = &uart0;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	connector {
++		compatible = "hdmi-connector";
++		type = "a";
++
++		port {
++			hdmi_con_in: endpoint {
++				remote-endpoint = <&hdmi_out_con>;
++			};
++		};
++	};
++
++	leds {
++		compatible = "gpio-leds";
++		pinctrl-names = "default";
++		pinctrl-0 = <&leds_opc>, <&leds_r_opc>;
++
++		pwr_led {
++			label = "sunvell-r69:red:pwr";
++			gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
++		};
++
++		status_led {
++			label = "sunvell-r69:blue:status";
++			gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>;
++			linux,default-trigger = "heartbeat";
++		};
++	};
++
++	reg_vdd_cpux: vdd-cpux-regulator {
++		compatible = "regulator-gpio";
++		regulator-name = "vdd-cpux";
++		regulator-type = "voltage";
++		regulator-boot-on;
++		regulator-always-on;
++		regulator-min-microvolt = <1100000>;
++		regulator-max-microvolt = <1300000>;
++		regulator-ramp-delay = <50>;		/* 4ms */
++
++		gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>;	/* PL6 */
++		enable-active-high;
++		gpios-states = <0x1>;
++		states = <1100000 0x0
++			  1300000 0x1>;
++	};
++
++	reg_vcc_wifi: reg_vcc_wifi {
++		compatible = "regulator-fixed";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		regulator-name = "vcc-wifi";
++		gpio = <&r_pio 0 7 GPIO_ACTIVE_HIGH>;
++	        startup-delay-us = <70000>;
++		enable-active-high;
++	};
++
++	wifi_pwrseq: wifi_pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		reset-gpios = <&r_pio 0 0 GPIO_ACTIVE_LOW>;
++		post-power-on-delay-ms = <200>;
++	};
++};
++
++&cpu0 {
++	cpu-supply = <&reg_vdd_cpux>;
++};
++
++&de {
++	status = "okay";
++};
++
++&ehci0 {
++	status = "okay";
++};
++
++&ehci1 {
++	status = "okay";
++};
++
++&emac {
++	phy-handle = <&int_mii_phy>;
++	phy-mode = "mii";
++	allwinner,leds-active-low;
++	status = "okay";
++};
++
++&hdmi {
++	status = "okay";
++};
++
++&hdmi_out {
++	hdmi_out_con: endpoint {
++		remote-endpoint = <&hdmi_con_in>;
++	};
++};
++
++&ir {
++	pinctrl-names = "default";
++	pinctrl-0 = <&r_ir_rx_pin>;		/* <&r_ir_rx_pin> */
++	status = "okay";
++};
++
++&mmc0 {
++	vmmc-supply = <&reg_vcc3v3>;
++	bus-width = <4>;
++	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;	/* PF6 */
++	status = "okay";
++};
++
++&mmc1 {
++	vmmc-supply = <&reg_vcc_wifi>;
++	mmc-pwrseq = <&wifi_pwrseq>;
++	bus-width = <4>;
++	non-removable;
++	status = "okay";
++
++	xr819: sdio_wifi@1 {
++		reg = <1>;
++		compatible = "xradio,xr819";
++		interrupt-parent = <&pio>;
++		interrupts = <0 11 IRQ_TYPE_EDGE_RISING>;
++		interrupt-names = "host-wake";
++	};
++};
++
++&mmc2 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&mmc2_8bit_pins>;
++	vmmc-supply = <&reg_vcc3v3>;
++	bus-width = <8>;
++	non-removable;
++	cap-mmc-hw-reset;
++	status = "okay";
++};
++
++&mmc2_8bit_pins {
++	/* Increase current from 30mA to 40mA for DDR eMMC */
++	allwinner,drive = <SUN4I_PINCTRL_40_MA>;
++};
++
++&ohci0 {
++	status = "okay";
++};
++
++&ohci1 {
++	status = "okay";
++};
++
++&pio {
++	leds_opc: led_pins {
++		pins = "PA15";
++		function = "gpio_out";
++	};
++};
++
++&r_pio {
++	leds_r_opc: led_pins {
++		pins = "PL10";
++		function = "gpio_out";
++	};
++};
++
++&reg_usb0_vbus {
++	gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>;	/* PL2 */
++	status = "okay";
++};
++
++&uart0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart0_pa_pins>;
++	status = "okay";
++};
++
++&uart1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart1_pins>;
++	status = "disabled";
++};
++
++&uart2 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart2_pins>;
++	status = "disabled";
++};
++
++&uart3 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart3_pins>;
++	status = "disabled";
++};
++
++&usb_otg {
++	dr_mode = "host";
++	status = "okay";
++};
++
++&usbphy {
++	status = "okay";
++};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-a10-cubiebord-a20-cubietruck-green-LED-mmc0-default-tri.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-a10-cubiebord-a20-cubietruck-green-LED-mmc0-default-tri.patch
new file mode 100644
index 000000000000..b76a34191d1a
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-a10-cubiebord-a20-cubietruck-green-LED-mmc0-default-tri.patch
@@ -0,0 +1,38 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Mon, 24 Jan 2022 14:46:11 +0300
+Subject: arm:dts: a10-cubiebord a20-cubietruck green LED mmc0 default-trigger
+
+---
+ arch/arm/boot/dts/allwinner/sun4i-a10-cubieboard.dts | 2 +-
+ arch/arm/boot/dts/allwinner/sun7i-a20-cubietruck.dts | 1 +
+ 2 files changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/allwinner/sun4i-a10-cubieboard.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/allwinner/sun4i-a10-cubieboard.dts
++++ b/arch/arm/boot/dts/allwinner/sun4i-a10-cubieboard.dts
+@@ -83,7 +83,7 @@ led-0 {
+ 		led-1 {
+ 			label = "cubieboard:green:usr";
+ 			gpios = <&pio 7 20 GPIO_ACTIVE_HIGH>; /* LED2 */
+-			linux,default-trigger = "heartbeat";
++			linux,default-trigger = "mmc0";
+ 		};
+ 	};
+ };
+diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-cubietruck.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/allwinner/sun7i-a20-cubietruck.dts
++++ b/arch/arm/boot/dts/allwinner/sun7i-a20-cubietruck.dts
+@@ -93,6 +93,7 @@ led-2 {
+ 		led-3 {
+ 			label = "cubietruck:green:usr";
+ 			gpios = <&pio 7 7 GPIO_ACTIVE_HIGH>;
++			linux,default-trigger = "mmc0";
+ 		};
+ 	};
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-a20-orangepi-and-mini-fix-phy-mode-hdmi.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-a20-orangepi-and-mini-fix-phy-mode-hdmi.patch
new file mode 100644
index 000000000000..193cbae8a5e0
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-a20-orangepi-and-mini-fix-phy-mode-hdmi.patch
@@ -0,0 +1,86 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Mon, 24 Jan 2022 13:18:28 +0300
+Subject: arm:dts: a20-orangepi and mini fix phy-mode, hdmi
+
+---
+ arch/arm/boot/dts/allwinner/sun7i-a20-orangepi-mini.dts |  2 +-
+ arch/arm/boot/dts/allwinner/sun7i-a20-orangepi.dts      | 31 +++++++++-
+ 2 files changed, 31 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-orangepi-mini.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-orangepi-mini.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/allwinner/sun7i-a20-orangepi-mini.dts
++++ b/arch/arm/boot/dts/allwinner/sun7i-a20-orangepi-mini.dts
+@@ -121,7 +121,7 @@ &gmac {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&gmac_rgmii_pins>;
+ 	phy-handle = <&phy1>;
+-	phy-mode = "rgmii";
++	phy-mode = "rgmii-id";
+ 	phy-supply = <&reg_gmac_3v3>;
+ 	status = "okay";
+ };
+diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-orangepi.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-orangepi.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/allwinner/sun7i-a20-orangepi.dts
++++ b/arch/arm/boot/dts/allwinner/sun7i-a20-orangepi.dts
+@@ -61,6 +61,17 @@ chosen {
+ 		stdout-path = "serial0:115200n8";
+ 	};
+ 
++	hdmi-connector {
++		compatible = "hdmi-connector";
++		type = "a";
++
++		port {
++			hdmi_con_in: endpoint {
++				remote-endpoint = <&hdmi_out_con>;
++			};
++		};
++	};
++
+ 	leds {
+ 		compatible = "gpio-leds";
+ 
+@@ -85,6 +96,14 @@ &ahci {
+ 	status = "okay";
+ };
+ 
++&codec {
++	status = "okay";
++};
++
++&de {
++	status = "okay";
++};
++
+ &ehci0 {
+ 	status = "okay";
+ };
+@@ -97,11 +116,21 @@ &gmac {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&gmac_rgmii_pins>;
+ 	phy-handle = <&phy1>;
+-	phy-mode = "rgmii";
++	phy-mode = "rgmii-id";
+ 	phy-supply = <&reg_gmac_3v3>;
+ 	status = "okay";
+ };
+ 
++&hdmi {
++	status = "okay";
++};
++
++&hdmi_out {
++	hdmi_out_con: endpoint {
++		remote-endpoint = <&hdmi_con_in>;
++	};
++};
++
+ &i2c0 {
+ 	status = "okay";
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-h3-nanopi-neo-Add-regulator-leds-mmc2.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-h3-nanopi-neo-Add-regulator-leds-mmc2.patch
new file mode 100644
index 000000000000..628fa13bfd79
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-h3-nanopi-neo-Add-regulator-leds-mmc2.patch
@@ -0,0 +1,80 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Mon, 24 Jan 2022 15:34:01 +0300
+Subject: arm:dts: h3-nanopi-neo Add regulator, leds, mmc2
+
+---
+ arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-neo.dts | 57 ++++++++++
+ 1 file changed, 57 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-neo.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-neo.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-neo.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-neo.dts
+@@ -49,6 +49,63 @@ / {
+ 	aliases {
+ 		ethernet0 = &emac;
+ 	};
++
++	/* Warning: sunxi-5.18:
++	 * The leds node is present in the sun8i-h3-nanopi.dtsi file
++	 * You will have to fix this situation yourself
++	 */
++	leds {
++		compatible = "gpio-leds";
++
++		pwr {
++			label = "nanopi:red:pwr";
++			gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */
++			linux,default-trigger = "default-on";
++		};
++
++		status {
++			label = "nanopi:green:status";
++			gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */
++			linux,default-trigger = "heartbeat";
++		};
++	};
++
++	vdd_cpux: gpio-regulator {
++		compatible = "regulator-gpio";
++		pinctrl-names = "default";
++		regulator-name = "vdd-cpux";
++		regulator-type = "voltage";
++		regulator-boot-on;
++		regulator-always-on;
++		regulator-min-microvolt = <1100000>;
++		regulator-max-microvolt = <1300000>;
++		regulator-ramp-delay = <50>; /* 4ms */
++		gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
++		gpios-states = <0x1>;
++		states = <1100000 0x0
++			  1300000 0x1>;
++	};
++};
++
++&cpu0 {
++	cpu-supply = <&vdd_cpux>;
++};
++
++&mmc2 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&mmc2_8bit_pins>;
++	vmmc-supply = <&reg_vcc3v3>;
++	bus-width = <8>;
++	non-removable;
++	cap-mmc-hw-reset;
++	status = "okay";
++};
++
++&mmc2_8bit_pins {
++	/* Increase drive strength for DDR modes */
++	drive-strength = <40>;
++	/* eMMC is missing pull-ups */
++	bias-pull-up;
+ };
+ 
+ &ehci0 {
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-h3-nanopi-neo-air-Add-regulator-camera-wifi-bluetooth-o.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-h3-nanopi-neo-air-Add-regulator-camera-wifi-bluetooth-o.patch
new file mode 100644
index 000000000000..d177b7eaa2bf
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-h3-nanopi-neo-air-Add-regulator-camera-wifi-bluetooth-o.patch
@@ -0,0 +1,196 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Mon, 24 Jan 2022 15:45:43 +0300
+Subject: arm:dts: h3-nanopi-neo-air Add regulator camera wifi bluetooth otg
+
+---
+ arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-neo-air.dts | 153 ++++++++++
+ 1 file changed, 153 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-neo-air.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-neo-air.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-neo-air.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi-neo-air.dts
+@@ -70,12 +70,92 @@ led-0 {
+ 		led-1 {
+ 			label = "nanopi:blue:status";
+ 			gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */
++			linux,default-trigger = "heartbeat";
+ 		};
+ 	};
+ 
++	vdd_cpux: gpio-regulator {
++		compatible = "regulator-gpio";
++		pinctrl-names = "default";
++		regulator-name = "vdd-cpux";
++		regulator-type = "voltage";
++		regulator-boot-on;
++		regulator-always-on;
++		regulator-min-microvolt = <1100000>;
++		regulator-max-microvolt = <1300000>;
++		regulator-ramp-delay = <50>; /* 4ms */
++		gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
++		gpios-states = <0x1>;
++		states = <1100000 0x0
++			  1300000 0x1>;
++	};
++
+ 	wifi_pwrseq: pwrseq {
+ 		compatible = "mmc-pwrseq-simple";
++		pinctrl-names = "default";
++		pinctrl-0 = <&wifi_en_npi>;
+ 		reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
++		post-power-on-delay-ms = <200>;
++	};
++
++	rfkill_bt {
++		compatible = "rfkill-gpio";
++		pinctrl-names = "default";
++		pinctrl-0 = <&bt_pwr_pin>;
++		reset-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */
++		clocks = <&osc32k>;
++		clock-frequency = <32768>;
++		rfkill-name = "sunxi-bt";
++		rfkill-type = "bluetooth";
++	};
++
++	cam_xclk: cam-xclk {
++		#clock-cells = <0>;
++		compatible = "fixed-clock";
++		clock-frequency = <24000000>;
++		clock-output-names = "cam-xclk";
++	};
++
++	reg_cam_avdd: cam-avdd {
++		compatible = "regulator-fixed";
++		regulator-name = "cam500b-avdd";
++		regulator-min-microvolt = <2800000>;
++		regulator-max-microvolt = <2800000>;
++		vin-supply = <&reg_vcc3v3>;
++	};
++
++	reg_cam_dovdd: cam-dovdd {
++		compatible = "regulator-fixed";
++		regulator-name = "cam500b-dovdd";
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		vin-supply = <&reg_vcc3v3>;
++	};
++
++	reg_cam_dvdd: cam-dvdd {
++		compatible = "regulator-fixed";
++		regulator-name = "cam500b-dvdd";
++		regulator-min-microvolt = <1500000>;
++		regulator-max-microvolt = <1500000>;
++		vin-supply = <&reg_vcc3v3>;
++	};
++};
++
++&cpu0 {
++	cpu-supply = <&vdd_cpux>;
++};
++
++&pio {
++	bt_pwr_pin: bt_pwr_pin@0 {
++		pins = "PG13";
++		function = "gpio_out";
++	};
++};
++
++&r_pio {
++	wifi_en_npi: wifi_en_pin {
++		pins = "PL7";
++		function = "gpio_out";
+ 	};
+ };
+ 
+@@ -110,6 +190,74 @@ &mmc2 {
+ 	vqmmc-supply = <&reg_vcc3v3>;
+ 	bus-width = <8>;
+ 	non-removable;
++	cap-mmc-hw-reset;
++	status = "okay";
++};
++
++&mmc2_8bit_pins {
++	/* Increase drive strength for DDR modes */
++	drive-strength = <40>;
++	/* eMMC is missing pull-ups */
++	bias-pull-up;
++};
++
++&csi {
++	status = "okay";
++
++	port {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		/* Parallel bus endpoint */
++		csi_from_ov5640: endpoint {
++			remote-endpoint = <&ov5640_to_csi>;
++			bus-width = <8>;
++			data-shift = <2>;
++			hsync-active = <1>; /* Active high */
++			vsync-active = <0>; /* Active low */
++			data-active = <1>;  /* Active high */
++			pclk-sample = <1>;  /* Rising */
++		};
++	};
++};
++
++&i2c2 {
++	status = "okay";
++	ov5640: camera@3c {
++		compatible = "ovti,ov5640";
++		reg = <0x3c>;
++		clocks = <&cam_xclk>;
++		clock-names = "xclk";
++
++		reset-gpios = <&pio 4 14 GPIO_ACTIVE_LOW>;
++		powerdown-gpios = <&pio 4 15 GPIO_ACTIVE_HIGH>;
++		AVDD-supply = <&reg_cam_avdd>;
++		DOVDD-supply = <&reg_cam_dovdd>;
++		DVDD-supply = <&reg_cam_dvdd>;
++
++		port {
++			ov5640_to_csi: endpoint {
++				remote-endpoint = <&csi_from_ov5640>;
++				bus-width = <8>;
++				data-shift = <2>;
++				hsync-active = <1>; /* Active high */
++				vsync-active = <0>; /* Active low */
++				data-active = <1>;  /* Active high */
++				pclk-sample = <1>;  /* Rising */
++			};
++		};
++	};
++};
++
++&i2c2_pins {
++	bias-pull-up;
++};
++
++&ehci0 {
++	status = "okay";
++};
++
++&ohci0 {
+ 	status = "okay";
+ };
+ 
+@@ -137,6 +285,11 @@ bluetooth {
+ 	};
+ };
+ 
++&usb_otg {
++	dr_mode = "peripheral";
++	status = "okay";
++};
++
+ &usbphy {
+ 	/* USB VBUS is always on */
+ 	status = "okay";
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-h3-orangepi-2-Add-regulator-vdd-cpu.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-h3-orangepi-2-Add-regulator-vdd-cpu.patch
new file mode 100644
index 000000000000..47ef2b500e36
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-h3-orangepi-2-Add-regulator-vdd-cpu.patch
@@ -0,0 +1,59 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Mon, 24 Jan 2022 18:23:18 +0300
+Subject: arm:dts: h3-orangepi-2 Add regulator vdd cpu
+
+---
+ arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-2.dts | 29 ++++++++++
+ 1 file changed, 29 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-2.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-2.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-2.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-2.dts
+@@ -124,6 +124,10 @@ &de {
+ 	status = "okay";
+ };
+ 
++&cpu0 {
++	cpu-supply = <&reg_vdd_cpux>;
++};
++
+ &ehci1 {
+ 	status = "okay";
+ };
+@@ -178,6 +182,31 @@ rtl8189: wifi@1 {
+ 	};
+ };
+ 
++&r_i2c {
++	status = "okay";
++
++	reg_vdd_cpux: regulator@65 {
++		compatible = "silergy,sy8106a";
++		reg = <0x65>;
++		regulator-name = "vdd-cpux";
++		silergy,fixed-microvolt = <1200000>;
++		/*
++		 * The datasheet uses 1.1V as the minimum value of VDD-CPUX,
++		 * however both the Armbian DVFS table and the official one
++		 * have operating points with voltage under 1.1V, and both
++		 * DVFS table are known to work properly at the lowest
++		 * operating point.
++		 *
++		 * Use 1.0V as the minimum voltage instead.
++		 */
++		regulator-min-microvolt = <1000000>;
++		regulator-max-microvolt = <1400000>;
++		regulator-ramp-delay = <200>;
++		regulator-boot-on;
++		regulator-always-on;
++	};
++};
++
+ &reg_usb1_vbus {
+ 	gpio = <&pio 6 13 GPIO_ACTIVE_HIGH>;
+ 	status = "okay";
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-overlay-Add-Overlays-for-sunxi.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-overlay-Add-Overlays-for-sunxi.patch
new file mode 100644
index 000000000000..e3817995d77f
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-overlay-Add-Overlays-for-sunxi.patch
@@ -0,0 +1,4964 @@
+From ab05f16488960a29e368534057af5aabea7cca78 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Wed, 2 Feb 2022 12:54:05 +0300
+Subject: arm:dts:overlay Add Overlays for sunxi
+
+---
+ arch/arm/boot/dts/allwinner/Makefile          |   2 +
+ arch/arm/boot/dts/allwinner/overlay/Makefile  |  97 +++++
+ .../overlay/README.sun4i-a10-overlays         | 278 ++++++++++++++
+ .../overlay/README.sun5i-a13-overlays         | 172 +++++++++
+ .../overlay/README.sun7i-a20-overlays         | 348 ++++++++++++++++++
+ .../overlay/README.sun8i-h3-overlays          | 250 +++++++++++++
+ .../overlay/sun4i-a10-analog-codec.dtso       |  13 +
+ .../dts/allwinner/overlay/sun4i-a10-can.dtso  |  15 +
+ .../allwinner/overlay/sun4i-a10-fixup.scr-cmd | 124 +++++++
+ .../dts/allwinner/overlay/sun4i-a10-i2c1.dtso |  22 ++
+ .../dts/allwinner/overlay/sun4i-a10-i2c2.dtso |  22 ++
+ .../dts/allwinner/overlay/sun4i-a10-nand.dtso | 103 ++++++
+ .../allwinner/overlay/sun4i-a10-pps-gpio.dtso |  29 ++
+ .../dts/allwinner/overlay/sun4i-a10-pwm.dtso  |  15 +
+ .../overlay/sun4i-a10-spdif-out.dtso          |  38 ++
+ .../overlay/sun4i-a10-spi-jedec-nor.dtso      |  57 +++
+ .../overlay/sun4i-a10-spi-spidev.dtso         |  57 +++
+ .../dts/allwinner/overlay/sun4i-a10-spi0.dtso |  23 ++
+ .../dts/allwinner/overlay/sun4i-a10-spi1.dtso |  22 ++
+ .../dts/allwinner/overlay/sun4i-a10-spi2.dtso |  23 ++
+ .../allwinner/overlay/sun4i-a10-uart2.dtso    |  37 ++
+ .../allwinner/overlay/sun4i-a10-uart3.dtso    |  47 +++
+ .../allwinner/overlay/sun4i-a10-uart4.dtso    |  37 ++
+ .../allwinner/overlay/sun4i-a10-uart5.dtso    |  32 ++
+ .../allwinner/overlay/sun4i-a10-uart6.dtso    |  32 ++
+ .../allwinner/overlay/sun4i-a10-uart7.dtso    |  32 ++
+ .../allwinner/overlay/sun4i-a10-w1-gpio.dtso  |  29 ++
+ .../overlay/sun5i-a13-analog-codec.dtso       |  13 +
+ .../allwinner/overlay/sun5i-a13-fixup.scr-cmd |  48 +++
+ .../dts/allwinner/overlay/sun5i-a13-i2c1.dtso |  22 ++
+ .../dts/allwinner/overlay/sun5i-a13-i2c2.dtso |  22 ++
+ .../dts/allwinner/overlay/sun5i-a13-nand.dtso |  60 +++
+ .../dts/allwinner/overlay/sun5i-a13-pwm.dtso  |  15 +
+ .../overlay/sun5i-a13-spi-jedec-nor.dtso      |  57 +++
+ .../overlay/sun5i-a13-spi-spidev.dtso         |  57 +++
+ .../dts/allwinner/overlay/sun5i-a13-spi0.dtso |  38 ++
+ .../dts/allwinner/overlay/sun5i-a13-spi1.dtso |  39 ++
+ .../dts/allwinner/overlay/sun5i-a13-spi2.dtso |  22 ++
+ .../allwinner/overlay/sun5i-a13-uart0.dtso    |  32 ++
+ .../allwinner/overlay/sun5i-a13-uart1.dtso    |  22 ++
+ .../allwinner/overlay/sun5i-a13-uart2.dtso    |  22 ++
+ .../allwinner/overlay/sun5i-a13-uart3.dtso    |  22 ++
+ .../overlay/sun7i-a20-analog-codec.dtso       |  13 +
+ .../dts/allwinner/overlay/sun7i-a20-can.dtso  |  15 +
+ .../allwinner/overlay/sun7i-a20-fixup.scr-cmd | 143 +++++++
+ .../dts/allwinner/overlay/sun7i-a20-i2c1.dtso |  22 ++
+ .../dts/allwinner/overlay/sun7i-a20-i2c2.dtso |  22 ++
+ .../dts/allwinner/overlay/sun7i-a20-i2c3.dtso |  22 ++
+ .../dts/allwinner/overlay/sun7i-a20-i2c4.dtso |  32 ++
+ .../dts/allwinner/overlay/sun7i-a20-i2s0.dtso |  25 ++
+ .../dts/allwinner/overlay/sun7i-a20-i2s1.dtso |  25 ++
+ .../dts/allwinner/overlay/sun7i-a20-mmc2.dtso |  18 +
+ .../dts/allwinner/overlay/sun7i-a20-nand.dtso | 103 ++++++
+ .../allwinner/overlay/sun7i-a20-pps-gpio.dtso |  29 ++
+ .../dts/allwinner/overlay/sun7i-a20-pwm.dtso  |  15 +
+ .../overlay/sun7i-a20-spdif-out.dtso          |  38 ++
+ .../overlay/sun7i-a20-spi-add-cs1.dtso        |  16 +
+ .../overlay/sun7i-a20-spi-jedec-nor.dtso      |  57 +++
+ .../overlay/sun7i-a20-spi-spidev.dtso         |  57 +++
+ .../dts/allwinner/overlay/sun7i-a20-spi0.dtso |  23 ++
+ .../dts/allwinner/overlay/sun7i-a20-spi1.dtso |  22 ++
+ .../dts/allwinner/overlay/sun7i-a20-spi2.dtso |  23 ++
+ .../allwinner/overlay/sun7i-a20-uart2.dtso    |  32 ++
+ .../allwinner/overlay/sun7i-a20-uart3.dtso    |  42 +++
+ .../allwinner/overlay/sun7i-a20-uart4.dtso    |  22 ++
+ .../allwinner/overlay/sun7i-a20-uart5.dtso    |  22 ++
+ .../allwinner/overlay/sun7i-a20-uart6.dtso    |  22 ++
+ .../allwinner/overlay/sun7i-a20-uart7.dtso    |  22 ++
+ .../allwinner/overlay/sun7i-a20-w1-gpio.dtso  |  29 ++
+ .../overlay/sun8i-h3-analog-codec.dtso        |  17 +
+ .../dts/allwinner/overlay/sun8i-h3-cir.dtso   |  15 +
+ .../allwinner/overlay/sun8i-h3-fixup.scr-cmd  | 110 ++++++
+ .../dts/allwinner/overlay/sun8i-h3-i2c0.dtso  |  20 +
+ .../dts/allwinner/overlay/sun8i-h3-i2c1.dtso  |  20 +
+ .../dts/allwinner/overlay/sun8i-h3-i2c2.dtso  |  20 +
+ .../allwinner/overlay/sun8i-h3-pps-gpio.dtso  |  29 ++
+ .../dts/allwinner/overlay/sun8i-h3-pwm.dtso   |  39 ++
+ .../allwinner/overlay/sun8i-h3-spdif-out.dtso |  38 ++
+ .../overlay/sun8i-h3-spi-add-cs1.dtso         |  41 +++
+ .../overlay/sun8i-h3-spi-jedec-nor.dtso       |  42 +++
+ .../overlay/sun8i-h3-spi-spidev.dtso          |  42 +++
+ .../dts/allwinner/overlay/sun8i-h3-uart1.dtso |  22 ++
+ .../dts/allwinner/overlay/sun8i-h3-uart2.dtso |  22 ++
+ .../dts/allwinner/overlay/sun8i-h3-uart3.dtso |  22 ++
+ .../allwinner/overlay/sun8i-h3-usbhost0.dtso  |  27 ++
+ .../allwinner/overlay/sun8i-h3-usbhost1.dtso  |  27 ++
+ .../allwinner/overlay/sun8i-h3-usbhost2.dtso  |  27 ++
+ .../allwinner/overlay/sun8i-h3-usbhost3.dtso  |  27 ++
+ .../allwinner/overlay/sun8i-h3-w1-gpio.dtso   |  29 ++
+ .../dts/allwinner/overlay/sun8i-r40-i2c2.dtso |  20 +
+ .../dts/allwinner/overlay/sun8i-r40-i2c3.dtso |  20 +
+ .../overlay/sun8i-r40-spi-spidev0.dtso        |  27 ++
+ .../overlay/sun8i-r40-spi-spidev1.dtso        |  27 ++
+ .../allwinner/overlay/sun8i-r40-uart2.dtso    |  22 ++
+ .../allwinner/overlay/sun8i-r40-uart4.dtso    |  22 ++
+ .../allwinner/overlay/sun8i-r40-uart5.dtso    |  22 ++
+ .../allwinner/overlay/sun8i-r40-uart7.dtso    |  22 ++
+ 97 files changed, 4176 insertions(+)
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/Makefile
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/README.sun4i-a10-overlays
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/README.sun5i-a13-overlays
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/README.sun7i-a20-overlays
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/README.sun8i-h3-overlays
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun4i-a10-analog-codec.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun4i-a10-can.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun4i-a10-fixup.scr-cmd
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun4i-a10-i2c1.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun4i-a10-i2c2.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun4i-a10-nand.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun4i-a10-pps-gpio.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun4i-a10-pwm.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun4i-a10-spdif-out.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun4i-a10-spi-jedec-nor.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun4i-a10-spi-spidev.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun4i-a10-spi0.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun4i-a10-spi1.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun4i-a10-spi2.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun4i-a10-uart2.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun4i-a10-uart3.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun4i-a10-uart4.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun4i-a10-uart5.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun4i-a10-uart6.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun4i-a10-uart7.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun4i-a10-w1-gpio.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun5i-a13-analog-codec.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun5i-a13-fixup.scr-cmd
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun5i-a13-i2c1.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun5i-a13-i2c2.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun5i-a13-nand.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun5i-a13-pwm.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun5i-a13-spi-jedec-nor.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun5i-a13-spi-spidev.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun5i-a13-spi0.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun5i-a13-spi1.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun5i-a13-spi2.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun5i-a13-uart0.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun5i-a13-uart1.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun5i-a13-uart2.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun5i-a13-uart3.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun7i-a20-analog-codec.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun7i-a20-can.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun7i-a20-fixup.scr-cmd
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun7i-a20-i2c1.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun7i-a20-i2c2.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun7i-a20-i2c3.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun7i-a20-i2c4.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun7i-a20-i2s0.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun7i-a20-i2s1.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun7i-a20-mmc2.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun7i-a20-nand.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun7i-a20-pps-gpio.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun7i-a20-pwm.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun7i-a20-spdif-out.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun7i-a20-spi-add-cs1.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun7i-a20-spi-jedec-nor.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun7i-a20-spi-spidev.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun7i-a20-spi0.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun7i-a20-spi1.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun7i-a20-spi2.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun7i-a20-uart2.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun7i-a20-uart3.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun7i-a20-uart4.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun7i-a20-uart5.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun7i-a20-uart6.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun7i-a20-uart7.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun7i-a20-w1-gpio.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-h3-analog-codec.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-h3-cir.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-h3-fixup.scr-cmd
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-h3-i2c0.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-h3-i2c1.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-h3-i2c2.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-h3-pps-gpio.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-h3-pwm.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-h3-spdif-out.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-h3-spi-add-cs1.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-h3-spi-jedec-nor.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-h3-spi-spidev.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-h3-uart1.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-h3-uart2.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-h3-uart3.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-h3-usbhost0.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-h3-usbhost1.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-h3-usbhost2.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-h3-usbhost3.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-h3-w1-gpio.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-r40-i2c2.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-r40-i2c3.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-r40-spi-spidev0.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-r40-spi-spidev1.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-r40-uart2.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-r40-uart4.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-r40-uart5.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-r40-uart7.dtso
+
+diff --git a/arch/arm/boot/dts/allwinner/Makefile b/arch/arm/boot/dts/allwinner/Makefile
+index 2e8615538458..ff32410674de 100644
+--- a/arch/arm/boot/dts/allwinner/Makefile
++++ b/arch/arm/boot/dts/allwinner/Makefile
+@@ -272,3 +272,5 @@ dtb-$(CONFIG_MACH_SUNIV) += \
+ 	suniv-f1c100s-licheepi-nano.dtb \
+ 	suniv-f1c200s-lctech-pi.dtb \
+ 	suniv-f1c200s-popstick-v1.1.dtb
++
++subdir-y	:= overlay
+diff --git a/arch/arm/boot/dts/allwinner/overlay/Makefile b/arch/arm/boot/dts/allwinner/overlay/Makefile
+new file mode 100644
+index 000000000000..0c47e8fda8fc
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/Makefile
+@@ -0,0 +1,97 @@
++# SPDX-License-Identifier: GPL-2.0
++dtb-$(CONFIG_MACH_SUN4I) += \
++	sun4i-a10-analog-codec.dtbo \
++	sun4i-a10-can.dtbo \
++	sun4i-a10-i2c1.dtbo \
++	sun4i-a10-i2c2.dtbo \
++	sun4i-a10-nand.dtbo \
++	sun4i-a10-pps-gpio.dtbo \
++	sun4i-a10-pwm.dtbo \
++	sun4i-a10-spdif-out.dtbo \
++	sun4i-a10-spi-jedec-nor.dtbo \
++	sun4i-a10-spi-spidev.dtbo \
++	sun4i-a10-uart2.dtbo \
++	sun4i-a10-uart3.dtbo \
++	sun4i-a10-uart4.dtbo \
++	sun4i-a10-uart5.dtbo \
++	sun4i-a10-uart6.dtbo \
++	sun4i-a10-uart7.dtbo \
++	sun4i-a10-w1-gpio.dtbo
++
++dtb-$(CONFIG_MACH_SUN5I) += \
++	sun5i-a13-analog-codec.dtbo \
++	sun5i-a13-i2c1.dtbo \
++	sun5i-a13-i2c2.dtbo \
++	sun5i-a13-nand.dtbo \
++	sun5i-a13-pwm.dtbo \
++	sun5i-a13-spi0.dtbo \
++	sun5i-a13-spi1.dtbo \
++	sun5i-a13-spi2.dtbo \
++	sun5i-a13-spi-jedec-nor.dtbo \
++	sun5i-a13-spi-spidev.dtbo \
++	sun5i-a13-uart0.dtbo \
++	sun5i-a13-uart1.dtbo \
++	sun5i-a13-uart2.dtbo \
++	sun5i-a13-uart3.dtbo
++
++dtb-$(CONFIG_MACH_SUN7I) += \
++	sun7i-a20-analog-codec.dtbo \
++	sun7i-a20-can.dtbo \
++	sun7i-a20-i2c1.dtbo \
++	sun7i-a20-i2c2.dtbo \
++	sun7i-a20-i2c3.dtbo \
++	sun7i-a20-i2c4.dtbo \
++	sun7i-a20-mmc2.dtbo \
++	sun7i-a20-nand.dtbo \
++	sun7i-a20-pps-gpio.dtbo \
++	sun7i-a20-pwm.dtbo \
++	sun7i-a20-spdif-out.dtbo \
++	sun7i-a20-spi-add-cs1.dtbo \
++	sun7i-a20-spi-jedec-nor.dtbo \
++	sun7i-a20-spi-spidev.dtbo \
++	sun7i-a20-uart2.dtbo \
++	sun7i-a20-uart3.dtbo \
++	sun7i-a20-uart4.dtbo \
++	sun7i-a20-uart5.dtbo \
++	sun7i-a20-uart6.dtbo \
++	sun7i-a20-uart7.dtbo \
++	sun7i-a20-w1-gpio.dtbo
++
++dtb-$(CONFIG_MACH_SUN8I) += \
++	sun8i-h3-analog-codec.dtbo \
++	sun8i-h3-cir.dtbo \
++	sun8i-h3-i2c0.dtbo \
++	sun8i-h3-i2c1.dtbo \
++	sun8i-h3-i2c2.dtbo \
++	sun8i-h3-pps-gpio.dtbo \
++	sun8i-h3-pwm.dtbo \
++	sun8i-h3-spdif-out.dtbo \
++	sun8i-h3-spi-add-cs1.dtbo \
++	sun8i-h3-spi-jedec-nor.dtbo \
++	sun8i-h3-spi-spidev.dtbo \
++	sun8i-h3-uart1.dtbo \
++	sun8i-h3-uart2.dtbo \
++	sun8i-h3-uart3.dtbo \
++	sun8i-h3-usbhost0.dtbo \
++	sun8i-h3-usbhost1.dtbo \
++	sun8i-h3-usbhost2.dtbo \
++	sun8i-h3-usbhost3.dtbo \
++	sun8i-h3-w1-gpio.dtbo \
++	sun8i-r40-i2c2.dtbo \
++	sun8i-r40-i2c3.dtbo \
++	sun8i-r40-spi-spidev0.dtbo \
++	sun8i-r40-spi-spidev1.dtbo \
++	sun8i-r40-uart2.dtbo \
++	sun8i-r40-uart4.dtbo \
++	sun8i-r40-uart5.dtbo \
++	sun8i-r40-uart7.dtbo
++
++scr-$(CONFIG_MACH_SUN4I) += sun4i-a10-fixup.scr
++scr-$(CONFIG_MACH_SUN5I) += sun5i-a13-fixup.scr
++scr-$(CONFIG_MACH_SUN7I) += sun7i-a20-fixup.scr
++scr-$(CONFIG_MACH_SUN8I) += sun8i-h3-fixup.scr
++
++dtbotxt-$(CONFIG_MACH_SUN4I) += README.sun4i-a10-overlays
++dtbotxt-$(CONFIG_MACH_SUN5I) += README.sun5i-a13-overlays
++dtbotxt-$(CONFIG_MACH_SUN7I) += README.sun7i-a20-overlays
++dtbotxt-$(CONFIG_MACH_SUN8I) += README.sun8i-h3-overlays
+diff --git a/arch/arm/boot/dts/allwinner/overlay/README.sun4i-a10-overlays b/arch/arm/boot/dts/allwinner/overlay/README.sun4i-a10-overlays
+new file mode 100644
+index 000000000000..e0795f13ddf1
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/README.sun4i-a10-overlays
+@@ -0,0 +1,278 @@
++This document describes overlays provided in the kernel packages
++For generic Armbian overlays documentation please see
++https://docs.armbian.com/User-Guide_Allwinner_overlays/
++
++### Platform:
++
++sun4i-a10 (Allwinner A10)
++
++### Platform details:
++
++Supported pin banks: PB, PC, PD, PE, PG, PH, PI
++
++SPI controller 0 have 2 exposed hardware CS,
++other SPI controllers have only one hardware CS
++Reference: A10 User manual section 17.4.13, A10 datasheet section 5.2
++
++I2C bus 0 is used for the AXP209 PMIC
++
++### Provided overlays:
++
++- analog-codec
++- can
++- i2c1
++- i2c2
++- nand
++- pps-gpio
++- pwm
++- spdif-out
++- spi0
++- spi1
++- spi2
++- spi-jedec-nor
++- spi-spidev
++- uart1
++- uart2
++- uart3
++- uart4
++- uart5
++- uart6
++- uart7
++- w1-gpio
++
++### Overlay details:
++
++### analog-codec
++
++Activates SoC analog codec driver that provides Line Out and Mic In
++functionality
++
++## can
++
++Activates SoC CAN controller
++
++CAN pins (TX, RX): PH20, PH21
++
++### i2c1
++
++Activates TWI/I2C bus 1
++
++I2C1 pins (SCL, SDA): PB18, PB19
++
++### i2c2
++
++Activates TWI/I2C bus 2
++
++I2C2 pins (SCL, SDA): PB20, PB21
++
++### nand
++
++Activates NAND controller
++
++This overlay should not be used until mainline MLC NAND support
++allows using NAND storage reliably
++
++### pps-gpio
++
++Activates pulse-per-second GPIO client
++
++Parameters:
++
++param_pps_pin (pin)
++	Pin PPS source is connected to
++	Optional
++	Default: PI15
++
++param_pps_falling_edge (bool)
++	Assert by falling edge
++	Optional
++	Default: 0
++	When set (to 1), assert is indicated by a falling edge
++		(instead of by a rising edge)
++
++### pwm
++
++Activates hardware PWM controller
++
++PWM pins (PWM0, PWM1): PB2, PI3
++
++Parameters:
++
++param_pwm_pins (string)
++	PWM pins activated with this overlay
++	Optional
++	Default: both
++	Supported values: 0, 1, both
++	If set to 0 only PWM0 can be used,
++		if set to 1 then only PWM1 can be used,
++		if set to both (default), both PWM0 and PWM1 can be used
++
++### spdif-out
++
++Activates SPDIF/Toslink audio output
++
++SPDIF pin: PB13
++
++### spi0
++
++Activates SPI controller 0 to use it with other overlays and sets up the pin multiplexing for it
++
++SPI 0 pins (MOSI, MISO, SCK, CS0, CS1): PI12, PI13, PI11, PI10, PI14
++
++### spi1
++
++Activates SPI controller 1 to use it with other overlays and sets up the pin multiplexing for it
++
++SPI 1 pins (MOSI, MISO, SCK, CS0): PI18, PI19, PI17, PI16
++
++### spi2
++
++Activates SPI controller 2 to use it with other overlays and sets up the pin multiplexing for it
++
++SPI 2 pins a (MOSI, MISO, SCK, CS0): PC21, PC22, PC20, PC19
++SPI 2 pins b (MOSI, MISO, SCK, CS0): PB16, PB17, PB15, PB14
++
++Parameters:
++
++param_spi2_bus_pins (char)
++	SPI bus 2 pinmux variant
++	Optional
++	Default: a
++	Supported values: a, b
++	Determines what pins SPI bus 2 is exposed on if SPI 2 is used
++
++
++### spi-jedec-nor
++
++Activates MTD support for JEDEC compatible SPI NOR flash chips on SPI bus
++supported by the kernel SPI NOR driver
++
++SPI 0 pins (MOSI, MISO, SCK, CS0, CS1): PI12, PI13, PI11, PI10, PI14
++SPI 1 pins (MOSI, MISO, SCK, CS0): PI18, PI19, PI17, PI16
++SPI 2 pins a (MOSI, MISO, SCK, CS0): PC21, PC22, PC20, PC19
++SPI 2 pins b (MOSI, MISO, SCK, CS0): PB16, PB17, PB15, PB14
++
++Parameters:
++
++param_spinor_spi_bus (int)
++	SPI bus to activate SPI NOR flash support on
++	Required
++	Supported values: 0, 1, 2
++
++param_spinor_max_freq (int)
++	Maximum SPI frequency
++	Optional
++	Default: 1000000
++	Range: 3000 - 100000000
++
++### spi-spidev
++
++Activates SPIdev device node (/dev/spidevX.Y) for userspace SPI access,
++where X is the bus number and Y is the CS number
++
++SPI 0 pins (MOSI, MISO, SCK, CS0, CS1): PI12, PI13, PI11, PI10, PI14
++SPI 1 pins (MOSI, MISO, SCK, CS0): PI18, PI19, PI17, PI16
++SPI 2 pins a (MOSI, MISO, SCK, CS0): PC21, PC22, PC20, PC19
++SPI 2 pins b (MOSI, MISO, SCK, CS0): PB16, PB17, PB15, PB14
++
++Parameters:
++
++param_spidev_spi_bus (int)
++	SPI bus to activate mcp2515 support on
++	Required
++	Supported values: 0, 1, 2
++
++param_spidev_max_freq (int)
++	Maximum SPIdev frequency
++	Optional
++	Default: 1000000
++	Range: 3000 - 100000000
++
++### uart2
++
++Activates serial port 2 (/dev/ttyS2)
++
++UART 2 pins (TX, RX, RTS, CTS): PI18, PI19, PI16, PI17
++
++Parameters:
++
++param_uart2_rtscts (bool)
++	Enable RTS and CTS pins
++	Optional
++	Default: 0
++	Set to 1 to enable CTS and RTS pins
++
++### uart3
++
++Activates serial port 3 (/dev/ttyS3)
++
++UART 3 pins a (TX, RX, RTS, CTS): PG6, PG7, PG8, PG9
++UART 3 pins b (TX, RX, RTS, CTS): PH0, PH1, PH2, PH3
++
++Parameters:
++
++param_uart3_pins (char)
++	Determines what pins UART 3 is exposed on
++	Optional
++	Default: a
++	Supported values: a, b
++
++param_uart3_rtscts (bool)
++	Enable RTS and CTS pins
++	Optional
++	Default: 0
++	Set to 1 to enable CTS and RTS pins
++
++### uart4
++
++Activates serial port 4 (/dev/ttyS4)
++
++UART 4 pins a (TX, RX): PG10, PG11
++UART 4 pins b (TX, RX): PH4, PH5
++
++Parameters:
++
++param_uart4_pins (char)
++	Determines what pins UART 4 is exposed on
++	Optional
++	Default: a
++	Supported values: a, b
++
++### uart 5
++
++Activates serial port 5 (/dev/ttyS5)
++
++UART 5 pins (TX, RX): PH6, PH7
++
++### uart 6
++
++Activates serial port 6 (/dev/ttyS6)
++
++UART 6 pins (TX, RX): PI12, PI13
++
++### uart 7
++
++Activates serial port 7 (/dev/ttyS7)
++
++UART 7 pins (TX, RX): PI20, PI21
++
++### w1-gpio
++
++Activates 1-Wire GPIO master
++Requires an external pull-up resistor on the data pin
++or enabling the internal pull-up
++
++Parameters:
++
++param_w1_pin (pin)
++	Data pin for 1-Wire master
++	Optional
++	Default: PI15
++
++param_w1_pin_int_pullup (bool)
++	Enable internal pull-up for the data pin
++	Optional
++	Default: 0
++	Set to 1 to enable the pull-up
++	This option should not be used with multiple sensors or long wires -
++		please use external pull-up resistor instead
+diff --git a/arch/arm/boot/dts/allwinner/overlay/README.sun5i-a13-overlays b/arch/arm/boot/dts/allwinner/overlay/README.sun5i-a13-overlays
+new file mode 100644
+index 000000000000..9f9653f09573
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/README.sun5i-a13-overlays
+@@ -0,0 +1,172 @@
++This document describes overlays provided in the kernel packages
++For generic Armbian overlays documentation please see
++https://docs.armbian.com/User-Guide_Allwinner_overlays/
++
++### Platform:
++
++sun5i-a13 (Allwinner A13)
++
++### Platform details:
++
++I2C bus 0 is used for the AXP209 PMIC
++
++### Provided overlays:
++
++- analog-codec
++- i2c1
++- i2c2
++- nand
++- pwm
++- spi0
++- spi1
++- spi2
++- spi-jedec-nor
++- spi-spidev
++- uart0
++- uart1
++- uart2
++- uart3
++
++### Overlay details:
++
++### analog-codec
++
++Activates SoC analog codec driver that provides HP Out and Mic In
++functionality
++
++### i2c1
++
++Activates TWI/I2C bus 1
++
++I2C1 pins (SCL, SDA): PB15, PB16
++
++### i2c2
++
++Activates TWI/I2C bus 2
++
++I2C2 pins (SCL, SDA): PB17, PB18
++
++### nand
++
++Activates NAND controller
++
++This overlay should not be used until mainline MLC NAND support
++allows using NAND storage reliably
++
++### pwm
++
++Activates hardware PWM controller
++
++PWM pins (PWM0): PB2
++
++### spi0
++
++Activates SPI controller 0 to use it with other overlays and sets up the pin multiplexing for it
++
++SPI 0 pins (MOSI, MISO, SCK, CS0): PC0, PC1, PC2, PC3
++
++### spi1
++
++Activates SPI controller 1 to use it with other overlays and sets up the pin multiplexing for it
++
++SPI 1 pins (MOSI, MISO, SCK, CS0): PG11, PG12, PG10, PG9
++
++### spi2
++
++Activates SPI controller 2 to use it with other overlays and sets up the pin multiplexing for it
++
++SPI 2 pins (MOSI, MISO, SCK, CS0): PE2, PE3, PE1, PE0
++
++### spi-jedec-nor
++
++Activates MTD support for JEDEC compatible SPI NOR flash chips on SPI bus
++supported by the kernel SPI NOR driver
++
++SPI 0 pins (MOSI, MISO, SCK, CS0): PC0, PC1, PC2, PC3
++SPI 1 pins (MOSI, MISO, SCK, CS0): PG11, PG12, PG10, PG9
++SPI 2 pins (MOSI, MISO, SCK, CS0): PE2, PE3, PE1, PE0
++
++Parameters:
++
++param_spinor_spi_bus (int)
++	SPI bus to activate SPI NOR flash support on
++	Required
++	Supported values: 0, 1, 2
++
++param_spinor_max_freq (int)
++	Maximum SPI frequency
++	Optional
++	Default: 1000000
++	Range: 3000 - 100000000
++
++### spi-spidev
++
++Activates SPIdev device node (/dev/spidevX.Y) for userspace SPI access,
++where X is the bus number and Y is the CS number
++
++SPI 0 pins (MOSI, MISO, SCK, CS0): PC0, PC1, PC2, PC3
++SPI 1 pins (MOSI, MISO, SCK, CS0): PG11, PG12, PG10, PG9
++SPI 2 pins (MOSI, MISO, SCK, CS0): PE2, PE3, PE1, PE0
++
++Parameters:
++
++param_spidev_spi_bus (int)
++	SPI bus to activate mcp2515 support on
++	Required
++	Supported values: 0, 1, 2
++
++param_spidev_max_freq (int)
++	Maximum SPIdev frequency
++	Optional
++	Default: 1000000
++	Range: 3000 - 100000000
++
++### uart 0
++
++Activates serial port 0 (/dev/ttyS0)
++
++UART 0 pins (TX, RX): PF2, PF4
++
++### uart 1
++
++Activates serial port 1 (/dev/ttyS1)
++
++UART 1 pins a (TX, RX): PE10, PE11
++UART 1 pins b (TX, RX): PG3, PG4
++
++Parameters:
++
++param_uart1_pins (char)
++	UART 1 pinmux variant
++	Optional
++	Default: a
++	Supported values: a, b
++	Determines what pins UART 1 is exposed on if UART 1 is used
++
++### uart2
++
++Activates serial port 2 (/dev/ttyS2)
++
++UART 2 pins (TX, RX, RTS, CTS): PD2, PD3, PD4, PD5
++
++Parameters:
++
++param_uart2_rtscts (bool)
++	Enable RTS and CTS pins
++	Optional
++	Default: 0
++	Set to 1 to enable CTS and RTS pins
++
++### uart3
++
++Activates serial port 3 (/dev/ttyS3)
++
++UART 3 pins (TX, RX, RTS, CTS): PG9, PG10, PG12, PG11
++
++Parameters:
++
++param_uart3_rtscts (bool)
++	Enable RTS and CTS pins
++	Optional
++	Default: 0
++	Set to 1 to enable CTS and RTS pins
+diff --git a/arch/arm/boot/dts/allwinner/overlay/README.sun7i-a20-overlays b/arch/arm/boot/dts/allwinner/overlay/README.sun7i-a20-overlays
+new file mode 100644
+index 000000000000..362f87961135
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/README.sun7i-a20-overlays
+@@ -0,0 +1,348 @@
++This document describes overlays provided in the kernel packages
++For generic Armbian overlays documentation please see
++https://docs.armbian.com/User-Guide_Allwinner_overlays/
++
++### Platform:
++
++sun7i-a20 (Allwinner A20)
++
++### Platform details:
++
++Supported pin banks: PB, PC, PD, PE, PG, PH, PI
++
++SPI controller 0 have 2 exposed hardware CS,
++other SPI controllers have only one hardware CS
++Reference: A20 Datasheet sections 6.3.5.1, 1.19.2
++
++I2C bus 0 is used for the AXP209 PMIC
++
++### Provided overlays:
++
++- analog-codec
++- can
++- i2c1
++- i2c2
++- i2c3
++- i2c4
++- i2s0
++- i2s1
++- mmc2
++- nand
++- pps-gpio
++- pwm
++- spdif-out
++- spi0
++- spi1
++- spi2
++- spi-add-cs1
++- spi-jedec-nor
++- spi-spidev
++- uart1
++- uart2
++- uart3
++- uart4
++- uart5
++- uart6
++- uart7
++- w1-gpio
++
++### Overlay details:
++
++### analog-codec
++
++Activates SoC analog codec driver that provides Line Out and Mic In
++functionality
++
++## can
++
++Activates SoC CAN controller
++
++CAN pins (TX, RX): PH20, PH21
++
++### i2c1
++
++Activates TWI/I2C bus 1
++
++I2C1 pins (SCL, SDA): PB18, PB19
++
++### i2c2
++
++Activates TWI/I2C bus 2
++
++I2C2 pins (SCL, SDA): PB20, PB21
++
++### i2c3
++
++Activates TWI/I2C bus 3
++
++I2C3 pins (SCL, SDA): PI0, PI1
++
++### i2c4
++
++Activates TWI/I2C bus 4
++
++I2C4 pins (SCL, SDA): PI2, PI3
++
++### i2s0
++
++Activates SoC I2S controller 0
++
++I2S0 pins (MCLK, BCLK, LRCK, DO0, DO1, DO2, DO3, DI): PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12
++
++### i2s1
++
++Activates SoC I2S controller 1
++
++I2S1 pins (MCLK, BCLK, LRCK, DO, DI): PA9, PA14, PA15, PA16, PA17
++
++### mmc2
++
++Activates SD/MMC controller 2. To be used on boards with second SD slot, eMMC
++or tSD instead of NAND storage.
++
++MMC2 pins: PC6, PC7, PC8, PC9, PC10, PC11
++
++Parameters:
++
++param_mmc2_cd_pin (pin)
++	SD/MMC 2 card detect pin
++	Optional
++	Default: PH0
++
++param_mmc2_non_removable (bool)
++	Option for non-removable storage options on MMC 2 controller (eMMC or tSD)
++	Optional
++	Default: 0
++	Set to 1 to use this option
++
++### nand
++
++Activates NAND controller
++
++This overlay should not be used until mainline MLC NAND support
++allows using NAND storage reliably
++
++### pps-gpio
++
++Activates pulse-per-second GPIO client
++
++Parameters:
++
++param_pps_pin (pin)
++	Pin PPS source is connected to
++	Optional
++	Default: PI15
++
++param_pps_falling_edge (bool)
++	Assert by falling edge
++	Optional
++	Default: 0
++	When set (to 1), assert is indicated by a falling edge
++		(instead of by a rising edge)
++
++### pwm
++
++Activates hardware PWM controller
++
++PWM pins (PWM0, PWM1): PB2, PI3
++
++Parameters:
++
++param_pwm_pins (string)
++	PWM pins activated with this overlay
++	Optional
++	Default: both
++	Supported values: 0, 1, both
++	If set to 0 only PWM0 can be used,
++		if set to 1 then only PWM1 can be used,
++		if set to both (default), both PWM0 and PWM1 can be used
++
++### spdif-out
++
++Activates SPDIF/Toslink audio output
++
++SPDIF pin: PB13
++
++### spi0
++
++Activates SPI controller 0 to use it with other overlays and sets up the pin multiplexing for it
++
++SPI 0 pins (MOSI, MISO, SCK, CS0, CS1): PI12, PI13, PI11, PI10, PI14
++
++### spi1
++
++Activates SPI controller 1 to use it with other overlays and sets up the pin multiplexing for it
++
++SPI 1 pins (MOSI, MISO, SCK, CS0): PI18, PI19, PI17, PI16
++
++### spi2
++
++Activates SPI controller 2 to use it with other overlays and sets up the pin multiplexing for it
++
++SPI 2 pins a (MOSI, MISO, SCK, CS0): PC21, PC22, PC20, PC19
++SPI 2 pins b (MOSI, MISO, SCK, CS0): PB16, PB17, PB15, PB14
++
++Parameters:
++
++param_spi2_bus_pins (char)
++	SPI bus 2 pinmux variant
++	Optional
++	Default: a
++	Supported values: a, b
++	Determines what pins SPI bus 2 is exposed on if SPI 2 is used
++
++### spi-add-cs1
++
++Activates SPI chip select 1 on SPI controller 0
++This overlay is required for using chip select 1 with other SPI overlays
++
++SPI 0 CS1 pin: PI14
++
++### spi-jedec-nor
++
++Activates MTD support for JEDEC compatible SPI NOR flash chips on SPI bus
++supported by the kernel SPI NOR driver
++
++SPI 0 pins (MOSI, MISO, SCK, CS0, CS1): PI12, PI13, PI11, PI10, PI14
++SPI 1 pins (MOSI, MISO, SCK, CS0): PI18, PI19, PI17, PI16
++SPI 2 pins a (MOSI, MISO, SCK, CS0): PC21, PC22, PC20, PC19
++SPI 2 pins b (MOSI, MISO, SCK, CS0): PB16, PB17, PB15, PB14
++
++Parameters:
++
++param_spinor_spi_bus (int)
++	SPI bus to activate SPI NOR flash support on
++	Required
++	Supported values: 0, 1, 2
++
++param_spinor_spi_cs (int)
++	SPI chip select number for SPI NOR connected to SPI bus 0
++	Optional
++	Default: 0
++	Supported values: 0, 1
++	Using chip select 1 on SPI 0 requires using "spi-add-cs1" overlay
++
++param_spinor_max_freq (int)
++	Maximum SPI frequency
++	Optional
++	Default: 1000000
++	Range: 3000 - 100000000
++
++### spi-spidev
++
++Activates SPIdev device node (/dev/spidevX.Y) for userspace SPI access,
++where X is the bus number and Y is the CS number
++
++SPI 0 pins (MOSI, MISO, SCK, CS0, CS1): PI12, PI13, PI11, PI10, PI14
++SPI 1 pins (MOSI, MISO, SCK, CS0): PI18, PI19, PI17, PI16
++SPI 2 pins a (MOSI, MISO, SCK, CS0): PC21, PC22, PC20, PC19
++SPI 2 pins b (MOSI, MISO, SCK, CS0): PB16, PB17, PB15, PB14
++
++Parameters:
++
++param_spidev_spi_bus (int)
++	SPI bus to activate mcp2515 support on
++	Required
++	Supported values: 0, 1, 2
++
++param_spidev_spi_cs (int)
++	SPI chip select number for SPIdev on SPI bus 0
++	Optional
++	Default: 0
++	Supported values: 0, 1
++	Using chip select 1 on SPI 0 requires using "spi-add-cs1" overlay
++
++param_spidev_max_freq (int)
++	Maximum SPIdev frequency
++	Optional
++	Default: 1000000
++	Range: 3000 - 100000000
++
++### uart2
++
++Activates serial port 2 (/dev/ttyS2)
++
++UART 2 pins (TX, RX, RTS, CTS): PI18, PI19, PI16, PI17
++
++Parameters:
++
++param_uart2_rtscts (bool)
++	Enable RTS and CTS pins
++	Optional
++	Default: 0
++	Set to 1 to enable CTS and RTS pins
++
++### uart3
++
++Activates serial port 3 (/dev/ttyS3)
++
++UART 3 pins a (TX, RX, RTS, CTS): PG6, PG7, PG8, PG9
++UART 3 pins b (TX, RX, RTS, CTS): PH0, PH1, PH2, PH3
++
++Parameters:
++
++param_uart3_pins (char)
++	Determines what pins UART 3 is exposed on
++	Optional
++	Default: a
++	Supported values: a, b
++
++param_uart3_rtscts (bool)
++	Enable RTS and CTS pins
++	Optional
++	Default: 0
++	Set to 1 to enable CTS and RTS pins
++
++### uart4
++
++Activates serial port 4 (/dev/ttyS4)
++
++UART 4 pins a (TX, RX): PG10, PG11
++UART 4 pins b (TX, RX): PH4, PH5
++
++Parameters:
++
++param_uart4_pins (char)
++	Determines what pins UART 4 is exposed on
++	Optional
++	Default: a
++	Supported values: a, b
++
++### uart 5
++
++Activates serial port 5 (/dev/ttyS5)
++
++UART 5 pins (TX, RX): PH6, PH7
++
++### uart 6
++
++Activates serial port 6 (/dev/ttyS6)
++
++UART 6 pins (TX, RX): PI12, PI13
++
++### uart 7
++
++Activates serial port 7 (/dev/ttyS7)
++
++UART 7 pins (TX, RX): PI20, PI21
++
++### w1-gpio
++
++Activates 1-Wire GPIO master
++Requires an external pull-up resistor on the data pin
++or enabling the internal pull-up
++
++Parameters:
++
++param_w1_pin (pin)
++	Data pin for 1-Wire master
++	Optional
++	Default: PI15
++
++param_w1_pin_int_pullup (bool)
++	Enable internal pull-up for the data pin
++	Optional
++	Default: 0
++	Set to 1 to enable the pull-up
++	This option should not be used with multiple sensors or long wires -
++		please use external pull-up resistor instead
+diff --git a/arch/arm/boot/dts/allwinner/overlay/README.sun8i-h3-overlays b/arch/arm/boot/dts/allwinner/overlay/README.sun8i-h3-overlays
+new file mode 100644
+index 000000000000..302973491051
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/README.sun8i-h3-overlays
+@@ -0,0 +1,250 @@
++This document describes overlays provided in the kernel packages
++For generic Armbian overlays documentation please see
++https://docs.armbian.com/User-Guide_Allwinner_overlays/
++
++### Platform:
++
++sun8i-h3 (Allwinner H3)
++
++### Platform details:
++
++Supported pin banks: PA, PC, PD, PG
++
++Both SPI controllers have only one hardware CS pin exposed,
++adding fixed software (GPIO) chip selects is possible with a separate overlay
++
++### Provided overlays:
++
++- analog-codec
++- cir
++- i2c0
++- i2c1
++- i2c2
++- pps-gpio
++- pwm
++- spdif-out
++- spi-add-cs1
++- spi-jedec-nor
++- spi-spidev
++- uart1
++- uart2
++- uart3
++- usbhost0
++- usbhost1
++- usbhost2
++- usbhost3
++- w1-gpio
++
++### Overlay details:
++
++### analog-codec
++
++Activates SoC analog codec driver that provides Line Out and Mic In
++functionality
++
++### cir
++
++Activates CIR (Infrared remote) receiver
++
++CIR pin: PL11
++
++### i2c0
++
++Activates TWI/I2C bus 0
++
++I2C0 pins (SCL, SDA): PA11, PA12
++
++### i2c1
++
++Activates TWI/I2C bus 1
++
++I2C1 pins (SCL, SDA): PA18, PA19
++
++### i2c2
++
++Activates TWI/I2C bus 2
++
++I2C2 pins (SCL, SDA): PE12, PE13
++
++On most board this bus is wired to Camera (CSI) socket
++
++### pps-gpio
++
++Activates pulse-per-second GPIO client
++
++Parameters:
++
++param_pps_pin (pin)
++	Pin PPS source is connected to
++	Optional
++	Default: PD14
++
++param_pps_falling_edge (bool)
++	Assert by falling edge
++	Optional
++	Default: 0
++	When set (to 1), assert is indicated by a falling edge
++		(instead of by a rising edge)
++
++### pwm
++
++Activates hardware PWM controller
++
++PWM pin: PA5
++
++Pin PA5 is used as UART0 RX by default, so if this overlay is activated,
++UART0 and kernel console on ttyS0 will be disabled
++
++### spdif-out
++
++Activates SPDIF/Toslink audio output
++
++SPDIF pin: PA17
++
++### spi-add-cs1
++
++Adds support for using SPI chip select 1 with GPIO for both SPI controllers
++Respective GPIO will be claimed only if controller is enabled by another
++overlay
++This overlay is required for using chip select 1 with other SPI overlays
++Due to the u-boot limitations CS1 pin can't be customized by a parameter, but
++it can be changed by using an edited copy of this overlay
++A total of 4 chip selects can be used with custom overlays (1 HW + 3 GPIO)
++
++SPI 0 pins (CS1): PA21
++SPI 1 pins (CS1): PA10
++
++### spi-jedec-nor
++
++Activates MTD support for JEDEC compatible SPI NOR flash chips on SPI bus
++supported by the kernel SPI NOR driver
++
++SPI 0 pins (MOSI, MISO, SCK, CS): PC0, PC1, PC2, PC3
++SPI 1 pins (MOSI, MISO, SCK, CS): PA15, PA16, PA14, PA13
++
++Parameters:
++
++param_spinor_spi_bus (int)
++	SPI bus to activate SPI NOR flash support on
++	Required
++	Supported values: 0, 1
++
++param_spinor_spi_cs (int)
++	SPI chip select number
++	Optional
++	Default: 0
++	Supported values: 0, 1
++	Using chip select 1 requires using "spi-add-cs1" overlay
++
++param_spinor_max_freq (int)
++	Maximum SPI frequency
++	Optional
++	Default: 1000000
++	Range: 3000 - 100000000
++
++### spi-spidev
++
++Activates SPIdev device node (/dev/spidevX.Y) for userspace SPI access,
++where X is the bus number and Y is the CS number
++
++SPI 0 pins (MOSI, MISO, SCK, CS): PC0, PC1, PC2, PC3
++SPI 1 pins (MOSI, MISO, SCK, CS): PA15, PA16, PA14, PA13
++
++Parameters:
++
++param_spidev_spi_bus (int)
++	SPI bus to activate SPIdev support on
++	Required
++	Supported values: 0, 1
++
++param_spidev_spi_cs (int)
++	SPI chip select number
++	Optional
++	Default: 0
++	Supported values: 0, 1
++	Using chip select 1 requires using "spi-add-cs1" overlay
++
++param_spidev_max_freq (int)
++	Maximum SPIdev frequency
++	Optional
++	Default: 1000000
++	Range: 3000 - 100000000
++
++### uart1
++
++Activates serial port 1 (/dev/ttyS1)
++
++UART 1 pins (TX, RX, RTS, CTS): PG6, PG7, PG8, PG9
++
++Parameters:
++
++param_uart1_rtscts (bool)
++	Enable RTS and CTS pins
++	Optional
++	Default: 0
++	Set to 1 to enable
++
++### uart2
++
++Activates serial port 2 (/dev/ttyS2)
++
++UART 2 pins (TX, RX, RTS, CTS): PA0, PA1, PA2, PA3
++
++Parameters:
++
++param_uart2_rtscts (bool)
++	Enable RTS and CTS pins
++	Optional
++	Default: 0
++	Set to 1 to enable CTS and RTS pins
++
++### uart3
++
++Activates serial port 3 (/dev/ttyS3)
++
++UART 3 pins (TX, RX, RTS, CTS): PA13, PA14, PA15, PA16
++
++Parameters:
++
++param_uart3_rtscts (bool)
++	Enable RTS and CTS pins
++	Optional
++	Default: 0
++	Set to 1 to enable CTS and RTS pins
++
++### usbhost0
++
++Activates USB host controller 0
++
++### usbhost1
++
++Activates USB host controller 1
++
++### usbhost2
++
++Activates USB host controller 2
++
++### usbhost3
++
++Activates USB host controller 3
++
++### w1-gpio
++
++Activates 1-Wire GPIO master
++Requires an external pull-up resistor on the data pin
++or enabling the internal pull-up
++
++Parameters:
++
++param_w1_pin (pin)
++	Data pin for 1-Wire master
++	Optional
++	Default: PD14
++
++param_w1_pin_int_pullup (bool)
++	Enable internal pull-up for the data pin
++	Optional
++	Default: 0
++	Set to 1 to enable the pull-up
++	This option should not be used with multiple devices, parasite power setup
++		or long wires -	please use external pull-up resistor instead
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-analog-codec.dtso b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-analog-codec.dtso
+new file mode 100644
+index 000000000000..9254e22e0eea
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-analog-codec.dtso
+@@ -0,0 +1,13 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun4i-a10";
++
++	fragment@0 {
++		target = <&codec>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-can.dtso b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-can.dtso
+new file mode 100644
+index 000000000000..1a9511d1956b
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-can.dtso
+@@ -0,0 +1,15 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun4i-a10";
++
++	fragment@0 {
++		target = <&can0>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&can0_ph_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-fixup.scr-cmd b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-fixup.scr-cmd
+new file mode 100644
+index 000000000000..c5614cb95124
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-fixup.scr-cmd
+@@ -0,0 +1,124 @@
++# overlays fixup script
++# implements (or rather substitutes) overlay arguments functionality
++# using u-boot scripting, environment variables and "fdt" command
++
++# setexpr test_var ${tmp_bank} - A
++# works only for hex numbers (A-F)
++
++setenv decompose_pin 'setexpr tmp_bank sub "P(B|C|D|E|G|H|I)\\d+" "\\1";
++setexpr tmp_pin sub "P\\S(\\d+)" "\\1";
++test "${tmp_bank}" = "B" && setenv tmp_bank 1;
++test "${tmp_bank}" = "C" && setenv tmp_bank 2;
++test "${tmp_bank}" = "D" && setenv tmp_bank 3;
++test "${tmp_bank}" = "E" && setenv tmp_bank 4;
++test "${tmp_bank}" = "G" && setenv tmp_bank 6;
++test "${tmp_bank}" = "H" && setenv tmp_bank 7;
++test "${tmp_bank}" = "I" && setenv tmp_bank 8'
++
++if test -n "${param_spinor_spi_bus}"; then
++	test "${param_spinor_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c05000"
++	test "${param_spinor_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c06000"
++	test "${param_spinor_spi_bus}" = "2" && setenv tmp_spi_path "spi@1c17000"
++	fdt set /soc/${tmp_spi_path} status "okay"
++	fdt set /soc/${tmp_spi_path}/spiflash status "okay"
++	if test -n "${param_spinor_max_freq}"; then
++		fdt set /soc/${tmp_spi_path}/spiflash spi-max-frequency "<${param_spinor_max_freq}>"
++	fi
++	env delete tmp_spi_path
++fi
++
++if test -n "${param_spidev_spi_bus}"; then
++	test "${param_spidev_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c05000"
++	test "${param_spidev_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c06000"
++	test "${param_spidev_spi_bus}" = "2" && setenv tmp_spi_path "spi@1c17000"
++	fdt set /soc/${tmp_spi_path} status "okay"
++	fdt set /soc/${tmp_spi_path}/spidev status "okay"
++	if test -n "${param_spidev_max_freq}"; then
++		fdt set /soc/${tmp_spi_path}/spidev spi-max-frequency "<${param_spidev_max_freq}>"
++	fi
++	env delete tmp_spi_path
++fi
++
++if test "${param_spi2_bus_pins}" = "b"; then
++	fdt get value tmp_phandle1 /soc/pinctrl@1c20800/spi2@1 phandle
++	fdt get value tmp_phandle2 /soc/pinctrl@1c20800/spi2_cs0@1 phandle
++	fdt set /soc/spi@1c17000 pinctrl-0 "<${tmp_phandle1}>"
++	fdt set /soc/spi@1c17000 pinctrl-1 "<${tmp_phandle2}>"
++	env delete tmp_phandle1 tmp_phandle2
++fi
++
++if test -n "${param_pps_pin}"; then
++	setenv tmp_bank "${param_pps_pin}"
++	setenv tmp_pin "${param_pps_pin}"
++	run decompose_pin
++	fdt set /soc/pinctrl@1c20800/pps_pins pins "${param_pps_pin}"
++	fdt get value tmp_phandle /soc/pinctrl@1c20800 phandle
++	fdt set /pps@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>"
++	env delete tmp_pin tmp_bank tmp_phandle
++fi
++
++if test "${param_pps_falling_edge}" = "1"; then
++	fdt set /pps@0 assert-falling-edge
++fi
++
++if test "${param_pwm_pins}" = "0"; then
++	fdt get value tmp_phandle /soc/pinctrl@1c20800/pwm0@0
++	fdt set /soc/pwm@1c20e00 pinctrl-0 "<${tmp_phandle}>"
++	env delete tmp_phandle
++fi
++
++if test "${param_pwm_pins}" = "1"; then
++	fdt get value tmp_phandle /soc/pinctrl@1c20800/pwm1@0
++	fdt set /soc/pwm@1c20e00 pinctrl-0 "<${tmp_phandle}>"
++	env delete tmp_phandle
++fi
++
++if test -n "${param_w1_pin}"; then
++	setenv tmp_bank "${param_w1_pin}"
++	setenv tmp_pin "${param_w1_pin}"
++	run decompose_pin
++	fdt set /soc/pinctrl@1c20800/w1_pins pins "${param_w1_pin}"
++	fdt get value tmp_phandle /soc/pinctrl@1c20800 phandle
++	fdt set /onewire@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>"
++	env delete tmp_pin tmp_bank tmp_phandle
++fi
++
++if test "${param_w1_pin_int_pullup}" = "1"; then
++	fdt set /soc/pinctrl@1c20800/w1_pins bias-pull-up
++fi
++
++if test "${param_uart2_rtscts}" = "1"; then
++	fdt get value tmp_phandle /soc/pinctrl@1c20800/uart2@0 phandle
++	fdt set /soc/serial@1c28800 pinctrl-0 "<${tmp_phandle}>"
++	env delete tmp_phandle
++fi
++
++if test "${param_uart3_pins}" = "b"; then
++	if test "${param_uart3_rtscts}" = "1"; then
++		fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart3_pins_b phandle
++		fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart3_pins_b_rts_cts phandle
++		fdt set /soc/serial@1c28c00 pinctrl-names "default" "default"
++		fdt set /soc/serial@1c28c00 pinctrl-0 "<${tmp_phandle1}>"
++		fdt set /soc/serial@1c28c00 pinctrl-1 "<${tmp_phandle2}>"
++		env delete tmp_phandle1 tmp_phandle2
++	else
++		fdt get value tmp_phandle /soc/pinctrl@1c20800/uart3_pins_b phandle
++		fdt set /soc/serial@1c28c00 pinctrl-0 "<${tmp_phandle}>"
++		env delete tmp_phandle
++	fi
++else
++	if test "${param_uart3_rtscts}" = "1"; then
++		fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart3_pins_a phandle
++		fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart3_pins_a_rts_cts phandle
++		fdt set /soc/serial@1c28c00 pinctrl-names "default" "default"
++		fdt set /soc/serial@1c28c00 pinctrl-0 "<${tmp_phandle1}>"
++		fdt set /soc/serial@1c28c00 pinctrl-1 "<${tmp_phandle2}>"
++		env delete tmp_phandle1 tmp_phandle2
++	fi
++fi
++
++if test "${param_uart4_pins}" = "b"; then
++	fdt get value tmp_phandle /soc/pinctrl@1c20800/uart4@1 phandle
++	fdt set /soc/serial@1c29000 pinctrl-0 "<${tmp_phandle}>"
++	env delete tmp_phandle
++fi
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-i2c1.dtso b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-i2c1.dtso
+new file mode 100644
+index 000000000000..4c104bf4a5f0
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-i2c1.dtso
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun4i-a10";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			i2c1 = "/soc@1c00000/i2c@1c2b000";
++		};
++	};
++
++	fragment@1 {
++		target = <&i2c1>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&i2c1_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-i2c2.dtso b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-i2c2.dtso
+new file mode 100644
+index 000000000000..1c2c3e9aca81
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-i2c2.dtso
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun4i-a10";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			i2c2 = "/soc@1c00000/i2c@1c2b400";
++		};
++	};
++
++	fragment@1 {
++		target = <&i2c2>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&i2c2_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-nand.dtso b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-nand.dtso
+new file mode 100644
+index 000000000000..f0d4c2f34859
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-nand.dtso
+@@ -0,0 +1,103 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun4i-a10";
++
++	fragment@0 {
++		target = <&pio>;
++		__overlay__ {
++			nand_pins_a: nand_pins@0 {
++				pins = "PC0", "PC1", "PC2",
++						"PC5", "PC8", "PC9", "PC10",
++						"PC11", "PC12", "PC13", "PC14",
++						"PC15", "PC16";
++				function = "nand0";
++			};
++
++			nand_cs0_pins_a: nand_cs@0 {
++				pins = "PC4";
++				function = "nand0";
++			};
++
++			nand_cs1_pins_a: nand_cs@1 {
++				pins = "PC3";
++				function = "nand0";
++			};
++
++			nand_cs2_pins_a: nand_cs@2 {
++				pins = "PC17";
++				function = "nand0";
++			};
++
++			nand_cs3_pins_a: nand_cs@3 {
++				pins = "PC18";
++				function = "nand0";
++			};
++
++			nand_rb0_pins_a: nand_rb@0 {
++				pins = "PC6";
++				function = "nand0";
++			};
++
++			nand_rb1_pins_a: nand_rb@1 {
++				pins = "PC7";
++				function = "nand0";
++			};
++		};
++	};
++
++	fragment@1 {
++		target = <&nfc>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			pinctrl-names = "default";
++			pinctrl-0 = <&nand_pins_a>, <&nand_cs0_pins_a>, <&nand_rb0_pins_a>;
++			status = "okay";
++
++			nand@0 {
++				reg = <0>;
++				allwinner,rb = <0>;
++				nand-ecc-mode = "hw";
++				nand-on-flash-bbt;
++
++				partitions {
++					compatible = "fixed-partitions";
++					#address-cells = <2>;
++					#size-cells = <2>;
++
++					partition@0 {
++						label = "SPL";
++						reg = <0x0 0x0 0x0 0x400000>;
++					};
++
++					partition@400000 {
++						label = "SPL.backup";
++						reg = <0x0 0x400000 0x0 0x400000>;
++					};
++
++					partition@800000 {
++						label = "U-Boot";
++						reg = <0x0 0x800000 0x0 0x400000>;
++					};
++
++					partition@c00000 {
++						label = "U-Boot.backup";
++						reg = <0x0 0xc00000 0x0 0x400000>;
++					};
++
++					partition@1000000 {
++						label = "env";
++						reg = <0x0 0x1000000 0x0 0x400000>;
++					};
++
++					partition@1400000 {
++						label = "rootfs";
++						reg = <0x0 0xa00000 0x01 0xff000000>;
++					};
++				};
++			};
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-pps-gpio.dtso b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-pps-gpio.dtso
+new file mode 100644
+index 000000000000..6031fc53e548
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-pps-gpio.dtso
+@@ -0,0 +1,29 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun4i-a10";
++
++	fragment@0 {
++		target = <&pio>;
++		__overlay__ {
++			pps_pins: pps_pins {
++				pins = "PI15";
++				function = "gpio_in";
++			};
++		};
++	};
++
++	fragment@1 {
++		target-path = "/";
++		__overlay__ {
++			pps@0 {
++				compatible = "pps-gpio";
++				pinctrl-names = "default";
++				pinctrl-0 = <&pps_pins>;
++				gpios = <&pio 8 15 0>;  /* PI15 */
++				status = "okay";
++			};
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-pwm.dtso b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-pwm.dtso
+new file mode 100644
+index 000000000000..ba885004fe4f
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-pwm.dtso
+@@ -0,0 +1,15 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun4i-a10";
++
++	fragment@0 {
++		target = <&pwm>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&pwm0_pin>, <&pwm1_pin>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-spdif-out.dtso b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-spdif-out.dtso
+new file mode 100644
+index 000000000000..234dfc880f1f
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-spdif-out.dtso
+@@ -0,0 +1,38 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun4i-a10";
++
++	fragment@0 {
++		target = <&spdif>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&spdif_tx_pin>;
++			status = "okay";
++		};
++	};
++
++	fragment@1 {
++		target-path = "/";
++		__overlay__ {
++			sound {
++				compatible = "simple-audio-card";
++				simple-audio-card,name = "On-board SPDIF";
++
++				simple-audio-card,cpu {
++					sound-dai = <&spdif>;
++				};
++
++				simple-audio-card,codec {
++					sound-dai = <&spdif_out>;
++				};
++			};
++
++			spdif_out: spdif-out {
++				#sound-dai-cells = <0>;
++				compatible = "linux,spdif-dit";
++			};
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-spi-jedec-nor.dtso b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-spi-jedec-nor.dtso
+new file mode 100644
+index 000000000000..ee4ff6f453d1
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-spi-jedec-nor.dtso
+@@ -0,0 +1,57 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun4i-a10";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi0 = "/soc@1c00000/spi@1c05000";
++			spi1 = "/soc@1c00000/spi@1c06000";
++			spi2 = "/soc@1c00000/spi@1c17000";
++		};
++	};
++
++	fragment@1 {
++		target = <&spi0>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spiflash@0 {
++				compatible = "jedec,spi-nor";
++				status = "disabled";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&spi1>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spiflash@0 {
++				compatible = "jedec,spi-nor";
++				status = "disabled";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++
++	fragment@3 {
++		target = <&spi2>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spiflash@0 {
++				compatible = "jedec,spi-nor";
++				status = "disabled";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-spi-spidev.dtso b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-spi-spidev.dtso
+new file mode 100644
+index 000000000000..eac4f1e2d244
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-spi-spidev.dtso
+@@ -0,0 +1,57 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun4i-a10";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi0 = "/soc@1c00000/spi@1c05000";
++			spi1 = "/soc@1c00000/spi@1c06000";
++			spi2 = "/soc@1c00000/spi@1c17000";
++		};
++	};
++
++	fragment@1 {
++		target = <&spi0>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spidev@0 {
++				compatible = "armbian,spi-dev";
++				status = "disabled";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&spi1>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spidev@0 {
++				compatible = "armbian,spi-dev";
++				status = "disabled";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++
++	fragment@3 {
++		target = <&spi2>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spidev@0 {
++				compatible = "armbian,spi-dev";
++				status = "disabled";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-spi0.dtso b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-spi0.dtso
+new file mode 100644
+index 000000000000..cad50d8a29a7
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-spi0.dtso
+@@ -0,0 +1,23 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun7i-a20";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi0 = "/soc@1c00000/spi@1c05000";
++		};
++	};
++
++	fragment@1 {
++		target = <&spi0>;
++		__overlay__ {
++			status = "okay";
++			pinctrl-names = "default", "default";
++			pinctrl-0 = <&spi0_pi_pins>;
++			pinctrl-1 = <&spi0_cs0_pi_pin>;
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-spi1.dtso b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-spi1.dtso
+new file mode 100644
+index 000000000000..8c606d6b06a1
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-spi1.dtso
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun7i-a20";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi1 = "/soc@1c00000/spi@1c06000";
++		};
++	};
++
++	fragment@1 {
++		target = <&spi1>;
++		__overlay__ {
++			status = "okay";
++			pinctrl-names = "default";
++			pinctrl-0 = <&spi1_pins>, <&spi1_cs0_pin>;
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-spi2.dtso b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-spi2.dtso
+new file mode 100644
+index 000000000000..145f285588f8
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-spi2.dtso
+@@ -0,0 +1,23 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun7i-a20";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi2 = "/soc@1c00000/spi@1c17000";
++		};
++	};
++
++	fragment@1 {
++		target = <&spi2>;
++		__overlay__ {
++			status = "okay";
++			pinctrl-names = "default", "default";
++			pinctrl-0 = <&spi2_pins_a>;
++			pinctrl-1 = <&spi2_cs0_pins_a>;
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-uart2.dtso b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-uart2.dtso
+new file mode 100644
+index 000000000000..89bb44d5aee0
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-uart2.dtso
+@@ -0,0 +1,37 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun4i-a10";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			serial2 = "/soc@1c00000/serial@1c28800";
++		};
++	};
++
++	fragment@1 {
++		target = <&pio>;
++		__overlay__ {
++			uart2_pins_a: uart2@0 {
++				pins = "PI16", "PI17", "PI18", "PI19";
++				function = "uart2";
++			};
++
++			uart2_pins_a_2: uart2@1 {
++				pins = "PI18", "PI19";
++				function = "uart2";
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&uart2>;
++		 __overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart2_pins_a_2>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-uart3.dtso b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-uart3.dtso
+new file mode 100644
+index 000000000000..f599d92082e4
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-uart3.dtso
+@@ -0,0 +1,47 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun4i-a10";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			serial3 = "/soc@1c00000/serial@1c28c00";
++		};
++	};
++
++	fragment@1 {
++		target = <&pio>;
++		__overlay__ {
++			uart3_pins_a: uart3@0 {
++				pins = "PG6", "PG7";
++				function = "uart3";
++			};
++
++			uart3_pins_a_rts_cts: uart3@1 {
++				pins = "PG8", "PG9";
++				function = "uart3";
++			};
++
++			uart3_pins_b: uart3@2 {
++				pins = "PH0", "PH1";
++				function = "uart3";
++			};
++
++			uart3_pins_b_rts_cts: uart3@3 {
++				pins = "PH2", "PH3";
++				function = "uart3";
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&uart3>;
++		 __overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart3_pins_a>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-uart4.dtso b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-uart4.dtso
+new file mode 100644
+index 000000000000..b5e562a6477b
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-uart4.dtso
+@@ -0,0 +1,37 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun4i-a10";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			serial4 = "/soc@1c00000/serial@1c29000";
++		};
++	};
++
++	fragment@1 {
++		target = <&pio>;
++		__overlay__ {
++			uart4_pins_a: uart4@0 {
++				pins = "PG10", "PG11";
++				function = "uart4";
++			};
++
++			uart4_pins_b: uart4@1 {
++				pins = "PH4", "PH5";
++				function = "uart4";
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&uart4>;
++		 __overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart4_pins_a>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-uart5.dtso b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-uart5.dtso
+new file mode 100644
+index 000000000000..12c3f9699b23
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-uart5.dtso
+@@ -0,0 +1,32 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun4i-a10";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			serial5 = "/soc@1c00000/serial@1c29400";
++		};
++	};
++
++	fragment@1 {
++		target = <&pio>;
++		__overlay__ {
++			uart5_pins_a: uart5@0 {
++				pins = "PH6", "PH7";
++				function = "uart5";
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&uart5>;
++		 __overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart5_pins_a>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-uart6.dtso b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-uart6.dtso
+new file mode 100644
+index 000000000000..6be41d505509
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-uart6.dtso
+@@ -0,0 +1,32 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun4i-a10";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			serial6 = "/soc@1c00000/serial@1c29800";
++		};
++	};
++
++	fragment@1 {
++		target = <&pio>;
++		__overlay__ {
++			uart6_pins_a: uart6@0 {
++				pins = "PI12", "PI13";
++				function = "uart6";
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&uart6>;
++		 __overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart6_pins_a>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-uart7.dtso b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-uart7.dtso
+new file mode 100644
+index 000000000000..967f6afbe7d3
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-uart7.dtso
+@@ -0,0 +1,32 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun4i-a10";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			serial7 = "/soc@1c00000/serial@1c29c00";
++		};
++	};
++
++	fragment@1 {
++		target = <&pio>;
++		__overlay__ {
++			uart7_pins_a: uart7@0 {
++				pins = "PI20", "PI21";
++				function = "uart7";
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&uart7>;
++		 __overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart7_pins_a>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-w1-gpio.dtso b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-w1-gpio.dtso
+new file mode 100644
+index 000000000000..41da08c60aa7
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun4i-a10-w1-gpio.dtso
+@@ -0,0 +1,29 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun4i-a10";
++
++	fragment@0 {
++		target = <&pio>;
++		__overlay__ {
++			w1_pins: w1_pins {
++				pins = "PI15";
++				function = "gpio_in";
++			};
++		};
++	};
++
++	fragment@1 {
++		target-path = "/";
++		__overlay__ {
++			onewire@0 {
++				compatible = "w1-gpio";
++				pinctrl-names = "default";
++				pinctrl-0 = <&w1_pins>;
++				gpios = <&pio 8 15 0>; /* PI15 */
++				status = "okay";
++			};
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-analog-codec.dtso b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-analog-codec.dtso
+new file mode 100644
+index 000000000000..60e2717fc582
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-analog-codec.dtso
+@@ -0,0 +1,13 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun4i-a13";
++
++	fragment@0 {
++		target = <&codec>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-fixup.scr-cmd b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-fixup.scr-cmd
+new file mode 100644
+index 000000000000..c82590c1ac18
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-fixup.scr-cmd
+@@ -0,0 +1,48 @@
++# overlays fixup script
++# implements (or rather substitutes) overlay arguments functionality
++# using u-boot scripting, environment variables and "fdt" command
++
++if test -n "${param_spinor_spi_bus}"; then
++	test "${param_spinor_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c05000"
++	test "${param_spinor_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c06000"
++	test "${param_spinor_spi_bus}" = "2" && setenv tmp_spi_path "spi@1c17000"
++	fdt set /soc/${tmp_spi_path} status "okay"
++	fdt set /soc/${tmp_spi_path}/spiflash status "okay"
++	if test -n "${param_spinor_max_freq}"; then
++		fdt set /soc/${tmp_spi_path}/spiflash spi-max-frequency "<${param_spinor_max_freq}>"
++	fi
++	env delete tmp_spi_path
++fi
++
++if test -n "${param_spidev_spi_bus}"; then
++	test "${param_spidev_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c05000"
++	test "${param_spidev_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c06000"
++	test "${param_spidev_spi_bus}" = "2" && setenv tmp_spi_path "spi@1c17000"
++	fdt set /soc/${tmp_spi_path} status "okay"
++	fdt set /soc/${tmp_spi_path}/spidev status "okay"
++	if test -n "${param_spidev_max_freq}"; then
++		fdt set /soc/${tmp_spi_path}/spidev spi-max-frequency "<${param_spidev_max_freq}>"
++	fi
++	env delete tmp_spi_path
++fi
++
++if test "${param_uart1_pins}" = "b"; then
++	fdt get value tmp_phandle /soc/pinctrl@1c28400/uart1@1 phandle
++	fdt set /soc/serial@1c28400 pinctrl-0 "<${tmp_phandle}>"
++	env delete tmp_phandle
++fi
++
++if test "${param_uart2_rtscts}" = "1"; then
++	fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart2@0 phandle
++	fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart2-cts-rts@0 phandle
++	fdt set /soc/serial@1c28800 pinctrl-0 "<${tmp_phandle1}>, <${tmp_phandle2}>"
++	env delete tmp_phandle1 tmp_phandle2
++fi
++
++if test "${param_uart3_rtscts}" = "1"; then
++	fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart3@0 phandle
++	fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart3-cts-rts@0 phandle
++	fdt set /soc/serial@1c28c00 pinctrl-names "default" "default"
++	fdt set /soc/serial@1c28c00 pinctrl-0 "<${tmp_phandle1}>, <${tmp_phandle2}>"
++	env delete tmp_phandle1 tmp_phandle2
++fi
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-i2c1.dtso b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-i2c1.dtso
+new file mode 100644
+index 000000000000..444c32ca01d5
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-i2c1.dtso
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun5i-a13";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			i2c1 = "/soc@1c00000/i2c@1c2b000";
++		};
++	};
++
++	fragment@1 {
++		target = <&i2c1>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&i2c1_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-i2c2.dtso b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-i2c2.dtso
+new file mode 100644
+index 000000000000..7a30681ca287
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-i2c2.dtso
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun5i-a13";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			i2c2 = "/soc@1c00000/i2c@1c2b400";
++		};
++	};
++
++	fragment@1 {
++		target = <&i2c2>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&i2c2_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-nand.dtso b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-nand.dtso
+new file mode 100644
+index 000000000000..0c5fc89a1058
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-nand.dtso
+@@ -0,0 +1,60 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun5i-a13";
++
++	fragment@0 {
++		target = <&nfc>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			pinctrl-names = "default";
++			pinctrl-0 = <&nand_pins>, <&nand_cs0_pin>, <&nand_rb0_pin>;
++			status = "okay";
++
++			nand@0 {
++				reg = <0>;
++				allwinner,rb = <0>;
++				nand-ecc-mode = "hw";
++				nand-on-flash-bbt;
++
++				partitions {
++					compatible = "fixed-partitions";
++					#address-cells = <2>;
++					#size-cells = <2>;
++
++					partition@0 {
++						label = "SPL";
++						reg = <0x0 0x0 0x0 0x400000>;
++					};
++
++					partition@400000 {
++						label = "SPL.backup";
++						reg = <0x0 0x400000 0x0 0x400000>;
++					};
++
++					partition@800000 {
++						label = "U-Boot";
++						reg = <0x0 0x800000 0x0 0x400000>;
++					};
++
++					partition@c00000 {
++						label = "U-Boot.backup";
++						reg = <0x0 0xc00000 0x0 0x400000>;
++					};
++
++					partition@1000000 {
++						label = "env";
++						reg = <0x0 0x1000000 0x0 0x400000>;
++					};
++
++					partition@1400000 {
++						label = "rootfs";
++						reg = <0x0 0xa00000 0x01 0xff000000>;
++					};
++				};
++			};
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-pwm.dtso b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-pwm.dtso
+new file mode 100644
+index 000000000000..54f5d5123eb1
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-pwm.dtso
+@@ -0,0 +1,15 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun5i-a13";
++
++	fragment@0 {
++		target = <&pwm>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&pwm0_pin>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-spi-jedec-nor.dtso b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-spi-jedec-nor.dtso
+new file mode 100644
+index 000000000000..8cebb0b988de
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-spi-jedec-nor.dtso
+@@ -0,0 +1,57 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun5i-a13";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi0 = "/soc/spi@1c05000";
++			spi1 = "/soc/spi@1c06000";
++			spi2 = "/soc/spi@1c17000";
++		};
++	};
++
++	fragment@1 {
++		target = <&spi0>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spiflash@0 {
++				compatible = "jedec,spi-nor";
++				status = "disabled";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&spi1>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spiflash@0 {
++				compatible = "jedec,spi-nor";
++				status = "disabled";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++
++	fragment@3 {
++		target = <&spi2>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spiflash@0 {
++				compatible = "jedec,spi-nor";
++				status = "disabled";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-spi-spidev.dtso b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-spi-spidev.dtso
+new file mode 100644
+index 000000000000..ad0685f8af18
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-spi-spidev.dtso
+@@ -0,0 +1,57 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun5i-a10";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi0 = "/soc/spi@1c05000";
++			spi1 = "/soc/spi@1c06000";
++			spi2 = "/soc/spi@1c17000";
++		};
++	};
++
++	fragment@1 {
++		target = <&spi0>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spidev@0 {
++				compatible = "armbian,spi-dev";
++				status = "disabled";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&spi1>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spidev@0 {
++				compatible = "armbian,spi-dev";
++				status = "disabled";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++
++	fragment@3 {
++		target = <&spi2>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spidev@0 {
++				compatible = "armbian,spi-dev";
++				status = "disabled";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-spi0.dtso b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-spi0.dtso
+new file mode 100644
+index 000000000000..b23a754c0006
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-spi0.dtso
+@@ -0,0 +1,38 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun5i-a13";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi0 = "/soc/spi@1c05000";
++		};
++	};
++
++	fragment@1 {
++		target = <&pio>;
++		__overlay__ {
++			spi0_pins_a: spi0@0 {
++				pins = "PC0", "PC1", "PC2";
++				function = "spi0";
++			};
++
++			spi0_cs0_pins_a: spi0-cs0@0 {
++				pins = "PC3";
++				function = "spi0";
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&spi0>;
++		__overlay__ {
++				status = "okay";
++				pinctrl-names = "default", "default";
++				pinctrl-0 = <&spi0_pins_a>;
++				pinctrl-1 = <&spi0_cs0_pins_a>;
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-spi1.dtso b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-spi1.dtso
+new file mode 100644
+index 000000000000..cc0af5db3fd0
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-spi1.dtso
+@@ -0,0 +1,39 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun5i-a13";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi1 = "/soc/spi@1c06000";
++		};
++	};
++
++	fragment@1 {
++		target = <&pio>;
++		__overlay__ {
++			spi1_pins_a: spi1@0 {
++				pins = "PG10", "PG11", "PG12";
++				function = "spi1";
++			};
++
++			spi1_cs0_pins_a: spi1-cs0@0 {
++				pins = "PG9";
++				function = "spi1";
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&spi1>;
++		__overlay__ {
++			status = "okay";
++			pinctrl-names = "default";
++			pinctrl-0 = <&spi1_pins_a>, <&spi1_cs0_pins_a>;
++		};
++	};
++
++
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-spi2.dtso b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-spi2.dtso
+new file mode 100644
+index 000000000000..6cf5c41a9eca
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-spi2.dtso
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun5i-a13";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi2 = "/soc/spi@1c17000";
++		};
++	};
++
++	fragment@1 {
++		target = <&spi2>;
++		__overlay__ {
++			status = "okay";
++			pinctrl-names = "default";
++			pinctrl-0 = <&spi2_pe_pins>, <&spi2_cs0_pe_pin>;
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-uart0.dtso b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-uart0.dtso
+new file mode 100644
+index 000000000000..6edad42bfcd7
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-uart0.dtso
+@@ -0,0 +1,32 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun5i-a13";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			uart0 = "/soc@1c00000/serial@1c28000";
++		};
++	};
++
++	fragment@1 {
++		target = <&pio>;
++		__overlay__ {
++			uart0_pa_pins: uart0@0 {
++				pins = "PF2", "PF4";
++				function = "uart0";
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&uart0>;
++		 __overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart0_pa_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-uart1.dtso b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-uart1.dtso
+new file mode 100644
+index 000000000000..675b701ed535
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-uart1.dtso
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun5i-a13";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			uart1 = "/soc@1c00000/serial@1c28400";
++		};
++	};
++
++	fragment@1 {
++		target = <&uart1>;
++		 __overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart1_pe_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-uart2.dtso b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-uart2.dtso
+new file mode 100644
+index 000000000000..b3c4e3d7a0e2
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-uart2.dtso
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun5i-a13";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			uart2 = "/soc@1c00000/serial@1c28800";
++		};
++	};
++
++	fragment@1 {
++		target = <&uart2>;
++		 __overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart2_pd_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-uart3.dtso b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-uart3.dtso
+new file mode 100644
+index 000000000000..15c25d0c5992
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun5i-a13-uart3.dtso
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun5i-a13";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			uart3 = "/soc@1c00000/serial@1c28c00";
++		};
++	};
++
++	fragment@1 {
++		target = <&uart3>;
++		 __overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart3_pg_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-analog-codec.dtso b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-analog-codec.dtso
+new file mode 100644
+index 000000000000..e1a70c5102bc
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-analog-codec.dtso
+@@ -0,0 +1,13 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun7i-a20";
++
++	fragment@0 {
++		target = <&codec>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-can.dtso b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-can.dtso
+new file mode 100644
+index 000000000000..65aebcd4144c
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-can.dtso
+@@ -0,0 +1,15 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun7i-a20";
++
++	fragment@0 {
++		target = <&can0>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&can0_pins_a>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-fixup.scr-cmd b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-fixup.scr-cmd
+new file mode 100644
+index 000000000000..b97042a720a7
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-fixup.scr-cmd
+@@ -0,0 +1,143 @@
++# overlays fixup script
++# implements (or rather substitutes) overlay arguments functionality
++# using u-boot scripting, environment variables and "fdt" command
++
++# setexpr test_var ${tmp_bank} - A
++# works only for hex numbers (A-F)
++
++setenv decompose_pin 'setexpr tmp_bank sub "P(B|C|D|E|G|H|I)\\d+" "\\1";
++setexpr tmp_pin sub "P\\S(\\d+)" "\\1";
++test "${tmp_bank}" = "B" && setenv tmp_bank 1;
++test "${tmp_bank}" = "C" && setenv tmp_bank 2;
++test "${tmp_bank}" = "D" && setenv tmp_bank 3;
++test "${tmp_bank}" = "E" && setenv tmp_bank 4;
++test "${tmp_bank}" = "G" && setenv tmp_bank 6;
++test "${tmp_bank}" = "H" && setenv tmp_bank 7;
++test "${tmp_bank}" = "I" && setenv tmp_bank 8'
++
++if test -n "${param_spinor_spi_bus}"; then
++	test "${param_spinor_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c05000"
++	test "${param_spinor_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c06000"
++	test "${param_spinor_spi_bus}" = "2" && setenv tmp_spi_path "spi@1c17000"
++	fdt set /soc/${tmp_spi_path} status "okay"
++	fdt set /soc/${tmp_spi_path}/spiflash status "okay"
++	if test -n "${param_spinor_max_freq}"; then
++		fdt set /soc/${tmp_spi_path}/spiflash spi-max-frequency "<${param_spinor_max_freq}>"
++	fi
++	if test "${param_spinor_spi_bus}" = "0" && test "${param_spinor_spi_cs}" = "1"; then
++		fdt set /soc/${tmp_spi_path}/spiflash reg "<1>"
++	fi
++	env delete tmp_spi_path
++fi
++
++if test -n "${param_spidev_spi_bus}"; then
++	test "${param_spidev_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c05000"
++	test "${param_spidev_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c06000"
++	test "${param_spidev_spi_bus}" = "2" && setenv tmp_spi_path "spi@1c17000"
++	fdt set /soc/${tmp_spi_path} status "okay"
++	fdt set /soc/${tmp_spi_path}/spidev status "okay"
++	if test -n "${param_spidev_max_freq}"; then
++		fdt set /soc/${tmp_spi_path}/spidev spi-max-frequency "<${param_spidev_max_freq}>"
++	fi
++	if test "${param_spidev_spi_bus}" = "0" && test "${param_spidev_spi_cs}" = "1"; then
++		fdt set /soc/${tmp_spi_path}/spidev reg "<1>"
++	fi
++	env delete tmp_spi_path
++fi
++
++if test "${param_spi2_bus_pins}" = "b"; then
++	fdt get value tmp_phandle1 /soc/pinctrl@1c20800/spi2@1 phandle
++	fdt get value tmp_phandle2 /soc/pinctrl@1c20800/spi2_cs0@1 phandle
++	fdt set /soc/spi@1c17000 pinctrl-0 "<${tmp_phandle1}>"
++	fdt set /soc/spi@1c17000 pinctrl-1 "<${tmp_phandle2}>"
++	env delete tmp_phandle1 tmp_phandle2
++fi
++
++if test -n "${param_pps_pin}"; then
++	setenv tmp_bank "${param_pps_pin}"
++	setenv tmp_pin "${param_pps_pin}"
++	run decompose_pin
++	fdt set /soc/pinctrl@1c20800/pps_pins pins "${param_pps_pin}"
++	fdt get value tmp_phandle /soc/pinctrl@1c20800 phandle
++	fdt set /pps@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>"
++	env delete tmp_pin tmp_bank tmp_phandle
++fi
++
++if test "${param_pps_falling_edge}" = "1"; then
++	fdt set /pps@0 assert-falling-edge
++fi
++
++if test "${param_pwm_pins}" = "0"; then
++	fdt get value tmp_phandle /soc/pinctrl@1c20800/pwm0@0
++	fdt set /soc/pwm@1c20e00 pinctrl-0 "<${tmp_phandle}>"
++	env delete tmp_phandle
++fi
++
++if test "${param_pwm_pins}" = "1"; then
++	fdt get value tmp_phandle /soc/pinctrl@1c20800/pwm1@0
++	fdt set /soc/pwm@1c20e00 pinctrl-0 "<${tmp_phandle}>"
++	env delete tmp_phandle
++fi
++
++if test -n "${param_w1_pin}"; then
++	setenv tmp_bank "${param_w1_pin}"
++	setenv tmp_pin "${param_w1_pin}"
++	run decompose_pin
++	fdt set /soc/pinctrl@1c20800/w1_pins pins "${param_w1_pin}"
++	fdt get value tmp_phandle /soc/pinctrl@1c20800 phandle
++	fdt set /onewire@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>"
++	env delete tmp_pin tmp_bank tmp_phandle
++fi
++
++if test -n "${param_mmc2_cd_pin}"; then
++	setenv tmp_bank "${param_mmc2_cd_pin}"
++	setenv tmp_pin "${param_mmc2_cd_pin}"
++	run decompose_pin
++	fdt get value tmp_phandle /soc/pinctrl@1c20800 phandle
++	fdt set /soc/mmc@1c11000 cd-gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 1>"
++fi
++
++if test "${param_mmc2_non_removable}" = "1"; then
++	fdt rm /soc/mmc@1c11000 cd-gpios
++	fdt set /soc/mmc@1c11000 non-removable
++fi
++
++if test "${param_w1_pin_int_pullup}" = "1"; then
++	fdt set /soc/pinctrl@1c20800/w1_pins bias-pull-up
++fi
++
++if test "${param_uart2_rtscts}" = "1"; then
++	fdt get value tmp_phandle /soc/pinctrl@1c20800/uart2-pi-pins phandle
++	fdt set /soc/serial@1c28800 pinctrl-0 "<${tmp_phandle}>"
++	env delete tmp_phandle
++fi
++
++if test "${param_uart3_pins}" = "b"; then
++	if test "${param_uart3_rtscts}" = "1"; then
++		fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart3-ph-pins phandle
++		fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart3-cts-rts-ph-pins phandle
++		fdt set /soc/serial@1c28c00 pinctrl-names "default" "default"
++		fdt set /soc/serial@1c28c00 pinctrl-0 "<${tmp_phandle1}>"
++		fdt set /soc/serial@1c28c00 pinctrl-1 "<${tmp_phandle2}>"
++		env delete tmp_phandle1 tmp_phandle2
++	else
++		fdt get value tmp_phandle /soc/pinctrl@1c20800/uart3-ph-pins phandle
++		fdt set /soc/serial@1c28c00 pinctrl-0 "<${tmp_phandle}>"
++		env delete tmp_phandle
++	fi
++else
++	if test "${param_uart3_rtscts}" = "1"; then
++		fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart3-pg-pins phandle
++		fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart3-cts-rts-pg-pins phandle
++		fdt set /soc/serial@1c28c00 pinctrl-names "default" "default"
++		fdt set /soc/serial@1c28c00 pinctrl-0 "<${tmp_phandle1}>"
++		fdt set /soc/serial@1c28c00 pinctrl-1 "<${tmp_phandle2}>"
++		env delete tmp_phandle1 tmp_phandle2
++	fi
++fi
++
++if test "${param_uart4_pins}" = "b"; then
++	fdt get value tmp_phandle /soc/pinctrl@1c20800/uart4-pg-pins phandle
++	fdt set /soc/serial@1c29000 pinctrl-0 "<${tmp_phandle}>"
++	env delete tmp_phandle
++fi
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-i2c1.dtso b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-i2c1.dtso
+new file mode 100644
+index 000000000000..c5f6e9732d3a
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-i2c1.dtso
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun7i-a20";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			i2c1 = "/soc@1c00000/i2c@1c2b000";
++		};
++	};
++
++	fragment@1 {
++		target = <&i2c1>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&i2c1_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-i2c2.dtso b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-i2c2.dtso
+new file mode 100644
+index 000000000000..fa93d1ed9b72
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-i2c2.dtso
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun7i-a20";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			i2c2 = "/soc@1c00000/i2c@1c2b400";
++		};
++	};
++
++	fragment@1 {
++		target = <&i2c2>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&i2c2_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-i2c3.dtso b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-i2c3.dtso
+new file mode 100644
+index 000000000000..945795c338e8
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-i2c3.dtso
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun7i-a20";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			i2c3 = "/soc@1c00000/i2c@1c2b800";
++		};
++	};
++
++	fragment@1 {
++		target = <&i2c3>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&i2c3_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-i2c4.dtso b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-i2c4.dtso
+new file mode 100644
+index 000000000000..4fcf08c2469b
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-i2c4.dtso
+@@ -0,0 +1,32 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun7i-a20";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			i2c4 = "/soc@1c00000/i2c@1c2c000";
++		};
++	};
++
++	fragment@1 {
++		target = <&pio>;
++		__overlay__ {
++			i2c4_pins_a: i2c4@0 {
++				pins = "PI2", "PI3";
++				function = "i2c4";
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&i2c4>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&i2c4_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-i2s0.dtso b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-i2s0.dtso
+new file mode 100644
+index 000000000000..1a19a2417d3b
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-i2s0.dtso
+@@ -0,0 +1,25 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun7i-a20";
++
++	fragment@0 {
++		target = <&pio>;
++		__overlay__ {
++			i2s0_pins: i2s0 {
++				pins = "PB5", "PB6", "PB7", "PB8", "PB9", "PB10", "PB11", "PB12";
++				function = "i2s0";
++			};
++		};
++	};
++
++	fragment@1 {
++		target = <&i2s0>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&i2s0_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-i2s1.dtso b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-i2s1.dtso
+new file mode 100644
+index 000000000000..e6f0a22b7991
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-i2s1.dtso
+@@ -0,0 +1,25 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun7i-a20";
++
++	fragment@0 {
++		target = <&pio>;
++		__overlay__ {
++			i2s1_pins: i2s1 {
++				pins = "PA9", "PA14", "PA15", "PA16", "PA17";
++				function = "i2s1";
++			};
++		};
++	};
++
++	fragment@1 {
++		target = <&i2s1>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&i2s1_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-mmc2.dtso b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-mmc2.dtso
+new file mode 100644
+index 000000000000..ede92f243a1d
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-mmc2.dtso
+@@ -0,0 +1,18 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun7i-a20";
++
++	fragment@0 {
++		target = <&mmc2>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&mmc2_pins>;
++			vmmc-supply = <&reg_vcc3v3>;
++			bus-width = <4>;
++			cd-gpios = <&pio 7 0 1>; /* PH0, active low */
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-nand.dtso b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-nand.dtso
+new file mode 100644
+index 000000000000..ffa49cc69473
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-nand.dtso
+@@ -0,0 +1,103 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun7i-a20";
++
++	fragment@0 {
++		target = <&pio>;
++		__overlay__ {
++			nand_pins_a: nand_pins@0 {
++				pins = "PC0", "PC1", "PC2",
++						"PC5", "PC8", "PC9", "PC10",
++						"PC11", "PC12", "PC13", "PC14",
++						"PC15", "PC16";
++				function = "nand0";
++			};
++
++			nand_cs0_pins_a: nand_cs@0 {
++				pins = "PC4";
++				function = "nand0";
++			};
++
++			nand_cs1_pins_a: nand_cs@1 {
++				pins = "PC3";
++				function = "nand0";
++			};
++
++			nand_cs2_pins_a: nand_cs@2 {
++				pins = "PC17";
++				function = "nand0";
++			};
++
++			nand_cs3_pins_a: nand_cs@3 {
++				pins = "PC18";
++				function = "nand0";
++			};
++
++			nand_rb0_pins_a: nand_rb@0 {
++				pins = "PC6";
++				function = "nand0";
++			};
++
++			nand_rb1_pins_a: nand_rb@1 {
++				pins = "PC7";
++				function = "nand0";
++			};
++		};
++	};
++
++	fragment@1 {
++		target = <&nfc>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			pinctrl-names = "default";
++			pinctrl-0 = <&nand_pins_a>, <&nand_cs0_pins_a>, <&nand_rb0_pins_a>;
++			status = "okay";
++
++			nand@0 {
++				reg = <0>;
++				allwinner,rb = <0>;
++				nand-ecc-mode = "hw";
++				nand-on-flash-bbt;
++
++				partitions {
++					compatible = "fixed-partitions";
++					#address-cells = <2>;
++					#size-cells = <2>;
++
++					partition@0 {
++						label = "SPL";
++						reg = <0x0 0x0 0x0 0x400000>;
++					};
++
++					partition@400000 {
++						label = "SPL.backup";
++						reg = <0x0 0x400000 0x0 0x400000>;
++					};
++
++					partition@800000 {
++						label = "U-Boot";
++						reg = <0x0 0x800000 0x0 0x400000>;
++					};
++
++					partition@c00000 {
++						label = "U-Boot.backup";
++						reg = <0x0 0xc00000 0x0 0x400000>;
++					};
++
++					partition@1000000 {
++						label = "env";
++						reg = <0x0 0x1000000 0x0 0x400000>;
++					};
++
++					partition@1400000 {
++						label = "rootfs";
++						reg = <0x0 0xa00000 0x01 0xff000000>;
++					};
++				};
++			};
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-pps-gpio.dtso b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-pps-gpio.dtso
+new file mode 100644
+index 000000000000..fe3e2bd96467
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-pps-gpio.dtso
+@@ -0,0 +1,29 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun7i-a20";
++
++	fragment@0 {
++		target = <&pio>;
++		__overlay__ {
++			pps_pins: pps_pins {
++				pins = "PI15";
++				function = "gpio_in";
++			};
++		};
++	};
++
++	fragment@1 {
++		target-path = "/";
++		__overlay__ {
++			pps@0 {
++				compatible = "pps-gpio";
++				pinctrl-names = "default";
++				pinctrl-0 = <&pps_pins>;
++				gpios = <&pio 8 15 0>;  /* PI15 */
++				status = "okay";
++			};
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-pwm.dtso b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-pwm.dtso
+new file mode 100644
+index 000000000000..b0cfe4deae76
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-pwm.dtso
+@@ -0,0 +1,15 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun7i-a20";
++
++	fragment@0 {
++		target = <&pwm>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&pwm0_pin>, <&pwm1_pin>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-spdif-out.dtso b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-spdif-out.dtso
+new file mode 100644
+index 000000000000..11a09396bd35
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-spdif-out.dtso
+@@ -0,0 +1,38 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun7i-a20";
++
++	fragment@0 {
++		target = <&spdif>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&spdif_tx_pin>;
++			status = "okay";
++		};
++	};
++
++	fragment@1 {
++		target-path = "/";
++		__overlay__ {
++			sound {
++				compatible = "simple-audio-card";
++				simple-audio-card,name = "On-board SPDIF";
++
++				simple-audio-card,cpu {
++					sound-dai = <&spdif>;
++				};
++
++				simple-audio-card,codec {
++					sound-dai = <&spdif_out>;
++				};
++			};
++
++			spdif_out: spdif-out {
++				#sound-dai-cells = <0>;
++				compatible = "linux,spdif-dit";
++			};
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-spi-add-cs1.dtso b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-spi-add-cs1.dtso
+new file mode 100644
+index 000000000000..c0a4ba2b3d4e
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-spi-add-cs1.dtso
+@@ -0,0 +1,16 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun7i-a20";
++
++	fragment@0 {
++		target = <&spi0>;
++		__overlay__ {
++			pinctrl-names = "default", "default", "default";
++			pinctrl-0 = <&spi0_pi_pins>;
++			pinctrl-1 = <&spi0_cs0_pi_pin>;
++			pinctrl-2 = <&spi0_cs1_pi_pin>;
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-spi-jedec-nor.dtso b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-spi-jedec-nor.dtso
+new file mode 100644
+index 000000000000..b91097eca5b6
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-spi-jedec-nor.dtso
+@@ -0,0 +1,57 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun7i-a20";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi0 = "/soc@1c00000/spi@1c05000";
++			spi1 = "/soc@1c00000/spi@1c06000";
++			spi2 = "/soc@1c00000/spi@1c17000";
++		};
++	};
++
++	fragment@1 {
++		target = <&spi0>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spiflash@0 {
++				compatible = "jedec,spi-nor";
++				status = "disabled";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&spi1>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spiflash@0 {
++				compatible = "jedec,spi-nor";
++				status = "disabled";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++
++	fragment@3 {
++		target = <&spi2>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spiflash@0 {
++				compatible = "jedec,spi-nor";
++				status = "disabled";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-spi-spidev.dtso b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-spi-spidev.dtso
+new file mode 100644
+index 000000000000..341fe3229ffc
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-spi-spidev.dtso
+@@ -0,0 +1,57 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun7i-a20";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi0 = "/soc@1c00000/spi@1c05000";
++			spi1 = "/soc@1c00000/spi@1c06000";
++			spi2 = "/soc@1c00000/spi@1c17000";
++		};
++	};
++
++	fragment@1 {
++		target = <&spi0>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spidev@0 {
++				compatible = "armbian,spi-dev";
++				status = "disabled";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&spi1>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spidev@0 {
++				compatible = "armbian,spi-dev";
++				status = "disabled";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++
++	fragment@3 {
++		target = <&spi2>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spidev@0 {
++				compatible = "armbian,spi-dev";
++				status = "disabled";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-spi0.dtso b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-spi0.dtso
+new file mode 100644
+index 000000000000..cad50d8a29a7
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-spi0.dtso
+@@ -0,0 +1,23 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun7i-a20";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi0 = "/soc@1c00000/spi@1c05000";
++		};
++	};
++
++	fragment@1 {
++		target = <&spi0>;
++		__overlay__ {
++			status = "okay";
++			pinctrl-names = "default", "default";
++			pinctrl-0 = <&spi0_pi_pins>;
++			pinctrl-1 = <&spi0_cs0_pi_pin>;
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-spi1.dtso b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-spi1.dtso
+new file mode 100644
+index 000000000000..f0218eb9f76b
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-spi1.dtso
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun7i-a20";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi1 = "/soc@1c00000/spi@1c06000";
++		};
++	};
++
++	fragment@1 {
++		target = <&spi1>;
++		__overlay__ {
++			status = "okay";
++			pinctrl-names = "default";
++			pinctrl-0 = <&spi1_pi_pins>, <&spi1_cs0_pi_pin>;
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-spi2.dtso b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-spi2.dtso
+new file mode 100644
+index 000000000000..effba42b48bd
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-spi2.dtso
+@@ -0,0 +1,23 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun7i-a20";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi2 = "/soc@1c00000/spi@1c17000";
++		};
++	};
++
++	fragment@1 {
++		target = <&spi2>;
++		__overlay__ {
++			status = "okay";
++			pinctrl-names = "default", "default";
++			pinctrl-0 = <&spi2_pb_pins>;
++			pinctrl-1 = <&spi2_pb_cs0_pin>;
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-uart2.dtso b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-uart2.dtso
+new file mode 100644
+index 000000000000..79d1dca7a311
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-uart2.dtso
+@@ -0,0 +1,32 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun7i-a20";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			serial2 = "/soc@1c00000/serial@1c28800";
++		};
++	};
++
++	fragment@1 {
++		target = <&pio>;
++		__overlay__ {
++			uart2_pins_a_2: uart2@1 {
++				pins = "PI18", "PI19";
++				function = "uart2";
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&uart2>;
++		 __overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart2_pins_a_2>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-uart3.dtso b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-uart3.dtso
+new file mode 100644
+index 000000000000..703acbcf377b
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-uart3.dtso
+@@ -0,0 +1,42 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun7i-a20";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			serial3 = "/soc@1c00000/serial@1c28c00";
++		};
++	};
++
++	fragment@1 {
++		target = <&pio>;
++		__overlay__ {
++			uart3_pins_a_2: uart3@2 {
++				pins = "PG6", "PG7";
++				function = "uart3";
++			};
++
++			uart3_pins_a_rts_cts: uart3@1 {
++				pins = "PG8", "PG9";
++				function = "uart3";
++			};
++
++			uart3_pins_b_rts_cts: uart3@3 {
++				pins = "PH2", "PH3";
++				function = "uart3";
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&uart3>;
++		 __overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart3_pins_a_2>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-uart4.dtso b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-uart4.dtso
+new file mode 100644
+index 000000000000..19180341a67f
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-uart4.dtso
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun7i-a20";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			serial4 = "/soc@1c00000/serial@1c29000";
++		};
++	};
++
++	fragment@1 {
++		target = <&uart4>;
++		 __overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart4_pg_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-uart5.dtso b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-uart5.dtso
+new file mode 100644
+index 000000000000..a1369eee2917
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-uart5.dtso
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun7i-a20";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			serial5 = "/soc@1c00000/serial@1c29400";
++		};
++	};
++
++	fragment@1 {
++		target = <&uart5>;
++		 __overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart5_pi_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-uart6.dtso b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-uart6.dtso
+new file mode 100644
+index 000000000000..fb9efe2a9475
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-uart6.dtso
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun7i-a20";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			serial6 = "/soc@1c00000/serial@1c29800";
++		};
++	};
++
++	fragment@1 {
++		target = <&uart6>;
++		 __overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart6_pi_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-uart7.dtso b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-uart7.dtso
+new file mode 100644
+index 000000000000..bbdca3ec67ed
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-uart7.dtso
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun7i-a20";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			serial7 = "/soc@1c00000/serial@1c29c00";
++		};
++	};
++
++	fragment@1 {
++		target = <&uart7>;
++		 __overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart7_pi_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-w1-gpio.dtso b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-w1-gpio.dtso
+new file mode 100644
+index 000000000000..7d77606a1604
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun7i-a20-w1-gpio.dtso
+@@ -0,0 +1,29 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun7i-a20";
++
++	fragment@0 {
++		target = <&pio>;
++		__overlay__ {
++			w1_pins: w1_pins {
++				pins = "PI15";
++				function = "gpio_in";
++			};
++		};
++	};
++
++	fragment@1 {
++		target-path = "/";
++		__overlay__ {
++			onewire@0 {
++				compatible = "w1-gpio";
++				pinctrl-names = "default";
++				pinctrl-0 = <&w1_pins>;
++				gpios = <&pio 8 15 0>; /* PI15 */
++				status = "okay";
++			};
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-analog-codec.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-analog-codec.dtso
+new file mode 100644
+index 000000000000..36dbc31ae2a2
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-analog-codec.dtso
+@@ -0,0 +1,17 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun8i-h3";
++
++	fragment@0 {
++		target = <&codec>;
++		__overlay__ {
++			allwinner,audio-routing =
++				"Line Out", "LINEOUT",
++				"MIC1", "Mic",
++				"Mic",  "MBIAS";
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-cir.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-cir.dtso
+new file mode 100644
+index 000000000000..bf4a0eafa133
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-cir.dtso
+@@ -0,0 +1,15 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun8i-h3";
++
++	fragment@0 {
++		target = <&ir>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&r_ir_rx_pin>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-fixup.scr-cmd b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-fixup.scr-cmd
+new file mode 100644
+index 000000000000..604fe8bb78c1
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-fixup.scr-cmd
+@@ -0,0 +1,110 @@
++# overlays fixup script
++# implements (or rather substitutes) overlay arguments functionality
++# using u-boot scripting, environment variables and "fdt" command
++
++# setexpr test_var ${tmp_bank} - A
++# works only for hex numbers (A-F)
++
++setenv decompose_pin 'setexpr tmp_bank sub "P(A|C|D|G)\\d+" "\\1";
++setexpr tmp_pin sub "P\\S(\\d+)" "\\1";
++test "${tmp_bank}" = "A" && setenv tmp_bank 0;
++test "${tmp_bank}" = "C" && setenv tmp_bank 2;
++test "${tmp_bank}" = "D" && setenv tmp_bank 3;
++test "${tmp_bank}" = "G" && setenv tmp_bank 6'
++
++if test -n "${param_spinor_spi_bus}"; then
++	test "${param_spinor_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c68000"
++	test "${param_spinor_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c69000"
++	fdt set /soc/${tmp_spi_path} status "okay"
++	fdt set /soc/${tmp_spi_path}/spiflash status "okay"
++	if test -n "${param_spinor_max_freq}"; then
++		fdt set /soc/${tmp_spi_path}/spiflash spi-max-frequency "<${param_spinor_max_freq}>"
++	fi
++	if test "${param_spinor_spi_cs}" = "1"; then
++		fdt set /soc/${tmp_spi_path}/spiflash reg "<1>"
++	fi
++	env delete tmp_spi_path
++fi
++
++if test -n "${param_spidev_spi_bus}"; then
++	test "${param_spidev_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c68000"
++	test "${param_spidev_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c69000"
++	fdt set /soc/${tmp_spi_path} status "okay"
++	fdt set /soc/${tmp_spi_path}/spidev status "okay"
++	if test -n "${param_spidev_max_freq}"; then
++		fdt set /soc/${tmp_spi_path}/spidev spi-max-frequency "<${param_spidev_max_freq}>"
++	fi
++	if test "${param_spidev_spi_cs}" = "1"; then
++		fdt set /soc/${tmp_spi_path}/spidev reg "<1>"
++	fi
++	env delete tmp_spi_path
++fi
++
++if test -n "${param_pps_pin}"; then
++	setenv tmp_bank "${param_pps_pin}"
++	setenv tmp_pin "${param_pps_pin}"
++	run decompose_pin
++	fdt set /soc/pinctrl@1c20800/pps_pins pins "${param_pps_pin}"
++	fdt get value tmp_phandle /soc/pinctrl@1c20800 phandle
++	fdt set /pps@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>"
++	env delete tmp_pin tmp_bank tmp_phandle
++fi
++
++if test "${param_pps_falling_edge}" = "1"; then
++	fdt set /pps@0 assert-falling-edge
++fi
++
++for f in ${overlays}; do
++	if test "${f}" = "pwm"; then
++		setenv bootargs_new ""
++		for arg in ${bootargs}; do
++			if test "${arg}" = "console=ttyS0,115200"; then
++				echo "Warning: Disabling ttyS0 console due to enabled PWM overlay"
++			else
++				setenv bootargs_new "${bootargs_new} ${arg}"
++			fi
++		done
++		setenv bootargs "${bootargs_new}"
++	fi
++done
++
++if test -n "${param_w1_pin}"; then
++	setenv tmp_bank "${param_w1_pin}"
++	setenv tmp_pin "${param_w1_pin}"
++	run decompose_pin
++	fdt set /soc/pinctrl@1c20800/w1_pins pins "${param_w1_pin}"
++	fdt get value tmp_phandle /soc/pinctrl@1c20800 phandle
++	fdt set /onewire@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>"
++	env delete tmp_pin tmp_bank tmp_phandle
++fi
++
++if test "${param_w1_pin_int_pullup}" = "1"; then
++	fdt set /soc/pinctrl@1c20800/w1_pins bias-pull-up
++fi
++
++if test "${param_uart1_rtscts}" = "1"; then
++	fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart1-pins phandle
++	fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart1-rts-cts-pins phandle
++	fdt set /soc/serial@1c28400 pinctrl-names "default" "default"
++	fdt set /soc/serial@1c28400 pinctrl-0 "<${tmp_phandle1}>"
++	fdt set /soc/serial@1c28400 pinctrl-1 "<${tmp_phandle2}>"
++	env delete tmp_phandle1 tmp_phandle2
++fi
++
++if test "${param_uart2_rtscts}" = "1"; then
++	fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart2-pins phandle
++	fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart2-rts-cts-pins phandle
++	fdt set /soc/serial@1c28800 pinctrl-names "default" "default"
++	fdt set /soc/serial@1c28800 pinctrl-0 "<${tmp_phandle1}>"
++	fdt set /soc/serial@1c28800 pinctrl-1 "<${tmp_phandle2}>"
++	env delete tmp_phandle1 tmp_phandle2
++fi
++
++if test "${param_uart3_rtscts}" = "1"; then
++	fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart3-pins phandle
++	fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart3-rts-cts-pins phandle
++	fdt set /soc/serial@1c28c00 pinctrl-names "default" "default"
++	fdt set /soc/serial@1c28c00 pinctrl-0 "<${tmp_phandle1}>"
++	fdt set /soc/serial@1c28c00 pinctrl-1 "<${tmp_phandle2}>"
++	env delete tmp_phandle1 tmp_phandle2
++fi
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-i2c0.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-i2c0.dtso
+new file mode 100644
+index 000000000000..a36ac8667674
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-i2c0.dtso
+@@ -0,0 +1,20 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun8i-h3";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			i2c0 = "/soc/i2c@1c2ac00";
++		};
++	};
++
++	fragment@1 {
++		target = <&i2c0>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-i2c1.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-i2c1.dtso
+new file mode 100644
+index 000000000000..258c86de07cc
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-i2c1.dtso
+@@ -0,0 +1,20 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun8i-h3";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			i2c1 = "/soc/i2c@1c2b000";
++		};
++	};
++
++	fragment@1 {
++		target = <&i2c1>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-i2c2.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-i2c2.dtso
+new file mode 100644
+index 000000000000..a1e3284984df
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-i2c2.dtso
+@@ -0,0 +1,20 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun8i-h3";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			i2c2 = "/soc/i2c@1c2b400";
++		};
++	};
++
++	fragment@1 {
++		target = <&i2c2>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-pps-gpio.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-pps-gpio.dtso
+new file mode 100644
+index 000000000000..16a737b02935
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-pps-gpio.dtso
+@@ -0,0 +1,29 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun8i-h3";
++
++	fragment@0 {
++		target = <&pio>;
++		__overlay__ {
++			pps_pins: pps_pins {
++				pins = "PD14";
++				function = "gpio_in";
++			};
++		};
++	};
++
++	fragment@1 {
++		target-path = "/";
++		__overlay__ {
++			pps@0 {
++				compatible = "pps-gpio";
++				pinctrl-names = "default";
++				pinctrl-0 = <&pps_pins>;
++				gpios = <&pio 3 14 0>; /* PD14 */
++				status = "okay";
++			};
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-pwm.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-pwm.dtso
+new file mode 100644
+index 000000000000..ed3b8e606249
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-pwm.dtso
+@@ -0,0 +1,39 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun8i-h3";
++
++	fragment@0 {
++		target-path = "/chosen";
++		__overlay__ {
++			/delete-property/ stdout-path;
++		};
++	};
++
++	fragment@1 {
++		target = <&uart0>;
++		__overlay__ {
++			status = "disabled";
++		};
++	};
++
++	fragment@2 {
++		target = <&pio>;
++		__overlay__ {
++			pwm0_pin: pwm0 {
++				pins = "PA5";
++				function = "pwm0";
++			};
++		};
++	};
++
++	fragment@3 {
++		target = <&pwm>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&pwm0_pin>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-spdif-out.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-spdif-out.dtso
+new file mode 100644
+index 000000000000..35b2d567704c
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-spdif-out.dtso
+@@ -0,0 +1,38 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun8i-h3";
++
++	fragment@0 {
++		target = <&spdif>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&spdif_tx_pin>;
++			status = "okay";
++		};
++	};
++
++	fragment@1 {
++		target-path = "/";
++		__overlay__ {
++			sound {
++				compatible = "simple-audio-card";
++				simple-audio-card,name = "On-board SPDIF";
++
++				simple-audio-card,cpu {
++					sound-dai = <&spdif>;
++				};
++
++				simple-audio-card,codec {
++					sound-dai = <&spdif_out>;
++				};
++			};
++
++			spdif_out: spdif-out {
++				#sound-dai-cells = <0>;
++				compatible = "linux,spdif-dit";
++			};
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-spi-add-cs1.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-spi-add-cs1.dtso
+new file mode 100644
+index 000000000000..bd8e2561729d
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-spi-add-cs1.dtso
+@@ -0,0 +1,41 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun8i-h3";
++
++	fragment@0 {
++		target = <&pio>;
++		__overlay__ {
++			spi0_cs1: spi0_cs1 {
++				pins = "PA21";
++				function = "gpio_out";
++				output-high;
++			};
++
++			spi1_cs1: spi1_cs1 {
++				pins = "PA10";
++				function = "gpio_out";
++				output-high;
++			};
++		};
++	};
++
++	fragment@1 {
++		target = <&spi0>;
++		__overlay__ {
++			pinctrl-names = "default", "default";
++			pinctrl-1 = <&spi0_cs1>;
++			cs-gpios = <0>, <&pio 0 21 0>; /* PA21 */
++		};
++	};
++
++	fragment@2 {
++		target = <&spi1>;
++		__overlay__ {
++			pinctrl-names = "default", "default";
++			pinctrl-1 = <&spi1_cs1>;
++			cs-gpios = <0>, <&pio 0 10 0>; /* PA10 */
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-spi-jedec-nor.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-spi-jedec-nor.dtso
+new file mode 100644
+index 000000000000..95fa5f2ca1ef
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-spi-jedec-nor.dtso
+@@ -0,0 +1,42 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun8i-h3";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi0 = "/soc/spi@1c68000";
++			spi1 = "/soc/spi@1c69000";
++		};
++	};
++
++	fragment@1 {
++		target = <&spi0>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spiflash@0 {
++				compatible = "jedec,spi-nor";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++				status = "disabled";
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&spi1>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spiflash@0 {
++				compatible = "jedec,spi-nor";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++				status = "disabled";
++			};
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-spi-spidev.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-spi-spidev.dtso
+new file mode 100644
+index 000000000000..c79beb95ecfa
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-spi-spidev.dtso
+@@ -0,0 +1,42 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun8i-h3";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi0 = "/soc/spi@1c68000";
++			spi1 = "/soc/spi@1c69000";
++		};
++	};
++
++	fragment@1 {
++		target = <&spi0>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spidev@0 {
++				compatible = "armbian,spi-dev";
++				status = "disabled";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&spi1>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spidev@0 {
++				compatible = "armbian,spi-dev";
++				status = "disabled";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-uart1.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-uart1.dtso
+new file mode 100644
+index 000000000000..3c10d4db420b
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-uart1.dtso
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun8i-h3";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			serial1 = "/soc/serial@1c28400";
++		};
++	};
++
++	fragment@1 {
++		target = <&uart1>;
++		 __overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart1_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-uart2.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-uart2.dtso
+new file mode 100644
+index 000000000000..f16e61862913
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-uart2.dtso
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun8i-h3";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			serial2 = "/soc/serial@1c28800";
++		};
++	};
++
++	fragment@1 {
++		target = <&uart2>;
++		 __overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart2_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-uart3.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-uart3.dtso
+new file mode 100644
+index 000000000000..b1aef575e0f0
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-uart3.dtso
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun8i-h3";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			serial3 = "/soc/serial@1c28c00";
++		};
++	};
++
++	fragment@1 {
++		target = <&uart3>;
++		 __overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart3_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-usbhost0.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-usbhost0.dtso
+new file mode 100644
+index 000000000000..6bd8aedbee20
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-usbhost0.dtso
+@@ -0,0 +1,27 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun8i-h3";
++
++	fragment@0 {
++		target = <&ehci0>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++
++	fragment@1 {
++		target = <&ohci0>;
++		 __overlay__ {
++			status = "okay";
++		};
++	};
++
++	fragment@2 {
++		target = <&usbphy>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-usbhost1.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-usbhost1.dtso
+new file mode 100644
+index 000000000000..4c7222b10beb
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-usbhost1.dtso
+@@ -0,0 +1,27 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun8i-h3";
++
++	fragment@0 {
++		target = <&ehci1>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++
++	fragment@1 {
++		target = <&ohci1>;
++		 __overlay__ {
++			status = "okay";
++		};
++	};
++
++	fragment@2 {
++		target = <&usbphy>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-usbhost2.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-usbhost2.dtso
+new file mode 100644
+index 000000000000..2b83ec933a9d
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-usbhost2.dtso
+@@ -0,0 +1,27 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun8i-h3";
++
++	fragment@0 {
++		target = <&ehci2>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++
++	fragment@1 {
++		target = <&ohci2>;
++		 __overlay__ {
++			status = "okay";
++		};
++	};
++
++	fragment@2 {
++		target = <&usbphy>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-usbhost3.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-usbhost3.dtso
+new file mode 100644
+index 000000000000..e2f28ab1ae64
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-usbhost3.dtso
+@@ -0,0 +1,27 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun8i-h3";
++
++	fragment@0 {
++		target = <&ehci3>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++
++	fragment@1 {
++		target = <&ohci3>;
++		 __overlay__ {
++			status = "okay";
++		};
++	};
++
++	fragment@2 {
++		target = <&usbphy>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-w1-gpio.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-w1-gpio.dtso
+new file mode 100644
+index 000000000000..f4ccb7fba9ad
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-w1-gpio.dtso
+@@ -0,0 +1,29 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun8i-h3";
++
++	fragment@0 {
++		target = <&pio>;
++		__overlay__ {
++			w1_pins: w1_pins {
++				pins = "PD14";
++				function = "gpio_in";
++			};
++		};
++	};
++
++	fragment@1 {
++		target-path = "/";
++		__overlay__ {
++			onewire@0 {
++				compatible = "w1-gpio";
++				pinctrl-names = "default";
++				pinctrl-0 = <&w1_pins>;
++				gpios = <&pio 3 14 0>; /* PD14 */
++				status = "okay";
++			};
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-r40-i2c2.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-r40-i2c2.dtso
+new file mode 100644
+index 000000000000..a1e3284984df
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-r40-i2c2.dtso
+@@ -0,0 +1,20 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun8i-h3";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			i2c2 = "/soc/i2c@1c2b400";
++		};
++	};
++
++	fragment@1 {
++		target = <&i2c2>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-r40-i2c3.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-r40-i2c3.dtso
+new file mode 100644
+index 000000000000..949a98234551
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-r40-i2c3.dtso
+@@ -0,0 +1,20 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun8i-h3";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			i2c3 = "/soc/i2c@1c2b800";
++		};
++	};
++
++	fragment@1 {
++		target = <&i2c3>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-r40-spi-spidev0.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-r40-spi-spidev0.dtso
+new file mode 100644
+index 000000000000..fae9c3f75bb7
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-r40-spi-spidev0.dtso
+@@ -0,0 +1,27 @@
++/dts-v1/;
++/ {
++    compatible = "allwinner,sun8i-r40";
++    fragment@0 {
++        target-path = "/aliases";
++        __overlay__ {
++            spi0 = "/soc/spi@1c05000";
++        };
++    };
++    fragment@1 {
++        target = <0xffffffff>;
++        __overlay__ {
++            #address-cells = <0x00000001>;
++            #size-cells = <0x00000000>;
++            status = "okay";
++            spidev@0 {
++                compatible = "armbian,spi-dev";
++                status = "okay";
++                reg = <0x00000000>;
++                spi-max-frequency = <0x000f4240>;
++            };
++        };
++    };
++    __fixups__ {
++        spi0 = "/fragment@1:target:0";
++    };
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-r40-spi-spidev1.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-r40-spi-spidev1.dtso
+new file mode 100644
+index 000000000000..cb98ddf6bbd8
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-r40-spi-spidev1.dtso
+@@ -0,0 +1,27 @@
++/dts-v1/;
++/ {
++    compatible = "allwinner,sun8i-r40";
++    fragment@0 {
++        target-path = "/aliases";
++        __overlay__ {
++            spi1 = "/soc/spi@1c06000";
++        };
++    };
++    fragment@1 {
++        target = <0xffffffff>;
++        __overlay__ {
++            #address-cells = <0x00000001>;
++            #size-cells = <0x00000000>;
++            status = "okay";
++            spidev@0 {
++                compatible = "armbian,spi-dev";
++                status = "okay";
++                reg = <0x00000000>;
++                spi-max-frequency = <0x000f4240>;
++            };
++        };
++    };
++    __fixups__ {
++        spi1 = "/fragment@1:target:0";
++    };
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-r40-uart2.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-r40-uart2.dtso
+new file mode 100644
+index 000000000000..2030d6777fa9
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-r40-uart2.dtso
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/ {
++    compatible = "allwinner,sun8i-r40";
++    fragment@0 {
++        target-path = "/aliases";
++        __overlay__ {
++            serial2 = "/soc/serial@1c28800";
++        };
++    };
++    fragment@1 {
++        target = <0xffffffff>;
++        __overlay__ {
++            pinctrl-names = "default";
++            pinctrl-0 = <0xffffffff>;
++            status = "okay";
++        };
++    };
++    __fixups__ {
++        uart2 = "/fragment@1:target:0";
++        uart2_pi_pins = "/fragment@1/__overlay__:pinctrl-0:0";
++    };
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-r40-uart4.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-r40-uart4.dtso
+new file mode 100644
+index 000000000000..0d7f934f6828
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-r40-uart4.dtso
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/ {
++    compatible = "allwinner,sun8i-r40";
++    fragment@0 {
++        target-path = "/aliases";
++        __overlay__ {
++            serial4 = "/soc/serial@1c29000";
++        };
++    };
++    fragment@1 {
++        target = <0xffffffff>;
++        __overlay__ {
++            pinctrl-names = "default";
++            pinctrl-0 = <0xffffffff>;
++            status = "okay";
++        };
++    };
++    __fixups__ {
++        uart4 = "/fragment@1:target:0";
++        uart4_ph_pins = "/fragment@1/__overlay__:pinctrl-0:0";
++    };
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-r40-uart5.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-r40-uart5.dtso
+new file mode 100644
+index 000000000000..e695535afc7e
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-r40-uart5.dtso
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/ {
++    compatible = "allwinner,sun8i-r40";
++    fragment@0 {
++        target-path = "/aliases";
++        __overlay__ {
++            serial5 = "/soc/serial@1c29400";
++        };
++    };
++    fragment@1 {
++        target = <0xffffffff>;
++        __overlay__ {
++            pinctrl-names = "default";
++            pinctrl-0 = <0xffffffff>;
++            status = "okay";
++        };
++    };
++    __fixups__ {
++        uart5 = "/fragment@1:target:0";
++        uart5_ph_pins = "/fragment@1/__overlay__:pinctrl-0:0";
++    };
++};
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-r40-uart7.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-r40-uart7.dtso
+new file mode 100644
+index 000000000000..e572598339a6
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-r40-uart7.dtso
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/ {
++    compatible = "allwinner,sun8i-r40";
++    fragment@0 {
++        target-path = "/aliases";
++        __overlay__ {
++            serial7 = "/soc/serial@1c29c00";
++        };
++    };
++    fragment@1 {
++        target = <0xffffffff>;
++        __overlay__ {
++            pinctrl-names = "default";
++            pinctrl-0 = <0xffffffff>;
++            status = "okay";
++        };
++    };
++    __fixups__ {
++        uart7 = "/fragment@1:target:0";
++        uart7_pi_pins = "/fragment@1/__overlay__:pinctrl-0:0";
++    };
++};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-overlay-sun8i-h3-cpu-clock-add-overclock.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-overlay-sun8i-h3-cpu-clock-add-overclock.patch
new file mode 100644
index 000000000000..39057b76d5d0
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-overlay-sun8i-h3-cpu-clock-add-overclock.patch
@@ -0,0 +1,209 @@
+From ec30b77c7935d7f1ec1ea430424dddfe552e55c8 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Wed, 2 Feb 2022 21:29:16 +0300
+Subject: arm:dts:overlay: sun8i-h3-cpu-clock add overclock
+
+---
+ arch/arm/boot/dts/allwinner/overlay/Makefile  |  3 +
+ .../sun8i-h3-cpu-clock-1.2GHz-1.3v.dtso       | 31 +++++++++
+ .../sun8i-h3-cpu-clock-1.368GHz-1.3v.dtso     | 67 +++++++++++++++++++
+ .../sun8i-h3-cpu-clock-1.3GHz-1.3v.dtso       | 61 +++++++++++++++++
+ 4 files changed, 162 insertions(+)
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-h3-cpu-clock-1.2GHz-1.3v.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-h3-cpu-clock-1.368GHz-1.3v.dtso
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-h3-cpu-clock-1.3GHz-1.3v.dtso
+
+diff --git a/arch/arm/boot/dts/allwinner/overlay/Makefile b/arch/arm/boot/dts/allwinner/overlay/Makefile
+index 0c47e8fda8fc..560f926b7018 100644
+--- a/arch/arm/boot/dts/allwinner/overlay/Makefile
++++ b/arch/arm/boot/dts/allwinner/overlay/Makefile
+@@ -60,6 +60,9 @@ dtb-$(CONFIG_MACH_SUN7I) += \
+ dtb-$(CONFIG_MACH_SUN8I) += \
+ 	sun8i-h3-analog-codec.dtbo \
+ 	sun8i-h3-cir.dtbo \
++	sun8i-h3-cpu-clock-1.2GHz-1.3v.dtbo \
++	sun8i-h3-cpu-clock-1.368GHz-1.3v.dtbo \
++	sun8i-h3-cpu-clock-1.3GHz-1.3v.dtbo \
+ 	sun8i-h3-i2c0.dtbo \
+ 	sun8i-h3-i2c1.dtbo \
+ 	sun8i-h3-i2c2.dtbo \
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-cpu-clock-1.2GHz-1.3v.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-cpu-clock-1.2GHz-1.3v.dtso
+new file mode 100644
+index 000000000000..b07e694c781a
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-cpu-clock-1.2GHz-1.3v.dtso
+@@ -0,0 +1,31 @@
++// DT overlay for CPU frequency operating points to up to 1.2GHz at a maximum CPU voltage of 1.3v
++
++/dts-v1/;
++/plugin/;
++
++/ {
++	fragment@0 {
++		target = <&cpu0_opp_table>;
++
++		__overlay__ {
++			compatible = "operating-points-v2";
++			opp-shared;
++
++			// in order to match the existing DT cooling-maps, update the existing OP table in-place
++			// with the new voltages
++
++			opp-1104000000 {
++				opp-hz = /bits/ 64 <1104000000>;
++				opp-microvolt = <1300000 1300000 1300000>;
++				clock-latency-ns = <244144>; /* 8 32k periods */
++			};
++
++			opp-1200000000 {
++				opp-hz = /bits/ 64 <1200000000>;
++				opp-microvolt = <1300000 1300000 1300000>;
++				clock-latency-ns = <244144>; /* 8 32k periods */
++			};
++		};
++	};
++};
++
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-cpu-clock-1.368GHz-1.3v.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-cpu-clock-1.368GHz-1.3v.dtso
+new file mode 100644
+index 000000000000..e3fd7e5c85a6
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-cpu-clock-1.368GHz-1.3v.dtso
+@@ -0,0 +1,67 @@
++// DT overlay for CPU frequency operating points to 1.3GHz at a maximum CPU voltage of 1.3v
++
++/dts-v1/;
++/plugin/;
++
++/ {
++	fragment@0 {
++		target = <&cpu0_opp_table>;
++
++		__overlay__ {
++			compatible = "operating-points-v2";
++			opp-shared;
++
++			// in order to match the DT cooling-maps, update the existing OP table in-place
++			// with the new voltages
++
++			opp-1056000000 {
++				opp-hz = /bits/ 64 <1056000000>;
++				opp-microvolt = <1300000 1300000 1300000>;
++				clock-latency-ns = <244144>; /* 8 32k periods */
++			};
++
++			opp-1104000000 {
++				opp-hz = /bits/ 64 <1104000000>;
++				opp-microvolt = <1300000 1300000 1300000>;
++				clock-latency-ns = <244144>; /* 8 32k periods */
++			};
++
++			opp-1152000000 {
++				opp-hz = /bits/ 64 <1152000000>;
++				opp-microvolt = <1300000 1300000 1300000>;
++				clock-latency-ns = <244144>; /* 8 32k periods */
++			};
++
++			opp-1200000000 {
++				opp-hz = /bits/ 64 <1200000000>;
++				opp-microvolt = <1300000 1300000 1300000>;
++				clock-latency-ns = <244144>; /* 8 32k periods */
++			};
++
++			opp-1224000000 {
++				opp-hz = /bits/ 64 <1224000000>;
++				opp-microvolt = <1300000 1300000 1300000>;
++				clock-latency-ns = <244144>; /* 8 32k periods */
++			};
++
++			opp-1248000000 {
++				opp-hz = /bits/ 64 <1248000000>;
++				opp-microvolt = <1300000 1300000 1300000>;
++				clock-latency-ns = <244144>; /* 8 32k periods */
++			};
++
++			opp-1296000000 {
++				opp-hz = /bits/ 64 <1296000000>;
++				opp-microvolt = <1300000 1300000 1300000>;
++				clock-latency-ns = <244144>; /* 8 32k periods */
++			};
++
++			opp-1368000000 {
++				opp-hz = /bits/ 64 <1368000000>;
++				opp-microvolt = <1300000 1300000 1300000>;
++				clock-latency-ns = <244144>; /* 8 32k periods */
++			};
++		};
++	};
++};
++
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-cpu-clock-1.3GHz-1.3v.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-cpu-clock-1.3GHz-1.3v.dtso
+new file mode 100644
+index 000000000000..413222831eab
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-cpu-clock-1.3GHz-1.3v.dtso
+@@ -0,0 +1,61 @@
++// DT overlay for CPU frequency operating points to 1.3GHz at a maximum CPU voltage of 1.3v
++
++/dts-v1/;
++/plugin/;
++
++/ {
++	fragment@0 {
++		target = <&cpu0_opp_table>;
++
++		__overlay__ {
++			compatible = "operating-points-v2";
++			opp-shared;
++
++			// in order to match the DT cooling-maps, update the existing OP table in-place
++			// with the new voltages
++
++			opp-1056000000 {
++				opp-hz = /bits/ 64 <1056000000>;
++				opp-microvolt = <1300000 1300000 1300000>;
++				clock-latency-ns = <244144>; /* 8 32k periods */
++			};
++
++			opp-1104000000 {
++				opp-hz = /bits/ 64 <1104000000>;
++				opp-microvolt = <1300000 1300000 1300000>;
++				clock-latency-ns = <244144>; /* 8 32k periods */
++			};
++
++			opp-1152000000 {
++				opp-hz = /bits/ 64 <1152000000>;
++				opp-microvolt = <1300000 1300000 1300000>;
++				clock-latency-ns = <244144>; /* 8 32k periods */
++			};
++
++			opp-1200000000 {
++				opp-hz = /bits/ 64 <1200000000>;
++				opp-microvolt = <1300000 1300000 1300000>;
++				clock-latency-ns = <244144>; /* 8 32k periods */
++			};
++
++			opp-1224000000 {
++				opp-hz = /bits/ 64 <1224000000>;
++				opp-microvolt = <1300000 1300000 1300000>;
++				clock-latency-ns = <244144>; /* 8 32k periods */
++			};
++
++			opp-1248000000 {
++				opp-hz = /bits/ 64 <1248000000>;
++				opp-microvolt = <1300000 1300000 1300000>;
++				clock-latency-ns = <244144>; /* 8 32k periods */
++			};
++
++			opp-1296000000 {
++				opp-hz = /bits/ 64 <1296000000>;
++				opp-microvolt = <1300000 1300000 1300000>;
++				clock-latency-ns = <244144>; /* 8 32k periods */
++			};
++		};
++	};
++};
++
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun5i-a13-olinuxino-Add-panel-lcd-olinuxino-4.3-needed-.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun5i-a13-olinuxino-Add-panel-lcd-olinuxino-4.3-needed-.patch
new file mode 100644
index 000000000000..7d2f97eb9855
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun5i-a13-olinuxino-Add-panel-lcd-olinuxino-4.3-needed-.patch
@@ -0,0 +1,133 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: hehopmajieh <hehopmajieh@debian.bg>
+Date: Thu, 19 Mar 2020 10:40:44 +0200
+Subject: arm:dts:sun5i-a13-olinuxino Add panel lcd-olinuxino-4.3 needed to fix
+ overlay tests
+
+---
+ arch/arm/boot/dts/allwinner/sun5i-a13-olinuxino.dts | 79 ++++++----
+ 1 file changed, 44 insertions(+), 35 deletions(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/allwinner/sun5i-a13-olinuxino.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/allwinner/sun5i-a13-olinuxino.dts
++++ b/arch/arm/boot/dts/allwinner/sun5i-a13-olinuxino.dts
+@@ -48,6 +48,7 @@
+ 
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/input/input.h>
++#include <dt-bindings/pwm/pwm.h>
+ 
+ / {
+ 	model = "Olimex A13-Olinuxino";
+@@ -72,40 +73,28 @@ led {
+ 		};
+ 	};
+ 
+-	bridge {
+-		compatible = "dumb-vga-dac";
++	lcd_backlight: backlight {
++                compatible = "pwm-backlight";
++                pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
++                brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
++                default-brightness-level = <8>;
++        };
++
++        panel: panel {
++                compatible = "olimex,lcd-olinuxino-4.3";
++                backlight = <&lcd_backlight>;
++                enable-gpios = <&axp_gpio 0 GPIO_ACTIVE_HIGH>; /* AXP GPIO0 */
++                pinctrl-names = "default";
++                #address-cells = <1>;
++                #size-cells = <0>;
++                port {
++                        panel_input: endpoint {
++                        	remote-endpoint = <&tcon0_out_lcd>;
++                        };
++                };
++
++        };
+ 
+-		ports {
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-
+-			port@0 {
+-				reg = <0>;
+-
+-				vga_bridge_in: endpoint {
+-					remote-endpoint = <&tcon0_out_vga>;
+-				};
+-			};
+-
+-			port@1 {
+-				reg = <1>;
+-
+-				vga_bridge_out: endpoint {
+-					remote-endpoint = <&vga_con_in>;
+-				};
+-			};
+-		};
+-	};
+-
+-	vga {
+-		compatible = "vga-connector";
+-
+-		port {
+-			vga_con_in: endpoint {
+-				remote-endpoint = <&vga_bridge_out>;
+-			};
+-		};
+-	};
+ };
+ 
+ &be0 {
+@@ -130,6 +119,11 @@ axp209: pmic@34 {
+ 
+ 		interrupt-controller;
+ 		#interrupt-cells = <1>;
++		axp_gpio:gpio{ 
++                        compatible = "x-powers,axp209-gpio";
++                        gpio-controller;
++                        #gpio-cells = <2>; 
++                };
+ 	};
+ };
+ 
+@@ -221,12 +215,18 @@ &tcon0 {
+ };
+ 
+ &tcon0_out {
+-	tcon0_out_vga: endpoint@0 {
++	tcon0_out_lcd: endpoint@0 {
+ 		reg = <0>;
+-		remote-endpoint = <&vga_bridge_in>;
++		remote-endpoint = <&panel_input>;
+ 	};
+ };
+ 
++&pwm {
++        pinctrl-names = "default";
++        pinctrl-0 = <&pwm0_pin>;
++        status = "okay";
++};
++
+ &uart1 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart1_pg_pins>;
+@@ -245,3 +245,12 @@ &usbphy {
+ 	usb1_vbus-supply = <&reg_usb1_vbus>;
+ 	status = "okay";
+ };
++
++&rtp {
++	allwinner,ts-attached;
++	#thermal-sensor-cells = <0>;
++	/* sensitive/noisy touch panel */
++	touchscreen-inverted-x;
++	allwinner,tp-sensitive-adjust = <0>;
++	allwinner,filter-type = <3>;
++};
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun5i-a13-olinuxino-micro-add-panel-lcd-olinuxino-4.3.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun5i-a13-olinuxino-micro-add-panel-lcd-olinuxino-4.3.patch
new file mode 100644
index 000000000000..ec37739c3be9
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun5i-a13-olinuxino-micro-add-panel-lcd-olinuxino-4.3.patch
@@ -0,0 +1,106 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Mitko Gamishev <hehopmajieh@debian.bg>
+Date: Wed, 5 Feb 2020 15:00:25 +0200
+Subject: arm:dts:sun5i-a13-olinuxino-micro add panel lcd-olinuxino-4.3
+
+---
+ arch/arm/boot/dts/allwinner/sun5i-a13-olinuxino-micro.dts | 62 +++++++++-
+ 1 file changed, 60 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun5i-a13-olinuxino-micro.dts b/arch/arm/boot/dts/allwinner/sun5i-a13-olinuxino-micro.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/allwinner/sun5i-a13-olinuxino-micro.dts
++++ b/arch/arm/boot/dts/allwinner/sun5i-a13-olinuxino-micro.dts
+@@ -44,7 +44,7 @@
+ /dts-v1/;
+ #include "sun5i-a13.dtsi"
+ #include "sunxi-common-regulators.dtsi"
+-
++#include <dt-bindings/pwm/pwm.h>
+ #include <dt-bindings/gpio/gpio.h>
+ 
+ / {
+@@ -70,6 +70,40 @@ led {
+ 			default-state = "on";
+ 		};
+ 	};
++
++	 backlight: backlight {
++		compatible = "pwm-backlight";
++		pwms = <&pwm 0 50000 PWM_POLARITY_INVERTED>;
++                brightness-levels = <0 10 20 30 40 50 60 70 80 90 100>;
++                default-brightness-level = <8>;
++
++        };
++
++	 panel: panel {
++                compatible = "olimex,lcd-olinuxino-4.3";
++                backlight = <&backlight>;
++		enable-gpios = <&pio 1 10 GPIO_ACTIVE_HIGH>; /* PB10 */
++		pinctrl-names = "default";
++                #address-cells = <1>;
++                #size-cells = <0>;
++		port {
++			panel_input: endpoint {
++				remote-endpoint = <&tcon0_out_lcd>;
++			};
++		};
++
++                };
++
++	};
++
++
++
++&be0 {
++	status = "okay";
++};
++
++&codec {
++	status = "okay";
+ };
+ 
+ &ehci0 {
+@@ -117,10 +151,28 @@ &reg_usb0_vbus {
+ };
+ 
+ &reg_usb1_vbus {
+-	gpio = <&pio 6 11 GPIO_ACTIVE_HIGH>;
++	gpio = <&pio 2 19 GPIO_ACTIVE_HIGH>;
+ 	status = "okay";
+ };
+ 
++&tcon0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&lcd_rgb666_pins>;
++	status = "okay";
++};
++&tcon0_out {
++	tcon0_out_lcd: endpoint@0 {
++		reg = <0>;
++		remote-endpoint = <&panel_input>;
++	};
++};
++
++&pwm {
++        pinctrl-names = "default";
++        pinctrl-0 = <&pwm0_pin>;
++        status = "okay";
++};
++
+ &uart1 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart1_pg_pins>;
+@@ -139,3 +191,9 @@ &usbphy {
+ 	usb1_vbus-supply = <&reg_usb1_vbus>;
+ 	status = "okay";
+ };
++
++&rtp {
++	allwinner,ts-attached;
++	touchscreen-inverted-x;
++};
++
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun7i-a20-Disable-OOB-IRQ-for-brcm-wifi-on-Cubietruck-a.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun7i-a20-Disable-OOB-IRQ-for-brcm-wifi-on-Cubietruck-a.patch
new file mode 100644
index 000000000000..8d2a66b7ec69
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun7i-a20-Disable-OOB-IRQ-for-brcm-wifi-on-Cubietruck-a.patch
@@ -0,0 +1,99 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Sun, 23 Jan 2022 22:32:07 +0300
+Subject: arm:dts:sun7i-a20 Disable OOB IRQ for brcm-wifi on Cubietruck and
+ Banana-Pro
+
+While doing some brcmfmac driver work I needed to test this also on some
+devicetree based boards. So I fired up the good old Cubietruck and when
+that would not work a Banana Pro.
+
+With an unmodified 4.17 kernel both boards intermittently would come up
+with non working wifi with the following errors:
+
+ brcmfmac: brcmf_sdio_bus_rxctl: resumed on timeout
+ brcmfmac: brcmf_bus_started: failed: -110
+ brcmfmac: brcmf_attach: dongle is not responding: err=-110
+ brcmfmac: brcmf_sdio_firmware_callback: brcmf_attach failed
+
+They would come up this way more often then with actual working wifi,
+once this problem happens it seems to require a power-cycle to fix.
+Once things work one can safely reboot without hitting the issue.
+
+I've found that disabling OOB interrupts fixes this. This really is more
+of a workaround then a proper fix, but it makes the wifi reliable again
+and it does not have much of a downside.
+
+Using an OOB IRQ instead of the sdio-IRQ mechanism is mostly important to
+allow the MMC controller to go into runtime-suspend which is not really an
+issue on these boards since they are (usually) not battery powered.
+
+I've looked at recent brcmfmac and mmc-core changes which may explain this
+and I've not found anything. So the most likely culprit is the A20 external
+interrupt handling e.g. perhaps it is set to edge instead of level? Either
+way I do not have time to further investigate this.
+
+BugLink: https://bugs.debian.org/cgi-bin/bugreport.cgi?bug=908438
+Signed-off-by: Hans de Goede <hdegoede@redhat.com>
+---
+ arch/arm/boot/dts/allwinner/sun7i-a20-bananapro.dts  | 16 ++++++++--
+ arch/arm/boot/dts/allwinner/sun7i-a20-cubietruck.dts | 16 ++++++++--
+ 2 files changed, 26 insertions(+), 6 deletions(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-bananapro.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-bananapro.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/allwinner/sun7i-a20-bananapro.dts
++++ b/arch/arm/boot/dts/allwinner/sun7i-a20-bananapro.dts
+@@ -162,9 +162,19 @@ &mmc3 {
+ 	brcmf: wifi@1 {
+ 		reg = <1>;
+ 		compatible = "brcm,bcm4329-fmac";
+-		interrupt-parent = <&pio>;
+-		interrupts = <7 15 IRQ_TYPE_LEVEL_LOW>;
+-		interrupt-names = "host-wake";
++		/*
++		 * OOB interrupt support is broken ATM, often the first irq
++		 * does not get seen resulting in the drv probe failing with:
++		 *
++		 * brcmfmac: brcmf_sdio_bus_rxctl: resumed on timeout
++		 * brcmfmac: brcmf_bus_started: failed: -110
++		 * brcmfmac: brcmf_attach: dongle is not responding: err=-110
++		 * brcmfmac: brcmf_sdio_firmware_callback: brcmf_attach failed
++		 *
++		 * interrupt-parent = <&pio>;
++		 * interrupts = <7 15 IRQ_TYPE_LEVEL_LOW>;
++		 * interrupt-names = "host-wake";
++		 */
+ 	};
+ };
+ 
+diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-cubietruck.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/allwinner/sun7i-a20-cubietruck.dts
++++ b/arch/arm/boot/dts/allwinner/sun7i-a20-cubietruck.dts
+@@ -213,9 +213,19 @@ &mmc3 {
+ 	brcmf: wifi@1 {
+ 		reg = <1>;
+ 		compatible = "brcm,bcm4329-fmac";
+-		interrupt-parent = <&pio>;
+-		interrupts = <7 10 IRQ_TYPE_LEVEL_LOW>; /* PH10 / EINT10 */
+-		interrupt-names = "host-wake";
++		/*
++		 * OOB interrupt support is broken ATM, often the first irq
++		 * does not get seen resulting in the drv probe failing with:
++		 *
++		 * brcmfmac: brcmf_sdio_bus_rxctl: resumed on timeout
++		 * brcmfmac: brcmf_bus_started: failed: -110
++		 * brcmfmac: brcmf_attach: dongle is not responding: err=-110
++		 * brcmfmac: brcmf_sdio_firmware_callback: brcmf_attach failed
++		 *
++		 * interrupt-parent = <&pio>;
++		 * interrupts = <7 10 IRQ_TYPE_LEVEL_LOW>;
++		 * interrupt-names = "host-wake";
++		 */
+ 	};
+ };
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun7i-a20-bananapro-add-AXP209-regulators.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun7i-a20-bananapro-add-AXP209-regulators.patch
new file mode 100644
index 000000000000..f85b273cdea4
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun7i-a20-bananapro-add-AXP209-regulators.patch
@@ -0,0 +1,72 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Tue, 12 Apr 2022 21:14:36 +0300
+Subject: arm: dts: sun7i-a20-bananapro: add AXP209 regulators
+
+Author: Heiko Jehmlich <hje@jecons.de>
+Signed-off-by: Heiko Jehmlich <hje@jecons.de>
+---
+ arch/arm/boot/dts/allwinner/sun7i-a20-bananapro.dts | 50 ++++++++++
+ 1 file changed, 50 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-bananapro.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-bananapro.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/allwinner/sun7i-a20-bananapro.dts
++++ b/arch/arm/boot/dts/allwinner/sun7i-a20-bananapro.dts
+@@ -257,3 +257,53 @@ &usbphy {
+ &reg_ahci_5v {
+ 	status = "okay";
+ };
++
++#include "axp209.dtsi"
++
++&ac_power_supply {
++	status = "okay";
++};
++
++&battery_power_supply {
++	status = "okay";
++};
++
++&reg_dcdc2 {
++	regulator-always-on;
++	regulator-min-microvolt = <1000000>;
++	regulator-max-microvolt = <1450000>;
++	regulator-name = "vdd-cpu";
++};
++
++&reg_dcdc3 {
++	regulator-always-on;
++	regulator-min-microvolt = <1000000>;
++	regulator-max-microvolt = <1400000>;
++	regulator-name = "vdd-int-dll";
++};
++
++&reg_ldo1 {
++	regulator-name = "vdd-rtc";
++};
++
++&reg_ldo2 {
++	regulator-always-on;
++	regulator-min-microvolt = <3000000>;
++	regulator-max-microvolt = <3000000>;
++	regulator-name = "avcc";
++};
++
++&reg_ldo3 {
++	regulator-always-on;
++	regulator-min-microvolt = <2800000>;
++	regulator-max-microvolt = <2800000>;
++	regulator-name = "vddio-csi0";
++	regulator-ramp-delay = <1600>;
++};
++
++&reg_ldo4 {
++	regulator-always-on; /* required for SATA */
++	regulator-min-microvolt = <2800000>;
++	regulator-max-microvolt = <2800000>;
++	regulator-name = "vddio-csi1";
++};
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun7i-a20-bananapro-add-hdmi-connector-de.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun7i-a20-bananapro-add-hdmi-connector-de.patch
new file mode 100644
index 000000000000..b0fa237fb46d
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun7i-a20-bananapro-add-hdmi-connector-de.patch
@@ -0,0 +1,78 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Fri, 28 Jan 2022 15:15:19 +0300
+Subject: arm:dts: sun7i-a20-bananapro add hdmi-connector, de
+
+---
+ arch/arm/boot/dts/allwinner/sun7i-a20-bananapro.dts | 30 ++++++++++
+ 1 file changed, 30 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-bananapro.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-bananapro.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/allwinner/sun7i-a20-bananapro.dts
++++ b/arch/arm/boot/dts/allwinner/sun7i-a20-bananapro.dts
+@@ -60,6 +60,17 @@ chosen {
+ 		stdout-path = "serial0:115200n8";
+ 	};
+ 
++	hdmi-connector {
++		compatible = "hdmi-connector";
++		type = "a";
++
++		port {
++			hdmi_con_in: endpoint {
++				remote-endpoint = <&hdmi_out_con>;
++			};
++		};
++	};
++
+ 	leds {
+ 		compatible = "gpio-leds";
+ 
+@@ -91,6 +102,7 @@ reg_gmac_3v3: gmac-3v3 {
+ };
+ 
+ &ahci {
++	target-supply = <&reg_ahci_5v>;
+ 	status = "okay";
+ };
+ 
+@@ -98,6 +110,10 @@ &codec {
+ 	status = "okay";
+ };
+ 
++&de {
++	status = "okay";
++};
++
+ &ehci0 {
+ 	status = "okay";
+ };
+@@ -115,6 +131,16 @@ &gmac {
+ 	status = "okay";
+ };
+ 
++&hdmi {
++	status = "okay";
++};
++
++&hdmi_out {
++	hdmi_out_con: endpoint {
++		remote-endpoint = <&hdmi_con_in>;
++	};
++};
++
+ &i2c0 {
+ 	status = "okay";
+ 
+@@ -227,3 +253,7 @@ &usbphy {
+ 	usb2_vbus-supply = <&reg_usb2_vbus>;
+ 	status = "okay";
+ };
++
++&reg_ahci_5v {
++	status = "okay";
++};
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun7i-a20-cubietruck-add-alias-uart2.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun7i-a20-cubietruck-add-alias-uart2.patch
new file mode 100644
index 000000000000..4723018cd027
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun7i-a20-cubietruck-add-alias-uart2.patch
@@ -0,0 +1,24 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Fri, 28 Jan 2022 11:38:08 +0300
+Subject: arm:dts: sun7i-a20-cubietruck add alias uart2
+
+---
+ arch/arm/boot/dts/allwinner/sun7i-a20-cubietruck.dts | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-cubietruck.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/allwinner/sun7i-a20-cubietruck.dts
++++ b/arch/arm/boot/dts/allwinner/sun7i-a20-cubietruck.dts
+@@ -55,6 +55,7 @@ / {
+ 
+ 	aliases {
+ 		serial0 = &uart0;
++		serial2 = &uart2;
+ 	};
+ 
+ 	chosen {
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun7i-a20-olimex-som-204-evb-olinuxino-micro-decrease-d.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun7i-a20-olimex-som-204-evb-olinuxino-micro-decrease-d.patch
new file mode 100644
index 000000000000..b0a0cd3ba38a
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun7i-a20-olimex-som-204-evb-olinuxino-micro-decrease-d.patch
@@ -0,0 +1,55 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Stefan Saraev <stefan@saraev.ca>
+Date: Wed, 24 Jun 2020 20:53:36 +0300
+Subject: arm:dts:sun7i-a20: olimex-som(204)-evb,olinuxino-micro decrease dcdc2
+ min voltage
+
+fixes some kernel crashes
+---
+ arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som-evb.dts    | 2 +-
+ arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som204-evb.dts | 2 +-
+ arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-micro.dts   | 2 +-
+ 3 files changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som-evb.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som-evb.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som-evb.dts
++++ b/arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som-evb.dts
+@@ -247,7 +247,7 @@ &reg_ahci_5v {
+ 
+ &reg_dcdc2 {
+ 	regulator-always-on;
+-	regulator-min-microvolt = <1000000>;
++	regulator-min-microvolt = <1300000>;
+ 	regulator-max-microvolt = <1400000>;
+ 	regulator-name = "vdd-cpu";
+ };
+diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som204-evb.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som204-evb.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som204-evb.dts
++++ b/arch/arm/boot/dts/allwinner/sun7i-a20-olimex-som204-evb.dts
+@@ -218,7 +218,7 @@ &reg_ahci_5v {
+ 
+ &reg_dcdc2 {
+ 	regulator-always-on;
+-	regulator-min-microvolt = <1000000>;
++	regulator-min-microvolt = <1300000>;
+ 	regulator-max-microvolt = <1400000>;
+ 	regulator-name = "vdd-cpu";
+ };
+diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-micro.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-micro.dts
++++ b/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-micro.dts
+@@ -268,7 +268,7 @@ &battery_power_supply {
+ 
+ &reg_dcdc2 {
+ 	regulator-always-on;
+-	regulator-min-microvolt = <1000000>;
++	regulator-min-microvolt = <1300000>;
+ 	regulator-max-microvolt = <1400000>;
+ 	regulator-name = "vdd-cpu";
+ };
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun7i-a20-olinuxino-lime2-enable-audio-codec.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun7i-a20-olinuxino-lime2-enable-audio-codec.patch
new file mode 100644
index 000000000000..7b16b96b2604
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun7i-a20-olinuxino-lime2-enable-audio-codec.patch
@@ -0,0 +1,27 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Stefan Saraev <stefan@saraev.ca>
+Date: Wed, 3 Jun 2020 13:49:44 +0300
+Subject: arm:dts:sun7i-a20-olinuxino-lime2 enable audio codec
+
+---
+ arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-lime2.dts | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-lime2.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-lime2.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-lime2.dts
++++ b/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-lime2.dts
+@@ -96,6 +96,10 @@ &ahci {
+ 	status = "okay";
+ };
+ 
++&codec {
++        status = "okay";
++};
++
+ &de {
+ 	status = "okay";
+ };
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun7i-a20-olinuxino-lime2-enable-ldo3-always-on.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun7i-a20-olinuxino-lime2-enable-ldo3-always-on.patch
new file mode 100644
index 000000000000..f09de647d7a0
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun7i-a20-olinuxino-lime2-enable-ldo3-always-on.patch
@@ -0,0 +1,28 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: hehopmajieh <hehopmajieh@debian.bg>
+Date: Tue, 16 Jun 2020 15:40:59 +0300
+Subject: arm:dts:sun7i-a20-olinuxino-lime2 enable ldo3 always-on
+
+---
+ arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-lime2.dts | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-lime2.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-lime2.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-lime2.dts
++++ b/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-lime2.dts
+@@ -237,10 +237,10 @@ &reg_ldo2 {
+ };
+ 
+ &reg_ldo3 {
++	regulator-always-on;
+ 	regulator-min-microvolt = <2800000>;
+ 	regulator-max-microvolt = <2800000>;
+ 	regulator-name = "vddio-csi0";
+-	regulator-soft-start;
+ 	regulator-ramp-delay = <1600>;
+ };
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun7i-a20-olinuxino-micro-emmc-Add-vqmmc-node.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun7i-a20-olinuxino-micro-emmc-Add-vqmmc-node.patch
new file mode 100644
index 000000000000..1754ccffa79b
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun7i-a20-olinuxino-micro-emmc-Add-vqmmc-node.patch
@@ -0,0 +1,24 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: hehopmajieh <hehopmajieh@debian.bg>
+Date: Tue, 14 Apr 2020 10:28:16 +0300
+Subject: arm:dts:sun7i-a20-olinuxino-micro-emmc Add vqmmc node
+
+---
+ arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-micro-emmc.dts | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-micro-emmc.dts b/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-micro-emmc.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-micro-emmc.dts
++++ b/arch/arm/boot/dts/allwinner/sun7i-a20-olinuxino-micro-emmc.dts
+@@ -55,6 +55,7 @@ mmc2_pwrseq: pwrseq {
+ 
+ &mmc2 {
+ 	vmmc-supply = <&reg_vcc3v3>;
++	vqmmc-supply = <&reg_vcc3v3>;
+ 	bus-width = <4>;
+ 	non-removable;
+ 	mmc-pwrseq = <&mmc2_pwrseq>;
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun8i-h2-plus-orangepi-zero-fix-usb_otg-dr_mode.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun8i-h2-plus-orangepi-zero-fix-usb_otg-dr_mode.patch
new file mode 100644
index 000000000000..6eebf83de7bb
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun8i-h2-plus-orangepi-zero-fix-usb_otg-dr_mode.patch
@@ -0,0 +1,25 @@
+From 2f8b8f221f69c044f5d8821025c60ae76cce2bfc Mon Sep 17 00:00:00 2001
+From: Your Name <you@example.com>
+Date: Fri, 10 Jan 2025 20:56:39 +0300
+Subject: arm: dts: sun8i-h2-plus-orangepi-zero: fix usb_otg dr_mode
+
+---
+ arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-zero.dts | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-zero.dts
+index 1bb54edb00ce..f5c0e103b748 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-zero.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-zero.dts
+@@ -203,7 +203,7 @@ &uart2 {
+ };
+ 
+ &usb_otg {
+-	dr_mode = "peripheral";
++	dr_mode = "otg";
+ 	status = "okay";
+ };
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun8i-h2-plus-orangepi-zero-fix-xradio-interrupt.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun8i-h2-plus-orangepi-zero-fix-xradio-interrupt.patch
new file mode 100644
index 000000000000..b370772a9c05
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun8i-h2-plus-orangepi-zero-fix-xradio-interrupt.patch
@@ -0,0 +1,35 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Mon, 7 Feb 2022 19:15:17 +0300
+Subject: arm:dts: sun8i-h2-plus-orangepi-zero fix xradio interrupt
+
+---
+ arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-zero.dts | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-zero.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-zero.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-zero.dts
+@@ -49,6 +49,7 @@
+ 
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/input/input.h>
++#include <dt-bindings/pinctrl/sun4i-a10.h>
+ 
+ / {
+ 	model = "Xunlong Orange Pi Zero";
+@@ -151,6 +152,10 @@ &mmc1 {
+ 	 */
+ 	xr819: wifi@1 {
+ 		reg = <1>;
++		compatible = "xradio,xr819";
++		interrupt-parent = <&pio>;
++		interrupts = <6 10 IRQ_TYPE_EDGE_RISING>;
++		interrupt-names = "host-wake";
+ 	};
+ };
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun8i-h3-add-thermal-zones.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun8i-h3-add-thermal-zones.patch
new file mode 100644
index 000000000000..30018b3a9748
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun8i-h3-add-thermal-zones.patch
@@ -0,0 +1,104 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Wed, 2 Feb 2022 21:34:48 +0300
+Subject: arm:dts:sun8i-h3 add thermal zones
+
+---
+ arch/arm/boot/dts/allwinner/sun8i-h3.dtsi | 68 ++++++++--
+ 1 file changed, 55 insertions(+), 13 deletions(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi b/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi
+@@ -297,32 +297,74 @@ ths: thermal-sensor@1c25000 {
+ 	};
+ 
+ 	thermal-zones {
+-		cpu_thermal: cpu-thermal {
+-			polling-delay-passive = <0>;
+-			polling-delay = <0>;
++		cpu_thermal {
++			/* milliseconds */
++			polling-delay-passive = <250>;
++			polling-delay = <1000>;
+ 			thermal-sensors = <&ths>;
+ 
+ 			trips {
+-				cpu_hot_trip: cpu-hot {
++				cpu_warm: cpu_warm {
++					temperature = <75000>;
++					hysteresis = <2000>;
++					type = "passive";
++				};
++
++				cpu_hot_pre: cpu_hot_pre {
+ 					temperature = <80000>;
+ 					hysteresis = <2000>;
+ 					type = "passive";
+ 				};
+ 
+-				cpu_very_hot_trip: cpu-very-hot {
+-					temperature = <100000>;
+-					hysteresis = <0>;
++				cpu_hot: cpu_hot {
++					temperature = <85000>;
++					hysteresis = <2000>;
++					type = "passive";
++				};
++
++				cpu_very_hot_pre: cpu_very_hot_pre {
++					temperature = <90000>;
++					hysteresis = <2000>;
++					type = "passive";
++				};
++
++				cpu_very_hot: cpu_very_hot {
++					temperature = <95000>;
++					hysteresis = <2000>;
++					type = "passive";
++				};
++
++				cpu_crit: cpu_crit {
++					temperature = <105000>;
++					hysteresis = <2000>;
+ 					type = "critical";
+ 				};
+ 			};
+ 
+ 			cooling-maps {
+-				cpu-hot-limit {
+-					trip = <&cpu_hot_trip>;
+-					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+-							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+-							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+-							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
++				cpu_warm_limit_cpu {
++					trip = <&cpu_warm>;
++					cooling-device = <&cpu0 THERMAL_NO_LIMIT 2>;
++				};
++
++				cpu_hot_pre_limit_cpu {
++					trip = <&cpu_hot_pre>;
++					cooling-device = <&cpu0 2 3>;
++				};
++
++				cpu_hot_limit_cpu {
++					trip = <&cpu_hot>;
++					cooling-device = <&cpu0 3 4>;
++				};
++
++				cpu_very_hot_pre_limit_cpu {
++					trip = <&cpu_very_hot_pre>;
++					cooling-device = <&cpu0 5 6>;
++				};
++
++				cpu_very_hot_limit_cpu {
++					trip = <&cpu_very_hot>;
++					cooling-device = <&cpu0 7 THERMAL_NO_LIMIT>;
+ 				};
+ 			};
+ 		};
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun8i-h3-bananapi-m2-plus-add-wifi_pwrseq.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun8i-h3-bananapi-m2-plus-add-wifi_pwrseq.patch
new file mode 100644
index 000000000000..f185b1effa09
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun8i-h3-bananapi-m2-plus-add-wifi_pwrseq.patch
@@ -0,0 +1,25 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Fri, 28 Jan 2022 15:06:34 +0300
+Subject: arm:dts:sun8i-h3-bananapi-m2-plus add wifi_pwrseq
+
+---
+ arch/arm/boot/dts/allwinner/sun8i-h3-bananapi-m2-plus.dts | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-bananapi-m2-plus.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-bananapi-m2-plus.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-bananapi-m2-plus.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-bananapi-m2-plus.dts
+@@ -48,3 +48,8 @@ / {
+ 	model = "Banana Pi BPI-M2-Plus H3";
+ 	compatible = "sinovoip,bpi-m2-plus", "allwinner,sun8i-h3";
+ };
++
++&wifi_pwrseq {
++		clocks = <&rtc 1>;
++		clock-names = "ext_clock";
++};
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun8i-h3-nanopi-add-leds-pio-pins.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun8i-h3-nanopi-add-leds-pio-pins.patch
new file mode 100644
index 000000000000..3465f150f194
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun8i-h3-nanopi-add-leds-pio-pins.patch
@@ -0,0 +1,60 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Mon, 24 Jan 2022 14:14:41 +0300
+Subject: arm:dts: sun8i-h3-nanopi add leds pio pins
+
+---
+ arch/arm/boot/dts/allwinner/sun8i-h3-nanopi.dtsi | 23 ++++++++++
+ 1 file changed, 23 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi.dtsi b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-nanopi.dtsi
+@@ -59,6 +59,8 @@ chosen {
+ 
+ 	leds {
+ 		compatible = "gpio-leds";
++		pinctrl-names = "default";
++		pinctrl-0 = <&leds_npi>, <&leds_r_npi>;
+ 
+ 		led-0 {
+ 			label = "nanopi:blue:status";
+@@ -75,6 +77,8 @@ led-1 {
+ 
+ 	gpio-keys {
+ 		compatible = "gpio-keys";
++		pinctrl-names = "default";
++		pinctrl-0 = <&sw_r_npi>;
+ 
+ 		key-0 {
+ 			label = "k1";
+@@ -100,6 +104,25 @@ &ohci3 {
+ 	status = "okay";
+ };
+ 
++&pio {
++	leds_npi: led_pins {
++		pins = "PA10";
++		function = "gpio_out";
++	};
++};
++
++&r_pio {
++	leds_r_npi: led_pins {
++		pins = "PL10";
++		function = "gpio_out";
++	};
++
++	sw_r_npi: key_pins {
++		pins = "PL3";
++		function = "gpio_in";
++	};
++};
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_pa_pins>;
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun8i-h3-orangepi-pc-plus-add-wifi_pwrseq.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun8i-h3-orangepi-pc-plus-add-wifi_pwrseq.patch
new file mode 100644
index 000000000000..88715c9113f9
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun8i-h3-orangepi-pc-plus-add-wifi_pwrseq.patch
@@ -0,0 +1,33 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Mon, 7 Feb 2022 19:01:59 +0300
+Subject: arm:dts: sun8i-h3-orangepi-pc-plus add wifi_pwrseq
+
+---
+ arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc-plus.dts | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc-plus.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc-plus.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc-plus.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc-plus.dts
+@@ -51,10 +51,16 @@ aliases {
+ 		/* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
+ 		ethernet1 = &rtl8189ftv;
+ 	};
++
++	wifi_pwrseq: wifi_pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 WIFI_EN */
++	};
+ };
+ 
+ &mmc1 {
+ 	vmmc-supply = <&reg_vcc3v3>;
++	mmc-pwrseq = <&wifi_pwrseq>;
+ 	bus-width = <4>;
+ 	non-removable;
+ 	status = "okay";
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun8i-h3-reduce-opp-microvolt-to-prevent-not-supported-.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun8i-h3-reduce-opp-microvolt-to-prevent-not-supported-.patch
new file mode 100644
index 000000000000..29cf336c8e18
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun8i-h3-reduce-opp-microvolt-to-prevent-not-supported-.patch
@@ -0,0 +1,48 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Gunjan Gupta <viraniac@gmail.com>
+Date: Mon, 10 Jul 2023 19:24:21 +0000
+Subject: arm: dts: sun8i: h3: reduce opp-microvolt to prevent not supported by
+ regulator error
+
+---
+ arch/arm/boot/dts/allwinner/sun8i-h3.dtsi | 7 ++++---
+ 1 file changed, 4 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi b/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi
+@@ -86,19 +86,19 @@ opp-1008000000 {
+ 
+ 		opp-1104000000 {
+ 			opp-hz = /bits/ 64 <1104000000>;
+-			opp-microvolt = <1320000 1320000 1320000>;
++			opp-microvolt = <1300000 1300000 1300000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+ 		opp-1200000000 {
+ 			opp-hz = /bits/ 64 <1200000000>;
+-			opp-microvolt = <1320000 1320000 1320000>;
++			opp-microvolt = <1300000 1300000 1300000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+ 		opp-1296000000 {
+ 			opp-hz = /bits/ 64 <1296000000>;
+-			opp-microvolt = <1340000 1340000 1340000>;
++			opp-microvolt = <1300000 1300000 1300000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+@@ -106,6 +106,7 @@ opp-1368000000 {
+ 			opp-hz = /bits/ 64 <1368000000>;
+ 			opp-microvolt = <1400000 1400000 1400000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
++			status = "disabled";
+ 		};
+ 	};
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun8i-r40-add-clk_out_a-fix-bananam2ultra.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun8i-r40-add-clk_out_a-fix-bananam2ultra.patch
new file mode 100644
index 000000000000..b00e21cf0769
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun8i-r40-add-clk_out_a-fix-bananam2ultra.patch
@@ -0,0 +1,40 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Fri, 28 Jan 2022 15:01:30 +0300
+Subject: arm:dts: sun8i-r40 add clk_out_a fix bananam2ultra
+
+---
+ arch/arm/boot/dts/allwinner/sun8i-r40.dtsi | 17 ++++++++++
+ 1 file changed, 17 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-r40.dtsi b/arch/arm/boot/dts/allwinner/sun8i-r40.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-r40.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-r40.dtsi
+@@ -75,6 +75,23 @@ osc32k: osc32k {
+ 			clock-accuracy = <20000>;
+ 			clock-output-names = "ext-osc32k";
+ 		};
++
++		osc24M_32k: clk@1 {
++			#clock-cells = <0>;
++			compatible = "fixed-factor-clock";
++			clock-div = <732>;
++			clock-mult = <1>;
++			clocks = <&osc24M>;
++			clock-output-names = "osc24M_32k";
++		};
++
++		clk_out_a: clk@01c201f0 {
++			#clock-cells = <0>;
++			compatible = "allwinner,sun7i-a20-out-clk";
++			reg = <0x01c201f0 0x4>;
++			clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
++			clock-output-names = "clk_out_a";
++		};
+ 	};
+ 
+ 	cpus {
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun8i-r40-bananapi-m2-ultra-add-codec-analog.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun8i-r40-bananapi-m2-ultra-add-codec-analog.patch
new file mode 100644
index 000000000000..7f5de2404063
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun8i-r40-bananapi-m2-ultra-add-codec-analog.patch
@@ -0,0 +1,63 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Tue, 25 Jan 2022 21:18:21 +0300
+Subject: arm:dts: sun8i-r40 bananapi-m2-ultra add codec analog
+
+---
+ arch/arm/boot/dts/allwinner/sun8i-r40-bananapi-m2-ultra.dts | 10 ++++++
+ arch/arm/boot/dts/allwinner/sun8i-r40.dtsi                  | 18 ++++++++++
+ 2 files changed, 28 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/allwinner/sun8i-r40-bananapi-m2-ultra.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-r40-bananapi-m2-ultra.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-r40-bananapi-m2-ultra.dts
+@@ -118,6 +118,16 @@ &cpu0 {
+ 	cpu-supply = <&reg_dcdc2>;
+ };
+ 
++&codec {
++	allwinner,audio-routing =
++		"Headphone", "HP",
++		"Headphone", "HPCOM",
++		"MIC1", "Mic",
++		"Mic", "MBIAS";
++	allwinner,codec-analog-controls = <&codec_analog>;
++	status = "okay";
++};
++
+ &de {
+ 	status = "okay";
+ };
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-r40.dtsi b/arch/arm/boot/dts/allwinner/sun8i-r40.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-r40.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-r40.dtsi
+@@ -839,6 +839,24 @@ i2s2: i2s@1c22800 {
+ 			dma-names = "rx", "tx";
+ 		};
+ 
++		codec: codec@1c22c00 {
++			#sound-dai-cells = <1>;
++			compatible = "allwinner,sun8i-h3-codec";
++			reg = <0x01c22c00 0x300>;
++			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_CODEC>;
++			clock-names = "apb", "codec";
++			resets = <&ccu RST_BUS_CODEC>;
++			dmas = <&dma 19>, <&dma 19>;
++			dma-names = "rx", "tx";
++			status = "disabled";
++		};
++
++		codec_analog: codec-analog@1c22f00 {
++			compatible = "allwinner,sun8i-a23-codec-analog";
++			reg = <0x01c22f00 0x4>;
++		};
++
+ 		ths: thermal-sensor@1c24c00 {
+ 			compatible = "allwinner,sun8i-r40-ths";
+ 			reg = <0x01c24c00 0x100>;
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun8i-v3s-s3-pinecube-enable-sound-codec.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun8i-v3s-s3-pinecube-enable-sound-codec.patch
new file mode 100644
index 000000000000..34e94f08f98a
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun8i-v3s-s3-pinecube-enable-sound-codec.patch
@@ -0,0 +1,63 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Fri, 28 Jan 2022 12:58:57 +0300
+Subject: arm:dts: sun8i-v3s/s3-pinecube enable sound codec
+
+---
+ arch/arm/boot/dts/allwinner/sun8i-s3-pinecube.dts | 14 ++++++++++
+ arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi        | 14 ++++++++++
+ 2 files changed, 28 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-s3-pinecube.dts b/arch/arm/boot/dts/allwinner/sun8i-s3-pinecube.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-s3-pinecube.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-s3-pinecube.dts
+@@ -58,6 +58,20 @@ wifi_pwrseq: pwrseq {
+ 	};
+ };
+ 
++
++&i2s0 {
++       status = "okay";
++};
++
++&codec {
++	allwinner,audio-routing =
++		"Speaker", "LINEOUT",
++		"MIC1", "Mic",
++		"Mic",  "MBIAS";
++	allwinner,pa-gpios = <&pio 6 6 GPIO_ACTIVE_HIGH>; /* PG6 */
++	status = "okay";
++};
++
+ &csi1 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&csi1_8bit_pins>;
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi b/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-v3s.dtsi
+@@ -506,6 +506,20 @@ codec_analog: codec-analog@1c23000 {
+ 			reg = <0x01c23000 0x4>;
+ 		};
+ 
++
++               i2s0: i2s@1c22000 {
++                       #sound-dai-cells = <0>;
++                       compatible = "allwinner,sun8i-h3-i2s";
++                       reg = <0x01c22000 0x400>;
++                       interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
++                       clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
++                       clock-names = "apb", "mod";
++                       dmas = <&dma 3>, <&dma 3>;
++                       resets = <&ccu RST_BUS_I2S0>; /* TODO: Areset/sun8i-v3s-ccu says this isn't available on V3s */
++                       dma-names = "rx", "tx";
++                       status = "disabled";
++               };
++
+ 		uart0: serial@1c28000 {
+ 			compatible = "snps,dw-apb-uart";
+ 			reg = <0x01c28000 0x400>;
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun9i-a80-add-thermal-sensor.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun9i-a80-add-thermal-sensor.patch
new file mode 100644
index 000000000000..7bc5ee1492b8
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun9i-a80-add-thermal-sensor.patch
@@ -0,0 +1,41 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Philipp Rossak <embed3d@gmail.com>
+Date: Sat, 27 Jan 2018 21:30:16 +0100
+Subject: arm:dts: sun9i-a80 add thermal sensor
+
+As we have gained the support for the thermal sensor in A80,
+we can now add its device nodes to the device tree.
+
+The clocks and the resets are shared between the GPADC and the THS
+sensor.
+
+Signed-off-by: Philipp Rossak <embed3d@gmail.com>
+---
+ arch/arm/boot/dts/allwinner/sun9i-a80.dtsi | 11 ++++++++++
+ 1 file changed, 11 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun9i-a80.dtsi b/arch/arm/boot/dts/allwinner/sun9i-a80.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/allwinner/sun9i-a80.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun9i-a80.dtsi
+@@ -941,6 +941,17 @@ ccu: clock@6000000 {
+ 			#reset-cells = <1>;
+ 		};
+ 
++		ths: thermal-sensor@6004C00 {
++			compatible = "allwinner,sun9i-a80-ths";
++			reg = <0x06004C00 0x100>;
++			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_GPADC>, <&ccu CLK_GPADC>;
++			clock-names = "bus", "mod";
++			resets = <&ccu RST_BUS_GPADC>;
++			#thermal-sensor-cells = <1>;
++			#io-channel-cells = <0>;
++		};
++
+ 		timer@6000c00 {
+ 			compatible = "allwinner,sun4i-a10-timer";
+ 			reg = <0x06000c00 0xa0>;
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun9i-a80-add-thermal-zone.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun9i-a80-add-thermal-zone.patch
new file mode 100644
index 000000000000..03861d7e6b0f
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sun9i-a80-add-thermal-zone.patch
@@ -0,0 +1,54 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Philipp Rossak <embed3d@gmail.com>
+Date: Sat, 27 Jan 2018 21:39:09 +0100
+Subject: arm:dts: sun9i-a80 add thermal zone
+
+This patch adds the thermal zones to the A80.
+
+Sensor 0 is located besides the big CPU, sensor 1 is located besides the
+DRAM, sensor 2 is located besides the GPU and sensor 3 is located besides
+the small CPU.
+
+Signed-off-by: Philipp Rossak <embed3d@gmail.com>
+---
+ arch/arm/boot/dts/allwinner/sun9i-a80.dtsi | 26 ++++++++++
+ 1 file changed, 26 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun9i-a80.dtsi b/arch/arm/boot/dts/allwinner/sun9i-a80.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/allwinner/sun9i-a80.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun9i-a80.dtsi
+@@ -1261,4 +1261,30 @@ r_rsb: rsb@8003400 {
+ 			#size-cells = <0>;
+ 		};
+ 	};
++
++	thermal-zones {
++		cpu0_thermal: cpu0-thermal {
++			polling-delay-passive = <1000>;
++			polling-delay = <5000>;
++			thermal-sensors = <&ths 0>;
++		};
++
++		dram_thermal: dram-thermal {
++			polling-delay-passive = <1000>;
++			polling-delay = <5000>;
++			thermal-sensors = <&ths 1>;
++		};
++
++		gpu_thermal: gpu-thermal {
++			polling-delay-passive = <1000>;
++			polling-delay = <5000>;
++			thermal-sensors = <&ths 2>;
++		};
++
++		cpu2_thermal: cpu2-thermal {
++			polling-delay-passive = <1000>;
++			polling-delay = <5000>;
++			thermal-sensors = <&ths 3>;
++		};
++	};
+ };
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sunxi-h3-h5.dtsi-add-i2s0-i2s1-pins.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sunxi-h3-h5.dtsi-add-i2s0-i2s1-pins.patch
new file mode 100644
index 000000000000..107f8a6bbb10
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sunxi-h3-h5.dtsi-add-i2s0-i2s1-pins.patch
@@ -0,0 +1,33 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Tue, 1 Feb 2022 19:43:08 +0300
+Subject: arm:dts:sunxi-h3-h5.dtsi add i2s0 i2s1 pins
+
+---
+ arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi
++++ b/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi
+@@ -463,6 +463,16 @@ i2c2_pins: i2c2-pins {
+ 				function = "i2c2";
+ 			};
+ 
++			i2s0_pins: i2s0-pins {
++				pins = "PA18", "PA19", "PA20", "PA21";
++				function = "i2s0";
++			};
++
++			i2s1_pins: i2s1-pins {
++				pins = "PG10", "PG11", "PG12", "PG13";
++				function = "i2s1";
++			};
++
+ 			mmc0_pins: mmc0-pins {
+ 				pins = "PF0", "PF1", "PF2", "PF3",
+ 				       "PF4", "PF5";
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sunxi-h3-h5.dtsi-force-mmc0-bus-width.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sunxi-h3-h5.dtsi-force-mmc0-bus-width.patch
new file mode 100644
index 000000000000..e9d4944f94c2
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-dts-sunxi-h3-h5.dtsi-force-mmc0-bus-width.patch
@@ -0,0 +1,24 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Fri, 28 Jan 2022 16:12:37 +0300
+Subject: arm:dts: sunxi-h3-h5.dtsi force mmc0 bus-width
+
+---
+ arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi
++++ b/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi
+@@ -221,6 +221,7 @@ mmc0: mmc@1c0f000 {
+ 			resets = <&ccu RST_BUS_MMC0>;
+ 			reset-names = "ahb";
+ 			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
++			bus-width = <0x4>;
+ 			status = "disabled";
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-patch-call-flush_icache-ASAP-after-writing-new-instruction.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-patch-call-flush_icache-ASAP-after-writing-new-instruction.patch
new file mode 100644
index 000000000000..2c2e4563bdfa
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm-patch-call-flush_icache-ASAP-after-writing-new-instruction.patch
@@ -0,0 +1,63 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Mikhail Iakhiaev <mikhailai@gmail.com>
+Date: Mon, 29 Jul 2024 09:50:36 -0700
+Subject: arm/patch: call flush_icache ASAP after writing new instruction.
+
+The patch moves flush_icache before the patch_unmap call.
+The change avoids the possibility of the CPU seeing
+partially-patched instructions if a function from patch_unmap
+call tree has just been patched. That HAS been observed
+in practice, leading to kernel panic or freezing in early boot:
+https://bugzilla.kernel.org/show_bug.cgi?id=219089
+Specifically, the patch_unmap invokes _raw_spin_unlock_irqrestore
+(could be non-inlined) and that function is being patched
+during the ftrace_init, so the original code would run the
+patched code BEFORE flushing the icache.
+
+Note, some arches are more careful about flushing icache early. E.g.
+arch/riscv/kernel/patch.c:
+  __patch_insn_set and __patch_insn_write call the
+  local_flush_icache_range before the patch_unmap and have an
+  explicit comment about this.
+arch/x86/kernel/alternative.c:
+  text_poke_early calls sync_core (flushes icache) before
+  local_irq_restore.
+
+Closes: https://bugzilla.kernel.org/show_bug.cgi?id=219089
+Signed-off-by: Mikhail Iakhiaev <mikhailai@gmail.com>
+
+Signed-off-by: The-going <48602507+The-going@users.noreply.github.com>
+---
+ arch/arm/kernel/patch.c | 12 +++++++---
+ 1 file changed, 9 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm/kernel/patch.c b/arch/arm/kernel/patch.c
+index 111111111111..222222222222 100644
+--- a/arch/arm/kernel/patch.c
++++ b/arch/arm/kernel/patch.c
+@@ -99,13 +99,19 @@ void __kprobes __patch_text_real(void *addr, unsigned int insn, bool remap)
+ 		size = sizeof(u32);
+ 	}
+ 
+-	if (waddr != addr) {
++	if (waddr != addr)
+ 		flush_kernel_vmap_range(waddr, twopage ? size / 2 : size);
+-		patch_unmap(FIX_TEXT_POKE0, &flags);
+-	}
+ 
+ 	flush_icache_range((uintptr_t)(addr),
+ 			   (uintptr_t)(addr) + size);
++
++	/* Can only call 'patch_unmap' after flushing dcache and icache,
++	 * because it calls 'raw_spin_unlock_irqrestore', but that may
++	 * happen to be the very function we're currently patching
++	 * (as it happens during the ftrace init).
++	 */
++	if (waddr != addr)
++		patch_unmap(FIX_TEXT_POKE0, &flags);
+ }
+ 
+ static int __kprobes patch_text_stop_machine(void *data)
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-allwinner-Add-sun50i-h618-bananapi-m4-berry-support.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-allwinner-Add-sun50i-h618-bananapi-m4-berry-support.patch
new file mode 100644
index 000000000000..ff670c4a5112
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-allwinner-Add-sun50i-h618-bananapi-m4-berry-support.patch
@@ -0,0 +1,353 @@
+From 415c6765e95f564ae3f56b202b6200ea505748bd Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Mon, 10 Feb 2025 13:34:14 +0300
+Subject: arm64: allwinner: Add sun50i-h618-bananapi-m4-berry support
+
+---
+ arch/arm64/boot/dts/allwinner/Makefile        |   1 +
+ .../arm64/boot/dts/allwinner/sun50i-h616.dtsi |   4 +-
+ .../sun50i-h618-bananapi-m4-berry.dts         | 305 ++++++++++++++++++
+ 3 files changed, 308 insertions(+), 2 deletions(-)
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h618-bananapi-m4-berry.dts
+
+diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
+index a676c57aad1d..a34f2dbcc9b4 100644
+--- a/arch/arm64/boot/dts/allwinner/Makefile
++++ b/arch/arm64/boot/dts/allwinner/Makefile
+@@ -59,6 +59,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-bigtreetech-cb1-emmc.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-bigtreetech-pi.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-orangepi-zero2.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-x96-mate.dtb
++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-bananapi-m4-berry.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-bananapi-m4-zero.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-longanpi-3h.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h618-orangepi-zero2w.dtb
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+index 004e824dfe0b..0f4587be1c0e 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+@@ -391,8 +391,8 @@ pio: pinctrl@300b000 {
+ 			ext_rgmii_pins: rgmii-pins {
+ 				pins = "PI0", "PI1", "PI2", "PI3", "PI4",
+ 				       "PI5", "PI7", "PI8", "PI9", "PI10",
+-				       "PI11", "PI12", "PI13", "PI14", "PI15",
+-				       "PI16";
++				       "PI11", "PI12", "PI13", "PI14", "PI15";
++				       /* "PI16" Managed by mdio */
+ 				function = "emac0";
+ 				drive-strength = <40>;
+ 			};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-bananapi-m4-berry.dts b/arch/arm64/boot/dts/allwinner/sun50i-h618-bananapi-m4-berry.dts
+new file mode 100644
+index 000000000000..29869f39de97
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-bananapi-m4-berry.dts
+@@ -0,0 +1,305 @@
++// SPDX-License-Identifier: (GPL-2.0+ or MIT)
++/*
++ * Copyright (C) 2020 Arm Ltd.
++ */
++
++/dts-v1/;
++
++#include "sun50i-h616.dtsi"
++#include "sun50i-h616-cpu-opp.dtsi"
++#include "axp313a.dtsi"
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/linux-event-codes.h>
++#include <dt-bindings/interrupt-controller/arm-gic.h>
++#include <dt-bindings/leds/common.h>
++
++/ {
++	model = "BananaPi M4 Berry";
++	compatible = "BiPai,bananapi-m4berry", "allwinner,sun50i-h616";
++
++	aliases {
++		ethernet0 = &emac0;
++		ethernet1 = &emac1;
++		serial0 = &uart0;
++		serial5 = &uart5;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	connector {
++		compatible = "hdmi-connector";
++		type = "d";
++
++		port {
++			hdmi_con_in: endpoint {
++				remote-endpoint = <&hdmi_out_con>;
++			};
++		};
++	};
++
++	leds: leds {
++		compatible = "gpio-leds";
++
++		led-0 {
++			label = "red_led";
++			gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>; /* PC12 */
++			linux,default-trigger = "heartbeat";
++		};
++	};
++
++	gpio-keys {
++		compatible = "gpio-keys";
++
++		key-sw3 {
++			label = "sw3";
++			linux,code = <BTN_0>;
++			gpios = <&pio 2 7 GPIO_ACTIVE_LOW>;	/* PC7 */
++		};
++	};
++
++	reg_vcc5v: vcc5v {
++		/* board wide 5V supply directly from the USB-C socket */
++		compatible = "regulator-fixed";
++		regulator-name = "vcc-5v";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		regulator-always-on;
++	};
++
++	reg_usb_vbus: regulator-usb-vbus {
++		/* separate discrete regulator for the USB ports */
++		compatible = "regulator-fixed";
++		regulator-name = "usb-vbus";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		vin-supply = <&reg_vcc5v>;
++	};
++
++	reg_vcc3v3: vcc3v3 {
++		/* SY8089 DC/DC converter */
++		compatible = "regulator-fixed";
++		regulator-name = "vcc-3v3";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		vin-supply = <&reg_dldo1>;
++		regulator-always-on;
++	};
++
++	reg_vcc1v8: vcc1v8 {
++		/* Always on 1.8V/300mA regulator for WiFi and BT IO */
++		compatible = "regulator-fixed";
++		regulator-name = "vcc-1v8";
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		regulator-always-on;
++		vin-supply = <&reg_aldo1>;
++	};
++
++	reg_gmac_3v3: gmac-3v3 {
++		compatible = "regulator-fixed";
++		regulator-name = "gmac-3v3";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		regulator-always-on;
++		vin-supply = <&reg_vcc5v>;
++	};
++
++	wifi_usb {
++		compatible = "usb-wifi";
++		status = "okay";
++		power_on_pin = <&pio 2 2 GPIO_ACTIVE_HIGH>; /* PC2 */
++	};
++
++};
++
++&cpu0 {
++	cpu-supply = <&reg_dcdc2>;
++	status = "okay";
++};
++
++&sid {
++	ephy_calibration: ephy-calibration@2c {
++		reg = <0x2c 0x2>;
++	};
++};
++
++&de {
++	status = "okay";
++};
++
++&hdmi {
++	hvcc-supply = <&reg_aldo1>;
++	status = "okay";
++};
++
++&hdmi_out {
++	hdmi_out_con: endpoint {
++		remote-endpoint = <&hdmi_con_in>;
++	};
++};
++
++&gpu {
++	mali-supply = <&reg_dcdc1>;
++	status = "okay";
++};
++
++&mmc0 {
++	vmmc-supply = <&reg_dldo1>;
++	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;	/* PF6 */
++	bus-width = <4>;
++	max-frequency = <50000000>;
++	status = "okay";
++};
++
++&mmc2 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&mmc2_pins>;
++	vmmc-supply = <&reg_dldo1>;
++	bus-width = <8>;
++	max-frequency = <150000000>;
++	non-removable;
++	cap-mmc-hw-reset;
++	status = "okay";
++};
++
++&pio {
++	vcc-pc-supply = <&reg_aldo1>;
++	vcc-pf-supply = <&reg_dldo1>;
++	vcc-pg-supply = <&reg_dldo1>;
++	vcc-ph-supply = <&reg_dldo1>;
++	vcc-pi-supply = <&reg_dldo1>;
++};
++
++&emac0 {
++	compatible = "allwinner,sun50i-h616-emac";
++	pinctrl-names = "default";
++	pinctrl-0 = <&ext_rgmii_pins>;
++	phy-mode = "rgmii";
++	phy-handle = <&ext_rgmii_phy>;
++	phy-supply = <&reg_gmac_3v3>;
++	phy-io-supply = <&reg_dldo1>;
++	allwinner,rx-delay-ps = <3100>;
++	allwinner,tx-delay-ps = <700>;
++	status = "okay";
++};
++
++&mdio0 {
++	ext_rgmii_phy: ethernet-phy@1 {
++		/* rtl8211F compatible string for mdio and phy */
++		compatible = "ethernet-phy-id001c.c916";
++		reg = <1>;
++		reset-assert-us = <20000>;
++		reset-deassert-us = <100000>;
++		reset-gpios = <&pio 8 16 GPIO_ACTIVE_LOW>;      /* PI16 */
++	};
++};
++
++&emac1 {
++	compatible = "allwinner,sunxi-gmac";
++	status = "disabled";
++};
++
++&mdio1 {
++	rmii_phy: ethernet-phy@1 {
++		compatible = "ethernet-phy-ieee802.3-c22";
++		reg = <1>;
++	};
++};
++
++&uart0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart0_ph_pins>;
++	status = "okay";
++};
++
++&usbotg {
++	/*
++	 * PHY0 pins are connected to a USB-C socket, but a role switch
++	 * is not implemented: both CC pins are pulled to GND.
++	 * The VBUS pins power the device, so a fixed peripheral mode
++	 * is the best choice.
++	 * The board can be powered via GPIOs, in this case port0 *can*
++	 * act as a host (with a cable/adapter ignoring CC), as VBUS is
++	 * then provided by the GPIOs. Any user of this setup would
++	 * need to adjust the DT accordingly: dr_mode set to "host",
++	 * enabling OHCI0 and EHCI0.
++	 */
++	dr_mode = "peripheral";
++	status = "okay";
++};
++
++&usbphy {
++	usb1_vbus-supply = <&reg_usb_vbus>;
++	status = "okay";
++};
++
++&ehci0 {
++	status = "disabled";
++};
++
++&ehci1 {
++	status = "okay";
++};
++
++&ehci2 {
++	status = "okay";
++};
++
++&ehci3 {
++	status = "okay";
++};
++
++&ohci0 {
++	status = "disabled";
++};
++
++&ohci1 {
++	status = "okay";
++};
++
++&ohci2 {
++	status = "okay";
++};
++
++&ohci3 {
++	status = "okay";
++};
++
++&ir {
++	pinctrl-names = "default";
++	pinctrl-0 = <&ir_rx_pin>;
++	status = "okay";
++};
++
++&uart5 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart5_pins>;
++	status = "disabled";
++};
++
++&codec {
++	allwinner,audio-routing =
++	        "Line Out", "LINEOUT";
++	status = "okay";
++};
++
++&ahub_dam_plat {
++	status = "okay";
++};
++
++&ahub1_plat {
++	status = "okay";
++};
++
++&ahub1_mach {
++	status = "okay";
++};
++
++/*
++&ahub_i2s2 {
++	status = "okay";
++};
++*/
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-k1-plus-device.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-k1-plus-device.patch
new file mode 100644
index 000000000000..1166ec4a2b68
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-k1-plus-device.patch
@@ -0,0 +1,429 @@
+From be8fe8faded4a25f199ba65b9990b625844c2a15 Mon Sep 17 00:00:00 2001
+From: wuweidong <625769020@qq.com>
+Date: Mon, 27 Nov 2017 10:23:51 +0800
+Subject: arm64:dts: Add sun50i-h5-nanopi-k1-plus device
+
+---
+ arch/arm64/boot/dts/allwinner/Makefile        |   1 +
+ .../allwinner/sun50i-h5-nanopi-k1-plus.dts    | 396 ++++++++++++++++++
+ 2 files changed, 397 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-k1-plus.dts
+
+diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
+index 9fd6b08ea528..b747c2b5395a 100644
+--- a/arch/arm64/boot/dts/allwinner/Makefile
++++ b/arch/arm64/boot/dts/allwinner/Makefile
+@@ -29,6 +29,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo2.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo-plus2.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-r1s-h5.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-pc2.dtb
++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-k1-plus.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-prime.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus2.dtb
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-k1-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-k1-plus.dts
+new file mode 100644
+index 000000000000..b7045a9efab5
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-k1-plus.dts
+@@ -0,0 +1,396 @@
++/*
++ * Copyright (C) 2016 ARM Ltd.
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPL or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ *  a) This file is free software; you can redistribute it and/or
++ *     modify it under the terms of the GNU General Public License as
++ *     published by the Free Software Foundation; either version 2 of the
++ *     License, or (at your option) any later version.
++ *
++ *     This file is distributed in the hope that it will be useful,
++ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *     GNU General Public License for more details.
++ *
++ * Or, alternatively,
++ *
++ *  b) Permission is hereby granted, free of charge, to any person
++ *     obtaining a copy of this software and associated documentation
++ *     files (the "Software"), to deal in the Software without
++ *     restriction, including without limitation the rights to use,
++ *     copy, modify, merge, publish, distribute, sublicense, and/or
++ *     sell copies of the Software, and to permit persons to whom the
++ *     Software is furnished to do so, subject to the following
++ *     conditions:
++ *
++ *     The above copyright notice and this permission notice shall be
++ *     included in all copies or substantial portions of the Software.
++ *
++ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ *     OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++/dts-v1/;
++#include "sun50i-h5.dtsi"
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/input.h>
++#include <dt-bindings/pinctrl/sun4i-a10.h>
++
++/ {
++	model = "FriendlyElec NanoPi K1 Plus";
++	compatible = "friendlyelec,nanopi-k1-plus", "allwinner,sun50i-h5";
++
++	reg_vcc3v3: vcc3v3 {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc3v3";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++	};
++
++	aliases {
++		ethernet0 = &emac;
++		serial0 = &uart0;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	connector {
++		compatible = "hdmi-connector";
++		type = "a";
++
++		port {
++			hdmi_con_in: endpoint {
++				remote-endpoint = <&hdmi_out_con>;
++			};
++		};
++	};
++
++	leds {
++		compatible = "gpio-leds";
++
++		status {
++			label = "nanopi:green:status";
++			gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>;
++			linux,default-trigger = "heartbeat";
++			};
++		pwr {
++			label = "nanopi:red:pwr";
++			gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
++			default-state = "on";
++		};
++
++	};
++
++	r-gpio-keys {
++		compatible = "gpio-keys";
++
++		sw4 {
++			label = "sw4";
++			linux,code = <BTN_0>;
++			gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
++		};
++	};
++
++	reg_gmac_3v3: gmac-3v3 {
++		compatible = "regulator-fixed";
++		pinctrl-names = "default";
++		pinctrl-0 = <&gmac_power_pin_nanopi>;
++		regulator-name = "gmac-3v3";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		startup-delay-us = <100000>;
++		enable-active-high;
++		gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
++	};
++
++	reg_usb0_vbus: usb0-vbus {
++		compatible = "regulator-fixed";
++		regulator-name = "usb0-vbus";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		enable-active-high;
++		gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */
++		status = "okay";
++	};
++
++	wifi_pwrseq: wifi_pwrseq {
++        compatible = "mmc-pwrseq-simple";
++        pinctrl-names = "default";
++        pinctrl-0 = <&wifi_en_npi>;
++        reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
++        post-power-on-delay-ms = <200>;
++    };
++
++	rfkill_bt {
++		compatible = "rfkill-gpio";
++		pinctrl-names = "default";
++		pinctrl-0 = <&bt_pwr_pin>;
++		reset-gpios = <&pio 6 13 GPIO_ACTIVE_HIGH>; /* PG13 */
++		clocks = <&osc32k>;
++		clock-frequency = <32768>;
++		rfkill-name = "sunxi-bt";
++		rfkill-type = "bluetooth";
++	};
++
++	pcm5102a: pcm5102a-codec {
++        #sound-dai-cells = <0>;
++        compatible = "ti,pcm5102a";
++        status = "disabled";
++    };
++};
++
++&cpu0 {
++	cpu-supply = <&reg_vdd_cpux>;
++};
++
++&codec {
++	allwinner,audio-routing =
++		"Line Out", "LINEOUT",
++		"MIC1", "Mic",
++		"Mic",  "MBIAS";
++	status = "okay";
++};
++
++&de {
++	status = "okay";
++};
++
++&ehci0 {
++	status = "okay";
++};
++
++&ehci1 {
++	status = "okay";
++};
++
++&ehci2 {
++	status = "okay";
++};
++
++&ehci3 {
++	status = "okay";
++};
++
++&external_mdio {
++	ext_rgmii_phy: ethernet-phy@1 {
++		compatible = "ethernet-phy-ieee802.3-c22";
++		reg = <0>;
++	};
++};
++
++&emac {
++	pinctrl-names = "default";
++	pinctrl-0 = <&emac_rgmii_pins>;
++	phy-supply = <&reg_gmac_3v3>;
++	phy-handle = <&ext_rgmii_phy>;
++	phy-mode = "rgmii-id";
++	local-mac-address = [ 00 00 00 00 00 00 ];
++	allwinner,leds-active-low;
++	status = "okay";
++};
++
++&ir {
++	pinctrl-names = "default";
++	pinctrl-0 = <&r_ir_rx_pin>;
++	status = "okay";
++};
++
++&mmc0 {
++	vmmc-supply = <&reg_vcc3v3>;
++	bus-width = <4>;
++	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
++	status = "okay";
++};
++
++&mmc1 {
++    vmmc-supply = <&reg_vcc3v3>;
++    vqmmc-supply = <&reg_vcc3v3>;
++    mmc-pwrseq = <&wifi_pwrseq>;
++    bus-width = <4>;
++    non-removable;
++    status = "okay";
++    brcmf: bcrmf@1 {
++        reg = <1>;
++        compatible = "brcm,bcm4329-fmac";
++    };
++};
++
++&mmc2 {
++    vmmc-supply = <&reg_vcc3v3>;
++    bus-width = <8>;
++    non-removable;
++    cap-mmc-hw-reset;
++    boot_device = <0>;
++    status = "okay";
++};
++
++&mmc2_8bit_pins {
++    /* Increase drive strength for DDR modes */
++    drive-strength = <40>;
++    /* eMMC is missing pull-ups */
++    bias-pull-up;
++};
++
++&hdmi {
++	status = "okay";
++};
++
++&hdmi_out {
++	hdmi_out_con: endpoint {
++		remote-endpoint = <&hdmi_con_in>;
++	};
++};
++
++
++&pio {
++	leds_npi: led_pins@0 {
++		pins = "PA10";
++		function = "gpio_out";
++	};
++	gmac_power_pin_nanopi: gmac_power_pin@0 {
++		pins = "PD6";
++		function = "gpio_out";
++	};
++	bt_pwr_pin: bt_pwr_pin@0 {
++		pins = "PG13";
++		function = "gpio_out";
++	};
++	spi0_cs_pins: spi0_cs_pins {
++        pins = "PC3", "PA6";
++        function = "gpio_out";
++    };
++};
++&r_pio {
++	leds_r_npi: led_pins@0 {
++		pins = "PL10";
++		function = "gpio_out";
++	};
++	vdd_cpux_r_npi: regulator_pins@0 {
++		allwinner,pins = "PL6";
++		allwinner,function = "gpio_out";
++		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
++		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
++	};
++	wifi_en_npi: wifi_en_pin {
++        pins = "PL7";
++        function = "gpio_out";
++    };
++};
++&ohci0 {
++	status = "okay";
++};
++
++&ohci1 {
++	status = "okay";
++};
++
++&ohci2 {
++	status = "okay";
++};
++
++&ohci3 {
++	status = "okay";
++};
++
++
++&r_i2c {
++	status = "okay";
++	reg_vdd_cpux: regulator@65 {
++		compatible = "silergy,sy8106a";
++		reg = <0x65>;
++		regulator-name = "vdd-cpux";
++		silergy,fixed-microvolt = <1200000>;
++		/*
++		 * The datasheet uses 1.1V as the minimum value of VDD-CPUX,
++		 * however both the Armbian DVFS table and the official one
++		 * have operating points with voltage under 1.1V, and both
++		 * DVFS table are known to work properly at the lowest
++		 * operating point.
++		 *
++		 * Use 1.0V as the minimum voltage instead.
++		 */
++		regulator-min-microvolt = <1000000>;
++		regulator-max-microvolt = <1400000>;
++		regulator-ramp-delay = <200>;
++		regulator-boot-on;
++		regulator-always-on;
++	};
++};
++
++&spi0 {
++	status = "okay";
++        spi-flash@0 {
++                #address-cells = <1>;
++                #size-cells = <0>;
++                compatible = "jedec,spi-nor";
++                reg = <0>; /* Chip select 0 */
++                spi-max-frequency = <10000000>;
++                status = "okay";
++                partitions {
++                        compatible = "fixed-partitions";
++                        #address-cells = <1>;
++                        #size-cells = <1>;
++                        partition@0 {
++                                label = "uboot";
++                                reg = <0x0 0x100000>;
++                        };
++                        partition@100000 {
++                                label = "env";
++                                reg = <0x100000 0x100000>;
++                        };
++                };
++        };
++};
++
++&uart0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart0_pa_pins>;
++	status = "okay";
++};
++
++&uart1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart1_pins>;
++	status = "disabled";
++};
++
++&uart2 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart2_pins>;
++	status = "disabled";
++};
++
++&uart3 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart3_pins>, <&uart3_rts_cts_pins>;
++	status = "okay";
++};
++&usb_otg {
++	dr_mode = "otg";
++	status = "okay";
++};
++
++&usbphy {
++	/* USB Type-A ports' VBUS is always on */
++	usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
++	usb0_vbus-supply = <&reg_usb0_vbus>;
++	status = "okay";
++};
++
++&i2s0 {
++	sound-dai = <&pcm5102a>;
++	status = "disabled";
++};
+\ No newline at end of file
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-m1-plus2-device.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-m1-plus2-device.patch
new file mode 100644
index 000000000000..dbfbefd5bd0c
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-m1-plus2-device.patch
@@ -0,0 +1,272 @@
+From eebb3d14b3c9e034531885de9b574f7b1e2f2566 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Mon, 24 Jan 2022 18:54:36 +0300
+Subject: arm64:dts: Add sun50i-h5-nanopi-m1-plus2 device
+
+---
+ arch/arm64/boot/dts/allwinner/Makefile        |   1 +
+ .../allwinner/sun50i-h5-nanopi-m1-plus2.dts   | 240 ++++++++++++++++++
+ 2 files changed, 241 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-m1-plus2.dts
+
+diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
+index f7f9463d7cb0..f80ea3d3ecec 100644
+--- a/arch/arm64/boot/dts/allwinner/Makefile
++++ b/arch/arm64/boot/dts/allwinner/Makefile
+@@ -32,6 +32,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo-core2.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-r1s-h5.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-pc2.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-k1-plus.dtb
++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-m1-plus2.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-prime.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus2.dtb
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-m1-plus2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-m1-plus2.dts
+new file mode 100644
+index 000000000000..d051382cc800
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-m1-plus2.dts
+@@ -0,0 +1,240 @@
++/*
++ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
++ * Copyright (C) 2017 Armbian
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPL or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ *  a) This file is free software; you can redistribute it and/or
++ *     modify it under the terms of the GNU General Public License as
++ *     published by the Free Software Foundation; either version 2 of the
++ *     License, or (at your option) any later version.
++ *
++ *     This file is distributed in the hope that it will be useful,
++ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *     GNU General Public License for more details.
++ *
++ * Or, alternatively,
++ *
++ *  b) Permission is hereby granted, free of charge, to any person
++ *     obtaining a copy of this software and associated documentation
++ *     files (the "Software"), to deal in the Software without
++ *     restriction, including without limitation the rights to use,
++ *     copy, modify, merge, publish, distribute, sublicense, and/or
++ *     sell copies of the Software, and to permit persons to whom the
++ *     Software is furnished to do so, subject to the following
++ *     conditions:
++ *
++ *     The above copyright notice and this permission notice shall be
++ *     included in all copies or substantial portions of the Software.
++ *
++ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ *     OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++/dts-v1/;
++#include "sun50i-h5.dtsi"
++
++#include <dt-bindings/gpio/gpio.h>
++
++/ {
++	model = "FriendlyARM Nanopi M1 Plus 2";
++	compatible = "friendlyarm,nanopi-neo2", "allwinner,sun50i-h5";
++
++	aliases {
++		ethernet0 = &emac;
++		serial0 = &uart0;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	leds {
++		compatible = "gpio-leds";
++
++		pwr {
++			label = "nanopi:green:pwr";
++			gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
++			default-state = "on";
++		};
++
++		status {
++			label = "nanopi:blue:status";
++			gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>;
++		};
++	};
++
++	reg_gmac_3v3: gmac-3v3 {
++		compatible = "regulator-fixed";
++		regulator-name = "gmac-3v3";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		startup-delay-us = <100000>;
++		enable-active-high;
++		gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
++	};
++
++	reg_vcc3v3: vcc3v3 {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc3v3";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++	};
++
++	reg_usb0_vbus: usb0-vbus {
++		compatible = "regulator-fixed";
++		regulator-name = "usb0-vbus";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		enable-active-high;
++		gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */
++		status = "okay";
++	};
++
++	wifi_pwrseq: wifi_pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
++		post-power-on-delay-ms = <50>;
++	};
++
++};
++
++&ehci0 {
++	status = "okay";
++};
++
++&ehci1 {
++	status = "okay";
++};
++
++&ehci2 {
++	status = "okay";
++};
++
++&ehci3 {
++	status = "okay";
++};
++
++&emac {
++	pinctrl-names = "default";
++	pinctrl-0 = <&emac_rgmii_pins>;
++	phy-supply = <&reg_gmac_3v3>;
++	phy-handle = <&ext_rgmii_phy>;
++	phy-mode = "rgmii";
++	status = "okay";
++};
++
++&mdio {
++	ext_rgmii_phy: ethernet-phy@7 {
++		compatible = "ethernet-phy-ieee802.3-c22";
++		reg = <7>;
++	};
++};
++
++&mmc0 {
++	vmmc-supply = <&reg_vcc3v3>;
++	bus-width = <4>;
++	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
++	status = "okay";
++};
++
++&mmc1 {
++        vmmc-supply = <&reg_vcc3v3>;
++        vqmmc-supply = <&reg_vcc3v3>;
++        mmc-pwrseq = <&wifi_pwrseq>;
++        bus-width = <4>;
++        non-removable;
++        status = "okay";
++
++        brcmf: brcmf@1 {
++                reg = <1>;
++                compatible = "brcm,bcm4329-fmac";
++                interrupt-parent = <&pio>;
++                interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 */
++                interrupt-names = "host-wake";
++                pinctrl-names = "default";
++                pinctrl-0 = <&wifi_wake>;
++        };
++};
++
++&mmc2 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&mmc2_8bit_pins>;
++	vmmc-supply = <&reg_vcc3v3>;
++	bus-width = <8>;
++	non-removable;
++	cap-mmc-hw-reset;
++	status = "okay";
++};
++
++&de {
++	status = "okay";
++};
++
++&ohci0 {
++	status = "okay";
++};
++
++&ohci1 {
++	status = "okay";
++};
++
++&ohci2 {
++	status = "okay";
++};
++
++&ohci3 {
++	status = "okay";
++};
++
++&hdmi {
++	status = "okay";
++};
++
++&mixer0 {
++	status = "okay";
++};
++
++&r_pio {
++	wifi_wake: wifi_wake@0 {
++		pins = "PL7";
++		function = "irq";
++		bias-pull-up;
++	};
++};
++
++&tcon0 {
++	status = "okay";
++};
++
++&r_i2c {
++	status = "okay";
++};
++
++&uart0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart0_pa_pins>;
++	status = "okay";
++};
++
++&usb_otg {
++	dr_mode = "peripheral";
++	status = "okay";
++};
++
++&usbphy {
++	/* USB Type-A port's VBUS is always on */
++	usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
++	usb0_vbus-supply = <&reg_usb0_vbus>;
++	status = "okay";
++};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-neo-core2-device.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-neo-core2-device.patch
new file mode 100644
index 000000000000..4ebaecc89847
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-neo-core2-device.patch
@@ -0,0 +1,242 @@
+From 760b8a23a133dbf659072784fd2f7dcb98c142dd Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Mon, 24 Jan 2022 18:43:42 +0300
+Subject: arm64:dts: Add sun50i-h5-nanopi-neo-core2 device
+
+---
+ arch/arm64/boot/dts/allwinner/Makefile        |   1 +
+ .../allwinner/sun50i-h5-nanopi-neo-core2.dts  | 210 ++++++++++++++++++
+ 2 files changed, 211 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-core2.dts
+
+diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
+index b747c2b5395a..5f535145f010 100644
+--- a/arch/arm64/boot/dts/allwinner/Makefile
++++ b/arch/arm64/boot/dts/allwinner/Makefile
+@@ -27,6 +27,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-libretech-all-h3-it.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-libretech-all-h5-cc.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo2.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo-plus2.dtb
++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo-core2.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-r1s-h5.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-pc2.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-k1-plus.dtb
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-core2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-core2.dts
+new file mode 100644
+index 000000000000..57283cc16ad9
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-core2.dts
+@@ -0,0 +1,210 @@
++/*
++ * Copyright (C) 2017 Antony Antony <antony@phenome.org>
++ * Copyright (C) 2016 ARM Ltd.
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPL or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ *  a) This file is free software; you can redistribute it and/or
++ *     modify it under the terms of the GNU General Public License as
++ *     published by the Free Software Foundation; either version 2 of the
++ *     License, or (at your option) any later version.
++ *
++ *     This file is distributed in the hope that it will be useful,
++ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *     GNU General Public License for more details.
++ *
++ * Or, alternatively,
++ *
++ *  b) Permission is hereby granted, free of charge, to any person
++ *     obtaining a copy of this software and associated documentation
++ *     files (the "Software"), to deal in the Software without
++ *     restriction, including without limitation the rights to use,
++ *     copy, modify, merge, publish, distribute, sublicense, and/or
++ *     sell copies of the Software, and to permit persons to whom the
++ *     Software is furnished to do so, subject to the following
++ *     conditions:
++ *
++ *     The above copyright notice and this permission notice shall be
++ *     included in all copies or substantial portions of the Software.
++ *
++ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ *     OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++/dts-v1/;
++#include "sun50i-h5.dtsi"
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/input.h>
++#include <dt-bindings/pinctrl/sun4i-a10.h>
++
++/ {
++	model = "FriendlyARM NanoPi NEO Core2";
++	compatible = "friendlyarm,nanopi-neo-core2", "allwinner,sun50i-h5";
++
++	aliases {
++		ethernet0 = &emac;
++		serial0 = &uart0;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	leds {
++		compatible = "gpio-leds";
++
++		pwr {
++			label = "nanopi:red:pwr";
++			gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */
++			linux,default-trigger = "default-on";
++		};
++
++		status {
++			label = "nanopi:green:status";
++			gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */
++			linux,default-trigger = "heartbeat";
++		};
++	};
++
++	reg_gmac_3v3: gmac-3v3 {
++		compatible = "regulator-fixed";
++		pinctrl-names = "default";
++		regulator-name = "gmac-3v3";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		startup-delay-us = <100000>;
++		enable-active-high;
++		gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
++	};
++
++	reg_vcc3v3: vcc3v3 {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc3v3";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++	};
++
++	wifi_pwrseq: wifi_pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		pinctrl-names = "default";
++		reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
++		post-power-on-delay-ms = <200>;
++	};
++};
++
++&cpu0 {
++	cpu-supply = <&vdd_cpux>;
++};
++
++&codec {
++	allwinner,audio-routing =
++		"Line Out", "LINEOUT",
++		"MIC1", "Mic",
++		"Mic",  "MBIAS";
++	status = "okay";
++};
++
++&ehci0 {
++	status = "okay";
++};
++
++&ehci3 {
++	status = "okay";
++};
++
++&emac {
++	pinctrl-names = "default";
++	pinctrl-0 = <&emac_rgmii_pins>;
++	phy-supply = <&reg_gmac_3v3>;
++	phy-handle = <&ext_rgmii_phy>;
++	phy-mode = "rgmii-id";
++	status = "okay";
++};
++
++&external_mdio {
++	ext_rgmii_phy: ethernet-phy@7 {
++		compatible = "ethernet-phy-ieee802.3-c22";
++		reg = <7>;
++	};
++};
++
++&mmc0 {
++	vmmc-supply = <&reg_vcc3v3>;
++	bus-width = <4>;
++	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
++	status = "okay";
++};
++
++&mmc1 {
++	vmmc-supply = <&reg_vcc3v3>;
++	vqmmc-supply = <&reg_vcc3v3>;
++	mmc-pwrseq = <&wifi_pwrseq>;
++	bus-width = <4>;
++	non-removable;
++	status = "okay";
++
++	brcmf: wifi@1 {
++		reg = <1>;
++		compatible = "brcm,bcm4329-fmac";
++	};
++};
++
++&mmc2 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&mmc2_8bit_pins>;
++	vmmc-supply = <&reg_vcc3v3>;
++	bus-width = <8>;
++	non-removable;
++	cap-mmc-hw-reset;
++	status = "okay";
++};
++
++&ohci0 {
++	status = "okay";
++};
++
++&ohci3 {
++	status = "okay";
++};
++
++&r_i2c {
++	status = "okay";
++
++	vdd_cpux: regulator@65 {
++		compatible = "silergy,sy8106a";
++		reg = <0x65>;
++		silergy,fixed-microvolt = <1000000>;
++		regulator-min-microvolt = <1000000>;
++		regulator-max-microvolt = <1400000>;
++		regulator-ramp-delay = <200>;
++		regulator-boot-on;
++		regulator-always-on;
++	};
++};
++
++&uart0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart0_pa_pins>;
++	status = "okay";
++};
++
++&usb_otg {
++	dr_mode = "otg";
++	status = "okay";
++};
++
++&usbphy {
++	/* USB Type-A ports' VBUS is always on */
++	status = "okay";
++};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-neo2-v1.1-device.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-neo2-v1.1-device.patch
new file mode 100644
index 000000000000..827ab8de48c3
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-neo2-v1.1-device.patch
@@ -0,0 +1,212 @@
+From 7990afaf4d7e858e03de98b2024cc22c9127bd6a Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Mon, 24 Jan 2022 18:49:55 +0300
+Subject: arm64:dts: Add sun50i-h5-nanopi-neo2-v1.1 device
+
+---
+ arch/arm64/boot/dts/allwinner/Makefile        |   1 +
+ .../allwinner/sun50i-h5-nanopi-neo2-v1.1.dts  | 180 ++++++++++++++++++
+ 2 files changed, 181 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2-v1.1.dts
+
+diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
+index 5f535145f010..f7f9463d7cb0 100644
+--- a/arch/arm64/boot/dts/allwinner/Makefile
++++ b/arch/arm64/boot/dts/allwinner/Makefile
+@@ -26,6 +26,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-libretech-all-h3-cc.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-libretech-all-h3-it.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-libretech-all-h5-cc.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo2.dtb
++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo2-v1.1.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo-plus2.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo-core2.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-r1s-h5.dtb
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2-v1.1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2-v1.1.dts
+new file mode 100644
+index 000000000000..06ffbbd29a93
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2-v1.1.dts
+@@ -0,0 +1,180 @@
++/*
++ * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
++ *
++ * This file is dual-licensed: you can use it either under the terms
++ * of the GPL or the X11 license, at your option. Note that this dual
++ * licensing only applies to this file, and not this project as a
++ * whole.
++ *
++ *  a) This file is free software; you can redistribute it and/or
++ *     modify it under the terms of the GNU General Public License as
++ *     published by the Free Software Foundation; either version 2 of the
++ *     License, or (at your option) any later version.
++ *
++ *     This file is distributed in the hope that it will be useful,
++ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
++ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ *     GNU General Public License for more details.
++ *
++ * Or, alternatively,
++ *
++ *  b) Permission is hereby granted, free of charge, to any person
++ *     obtaining a copy of this software and associated documentation
++ *     files (the "Software"), to deal in the Software without
++ *     restriction, including without limitation the rights to use,
++ *     copy, modify, merge, publish, distribute, sublicense, and/or
++ *     sell copies of the Software, and to permit persons to whom the
++ *     Software is furnished to do so, subject to the following
++ *     conditions:
++ *
++ *     The above copyright notice and this permission notice shall be
++ *     included in all copies or substantial portions of the Software.
++ *
++ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
++ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
++ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
++ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
++ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
++ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
++ *     OTHER DEALINGS IN THE SOFTWARE.
++ */
++
++/dts-v1/;
++#include "sun50i-h5.dtsi"
++
++#include <dt-bindings/gpio/gpio.h>
++
++/ {
++	model = "FriendlyARM NanoPi NEO 2";
++	compatible = "friendlyarm,nanopi-neo2", "allwinner,sun50i-h5";
++
++	aliases {
++		ethernet0 = &emac;
++		serial0 = &uart0;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	leds {
++		compatible = "gpio-leds";
++
++		pwr {
++			label = "nanopi:red:pwr";
++			gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */
++			linux,default-trigger = "default-on";
++		};
++
++		status {
++			label = "nanopi:green:status";
++			gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */
++			linux,default-trigger = "heartbeat";
++		};
++	};
++
++	reg_gmac_3v3: gmac-3v3 {
++		compatible = "regulator-fixed";
++		regulator-name = "gmac-3v3";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		startup-delay-us = <100000>;
++		enable-active-high;
++		gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
++	};
++
++	reg_vcc3v3: vcc3v3 {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc3v3";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++	};
++
++	vdd_cpux: gpio-regulator {
++		compatible = "regulator-gpio";
++		pinctrl-names = "default";
++		regulator-name = "vdd-cpux";
++		regulator-type = "voltage";
++		regulator-boot-on;
++		regulator-always-on;
++		regulator-min-microvolt = <1100000>;
++		regulator-max-microvolt = <1300000>;
++		regulator-ramp-delay = <50>; /* 4ms */
++		gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
++		gpios-states = <0x1>;
++		states = <1100000 0x0
++			  1300000 0x1>;
++	};
++
++	reg_usb0_vbus: usb0-vbus {
++		compatible = "regulator-fixed";
++		regulator-name = "usb0-vbus";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		enable-active-high;
++		gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */
++		status = "okay";
++	};
++};
++
++&cpu0 {
++	cpu-supply = <&vdd_cpux>;
++};
++
++&ehci0 {
++	status = "okay";
++};
++
++&ehci3 {
++	status = "okay";
++};
++
++&emac {
++	pinctrl-names = "default";
++	pinctrl-0 = <&emac_rgmii_pins>;
++	phy-supply = <&reg_gmac_3v3>;
++	phy-handle = <&ext_rgmii_phy>;
++	phy-mode = "rgmii-id";
++	status = "okay";
++};
++
++&external_mdio {
++	ext_rgmii_phy: ethernet-phy@7 {
++		compatible = "ethernet-phy-ieee802.3-c22";
++		reg = <7>;
++	};
++};
++
++&mmc0 {
++	vmmc-supply = <&reg_vcc3v3>;
++	bus-width = <4>;
++	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
++	status = "okay";
++};
++
++&ohci0 {
++	status = "okay";
++};
++
++&ohci3 {
++	status = "okay";
++};
++
++&uart0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart0_pa_pins>;
++	status = "okay";
++};
++
++&usb_otg {
++	dr_mode = "otg";
++	status = "okay";
++};
++
++&usbphy {
++	/* USB Type-A port's VBUS is always on */
++	usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
++	usb0_vbus-supply = <&reg_usb0_vbus>;
++	status = "okay";
++};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-FIXME-a64-olinuxino-add-regulator-audio-mmc.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-FIXME-a64-olinuxino-add-regulator-audio-mmc.patch
new file mode 100644
index 000000000000..9f4478dacef3
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-FIXME-a64-olinuxino-add-regulator-audio-mmc.patch
@@ -0,0 +1,99 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Mon, 24 Jan 2022 14:24:40 +0300
+Subject: arm64:dts: FIXME: a64-olinuxino add regulator audio mmc
+
+Duplicate nodes appeared as a result of patching and this needs
+to be fixed and tested on the board
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts | 46 ++++++++++
+ 1 file changed, 46 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
+@@ -52,6 +52,13 @@ reg_usb1_vbus: usb1-vbus {
+ 		status = "okay";
+ 	};
+ 
++	reg_vcc3v3: vcc3v3 {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc3v3";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++	};
++
+ 	wifi_pwrseq: pwrseq {
+ 		compatible = "mmc-pwrseq-simple";
+ 		reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
+@@ -99,6 +106,10 @@ &ehci1 {
+ 	status = "okay";
+ };
+ 
++&mixer0 {
++	status = "okay";
++};
++
+ &emac {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&rgmii_pins>;
+@@ -159,6 +170,16 @@ rtl8723bs: wifi@1 {
+ 	};
+ };
+ 
++&mmc2 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&mmc2_pins>;
++	vmmc-supply = <&reg_vcc3v3>;
++	bus-width = <8>;
++	non-removable;
++	cap-mmc-hw-reset;
++	status = "okay";
++};
++
+ &ohci0 {
+ 	status = "okay";
+ };
+@@ -184,6 +205,7 @@ &r_pio {
+ 	 */
+ };
+ 
++/* FIXME: Duplicate node */
+ &pio {
+ 	vcc-pa-supply = <&reg_dcdc1>;
+ 	vcc-pb-supply = <&reg_dcdc1>;
+@@ -365,6 +387,30 @@ &sound_hdmi {
+ 	status = "okay";
+ };
+ 
++/* FIXME: Duplicate node
++ * &sound {
++ * 	status = "okay";
++ * 	simple-audio-card,widgets = "Microphone", "Internal Microphone Left",
++ * 				    "Microphone", "Internal Microphone Right",
++ * 				    "Headphone", "Headphone Jack";
++ * 	simple-audio-card,aux-devs = <&codec_analog>;
++ * 	simple-audio-card,routing =
++ * 			"Left DAC", "AIF1 Slot 0 Left",
++ * 			"Right DAC", "AIF1 Slot 0 Right",
++ * 			"INL", "LINEOUT",
++ * 			"INR", "LINEOUT",
++ * 			"Headphone Jack", "HP",
++ * 			"AIF1 Slot 0 Left ADC", "Left ADC",
++ * 			"AIF1 Slot 0 Right ADC", "Right ADC",
++ * 			"Left ADC", "ADC",
++ * 			"Right ADC", "ADC",
++ * 			"Internal Microphone Left", "MBIAS",
++ * 			"MIC1", "Internal Microphone Left",
++ * 			"Internal Microphone Right", "HBIAS",
++ * 			"MIC2", "Internal Microphone Right";
++ * };
++ */
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_pb_pins>;
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-add-sun50i-h618-cpu-dvfs.dtsi.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-add-sun50i-h618-cpu-dvfs.dtsi.patch
new file mode 100644
index 000000000000..0f8a601a0eac
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-add-sun50i-h618-cpu-dvfs.dtsi.patch
@@ -0,0 +1,260 @@
+From 4549dc5d132a65e48e93a5ed8f2d02cf5e0ea447 Mon Sep 17 00:00:00 2001
+From: AGM1968 <AGM1968@users.noreply.github.com>
+Date: Tue, 23 May 2023 16:43:00 +0000
+Subject: arm64: dts: add sun50i-h618-cpu-dvfs.dtsi
+
+Add sun50i-h616-cpu-opp-test.dtsi for tests only.
+Its unused production for kernel v6.10.
+
+Signed-off-by: AGM1968 <AGM1968@users.noreply.github.com>
+Signed-off-by: The-going <48602507+The-going@users.noreply.github.com>
+---
+ .../allwinner/sun50i-h616-cpu-opp-test.dtsi   | 75 +++++++++++++++++++
+ .../allwinner/sun50i-h616-orangepi-zero.dtsi  |  1 +
+ .../dts/allwinner/sun50i-h618-cpu-dvfs.dtsi   | 64 ++++++++++++++++
+ .../allwinner/sun50i-h618-orangepi-zero3.dts  | 57 +-------------
+ 4 files changed, 141 insertions(+), 56 deletions(-)
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp-test.dtsi
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h618-cpu-dvfs.dtsi
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp-test.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp-test.dtsi
+new file mode 100644
+index 000000000000..36f2950367c6
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-cpu-opp-test.dtsi
+@@ -0,0 +1,75 @@
++//SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++//Testing Version 1  from: AGM1968 <AGM1968@users.noreply.github.com>
++//Noted: PLL_CPUX = 24 MHz*N/P (WIP)
++
++/ {
++	cpu_opp_table: opp-table-cpu {
++		compatible = "allwinner,sun50i-h616-operating-points";
++		nvmem-cells = <&cpu_speed_grade>;
++		opp-shared;
++ 
++		opp-480000000 {
++			clock-latency-ns = <244144>; /* 8 32k periods */
++			opp-hz = /bits/ 64 <480000000>;
++			opp-microvolt-speed0 = <820000 820000 1100000>; 
++			opp-microvolt-speed1 = <880000 880000 1100000>;
++			opp-microvolt-speed2 = <880000 880000 1100000>;
++		};
++	
++		opp-600000000 {
++			clock-latency-ns = <244144>; /* 8 32k periods */
++			opp-hz = /bits/ 64 <600000000>;
++			opp-microvolt-speed0 = <820000 820000 1100000>;
++			opp-microvolt-speed1 = <880000 880000 1100000>;
++			opp-microvolt-speed2 = <880000 880000 1100000>;
++		};
++
++		opp-792000000 {
++			clock-latency-ns = <244144>; /* 8 32k periods */
++			opp-hz = /bits/ 64 <792000000>;
++		        opp-microvolt-speed0 = <860000 860000 1100000>;
++			opp-microvolt-speed1 = <940000 940000 1100000>;
++			opp-microvolt-speed2 = <940000 940000 1100000>;
++		};
++
++		opp-1008000000 {
++			clock-latency-ns = <244144>; /* 8 32k periods */
++			opp-hz = /bits/ 64 <1008000000>;
++			opp-microvolt-speed0 = <900000 900000 1100000>;
++			opp-microvolt-speed1 = <1020000 1020000 1100000>;
++			opp-microvolt-speed2 = <1020000 1020000 1100000>;
++		};
++
++		opp-1200000000 {
++			clock-latency-ns = <244144>; /* 8 32k periods */
++			opp-hz = /bits/ 64 <1200000000>;
++			opp-microvolt-speed0 = <960000 960000 1100000>;
++			opp-microvolt-speed1 = <1100000 1100000 1100000>;
++			opp-microvolt-speed2 = <1100000 1100000 1100000>;
++		};
++
++		opp-1512000000 {
++			clock-latency-ns = <244144>; /* 8 32k periods */
++			opp-hz = /bits/ 64 <1512000000>;
++			opp-microvolt-speed0 = <1100000 1100000 1100000>;
++			opp-microvolt-speed1 = <1100000 1100000 1100000>;
++			opp-microvolt-speed2 = <1100000 1100000 1100000>;
++		};
++	};
++};
++
++&cpu0 {
++	operating-points-v2 = <&cpu_opp_table>;
++};
++ 
++&cpu1 {
++	operating-points-v2 = <&cpu_opp_table>;
++};
++ 
++&cpu2 {
++	operating-points-v2 = <&cpu_opp_table>;
++};
++ 
++&cpu3 {
++	operating-points-v2 = <&cpu_opp_table>;
++};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
+index a795087c681f..54dfaf24e75d 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
+@@ -7,6 +7,7 @@
+  */
+ 
+ #include "sun50i-h616.dtsi"
++#include "sun50i-h616-cpu-opp.dtsi"
+ 
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-cpu-dvfs.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h618-cpu-dvfs.dtsi
+new file mode 100644
+index 000000000000..0509e3fb22e2
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-cpu-dvfs.dtsi
+@@ -0,0 +1,64 @@
++
++
++&r_i2c {
++	status = "okay";
++
++	axp313: pmic@36 {
++		compatible = "x-powers,axp313a";
++		reg = <0x36>;
++		#interrupt-cells = <1>;
++		interrupt-controller;
++		interrupt-parent = <&pio>;
++		interrupts = <2 9 IRQ_TYPE_LEVEL_LOW>;	/* PC9 */
++
++		vin1-supply = <&reg_vcc5v>;
++		vin2-supply = <&reg_vcc5v>;
++		vin3-supply = <&reg_vcc5v>;
++
++		regulators {
++			/* Supplies VCC-PLL and DRAM */
++			reg_aldo1: aldo1 {
++				regulator-always-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-name = "vcc1v8";
++			};
++
++			/* Supplies VCC-IO, so needs to be always on. */
++			reg_dldo1: dldo1 {
++				regulator-always-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-name = "vcc3v3";
++			};
++
++			reg_dcdc1: dcdc1 {
++				regulator-always-on;
++				regulator-min-microvolt = <810000>;
++				regulator-max-microvolt = <990000>;
++				regulator-step-delay-us = <25>;
++				regulator-final-delay-us = <50>;
++				regulator-name = "vdd-gpu-sys";
++			};
++
++			reg_dcdc2: dcdc2 {
++				regulator-always-on;
++				regulator-min-microvolt = <500000>;
++				regulator-max-microvolt = <1100000>;
++				regulator-step-delay-us = <25>;
++				regulator-final-delay-us = <50>;
++				regulator-ramp-delay = <200>;
++				regulator-name = "vdd-cpu";
++			};
++
++			reg_dcdc3: dcdc3 {
++				regulator-always-on;
++				regulator-min-microvolt = <1100000>;
++				regulator-max-microvolt = <1100000>;
++				regulator-step-delay-us = <25>;
++				regulator-final-delay-us = <50>;
++				regulator-name = "vdd-dram";
++			};
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts
+index e1cd7572a14c..222ae63013eb 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts
+@@ -7,6 +7,7 @@
+ 
+ #include "sun50i-h616-orangepi-zero.dtsi"
+ #include "sun50i-h616-cpu-opp.dtsi"
++#include "sun50i-h618-cpu-dvfs.dtsi"
+ 
+ / {
+ 	model = "OrangePi Zero3";
+@@ -36,62 +37,6 @@ &mmc0 {
+ 	vmmc-supply = <&reg_dldo1>;
+ };
+ 
+-&r_i2c {
+-	status = "okay";
+-
+-	axp313: pmic@36 {
+-		compatible = "x-powers,axp313a";
+-		reg = <0x36>;
+-		#interrupt-cells = <1>;
+-		interrupt-controller;
+-		interrupt-parent = <&pio>;
+-		interrupts = <2 9 IRQ_TYPE_LEVEL_LOW>;	/* PC9 */
+-
+-		vin1-supply = <&reg_vcc5v>;
+-		vin2-supply = <&reg_vcc5v>;
+-		vin3-supply = <&reg_vcc5v>;
+-
+-		regulators {
+-			/* Supplies VCC-PLL, so needs to be always on. */
+-			reg_aldo1: aldo1 {
+-				regulator-always-on;
+-				regulator-min-microvolt = <1800000>;
+-				regulator-max-microvolt = <1800000>;
+-				regulator-name = "vcc1v8";
+-			};
+-
+-			/* Supplies VCC-IO, so needs to be always on. */
+-			reg_dldo1: dldo1 {
+-				regulator-always-on;
+-				regulator-min-microvolt = <3300000>;
+-				regulator-max-microvolt = <3300000>;
+-				regulator-name = "vcc3v3";
+-			};
+-
+-			reg_dcdc1: dcdc1 {
+-				regulator-always-on;
+-				regulator-min-microvolt = <810000>;
+-				regulator-max-microvolt = <990000>;
+-				regulator-name = "vdd-gpu-sys";
+-			};
+-
+-			reg_dcdc2: dcdc2 {
+-				regulator-always-on;
+-				regulator-min-microvolt = <810000>;
+-				regulator-max-microvolt = <1100000>;
+-				regulator-name = "vdd-cpu";
+-			};
+-
+-			reg_dcdc3: dcdc3 {
+-				regulator-always-on;
+-				regulator-min-microvolt = <1100000>;
+-				regulator-max-microvolt = <1100000>;
+-				regulator-name = "vdd-dram";
+-			};
+-		};
+-	};
+-};
+-
+ &pio {
+ 	vcc-pc-supply = <&reg_dldo1>;
+ 	vcc-pf-supply = <&reg_dldo1>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-allwinner-Add-axp313a.dtsi.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-allwinner-Add-axp313a.dtsi.patch
new file mode 100644
index 000000000000..10f57e68c8dc
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-allwinner-Add-axp313a.dtsi.patch
@@ -0,0 +1,83 @@
+From 1989d73c62ac37fa9130595b0543c0459f77aed5 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Sun, 9 Feb 2025 17:52:52 +0300
+Subject: [PATCH] arm64: dts: allwinner: Add axp313a.dtsi
+
+---
+ arch/arm64/boot/dts/allwinner/axp313a.dtsi | 64 ++++++++++++++++++++++
+ 1 file changed, 64 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/allwinner/axp313a.dtsi
+
+diff --git a/arch/arm64/boot/dts/allwinner/axp313a.dtsi b/arch/arm64/boot/dts/allwinner/axp313a.dtsi
+new file mode 100644
+index 000000000000..99057e975574
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/axp313a.dtsi
+@@ -0,0 +1,64 @@
++
++&r_i2c {
++	status = "okay";
++
++	axp313a: pmic@36 {
++		compatible = "x-powers,axp313a";
++		reg = <0x36>;
++		#interrupt-cells = <1>;
++		interrupt-controller;
++		interrupt-parent = <&pio>;
++
++		vin1-supply = <&reg_vcc5v>;
++		vin2-supply = <&reg_vcc5v>;
++		vin3-supply = <&reg_vcc5v>;
++
++		regulators {
++			reg_dcdc1: dcdc1 {
++				regulator-name = "vdd-gpu";
++				regulator-min-microvolt = <810000>;
++				regulator-max-microvolt = <990000>;
++				regulator-step-delay-us = <25>;
++				regulator-final-delay-us = <50>;
++				regulator-always-on;
++			};
++
++			reg_dcdc2: dcdc2 {
++				regulator-name = "vdd-cpu";
++				regulator-min-microvolt = <500000>;
++				regulator-max-microvolt = <1200000>;
++				regulator-step-delay-us = <25>;
++				regulator-final-delay-us = <50>;
++				regulator-ramp-delay = <200>;
++				regulator-always-on;
++			};
++
++			reg_dcdc3: dcdc3 {
++				regulator-name = "vcc-dram";
++				regulator-min-microvolt = <1100000>;
++				regulator-max-microvolt = <1100000>;
++				regulator-step-delay-us = <25>;
++				regulator-final-delay-us = <50>;
++				regulator-always-on;
++			};
++
++			reg_aldo1: aldo1 {
++				regulator-name = "vcc-1v8";
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-step-delay-us = <25>;
++				regulator-final-delay-us = <50>;
++				regulator-always-on;
++			};
++
++			reg_dldo1: dldo1 {
++				regulator-name = "vcc-3v3";
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-step-delay-us = <25>;
++				regulator-final-delay-us = <50>;
++				regulator-always-on;
++			};
++		};
++	};
++};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-allwinner-h6-Add-AC200-EPHY-nodes.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-allwinner-h6-Add-AC200-EPHY-nodes.patch
new file mode 100644
index 000000000000..f5b36ba00021
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-allwinner-h6-Add-AC200-EPHY-nodes.patch
@@ -0,0 +1,144 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@siol.net>
+Date: Fri, 16 Aug 2019 16:40:20 +0200
+Subject: arm64: dts: allwinner: h6: Add AC200 EPHY nodes
+
+All Allwinner H6 SoCs feature a co-packaged AC200 die, which replaces
+the integrated PHY and audio circuitry of its H3/H5 predecessors. It is
+using an internal I2C connection, but otherwise pretty much behaves as
+it would be externally connected.
+
+Since every H6 SoC contains this chip, add the required DT nodes to the
+SoC .dtsi, but keep them disabled. This is for now just covering the
+AC200 MFD parent and its EPHY child.
+Any board making use of one of the integrated PHY needs to enable it and
+connect the MAC and PHY accordingly.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 73 ++++++++++
+ 1 file changed, 73 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+@@ -24,6 +24,16 @@ aliases {
+ 		mmc2 = &mmc2;
+ 	};
+ 
++	ac200_pwm_clk: ac200_clk {
++		compatible = "pwm-clock";
++		#clock-cells = <0>;
++		clock-frequency = <24000000>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&pwm1_pin>;
++		pwms = <&pwm 1 42 0>;
++		status = "disabled";
++	};
++
+ 	cpus {
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+@@ -350,6 +360,14 @@ ths_calibration: thermal-sensor-calibration@14 {
+ 			cpu_speed_grade: cpu-speed-grade@1c {
+ 				reg = <0x1c 0x4>;
+ 			};
++
++			ephy_calib: ephy_calib@2c {
++				reg = <0x2c 0x2>;
++			};
++
++			ac200_bg: ac200_bg@30 {
++				reg = <0x30 0x2>;
++			};
+ 		};
+ 
+ 		timer@3009000 {
+@@ -405,6 +423,13 @@ ext_rgmii_pins: rgmii-pins {
+ 				drive-strength = <40>;
+ 			};
+ 
++			ext_rmii_pins: rmii_pins {
++				pins = "PA0", "PA1", "PA2", "PA3", "PA4",
++				       "PA5", "PA6", "PA7", "PA8", "PA9";
++				function = "emac";
++				drive-strength = <40>;
++			};
++
+ 			hdmi_pins: hdmi-pins {
+ 				pins = "PH8", "PH9", "PH10";
+ 				function = "hdmi";
+@@ -425,6 +450,12 @@ i2c2_pins: i2c2-pins {
+ 				function = "i2c2";
+ 			};
+ 
++			i2c3_pins: i2c3-pins {
++				pins = "PB17", "PB18";
++				function = "i2c3";
++				bias-pull-up;
++			};
++
+ 			mmc0_pins: mmc0-pins {
+ 				pins = "PF0", "PF1", "PF2", "PF3",
+ 				       "PF4", "PF5";
+@@ -452,6 +483,11 @@ mmc2_pins: mmc2-pins {
+ 				bias-pull-up;
+ 			};
+ 
++			pwm1_pin: pwm1-pin {
++				pins = "PB19";
++				function = "pwm1";
++			};
++
+ 			/omit-if-no-ref/
+ 			spi0_pins: spi0-pins {
+ 				pins = "PC0", "PC2", "PC3";
+@@ -664,6 +700,43 @@ i2c2: i2c@5002800 {
+ 			#size-cells = <0>;
+ 		};
+ 
++		i2c3: i2c@5002c00 {
++			compatible = "allwinner,sun50i-h6-i2c",
++				     "allwinner,sun6i-a31-i2c";
++			reg = <0x05002c00 0x400>;
++			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_I2C3>;
++			resets = <&ccu RST_BUS_I2C3>;
++			pinctrl-names = "default";
++			pinctrl-0 = <&i2c3_pins>;
++			clock-frequency = <100000>;
++			status = "disabled";
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			ac200: mfd@10 {
++				compatible = "x-powers,ac200";
++				reg = <0x10>;
++				clocks = <&ac200_pwm_clk>;
++				interrupt-parent = <&pio>;
++				interrupts = <1 20 IRQ_TYPE_LEVEL_LOW>;
++				interrupt-controller;
++				#interrupt-cells = <1>;
++				nvmem-cells = <&ac200_bg>;
++				nvmem-cell-names = "bandgap";
++
++				ac200_ephy_ctl: syscon {
++					compatible = "x-powers,ac200-ephy-ctl";
++					nvmem-cells = <&ephy_calib>;
++					nvmem-cell-names = "calibration";
++					#clock-cells = <0>;
++					#reset-cells = <0>;
++					phy-mode = "rmii";
++					status = "disabled";
++				};
++			};
++		};
++
+ 		spi0: spi@5010000 {
+ 			compatible = "allwinner,sun50i-h6-spi",
+ 				     "allwinner,sun8i-h3-spi";
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-allwinner-h6-add-AC200-codec-nodes.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-allwinner-h6-add-AC200-codec-nodes.patch
new file mode 100644
index 000000000000..19f738dd60e6
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-allwinner-h6-add-AC200-codec-nodes.patch
@@ -0,0 +1,87 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Thu, 1 Sep 2022 17:45:03 +0200
+Subject: arm64: dts: allwinner: h6: add AC200 codec nodes
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 42 ++++++++++
+ 1 file changed, 42 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+@@ -24,6 +24,22 @@ aliases {
+ 		mmc2 = &mmc2;
+ 	};
+ 
++	analog: analog-codec {
++		compatible = "simple-audio-card";
++		simple-audio-card,format = "i2s";
++		simple-audio-card,name = "ac200-audio";
++		simple-audio-card,mclk-fs = <512>;
++		status = "disabled";
++
++		simple-audio-card,cpu {
++			sound-dai = <&i2s3>;
++		};
++
++		simple-audio-card,codec {
++			sound-dai = <&ac200_codec>;
++		};
++	};
++
+ 	ac200_pwm_clk: ac200_clk {
+ 		compatible = "pwm-clock";
+ 		#clock-cells = <0>;
+@@ -456,6 +472,11 @@ i2c3_pins: i2c3-pins {
+ 				bias-pull-up;
+ 			};
+ 
++			i2s3_pins: i2s3-pins {
++				pins = "PB12", "PB13", "PB14", "PB15", "PB16";
++				function = "i2s3";
++			};
++
+ 			mmc0_pins: mmc0-pins {
+ 				pins = "PF0", "PF1", "PF2", "PF3",
+ 				       "PF4", "PF5";
+@@ -734,6 +755,12 @@ ac200_ephy_ctl: syscon {
+ 					phy-mode = "rmii";
+ 					status = "disabled";
+ 				};
++
++				ac200_codec: codec {
++					#sound-dai-cells = <0>;
++					compatible = "x-powers,ac200-codec";
++					status = "disabled";
++				};
+ 			};
+ 		};
+ 
+@@ -791,6 +818,21 @@ mdio: mdio {
+ 			};
+ 		};
+ 
++		i2s3: i2s@508f000 {
++			#sound-dai-cells = <0>;
++			compatible = "allwinner,sun50i-h6-i2s";
++			reg = <0x0508f000 0x1000>;
++			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_I2S3>, <&ccu CLK_I2S3>;
++			clock-names = "apb", "mod";
++			dmas = <&dma 6>, <&dma 6>;
++			resets = <&ccu RST_BUS_I2S3>;
++			dma-names = "rx", "tx";
++			pinctrl-names = "default";
++			pinctrl-0 = <&i2s3_pins>;
++			status = "disabled";
++		};
++
+ 		i2s1: i2s@5091000 {
+ 			#sound-dai-cells = <0>;
+ 			compatible = "allwinner,sun50i-h6-i2s";
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-allwinner-h6-enable-AC200-codec.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-allwinner-h6-enable-AC200-codec.patch
new file mode 100644
index 000000000000..de32907b7145
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-allwinner-h6-enable-AC200-codec.patch
@@ -0,0 +1,142 @@
+From bf158ec720514f6b714ae71cb95d5792fdbc411d Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Thu, 1 Sep 2022 17:49:28 +0200
+Subject: arm64: dts: allwinner: h6: enable AC200 codec
+
+Enable AC200 analog codec on H6 based boards where present.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ .../dts/allwinner/sun50i-h6-orangepi-3.dts    | 25 +++++++++++++++++++
+ .../boot/dts/allwinner/sun50i-h6-pine-h64.dts | 25 +++++++++++++++++++
+ .../allwinner/sun50i-h6-tanix-tx6-mini.dts    | 14 +++++++++++
+ 3 files changed, 64 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
+index 5371662e52e7..74c9e4bac60d 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
+@@ -104,6 +104,19 @@ wifi_pwrseq: wifi-pwrseq {
+ 	};
+ };
+ 
++&ac200_codec {
++	avcc-supply = <&reg_aldo2>;
++	status = "okay";
++};
++
++&ac200_pwm_clk {
++	status = "okay";
++};
++
++&analog {
++	status = "okay";
++};
++
+ &cpu0 {
+ 	cpu-supply = <&reg_dcdca>;
+ };
+@@ -133,6 +146,14 @@ &i2s1 {
+ 	status = "okay";
+ };
+ 
++&i2c3 {
++	status = "okay";
++};
++
++&i2s3 {
++	status = "okay";
++};
++
+ &hdmi {
+ 	status = "okay";
+ };
+@@ -220,6 +241,10 @@ &pio {
+ 	vcc-pg-supply = <&reg_vcc_wifi_io>;
+ };
+ 
++&pwm {
++	status = "okay";
++};
++
+ &r_ir {
+ 	status = "okay";
+ };
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
+index cb7231b386cd..e4796586dc79 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
+@@ -93,6 +93,19 @@ &dwc3 {
+ 	status = "okay";
+ };
+ 
++&ac200_codec {
++	avcc-supply = <&reg_aldo2>;
++	status = "okay";
++};
++
++&ac200_pwm_clk {
++	status = "okay";
++};
++
++&analog {
++	status = "okay";
++};
++
+ &cpu0 {
+ 	cpu-supply = <&reg_dcdca>;
+ };
+@@ -139,6 +152,14 @@ &i2s1 {
+ 	status = "okay";
+ };
+ 
++&i2c3 {
++	status = "okay";
++};
++
++&i2s3 {
++	status = "okay";
++};
++
+ &mdio {
+ 	ext_rgmii_phy: ethernet-phy@1 {
+ 		compatible = "ethernet-phy-ieee802.3-c22";
+@@ -196,6 +217,10 @@ &pio {
+ 	vcc-pg-supply = <&reg_aldo1>;
+ };
+ 
++&pwm {
++	status = "okay";
++};
++
+ &r_i2c {
+ 	status = "okay";
+ 
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6-mini.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6-mini.dts
+index 08d84160d88f..931e8b99fd93 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6-mini.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix-tx6-mini.dts
+@@ -10,6 +10,20 @@ / {
+ 	compatible = "oranth,tanix-tx6-mini", "allwinner,sun50i-h6";
+ };
+ 
++
++&ac200_codec {
++	avcc-supply = <&reg_vcc3v3>;
++	status = "okay";
++};
++
++&analog {
++	status = "okay";
++};
++
++&i2s3 {
++	status = "okay";
++};
++
+ &r_ir {
+ 	linux,rc-map-name = "rc-tanix-tx3mini";
+ };
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-allwinner-h6-tanix-enable-Ethernet.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-allwinner-h6-tanix-enable-Ethernet.patch
new file mode 100644
index 000000000000..eed6ca0c777d
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-allwinner-h6-tanix-enable-Ethernet.patch
@@ -0,0 +1,97 @@
+From 7c87d7c71b5d5982bdcf592fe12fb851c30d54de Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@siol.net>
+Date: Sat, 24 Aug 2019 01:03:05 +0200
+Subject: arm64: dts: allwinner: h6: tanix: enable Ethernet
+
+Tanix-TX6 and TX6 mini boards provide an 100MBit/s Ethernet port, which
+uses the EPHY integrated into the Allwinner H6 SoC.
+
+Enable the MAC node, plus the required AC200 nodes to allow configuring
+and enabling the integrated PHY.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+---
+ .../boot/dts/allwinner/sun50i-h6-tanix.dtsi   | 38 +++++++++++++++++++
+ 1 file changed, 38 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi
+index bb7de37c0d58..a660ef85100e 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-tanix.dtsi
+@@ -10,6 +10,7 @@
+ 
+ / {
+ 	aliases {
++		ethernet0 = &emac;
+ 		serial0 = &uart0;
+ 	};
+ 
+@@ -84,6 +85,16 @@ wifi_pwrseq: wifi-pwrseq {
+ 	};
+ };
+ 
++&ac200_ephy_ctl {
++	x-powers,led-polarity = <GPIO_ACTIVE_HIGH>;
++	phy-address = <1>;
++	status = "okay";
++};
++
++&ac200_pwm_clk {
++	status = "okay";
++};
++
+ &cpu0 {
+ 	cpu-supply = <&reg_vdd_cpu_gpu>;
+ };
+@@ -104,6 +115,14 @@ &ehci3 {
+ 	status = "okay";
+ };
+ 
++&emac {
++	pinctrl-names = "default";
++	pinctrl-0 = <&ext_rmii_pins>;
++	phy-mode = "rmii";
++	phy-handle = <&ext_rmii_phy>;
++	status = "okay";
++};
++
+ &gpu {
+ 	mali-supply = <&reg_vdd_cpu_gpu>;
+ 	status = "okay";
+@@ -119,6 +138,21 @@ hdmi_out_con: endpoint {
+ 	};
+ };
+ 
++&i2c3 {
++	status = "okay";
++};
++
++&mdio {
++	ext_rmii_phy: ethernet-phy@1 {
++		compatible = "ethernet-phy-id0044.1400",
++			     "ethernet-phy-ieee802.3-c22";
++		reg = <1>;
++		resets = <&ac200_ephy_ctl>;
++		reset-names = "phy";
++		clocks = <&ac200_ephy_ctl>;
++	};
++};
++
+ &mmc0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&mmc0_pins>;
+@@ -162,6 +196,10 @@ &pio {
+ 	vcc-pg-supply = <&reg_vcc1v8>;
+ };
+ 
++&pwm {
++	status = "okay";
++};
++
+ &r_ir {
+ 	status = "okay";
+ };
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-allwinner-h616-orangepi-zero2-Enable-expansion-board-.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-allwinner-h616-orangepi-zero2-Enable-expansion-board-.patch
new file mode 100644
index 000000000000..3e546d3b9a39
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-allwinner-h616-orangepi-zero2-Enable-expansion-board-.patch
@@ -0,0 +1,48 @@
+From 44da59a4153403368ef6f295e3ff1b0b3868e90a Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Micha=C5=82=20Dzieko=C5=84ski?=
+ <michal.dziekonski+github@gmail.com>
+Date: Sun, 28 May 2023 00:26:43 +0000
+Subject: arm64: dts: allwinner: h616 orangepi zero2: Enable expansion board
+ USB ports
+
+Signed-off-by: Michal Dziekonski <michal.dziekonski+github@gmail.com>
+---
+ .../dts/allwinner/sun50i-h616-orangepi-zero.dtsi  | 15 +++++++++++++++
+ 1 file changed, 15 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
+index b5548923b7c4..8860844a4a79 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
+@@ -72,6 +72,13 @@ &ehci1 {
+ };
+ 
+ /* USB 2 & 3 are on headers only. */
++&ehci2 {
++	status = "okay";
++};
++
++&ehci3 {
++	status = "okay";
++};
+ 
+ &emac0 {
+ 	pinctrl-names = "default";
+@@ -98,6 +105,14 @@ &ohci1 {
+ 	status = "okay";
+ };
+ 
++&ohci2 {
++	status = "okay";
++};
++
++&ohci3 {
++	status = "okay";
++};
++
+ &spi0  {
+ 	status = "okay";
+ 	pinctrl-names = "default";
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-allwinner-overlay-Add-Overlays-for-sunxi64.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-allwinner-overlay-Add-Overlays-for-sunxi64.patch
new file mode 100644
index 000000000000..24b03ffd64f9
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-allwinner-overlay-Add-Overlays-for-sunxi64.patch
@@ -0,0 +1,2471 @@
+From a5de8971554d5cd8ff1bb665d7e5c58087a7f1a8 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Wed, 2 Feb 2022 13:02:10 +0300
+Subject: arm64:dts:allwinner:overlay: Add Overlays for sunxi64
+
+---
+ arch/arm64/boot/dts/allwinner/Makefile        |   2 +
+ .../arm64/boot/dts/allwinner/overlay/Makefile |  58 ++++
+ .../overlay/README.sun50i-a64-overlays        | 196 ++++++++++++++
+ .../overlay/README.sun50i-h5-overlays         | 250 ++++++++++++++++++
+ .../overlay/sun50i-a64-fixup.scr-cmd          |  95 +++++++
+ .../allwinner/overlay/sun50i-a64-i2c0.dtso    |  32 +++
+ .../allwinner/overlay/sun50i-a64-i2c1.dtso    |  22 ++
+ .../overlay/sun50i-a64-pps-gpio.dtso          |  29 ++
+ .../overlay/sun50i-a64-spi-add-cs1.dtso       |  41 +++
+ .../overlay/sun50i-a64-spi-jedec-nor.dtso     |  34 +++
+ .../overlay/sun50i-a64-spi-spidev.dtso        |  42 +++
+ .../allwinner/overlay/sun50i-a64-uart1.dtso   |  22 ++
+ .../allwinner/overlay/sun50i-a64-uart2.dtso   |  37 +++
+ .../allwinner/overlay/sun50i-a64-uart3.dtso   |  32 +++
+ .../allwinner/overlay/sun50i-a64-uart4.dtso   |  37 +++
+ .../allwinner/overlay/sun50i-a64-w1-gpio.dtso |  29 ++
+ .../overlay/sun50i-h5-analog-codec.dtso       |  17 ++
+ .../dts/allwinner/overlay/sun50i-h5-cir.dtso  |  15 ++
+ .../allwinner/overlay/sun50i-h5-fixup.scr-cmd | 110 ++++++++
+ .../dts/allwinner/overlay/sun50i-h5-i2c0.dtso |  20 ++
+ .../dts/allwinner/overlay/sun50i-h5-i2c1.dtso |  20 ++
+ .../dts/allwinner/overlay/sun50i-h5-i2c2.dtso |  20 ++
+ .../allwinner/overlay/sun50i-h5-pps-gpio.dtso |  29 ++
+ .../dts/allwinner/overlay/sun50i-h5-pwm.dtso  |  39 +++
+ .../overlay/sun50i-h5-spdif-out.dtso          |  38 +++
+ .../overlay/sun50i-h5-spi-add-cs1.dtso        |  41 +++
+ .../overlay/sun50i-h5-spi-jedec-nor.dtso      |  42 +++
+ .../overlay/sun50i-h5-spi-spidev.dtso         |  42 +++
+ .../allwinner/overlay/sun50i-h5-uart1.dtso    |  22 ++
+ .../allwinner/overlay/sun50i-h5-uart2.dtso    |  32 +++
+ .../allwinner/overlay/sun50i-h5-uart3.dtso    |  32 +++
+ .../allwinner/overlay/sun50i-h5-usbhost0.dtso |  27 ++
+ .../allwinner/overlay/sun50i-h5-usbhost1.dtso |  27 ++
+ .../allwinner/overlay/sun50i-h5-usbhost2.dtso |  27 ++
+ .../allwinner/overlay/sun50i-h5-usbhost3.dtso |  27 ++
+ .../allwinner/overlay/sun50i-h5-w1-gpio.dtso  |  29 ++
+ .../allwinner/overlay/sun50i-h6-fixup.scr-cmd | 110 ++++++++
+ .../dts/allwinner/overlay/sun50i-h6-i2c0.dtso |  20 ++
+ .../dts/allwinner/overlay/sun50i-h6-i2c1.dtso |  20 ++
+ .../dts/allwinner/overlay/sun50i-h6-i2c2.dtso |  20 ++
+ .../allwinner/overlay/sun50i-h6-ruart.dtso    |  13 +
+ .../overlay/sun50i-h6-spi-add-cs1.dtso        |  41 +++
+ .../overlay/sun50i-h6-spi-jedec-nor.dtso      |  42 +++
+ .../overlay/sun50i-h6-spi-spidev.dtso         |  42 +++
+ .../overlay/sun50i-h6-spi-spidev1.dtso        |  30 +++
+ .../allwinner/overlay/sun50i-h6-uart1.dtso    |  22 ++
+ .../allwinner/overlay/sun50i-h6-uart2.dtso    |  32 +++
+ .../allwinner/overlay/sun50i-h6-uart3.dtso    |  32 +++
+ .../allwinner/overlay/sun50i-h6-w1-gpio.dtso  |  29 ++
+ 49 files changed, 2067 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/Makefile
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/README.sun50i-a64-overlays
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/README.sun50i-h5-overlays
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-fixup.scr-cmd
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-i2c0.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-i2c1.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-pps-gpio.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-spi-add-cs1.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-spi-jedec-nor.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-spi-spidev.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart1.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart2.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart3.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart4.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-w1-gpio.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-analog-codec.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cir.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-fixup.scr-cmd
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-i2c0.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-i2c1.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-i2c2.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-pps-gpio.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-pwm.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spdif-out.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spi-add-cs1.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spi-jedec-nor.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spi-spidev.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-uart1.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-uart2.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-uart3.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost0.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost1.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost2.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost3.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-w1-gpio.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-fixup.scr-cmd
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-i2c0.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-i2c1.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-i2c2.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-ruart.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-add-cs1.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-jedec-nor.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-spidev.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-spidev1.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-uart1.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-uart2.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-uart3.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-w1-gpio.dtso
+
+diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
+index f80ea3d3ecec..80098fa014ac 100644
+--- a/arch/arm64/boot/dts/allwinner/Makefile
++++ b/arch/arm64/boot/dts/allwinner/Makefile
+@@ -57,3 +57,5 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h700-anbernic-rg35xx-2024.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h700-anbernic-rg35xx-h.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h700-anbernic-rg35xx-plus.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h700-anbernic-rg35xx-sp.dtb
++
++subdir-y	:= $(dts-dirs) overlay
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/Makefile b/arch/arm64/boot/dts/allwinner/overlay/Makefile
+new file mode 100644
+index 000000000000..ae404a5258a9
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/Makefile
+@@ -0,0 +1,58 @@
++# SPDX-License-Identifier: GPL-2.0
++dtb-$(CONFIG_ARCH_SUNXI) += \
++	sun50i-a64-i2c0.dtbo \
++	sun50i-a64-i2c1.dtbo \
++	sun50i-a64-pps-gpio.dtbo \
++	sun50i-a64-spi-add-cs1.dtbo \
++	sun50i-a64-spi-jedec-nor.dtbo \
++	sun50i-a64-spi-spidev.dtbo \
++	sun50i-a64-uart1.dtbo \
++	sun50i-a64-uart2.dtbo \
++	sun50i-a64-uart3.dtbo \
++	sun50i-a64-uart4.dtbo \
++	sun50i-a64-w1-gpio.dtbo \
++	sun50i-h5-analog-codec.dtbo \
++	sun50i-h5-cir.dtbo \
++	sun50i-h5-i2c0.dtbo \
++	sun50i-h5-i2c1.dtbo \
++	sun50i-h5-i2c2.dtbo \
++	sun50i-h5-pps-gpio.dtbo \
++	sun50i-h5-pwm.dtbo \
++	sun50i-h5-spdif-out.dtbo \
++	sun50i-h5-spi-add-cs1.dtbo \
++	sun50i-h5-spi-jedec-nor.dtbo \
++	sun50i-h5-spi-spidev.dtbo \
++	sun50i-h5-uart1.dtbo \
++	sun50i-h5-uart2.dtbo \
++	sun50i-h5-uart3.dtbo \
++	sun50i-h5-usbhost0.dtbo \
++	sun50i-h5-usbhost1.dtbo \
++	sun50i-h5-usbhost2.dtbo \
++	sun50i-h5-usbhost3.dtbo \
++	sun50i-h5-w1-gpio.dtbo \
++	sun50i-h6-i2c0.dtbo \
++	sun50i-h6-i2c1.dtbo \
++	sun50i-h6-i2c2.dtbo \
++	sun50i-h6-ruart.dtbo \
++	sun50i-h6-spi-add-cs1.dtbo \
++	sun50i-h6-spi-jedec-nor.dtbo \
++	sun50i-h6-spi-spidev.dtbo \
++	sun50i-h6-spi-spidev1.dtbo \
++	sun50i-h6-uart1.dtbo \
++	sun50i-h6-uart2.dtbo \
++	sun50i-h6-uart3.dtbo \
++	sun50i-h6-w1-gpio.dtbo
++
++scr-$(CONFIG_ARCH_SUNXI) += \
++	sun50i-a64-fixup.scr \
++	sun50i-h5-fixup.scr \
++	sun50i-h6-fixup.scr
++
++dtbotxt-$(CONFIG_ARCH_SUNXI) += \
++	README.sun50i-a64-overlays \
++	README.sun50i-h5-overlays
++
++targets += $(dtb-y) $(scr-y) $(dtbotxt-y)
++
++always		:= $(dtb-y) $(scr-y) $(dtbotxt-y)
++clean-files	:= *.dtbo *.scr
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/README.sun50i-a64-overlays b/arch/arm64/boot/dts/allwinner/overlay/README.sun50i-a64-overlays
+new file mode 100644
+index 000000000000..cd9dbc686412
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/README.sun50i-a64-overlays
+@@ -0,0 +1,196 @@
++This document describes overlays provided in the kernel packages
++For generic Armbian overlays documentation please see
++https://docs.armbian.com/Hardware_Allwinner_overlays/
++
++### Platform:
++
++sun50i-a64 (Allwinner A64)
++
++### Platform details:
++
++Supported pin banks: PB, PC, PD, PH
++
++Both SPI controllers have only one hardware CS pin exposed,
++adding fixed software (GPIO) chip selects is possible with a separate overlay
++
++I2C controller 2 (PE14, PE15) pins are used for non-I2C CSI functions or are not available
++on supported boards, so this controller is not supported in provided overlays
++
++### Provided overlays:
++
++- i2c0
++- i2c1
++- pps-gpio
++- spi-add-cs1
++- spi-jedec-nor
++- spi-spidev
++- uart1
++- uart2
++- uart3
++- uart4
++- w1-gpio
++
++### Overlay details:
++
++### i2c0
++
++Activates TWI/I2C bus 0
++
++I2C0 pins (SCL, SDA): PH0, PH1
++
++### i2c1
++
++Activates TWI/I2C bus 1
++
++I2C1 pins (SCL, SDA): PH2, PH3
++
++### pps-gpio
++
++Activates pulse-per-second GPIO client
++
++Parameters:
++
++param_pps_pin (pin)
++	Pin PPS source is connected to
++	Optional
++	Default: PD4
++
++param_pps_falling_edge (bool)
++	Assert by falling edge
++	Optional
++	Default: 0
++	When set (to 1), assert is indicated by a falling edge
++		(instead of by a rising edge)
++
++### spi-add-cs1
++
++Adds support for using SPI chip select 1 with GPIO for both SPI controllers
++Respective GPIO will be claimed only if controller is enabled by another overlay
++This overlay is required for using chip select 1 with other SPI overlays
++
++SPI 0 pins (CS1): PB6
++SPI 1 pins (CS1): PD6
++
++### spi-jedec-nor
++
++Activates MTD support for JEDEC compatible SPI NOR flash chips on SPI bus
++supported by the kernel SPI NOR driver
++
++SPI 0 pins (MOSI, MISO, SCK, CS): PC0, PC1, PC2, PC3
++SPI 1 pins (MOSI, MISO, SCK, CS): PD2, PD3, PD1, PD0
++
++Parameters:
++
++param_spinor_spi_bus (int)
++	SPI bus to activate SPI NOR flash support on
++	Required
++	Supported values: 0, 1
++
++param_spinor_spi_cs (int)
++	SPI chip select number
++	Optional
++	Default: 0
++	Supported values: 0, 1
++	Using chip select 1 requires using "spi-add-cs1" overlay
++
++param_spinor_max_freq (int)
++	Maximum SPI frequency
++	Optional
++	Default: 1000000
++	Range: 3000 - 100000000
++
++### spi-spidev
++
++Activates SPIdev device node (/dev/spidevX.Y) for userspace SPI access,
++where X is the bus number and Y is the CS number
++
++SPI 0 pins (MOSI, MISO, SCK, CS): PC0, PC1, PC2, PC3
++SPI 1 pins (MOSI, MISO, SCK, CS): PD2, PD3, PD1, PD0
++
++Parameters:
++
++param_spidev_spi_bus (int)
++	SPI bus to activate SPIdev support on
++	Required
++	Supported values: 0, 1
++
++param_spidev_spi_cs (int)
++	SPI chip select number
++	Optional
++	Default: 0
++	Supported values: 0, 1
++	Using chip select 1 requires using "spi-add-cs1" overlay
++
++param_spidev_max_freq (int)
++	Maximum SPIdev frequency
++	Optional
++	Default: 1000000
++	Range: 3000 - 100000000
++
++### uart1
++
++Activates serial port 1 (/dev/ttyS1)
++
++UART 1 pins (TX, RX, RTS, CTS): PG6, PG7, PG8, PG9
++
++Parameters:
++
++param_uart1_rtscts (bool)
++	Enable RTS and CTS pins
++	Optional
++	Default: 0
++	Set to 1 to enable
++
++### uart2
++
++Activates serial port 2 (/dev/ttyS2)
++
++UART 2 pins (TX, RX, RTS, CTS): PB0, PB1, PB2, PB3
++
++Parameters:
++
++param_uart2_rtscts (bool)
++	Enable RTS and CTS pins
++	Optional
++	Default: 0
++	Set to 1 to enable CTS and RTS pins
++
++### uart3
++
++Activates serial port 3 (/dev/ttyS3)
++
++UART 3 pins (TX, RX): PD0, PD1
++
++### uart4
++
++Activates serial port 4 (/dev/ttyS4)
++
++UART 4 pins (TX, RX, RTS, CTS): PD2, PD3, PD4, PD5
++
++Parameters:
++
++param_uart2_rtscts (bool)
++	Enable RTS and CTS pins
++	Optional
++	Default: 0
++	Set to 1 to enable CTS and RTS pins
++
++### w1-gpio
++
++Activates 1-Wire GPIO master
++Requires external pull-up resistor on data pin
++
++Parameters:
++
++param_w1_pin (pin)
++	Data pin for 1-Wire master
++	Optional
++	Default: PD4
++
++param_w1_pin_int_pullup (bool)
++	Enable internal pull-up for the data pin
++	Optional
++	Default: 0
++	Set to 1 to enable the pull-up
++	This option should not be used with multiple devices, parasite power setup
++		or long wires -	please use external pull-up resistor instead
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/README.sun50i-h5-overlays b/arch/arm64/boot/dts/allwinner/overlay/README.sun50i-h5-overlays
+new file mode 100644
+index 000000000000..1ac7fbcf62d1
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/README.sun50i-h5-overlays
+@@ -0,0 +1,250 @@
++This document describes overlays provided in the kernel packages
++For generic Armbian overlays documentation please see
++https://docs.armbian.com/User-Guide_Allwinner_overlays/
++
++### Platform:
++
++sun50i-h5 (Allwinner H5)
++
++### Platform details:
++
++Supported pin banks: PA, PC, PD, PG
++
++Both SPI controllers have only one hardware CS pin exposed,
++adding fixed software (GPIO) chip selects is possible with a separate overlay
++
++### Provided overlays:
++
++- analog-codec
++- cir
++- i2c0
++- i2c1
++- i2c2
++- pps-gpio
++- pwm
++- spdif-out
++- spi-add-cs1
++- spi-jedec-nor
++- spi-spidev
++- uart1
++- uart2
++- uart3
++- usbhost0
++- usbhost1
++- usbhost2
++- usbhost3
++- w1-gpio
++
++### Overlay details:
++
++### analog-codec
++
++Activates SoC analog codec driver that provides Line Out and Mic In
++functionality
++
++### cir
++
++Activates CIR (Infrared remote) receiver
++
++CIR pin: PL11
++
++### i2c0
++
++Activates TWI/I2C bus 0
++
++I2C0 pins (SCL, SDA): PA11, PA12
++
++### i2c1
++
++Activates TWI/I2C bus 1
++
++I2C1 pins (SCL, SDA): PA18, PA19
++
++### i2c2
++
++Activates TWI/I2C bus 2
++
++I2C2 pins (SCL, SDA): PE12, PE13
++
++On most board this bus is wired to Camera (CSI) socket
++
++### pps-gpio
++
++Activates pulse-per-second GPIO client
++
++Parameters:
++
++param_pps_pin (pin)
++	Pin PPS source is connected to
++	Optional
++	Default: PD14
++
++param_pps_falling_edge (bool)
++	Assert by falling edge
++	Optional
++	Default: 0
++	When set (to 1), assert is indicated by a falling edge
++		(instead of by a rising edge)
++
++### pwm
++
++Activates hardware PWM controller
++
++PWM pin: PA5
++
++Pin PA5 is used as UART0 RX by default, so if this overlay is activated,
++UART0 and kernel console on ttyS0 will be disabled
++
++### spdif-out
++
++Activates SPDIF/Toslink audio output
++
++SPDIF pin: PA17
++
++### spi-add-cs1
++
++Adds support for using SPI chip select 1 with GPIO for both SPI controllers
++Respective GPIO will be claimed only if controller is enabled by another
++overlay
++This overlay is required for using chip select 1 with other SPI overlays
++Due to the u-boot limitations CS1 pin can't be customized by a parameter, but
++it can be changed by using an edited copy of this overlay
++A total of 4 chip selects can be used with custom overlays (1 HW + 3 GPIO)
++
++SPI 0 pins (CS1): PA21
++SPI 1 pins (CS1): PA10
++
++### spi-jedec-nor
++
++Activates MTD support for JEDEC compatible SPI NOR flash chips on SPI bus
++supported by the kernel SPI NOR driver
++
++SPI 0 pins (MOSI, MISO, SCK, CS): PC0, PC1, PC2, PC3
++SPI 1 pins (MOSI, MISO, SCK, CS): PA15, PA16, PA14, PA13
++
++Parameters:
++
++param_spinor_spi_bus (int)
++	SPI bus to activate SPI NOR flash support on
++	Required
++	Supported values: 0, 1
++
++param_spinor_spi_cs (int)
++	SPI chip select number
++	Optional
++	Default: 0
++	Supported values: 0, 1
++	Using chip select 1 requires using "spi-add-cs1" overlay
++
++param_spinor_max_freq (int)
++	Maximum SPI frequency
++	Optional
++	Default: 1000000
++	Range: 3000 - 100000000
++
++### spi-spidev
++
++Activates SPIdev device node (/dev/spidevX.Y) for userspace SPI access,
++where X is the bus number and Y is the CS number
++
++SPI 0 pins (MOSI, MISO, SCK, CS): PC0, PC1, PC2, PC3
++SPI 1 pins (MOSI, MISO, SCK, CS): PA15, PA16, PA14, PA13
++
++Parameters:
++
++param_spidev_spi_bus (int)
++	SPI bus to activate SPIdev support on
++	Required
++	Supported values: 0, 1
++
++param_spidev_spi_cs (int)
++	SPI chip select number
++	Optional
++	Default: 0
++	Supported values: 0, 1
++	Using chip select 1 requires using "spi-add-cs1" overlay
++
++param_spidev_max_freq (int)
++	Maximum SPIdev frequency
++	Optional
++	Default: 1000000
++	Range: 3000 - 100000000
++
++### uart1
++
++Activates serial port 1 (/dev/ttyS1)
++
++UART 1 pins (TX, RX, RTS, CTS): PG6, PG7, PG8, PG9
++
++Parameters:
++
++param_uart1_rtscts (bool)
++	Enable RTS and CTS pins
++	Optional
++	Default: 0
++	Set to 1 to enable
++
++### uart2
++
++Activates serial port 2 (/dev/ttyS2)
++
++UART 2 pins (TX, RX, RTS, CTS): PA0, PA1, PA2, PA3
++
++Parameters:
++
++param_uart2_rtscts (bool)
++	Enable RTS and CTS pins
++	Optional
++	Default: 0
++	Set to 1 to enable CTS and RTS pins
++
++### uart3
++
++Activates serial port 3 (/dev/ttyS3)
++
++UART 3 pins (TX, RX, RTS, CTS): PA13, PA14, PA15, PA16
++
++Parameters:
++
++param_uart3_rtscts (bool)
++	Enable RTS and CTS pins
++	Optional
++	Default: 0
++	Set to 1 to enable CTS and RTS pins
++
++### usbhost0
++
++Activates USB host controller 0
++
++### usbhost1
++
++Activates USB host controller 1
++
++### usbhost2
++
++Activates USB host controller 2
++
++### usbhost3
++
++Activates USB host controller 3
++
++### w1-gpio
++
++Activates 1-Wire GPIO master
++Requires an external pull-up resistor on the data pin
++or enabling the internal pull-up
++
++Parameters:
++
++param_w1_pin (pin)
++	Data pin for 1-Wire master
++	Optional
++	Default: PD14
++
++param_w1_pin_int_pullup (bool)
++	Enable internal pull-up for the data pin
++	Optional
++	Default: 0
++	Set to 1 to enable the pull-up
++	This option should not be used with multiple devices, parasite power setup
++		or long wires -	please use external pull-up resistor instead
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-fixup.scr-cmd b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-fixup.scr-cmd
+new file mode 100644
+index 000000000000..9b34c05ecf18
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-fixup.scr-cmd
+@@ -0,0 +1,95 @@
++# overlays fixup script
++# implements (or rather substitutes) overlay arguments functionality
++# using u-boot scripting, environment variables and "fdt" command
++
++# setexpr test_var ${tmp_bank} - A
++# works only for hex numbers (A-F)
++
++setenv decompose_pin 'setexpr tmp_bank sub "P(B|C|D|H)\\d+" "\\1";
++setexpr tmp_pin sub "P\\S(\\d+)" "\\1";
++test "${tmp_bank}" = "B" && setenv tmp_bank 1;
++test "${tmp_bank}" = "C" && setenv tmp_bank 2;
++test "${tmp_bank}" = "D" && setenv tmp_bank 3;
++test "${tmp_bank}" = "H" && setenv tmp_bank 7'
++
++if test -n "${param_spinor_spi_bus}"; then
++	test "${param_spinor_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c68000"
++	test "${param_spinor_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c69000"
++	fdt set /soc/${tmp_spi_path} status "okay"
++	fdt set /soc/${tmp_spi_path}/spiflash@0 status "okay"
++	if test -n "${param_spinor_max_freq}"; then
++		fdt set /soc/${tmp_spi_path}/spiflash@0 spi-max-frequency "<${param_spinor_max_freq}>"
++	fi
++	if test "${param_spinor_spi_cs}" = "1"; then
++		fdt set /soc/${tmp_spi_path}/spiflash@0 reg "<1>";
++	fi
++	env delete tmp_spi_path
++fi
++
++if test -n "${param_spidev_spi_bus}"; then
++	test "${param_spidev_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c68000"
++	test "${param_spidev_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c69000"
++	fdt set /soc/${tmp_spi_path} status "okay"
++	fdt set /soc/${tmp_spi_path}/spidev status "okay"
++	if test -n "${param_spidev_max_freq}"; then
++		fdt set /soc/${tmp_spi_path}/spidev spi-max-frequency "<${param_spidev_max_freq}>"
++	fi
++	if test "${param_spidev_spi_cs}" = "1"; then
++		fdt set /soc/${tmp_spi_path}/spidev reg "<1>";
++	fi
++fi
++
++if test -n "${param_pps_pin}"; then
++	setenv tmp_bank "${param_pps_pin}"
++	setenv tmp_pin "${param_pps_pin}"
++	run decompose_pin
++	fdt set /soc/pinctrl@1c20800/pps_pins pins "${param_pps_pin}"
++	fdt get value tmp_phandle /soc/pinctrl@1c20800 phandle
++	fdt set /pps@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>"
++	env delete tmp_pin tmp_bank tmp_phandle
++fi
++
++if test "${param_pps_falling_edge}" = "1"; then
++	fdt set /pps@0 assert-falling-edge
++fi
++
++if test -n "${param_w1_pin}"; then
++	setenv tmp_bank "${param_w1_pin}"
++	setenv tmp_pin "${param_w1_pin}"
++	run decompose_pin
++	fdt set /soc/pinctrl@1c20800/w1_pins pins "${param_w1_pin}"
++	fdt get value tmp_phandle /soc/pinctrl@1c20800 phandle
++	fdt set /onewire@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>"
++	env delete tmp_pin tmp_bank tmp_phandle
++fi
++
++if test "${param_w1_pin_int_pullup}" = "1"; then
++	fdt set /soc/pinctrl@1c20800/w1_pins bias-pull-up
++fi
++
++if test "${param_uart1_rtscts}" = "1"; then
++	fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart1-pins phandle
++	fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart1-rts-cts-pins phandle
++	fdt set /soc/serial@1c28400 pinctrl-names "default" "default"
++	fdt set /soc/serial@1c28400 pinctrl-0 "<${tmp_phandle1}>"
++	fdt set /soc/serial@1c28400 pinctrl-1 "<${tmp_phandle2}>"
++	env delete tmp_phandle1 tmp_phandle2
++fi
++
++if test "${param_uart2_rtscts}" = "1"; then
++	fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart2-pins phandle
++	fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart2-rts-cts-pins phandle
++	fdt set /soc/serial@1c28800 pinctrl-names "default" "default"
++	fdt set /soc/serial@1c28800 pinctrl-0 "<${tmp_phandle1}>"
++	fdt set /soc/serial@1c28800 pinctrl-1 "<${tmp_phandle2}>"
++	env delete tmp_phandle1 tmp_phandle2
++fi
++
++if test "${param_uart4_rtscts}" = "1"; then
++	fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart4-pins phandle
++	fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart4-rts-cts-pins phandle
++	fdt set /soc/serial@1c29000 pinctrl-names "default" "default"
++	fdt set /soc/serial@1c29000 pinctrl-0 "<${tmp_phandle1}>"
++	fdt set /soc/serial@1c29000 pinctrl-1 "<${tmp_phandle2}>"
++	env delete tmp_phandle1 tmp_phandle2
++fi
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-i2c0.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-i2c0.dtso
+new file mode 100644
+index 000000000000..37bdb2c2fae3
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-i2c0.dtso
+@@ -0,0 +1,32 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-a64";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			i2c0 = "/soc/i2c@1c2ac00";
++		};
++	};
++
++	fragment@1 {
++		target = <&pio>;
++		__overlay__ {
++			i2c0_pins: i2c0_pins {
++				pins = "PH0", "PH1";
++				function = "i2c0";
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&i2c0>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&i2c0_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-i2c1.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-i2c1.dtso
+new file mode 100644
+index 000000000000..b2483c9cd7b2
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-i2c1.dtso
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-a64";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			i2c1 = "/soc/i2c@1c2b000";
++		};
++	};
++
++	fragment@1 {
++		target = <&i2c1>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&i2c1_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-pps-gpio.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-pps-gpio.dtso
+new file mode 100644
+index 000000000000..5fa161c4718e
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-pps-gpio.dtso
+@@ -0,0 +1,29 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-a64";
++
++	fragment@0 {
++		target = <&pio>;
++		__overlay__ {
++			pps_pins: pps_pins {
++				pins = "PD4";
++				function = "gpio_in";
++			};
++		};
++	};
++
++	fragment@1 {
++		target-path = "/";
++		__overlay__ {
++			pps@0 {
++				compatible = "pps-gpio";
++				pinctrl-names = "default";
++				pinctrl-0 = <&pps_pins>;
++				gpios = <&pio 3 4 0>; /* PD4 */
++				status = "okay";
++			};
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-spi-add-cs1.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-spi-add-cs1.dtso
+new file mode 100644
+index 000000000000..4432aac51f2e
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-spi-add-cs1.dtso
+@@ -0,0 +1,41 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-a64";
++
++	fragment@0 {
++		target = <&pio>;
++		__overlay__ {
++			spi0_cs1: spi0_cs1 {
++				pins = "PB6";
++				function = "gpio_out";
++				output-high;
++			};
++
++			spi1_cs1: spi1_cs1 {
++				pins = "PD6";
++				function = "gpio_out";
++				output-high;
++			};
++		};
++	};
++
++	fragment@1 {
++		target = <&spi0>;
++		__overlay__ {
++			pinctrl-names = "default", "default";
++			pinctrl-1 = <&spi0_cs1>;
++			cs-gpios = <0>, <&pio 1 6 0>; /* PB6 */
++		};
++	};
++
++	fragment@2 {
++		target = <&spi1>;
++		__overlay__ {
++			pinctrl-names = "default", "default";
++			pinctrl-1 = <&spi1_cs1>;
++			cs-gpios = <0>, <&pio 3 6 0>; /* PD6 */
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-spi-jedec-nor.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-spi-jedec-nor.dtso
+new file mode 100644
+index 000000000000..31d73e572281
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-spi-jedec-nor.dtso
+@@ -0,0 +1,34 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-a64";
++
++	fragment@0 {
++		target = <&spi0>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spiflash@0 {
++				compatible = "jedec,spi-nor";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++				status = "disabled";
++			};
++		};
++	};
++
++	fragment@1 {
++		target = <&spi1>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spiflash@0 {
++				compatible = "jedec,spi-nor";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++				status = "disabled";
++			};
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-spi-spidev.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-spi-spidev.dtso
+new file mode 100644
+index 000000000000..84a435b79bee
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-spi-spidev.dtso
+@@ -0,0 +1,42 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-a64";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi0 = "/soc/spi@1c68000";
++			spi1 = "/soc/spi@1c69000";
++		};
++	};
++
++	fragment@1 {
++		target = <&spi0>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spidev@0 {
++				compatible = "armbian,spi-dev";
++				status = "disabled";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&spi1>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spidev@0 {
++				compatible = "armbian,spi-dev";
++				status = "disabled";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart1.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart1.dtso
+new file mode 100644
+index 000000000000..4d8dac1a59cb
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart1.dtso
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-a64";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			serial1 = "/soc/serial@1c28800";
++		};
++	};
++
++	fragment@1 {
++		target = <&uart1>;
++		 __overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart1_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart2.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart2.dtso
+new file mode 100644
+index 000000000000..7286d7360df1
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart2.dtso
+@@ -0,0 +1,37 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-a64";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			serial2 = "/soc/serial@1c28800";
++		};
++	};
++
++	fragment@1 {
++		target = <&pio>;
++		__overlay__ {
++			uart2_pins: uart2-pins {
++				pins = "PB0", "PB1";
++				function = "uart2";
++			};
++
++			uart2_rts_cts_pins: uart2-rts-cts-pins {
++				pins = "PB2", "PB3";
++				function = "uart2";
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&uart2>;
++		 __overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart2_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart3.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart3.dtso
+new file mode 100644
+index 000000000000..c5729b9d2568
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart3.dtso
+@@ -0,0 +1,32 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-a64";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			serial3 = "/soc/serial@1c28c00";
++		};
++	};
++
++	fragment@1 {
++		target = <&pio>;
++		__overlay__ {
++			uart3_pins: uart3-pins {
++				pins = "PD0", "PD1";
++				function = "uart3";
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&uart3>;
++		 __overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart3_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart4.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart4.dtso
+new file mode 100644
+index 000000000000..21c9b738aa93
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-uart4.dtso
+@@ -0,0 +1,37 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-a64";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			serial4 = "/soc/serial@1c29000";
++		};
++	};
++
++	fragment@1 {
++		target = <&pio>;
++		__overlay__ {
++			uart4_pins: uart4-pins {
++				pins = "PD2", "PD3";
++				function = "uart4";
++			};
++
++			uart4_rts_cts_pins: uart4-rts-cts-pins {
++				pins = "PD4", "PD5";
++				function = "uart4";
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&uart4>;
++		 __overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart4_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-w1-gpio.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-w1-gpio.dtso
+new file mode 100644
+index 000000000000..d230469135de
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-w1-gpio.dtso
+@@ -0,0 +1,29 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-a64";
++
++	fragment@0 {
++		target = <&pio>;
++		__overlay__ {
++			w1_pins: w1_pins {
++				pins = "PD4";
++				function = "gpio_in";
++			};
++		};
++	};
++
++	fragment@1 {
++		target-path = "/";
++		__overlay__ {
++			onewire@0 {
++				compatible = "w1-gpio";
++				pinctrl-names = "default";
++				pinctrl-0 = <&w1_pins>;
++				gpios = <&pio 3 4 0>; /* PD4 */
++				status = "okay";
++			};
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-analog-codec.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-analog-codec.dtso
+new file mode 100644
+index 000000000000..aaa66d5e7ca1
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-analog-codec.dtso
+@@ -0,0 +1,17 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h5";
++
++	fragment@0 {
++		target = <&codec>;
++		__overlay__ {
++			allwinner,audio-routing =
++				"Line Out", "LINEOUT",
++				"MIC1", "Mic",
++				"Mic",  "MBIAS";
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cir.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cir.dtso
+new file mode 100644
+index 000000000000..90c264a0ab78
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cir.dtso
+@@ -0,0 +1,15 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h5";
++
++	fragment@0 {
++		target = <&ir>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&r_ir_rx_pin>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-fixup.scr-cmd b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-fixup.scr-cmd
+new file mode 100644
+index 000000000000..7abb64d84a8a
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-fixup.scr-cmd
+@@ -0,0 +1,110 @@
++# overlays fixup script
++# implements (or rather substitutes) overlay arguments functionality
++# using u-boot scripting, environment variables and "fdt" command
++
++# setexpr test_var ${tmp_bank} - A
++# works only for hex numbers (A-F)
++
++setenv decompose_pin 'setexpr tmp_bank sub "P(A|C|D|G)\\d+" "\\1";
++setexpr tmp_pin sub "P\\S(\\d+)" "\\1";
++test "${tmp_bank}" = "A" && setenv tmp_bank 0;
++test "${tmp_bank}" = "C" && setenv tmp_bank 2;
++test "${tmp_bank}" = "D" && setenv tmp_bank 3;
++test "${tmp_bank}" = "G" && setenv tmp_bank 6'
++
++if test -n "${param_spinor_spi_bus}"; then
++	test "${param_spinor_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c68000"
++	test "${param_spinor_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c69000"
++	fdt set /soc/${tmp_spi_path} status "okay"
++	fdt set /soc/${tmp_spi_path}/spiflash@0 status "okay"
++	if test -n "${param_spinor_max_freq}"; then
++		fdt set /soc/${tmp_spi_path}/spiflash@0 spi-max-frequency "<${param_spinor_max_freq}>"
++	fi
++	if test "${param_spinor_spi_cs}" = "1"; then
++		fdt set /soc/${tmp_spi_path}/spiflash@0 reg "<1>"
++	fi
++	env delete tmp_spi_path
++fi
++
++if test -n "${param_spidev_spi_bus}"; then
++	test "${param_spidev_spi_bus}" = "0" && setenv tmp_spi_path "spi@1c68000"
++	test "${param_spidev_spi_bus}" = "1" && setenv tmp_spi_path "spi@1c69000"
++	fdt set /soc/${tmp_spi_path} status "okay"
++	fdt set /soc/${tmp_spi_path}/spidev status "okay"
++	if test -n "${param_spidev_max_freq}"; then
++		fdt set /soc/${tmp_spi_path}/spidev spi-max-frequency "<${param_spidev_max_freq}>"
++	fi
++	if test "${param_spidev_spi_cs}" = "1"; then
++		fdt set /soc/${tmp_spi_path}/spidev reg "<1>"
++	fi
++	env delete tmp_spi_path
++fi
++
++if test -n "${param_pps_pin}"; then
++	setenv tmp_bank "${param_pps_pin}"
++	setenv tmp_pin "${param_pps_pin}"
++	run decompose_pin
++	fdt set /soc/pinctrl@1c20800/pps_pins pins "${param_pps_pin}"
++	fdt get value tmp_phandle /soc/pinctrl@1c20800 phandle
++	fdt set /pps@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>"
++	env delete tmp_pin tmp_bank tmp_phandle
++fi
++
++if test "${param_pps_falling_edge}" = "1"; then
++	fdt set /pps@0 assert-falling-edge
++fi
++
++for f in ${overlays}; do
++	if test "${f}" = "pwm"; then
++		setenv bootargs_new ""
++		for arg in ${bootargs}; do
++			if test "${arg}" = "console=ttyS0,115200"; then
++				echo "Warning: Disabling ttyS0 console due to enabled PWM overlay"
++			else
++				setenv bootargs_new "${bootargs_new} ${arg}"
++			fi
++		done
++		setenv bootargs "${bootargs_new}"
++	fi
++done
++
++if test -n "${param_w1_pin}"; then
++	setenv tmp_bank "${param_w1_pin}"
++	setenv tmp_pin "${param_w1_pin}"
++	run decompose_pin
++	fdt set /soc/pinctrl@1c20800/w1_pins pins "${param_w1_pin}"
++	fdt get value tmp_phandle /soc/pinctrl@1c20800 phandle
++	fdt set /onewire@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>"
++	env delete tmp_pin tmp_bank tmp_phandle
++fi
++
++if test "${param_w1_pin_int_pullup}" = "1"; then
++	fdt set /soc/pinctrl@1c20800/w1_pins bias-pull-up
++fi
++
++if test "${param_uart1_rtscts}" = "1"; then
++	fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart1-pins phandle
++	fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart1-rts-cts-pins phandle
++	fdt set /soc/serial@1c28400 pinctrl-names "default" "default"
++	fdt set /soc/serial@1c28400 pinctrl-0 "<${tmp_phandle1}>"
++	fdt set /soc/serial@1c28400 pinctrl-1 "<${tmp_phandle2}>"
++	env delete tmp_phandle1 tmp_phandle2
++fi
++
++if test "${param_uart2_rtscts}" = "1"; then
++	fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart2-pins phandle
++	fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart2-rts-cts-pins phandle
++	fdt set /soc/serial@1c28800 pinctrl-names "default" "default"
++	fdt set /soc/serial@1c28800 pinctrl-0 "<${tmp_phandle1}>"
++	fdt set /soc/serial@1c28800 pinctrl-1 "<${tmp_phandle2}>"
++	env delete tmp_phandle1 tmp_phandle2
++fi
++
++if test "${param_uart3_rtscts}" = "1"; then
++	fdt get value tmp_phandle1 /soc/pinctrl@1c20800/uart3-pins phandle
++	fdt get value tmp_phandle2 /soc/pinctrl@1c20800/uart3-rts-cts-pins phandle
++	fdt set /soc/serial@1c28c00 pinctrl-names "default" "default"
++	fdt set /soc/serial@1c28c00 pinctrl-0 "<${tmp_phandle1}>"
++	fdt set /soc/serial@1c28c00 pinctrl-1 "<${tmp_phandle2}>"
++	env delete tmp_phandle1 tmp_phandle2
++fi
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-i2c0.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-i2c0.dtso
+new file mode 100644
+index 000000000000..87fbd7e51a11
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-i2c0.dtso
+@@ -0,0 +1,20 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h5";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			i2c0 = "/soc/i2c@1c2ac00";
++		};
++	};
++
++	fragment@1 {
++		target = <&i2c0>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-i2c1.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-i2c1.dtso
+new file mode 100644
+index 000000000000..6008b9a0853e
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-i2c1.dtso
+@@ -0,0 +1,20 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h5";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			i2c1 = "/soc/i2c@1c2b000";
++		};
++	};
++
++	fragment@1 {
++		target = <&i2c1>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-i2c2.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-i2c2.dtso
+new file mode 100644
+index 000000000000..2980dbf34300
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-i2c2.dtso
+@@ -0,0 +1,20 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h5";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			i2c2 = "/soc/i2c@1c2b400";
++		};
++	};
++
++	fragment@1 {
++		target = <&i2c2>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-pps-gpio.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-pps-gpio.dtso
+new file mode 100644
+index 000000000000..46e067562e3d
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-pps-gpio.dtso
+@@ -0,0 +1,29 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h5";
++
++	fragment@0 {
++		target = <&pio>;
++		__overlay__ {
++			pps_pins: pps_pins {
++				pins = "PD14";
++				function = "gpio_in";
++			};
++		};
++	};
++
++	fragment@1 {
++		target-path = "/";
++		__overlay__ {
++			pps@0 {
++				compatible = "pps-gpio";
++				pinctrl-names = "default";
++				pinctrl-0 = <&pps_pins>;
++				gpios = <&pio 3 14 0>; /* PD14 */
++				status = "okay";
++			};
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-pwm.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-pwm.dtso
+new file mode 100644
+index 000000000000..6d12e8420de9
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-pwm.dtso
+@@ -0,0 +1,39 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h5";
++
++	fragment@0 {
++		target-path = "/chosen";
++		__overlay__ {
++			/delete-property/ stdout-path;
++		};
++	};
++
++	fragment@1 {
++		target = <&uart0>;
++		__overlay__ {
++			status = "disabled";
++		};
++	};
++
++	fragment@2 {
++		target = <&pio>;
++		__overlay__ {
++			pwm0_pin: pwm0 {
++				pins = "PA5";
++				function = "pwm0";
++			};
++		};
++	};
++
++	fragment@3 {
++		target = <&pwm>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&pwm0_pin>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spdif-out.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spdif-out.dtso
+new file mode 100644
+index 000000000000..65bc51b0218e
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spdif-out.dtso
+@@ -0,0 +1,38 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h5";
++
++	fragment@0 {
++		target = <&spdif>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&spdif_tx_pin>;
++			status = "okay";
++		};
++	};
++
++	fragment@1 {
++		target-path = "/";
++		__overlay__ {
++			sound {
++				compatible = "simple-audio-card";
++				simple-audio-card,name = "On-board SPDIF";
++
++				simple-audio-card,cpu {
++					sound-dai = <&spdif>;
++				};
++
++				simple-audio-card,codec {
++					sound-dai = <&spdif_out>;
++				};
++			};
++
++			spdif_out: spdif-out {
++				#sound-dai-cells = <0>;
++				compatible = "linux,spdif-dit";
++			};
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spi-add-cs1.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spi-add-cs1.dtso
+new file mode 100644
+index 000000000000..8e3eab295f49
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spi-add-cs1.dtso
+@@ -0,0 +1,41 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h5";
++
++	fragment@0 {
++		target = <&pio>;
++		__overlay__ {
++			spi0_cs1: spi0_cs1 {
++				pins = "PA21";
++				function = "gpio_out";
++				output-high;
++			};
++
++			spi1_cs1: spi1_cs1 {
++				pins = "PA10";
++				function = "gpio_out";
++				output-high;
++			};
++		};
++	};
++
++	fragment@1 {
++		target = <&spi0>;
++		__overlay__ {
++			pinctrl-names = "default", "default";
++			pinctrl-1 = <&spi0_cs1>;
++			cs-gpios = <0>, <&pio 0 21 0>; /* PA21 */
++		};
++	};
++
++	fragment@2 {
++		target = <&spi1>;
++		__overlay__ {
++			pinctrl-names = "default", "default";
++			pinctrl-1 = <&spi1_cs1>;
++			cs-gpios = <0>, <&pio 0 10 0>; /* PA10 */
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spi-jedec-nor.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spi-jedec-nor.dtso
+new file mode 100644
+index 000000000000..5a45808c11a5
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spi-jedec-nor.dtso
+@@ -0,0 +1,42 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h5";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi0 = "/soc/spi@1c68000";
++			spi1 = "/soc/spi@1c69000";
++		};
++	};
++
++	fragment@1 {
++		target = <&spi0>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spiflash@0 {
++				compatible = "jedec,spi-nor";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++				status = "disabled";
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&spi1>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spiflash@0 {
++				compatible = "jedec,spi-nor";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++				status = "disabled";
++			};
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spi-spidev.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spi-spidev.dtso
+new file mode 100644
+index 000000000000..69a14b2c60e4
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-spi-spidev.dtso
+@@ -0,0 +1,42 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h5";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi0 = "/soc/spi@1c68000";
++			spi1 = "/soc/spi@1c69000";
++		};
++	};
++
++	fragment@1 {
++		target = <&spi0>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spidev@0 {
++				compatible = "armbian,spi-dev";
++				status = "disabled";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&spi1>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spidev@0 {
++				compatible = "armbian,spi-dev";
++				status = "disabled";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-uart1.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-uart1.dtso
+new file mode 100644
+index 000000000000..92e3eb4d9b66
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-uart1.dtso
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h5";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			serial1 = "/soc/serial@1c28400";
++		};
++	};
++
++	fragment@1 {
++		target = <&uart1>;
++		 __overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart1_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-uart2.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-uart2.dtso
+new file mode 100644
+index 000000000000..92bee1a9600a
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-uart2.dtso
+@@ -0,0 +1,32 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h5";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			serial2 = "/soc/serial@1c28800";
++		};
++	};
++
++	fragment@1 {
++		target = <&pio>;
++		__overlay__ {
++			uart2_rts_cts: uart2-rts-cts-pins {
++				pins = "PA2", "PA3";
++				function = "uart2";
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&uart2>;
++		 __overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart2_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-uart3.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-uart3.dtso
+new file mode 100644
+index 000000000000..a2197f1668fb
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-uart3.dtso
+@@ -0,0 +1,32 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h5";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			serial3 = "/soc/serial@1c28c00";
++		};
++	};
++
++	fragment@1 {
++		target = <&pio>;
++		__overlay__ {
++			uart3_rts_cts: uart3-rts-cts-pins {
++				pins = "PA15", "PA16";
++				function = "uart3";
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&uart3>;
++		 __overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart3_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost0.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost0.dtso
+new file mode 100644
+index 000000000000..c1d79c232fa4
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost0.dtso
+@@ -0,0 +1,27 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h5";
++
++	fragment@0 {
++		target = <&ehci0>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++
++	fragment@1 {
++		target = <&ohci0>;
++		 __overlay__ {
++			status = "okay";
++		};
++	};
++
++	fragment@2 {
++		target = <&usbphy>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost1.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost1.dtso
+new file mode 100644
+index 000000000000..2b4f245bf297
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost1.dtso
+@@ -0,0 +1,27 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h5";
++
++	fragment@0 {
++		target = <&ehci1>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++
++	fragment@1 {
++		target = <&ohci1>;
++		 __overlay__ {
++			status = "okay";
++		};
++	};
++
++	fragment@2 {
++		target = <&usbphy>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost2.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost2.dtso
+new file mode 100644
+index 000000000000..54800e729538
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost2.dtso
+@@ -0,0 +1,27 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h5";
++
++	fragment@0 {
++		target = <&ehci2>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++
++	fragment@1 {
++		target = <&ohci2>;
++		 __overlay__ {
++			status = "okay";
++		};
++	};
++
++	fragment@2 {
++		target = <&usbphy>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost3.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost3.dtso
+new file mode 100644
+index 000000000000..a99524ea38f3
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-usbhost3.dtso
+@@ -0,0 +1,27 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h5";
++
++	fragment@0 {
++		target = <&ehci3>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++
++	fragment@1 {
++		target = <&ohci3>;
++		 __overlay__ {
++			status = "okay";
++		};
++	};
++
++	fragment@2 {
++		target = <&usbphy>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-w1-gpio.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-w1-gpio.dtso
+new file mode 100644
+index 000000000000..6e99626ac660
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-w1-gpio.dtso
+@@ -0,0 +1,29 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h5";
++
++	fragment@0 {
++		target = <&pio>;
++		__overlay__ {
++			w1_pins: w1_pins {
++				pins = "PD14";
++				function = "gpio_in";
++			};
++		};
++	};
++
++	fragment@1 {
++		target-path = "/";
++		__overlay__ {
++			onewire@0 {
++				compatible = "w1-gpio";
++				pinctrl-names = "default";
++				pinctrl-0 = <&w1_pins>;
++				gpios = <&pio 3 14 0>; /* PD14 */
++				status = "okay";
++			};
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-fixup.scr-cmd b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-fixup.scr-cmd
+new file mode 100644
+index 000000000000..d8e79ba4531b
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-fixup.scr-cmd
+@@ -0,0 +1,110 @@
++# overlays fixup script
++# implements (or rather substitutes) overlay arguments functionality
++# using u-boot scripting, environment variables and "fdt" command
++
++# setexpr test_var ${tmp_bank} - A
++# works only for hex numbers (A-F)
++
++setenv decompose_pin 'setexpr tmp_bank sub "P(A|C|D|G)\\d+" "\\1";
++setexpr tmp_pin sub "P\\S(\\d+)" "\\1";
++test "${tmp_bank}" = "A" && setenv tmp_bank 0;
++test "${tmp_bank}" = "C" && setenv tmp_bank 2;
++test "${tmp_bank}" = "D" && setenv tmp_bank 3;
++test "${tmp_bank}" = "G" && setenv tmp_bank 6'
++
++if test -n "${param_spinor_spi_bus}"; then
++	test "${param_spinor_spi_bus}" = "0" && setenv tmp_spi_path "spi@5010000"
++	test "${param_spinor_spi_bus}" = "1" && setenv tmp_spi_path "spi@5011000"
++	fdt set /soc/${tmp_spi_path} status "okay"
++	fdt set /soc/${tmp_spi_path}/spiflash@0 status "okay"
++	if test -n "${param_spinor_max_freq}"; then
++		fdt set /soc/${tmp_spi_path}/spiflash@0 spi-max-frequency "<${param_spinor_max_freq}>"
++	fi
++	if test "${param_spinor_spi_cs}" = "1"; then
++		fdt set /soc/${tmp_spi_path}/spiflash@0 reg "<1>"
++	fi
++	env delete tmp_spi_path
++fi
++
++if test -n "${param_spidev_spi_bus}"; then
++	test "${param_spidev_spi_bus}" = "0" && setenv tmp_spi_path "spi@5010000"
++	test "${param_spidev_spi_bus}" = "1" && setenv tmp_spi_path "spi@5011000"
++	fdt set /soc/${tmp_spi_path} status "okay"
++	fdt set /soc/${tmp_spi_path}/spidev status "okay"
++	if test -n "${param_spidev_max_freq}"; then
++		fdt set /soc/${tmp_spi_path}/spidev spi-max-frequency "<${param_spidev_max_freq}>"
++	fi
++	if test "${param_spidev_spi_cs}" = "1"; then
++		fdt set /soc/${tmp_spi_path}/spidev reg "<1>"
++	fi
++	env delete tmp_spi_path
++fi
++
++if test -n "${param_pps_pin}"; then
++	setenv tmp_bank "${param_pps_pin}"
++	setenv tmp_pin "${param_pps_pin}"
++	run decompose_pin
++	fdt set /soc/pinctrl@300b000/pps_pins pins "${param_pps_pin}"
++	fdt get value tmp_phandle /soc/pinctrl@300b000 phandle
++	fdt set /pps@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>"
++	env delete tmp_pin tmp_bank tmp_phandle
++fi
++
++if test "${param_pps_falling_edge}" = "1"; then
++	fdt set /pps@0 assert-falling-edge
++fi
++
++for f in ${overlays}; do
++	if test "${f}" = "pwm"; then
++		setenv bootargs_new ""
++		for arg in ${bootargs}; do
++			if test "${arg}" = "console=ttyS0,115200"; then
++				echo "Warning: Disabling ttyS0 console due to enabled PWM overlay"
++			else
++				setenv bootargs_new "${bootargs_new} ${arg}"
++			fi
++		done
++		setenv bootargs "${bootargs_new}"
++	fi
++done
++
++if test -n "${param_w1_pin}"; then
++	setenv tmp_bank "${param_w1_pin}"
++	setenv tmp_pin "${param_w1_pin}"
++	run decompose_pin
++	fdt set /soc/pinctrl@300b000/w1_pins pins "${param_w1_pin}"
++	fdt get value tmp_phandle /soc/pinctrl@300b000 phandle
++	fdt set /onewire@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>"
++	env delete tmp_pin tmp_bank tmp_phandle
++fi
++
++if test "${param_w1_pin_int_pullup}" = "1"; then
++	fdt set /soc/pinctrl@300b000/w1_pins bias-pull-up
++fi
++
++if test "${param_uart1_rtscts}" = "1"; then
++	fdt get value tmp_phandle1 /soc/pinctrl@300b000/uart1-pins phandle
++	fdt get value tmp_phandle2 /soc/pinctrl@300b000/uart1-rts-cts-pins phandle
++	fdt set /soc/serial@5000400 pinctrl-names "default" "default"
++	fdt set /soc/serial@5000400 pinctrl-0 "<${tmp_phandle1}>"
++	fdt set /soc/serial@5000400 pinctrl-1 "<${tmp_phandle2}>"
++	env delete tmp_phandle1 tmp_phandle2
++fi
++
++if test "${param_uart2_rtscts}" = "1"; then
++	fdt get value tmp_phandle1 /soc/pinctrl@300b000/uart2-pins phandle
++	fdt get value tmp_phandle2 /soc/pinctrl@300b000/uart2-rts-cts-pins phandle
++	fdt set /soc/serial@5000800 pinctrl-names "default" "default"
++	fdt set /soc/serial@5000800 pinctrl-0 "<${tmp_phandle1}>"
++	fdt set /soc/serial@5000800 pinctrl-1 "<${tmp_phandle2}>"
++	env delete tmp_phandle1 tmp_phandle2
++fi
++
++if test "${param_uart3_rtscts}" = "1"; then
++	fdt get value tmp_phandle1 /soc/pinctrl@300b000/uart3-pins phandle
++	fdt get value tmp_phandle2 /soc/pinctrl@300b000/uart3-rts-cts-pins phandle
++	fdt set /soc/serial@5000c00 pinctrl-names "default" "default"
++	fdt set /soc/serial@5000c00 pinctrl-0 "<${tmp_phandle1}>"
++	fdt set /soc/serial@5000c00 pinctrl-1 "<${tmp_phandle2}>"
++	env delete tmp_phandle1 tmp_phandle2
++fi
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-i2c0.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-i2c0.dtso
+new file mode 100644
+index 000000000000..7e7ee8c46e9c
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-i2c0.dtso
+@@ -0,0 +1,20 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h6";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			i2c0 = "/soc/i2c@5002000";
++		};
++	};
++
++	fragment@1 {
++		target = <&i2c0>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-i2c1.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-i2c1.dtso
+new file mode 100644
+index 000000000000..111769821262
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-i2c1.dtso
+@@ -0,0 +1,20 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h6";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			i2c1 = "/soc/i2c@5002400";
++		};
++	};
++
++	fragment@1 {
++		target = <&i2c1>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-i2c2.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-i2c2.dtso
+new file mode 100644
+index 000000000000..b627529c2144
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-i2c2.dtso
+@@ -0,0 +1,20 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h6";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			i2c2 = "/soc/i2c@5002800";
++		};
++	};
++
++	fragment@1 {
++		target = <&i2c2>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-ruart.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-ruart.dtso
+new file mode 100644
+index 000000000000..6430cb083370
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-ruart.dtso
+@@ -0,0 +1,13 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h6";
++
++	fragment@0 {
++		target = <&r_uart>;
++		 __overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-add-cs1.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-add-cs1.dtso
+new file mode 100644
+index 000000000000..0fa060fa1eff
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-add-cs1.dtso
+@@ -0,0 +1,41 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h6";
++
++	fragment@0 {
++		target = <&pio>;
++		__overlay__ {
++			spi0_cs1: spi0_cs1 {
++				pins = "PA10";
++				function = "gpio_out";
++				output-high;
++			};
++
++			spi1_cs1: spi1_cs1 {
++				pins = "PA21";
++				function = "gpio_out";
++				output-high;
++			};
++		};
++	};
++
++	fragment@1 {
++		target = <&spi0>;
++		__overlay__ {
++			pinctrl-names = "default", "default";
++			pinctrl-1 = <&spi0_cs1>;
++			cs-gpios = <0>, <&pio 0 10 0>; /* PA10 */
++		};
++	};
++
++	fragment@2 {
++		target = <&spi1>;
++		__overlay__ {
++			pinctrl-names = "default", "default";
++			pinctrl-1 = <&spi1_cs1>;
++			cs-gpios = <0>, <&pio 0 21 0>; /* PA21 */
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-jedec-nor.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-jedec-nor.dtso
+new file mode 100644
+index 000000000000..4f81dbb9924c
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-jedec-nor.dtso
+@@ -0,0 +1,42 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h6";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi0 = "/soc/spi@5010000";
++			spi1 = "/soc/spi@5011000";
++		};
++	};
++
++	fragment@1 {
++		target = <&spi0>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spiflash@0 {
++				compatible = "jedec,spi-nor";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++				status = "disabled";
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&spi1>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spiflash@0 {
++				compatible = "jedec,spi-nor";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++				status = "disabled";
++			};
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-spidev.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-spidev.dtso
+new file mode 100644
+index 000000000000..1f077ea80ae5
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-spidev.dtso
+@@ -0,0 +1,42 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun8i-h3-spi";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi0 = "/soc/spi@5010000";
++			spi1 = "/soc/spi@5011000";
++		};
++	};
++
++	fragment@1 {
++		target = <&spi0>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spidev@0 {
++				compatible = "armbian,spi-dev";
++				status = "disabled";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&spi1>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spidev@0 {
++				compatible = "armbian,spi-dev";
++				status = "disabled";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-spidev1.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-spidev1.dtso
+new file mode 100644
+index 000000000000..5e6b70530fae
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-spi-spidev1.dtso
+@@ -0,0 +1,30 @@
++// Enable the spidev interface
++/dts-v1/;
++/plugin/;
++
++/ {
++    compatible = "allwinner,sun8i-h3-spi";
++
++    fragment@0 {
++	target-path = "/aliases";
++	__overlay__ {
++            /* Path to the SPI controller nodes */
++            spi1 = "/soc/spi@5011000";
++        };
++    };
++    fragment@1 {
++        target = <&spi1>;
++        __overlay__ {
++            pinctrl-names = "default";
++            pinctrl-0 = <&spi1_pins>;
++            status = "okay";
++            #address-cells = <1>;
++            #size-cells = <0>;
++            spidev@0 {
++                compatible = "armbian,spi-dev";
++                reg = <0x0>;
++                spi-max-frequency = <1000000>;
++            };
++        };
++    };
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-uart1.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-uart1.dtso
+new file mode 100644
+index 000000000000..44aa94efdad1
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-uart1.dtso
+@@ -0,0 +1,22 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h6";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			serial1 = "/soc/serial@5000400";
++		};
++	};
++
++	fragment@1 {
++		target = <&uart1>;
++		 __overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart1_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-uart2.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-uart2.dtso
+new file mode 100644
+index 000000000000..bf9174bcd2e6
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-uart2.dtso
+@@ -0,0 +1,32 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h6";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			serial2 = "/soc/serial@5000800";
++		};
++	};
++
++	fragment@1 {
++		target = <&pio>;
++		__overlay__ {
++			uart2_rts_cts: uart2-rts-cts-pins {
++				pins = "PD21", "PD22";
++				function = "uart2";
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&uart2>;
++		 __overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart2_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-uart3.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-uart3.dtso
+new file mode 100644
+index 000000000000..418edc14a0e4
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-uart3.dtso
+@@ -0,0 +1,32 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h6";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			serial3 = "/soc/serial@5000c00";
++		};
++	};
++
++	fragment@1 {
++		target = <&pio>;
++		__overlay__ {
++			uart3_rts_cts: uart3-rts-cts-pins {
++				pins = "PD25", "PD26";
++				function = "uart3";
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&uart3>;
++		 __overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart3_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-w1-gpio.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-w1-gpio.dtso
+new file mode 100644
+index 000000000000..3043c87780e4
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h6-w1-gpio.dtso
+@@ -0,0 +1,29 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h6";
++
++	fragment@0 {
++		target = <&pio>;
++		__overlay__ {
++			w1_pins: w1_pins {
++				pins = "PC9";
++				function = "gpio_in";
++			};
++		};
++	};
++
++	fragment@1 {
++		target-path = "/";
++		__overlay__ {
++			onewire@0 {
++				compatible = "w1-gpio";
++				pinctrl-names = "default";
++				pinctrl-0 = <&w1_pins>;
++				gpios = <&pio 2 9 0>; /* PC9 */
++				status = "okay";
++			};
++		};
++	};
++};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-allwinner-sun50i-h6-Fix-H6-emmc.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-allwinner-sun50i-h6-Fix-H6-emmc.patch
new file mode 100644
index 000000000000..724f703c56c3
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-allwinner-sun50i-h6-Fix-H6-emmc.patch
@@ -0,0 +1,26 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Ukhellfire <afaulkner420@gmail.com>
+Date: Fri, 25 Mar 2022 07:10:57 +0000
+Subject: arm64: dts/allwinner/sun50i-h6: Fix H6 emmc
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+@@ -563,8 +563,7 @@ mmc1: mmc@4021000 {
+ 		};
+ 
+ 		mmc2: mmc@4022000 {
+-			compatible = "allwinner,sun50i-h6-emmc",
+-				     "allwinner,sun50i-a64-emmc";
++			compatible = "allwinner,sun50i-h6-emmc";
+ 			reg = <0x04022000 0x1000>;
+ 			clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
+ 			clock-names = "ahb", "mmc";
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-allwinner-sun50i-h616-Add-VPU-node.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-allwinner-sun50i-h616-Add-VPU-node.patch
new file mode 100644
index 000000000000..f6a641398a5f
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-allwinner-sun50i-h616-Add-VPU-node.patch
@@ -0,0 +1,55 @@
+From 3561685a36bdb6cba7af84f303e068b8448bf652 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Fri, 15 Oct 2021 21:14:55 +0200
+Subject: arm64:dts:allwinner: sun50i-h616 Add VPU node
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 24 +++++++++++++++++++
+ 1 file changed, 24 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+index 8a3ee8ecf671..6d1ed00375bc 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+@@ -175,6 +175,17 @@ crypto: crypto@1904000 {
+ 			resets = <&ccu RST_BUS_CE>;
+ 		};
+ 
++		video-codec@1c0e000 {
++			compatible = "allwinner,sun50i-h616-video-engine";
++			reg = <0x01c0e000 0x2000>;
++			clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
++				 <&ccu CLK_MBUS_VE>;
++			clock-names = "ahb", "mod", "ram";
++			resets = <&ccu RST_BUS_VE>;
++			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
++			allwinner,sram = <&ve_sram 1>;
++		};
++
+ 		syscon: syscon@3000000 {
+ 			compatible = "allwinner,sun50i-h616-system-control";
+ 			reg = <0x03000000 0x1000>;
+@@ -189,6 +200,19 @@ sram_c: sram@28000 {
+ 				#size-cells = <1>;
+ 				ranges = <0 0x00028000 0x30000>;
+ 			};
++
++			sram_c1: sram@1a00000 {
++				compatible = "mmio-sram";
++				reg = <0x01a00000 0x200000>;
++				#address-cells = <1>;
++				#size-cells = <1>;
++				ranges = <0 0x01a00000 0x200000>;
++
++				ve_sram: sram-section@0 {
++					compatible = "allwinner,sun50i-h616-sram-c1";
++					reg = <0x000000 0x200000>;
++				};
++			};
+ 		};
+ 
+ 		ccu: clock@3001000 {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-h616-8-Add-overlays-i2c-pwm-uart.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-h616-8-Add-overlays-i2c-pwm-uart.patch
new file mode 100644
index 000000000000..e80b825760a8
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-h616-8-Add-overlays-i2c-pwm-uart.patch
@@ -0,0 +1,369 @@
+From c07564c395a35f421a9eff81d9ca77496c0106e6 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Thu, 10 Apr 2025 21:46:22 +0300
+Subject: arm64: dts: h616(8): Add overlays i2c, pwm, uart
+
+---
+ .../arm64/boot/dts/allwinner/overlay/Makefile | 14 +++++++++++++
+ .../overlay/sun50i-h616-i2c2-ph.dtso          | 13 ++++++++++++
+ .../overlay/sun50i-h616-i2c3-pg.dtso          | 13 ++++++++++++
+ .../overlay/sun50i-h616-i2c3-ph.dtso          | 13 ++++++++++++
+ .../overlay/sun50i-h616-i2c4-pg.dtso          | 13 ++++++++++++
+ .../overlay/sun50i-h616-i2c4-ph.dtso          | 13 ++++++++++++
+ .../overlay/sun50i-h616-pwm1-ph3.dtso         | 20 +++++++++++++++++++
+ .../overlay/sun50i-h616-pwm1-pi11.dtso        | 20 +++++++++++++++++++
+ .../overlay/sun50i-h616-pwm4-ph1.dtso         | 20 +++++++++++++++++++
+ .../overlay/sun50i-h616-pwm4-pi14.dtso        | 20 +++++++++++++++++++
+ .../overlay/sun50i-h616-uart2-pg-rts-cts.dtso | 15 ++++++++++++++
+ .../overlay/sun50i-h616-uart2-pg.dtso         | 15 ++++++++++++++
+ .../overlay/sun50i-h616-uart2-ph-rts-cts.dtso | 15 ++++++++++++++
+ .../overlay/sun50i-h616-uart2-ph.dtso         | 15 ++++++++++++++
+ .../allwinner/overlay/sun50i-h616-uart5.dtso  | 15 ++++++++++++++
+ 15 files changed, 234 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c2-ph.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c3-pg.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c3-ph.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c4-pg.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c4-ph.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-pwm1-ph3.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-pwm1-pi11.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-pwm4-ph1.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-pwm4-pi14.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart2-pg-rts-cts.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart2-pg.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart2-ph-rts-cts.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart2-ph.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart5.dtso
+
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/Makefile b/arch/arm64/boot/dts/allwinner/overlay/Makefile
+index 84711585fc86..fd0b06d173f7 100644
+--- a/arch/arm64/boot/dts/allwinner/overlay/Makefile
++++ b/arch/arm64/boot/dts/allwinner/overlay/Makefile
+@@ -49,6 +49,20 @@ dtb-$(CONFIG_ARCH_SUNXI) += \
+ 	sun50i-h6-uart2.dtbo \
+ 	sun50i-h6-uart3.dtbo \
+ 	sun50i-h6-w1-gpio.dtbo \
++	sun50i-h616-i2c2-ph.dtbo \
++	sun50i-h616-i2c3-pg.dtbo \
++	sun50i-h616-i2c3-ph.dtbo \
++	sun50i-h616-i2c4-pg.dtbo \
++	sun50i-h616-i2c4-ph.dtbo \
++	sun50i-h616-pwm1-ph3.dtbo \
++	sun50i-h616-pwm1-pi11.dtbo \
++	sun50i-h616-pwm4-ph1.dtbo \
++	sun50i-h616-pwm4-pi14.dtbo \
++	sun50i-h616-uart2-pg.dtbo \
++	sun50i-h616-uart2-pg-rts-cts.dtbo \
++	sun50i-h616-uart2-ph.dtbo \
++	sun50i-h616-uart2-ph-rts-cts.dtbo \
++	sun50i-h616-uart5.dtbo \
+ 	sun50i-h616-spi-spidev.dtbo \
+ 	sun50i-h616-spidev0_0.dtbo \
+ 	sun50i-h616-spidev1_0.dtbo \
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c2-ph.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c2-ph.dtso
+new file mode 100644
+index 000000000000..663633f6c7c9
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c2-ph.dtso
+@@ -0,0 +1,13 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	fragment@0 {
++		target = <&i2c2>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&i2c2_ph_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c3-pg.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c3-pg.dtso
+new file mode 100644
+index 000000000000..eb71dcb593cc
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c3-pg.dtso
+@@ -0,0 +1,13 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	fragment@0 {
++		target = <&i2c3>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&i2c3_pg_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c3-ph.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c3-ph.dtso
+new file mode 100644
+index 000000000000..b0aed6f59bb0
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c3-ph.dtso
+@@ -0,0 +1,13 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	fragment@0 {
++		target = <&i2c3>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&i2c3_ph_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c4-pg.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c4-pg.dtso
+new file mode 100644
+index 000000000000..6a83466f5b37
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c4-pg.dtso
+@@ -0,0 +1,13 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	fragment@0 {
++		target = <&i2c4>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&i2c4_pg_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c4-ph.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c4-ph.dtso
+new file mode 100644
+index 000000000000..cfa737d701d8
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-i2c4-ph.dtso
+@@ -0,0 +1,13 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	fragment@0 {
++		target = <&i2c4>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&i2c4_ph_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-pwm1-ph3.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-pwm1-ph3.dtso
+new file mode 100644
+index 000000000000..fa7697a63915
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-pwm1-ph3.dtso
+@@ -0,0 +1,20 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	fragment@0 {
++		target = <&pwm>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++
++	fragment@1 {
++		target = <&pwm1>;
++		__overlay__ {
++			status = "okay";
++			pinctrl-names = "default";
++			pinctrl-0 = <&pwm1_ph_pin>;
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-pwm1-pi11.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-pwm1-pi11.dtso
+new file mode 100644
+index 000000000000..c42dabb470f3
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-pwm1-pi11.dtso
+@@ -0,0 +1,20 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	fragment@0 {
++		target = <&pwm>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++
++	fragment@1 {
++		target = <&pwm1>;
++		__overlay__ {
++			status = "okay";
++			pinctrl-names = "default";
++			pinctrl-0 = <&pwm1_pi_pin>;
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-pwm4-ph1.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-pwm4-ph1.dtso
+new file mode 100644
+index 000000000000..381a3db48cba
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-pwm4-ph1.dtso
+@@ -0,0 +1,20 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	fragment@0 {
++		target = <&pwm>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++
++	fragment@1 {
++		target = <&pwm4>;
++		__overlay__ {
++			status = "okay";
++			pinctrl-names = "default";
++			pinctrl-0 = <&pwm4_ph_pin>;
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-pwm4-pi14.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-pwm4-pi14.dtso
+new file mode 100644
+index 000000000000..47302a13a7bf
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-pwm4-pi14.dtso
+@@ -0,0 +1,20 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	fragment@0 {
++		target = <&pwm>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++
++	fragment@1 {
++		target = <&pwm4>;
++		__overlay__ {
++			status = "okay";
++			pinctrl-names = "default";
++			pinctrl-0 = <&pwm4_pi_pin>;
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart2-pg-rts-cts.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart2-pg-rts-cts.dtso
+new file mode 100644
+index 000000000000..7cee4ebec233
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart2-pg-rts-cts.dtso
+@@ -0,0 +1,15 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h616", "allwinner,sun50i-h618";
++
++	fragment@0 {
++		target = <&uart2>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart2_pg_pins>, <&uart2_pg_rts_cts_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart2-pg.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart2-pg.dtso
+new file mode 100644
+index 000000000000..298cb56023a1
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart2-pg.dtso
+@@ -0,0 +1,15 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h616", "allwinner,sun50i-h618";
++
++	fragment@0 {
++		target = <&uart2>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart2_pg_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart2-ph-rts-cts.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart2-ph-rts-cts.dtso
+new file mode 100644
+index 000000000000..66193cde7526
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart2-ph-rts-cts.dtso
+@@ -0,0 +1,15 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h616", "allwinner,sun50i-h618";
++
++	fragment@0 {
++		target = <&uart2>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart2_ph_pins>, <&uart2_ph_rts_cts_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart2-ph.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart2-ph.dtso
+new file mode 100644
+index 000000000000..438af7517b5a
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart2-ph.dtso
+@@ -0,0 +1,15 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h616", "allwinner,sun50i-h618";
++
++	fragment@0 {
++		target = <&uart2>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart2_ph_pins>;
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart5.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart5.dtso
+new file mode 100644
+index 000000000000..27b4ab085d98
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-uart5.dtso
+@@ -0,0 +1,15 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h616", "allwinner,sun50i-h618";
++
++	fragment@0 {
++		target = <&uart5>;
++		__overlay__ {
++			pinctrl-names = "default";
++			pinctrl-0 = <&uart5_pins>;
++			status = "okay";
++		};
++	};
++};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-h616-add-hdmi-support-for-zero2-and-zero3.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-h616-add-hdmi-support-for-zero2-and-zero3.patch
new file mode 100644
index 000000000000..5f6130749a5e
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-h616-add-hdmi-support-for-zero2-and-zero3.patch
@@ -0,0 +1,339 @@
+From 2c8fcfebe335951a63e1ecb3c8906c919f4ab94c Mon Sep 17 00:00:00 2001
+From: Gunjan Gupta <viraniac@gmail.com>
+Date: Fri, 29 Dec 2023 11:18:33 +0000
+Subject: arm64: dts: h616: add hdmi support for zero2 and zero3
+
+---
+ .../allwinner/sun50i-h616-orangepi-zero.dtsi  |  25 ++
+ .../allwinner/sun50i-h616-orangepi-zero2.dts  |   4 +
+ .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 213 ++++++++++++++++++
+ 3 files changed, 242 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
+index 061848cf8b13..60f643abb3eb 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
+@@ -23,6 +23,17 @@ chosen {
+ 		stdout-path = "serial0:115200n8";
+ 	};
+ 
++	connector {
++		compatible = "hdmi-connector";
++		type = "d";
++
++		port {
++			hdmi_con_in: endpoint {
++				remote-endpoint = <&hdmi_out_con>;
++			};
++		};
++	};
++
+ 	leds {
+ 		compatible = "gpio-leds";
+ 
+@@ -95,6 +106,10 @@ &codec {
+ 	status = "okay";
+ };
+ 
++&de {
++	status = "okay";
++};
++
+ &ehci1 {
+ 	status = "okay";
+ };
+@@ -115,6 +130,16 @@ &emac0 {
+ 	status = "okay";
+ };
+ 
++&hdmi {
++	status = "okay";
++};
++
++&hdmi_out {
++	hdmi_out_con: endpoint {
++		remote-endpoint = <&hdmi_con_in>;
++	};
++};
++
+ &mdio0 {
+ 	ext_rgmii_phy: ethernet-phy@1 {
+ 		compatible = "ethernet-phy-ieee802.3-c22";
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
+index 42c099483fdd..60dd0860f49f 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
+@@ -29,6 +29,10 @@ &gpu {
+ 	status = "okay";
+ };
+ 
++&hdmi {
++	hvcc-supply = <&reg_bldo1>;
++};
++
+ &mmc0 {
+ 	vmmc-supply = <&reg_dcdce>;
+ };
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+index 5c1e2dc77268..564c5853af97 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+@@ -7,8 +7,11 @@
+ #include <dt-bindings/clock/sun50i-h616-ccu.h>
+ #include <dt-bindings/clock/sun50i-h6-r-ccu.h>
+ #include <dt-bindings/clock/sun6i-rtc.h>
++#include <dt-bindings/clock/sun8i-de2.h>
++#include <dt-bindings/clock/sun8i-tcon-top.h>
+ #include <dt-bindings/reset/sun50i-h616-ccu.h>
+ #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
++#include <dt-bindings/reset/sun8i-de2.h>
+ #include <dt-bindings/thermal/thermal.h>
+ 
+ / {
+@@ -94,6 +97,12 @@ l2_cache: l2-cache {
+ 		};
+ 	};
+ 
++	de: display-engine {
++		compatible = "allwinner,sun50i-h6-display-engine";
++		allwinner,pipelines = <&mixer0>;
++		status = "disabled";
++	};
++
+ 	reserved-memory {
+ 		#address-cells = <2>;
+ 		#size-cells = <2>;
+@@ -150,6 +159,50 @@ soc {
+ 		#size-cells = <1>;
+ 		ranges = <0x0 0x0 0x0 0x40000000>;
+ 
++		bus@1000000 {
++			compatible = "allwinner,sun50i-h616-de33",
++				     "allwinner,sun50i-a64-de2";
++			reg = <0x1000000 0x400000>;
++			allwinner,sram = <&de3_sram 1>;
++			#address-cells = <1>;
++			#size-cells = <1>;
++			ranges = <0 0x1000000 0x400000>;
++
++			display_clocks: clock@8000 {
++				compatible = "allwinner,sun50i-h616-de33-clk";
++				reg = <0x8000 0x100>;
++				clocks = <&ccu CLK_DE>, <&ccu CLK_BUS_DE>;
++				clock-names = "mod", "bus";
++				resets = <&ccu RST_BUS_DE>;
++				#clock-cells = <1>;
++				#reset-cells = <1>;
++			};
++
++			mixer0: mixer@100000 {
++				compatible = "allwinner,sun50i-h616-de33-mixer-0";
++				reg = <0x100000 0x100000>,
++				      <0x8100 0x40>,
++				      <0x280000 0x20000>;
++				clocks = <&display_clocks CLK_BUS_MIXER0>,
++					 <&display_clocks CLK_MIXER0>;
++				clock-names = "bus", "mod";
++				resets = <&display_clocks RST_MIXER0>;
++
++				ports {
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					mixer0_out: port@1 {
++						reg = <1>;
++
++						mixer0_out_tcon_top_mixer0: endpoint {
++							remote-endpoint = <&tcon_top_mixer0_in_mixer0>;
++						};
++					};
++				};
++			};
++		};
++
+ 		gpu: gpu@1800000 {
+ 			compatible = "allwinner,sun50i-h616-mali",
+ 				     "arm,mali-bifrost";
+@@ -193,12 +246,31 @@ syscon: syscon@3000000 {
+ 			#size-cells = <1>;
+ 			ranges;
+ 
++			sram_a2: sram@100000 {
++				compatible = "mmio-sram";
++				reg = <0x00100000 0x18000>;
++				#address-cells = <1>;
++				#size-cells = <1>;
++				ranges = <0 0x00100000 0x18000>;
++
++				scpi_sram: scpi-sram@17c00 {
++					compatible = "arm,scp-shmem";
++					reg = <0x17c00 0x200>;
++				};
++			};
++
+ 			sram_c: sram@28000 {
+ 				compatible = "mmio-sram";
+ 				reg = <0x00028000 0x30000>;
+ 				#address-cells = <1>;
+ 				#size-cells = <1>;
+ 				ranges = <0 0x00028000 0x30000>;
++
++				de3_sram: sram-section@0 {
++					compatible = "allwinner,sun50i-h616-sram-c",
++						     "allwinner,sun50i-a64-sram-c";
++					reg = <0x0000 0x1e000>;
++				};
+ 			};
+ 
+ 			sram_c1: sram@1a00000 {
+@@ -918,6 +990,147 @@ ohci3: usb@5311400 {
+ 			status = "disabled";
+ 		};
+ 
++		hdmi: hdmi@6000000 {
++			#sound-dai-cells = <0>;
++			compatible = "allwinner,sun50i-h616-dw-hdmi",
++				     "allwinner,sun50i-h6-dw-hdmi";
++			reg = <0x06000000 0x10000>;
++			reg-io-width = <1>;
++			interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
++				 <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>,
++				 <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>;
++			clock-names = "iahb", "isfr", "tmds", "cec", "hdcp",
++				      "hdcp-bus";
++			resets = <&ccu RST_BUS_HDMI>, <&ccu RST_BUS_HDCP>;
++			reset-names = "ctrl", "hdcp";
++			phys = <&hdmi_phy>;
++			phy-names = "phy";
++			status = "disabled";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				hdmi_in: port@0 {
++					reg = <0>;
++
++					hdmi_in_tcon_top: endpoint {
++						remote-endpoint = <&tcon_top_hdmi_out_hdmi>;
++					};
++				};
++
++				hdmi_out: port@1 {
++					reg = <1>;
++				};
++			};
++		};
++
++		hdmi_phy: hdmi-phy@6010000 {
++			compatible = "allwinner,sun50i-h616-hdmi-phy";
++			reg = <0x06010000 0x10000>;
++			clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>;
++			clock-names = "bus", "mod";
++			resets = <&ccu RST_BUS_HDMI_SUB>;
++			reset-names = "phy";
++			#phy-cells = <0>;
++		};
++
++		tcon_top: tcon-top@6510000 {
++			compatible = "allwinner,sun50i-h6-tcon-top";
++			reg = <0x06510000 0x1000>;
++			clocks = <&ccu CLK_BUS_TCON_TOP>,
++				 <&ccu CLK_TCON_TV0>;
++			clock-names = "bus",
++				      "tcon-tv0";
++			clock-output-names = "tcon-top-tv0";
++			resets = <&ccu RST_BUS_TCON_TOP>;
++			#clock-cells = <1>;
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				tcon_top_mixer0_in: port@0 {
++					#address-cells = <1>;
++					#size-cells = <0>;
++					reg = <0>;
++
++					tcon_top_mixer0_in_mixer0: endpoint@0 {
++						reg = <0>;
++						remote-endpoint = <&mixer0_out_tcon_top_mixer0>;
++					};
++				};
++
++				tcon_top_mixer0_out: port@1 {
++					#address-cells = <1>;
++					#size-cells = <0>;
++					reg = <1>;
++
++					tcon_top_mixer0_out_tcon_tv: endpoint@2 {
++						reg = <2>;
++						remote-endpoint = <&tcon_tv_in_tcon_top_mixer0>;
++					};
++				};
++
++				tcon_top_hdmi_in: port@4 {
++					#address-cells = <1>;
++					#size-cells = <0>;
++					reg = <4>;
++
++					tcon_top_hdmi_in_tcon_tv: endpoint@0 {
++						reg = <0>;
++						remote-endpoint = <&tcon_tv_out_tcon_top>;
++					};
++				};
++
++				tcon_top_hdmi_out: port@5 {
++					reg = <5>;
++
++					tcon_top_hdmi_out_hdmi: endpoint {
++						remote-endpoint = <&hdmi_in_tcon_top>;
++					};
++				};
++			};
++		};
++
++		tcon_tv: lcd-controller@6515000 {
++			compatible = "allwinner,sun50i-h6-tcon-tv",
++				     "allwinner,sun8i-r40-tcon-tv";
++			reg = <0x06515000 0x1000>;
++			interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_TCON_TV0>,
++				 <&tcon_top CLK_TCON_TOP_TV0>;
++			clock-names = "ahb",
++				      "tcon-ch1";
++			resets = <&ccu RST_BUS_TCON_TV0>;
++			reset-names = "lcd";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				tcon_tv_in: port@0 {
++					reg = <0>;
++
++					tcon_tv_in_tcon_top_mixer0: endpoint {
++						remote-endpoint = <&tcon_top_mixer0_out_tcon_tv>;
++					};
++				};
++
++				tcon_tv_out: port@1 {
++					#address-cells = <1>;
++					#size-cells = <0>;
++					reg = <1>;
++
++					tcon_tv_out_tcon_top: endpoint@1 {
++						reg = <1>;
++						remote-endpoint = <&tcon_top_hdmi_in_tcon_tv>;
++					};
++				};
++			};
++		};
++
+ 		rtc: rtc@7000000 {
+ 			compatible = "allwinner,sun50i-h616-rtc";
+ 			reg = <0x07000000 0x400>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-h616-add-wifi-support-for-orange-pi-zero-2-and-zero3.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-h616-add-wifi-support-for-orange-pi-zero-2-and-zero3.patch
new file mode 100644
index 000000000000..98c239c02585
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-h616-add-wifi-support-for-orange-pi-zero-2-and-zero3.patch
@@ -0,0 +1,68 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Gunjan Gupta <viraniac@gmail.com>
+Date: Wed, 13 Dec 2023 19:15:45 +0000
+Subject: arm64: dts: h616: add wifi support for orange pi zero 2 and zero3
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi | 38 ++++++++++
+ 1 file changed, 38 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
+index 8860844a4a79..061848cf8b13 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
+@@ -60,6 +60,34 @@ reg_usb1_vbus: regulator-usb1-vbus {
+ 		gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */
+ 		status = "okay";
+ 	};
++
++	reg_vcc33_wifi: vcc33-wifi {
++		/* Always on 3.3V regulator for WiFi and BT */
++		compatible = "regulator-fixed";
++		regulator-name = "vcc33-wifi";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		regulator-always-on;
++		vin-supply = <&reg_vcc5v>;
++	};
++
++	reg_vcc_wifi_io: vcc-wifi-io {
++		/* Always on 1.8V/300mA regulator for WiFi and BT IO */
++		compatible = "regulator-fixed";
++		regulator-name = "vcc-wifi-io";
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		regulator-always-on;
++		vin-supply = <&reg_vcc33_wifi>;
++	};
++
++	wifi_pwrseq: wifi-pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		clocks = <&rtc 1>;
++		clock-names = "osc32k-out";
++		reset-gpios = <&pio 6 18 GPIO_ACTIVE_LOW>; /* PG18 */
++		post-power-on-delay-ms = <200>;
++	};
+ };
+ 
+ &codec {
+@@ -101,6 +129,16 @@ &mmc0 {
+ 	status = "okay";
+ };
+ 
++&mmc1 {
++	vmmc-supply = <&reg_vcc33_wifi>;
++	vqmmc-supply = <&reg_vcc_wifi_io>;
++	mmc-pwrseq = <&wifi_pwrseq>;
++	bus-width = <4>;
++	non-removable;
++	mmc-ddr-1_8v;
++	status = "okay";
++};
++
+ &ohci1 {
+ 	status = "okay";
+ };
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-nanopi-a64-set-right-phy-mode-to-rgmii-id.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-nanopi-a64-set-right-phy-mode-to-rgmii-id.patch
new file mode 100644
index 000000000000..5e86f582a307
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-nanopi-a64-set-right-phy-mode-to-rgmii-id.patch
@@ -0,0 +1,29 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: root <guido.lehwalder@gmail.com>
+Date: Tue, 26 Jan 2021 18:17:33 +0300
+Subject: arm64:dts: nanopi-a64 set right phy-mode to rgmii-id
+
+set right phy-mode for NPI A64 to rgmii-id for working
+onboard-ethernet
+
+Signed-off-by: root <guido.lehwalder@gmail.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts
+@@ -80,7 +80,7 @@ &ehci1 {
+ &emac {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&rgmii_pins>;
+-	phy-mode = "rgmii";
++	phy-mode = "rgmii-id";
+ 	phy-handle = <&ext_rgmii_phy>;
+ 	phy-supply = <&reg_dcdc1>;
+ 	status = "okay";
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-overlay-sun50i-a64-pine64-7inch-lcd.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-overlay-sun50i-a64-pine64-7inch-lcd.patch
new file mode 100644
index 000000000000..e09f175d446e
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-overlay-sun50i-a64-pine64-7inch-lcd.patch
@@ -0,0 +1,144 @@
+From 4a77c8ac8b0e2b479e81fb817bd05fd59b2788e3 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Wed, 2 Feb 2022 20:27:02 +0300
+Subject: arm64:dts:overlay: sun50i-a64-pine64-7inch-lcd
+
+Added to orange-pi-5.9 2020-11-30
+---
+ .../arm64/boot/dts/allwinner/overlay/Makefile |  1 +
+ .../overlay/README.sun50i-a64-overlays        |  5 ++
+ .../overlay/sun50i-a64-pine64-7inch-lcd.dtso  | 87 +++++++++++++++++++
+ 3 files changed, 93 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-pine64-7inch-lcd.dtso
+
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/Makefile b/arch/arm64/boot/dts/allwinner/overlay/Makefile
+index ae404a5258a9..8d5ae3e3beb8 100644
+--- a/arch/arm64/boot/dts/allwinner/overlay/Makefile
++++ b/arch/arm64/boot/dts/allwinner/overlay/Makefile
+@@ -2,6 +2,7 @@
+ dtb-$(CONFIG_ARCH_SUNXI) += \
+ 	sun50i-a64-i2c0.dtbo \
+ 	sun50i-a64-i2c1.dtbo \
++	sun50i-a64-pine64-7inch-lcd.dtbo \
+ 	sun50i-a64-pps-gpio.dtbo \
+ 	sun50i-a64-spi-add-cs1.dtbo \
+ 	sun50i-a64-spi-jedec-nor.dtbo \
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/README.sun50i-a64-overlays b/arch/arm64/boot/dts/allwinner/overlay/README.sun50i-a64-overlays
+index cd9dbc686412..b684c2e3abb1 100644
+--- a/arch/arm64/boot/dts/allwinner/overlay/README.sun50i-a64-overlays
++++ b/arch/arm64/boot/dts/allwinner/overlay/README.sun50i-a64-overlays
+@@ -20,6 +20,7 @@ on supported boards, so this controller is not supported in provided overlays
+ 
+ - i2c0
+ - i2c1
++- pine64-7inch-lcd
+ - pps-gpio
+ - spi-add-cs1
+ - spi-jedec-nor
+@@ -44,6 +45,10 @@ Activates TWI/I2C bus 1
+ 
+ I2C1 pins (SCL, SDA): PH2, PH3
+ 
++### pine64-7inch-lcd
++
++Activates the Pine64 7" LCD on pine64/pine64so boards
++
+ ### pps-gpio
+ 
+ Activates pulse-per-second GPIO client
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-pine64-7inch-lcd.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-pine64-7inch-lcd.dtso
+new file mode 100644
+index 000000000000..34708103fe15
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-a64-pine64-7inch-lcd.dtso
+@@ -0,0 +1,87 @@
++/dts-v1/;
++/plugin/;
++
++#include <dt-bindings/interrupt-controller/irq.h>
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/pwm/pwm.h>
++
++/ {
++	compatible = "allwinner,sun50i-a64";
++
++	fragment@0 {
++		target = <&reg_ldo_io0>;
++
++		__overlay__ {
++			regulator-min-microvolt = <3300000>;
++			regulator-max-microvolt = <3300000>;
++			regulator-name = "vcc-ctp";
++			status = "okay";
++		};
++	};
++
++	fragment@1 {
++		target = <&i2c0>;
++
++		__overlay__ {
++			status = "okay";
++
++			gt911: touchscreen@5d {
++				compatible = "goodix,gt911";
++				reg = <0x5d>;
++		
++				interrupt-parent = <&pio>;
++				interrupts = <7 4 IRQ_TYPE_EDGE_RISING>; /* PH4 */
++				reset-gpios = <&pio 7 11 GPIO_ACTIVE_HIGH>; /* PH11 */
++				AVDD28-supply = <&reg_ldo_io0>;
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&r_pwm>;
++
++		__overlay__ {
++			status = "okay";
++		};
++	};
++
++	fragment@3 {
++		target-path = "/";
++
++		__overlay__ {
++			backlight: backlight {
++				compatible = "pwm-backlight";
++				pwms = <&r_pwm 0 50000 PWM_POLARITY_INVERTED>;
++				brightness-levels = <1 2 4 8 16 32 64 128 512>;
++				default-brightness-level = <8>;
++				enable-gpios = <&pio 7 10 GPIO_ACTIVE_HIGH>; /* PH10 */
++			};
++		};
++	};
++
++	fragment@4 {
++		target = <&dsi>;
++
++		__overlay__ {
++			vcc-dsi-supply = <&reg_dldo1>;
++			status = "okay";
++		
++			panel@0 {
++				compatible = "feiyang,fy07024di26a30d";
++				reg = <0>;
++				avdd-supply = <&reg_dc1sw>;
++				dvdd-supply = <&reg_dldo2>;
++				reset-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* PD24 */
++				backlight = <&backlight>;
++			};
++		};
++	};
++
++	fragment@5 {
++		target = <&dphy>;
++
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-overlay-sun50i-h5-add-gpio-regulator-overclock.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-overlay-sun50i-h5-add-gpio-regulator-overclock.patch
new file mode 100644
index 000000000000..4923538b42d4
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-overlay-sun50i-h5-add-gpio-regulator-overclock.patch
@@ -0,0 +1,220 @@
+From c5b7968c7a8250669ecf04a0b0804f8d79984925 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Wed, 2 Feb 2022 21:01:10 +0300
+Subject: arm64:dts:overlay sun50i-h5 add gpio regulator overclock
+
+---
+ .../arm64/boot/dts/allwinner/overlay/Makefile |  4 ++
+ .../sun50i-h5-cpu-clock-1.0GHz-1.1v.dtso      | 31 ++++++++++
+ .../sun50i-h5-cpu-clock-1.2GHz-1.3v.dtso      | 31 ++++++++++
+ .../sun50i-h5-cpu-clock-1.3GHz-1.3v.dtso      | 61 +++++++++++++++++++
+ .../sun50i-h5-gpio-regulator-1.3v.dtso        | 38 ++++++++++++
+ 5 files changed, 165 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.0GHz-1.1v.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.2GHz-1.3v.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.3GHz-1.3v.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-gpio-regulator-1.3v.dtso
+
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/Makefile b/arch/arm64/boot/dts/allwinner/overlay/Makefile
+index 8d5ae3e3beb8..9e3def41669e 100644
+--- a/arch/arm64/boot/dts/allwinner/overlay/Makefile
++++ b/arch/arm64/boot/dts/allwinner/overlay/Makefile
+@@ -14,6 +14,10 @@ dtb-$(CONFIG_ARCH_SUNXI) += \
+ 	sun50i-a64-w1-gpio.dtbo \
+ 	sun50i-h5-analog-codec.dtbo \
+ 	sun50i-h5-cir.dtbo \
++	sun50i-h5-cpu-clock-1.0GHz-1.1v.dtbo \
++	sun50i-h5-cpu-clock-1.2GHz-1.3v.dtbo \
++	sun50i-h5-cpu-clock-1.3GHz-1.3v.dtbo \
++	sun50i-h5-gpio-regulator-1.3v.dtbo \
+ 	sun50i-h5-i2c0.dtbo \
+ 	sun50i-h5-i2c1.dtbo \
+ 	sun50i-h5-i2c2.dtbo \
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.0GHz-1.1v.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.0GHz-1.1v.dtso
+new file mode 100644
+index 000000000000..674ec1dcbfe4
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.0GHz-1.1v.dtso
+@@ -0,0 +1,31 @@
++// DT overlay for CPU frequency operating points to up to 1.0GHz at a maximum CPU voltage of 1.1v
++
++/dts-v1/;
++/plugin/;
++
++/ {
++	fragment@0 {
++		target = <&cpu_opp_table>;
++
++		__overlay__ {
++			compatible = "operating-points-v2";
++			opp-shared;
++
++			// in order to match the H5 DT cooling-maps, update the existing OP table in-place
++			// with the new voltages
++
++			opp-960000000 {
++				opp-hz = /bits/ 64 <960000000>;
++				opp-microvolt = <1100000 1100000 1300000>;
++				clock-latency-ns = <244144>; /* 8 32k periods */
++			};
++
++			opp-1008000000 {
++				opp-hz = /bits/ 64 <1008000000>;
++				opp-microvolt = <1100000 1100000 1300000>;
++				clock-latency-ns = <244144>; /* 8 32k periods */
++			};
++		};
++	};
++};
++
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.2GHz-1.3v.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.2GHz-1.3v.dtso
+new file mode 100644
+index 000000000000..4fb5c81d31d5
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.2GHz-1.3v.dtso
+@@ -0,0 +1,31 @@
++// DT overlay for CPU frequency operating points to up to 1.2GHz at a maximum CPU voltage of 1.3v
++
++/dts-v1/;
++/plugin/;
++
++/ {
++	fragment@0 {
++		target = <&cpu_opp_table>;
++
++		__overlay__ {
++			compatible = "operating-points-v2";
++			opp-shared;
++
++			// in order to match the H5 DT cooling-maps, update the existing OP table in-place
++			// with the new voltages
++
++			opp-1104000000 {
++				opp-hz = /bits/ 64 <1104000000>;
++				opp-microvolt = <1300000 1300000 1300000>;
++				clock-latency-ns = <244144>; /* 8 32k periods */
++			};
++
++			opp-1200000000 {
++				opp-hz = /bits/ 64 <1200000000>;
++				opp-microvolt = <1300000 1300000 1300000>;
++				clock-latency-ns = <244144>; /* 8 32k periods */
++			};
++		};
++	};
++};
++
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.3GHz-1.3v.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.3GHz-1.3v.dtso
+new file mode 100644
+index 000000000000..9c633973df8b
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-cpu-clock-1.3GHz-1.3v.dtso
+@@ -0,0 +1,61 @@
++// DT overlay for CPU frequency operating points to 1.3GHz at a maximum CPU voltage of 1.3v
++
++/dts-v1/;
++/plugin/;
++
++/ {
++	fragment@0 {
++		target = <&cpu_opp_table>;
++
++		__overlay__ {
++			compatible = "operating-points-v2";
++			opp-shared;
++
++			// in order to match the H5 DT cooling-maps, update the existing OP table in-place
++			// with the new voltages
++
++			opp-1056000000 {
++				opp-hz = /bits/ 64 <1056000000>;
++				opp-microvolt = <1300000 1300000 1300000>;
++				clock-latency-ns = <244144>; /* 8 32k periods */
++			};
++
++			opp-1104000000 {
++				opp-hz = /bits/ 64 <1104000000>;
++				opp-microvolt = <1300000 1300000 1300000>;
++				clock-latency-ns = <244144>; /* 8 32k periods */
++			};
++
++			opp-1152000000 {
++				opp-hz = /bits/ 64 <1152000000>;
++				opp-microvolt = <1300000 1300000 1300000>;
++				clock-latency-ns = <244144>; /* 8 32k periods */
++			};
++
++			opp-1200000000 {
++				opp-hz = /bits/ 64 <1200000000>;
++				opp-microvolt = <1300000 1300000 1300000>;
++				clock-latency-ns = <244144>; /* 8 32k periods */
++			};
++
++			opp-1224000000 {
++				opp-hz = /bits/ 64 <1224000000>;
++				opp-microvolt = <1300000 1300000 1300000>;
++				clock-latency-ns = <244144>; /* 8 32k periods */
++			};
++
++			opp-1248000000 {
++				opp-hz = /bits/ 64 <1248000000>;
++				opp-microvolt = <1300000 1300000 1300000>;
++				clock-latency-ns = <244144>; /* 8 32k periods */
++			};
++
++			opp-1296000000 {
++				opp-hz = /bits/ 64 <1296000000>;
++				opp-microvolt = <1300000 1300000 1300000>;
++				clock-latency-ns = <244144>; /* 8 32k periods */
++			};
++		};
++	};
++};
++
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-gpio-regulator-1.3v.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-gpio-regulator-1.3v.dtso
+new file mode 100644
+index 000000000000..8d2755c3d76f
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-gpio-regulator-1.3v.dtso
+@@ -0,0 +1,38 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h5";
++
++	fragment@0 {
++		target-path = "/";
++
++		__overlay__ {
++			reg_vdd_cpux: gpio-regulator {
++				compatible = "regulator-gpio";
++				regulator-name = "vdd-cpux";
++				regulator-type = "voltage";
++				regulator-boot-on;
++				regulator-always-on;
++				regulator-min-microvolt = <1100000>;
++				regulator-max-microvolt = <1300000>;
++				regulator-ramp-delay = <50>; /* 4ms */
++
++				gpios = <&r_pio 0 6 0>; /* PL6 */
++				enable-active-high;
++				gpios-states = <0x1>;
++				states = <1100000 0x0
++					  1300000 0x1>;
++			};
++		};
++	};
++
++	fragment@1 {
++		target = <&cpu0>;
++
++		__overlay__ {
++			cpu-supply = <&reg_vdd_cpux>;
++		};
++	};
++};
++
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64-force-mmc0-bus-width.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64-force-mmc0-bus-width.patch
new file mode 100644
index 000000000000..b64aa8068965
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64-force-mmc0-bus-width.patch
@@ -0,0 +1,24 @@
+From 85906a7fbd369ed9a0f6637d1f25eb5ce71d7a4b Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Fri, 28 Jan 2022 15:52:48 +0300
+Subject: arm64:dts: sun50i-a64 force mmc0 bus-width
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+index c4272550580c..b216cd417b15 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+@@ -568,6 +568,7 @@ mmc0: mmc@1c0f000 {
+ 			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ 			max-frequency = <150000000>;
+ 			status = "disabled";
++			bus-width = <0x4>;
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+ 		};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64-olinuxino-1Ge16GW-Disable-clock-phase-and-.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64-olinuxino-1Ge16GW-Disable-clock-phase-and-.patch
new file mode 100644
index 000000000000..5c5aa3eb8d62
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64-olinuxino-1Ge16GW-Disable-clock-phase-and-.patch
@@ -0,0 +1,28 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: hehopmajieh <hehopmajieh@debian.bg>
+Date: Wed, 20 May 2020 09:25:56 +0300
+Subject: arm64:dts:sun50i-a64-olinuxino-1Ge16GW Disable clock phase and hs
+ just for test
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Ge16GW.dts | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Ge16GW.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Ge16GW.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Ge16GW.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Ge16GW.dts
+@@ -15,8 +15,8 @@ / {
+ 
+ &mmc2 {
+ 	vqmmc-supply = <&reg_eldo1>;
+-	mmc-hs200-1_8v;
+-	allwinner,drive-data-phase = <180>;
++/*	mmc-hs200-1_8v;
++	allwinner,drive-data-phase = <180>;*/
+ };
+ 
+ &pio {
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64-olinuxino-1Ge16GW-enable-bluetooth.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64-olinuxino-1Ge16GW-enable-bluetooth.patch
new file mode 100644
index 000000000000..ef70980db0f4
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64-olinuxino-1Ge16GW-enable-bluetooth.patch
@@ -0,0 +1,41 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Stefan Saraev <stefan@saraev.ca>
+Date: Fri, 20 Mar 2020 17:31:49 +0200
+Subject: arm64:dts: sun50i-a64-olinuxino-1Ge16GW: enable bluetooth
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Ge16GW.dts | 21 ++++++++++
+ 1 file changed, 21 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Ge16GW.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Ge16GW.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Ge16GW.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Ge16GW.dts
+@@ -18,3 +18,24 @@ &mmc2 {
+ 	mmc-hs200-1_8v;
+ 	allwinner,drive-data-phase = <180>;
+ };
++
++&pio {
++	vcc-pc-supply = <&reg_eldo1>;
++	uart1_cts_pins: uart1_cts_pins {
++		pins = "PG8";
++		function = "uart1";
++	};
++};
++
++&uart1 {
++        pinctrl-names = "default";
++        pinctrl-0 = <&uart1_pins>, <&uart1_cts_pins>;
++        status = "okay";
++        bluetooth {
++                compatible = "realtek,rtl8723bs-bt";
++                reset-gpios = <&r_pio 0 4 GPIO_ACTIVE_LOW>; /* PL4 */
++                device-wake-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */
++                host-wake-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
++                firmware-postfix = "olinuxino";
++        };
++};
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64-olinuxino-add-boards.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64-olinuxino-add-boards.patch
new file mode 100644
index 000000000000..caf5c497f6f8
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64-olinuxino-add-boards.patch
@@ -0,0 +1,603 @@
+From b94c32c09b848a2b678554a39e81e31cb0ee5ea0 Mon Sep 17 00:00:00 2001
+From: Mitko Gamishev <hehopmajieh@debian.bg>
+Date: Wed, 5 Feb 2020 15:03:08 +0200
+Subject: arm64:dts:sun50i-a64-olinuxino add boards
+
+---
+ arch/arm64/boot/dts/allwinner/Makefile        |   5 +
+ .../dts/allwinner/sun50i-a64-olinuxino-1G.dts | 362 ++++++++++++++++++
+ .../sun50i-a64-olinuxino-1Ge16GW.dts          |  20 +
+ .../allwinner/sun50i-a64-olinuxino-1Ge4GW.dts |  97 +++++
+ .../allwinner/sun50i-a64-olinuxino-1Gs16M.dts |  31 ++
+ .../allwinner/sun50i-a64-olinuxino-2Ge8G.dts  |  25 ++
+ 6 files changed, 540 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1G.dts
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Ge16GW.dts
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Ge4GW.dts
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Gs16M.dts
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-2Ge8G.dts
+
+diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
+index 80098fa014ac..3280927df6e0 100644
+--- a/arch/arm64/boot/dts/allwinner/Makefile
++++ b/arch/arm64/boot/dts/allwinner/Makefile
+@@ -5,6 +5,11 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-nanopi-a64.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-oceanic-5205-5inmfd.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-olinuxino.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-olinuxino-emmc.dtb
++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-olinuxino-1G.dtb
++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-olinuxino-1Ge4GW.dtb
++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-olinuxino-1Ge16GW.dtb
++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-olinuxino-1Gs16M.dtb
++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-olinuxino-2Ge8G.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-orangepi-win.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-lts.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-plus.dtb sun50i-a64-pine64.dtb
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1G.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1G.dts
+new file mode 100644
+index 000000000000..54af704d2c68
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1G.dts
+@@ -0,0 +1,362 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (C) 2019 OLIMEX Ltd.
++ *
++ */
++
++/dts-v1/;
++
++#include "sun50i-a64.dtsi"
++
++#include <dt-bindings/gpio/gpio.h>
++
++/ {
++	model = "Olimex A64-Olinuxino-1G";
++	compatible = "olimex,a64-olinuxino-1g", "allwinner,sun50i-a64";
++
++	aliases {
++		ethernet0 = &emac;
++		serial0 = &uart0;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	hdmi-connector {
++		compatible = "hdmi-connector";
++		type = "a";
++
++		port {
++			hdmi_con_in: endpoint {
++				remote-endpoint = <&hdmi_out_con>;
++			};
++		};
++	};
++
++	hdmi-sound {
++		compatible = "simple-audio-card";
++		simple-audio-card,format = "i2s";
++		simple-audio-card,name = "allwinner,hdmi";
++		simple-audio-card,mclk-fs = <256>;
++		status = "okay";
++
++		simple-audio-card,codec {
++			sound-dai = <&hdmi>;
++		};
++
++		simple-audio-card,cpu {
++			sound-dai = <&i2s2>;
++		};
++	};
++
++	reg_vcc_sys: vcc-sys {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc-sys";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		regulator-always-on;
++		status = "okay";
++	};
++
++	reg_usb1_vbus: usb1-vbus {
++		compatible = "regulator-fixed";
++		regulator-name = "usb1-vbus";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		regulator-always-on;
++		enable-active-high;
++		gpio = <&pio 6 9 GPIO_ACTIVE_HIGH>; /* PG9 */
++		status = "okay";
++	};
++};
++
++&codec {
++	status = "okay";
++};
++
++&codec_analog {
++	hpvcc-supply = <&reg_eldo1>;
++	status = "okay";
++};
++
++&dai {
++	status = "okay";
++};
++
++&de {
++	status = "okay";
++};
++
++&ehci0 {
++	status = "okay";
++};
++
++&ehci1 {
++	status = "okay";
++};
++
++&emac {
++	pinctrl-names = "default";
++	pinctrl-0 = <&rgmii_pins>;
++	phy-mode = "rgmii";
++	phy-handle = <&ext_rgmii_phy>;
++	phy-supply = <&reg_dcdc1>;
++	allwinner,tx-delay-ps = <600>;
++	status = "okay";
++};
++
++&hdmi {
++	hvcc-supply = <&reg_dldo1>;
++	status = "okay";
++};
++
++&hdmi_out {
++	hdmi_out_con: endpoint {
++		remote-endpoint = <&hdmi_con_in>;
++	};
++};
++
++/* Exposed to UEXT connector */
++&i2c1 {
++	#address-cells = <1>;
++	#size-cells = <0>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c1_pins>;
++	status = "disabled";
++};
++
++&i2s2 {
++	status = "okay";
++};
++
++&mdio {
++	ext_rgmii_phy: ethernet-phy@1 {
++		compatible = "ethernet-phy-ieee802.3-c22";
++		reg = <1>;
++	};
++};
++
++&mmc0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&mmc0_pins>;
++	vmmc-supply = <&reg_dcdc1>;
++	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
++	disable-wp;
++	bus-width = <4>;
++	status = "okay";
++};
++
++&ohci0 {
++	status = "okay";
++};
++
++&ohci1 {
++	status = "okay";
++};
++
++&r_rsb {
++	status = "okay";
++
++	axp803: pmic@3a3 {
++		compatible = "x-powers,axp803";
++		reg = <0x3a3>;
++		interrupt-parent = <&r_intc>;
++		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_LOW>;
++		x-powers,drive-vbus-en;	/* set N_VBUSEN as output pin */
++	};
++};
++
++#include "axp803.dtsi"
++
++&ac_power_supply {
++	status = "okay";
++};
++
++&axp_led {
++	label = "axp20x:yellow:chgled";
++	status = "okay";
++	x-powers,charger-mode = <0>;
++};
++
++&battery_power_supply {
++	status = "okay";
++};
++
++&reg_aldo1 {
++	regulator-always-on;
++	regulator-min-microvolt = <2800000>;
++	regulator-max-microvolt = <2800000>;
++	regulator-name = "vcc-pe";
++};
++
++&reg_aldo2 {
++	regulator-always-on;
++	regulator-min-microvolt = <3300000>;
++	regulator-max-microvolt = <3300000>;
++	regulator-name = "vcc-pl";
++};
++
++&reg_aldo3 {
++	regulator-always-on;
++	regulator-min-microvolt = <3000000>;
++	regulator-max-microvolt = <3000000>;
++	regulator-name = "vcc-pll-avcc";
++};
++
++&reg_dcdc1 {
++	regulator-always-on;
++	regulator-min-microvolt = <3300000>;
++	regulator-max-microvolt = <3300000>;
++	regulator-name = "vcc-3v3";
++};
++
++&reg_dcdc2 {
++	regulator-always-on;
++	regulator-min-microvolt = <1040000>;
++	regulator-max-microvolt = <1300000>;
++	regulator-name = "vdd-cpux";
++};
++
++/* DCDC3 is polyphased with DCDC2 */
++
++/*
++ * The board uses DDR3L DRAM chips. 1.36V is the closest to the nominal
++ * 1.35V that the PMIC can drive.
++ */
++&reg_dcdc5 {
++	regulator-always-on;
++	regulator-min-microvolt = <1360000>;
++	regulator-max-microvolt = <1360000>;
++	regulator-name = "vcc-ddr3";
++};
++
++&reg_dcdc6 {
++	regulator-always-on;
++	regulator-min-microvolt = <1100000>;
++	regulator-max-microvolt = <1100000>;
++	regulator-name = "vdd-sys";
++};
++
++&reg_dldo1 {
++	regulator-min-microvolt = <3300000>;
++	regulator-max-microvolt = <3300000>;
++	regulator-name = "vcc-hdmi";
++};
++
++&reg_dldo2 {
++	regulator-min-microvolt = <3300000>;
++	regulator-max-microvolt = <3300000>;
++	regulator-name = "vcc-mipi";
++};
++
++&reg_dldo3 {
++	regulator-min-microvolt = <2800000>;
++	regulator-max-microvolt = <2800000>;
++	regulator-name = "vcc-avdd-csi";
++};
++
++&reg_dldo4 {
++	regulator-always-on;
++	regulator-min-microvolt = <3300000>;
++	regulator-max-microvolt = <3300000>;
++	regulator-name = "vcc-wifi-io";
++};
++
++&reg_drivevbus {
++	regulator-name = "usb0-vbus";
++	status = "okay";
++};
++
++&reg_eldo1 {
++	regulator-always-on;
++	regulator-min-microvolt = <1800000>;
++	regulator-max-microvolt = <1800000>;
++	regulator-name = "vcc-emmc";
++};
++
++&reg_eldo2 {
++	regulator-min-microvolt = <1800000>;
++	regulator-max-microvolt = <1800000>;
++	regulator-name = "vcc-dvdd-csi";
++};
++
++&reg_fldo1 {
++	regulator-min-microvolt = <1200000>;
++	regulator-max-microvolt = <1200000>;
++	regulator-name = "vcc-1v2-hsic";
++};
++
++/*
++ * The A64 chip cannot work without this regulator off, although
++ * it seems to be only driving the AR100 core.
++ * Maybe we don't still know well about CPUs domain.
++ */
++&reg_fldo2 {
++	regulator-always-on;
++	regulator-min-microvolt = <1100000>;
++	regulator-max-microvolt = <1100000>;
++	regulator-name = "vdd-cpus";
++};
++
++&reg_rtc_ldo {
++	regulator-name = "vcc-rtc";
++};
++
++&simplefb_hdmi {
++	vcc-hdmi-supply = <&reg_dldo1>;
++};
++
++&sound {
++	simple-audio-card,aux-devs = <&codec_analog>;
++	simple-audio-card,widgets = "Microphone", "Microphone Jack Left",
++				    "Microphone", "Microphone Jack Right",
++				    "Headphone", "Headphone Jack";
++	simple-audio-card,routing = "Left DAC", "AIF1 Slot 0 Left",
++				    "Right DAC", "AIF1 Slot 0 Right",
++				    "Headphone Jack", "HP",
++				    "AIF1 Slot 0 Left ADC", "Left ADC",
++				    "AIF1 Slot 0 Right ADC", "Right ADC",
++				    "Microphone Jack Left", "MBIAS",
++				    "MIC1", "Microphone Jack Left",
++				    "Microphone Jack Left", "HBIAS",
++				    "MIC2", "Microphone Jack Right";
++	status = "okay";
++};
++
++&spdif {
++	status = "disabled";
++};
++
++/* Exposed on UEXT */
++&spi0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&spi0_pins>;
++	status = "disabled";
++};
++
++&uart0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart0_pb_pins>;
++	status = "okay";
++};
++
++/* Exposed on UEXT */
++&uart3 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart3_pins>;
++	status = "disabled";
++};
++
++&usb_otg {
++	dr_mode = "otg";
++	status = "okay";
++};
++
++&usbphy {
++	status = "okay";
++	usb0_id_det-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */
++	usb0_vbus_det-gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
++	usb0_vbus-supply = <&reg_drivevbus>;
++	usb1_vbus-supply = <&reg_usb1_vbus>;
++};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Ge16GW.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Ge16GW.dts
+new file mode 100644
+index 000000000000..a508d77d2c09
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Ge16GW.dts
+@@ -0,0 +1,20 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (C) 2019 OLIMEX Ltd.
++ *
++ */
++
++/dts-v1/;
++
++#include "sun50i-a64-olinuxino-1Ge4GW.dts"
++
++/ {
++	model = "Olimex A64-Olinuxino-1Ge16GW";
++	compatible = "olimex,a64-olinuxino-1ge16gw", "allwinner,sun50i-a64";
++};
++
++&mmc2 {
++	vqmmc-supply = <&reg_eldo1>;
++	mmc-hs200-1_8v;
++	allwinner,drive-data-phase = <180>;
++};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Ge4GW.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Ge4GW.dts
+new file mode 100644
+index 000000000000..c87ecc6e1d8f
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Ge4GW.dts
+@@ -0,0 +1,97 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (C) 2019 OLIMEX Ltd.
++ *
++ */
++
++/dts-v1/;
++
++#include "sun50i-a64-olinuxino-1G.dts"
++
++/ {
++	model = "Olimex A64-Olinuxino-1Ge4GW";
++	compatible = "olimex,a64-olinuxino-1ge4gw", "allwinner,sun50i-a64";
++
++	aliases {
++		ethernet1 = &rtl8723bs;
++		mmc1 = &mmc2;
++	};
++
++	bt-sound {
++		compatible = "simple-audio-card";
++		simple-audio-card,format = "i2s";
++		simple-audio-card,bitclock-inversion = <1>;
++		simple-audio-card,mclk-fs = <256>;
++		simple-audio-card,name = "RTL8723BS";
++		simple-audio-card,cpu {
++			sound-dai = <&i2s1>;
++		};
++		simple-audio-card,codec {
++			sound-dai = <&bt_sco>;
++		};
++	};
++
++	bt_sco: bt-sco {
++		compatible = "linux,bt-sco";
++		#sound-dai-cells = <0>;
++		status = "okay";
++	};
++
++	wifi_pwrseq: wifi_pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
++	};
++};
++
++&i2s1 {
++	status = "okay";
++};
++
++&mmc1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&mmc1_pins>;
++	vmmc-supply = <&reg_aldo2>;
++	vqmmc-supply = <&reg_dldo4>;
++	mmc-pwrseq = <&wifi_pwrseq>;
++	bus-width = <4>;
++	non-removable;
++	status = "okay";
++
++	rtl8723bs: wifi@1 {
++		reg = <1>;
++		interrupt-parent = <&r_pio>;
++		interrupts = <0 3 IRQ_TYPE_LEVEL_LOW>; /* PL3 */
++		interrupt-names = "host-wake";
++	};
++};
++
++&mmc2 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&mmc2_pins>;
++	vmmc-supply = <&reg_dcdc1>;
++	vqmmc-supply = <&reg_dcdc1>;
++	bus-width = <8>;
++	non-removable;
++	cap-mmc-hw-reset;
++	status = "okay";
++};
++
++&pio {
++	uart1_cts_pins: uart1_cts_pins {
++		pins = "PG8";
++		function = "uart1";
++	};
++};
++
++&uart1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart1_pins>, <&uart1_cts_pins>;
++	status = "okay";
++	bluetooth {
++		compatible = "realtek,rtl8723bs-bt";
++		reset-gpios = <&r_pio 0 4 GPIO_ACTIVE_LOW>; /* PL4 */
++		device-wake-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */
++		host-wake-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
++		firmware-postfix = "olinuxino";
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Gs16M.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Gs16M.dts
+new file mode 100644
+index 000000000000..5b85f4d2b05f
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-1Gs16M.dts
+@@ -0,0 +1,31 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (C) 2019 OLIMEX Ltd.
++ *
++ */
++
++/dts-v1/;
++
++#include "sun50i-a64-olinuxino-1G.dts"
++
++/ {
++	model = "Olimex A64-Olinuxino-1Gs16M";
++	compatible = "olimex,a64-olinuxino-1gs16m", "allwinner,sun50i-a64";
++
++	aliases {
++		spi0 = &spi0;
++	};
++};
++
++&spi0 {
++	status = "okay";
++
++	spi-nor@0 {
++		#address-cells = <1>;
++		#size-cells = <1>;
++		compatible = "winbond,w25q128", "jedec,spi-nor", "spi-flash";
++		reg = <0>;
++		spi-max-frequency = <10000000>;
++		status = "okay";
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-2Ge8G.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-2Ge8G.dts
+new file mode 100644
+index 000000000000..3583c37d3930
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-2Ge8G.dts
+@@ -0,0 +1,25 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (C) 2019 OLIMEX Ltd.
++ *
++ */
++
++/dts-v1/;
++
++#include "sun50i-a64-olinuxino-1G.dts"
++
++/ {
++	model = "Olimex A64-Olinuxino-2Ge8G-IND";
++	compatible = "olimex,a64-olinuxino-2ge8g", "allwinner,sun50i-a64";
++};
++
++&mmc2 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&mmc2_pins>;
++	vmmc-supply = <&reg_dcdc1>;
++	vqmmc-supply = <&reg_dcdc1>;
++	bus-width = <8>;
++	non-removable;
++	cap-mmc-hw-reset;
++	status = "okay";
++};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64-olinuxino-emmc-enable-bluetooth.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64-olinuxino-emmc-enable-bluetooth.patch
new file mode 100644
index 000000000000..c21e5e8c13f8
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64-olinuxino-emmc-enable-bluetooth.patch
@@ -0,0 +1,38 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Stefan Saraev <stefan@saraev.ca>
+Date: Fri, 20 Mar 2020 13:53:44 +0200
+Subject: arm64:dts: sun50i-a64-olinuxino-emmc: enable bluetooth
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-emmc.dts | 17 ++++++++++
+ 1 file changed, 17 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-emmc.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-emmc.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-emmc.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino-emmc.dts
+@@ -22,4 +22,21 @@ &mmc2 {
+ 
+ &pio {
+ 	vcc-pc-supply = <&reg_eldo1>;
++	uart1_cts_pins: uart1_cts_pins {
++		pins = "PG8";
++		function = "uart1";
++	};
++};
++
++&uart1 {
++        pinctrl-names = "default";
++        pinctrl-0 = <&uart1_pins>, <&uart1_cts_pins>;
++        status = "okay";
++        bluetooth {
++                compatible = "realtek,rtl8723bs-bt";
++                reset-gpios = <&r_pio 0 4 GPIO_ACTIVE_LOW>; /* PL4 */
++                device-wake-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */
++                host-wake-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
++                firmware-postfix = "olinuxino";
++        };
+ };
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64-orangepi-win-add-aliase-ethernet1.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64-orangepi-win-add-aliase-ethernet1.patch
new file mode 100644
index 000000000000..5004fffe34b3
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64-orangepi-win-add-aliase-ethernet1.patch
@@ -0,0 +1,24 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Fri, 28 Jan 2022 15:48:25 +0300
+Subject: arm64:dts: sun50i-a64-orangepi-win add aliase ethernet1
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
+@@ -15,6 +15,7 @@ / {
+ 
+ 	aliases {
+ 		ethernet0 = &emac;
++		ethernet1 = &brcmf;
+ 		serial0 = &uart0;
+ 		serial1 = &uart1;
+ 		serial2 = &uart2;
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64-pine64-add-spi0.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64-pine64-add-spi0.patch
new file mode 100644
index 000000000000..9b00281e294e
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64-pine64-add-spi0.patch
@@ -0,0 +1,49 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Tue, 25 Jan 2022 19:10:06 +0300
+Subject: arm64:dts: sun50i-a64-pine64 add spi0
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 29 ++++++++++
+ 1 file changed, 29 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+@@ -350,3 +350,32 @@ &usb_otg {
+ &usbphy {
+ 	status = "okay";
+ };
++
++&spi0 {
++        status = "okay";
++        spi-flash@0 {
++                #address-cells = <1>;
++                #size-cells = <0>;
++                compatible = "jedec,spi-nor";
++                reg = <0>; /* Chip select 0 */
++                spi-max-frequency = <10000000>;
++                status = "disabled";
++                partitions {
++                        compatible = "fixed-partitions";
++                        #address-cells = <1>;
++                        #size-cells = <1>;
++                        partition@0 {
++                                label = "uboot";
++                                reg = <0x0 0x100000>;
++                        };
++                        partition@100000 {
++                                label = "env";
++                                reg = <0x100000 0x100000>;
++                        };
++                        partition@200000 {
++                                label = "data";
++                                reg = <0x200000 0x200000>;
++                        };
++                };
++        };
++};
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64-pine64-enable-Bluetooth.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64-pine64-enable-Bluetooth.patch
new file mode 100644
index 000000000000..5589ae0ff4c0
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64-pine64-enable-Bluetooth.patch
@@ -0,0 +1,40 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Vasily Khoruzhick <anarsoul@gmail.com>
+Date: Wed, 31 Oct 2018 20:45:16 -0700
+Subject: arm64:dts: sun50i-a64-pine64 enable Bluetooth
+
+Pine64 has optional RTL8723BS WiFi + BT module, BT is connected to UART1
+and uses PL4 as BT reset, PL5 as device wake GPIO, PL6 as host wake GPIO
+the I2C controlling signals are connected to R_I2C bus.
+
+Enable it in the device tree.
+
+Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 10 +++++++++-
+ 1 file changed, 9 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+@@ -310,7 +310,15 @@ &uart0 {
+ &uart1 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
+-	status = "disabled";
++	status = "okay";
++
++	bluetooth {
++		compatible = "realtek,rtl8723bs-bt";
++		reset-gpios = <&r_pio 0 4 GPIO_ACTIVE_LOW>; /* PL4 */
++		device-wake-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */
++		host-wake-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
++		firmware-postfix = "pine64";
++	};
+ };
+ 
+ /* On Pi-2 connector */
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64-pine64-enable-wifi-mmc1.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64-pine64-enable-wifi-mmc1.patch
new file mode 100644
index 000000000000..d12e8c3556e2
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64-pine64-enable-wifi-mmc1.patch
@@ -0,0 +1,52 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Icenowy Zheng <icenowy@aosc.io>
+Date: Thu, 9 Feb 2017 00:18:56 +0800
+Subject: arm64:dts: sun50i-a64-pine64 enable wifi mmc1
+
+The Wi-Fi modules of Pine64 is powered via DLDO4 and ELDO1 (the latter
+one provides I/O voltage).
+
+Add device node for it.
+
+Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 16 ++++++++++
+ 1 file changed, 16 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+@@ -35,6 +35,11 @@ hdmi_con_in: endpoint {
+ 			};
+ 		};
+ 	};
++
++	wifi_pwrseq: wifi_pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 */
++	};
+ };
+ 
+ &codec {
+@@ -128,6 +133,17 @@ &mmc0 {
+ 	status = "okay";
+ };
+ 
++&mmc1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&mmc1_pins>;
++	vmmc-supply = <&reg_dldo4>;
++	vqmmc-supply = <&reg_eldo1>;
++	mmc-pwrseq = <&wifi_pwrseq>;
++	non-removable;
++	bus-width = <4>;
++	status = "okay";
++};
++
+ &ohci0 {
+ 	status = "okay";
+ };
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64-sopine-baseboard-Add-i2s2-mmc1.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64-sopine-baseboard-Add-i2s2-mmc1.patch
new file mode 100644
index 000000000000..9fcb2b688034
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64-sopine-baseboard-Add-i2s2-mmc1.patch
@@ -0,0 +1,44 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Vasily Khoruzhick <anarsoul@gmail.com>
+Date: Sun, 3 Dec 2017 11:43:08 -0800
+Subject: arm64:dts: sun50i-a64-sopine-baseboard Add i2s2 mmc1
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts | 14 ++++++++++
+ 1 file changed, 14 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
+@@ -100,6 +100,10 @@ &i2s2 {
+ 	status = "okay";
+ };
+ 
++&i2s2 {
++	status = "okay";
++};
++
+ &mdio {
+ 	ext_rgmii_phy: ethernet-phy@1 {
+ 		compatible = "ethernet-phy-ieee802.3-c22";
+@@ -107,6 +111,16 @@ ext_rgmii_phy: ethernet-phy@1 {
+ 	};
+ };
+ 
++&mmc1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&mmc1_pins>;
++	vmmc-supply = <&reg_dldo4>;
++	vqmmc-supply = <&reg_eldo1>;
++	non-removable;
++	bus-width = <4>;
++	status = "okay";
++};
++
+ &mmc2 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&mmc2_pins>;
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64-sopine-baseboard-enable-Bluetooth.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64-sopine-baseboard-enable-Bluetooth.patch
new file mode 100644
index 000000000000..2727f6033233
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64-sopine-baseboard-enable-Bluetooth.patch
@@ -0,0 +1,44 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Vasily Khoruzhick <anarsoul@gmail.com>
+Date: Wed, 31 Oct 2018 20:50:09 -0700
+Subject: arm64:dts: sun50i-a64-sopine-baseboard enable Bluetooth
+
+SoPine has optional RTL8723BS WiFi + BT module, BT is connected to UART1
+and uses PL4 as BT reset, PL5 as device wake GPIO, PL6 as host wake GPIO
+the I2C controlling signals are connected to R_I2C bus.
+
+Enable it in the device tree.
+
+Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts | 14 ++++++++++
+ 1 file changed, 14 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
+@@ -197,6 +197,20 @@ &uart0 {
+ 	status = "okay";
+ };
+ 
++&uart1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
++	status = "okay";
++
++	bluetooth {
++		compatible = "realtek,rtl8723bs-bt";
++		reset-gpios = <&r_pio 0 4 GPIO_ACTIVE_LOW>; /* PL4 */
++		device-wake-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */
++		host-wake-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
++		firmware-postfix = "pine64";
++	};
++};
++
+ /* On Pi-2 connector */
+ &uart2 {
+ 	pinctrl-names = "default";
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64.dtsi-adjust-thermal-trip-points.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64.dtsi-adjust-thermal-trip-points.patch
new file mode 100644
index 000000000000..aa80a91e9d0f
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-a64.dtsi-adjust-thermal-trip-points.patch
@@ -0,0 +1,42 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Stefan Saraev <stefan@saraev.ca>
+Date: Mon, 6 Apr 2020 15:26:10 +0300
+Subject: arm64:dts:sun50i-a64.dtsi adjust thermal trip points
+
+default values for alert1/crit are way too high.
+---
+ arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+@@ -257,21 +257,21 @@ map1 {
+ 			trips {
+ 				cpu_alert0: cpu-alert0 {
+ 					/* milliCelsius */
+-					temperature = <75000>;
++					temperature = <70000>;
+ 					hysteresis = <2000>;
+ 					type = "passive";
+ 				};
+ 
+ 				cpu_alert1: cpu-alert1 {
+ 					/* milliCelsius */
+-					temperature = <90000>;
++					temperature = <80000>;
+ 					hysteresis = <2000>;
+ 					type = "hot";
+ 				};
+ 
+ 				cpu_crit: cpu-crit {
+ 					/* milliCelsius */
+-					temperature = <110000>;
++					temperature = <90000>;
+ 					hysteresis = <2000>;
+ 					type = "critical";
+ 				};
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h313-x96q-lpddr3.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h313-x96q-lpddr3.patch
new file mode 100644
index 000000000000..97a422a4d4f3
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h313-x96q-lpddr3.patch
@@ -0,0 +1,441 @@
+From 2729354bb6f8fed58045c8b26650402e98bdc77f Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Sat, 21 Sep 2024 11:28:33 +0300
+Subject: arm64: dts: sun50i-h313-x96q-lpddr3
+
+Add support X96Q TV Box LPDDR3 H313
+
+Author: sicXnull <notifications@github.com>
+Signed-off-by: The-going <48602507+The-going@users.noreply.github.com>
+---
+ arch/arm64/boot/dts/allwinner/Makefile        |   1 +
+ .../dts/allwinner/sun50i-h313-cpu-opp.dtsi    |  92 ++++++
+ .../dts/allwinner/sun50i-h313-x96q-lpddr3.dts | 305 ++++++++++++++++++
+ 3 files changed, 398 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h313-cpu-opp.dtsi
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h313-x96q-lpddr3.dts
+
+diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
+index 95d2886defc8..67f738f9b513 100644
+--- a/arch/arm64/boot/dts/allwinner/Makefile
++++ b/arch/arm64/boot/dts/allwinner/Makefile
+@@ -52,6 +52,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-inovato-quadra.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6-mini.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h313-tanix-tx1.dtb
++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h313-x96q-lpddr3.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-bigtreetech-cb1-manta.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-bigtreetech-cb1-sd.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-bigtreetech-cb1-emmc.dtb
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h313-cpu-opp.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h313-cpu-opp.dtsi
+new file mode 100644
+index 000000000000..0ad85cf1b393
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h313-cpu-opp.dtsi
+@@ -0,0 +1,92 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++// Copyright (C) 2021 Piotr Oniszczuk <piotr.oniszczuk@gmail.com>
++
++/*
++	X96-q DDR3 vendor Android DT:
++	480000000	900mV
++	600000000	900mV
++	792000000	900mV
++	1008000000	920mV
++	1200000000	980mV
++	1344000000	1120mV
++	1416000000	1140mV
++	1512000000	1160mV
++*/
++
++/ {
++	cpu_opp_table: opp-table-cpu {
++		compatible = "allwinner,sun50i-h616-operating-points";
++		nvmem-cells = <&cpu_speed_grade>;
++		opp-shared;
++
++		opp-480000000 {
++			clock-latency-ns = <244144>; /* 8 32k periods */
++			opp-hz = /bits/ 64 <480000000>;
++
++			opp-microvolt-speed0 = <900000 900000 1100000>;
++			opp-microvolt-speed1 = <900000 900000 1100000>;
++			opp-microvolt-speed2 = <900000 900000 1100000>;
++		};
++
++		opp-600000000 {
++			clock-latency-ns = <244144>; /* 8 32k periods */
++			opp-hz = /bits/ 64 <600000000>;
++
++			opp-microvolt-speed0 = <900000 900000 1100000>;
++			opp-microvolt-speed1 = <900000 900000 1100000>;
++			opp-microvolt-speed2 = <900000 900000 1100000>;
++		};
++
++		opp-792000000 {
++			clock-latency-ns = <244144>; /* 8 32k periods */
++			opp-hz = /bits/ 64 <792000000>;
++
++			opp-microvolt-speed0 = <900000 900000 1100000>;
++			opp-microvolt-speed1 = <900000 900000 1100000>;
++			opp-microvolt-speed2 = <900000 900000 1100000>;
++		};
++
++		opp-1008000000 {
++			clock-latency-ns = <244144>; /* 8 32k periods */
++			opp-hz = /bits/ 64 <1008000000>;
++
++			opp-microvolt-speed0 = <920000 920000 1100000>;
++			opp-microvolt-speed1 = <920000 920000 1100000>;
++			opp-microvolt-speed2 = <920000 920000 1100000>;
++		};
++
++		opp-1200000000 {
++			clock-latency-ns = <244144>; /* 8 32k periods */
++			opp-hz = /bits/ 64 <1200000000>;
++
++			opp-microvolt-speed0 = <980000 980000 1100000>;
++			opp-microvolt-speed1 = <980000 980000 1100000>;
++			opp-microvolt-speed2 = <980000 980000 1100000>;
++		};
++
++		opp-1512000000 {
++			clock-latency-ns = <244144>; /* 8 32k periods */
++			opp-hz = /bits/ 64 <1512000000>;
++
++			opp-microvolt-speed0 = <1100000 1100000 1100000>;
++			opp-microvolt-speed1 = <1100000 1100000 1100000>;
++			opp-microvolt-speed2 = <1100000 1100000 1100000>;
++		};
++	};
++};
++
++&cpu0 {
++	operating-points-v2 = <&cpu_opp_table>;
++};
++
++&cpu1 {
++	operating-points-v2 = <&cpu_opp_table>;
++};
++
++&cpu2 {
++	operating-points-v2 = <&cpu_opp_table>;
++};
++
++&cpu3 {
++	operating-points-v2 = <&cpu_opp_table>;
++};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h313-x96q-lpddr3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h313-x96q-lpddr3.dts
+new file mode 100644
+index 000000000000..4b1faad0e88c
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h313-x96q-lpddr3.dts
+@@ -0,0 +1,305 @@
++// SPDX-License-Identifier: (GPL-2.0+ or MIT)
++/*
++ * Author: piotr.oniszczuk@gmail.com
++ */
++
++/dts-v1/;
++
++#include "sun50i-h616.dtsi"
++#include "sun50i-h313-cpu-opp.dtsi"
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/interrupt-controller/arm-gic.h>
++#include <dt-bindings/leds/common.h>
++
++/ {
++	model = "X96Q TV-Box LPDDR3";
++	compatible = "hechuang,x96-q", "allwinner,sun50i-h616";
++
++	aliases {
++		mmc0 = &mmc0;
++		mmc2 = &mmc2;
++		ethernet0 = &emac1;
++		ethernet1 = &wlan;
++		serial0 = &uart0;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	connector {
++		compatible = "hdmi-connector";
++		type = "d";
++
++		port {
++			hdmi_con_in: endpoint {
++				remote-endpoint = <&hdmi_out_con>;
++			};
++		};
++	};
++
++	leds {
++		compatible = "gpio-leds";
++
++		led-red {
++			function = LED_FUNCTION_DISK_ACTIVITY;
++			color = <LED_COLOR_ID_RED>;
++			gpios = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
++			linux,default-trigger = "mmc0";
++		};
++	};
++
++	reg_vcc5v: vcc5v {
++		/* board wide 5V supply directly from the USB-C socket */
++		compatible = "regulator-fixed";
++		regulator-name = "vcc-5v";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		regulator-always-on;
++	};
++
++	reg_usb1_vbus: usb1-vbus {
++		compatible = "regulator-fixed";
++		regulator-name = "usb1-vbus";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		vin-supply = <&reg_vcc5v>;
++		enable-active-high;
++		/* gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; PC16 */
++		status = "okay";
++	};
++
++	reg_vcc_wifi: reg_vcc_wifi {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc-wifi";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		gpio = <&pio 6 18 GPIO_ACTIVE_HIGH>; /* PG18 WL_REG_ON */
++		regulator-always-on;
++		enable-active-high;
++		status = "okay";
++	};
++
++	wifi_pwrseq: wifi-pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		clocks = <&rtc 1>;
++		clock-names = "osc32k-out";
++		reset-gpios = <&pio 6 18 GPIO_ACTIVE_LOW>; /* PG18 */
++		post-power-on-delay-ms = <200>;
++	};
++};
++
++&cpu0 {
++	cpu-supply = <&reg_dcdc2>;
++	status = "okay";
++};
++
++&de {
++	status = "okay";
++};
++
++&ehci0 {
++	status = "okay";
++};
++
++&ehci1 {
++	status = "okay";
++};
++
++&ehci2 {
++	status = "okay";
++};
++
++&ehci3 {
++	status = "okay";
++};
++
++&hdmi {
++	hvcc-supply = <&reg_aldo1>;
++	status = "okay";
++};
++
++&hdmi_out {
++	hdmi_out_con: endpoint {
++		remote-endpoint = <&hdmi_con_in>;
++	};
++};
++
++&gpu {
++	mali-supply = <&reg_dcdc1>;
++	status = "okay";
++};
++
++&emac1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&rmii_pins>;
++	phy-mode = "rmii";
++	phy-handle = <&rmii_phy>;
++	phy-supply = <&reg_aldo1>;
++	allwinner,rx-delay-ps = <3100>;
++	allwinner,tx-delay-ps = <700>;
++	status = "okay";
++};
++
++&mdio1 {
++	rmii_phy: ethernet-phy@0 {
++		compatible = "ethernet-phy-ieee802.3-c22";
++		reg = <0>;
++	};
++};
++
++&mmc0 {
++	vmmc-supply = <&reg_dldo1>;
++	broken-cd;
++	bus-width = <4>;
++	status = "okay";
++};
++
++&mmc1 {
++	vmmc-supply = <&reg_dldo1>;
++	vqmmc-supply = <&reg_vcc_wifi>;
++	mmc-pwrseq = <&wifi_pwrseq>;
++	bus-width = <4>;
++	non-removable;
++	status = "okay";
++
++	wlan: wifi@1 {
++		reg = <1>;
++		interrupt-parent = <&pio>;
++		interrupts = <6 15 IRQ_TYPE_EDGE_RISING>; /* PG15 WL_HOSTWAKE*/
++		interrupt-names = "host-wake";
++		local-mac-address = [dc 44 6d c0 ff 02];
++	};
++};
++
++&mmc2 {
++	vmmc-supply = <&reg_dldo1>;
++	bus-width = <8>;
++	non-removable;
++	cap-mmc-hw-reset;
++	status = "okay";
++};
++
++&ohci0 {
++	status = "okay";
++};
++
++&ohci1 {
++	status = "okay";
++};
++
++&ohci2 {
++	status = "okay";
++};
++
++&ohci3 {
++	status = "okay";
++};
++
++&r_i2c {
++	status = "okay";
++
++	axp313a: pmic@36 {
++		compatible = "x-powers,axp313a";
++		reg = <0x36>;
++		wakeup-source;
++		vin1-supply = <&reg_vcc5v>;
++		vin2-supply = <&reg_vcc5v>;
++		vin3-supply = <&reg_vcc5v>;
++
++		regulators {
++			reg_dcdc1: dcdc1 {
++				regulator-always-on;
++				regulator-min-microvolt = <810000>;
++				regulator-max-microvolt = <1160000>;
++				regulator-name = "vdd-gpu";
++			};
++
++			reg_dcdc2: dcdc2 {
++				regulator-always-on;
++				regulator-min-microvolt = <810000>;
++				regulator-max-microvolt = <1160000>;
++				regulator-name = "vdd-cpu";
++			};
++
++			reg_dcdc3: dcdc3 {
++				regulator-always-on;
++				regulator-min-microvolt = <1200000>;
++				regulator-max-microvolt = <1200000>;
++				regulator-name = "vdd-dram";
++			};
++
++			reg_aldo1: aldo1 {
++				regulator-always-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-name = "vcc1v8";
++			};
++
++			reg_dldo1: dldo1 {
++				regulator-always-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-name = "vcc3v3";
++			};
++		};
++	};
++};
++
++&uart0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart0_ph_pins>;
++	status = "okay";
++};
++
++&uart1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>;
++	uart-has-rtscts;
++	status = "okay";
++
++	bluetooth {
++		compatible = "brcm,bcm43438-bt";
++		clocks = <&rtc 1>;
++		clock-names = "lpo";
++		vbat-supply = <&reg_dldo1>;
++		vddio-supply = <&reg_dldo1>;
++		device-wakeup-gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
++		host-wakeup-gpios = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 */
++		shutdown-gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */
++	};
++};
++
++&usbotg {
++	dr_mode = "peripheral";
++	status = "okay";
++};
++
++&usbphy {
++	usb1_vbus-supply = <&reg_usb1_vbus>;
++	status = "okay";
++};
++
++&ir {
++	linux,rc-map-name = "rc-beelink-gs1";
++	status = "okay";
++};
++
++&codec {
++	allwinner,audio-routing =
++	        "Line Out", "LINEOUT";
++	status = "okay";
++};
++
++&ahub_dam_plat {
++	status = "okay";
++};
++
++&ahub1_plat {
++	status = "okay";
++};
++
++&ahub1_mach {
++	status = "okay";
++};
++
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h5-add-cpu-opp-refs.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h5-add-cpu-opp-refs.patch
new file mode 100644
index 000000000000..0161cb92a47b
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h5-add-cpu-opp-refs.patch
@@ -0,0 +1,122 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Wed, 2 Feb 2022 20:40:02 +0300
+Subject: arm64:dts:sun50i-h5 add cpu opp refs
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus.dts | 1 +
+ arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-k1-plus.dts   | 3 ++-
+ arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-m1-plus2.dts  | 1 +
+ arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-core2.dts | 1 +
+ arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts | 1 +
+ arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2-v1.1.dts | 1 +
+ arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts      | 1 +
+ arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts   | 1 +
+ 8 files changed, 9 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-bananapi-m2-plus.dts
+@@ -3,6 +3,7 @@
+ 
+ /dts-v1/;
+ #include "sun50i-h5.dtsi"
++#include "sun50i-h5-cpu-opp.dtsi"
+ #include <arm/allwinner/sunxi-bananapi-m2-plus.dtsi>
+ 
+ / {
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-k1-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-k1-plus.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-k1-plus.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-k1-plus.dts
+@@ -42,6 +42,7 @@
+ 
+ /dts-v1/;
+ #include "sun50i-h5.dtsi"
++#include "sun50i-h5-cpu-opp.dtsi"
+ 
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/input/input.h>
+@@ -393,4 +394,4 @@ &usbphy {
+ &i2s0 {
+ 	sound-dai = <&pcm5102a>;
+ 	status = "disabled";
+-};
+\ No newline at end of file
++};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-m1-plus2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-m1-plus2.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-m1-plus2.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-m1-plus2.dts
+@@ -43,6 +43,7 @@
+ 
+ /dts-v1/;
+ #include "sun50i-h5.dtsi"
++#include "sun50i-h5-cpu-opp.dtsi"
+ 
+ #include <dt-bindings/gpio/gpio.h>
+ 
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-core2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-core2.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-core2.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-core2.dts
+@@ -43,6 +43,7 @@
+ 
+ /dts-v1/;
+ #include "sun50i-h5.dtsi"
++#include "sun50i-h5-cpu-opp.dtsi"
+ 
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/input/input.h>
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo-plus2.dts
+@@ -4,6 +4,7 @@
+ 
+ /dts-v1/;
+ #include "sun50i-h5.dtsi"
++#include "sun50i-h5-cpu-opp.dtsi"
+ 
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/input/input.h>
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2-v1.1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2-v1.1.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2-v1.1.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2-v1.1.dts
+@@ -42,6 +42,7 @@
+ 
+ /dts-v1/;
+ #include "sun50i-h5.dtsi"
++#include "sun50i-h5-cpu-opp.dtsi"
+ 
+ #include <dt-bindings/gpio/gpio.h>
+ 
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts
+@@ -3,6 +3,7 @@
+ 
+ /dts-v1/;
+ #include "sun50i-h5.dtsi"
++#include "sun50i-h5-cpu-opp.dtsi"
+ 
+ #include <dt-bindings/gpio/gpio.h>
+ 
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
+@@ -5,6 +5,7 @@
+ 
+ /dts-v1/;
+ #include "sun50i-h5.dtsi"
++#include "sun50i-h5-cpu-opp.dtsi"
+ 
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/input/input.h>
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h5-add-termal-zones.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h5-add-termal-zones.patch
new file mode 100644
index 000000000000..a29ccf368c10
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h5-add-termal-zones.patch
@@ -0,0 +1,102 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Wed, 2 Feb 2022 21:12:46 +0300
+Subject: arm64:dts:sun50i-h5 add termal zones
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi | 66 ++++++++--
+ 1 file changed, 54 insertions(+), 12 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
+@@ -207,31 +207,73 @@ ths: thermal-sensor@1c25000 {
+ 
+ 	thermal-zones {
+ 		cpu_thermal: cpu-thermal {
+-			polling-delay-passive = <0>;
+-			polling-delay = <0>;
++			/* milliseconds */
++			polling-delay-passive = <250>;
++			polling-delay = <1000>;
+ 			thermal-sensors = <&ths 0>;
+ 
+ 			trips {
+-				cpu_hot_trip: cpu-hot {
++				cpu_warm: cpu_warm {
++					temperature = <75000>;
++					hysteresis = <2000>;
++					type = "passive";
++				};
++
++				cpu_hot_pre: cpu_hot_pre {
+ 					temperature = <80000>;
+ 					hysteresis = <2000>;
+ 					type = "passive";
+ 				};
+ 
+-				cpu_very_hot_trip: cpu-very-hot {
+-					temperature = <100000>;
+-					hysteresis = <0>;
++				cpu_hot: cpu_hot {
++					temperature = <85000>;
++					hysteresis = <2000>;
++					type = "passive";
++				};
++
++				cpu_very_hot_pre: cpu_very_hot_pre {
++					temperature = <90000>;
++					hysteresis = <2000>;
++					type = "passive";
++				};
++
++				cpu_very_hot: cpu_very_hot {
++					temperature = <95000>;
++					hysteresis = <2000>;
++					type = "passive";
++				};
++
++				cpu_crit: cpu_crit {
++					temperature = <105000>;
++					hysteresis = <2000>;
+ 					type = "critical";
+ 				};
+ 			};
+ 
+ 			cooling-maps {
+-				cpu-hot-limit {
+-					trip = <&cpu_hot_trip>;
+-					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+-							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+-							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+-							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
++				cpu_warm_limit_cpu {
++					trip = <&cpu_warm>;
++					cooling-device = <&cpu0 THERMAL_NO_LIMIT 2>;
++				};
++
++				cpu_hot_pre_limit_cpu {
++					trip = <&cpu_hot_pre>;
++					cooling-device = <&cpu0 2 3>;
++				};
++
++				cpu_hot_limit_cpu {
++					trip = <&cpu_hot>;
++					cooling-device = <&cpu0 3 4>;
++				};
++
++				cpu_very_hot_pre_limit_cpu {
++					trip = <&cpu_very_hot_pre>;
++					cooling-device = <&cpu0 5 6>;
++				};
++
++				cpu_very_hot_limit_cpu {
++					trip = <&cpu_very_hot>;
++					cooling-device = <&cpu0 7 THERMAL_NO_LIMIT>;
+ 				};
+ 			};
+ 		};
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h5-enable-power-button-for-orangepi-prime.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h5-enable-power-button-for-orangepi-prime.patch
new file mode 100644
index 000000000000..30738490660e
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h5-enable-power-button-for-orangepi-prime.patch
@@ -0,0 +1,27 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Gunjan Gupta <viraniac@gmail.com>
+Date: Sat, 15 Jul 2023 17:06:17 +0000
+Subject: arm64: dts: sun50i: h5: enable power button for orangepi prime
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
+@@ -63,8 +63,9 @@ gpio-keys {
+ 
+ 		key-sw4 {
+ 			label = "sw4";
+-			linux,code = <BTN_0>;
++			linux,code = <KEY_POWER>;
+ 			gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
++			wakeup-source;
+ 		};
+ 	};
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h5-nanopi-neo2-add-regulator-led-triger.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h5-nanopi-neo2-add-regulator-led-triger.patch
new file mode 100644
index 000000000000..a2422be440f8
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h5-nanopi-neo2-add-regulator-led-triger.patch
@@ -0,0 +1,65 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Mon, 24 Jan 2022 19:24:24 +0300
+Subject: arm64:dts: sun50i-h5-nanopi-neo2 add regulator, led triger
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts | 23 +++++++++-
+ 1 file changed, 22 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts
+@@ -25,12 +25,13 @@ leds {
+ 		led-0 {
+ 			label = "nanopi:green:pwr";
+ 			gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
+-			default-state = "on";
++			linux,default-trigger = "default-on";
+ 		};
+ 
+ 		led-1 {
+ 			label = "nanopi:blue:status";
+ 			gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>;
++			linux,default-trigger = "heartbeat";
+ 		};
+ 	};
+ 
+@@ -51,6 +52,22 @@ reg_vcc3v3: vcc3v3 {
+ 		regulator-max-microvolt = <3300000>;
+ 	};
+ 
++	vdd_cpux: gpio-regulator {
++		compatible = "regulator-gpio";
++		pinctrl-names = "default";
++		regulator-name = "vdd-cpux";
++		regulator-type = "voltage";
++		regulator-boot-on;
++		regulator-always-on;
++		regulator-min-microvolt = <1100000>;
++		regulator-max-microvolt = <1100000>;
++		regulator-ramp-delay = <50>; /* 4ms */
++		gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
++		gpios-states = <0x1>;
++		states = <1100000 0x0
++			  1100000 0x1>;
++	};
++
+ 	reg_usb0_vbus: usb0-vbus {
+ 		compatible = "regulator-fixed";
+ 		regulator-name = "usb0-vbus";
+@@ -62,6 +79,10 @@ reg_usb0_vbus: usb0-vbus {
+ 	};
+ };
+ 
++&cpu0 {
++	cpu-supply = <&vdd_cpux>;
++};
++
+ &ehci0 {
+ 	status = "okay";
+ };
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h5-nanopi-r1s-h5-add-rtl8153-support.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h5-nanopi-r1s-h5-add-rtl8153-support.patch
new file mode 100644
index 000000000000..6b9e50ab6cf0
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h5-nanopi-r1s-h5-add-rtl8153-support.patch
@@ -0,0 +1,40 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Tue, 27 Sep 2022 15:28:08 +0300
+Subject: arm64: dts: sun50i-h5-nanopi-r1s-h5: add rtl8153 support
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts | 10 +++++++++-
+ 1 file changed, 9 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-r1s-h5.dts
+@@ -21,7 +21,8 @@ / {
+ 
+ 	aliases {
+ 		ethernet0 = &emac;
+-		ethernet1 = &rtl8189etv;
++		ethernet1 = &rtl8153;
++		ethernet2 = &rtl8189etv;
+ 		serial0 = &uart0;
+ 	};
+ 
+@@ -116,6 +117,13 @@ &cpu0 {
+ 
+ &ehci1 {
+ 	status = "okay";
++
++	rtl8153: device@1 {
++		compatible = "usbbda,8153";
++		reg = <1>;
++		realtek,led-data = <0x87>;
++		local-mac-address = [00 00 00 00 00 00];
++	};
+ };
+ 
+ &ehci2 {
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h5-orangepi-pc2-add-spi-flash.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h5-orangepi-pc2-add-spi-flash.patch
new file mode 100644
index 000000000000..f2bcc5878a8f
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h5-orangepi-pc2-add-spi-flash.patch
@@ -0,0 +1,51 @@
+From 1415de6f04125006c28aca89749a2709fd4294e7 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Mon, 24 Jan 2022 19:27:52 +0300
+Subject: arm64:dts: sun50i-h5-orangepi-pc2 add spi flash
+
+---
+ .../dts/allwinner/sun50i-h5-orangepi-pc2.dts  | 25 ++++++++++++++-----
+ 1 file changed, 19 insertions(+), 6 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
+index 3d16a6efa2a7..2790d03ca6cd 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
+@@ -199,15 +199,28 @@ &sound_hdmi {
+ 	status = "okay";
+ };
+ 
+-&spi0  {
++&spi0 {
+ 	status = "okay";
+-
+-	flash@0 {
++	spi-flash@0 {
+ 		#address-cells = <1>;
+-		#size-cells = <1>;
++		#size-cells = <0>;
+ 		compatible = "jedec,spi-nor";
+-		reg = <0>;
+-		spi-max-frequency = <40000000>;
++		reg = <0>; /* Chip select 0 */
++		spi-max-frequency = <10000000>;
++		status = "okay";
++		partitions {
++			compatible = "fixed-partitions";
++			#address-cells = <1>;
++			#size-cells = <1>;
++			partition@0 {
++				label = "uboot";
++				reg = <0x0 0x100000>;
++			};
++			partition@100000 {
++				label = "env";
++				reg = <0x100000 0x100000>;
++			};
++		};
+ 	};
+ };
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h5-orangepi-prime-add-regulator.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h5-orangepi-prime-add-regulator.patch
new file mode 100644
index 000000000000..f42da9de077c
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h5-orangepi-prime-add-regulator.patch
@@ -0,0 +1,92 @@
+From c53547f453102a2add3119cc599eda1d3fcb1f4e Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Mon, 24 Jan 2022 19:34:31 +0300
+Subject: arm64:dts: sun50i-h5-orangepi-prime add regulator
+
+---
+ .../allwinner/sun50i-h5-orangepi-prime.dts    | 43 ++++++++++++++++---
+ 1 file changed, 36 insertions(+), 7 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
+index 42d0ffa4a864..0932c817264d 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
+@@ -8,11 +8,19 @@
+ 
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/input/input.h>
++#include <dt-bindings/pinctrl/sun4i-a10.h>
+ 
+ / {
+ 	model = "Xunlong Orange Pi Prime";
+ 	compatible = "xunlong,orangepi-prime", "allwinner,sun50i-h5";
+ 
++	reg_vcc3v3: vcc3v3 {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc3v3";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++	};
++
+ 	aliases {
+ 		ethernet0 = &emac;
+ 		serial0 = &uart0;
+@@ -68,13 +76,6 @@ reg_gmac_3v3: gmac-3v3 {
+ 		gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
+ 	};
+ 
+-	reg_vcc3v3: vcc3v3 {
+-		compatible = "regulator-fixed";
+-		regulator-name = "vcc3v3";
+-		regulator-min-microvolt = <3300000>;
+-		regulator-max-microvolt = <3300000>;
+-	};
+-
+ 	reg_usb0_vbus: usb0-vbus {
+ 		compatible = "regulator-fixed";
+ 		regulator-name = "usb0-vbus";
+@@ -91,6 +92,10 @@ wifi_pwrseq: pwrseq {
+ 	};
+ };
+ 
++&cpu0 {
++	cpu-supply = <&reg_vdd_cpux>;
++};
++
+ &codec {
+ 	allwinner,audio-routing =
+ 		"Line Out", "LINEOUT",
+@@ -190,6 +195,30 @@ &ohci3 {
+ &sound_hdmi {
+ 	status = "okay";
+ };
++&r_i2c {
++	status = "okay";
++
++	reg_vdd_cpux: regulator@65 {
++		compatible = "silergy,sy8106a";
++		reg = <0x65>;
++		regulator-name = "vdd-cpux";
++		silergy,fixed-microvolt = <1200000>;
++		/*
++		 * The datasheet uses 1.1V as the minimum value of VDD-CPUX,
++		 * however both the Armbian DVFS table and the official one
++		 * have operating points with voltage under 1.1V, and both
++		 * DVFS table are known to work properly at the lowest
++		 * operating point.
++		 *
++		 * Use 1.0V as the minimum voltage instead.
++		 */
++		regulator-min-microvolt = <1000000>;
++		regulator-max-microvolt = <1400000>;
++		regulator-ramp-delay = <200>;
++		regulator-boot-on;
++		regulator-always-on;
++	};
++};
+ 
+ &uart0 {
+ 	pinctrl-names = "default";
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h5-orangepi-prime-add-rtl8723cs.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h5-orangepi-prime-add-rtl8723cs.patch
new file mode 100644
index 000000000000..89884599b79e
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h5-orangepi-prime-add-rtl8723cs.patch
@@ -0,0 +1,35 @@
+From 8a8d8ca9c2cd5d399cdcce38d2a66ad8dcb5be62 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Mon, 7 Feb 2022 19:11:07 +0300
+Subject: arm64:dts: sun50i-h5-orangepi-prime add rtl8723cs
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
+index 83ca3a354af7..1ec3696115ed 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-prime.dts
+@@ -25,6 +25,7 @@ reg_vcc3v3: vcc3v3 {
+ 	aliases {
+ 		ethernet0 = &emac;
+ 		serial0 = &uart0;
++		ethernet1 = &rtl8723cs;
+ 	};
+ 
+ 	chosen {
+@@ -175,6 +176,10 @@ &mmc1 {
+ 	bus-width = <4>;
+ 	non-removable;
+ 	status = "okay";
++
++	rtl8723cs: sdio_wifi@1 {
++		reg = <1>;
++	};
+ };
+ 
+ &ohci0 {
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h5-orangepi-zero-plus-add-regulator.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h5-orangepi-zero-plus-add-regulator.patch
new file mode 100644
index 000000000000..2d11c49cab07
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h5-orangepi-zero-plus-add-regulator.patch
@@ -0,0 +1,67 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Mon, 24 Jan 2022 19:49:11 +0300
+Subject: arm64:dts: sun50i-h5-orangepi-zero-plus add regulator
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts | 25 +++++++++-
+ 1 file changed, 24 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts
+@@ -4,6 +4,7 @@
+ 
+ /dts-v1/;
+ #include "sun50i-h5.dtsi"
++#include "sun50i-h5-cpu-opp.dtsi"
+ 
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/input/input.h>
+@@ -36,12 +37,13 @@ leds {
+ 		led-0 {
+ 			label = "orangepi:green:pwr";
+ 			gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */
+-			default-state = "on";
++			linux,default-trigger = "default-on";
+ 		};
+ 
+ 		led-1 {
+ 			label = "orangepi:red:status";
+ 			gpios = <&pio 0 17 GPIO_ACTIVE_HIGH>; /* PA17 */
++			linux,default-trigger = "heartbeat";
+ 		};
+ 	};
+ 
+@@ -54,6 +56,27 @@ reg_gmac_3v3: gmac-3v3 {
+ 		enable-active-high;
+ 		gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
+ 	};
++
++	reg_sy8113b: gpio-regulator {
++		compatible = "regulator-gpio";
++		regulator-name = "vdd-cpux";
++		regulator-type = "voltage";
++		regulator-boot-on;
++		regulator-always-on;
++		regulator-min-microvolt = <1100000>;
++		regulator-max-microvolt = <1300000>;
++		regulator-ramp-delay = <50>; /* 4ms */
++
++		gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */
++		enable-active-high;
++		gpios-states = <0x1>;
++		states = <1100000 0x0
++			  1300000 0x1>;
++	};
++};
++
++&cpu0 {
++	cpu-supply = <&reg_sy8113b>;
+ };
+ 
+ &ehci0 {
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6-Add-r_uart-uart2-3-pins.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6-Add-r_uart-uart2-3-pins.patch
new file mode 100644
index 000000000000..f04574780cb3
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6-Add-r_uart-uart2-3-pins.patch
@@ -0,0 +1,119 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Sun, 23 Jan 2022 20:49:27 +0300
+Subject: arm64:dts: sun50i-h6 Add r_uart uart2-3 pins
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 60 ++++++++--
+ 1 file changed, 50 insertions(+), 10 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+@@ -325,6 +325,17 @@ msgbox: mailbox@3003000 {
+ 			#mbox-cells = <1>;
+ 		};
+ 
++		gic: interrupt-controller@3021000 {
++			compatible = "arm,gic-400";
++			reg = <0x03021000 0x1000>,
++			      <0x03022000 0x2000>,
++			      <0x03024000 0x2000>,
++			      <0x03026000 0x2000>;
++			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
++			interrupt-controller;
++			#interrupt-cells = <3>;
++		};
++
+ 		sid: efuse@3006000 {
+ 			compatible = "allwinner,sun50i-h6-sid";
+ 			reg = <0x03006000 0x400>;
+@@ -384,6 +395,7 @@ pio: pinctrl@300b000 {
+ 			interrupt-controller;
+ 			#interrupt-cells = <3>;
+ 
++			/omit-if-no-ref/
+ 			ext_rgmii_pins: rgmii-pins {
+ 				pins = "PD0", "PD1", "PD2", "PD3", "PD4",
+ 				       "PD5", "PD7", "PD8", "PD9", "PD10",
+@@ -429,6 +441,7 @@ mmc1_pins: mmc1-pins {
+ 				bias-pull-up;
+ 			};
+ 
++			/omit-if-no-ref/
+ 			mmc2_pins: mmc2-pins {
+ 				pins = "PC1", "PC4", "PC5", "PC6",
+ 				       "PC7", "PC8", "PC9", "PC10",
+@@ -483,17 +496,26 @@ uart1_rts_cts_pins: uart1-rts-cts-pins {
+ 				pins = "PG8", "PG9";
+ 				function = "uart1";
+ 			};
+-		};
+ 
+-		gic: interrupt-controller@3021000 {
+-			compatible = "arm,gic-400";
+-			reg = <0x03021000 0x1000>,
+-			      <0x03022000 0x2000>,
+-			      <0x03024000 0x2000>,
+-			      <0x03026000 0x2000>;
+-			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+-			interrupt-controller;
+-			#interrupt-cells = <3>;
++			uart2_pins: uart2-pins {
++				pins = "PD19", "PD20";
++				function = "uart2";
++			};
++
++			uart2_rts_cts_pins: uart2-rts-cts-pins {
++				pins = "PD21", "PD22";
++				function = "uart2";
++			};
++
++			uart3_pins: uart3-pins {
++				pins = "PD23", "PD24";
++				function = "uart3";
++			};
++
++			uart3_rts_cts_pins: uart3-rts-cts-pins {
++				pins = "PD25", "PD26";
++				function = "uart3";
++			};
+ 		};
+ 
+ 		iommu: iommu@30f0000 {
+@@ -978,6 +1000,19 @@ tcon_tv_out_tcon_top: endpoint@1 {
+ 			};
+ 		};
+ 
++		r_uart: serial@7080000 {
++			compatible = "snps,dw-apb-uart";
++			reg = <0x07080000 0x400>;
++			interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
++			reg-shift = <2>;
++			reg-io-width = <4>;
++			clocks = <&r_ccu CLK_R_APB2_UART>;
++			resets = <&r_ccu RST_R_APB2_UART>;
++			pinctrl-names = "default";
++			pinctrl-0 = <&r_uart_pins>;
++			status = "disabled";
++		};
++
+ 		rtc: rtc@7000000 {
+ 			compatible = "allwinner,sun50i-h6-rtc";
+ 			reg = <0x07000000 0x400>;
+@@ -1042,6 +1077,11 @@ r_rsb_pins: r-rsb-pins {
+ 				pins = "PL0", "PL1";
+ 				function = "s_rsb";
+ 			};
++
++			r_uart_pins: r-uart-pins {
++				pins = "PL2", "PL3";
++				function = "s_uart";
++			};
+ 		};
+ 
+ 		r_ir: ir@7040000 {
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6-orangepi-3-add-r_uart-aliase.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6-orangepi-3-add-r_uart-aliase.patch
new file mode 100644
index 000000000000..ad362cf59871
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6-orangepi-3-add-r_uart-aliase.patch
@@ -0,0 +1,24 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Wed, 2 Feb 2022 20:12:37 +0300
+Subject: arm64:dts: sun50i-h6-orangepi-3 add r_uart aliase
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
+@@ -15,6 +15,7 @@ / {
+ 	aliases {
+ 		serial0 = &uart0;
+ 		serial1 = &uart1;
++		serial9 = &r_uart;
+ 		ethernet0 = &emac;
+ 	};
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6-orangepi-3-delete-node-spi0.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6-orangepi-3-delete-node-spi0.patch
new file mode 100644
index 000000000000..e62045f66293
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6-orangepi-3-delete-node-spi0.patch
@@ -0,0 +1,25 @@
+From 505db041831ffe038d8cbb0920c3b2d97d8d4a5f Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Tue, 25 Jan 2022 17:06:21 +0300
+Subject: arm64:dts: sun50i-h6-orangepi-3 delete-node &spi0
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts | 2 ++
+ 1 file changed, 2 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
+index d1f5daf63484..2b61b6c4866f 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
+@@ -348,6 +348,8 @@ &sound_hdmi {
+ 	status = "okay";
+ };
+ 
++/delete-node/ &spi0;
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_ph_pins>;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6-orangepi-add-cpu-opp-refs.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6-orangepi-add-cpu-opp-refs.patch
new file mode 100644
index 000000000000..9a2679005563
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6-orangepi-add-cpu-opp-refs.patch
@@ -0,0 +1,35 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Wed, 2 Feb 2022 21:18:05 +0300
+Subject: arm64:dts: sun50i-h6-orangepi add cpu opp refs
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
+@@ -5,6 +5,7 @@
+ /dts-v1/;
+ 
+ #include "sun50i-h6.dtsi"
++#include "sun50i-h6-cpu-opp.dtsi"
+ 
+ #include <dt-bindings/gpio/gpio.h>
+ 
+@@ -64,6 +65,10 @@ reg_vcc5v: vcc5v {
+ 	};
+ };
+ 
++&cpu0 {
++        cpu-supply = <&reg_dcdca>;
++};
++
+ &de {
+ 	status = "okay";
+ };
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6-orangepi-enable-higher-clock-regulator-max-.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6-orangepi-enable-higher-clock-regulator-max-.patch
new file mode 100644
index 000000000000..a573bede9e34
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6-orangepi-enable-higher-clock-regulator-max-.patch
@@ -0,0 +1,26 @@
+From 7046bdcb478b36bc1886e3fca35a590e58c57201 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Wed, 2 Feb 2022 21:22:57 +0300
+Subject: arm64:dts: sun50i-h6-orangepi enable higher clock
+ regulator-max-microvolt
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
+index ca57044cfe57..1c0e8288ebf6 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
+@@ -218,7 +218,7 @@ reg_cldo3: cldo3 {
+ 			reg_dcdca: dcdca {
+ 				regulator-always-on;
+ 				regulator-min-microvolt = <810000>;
+-				regulator-max-microvolt = <1080000>;
++				regulator-max-microvolt = <1160000>;
+ 				regulator-name = "vdd-cpu";
+ 			};
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6-orangepi-lite2-spi0-usb3phy-dwc3-enable.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6-orangepi-lite2-spi0-usb3phy-dwc3-enable.patch
new file mode 100644
index 000000000000..37e2b3529d95
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6-orangepi-lite2-spi0-usb3phy-dwc3-enable.patch
@@ -0,0 +1,60 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Igor Pecovnik <igor.pecovnik@gmail.com>
+Date: Thu, 22 Jul 2021 08:56:39 +0200
+Subject: arm64:dts: sun50i-h6-orangepi-lite2 spi0, usb3phy, dwc3 enable
+
+Signed-off-by: Igor Pecovnik <igor.pecovnik@gmail.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts | 26 ++++++++++
+ 1 file changed, 26 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-lite2.dts
+@@ -1,5 +1,6 @@
+ // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ // Copyright (C) 2018 Jagan Teki <jagan@openedev.com>
++// Copyright (C) 2021 Igor Pecovnik <igor@armbian.com>
+ 
+ #include "sun50i-h6-orangepi.dtsi"
+ 
+@@ -11,6 +12,16 @@ aliases {
+ 		serial1 = &uart1; /* BT-UART */
+ 	};
+ 
++	reg_usb_vbus: vbus {
++		compatible = "regulator-fixed";
++		regulator-name = "usb-vbus";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		startup-delay-us = <100000>;
++		gpio = <&r_pio 0 5 GPIO_ACTIVE_HIGH>; /* PL5 USB0-DRVVBUS */
++		enable-active-high;
++	};
++
+ 	wifi_pwrseq: pwrseq {
+ 		compatible = "mmc-pwrseq-simple";
+ 		clocks = <&rtc CLK_OSC32K_FANOUT>;
+@@ -72,3 +83,18 @@ bluetooth {
+ 		max-speed = <1500000>;
+ 	};
+ };
++
++&spi0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&spi0_pins>;
++	status = "disabled";
++};
++
++&usb3phy {
++	phy-supply = <&reg_usb_vbus>;
++	status = "okay";
++};
++
++&dwc3 {
++	status = "okay";
++};
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6-orangepi.dtsi-Rollback-r_rsb-to-r_i2c.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6-orangepi.dtsi-Rollback-r_rsb-to-r_i2c.patch
new file mode 100644
index 000000000000..5580614569b0
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6-orangepi.dtsi-Rollback-r_rsb-to-r_i2c.patch
@@ -0,0 +1,40 @@
+From 274fb3935e7d3c889a3ad70f765fb1f036b8d761 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Sun, 24 Jul 2022 13:56:50 +0300
+Subject: arm64: dts: sun50i-h6-orangepi.dtsi: Rollback r_rsb to r_i2c
+
+This fix affects two boards:
+sun50i-h6-orangepi-lite2.dts
+sun50i-h6-orangepi-one-plus.dts
+
+It also depends on the revision of the board.
+If your board fails when working with this fix, just disable
+it by adding (-) minus to the first position of the line
+in which the patch is written in the series.conf file.
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
+index 1c0e8288ebf6..947fb4636aaa 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
+@@ -130,12 +130,12 @@ &r_pio {
+ 	vcc-pm-supply = <&reg_bldo3>;
+ };
+ 
+-&r_rsb {
++&r_i2c {
+ 	status = "okay";
+ 
+-	axp805: pmic@745 {
++	axp805: pmic@36 {
+ 		compatible = "x-powers,axp805", "x-powers,axp806";
+-		reg = <0x745>;
++		reg = <0x36>;
+ 		interrupt-parent = <&r_intc>;
+ 		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
+ 		interrupt-controller;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6-pine-h64-add-dwc3-usb3phy.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6-pine-h64-add-dwc3-usb3phy.patch
new file mode 100644
index 000000000000..de712e2eba7a
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6-pine-h64-add-dwc3-usb3phy.patch
@@ -0,0 +1,36 @@
+From 2e09c0cf2afa5c4bf0293b12b6653aac8431d454 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Tue, 25 Jan 2022 19:05:25 +0300
+Subject: arm64:dts: sun50i-h6-pine-h64 add dwc3 usb3phy
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
+index 8d5a651f24c0..cb7231b386cd 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
+@@ -89,6 +89,10 @@ reg_usb_vbus: vbus {
+ 	};
+ };
+ 
++&dwc3 {
++	status = "okay";
++};
++
+ &cpu0 {
+ 	cpu-supply = <&reg_dcdca>;
+ };
+@@ -379,3 +383,8 @@ &usb2phy {
+ 	usb3_vbus-supply = <&reg_usb_vbus>;
+ 	status = "okay";
+ };
++
++&usb3phy {
++	phy-supply = <&reg_usb_vbus>;
++	status = "okay";
++};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6-pine-h64-add-wifi-rtl8723cs.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6-pine-h64-add-wifi-rtl8723cs.patch
new file mode 100644
index 000000000000..a4758e55ad15
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6-pine-h64-add-wifi-rtl8723cs.patch
@@ -0,0 +1,82 @@
+From e4b7f55f57e5c895fe5dea8d5712affe95fc5f9f Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Tue, 25 Jan 2022 18:41:47 +0300
+Subject: arm64:dts: sun50i-h6-pine-h64 add wifi rtl8723cs
+
+Author: unknown author
+---
+ .../boot/dts/allwinner/sun50i-h6-pine-h64.dts | 38 +++++++++++++++++++
+ 1 file changed, 38 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
+index 95aea02bce40..8d5a651f24c0 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
+@@ -41,6 +41,14 @@ hdmi_con_in: endpoint {
+ 		};
+ 	};
+ 
++	wifi_pwrseq: pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		clocks = <&rtc 1>;
++		clock-names = "ext_clock";
++		reset-gpios = <&r_pio 1 3 GPIO_ACTIVE_LOW>; /* PM3 */
++		post-power-on-delay-ms = <200>;
++	};
++
+ 	leds {
+ 		compatible = "gpio-leds";
+ 
+@@ -142,6 +150,24 @@ &mmc0 {
+ 	status = "okay";
+ };
+ 
++&mmc1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&mmc1_pins>;
++	vmmc-supply = <&reg_cldo2>;
++	vqmmc-supply = <&reg_bldo2>;
++	mmc-pwrseq = <&wifi_pwrseq>;
++	bus-width = <4>;
++	non-removable;
++	status = "okay";
++
++	rtl8723cs: sdio_wifi@1 {
++		reg = <1>;
++		interrupt-parent = <&r_pio>;
++		interrupts = <1 0 IRQ_TYPE_LEVEL_LOW>; /* PM0 */
++		interrupt-names = "host-wake";
++	};
++};
++
+ &mmc2 {
+ 	vmmc-supply = <&reg_cldo1>;
+ 	vqmmc-supply = <&reg_bldo2>;
+@@ -235,12 +261,24 @@ reg_cldo1: cldo1 {
+ 			};
+ 
+ 			reg_cldo2: cldo2 {
++				/*
++				 * This regulator is connected with CLDO3.
++				 * Before the kernel can support synchronized
++				 * enable of coupled regulators, keep them
++				 * both always on as a ugly hack.
++				 */
++				regulator-always-on;
+ 				regulator-min-microvolt = <3300000>;
+ 				regulator-max-microvolt = <3300000>;
+ 				regulator-name = "vcc-wifi-1";
+ 			};
+ 
+ 			reg_cldo3: cldo3 {
++				/*
++				 * This regulator is connected with CLDO2.
++				 * See the comments for CLDO2.
++				 */
++				regulator-always-on;
+ 				regulator-min-microvolt = <3300000>;
+ 				regulator-max-microvolt = <3300000>;
+ 				regulator-name = "vcc-wifi-2";
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6.dtsi-add-pinctrl-pins-for-spi.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6.dtsi-add-pinctrl-pins-for-spi.patch
new file mode 100644
index 000000000000..2d850d49f12e
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6.dtsi-add-pinctrl-pins-for-spi.patch
@@ -0,0 +1,34 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Fri, 28 Jan 2022 15:19:32 +0300
+Subject: arm64:dts: sun50i-h6.dtsi add pinctrl pins for spi
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+@@ -674,6 +674,8 @@ spi0: spi@5010000 {
+ 			clock-names = "ahb", "mod";
+ 			dmas = <&dma 22>, <&dma 22>;
+ 			dma-names = "rx", "tx";
++			pinctrl-names = "default";
++			pinctrl-0 = <&spi0_pins>, <&spi0_cs_pin>;
+ 			resets = <&ccu RST_BUS_SPI0>;
+ 			status = "disabled";
+ 			#address-cells = <1>;
+@@ -689,6 +691,8 @@ spi1: spi@5011000 {
+ 			clock-names = "ahb", "mod";
+ 			dmas = <&dma 23>, <&dma 23>;
+ 			dma-names = "rx", "tx";
++			pinctrl-names = "default";
++			pinctrl-0 = <&spi1_pins>, <&spi1_cs_pin>;
+ 			resets = <&ccu RST_BUS_SPI1>;
+ 			status = "disabled";
+ 			#address-cells = <1>;
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6.dtsi-improve-thermals.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6.dtsi-improve-thermals.patch
new file mode 100644
index 000000000000..049672f61f01
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h6.dtsi-improve-thermals.patch
@@ -0,0 +1,111 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Tue, 25 Jan 2022 17:02:30 +0300
+Subject: arm64:dts: sun50i-h6.dtsi improve thermals
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 68 ++++++++--
+ 1 file changed, 55 insertions(+), 13 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+@@ -1,5 +1,6 @@
+ // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ // Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
++// Copyright (C) 2020 Igor Pecovnik <igor@armbian.com>
+ 
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/sun50i-h6-ccu.h>
+@@ -1141,33 +1142,74 @@ ths: thermal-sensor@5070400 {
+ 
+ 	thermal-zones {
+ 		cpu-thermal {
+-			polling-delay-passive = <0>;
+-			polling-delay = <0>;
++			polling-delay-passive = <250>;
++			polling-delay = <1000>;
+ 			thermal-sensors = <&ths 0>;
+ 
+ 			trips {
+-				cpu_alert: cpu-alert {
++				cpu_warm: cpu_warm {
++					temperature = <75000>;
++					hysteresis = <2000>;
++					type = "passive";
++				};
++
++				cpu_hot_pre: cpu_hot_pre {
++					temperature = <80000>;
++					hysteresis = <2000>;
++					type = "passive";
++				};
++
++				cpu_hot: cpu_hot {
+ 					temperature = <85000>;
+ 					hysteresis = <2000>;
+ 					type = "passive";
+ 				};
+ 
+-				cpu-crit {
+-					temperature = <100000>;
+-					hysteresis = <0>;
++				cpu_very_hot_pre: cpu_very_hot_pre {
++					temperature = <90000>;
++					hysteresis = <2000>;
++					type = "passive";
++				};
++
++				cpu_very_hot: cpu_very_hot {
++					temperature = <95000>;
++					hysteresis = <2000>;
++					type = "passive";
++				};
++
++				cpu_crit: cpu_crit {
++					temperature = <105000>;
++					hysteresis = <2000>;
+ 					type = "critical";
+ 				};
+ 			};
+ 
+ 			cooling-maps {
+-				map0 {
+-					trip = <&cpu_alert>;
+-					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+-							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+-							 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+-							 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
++				cpu_warm_limit_cpu {
++					trip = <&cpu_warm>;
++					cooling-device = <&cpu0 THERMAL_NO_LIMIT 2>;
+ 				};
+-			};
++
++				cpu_hot_pre_limit_cpu {
++					trip = <&cpu_hot_pre>;
++					cooling-device = <&cpu0 2 3>;
++				};
++
++				cpu_hot_limit_cpu {
++					trip = <&cpu_hot>;
++					cooling-device = <&cpu0 3 4>;
++				};
++
++				cpu_very_hot_pre_limit_cpu {
++					trip = <&cpu_very_hot_pre>;
++					cooling-device = <&cpu0 5 6>;
++				};
++
++				cpu_very_hot_limit_cpu {
++					trip = <&cpu_very_hot>;
++					cooling-device = <&cpu0 7 THERMAL_NO_LIMIT>;
++				};
++		       };
+ 		};
+ 
+ 		gpu-thermal {
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h616-add-pwm-nodes-support.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h616-add-pwm-nodes-support.patch
new file mode 100644
index 000000000000..08846ea4b4df
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h616-add-pwm-nodes-support.patch
@@ -0,0 +1,133 @@
+From 476ae5840384c7b61eb4270cdf7641772807f100 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Thu, 10 Apr 2025 13:19:52 +0300
+Subject: arm64: dts: sun50i-h616: add pwm nodes support
+
+---
+ .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 103 ++++++++++++++++++
+ 1 file changed, 103 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+index 668ed3b9090a..72d008d6d4e7 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+@@ -332,6 +332,44 @@ watchdog: watchdog@30090a0 {
+ 			clocks = <&osc24M>;
+ 		};
+ 
++		pwm: pwm@300a000 {
++			compatible = "allwinner,sun50i-h616-pwm";
++			reg = <0x0300a000 0x400>;
++			clocks = <&osc24M>, <&ccu CLK_BUS_PWM>;
++			clock-names = "mod", "bus";
++			resets = <&ccu RST_BUS_PWM>;
++			pwm-number = <6>;
++			pwm-base = <0x0>;
++			sunxi-pwms = <&pwm0>, <&pwm1>, <&pwm2>,
++			             <&pwm3>, <&pwm4>, <&pwm5>;
++			#pwm-cells = <3>;
++			status = "disabled";
++		};
++
++		pwm0: pwm0@0300a000 {
++			compatible = "allwinner,sunxi-pwm0";
++		};
++
++		pwm1: pwm1@0300a000 {
++			compatible = "allwinner,sunxi-pwm1";
++		};
++
++		pwm2: pwm2@0300a000 {
++			compatible = "allwinner,sunxi-pwm2";
++		};
++
++		pwm3: pwm3@0300a000 {
++			compatible = "allwinner,sunxi-pwm3";
++		};
++
++		pwm4: pwm4@0300a000 {
++			compatible = "allwinner,sunxi-pwm4";
++		};
++
++		pwm5: pwm5@0300a000 {
++			compatible = "allwinner,sunxi-pwm5";
++		};
++
+ 		pio: pinctrl@300b000 {
+ 			compatible = "allwinner,sun50i-h616-pinctrl";
+ 			reg = <0x0300b000 0x400>;
+@@ -444,6 +482,71 @@ mmc2_pins: mmc2-pins {
+ 				bias-pull-up;
+ 			};
+ 
++			/omit-if-no-ref/
++			pwm0_pin: pwm0-pin {
++				pins = "PD28";
++				function = "pwm0";
++			};
++
++			/omit-if-no-ref/
++			pwm1_pg_pin: pwm1-pg-pin {
++				pins = "PG19";
++				function = "pwm1";
++			};
++
++			/omit-if-no-ref/
++			pwm1_ph_pin: pwm1-ph-pin {
++				pins = "PH3";
++				function = "pwm1";
++			};
++
++			/omit-if-no-ref/
++			pwm1_pi_pin: pwm1-pi-pin {
++				pins = "PI11";
++				function = "pwm1";
++			};
++
++			/omit-if-no-ref/
++			pwm2_ph_pin: pwm2-ph-pin {
++				pins = "PH2";
++				function = "pwm2";
++			};
++
++			/omit-if-no-ref/
++			pwm2_pi_pin: pwm2-pi-pin {
++				pins = "PI12";
++				function = "pwm2";
++			};
++
++			/omit-if-no-ref/
++			pwm3_ph_pin: pwm3-ph-pin {
++				pins = "PH0";
++				function = "pwm3";
++			};
++
++			/omit-if-no-ref/
++			pwm3_pi_pin: pwm3-pi-pin {
++				pins = "PI13";
++				function = "pwm3";
++			};
++
++			/omit-if-no-ref/
++			pwm4_ph_pin: pwm4-ph-pin {
++				pins = "PH1";
++				function = "pwm4";
++			};
++
++			/omit-if-no-ref/
++			pwm4_pi_pin: pwm4-pi-pin {
++				pins = "PI14";
++				function = "pwm4";
++			};
++
++			pwm5_pin: pwm5-pin {
++				pins = "PA12";
++				function = "pwm5";
++			};
++
+ 			/omit-if-no-ref/
+ 			spi0_pins: spi0-pins {
+ 				pins = "PC0", "PC2", "PC4";
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h616-bigtreetech-cb1-sd-emmc.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h616-bigtreetech-cb1-sd-emmc.patch
new file mode 100644
index 000000000000..26448387d998
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h616-bigtreetech-cb1-sd-emmc.patch
@@ -0,0 +1,491 @@
+From 48881099e2a7b77aa04cba7effd35aef9c4627ea Mon Sep 17 00:00:00 2001
+From: Alan <Alan>
+Date: Tue, 30 May 2023 17:36:29 +0800
+Subject: arm64: dts: sun50i-h616-bigtreetech-cb1(sd, emmc)
+
+> X-Git-Archeology: > recovered message: > Signed-off-by: Alan.Ma from BigTreeTech tech@biqu3d.com
+> X-Git-Archeology: - Revision 9d69bb1da699f5729dc5c1dcc2d8d5f4590152fd: https://github.com/armbian/build/commit/9d69bb1da699f5729dc5c1dcc2d8d5f4590152fd
+> X-Git-Archeology:   Date: Tue, 30 May 2023 17:36:29 +0800
+> X-Git-Archeology:   From: Alan <Alan>
+> X-Git-Archeology:   Subject: Patches: add current(6.1) & edge(6.2) patch for BigTreeTech CB1
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 8562428877003ddd46045cb3429d7fdc9df4acee: https://github.com/armbian/build/commit/8562428877003ddd46045cb3429d7fdc9df4acee
+> X-Git-Archeology:   Date: Sat, 02 Sep 2023 03:34:28 +0518
+> X-Git-Archeology:   From: Gunjan Gupta <viraniac@gmail.com>
+> X-Git-Archeology:   Subject: Allwinner: Kernel patches for 6.5-rc7 kernel
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision bb78fac2fadb40a43a9ccb36266dbd21746c2eb6: https://github.com/armbian/build/commit/bb78fac2fadb40a43a9ccb36266dbd21746c2eb6
+> X-Git-Archeology:   Date: Fri, 29 Sep 2023 08:46:52 +0200
+> X-Git-Archeology:   From: Ricardo Pardini <ricardo@pardini.net>
+> X-Git-Archeology:   Subject: `sunxi`/`sunxi64` `edge` 6.5.y: rebase/rewrite all patches for v6.5.5; fix UTF-8 "From:" encoding
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision d1186b8a0e3d44d5b285e94772ebe2c17a014193: https://github.com/armbian/build/commit/d1186b8a0e3d44d5b285e94772ebe2c17a014193
+> X-Git-Archeology:   Date: Mon, 30 Oct 2023 22:46:11 +0518
+> X-Git-Archeology:   From: Gunjan Gupta <viraniac@gmail.com>
+> X-Git-Archeology:   Subject: kernel: sunxi: Add patches for 6.6 kernel
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision a269c9a1c5784bd89630df1652923f0d76278b61: https://github.com/armbian/build/commit/a269c9a1c5784bd89630df1652923f0d76278b61
+> X-Git-Archeology:   Date: Sun, 24 Dec 2023 09:13:08 +0100
+> X-Git-Archeology:   From: Gunjan Gupta <viraniac@gmail.com>
+> X-Git-Archeology:   Subject: Refreshed patches using rewrite-kernel-patches command
+> X-Git-Archeology:
+> X-Git-Archeology: - Revision 30ef1a3e149f96200bffaf1c3138a4467b6f0aa7: https://github.com/armbian/build/commit/30ef1a3e149f96200bffaf1c3138a4467b6f0aa7
+> X-Git-Archeology:   Date: Sun, 24 Dec 2023 09:13:08 +0100
+> X-Git-Archeology:   From: Gunjan Gupta <viraniac@gmail.com>
+> X-Git-Archeology:   Subject: Allwinner: Add kernel patches for 6.7 kernel
+> X-Git-Archeology:
+---
+ arch/arm64/boot/dts/allwinner/Makefile        |   2 +
+ .../sun50i-h616-bigtreetech-cb1-emmc.dts      |  44 ++++
+ .../sun50i-h616-bigtreetech-cb1-sd.dts        |  35 +++
+ .../sun50i-h616-bigtreetech-cb1.dtsi          | 223 ++++++++++++++++--
+ 4 files changed, 287 insertions(+), 17 deletions(-)
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-emmc.dts
+ create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-sd.dts
+
+diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
+index 3280927df6e0..54665bbb468d 100644
+--- a/arch/arm64/boot/dts/allwinner/Makefile
++++ b/arch/arm64/boot/dts/allwinner/Makefile
+@@ -51,6 +51,8 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-tanix-tx6-mini.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h313-tanix-tx1.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-bigtreetech-cb1-manta.dtb
++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-bigtreetech-cb1-sd.dtb
++dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-bigtreetech-cb1-emmc.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-bigtreetech-pi.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-orangepi-zero2.dtb
+ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h616-x96-mate.dtb
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-emmc.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-emmc.dts
+new file mode 100644
+index 000000000000..f878c23f1d90
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-emmc.dts
+@@ -0,0 +1,44 @@
++// SPDX-License-Identifier: (GPL-2.0+ or MIT)
++/*
++ * Copyright (C) 2023 Alan.Ma <tech@biqu3d.com>.
++ */
++
++/dts-v1/;
++
++#include "sun50i-h616-bigtreetech-cb1.dtsi"
++
++&mmc2 {
++	vmmc-supply = <&reg_dldo1>;
++
++	no-1-8-v;
++	bus-width = <8>;
++	non-removable;
++	status = "okay";
++};
++
++&ws2812 {
++	gpios = <&pio 8 15 GPIO_ACTIVE_LOW>; /* PI15 */
++};
++
++&i2c_gpio {
++	gpios = <&pio 8 6 GPIO_ACTIVE_HIGH>, /* SDA PI6 */
++			<&pio 8 4 GPIO_ACTIVE_HIGH>; /* SCL PI4 */
++};
++
++&can0_pin_irq {
++	pins = "PI3";
++};
++
++&can {
++	interrupts = <8 3 0x08>; /* PI3 IRQ_TYPE_LEVEL_LOW */
++};
++
++&tft_35 {
++	dc-gpios  = <&pio 8 15 GPIO_ACTIVE_HIGH>; /* PI15 */
++};
++
++&spi1 {
++	cs-gpios = <&pio 8 5 GPIO_ACTIVE_HIGH>, /* PI5 */
++			   <&pio 8 14 GPIO_ACTIVE_HIGH>, /* PI14 */
++			   <&pio 8 7 GPIO_ACTIVE_HIGH>; /* PI7 */
++};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-sd.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-sd.dts
+new file mode 100644
+index 000000000000..e18dd854d74b
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1-sd.dts
+@@ -0,0 +1,35 @@
++// SPDX-License-Identifier: (GPL-2.0+ or MIT)
++/*
++ * Copyright (C) 2023 Alan.Ma <tech@biqu3d.com>.
++ */
++
++/dts-v1/;
++
++#include "sun50i-h616-bigtreetech-cb1.dtsi"
++
++&ws2812 {
++	gpios = <&pio 2 14 GPIO_ACTIVE_LOW>; /* PC14 */
++};
++
++&i2c_gpio {
++	gpios = <&pio 2 12 GPIO_ACTIVE_HIGH>, /* SDA PC12 */
++			<&pio 2 10 GPIO_ACTIVE_HIGH>; /* SCL PC10 */
++};
++
++&can0_pin_irq {
++	pins = "PC9";
++};
++
++&can {
++	interrupts = <2 9 0x08>; /* PC9 IRQ_TYPE_LEVEL_LOW */
++};
++
++&tft_35 {
++	dc-gpios  = <&pio 2 14 GPIO_ACTIVE_HIGH>; /* PC14 */
++};
++
++&spi1 {
++	cs-gpios = <&pio 2 11 GPIO_ACTIVE_HIGH>, /* PC11 */
++			   <&pio 2 7 GPIO_ACTIVE_HIGH>, /* PC7 */
++			   <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */
++};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi
+index d12b01c5f41b..0da8f2e6e3d4 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-bigtreetech-cb1.dtsi
+@@ -1,6 +1,7 @@
+ // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ /*
+  * Copyright (C) 2023 Martin Botka <martin.botka@somainline.org>.
++ * Copyright (C) 2023 Alan.Ma <tech@biqu3d.com>.
+  */
+ 
+ /dts-v1/;
+@@ -13,22 +14,41 @@
+ #include <dt-bindings/leds/common.h>
+ 
+ / {
++	model = "BigTreeTech CB1";
++	compatible = "bigtreetech,cb1", "allwinner,sun50i-h616";
++
+ 	aliases {
+-		ethernet0 = &rtl8189ftv;
++		ethernet0 = &emac1;
++		serial0 = &uart0;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
+ 	};
+ 
+ 	leds {
+ 		compatible = "gpio-leds";
+ 
+-		led-0 {
+-			function = LED_FUNCTION_STATUS;
+-			color = <LED_COLOR_ID_GREEN>;
+-			gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
++		act_led: led-0 {
++			gpios = <&pio 7 5 GPIO_ACTIVE_LOW>; /* PH5 */
++			linux,default-trigger = "heartbeat";
++		};
++
++		gpio_1 {
++			function = "wifi_power";
++			gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
++			default-state = "on";
++		};
++
++		gpio_2 {
++			function = "wifi_wake";
++			gpios = <&pio 6 15 GPIO_ACTIVE_HIGH>; /* PG15 */
++			default-state = "on";
+ 		};
+ 	};
+ 
+ 	reg_vcc5v: regulator-vcc5v {
+-		/* board wide 5V supply from carrier boards */
++		/* board wide 5V supply directly from the USB-C socket */
+ 		compatible = "regulator-fixed";
+ 		regulator-name = "vcc-5v";
+ 		regulator-min-microvolt = <5000000>;
+@@ -36,7 +56,17 @@ reg_vcc5v: regulator-vcc5v {
+ 		regulator-always-on;
+ 	};
+ 
++	reg_usb1_vbus: regulator-usb1-vbus {
++		compatible = "regulator-fixed";
++		regulator-name = "usb1-vbus";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		vin-supply = <&reg_vcc5v>;
++		enable-active-high;
++	};
++
+ 	reg_vcc33_wifi: vcc33-wifi {
++		/* Always on 3.3V regulator for WiFi and BT */
+ 		compatible = "regulator-fixed";
+ 		regulator-name = "vcc33-wifi";
+ 		regulator-min-microvolt = <3300000>;
+@@ -46,6 +76,7 @@ reg_vcc33_wifi: vcc33-wifi {
+ 	};
+ 
+ 	reg_vcc_wifi_io: vcc-wifi-io {
++		/* Always on 1.8V/300mA regulator for WiFi and BT IO */
+ 		compatible = "regulator-fixed";
+ 		regulator-name = "vcc-wifi-io";
+ 		regulator-min-microvolt = <1800000>;
+@@ -57,10 +88,50 @@ reg_vcc_wifi_io: vcc-wifi-io {
+ 	wifi_pwrseq: wifi-pwrseq {
+ 		compatible = "mmc-pwrseq-simple";
+ 		clocks = <&rtc 1>;
+-		clock-names = "ext_clock";
++		clock-names = "osc32k-out";
+ 		reset-gpios = <&pio 6 18 GPIO_ACTIVE_LOW>; /* PG18 */
+ 		post-power-on-delay-ms = <200>;
+ 	};
++
++	ws2812: ws2812 {
++		compatible = "rgb-ws2812";
++		pinctrl-names = "default";
++		rgb_cnt = <2>;
++		rgb_value = <0x010000 0x010000>;
++		status = "disabled";
++	};
++
++	i2c_gpio: i2c-gpio {
++		#address-cells = <1>;
++		#size-cells = <0>;
++		compatible = "i2c-gpio";
++		status = "disabled";
++
++		i2c-gpio,delay-us = <3>; /* 100 kHz */
++
++		tft_tp: ns2009@48 {
++			compatible = "ti,tsc2007";
++			reg = <0x48>;
++			status = "disabled";
++			ti,x-plate-ohms = <660>;
++			ti,rt-thr = <3000>;
++			ti,fuzzx = <32>;
++			ti,fuzzy = <16>;
++			i2c,ignore-nak = <1>;
++		};
++
++		light: bh1750@5c {
++			compatible = "rohm,bh1750";
++			reg = <0x5c>;
++			status = "disabled";
++		};
++	};
++
++	mcp2515_clock: mcp2515_clock {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency  = <12000000>;
++	};
+ };
+ 
+ &cpu0 {
+@@ -69,9 +140,9 @@ &cpu0 {
+ 
+ &mmc0 {
+ 	vmmc-supply = <&reg_dldo1>;
+-	/* Card detection pin is not connected */
+ 	broken-cd;
+ 	bus-width = <4>;
++	max-frequency = <50000000>;
+ 	status = "okay";
+ };
+ 
+@@ -80,12 +151,56 @@ &mmc1 {
+ 	vqmmc-supply = <&reg_vcc_wifi_io>;
+ 	mmc-pwrseq = <&wifi_pwrseq>;
+ 	bus-width = <4>;
++	max-frequency = <25000000>;
+ 	non-removable;
+ 	mmc-ddr-1_8v;
+ 	status = "okay";
++};
+ 
+-	rtl8189ftv: wifi@1 {
++&pio {
++	can0_pin_irq: can0_pin_irq {
++		function = "irq";
++		bias-pull-up;
++	};
++};
++
++&spi1 {
++	#address-cells = <1>;
++	#size-cells = <0>;
++	status = "disabled";
++	pinctrl-names = "default";
++	pinctrl-0 = <&spi1_pins>;
++
++	can: mcp2515@0 {
++		status = "disabled";
++		compatible = "microchip,mcp2515";
++		reg = <0x0>;
++		clocks = <&mcp2515_clock>;
++		spi-max-frequency = <12500000>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&can0_pin_irq>;
++		interrupt-parent = <&pio>;
++		vdd-supply = <&reg_vcc33_wifi>;
++		xceiver-supply = <&reg_vcc33_wifi>;
++	};
++
++	tft_35: st7789v@1 {
++		status = "disabled";
++		compatible = "sitronix,st7796s";
+ 		reg = <1>;
++		spi-max-frequency =<12500000>;
++		fps =<60>;
++		buswidth = <8>;
++		rotate =<0>;
++		width = <480>;
++		height = <320>;
++		bpp = <24>;
++		bgr;
++		regwidth = <8>;
++		debug = <0x00>;	 //0x20 show fps
++		txbuflen = <307200>;
++		spi-cpol;
++		spi-cpha;
+ 	};
+ };
+ 
+@@ -95,29 +210,34 @@ &r_i2c {
+ 	axp313a: pmic@36 {
+ 		compatible = "x-powers,axp313a";
+ 		reg = <0x36>;
+-		interrupt-controller;
+-		#interrupt-cells = <1>;
++		wakeup-source;
+ 
+ 		regulators {
+ 			reg_dcdc1: dcdc1 {
+ 				regulator-name = "vdd-gpu-sys";
+-				regulator-min-microvolt = <810000>;
+-				regulator-max-microvolt = <990000>;
++				regulator-min-microvolt = <500000>;
++				regulator-max-microvolt = <3400000>;
++				regulator-step-delay-us = <25>;
++				regulator-final-delay-us = <50>;
+ 				regulator-always-on;
+ 			};
+ 
+ 			reg_dcdc2: dcdc2 {
+ 				regulator-name = "vdd-cpu";
+-				regulator-min-microvolt = <810000>;
+-				regulator-max-microvolt = <1100000>;
++				regulator-min-microvolt = <500000>;
++				regulator-max-microvolt = <1540000>;
++				regulator-step-delay-us = <25>;
++				regulator-final-delay-us = <50>;
+ 				regulator-ramp-delay = <200>;
+ 				regulator-always-on;
+ 			};
+ 
+ 			reg_dcdc3: dcdc3 {
+ 				regulator-name = "vcc-dram";
+-				regulator-min-microvolt = <1350000>;
+-				regulator-max-microvolt = <1500000>;
++				regulator-min-microvolt = <500000>;
++				regulator-max-microvolt = <1840000>;
++				regulator-step-delay-us = <25>;
++				regulator-final-delay-us = <50>;
+ 				regulator-always-on;
+ 			};
+ 
+@@ -125,6 +245,8 @@ reg_aldo1: aldo1 {
+ 				regulator-name = "vcc-1v8-pll";
+ 				regulator-min-microvolt = <1800000>;
+ 				regulator-max-microvolt = <1800000>;
++				regulator-step-delay-us = <25>;
++				regulator-final-delay-us = <50>;
+ 				regulator-always-on;
+ 			};
+ 
+@@ -132,12 +254,79 @@ reg_dldo1: dldo1 {
+ 				regulator-name = "vcc-3v3-io";
+ 				regulator-min-microvolt = <3300000>;
+ 				regulator-max-microvolt = <3300000>;
++				regulator-step-delay-us = <25>;
++				regulator-final-delay-us = <50>;
+ 				regulator-always-on;
+ 			};
+ 		};
+ 	};
+ };
+ 
++&cpu0 {
++	cpu-supply = <&reg_dcdc2>;
++	status = "okay";
++};
++
++&gpu {
++	mali-supply = <&reg_dcdc3>;
++	status = "okay";
++};
++
++&uart0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart0_ph_pins>;
++	status = "okay";
++};
++
+ &usbphy {
++	usb1_vbus-supply = <&reg_usb1_vbus>;
++	status = "okay";
++};
++
++&ehci0 {
++	status = "okay";
++};
++
++&ohci0 {
++	status = "okay";
++};
++
++&ehci1 {
++	status = "okay";
++};
++
++&ohci1 {
++	status = "okay";
++};
++
++&ehci2 {
++	status = "okay";
++};
++
++&ohci2 {
++	status = "okay";
++};
++
++&ehci3 {
++	status = "okay";
++};
++
++&ohci3 {
++	status = "okay";
++};
++
++&usbotg {
++	/*
++	 * PHY0 pins are connected to a USB-C socket, but a role switch
++	 * is not implemented: both CC pins are pulled to GND.
++	 * The VBUS pins power the device, so a fixed peripheral mode
++	 * is the best choice.
++	 * The board can be powered via GPIOs, in this case port0 *can*
++	 * act as a host (with a cable/adapter ignoring CC), as VBUS is
++	 * then provided by the GPIOs. Any user of this setup would
++	 * need to adjust the DT accordingly: dr_mode set to "host",
++	 * enabling OHCI0 and EHCI0.
++	 */
++	dr_mode = "peripheral";
+ 	status = "okay";
+ };
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h616-orangepi-zero2-Enable-GPU-mali.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h616-orangepi-zero2-Enable-GPU-mali.patch
new file mode 100644
index 000000000000..0019dc22c5aa
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h616-orangepi-zero2-Enable-GPU-mali.patch
@@ -0,0 +1,29 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Fri, 15 Oct 2021 21:09:42 +0200
+Subject: arm64:dts: sun50i-h616-orangepi-zero2 Enable GPU mali
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero2.dts
+@@ -24,6 +24,11 @@ &emac0 {
+ 	phy-supply = <&reg_dcdce>;
+ };
+ 
++&gpu {
++	mali-supply = <&reg_dcdcc>;
++	status = "okay";
++};
++
+ &mmc0 {
+ 	vmmc-supply = <&reg_dcdce>;
+ };
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h616-orangepi-zero2-reg_usb1_vbus-status-ok.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h616-orangepi-zero2-reg_usb1_vbus-status-ok.patch
new file mode 100644
index 000000000000..f2c928b69951
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h616-orangepi-zero2-reg_usb1_vbus-status-ok.patch
@@ -0,0 +1,24 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Wed, 14 Dec 2022 20:15:41 +0300
+Subject: arm64: dts: sun50i-h616-orangepi-zero2: reg_usb1_vbus status ok
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-orangepi-zero.dtsi
+@@ -56,6 +56,7 @@ reg_usb1_vbus: regulator-usb1-vbus {
+ 		vin-supply = <&reg_vcc5v>;
+ 		enable-active-high;
+ 		gpio = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */
++		status = "okay";
+ 	};
+ };
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h616-x96-mate-T95-eth-sd-card-hack.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h616-x96-mate-T95-eth-sd-card-hack.patch
new file mode 100644
index 000000000000..d1861f1979ba
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h616-x96-mate-T95-eth-sd-card-hack.patch
@@ -0,0 +1,103 @@
+From 4a174ed11c9bb1a6df8f591c5f6d852684c2130f Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Mon, 14 Jun 2021 20:48:15 +0200
+Subject: arm64:dts: sun50i-h616-x96-mate T95 eth & sd card hack
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ .../dts/allwinner/sun50i-h616-x96-mate.dts    | 21 ++++++++++++++-
+ .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 26 +++++++++++++++++++
+ 2 files changed, 46 insertions(+), 1 deletion(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts
+index 968960ebf1d1..447b131095b6 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts
+@@ -16,6 +16,7 @@ / {
+ 	compatible = "hechuang,x96-mate", "allwinner,sun50i-h616";
+ 
+ 	aliases {
++		ethernet0 = &emac1;
+ 		serial0 = &uart0;
+ 	};
+ 
+@@ -50,13 +51,31 @@ &ehci2 {
+ 	status = "okay";
+ };
+ 
++&emac1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&rmii_pins>;
++	phy-mode = "rmii";
++	phy-handle = <&rmii_phy>;
++	phy-supply = <&reg_aldo1>;
++	allwinner,rx-delay-ps = <3100>;
++	allwinner,tx-delay-ps = <700>;
++	status = "okay";
++};
++
++&mdio1 {
++	rmii_phy: ethernet-phy@1 {
++		compatible = "ethernet-phy-ieee802.3-c22";
++		reg = <1>;
++	};
++};
++
+ &ir {
+ 	status = "okay";
+ };
+ 
+ &mmc0 {
+ 	vmmc-supply = <&reg_dcdce>;
+-	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;	/* PF6 */
++	broken-cd;
+ 	disable-wp;
+ 	bus-width = <4>;
+ 	status = "okay";
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+index 6d1ed00375bc..72e46c263485 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+@@ -287,6 +287,13 @@ ext_rgmii_pins: rgmii-pins {
+ 				drive-strength = <40>;
+ 			};
+ 
++			rmii_pins: rmii-pins {
++				pins = "PA0", "PA1", "PA2", "PA3", "PA4",
++				       "PA5", "PA6", "PA7", "PA8", "PA9";
++				function = "emac1";
++				drive-strength = <40>;
++			};
++
+ 			i2c0_pins: i2c0-pins {
+ 				pins = "PI5", "PI6";
+ 				function = "i2c0";
+@@ -669,6 +676,25 @@ mdio0: mdio {
+ 			};
+ 		};
+ 
++		emac1: ethernet@5030000 {
++			compatible = "allwinner,sun50i-h616-emac";
++			syscon = <&syscon 1>;
++			reg = <0x05030000 0x10000>;
++			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
++			interrupt-names = "macirq";
++			resets = <&ccu RST_BUS_EMAC1>;
++			reset-names = "stmmaceth";
++			clocks = <&ccu CLK_BUS_EMAC1>;
++			clock-names = "stmmaceth";
++			status = "disabled";
++
++			mdio1: mdio {
++				compatible = "snps,dwmac-mdio";
++				#address-cells = <1>;
++				#size-cells = <0>;
++			};
++		};
++
+ 		gpadc: adc@5070000 {
+ 			compatible = "allwinner,sun50i-h616-gpadc",
+ 				     "allwinner,sun20i-d1-gpadc";
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h616-x96-mate-add-hdmi.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h616-x96-mate-add-hdmi.patch
new file mode 100644
index 000000000000..2cc913a7051f
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h616-x96-mate-add-hdmi.patch
@@ -0,0 +1,64 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Mon, 14 Jun 2021 22:39:58 +0200
+Subject: arm64:dts: sun50i-h616-x96-mate add hdmi
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts | 26 ++++++++++
+ 1 file changed, 26 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts b/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts
+index 447b131095b6..35a4620c7db8 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616-x96-mate.dts
+@@ -24,6 +24,17 @@ chosen {
+ 		stdout-path = "serial0:115200n8";
+ 	};
+ 
++	connector {
++		compatible = "hdmi-connector";
++		type = "a";
++
++		port {
++			hdmi_con_in: endpoint {
++				remote-endpoint = <&hdmi_out_con>;
++			};
++		};
++	};
++
+ 	reg_vcc5v: vcc5v {
+ 		/* board wide 5V supply directly from the DC input */
+ 		compatible = "regulator-fixed";
+@@ -43,6 +54,10 @@ &cpu0 {
+ 	cpu-supply = <&reg_dcdca>;
+ };
+ 
++&de {
++	status = "okay";
++};
++
+ &ehci0 {
+ 	status = "okay";
+ };
+@@ -69,6 +84,17 @@ rmii_phy: ethernet-phy@1 {
+ 	};
+ };
+ 
++&hdmi {
++	hvcc-supply = <&reg_bldo1>;
++	status = "okay";
++};
++
++&hdmi_out {
++	hdmi_out_con: endpoint {
++		remote-endpoint = <&hdmi_con_in>;
++	};
++};
++
+ &ir {
+ 	status = "okay";
+ };
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h616.dtsi-reserved-memory-512K-for-BL31.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h616.dtsi-reserved-memory-512K-for-BL31.patch
new file mode 100644
index 000000000000..f31cabe5dae8
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h616.dtsi-reserved-memory-512K-for-BL31.patch
@@ -0,0 +1,31 @@
+From abf887a3265a84d1593b319133e5ee106301a23a Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Sun, 13 Nov 2022 23:15:38 +0300
+Subject: arm64: dts: sun50i-h616.dtsi: reserved memory 512K for BL31
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+index e88c1fbac6ac..acba4de960ce 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+@@ -100,12 +100,12 @@ reserved-memory {
+ 		ranges;
+ 
+ 		/*
+-		 * 256 KiB reserved for Trusted Firmware-A (BL31).
++		 * 512 KiB reserved for Trusted Firmware-A (BL31).
+ 		 * This is added by BL31 itself, but some bootloaders fail
+ 		 * to propagate this into the DTB handed to kernels.
+ 		 */
+ 		secmon@40000000 {
+-			reg = <0x0 0x40000000 0x0 0x40000>;
++			reg = <0x0 0x40000000 0x0 0x80000>;
+ 			no-map;
+ 		};
+ 	};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h618-orangepi-zero2w-Add-missing-nodes.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h618-orangepi-zero2w-Add-missing-nodes.patch
new file mode 100644
index 000000000000..91845ba21bdd
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h618-orangepi-zero2w-Add-missing-nodes.patch
@@ -0,0 +1,434 @@
+From 8d4c66671ff780d7b64b88666573ca392aa93e88 Mon Sep 17 00:00:00 2001
+From: chraac <chraac@gmail.com>
+Date: Fri, 15 Mar 2024 12:30:26 +0800
+Subject: arm64: dts: sun50i-h618-orangepi-zero2w: Add missing nodes
+
+---
+ .../arm64/boot/dts/allwinner/sun50i-h616.dtsi |  25 +-
+ .../allwinner/sun50i-h618-orangepi-zero2w.dts | 289 ++++++++++++++++++
+ 2 files changed, 306 insertions(+), 8 deletions(-)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+index 72d008d6d4e7..6c1f1087f199 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+@@ -241,7 +241,7 @@ video-codec@1c0e000 {
+ 
+ 		syscon: syscon@3000000 {
+ 			compatible = "allwinner,sun50i-h616-system-control";
+-			reg = <0x03000000 0x1000>;
++			reg = <0x03000000 0x30>,<0x03000038 0x0fc8>;
+ 			#address-cells = <1>;
+ 			#size-cells = <1>;
+ 			ranges;
+@@ -919,19 +919,28 @@ mdio0: mdio {
+ 		};
+ 
+ 		emac1: ethernet@5030000 {
+-			compatible = "allwinner,sun50i-h616-emac";
+-			syscon = <&syscon 1>;
+-			reg = <0x05030000 0x10000>;
++			compatible = "allwinner,sunxi-gmac";
++			reg = <0x05030000 0x10000>,
++				<0x03000034 0x4>;
++			reg-names = "gmac1_reg","ephy_reg";
+ 			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+-			interrupt-names = "macirq";
++			interrupt-names = "gmacirq";
+ 			resets = <&ccu RST_BUS_EMAC1>;
+ 			reset-names = "stmmaceth";
+-			clocks = <&ccu CLK_BUS_EMAC1>;
+-			clock-names = "stmmaceth";
++			clocks = <&ccu CLK_BUS_EMAC1>,<&ccu CLK_EMAC_25M>;
++			clock-names = "bus-emac1","emac-25m";
++			pinctrl-0 = <&rmii_pins>;
++			pinctrl-names = "default";
++			tx-delay = <7>;
++			rx-delay = <31>;
++			phy-rst;
++			gmac-power0;
++			gmac-power1;
++			gmac-power2;
+ 			status = "disabled";
+ 
+ 			mdio1: mdio {
+-				compatible = "snps,dwmac-mdio";
++				compatible = "ethernet-phy-ieee802.3-c22";
+ 				#address-cells = <1>;
+ 				#size-cells = <0>;
+ 			};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts
+index a0fe7a9afb77..2296c359699e 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero2w.dts
+@@ -18,12 +18,27 @@ / {
+ 
+ 	aliases {
+ 		serial0 = &uart0;
++		serial2 = &uart2;
++		serial3 = &uart3;
++		serial4 = &uart4;
++		serial5 = &uart5;
+ 	};
+ 
+ 	chosen {
+ 		stdout-path = "serial0:115200n8";
+ 	};
+ 
++	connector {
++		compatible = "hdmi-connector";
++		type = "d";
++
++		port {
++			hdmi_con_in: endpoint {
++				remote-endpoint = <&hdmi_out_con>;
++			};
++		};
++	};
++
+ 	leds {
+ 		compatible = "gpio-leds";
+ 
+@@ -31,6 +46,19 @@ led-0 {
+ 			function = LED_FUNCTION_STATUS;
+ 			color = <LED_COLOR_ID_GREEN>;
+ 			gpios = <&pio 2 13 GPIO_ACTIVE_HIGH>; /* PC13 */
++			linux,default-trigger = "heartbeat";
++		};
++
++		100m_link {
++			label = "100m_link";
++			gpios = <&pio 2 15 GPIO_ACTIVE_HIGH>; /* PC15 */
++			default-state = "off";
++		};
++
++		100m_act {
++			label = "100m_act";
++			gpios = <&pio 2 16 GPIO_ACTIVE_HIGH>; /* PC16 */
++			default-state = "off";
+ 		};
+ 	};
+ 
+@@ -52,6 +80,85 @@ reg_vcc3v3: vcc3v3 {
+ 		vin-supply = <&reg_vcc5v>;
+ 		regulator-always-on;
+ 	};
++
++	reg_vcc_wifi_io: vcc-wifi-io {
++		/* Always on 1.8V/300mA regulator for WiFi and BT IO */
++		compatible = "regulator-fixed";
++		regulator-name = "vcc-wifi-io";
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		regulator-always-on;
++		vin-supply = <&reg_vcc3v3>;
++	};
++
++	wifi_pwrseq: wifi-pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		clocks = <&rtc 1>;
++		clock-names = "osc32k-out";
++		reset-gpios = <&pio 6 18 GPIO_ACTIVE_LOW>; /* PG18 */
++		post-power-on-delay-ms = <200>;
++	};
++
++	ac200_pwm_clk: ac200_clk {
++		compatible = "pwm-clock";
++		#clock-cells = <0>;
++		// pwm5 period_ns = 500 > 334 for select 24M clock.
++		pwms = <&pwm 5 500 0>;
++		clock-frequency = <2000000>;
++		status = "okay";
++	};
++
++	soc {
++		pwm: pwm@300a000 {
++			compatible = "allwinner,sun50i-h616-pwm";
++			reg = <0x0300a000 0x400>;
++			clocks = <&osc24M>, <&ccu CLK_BUS_PWM>;
++			clock-names = "mod", "bus";
++			resets = <&ccu RST_BUS_PWM>;
++			pwm-number = <6>;
++			pwm-base = <0x0>;
++			sunxi-pwms = <&pwm0>, <&pwm1>, <&pwm2>,
++			             <&pwm3>, <&pwm4>, <&pwm5>;
++			#pwm-cells = <3>;
++			status = "okay";
++		};
++
++		pwm0: pwm0@0300a000 {
++			compatible = "allwinner,sunxi-pwm0";
++		};
++
++		pwm1: pwm1@0300a000 {
++			compatible = "allwinner,sunxi-pwm1";
++			pinctrl-names = "default";
++			pinctrl-0 = <&pwm1_ph_pin>;
++		};
++
++		pwm2: pwm2@0300a000 {
++			compatible = "allwinner,sunxi-pwm2";
++			pinctrl-names = "default";
++			pinctrl-0 = <&pwm2_ph_pin>;
++		};
++
++		pwm3: pwm3@0300a000 {
++			compatible = "allwinner,sunxi-pwm3";
++			pinctrl-names = "default";
++			pinctrl-0 = <&pwm3_ph_pin>;
++		};
++
++		pwm4: pwm4@0300a000 {
++			compatible = "allwinner,sunxi-pwm4";
++			pinctrl-names = "default";
++			pinctrl-0 = <&pwm4_ph_pin>;
++		};
++
++		pwm5: pwm5@0300a000 {
++			compatible = "allwinner,sunxi-pwm5";
++			pinctrl-names = "default";
++			pinctrl-0 = <&pwm5_pin>;
++			clk_bypass_output = <0x1>;
++			status = "okay";
++		};
++	};
+ };
+ 
+ &codec {
+@@ -59,27 +166,110 @@ &codec {
+ 	status = "okay";
+ };
+ 
++&de {
++	status = "okay";
++};
++
++&gpu {
++	mali-supply = <&reg_dcdc1>;
++	status = "okay";
++};
++
++&hdmi {
++	hvcc-supply = <&reg_aldo1>;
++	status = "okay";
++};
++
++&hdmi_out {
++	hdmi_out_con: endpoint {
++		remote-endpoint = <&hdmi_con_in>;
++	};
++};
++
+ &cpu0 {
+ 	cpu-supply = <&reg_dcdc2>;
+ };
+ 
++&sid {
++	ephy_calibration: ephy-calibration@2c {
++		reg = <0x2c 0x2>;
++	};
++};
++
++&ehci0 {
++	status = "disabled";
++};
++
+ &ehci1 {
+ 	status = "okay";
+ };
+ 
++&ehci2 {
++	status = "okay";
++};
++
++&ehci3 {
++	status = "okay";
++};
++
+ /* USB 2 & 3 are on the FPC connector (or the exansion board) */
+ 
+ &mmc0 {
+ 	cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;	/* PF6 */
+ 	bus-width = <4>;
++	vmmc-supply = <&reg_dldo1>;
++	max-frequency = <50000000>;
++	status = "okay";
++};
++
++&mmc1 {
+ 	vmmc-supply = <&reg_vcc3v3>;
++	vqmmc-supply = <&reg_vcc_wifi_io>;
++	mmc-pwrseq = <&wifi_pwrseq>;
++	bus-width = <4>;
++	non-removable;
++	mmc-ddr-1_8v;
+ 	status = "okay";
+ };
+ 
++&emac0 {
++	status = "disabled";
++};
++
++&emac1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&rmii_pins>;
++	phy-mode = "rmii";
++	phy-handle = <&rmii_phy>;
++	phy-supply = <&reg_dldo1>;
++	allwinner,rx-delay-ps = <3100>;
++	allwinner,tx-delay-ps = <700>;
++	status = "okay";
++};
++
++&mdio1 {
++	rmii_phy: ethernet-phy@1 {
++		compatible = "ethernet-phy-ieee802.3-c22";
++		reg = <1>;
++	};
++};
++
++&ohci0 {
++	status = "disabled";
++};
++
+ &ohci1 {
+ 	status = "okay";
+ };
+ 
++&ohci2 {
++	status = "okay";
++};
++
++&ohci3 {
++	status = "okay";
++};
++
+ &pio {
+ 	vcc-pc-supply = <&reg_dldo1>;
+ 	vcc-pf-supply = <&reg_dldo1>;	/* internally via VCC-IO */
+@@ -144,6 +334,12 @@ reg_dcdc3: dcdc3 {
+ 	};
+ };
+ 
++&ir {
++	pinctrl-names = "default";
++	pinctrl-0 = <&ir_rx_pin>;
++	status = "okay";
++};
++
+ &spi0  {
+ 	status = "okay";
+ 	pinctrl-names = "default";
+@@ -158,12 +354,77 @@ flash@0 {
+ 	};
+ };
+ 
++&spi1 {
++	status = "disabled";
++	#address-cells = <1>;
++	#size-cells = <0>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&spi1_pins>, <&spi1_cs1_pin>;
++
++	spidev@1 {
++		compatible = "rohm,dh2228fv";
++		status = "disabled";
++		reg = <1>;
++		spi-max-frequency = <1000000>;
++	};
++};
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_ph_pins>;
+ 	status = "okay";
+ };
+ 
++&uart2 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart2_pi_pins>;
++	status = "disabled";
++};
++
++&uart3 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart3_pi_pins>;
++	status = "disabled";
++};
++
++&uart4 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart4_pi_pins>;
++	status = "disabled";
++};
++
++&uart5 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart5_pins>;
++	status = "disabled";
++};
++
++&i2c3 {
++	status = "okay";
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c3_pa_pins>;
++
++	ac200_x: mfd@10 {
++		compatible = "x-powers,ac200-sunxi";
++		reg = <0x10>;
++		clocks = <&ac200_pwm_clk>;
++		// ephy id
++		nvmem-cells = <&ephy_calibration>;
++		nvmem-cell-names = "calibration";
++
++		ac200_ephy: phy {
++			compatible = "x-powers,ac200-ephy-sunxi";
++			status = "okay";
++		};
++	};
++};
++
++&i2c4 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c4_ph_pins>;
++	status = "disabled";
++};
++
+ &usbotg {
+ 	/*
+ 	 * PHY0 pins are connected to a USB-C socket, but a role switch
+@@ -184,3 +445,31 @@ &usbphy {
+ 	usb1_vbus-supply = <&reg_vcc5v>;
+ 	status = "okay";
+ };
++
++&ahub_dam_plat {
++	status = "okay";
++};
++
++&ahub1_plat {
++	status = "okay";
++};
++
++&ahub1_mach {
++	status = "okay";
++};
++
++&cpu_critical {
++	temperature = <100000>;
++};
++
++&gpu_temp_critical {
++	temperature = <100000>;
++};
++
++&ve_temp_critical {
++	temperature = <100000>;
++};
++
++&ddr_temp_critical {
++	temperature = <100000>;
++};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h618-orangepi-zero3-Enable-GPU-mali.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h618-orangepi-zero3-Enable-GPU-mali.patch
new file mode 100644
index 000000000000..1f597e581d8e
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-dts-sun50i-h618-orangepi-zero3-Enable-GPU-mali.patch
@@ -0,0 +1,28 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Gunjan Gupta <viraniac@gmail.com>
+Date: Thu, 28 Dec 2023 15:01:03 +0000
+Subject: arm64:dts: sun50i-h618-orangepi-zero3 Enable GPU mali
+
+---
+ arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts
+index 111111111111..222222222222 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-orangepi-zero3.dts
+@@ -28,6 +28,11 @@ &ext_rgmii_phy {
+ 	motorcomm,clk-out-frequency-hz = <125000000>;
+ };
+ 
++&gpu {
++	mali-supply = <&reg_dcdc1>;
++	status = "okay";
++};
++
+ &mmc0 {
+ 	/*
+ 	 * The schematic shows the card detect pin wired up to PF6, via an
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-sun50i-h616-Add-i2c-2-3-4-uart-2-5-pins.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-sun50i-h616-Add-i2c-2-3-4-uart-2-5-pins.patch
new file mode 100644
index 000000000000..fe65d9db5b97
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/arm64-sun50i-h616-Add-i2c-2-3-4-uart-2-5-pins.patch
@@ -0,0 +1,107 @@
+From c171891d217842915642e7fcc23b8b1d474a7e68 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Sat, 8 Feb 2025 12:37:21 +0300
+Subject: arm64: sun50i-h616: Add i2c(2,3,4), uart(2,5) pins
+
+Add a description of the pins for further use
+in device trees and overlays.
+
+link to:
+drivers/pinctrl/sunxi/pinctrl-sun50i-h616.c
+---
+ .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 67 +++++++++++++++++++
+ 1 file changed, 67 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+index 564c5853af97..668ed3b9090a 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+@@ -371,11 +371,48 @@ i2c0_pins: i2c0-pins {
+ 				function = "i2c0";
+ 			};
+ 
++			/omit-if-no-ref/
++			i2c2_ph_pins: i2c2-ph-pins {
++				pins = "PH2", "PH3";
++				function = "i2c2";
++			};
++
++			/omit-if-no-ref/
++			i2c2_pi_pins: i2c2-pi-pins {
++				pins = "PI9", "PI10";
++				function = "i2c2";
++			};
++
++			i2c3_pa_pins: i2c3-pa-pins {
++				pins = "PA10", "PA11";
++				function = "i2c3";
++				bias-pull-up;
++			};
++
++			/omit-if-no-ref/
++			i2c3_pg_pins: i2c3-pg-pins {
++				pins = "PG17", "PG18";
++				function = "i2c3";
++			};
++
++			/omit-if-no-ref/
+ 			i2c3_ph_pins: i2c3-ph-pins {
+ 				pins = "PH4", "PH5";
+ 				function = "i2c3";
+ 			};
+ 
++			/omit-if-no-ref/
++			i2c4_pg_pins: i2c4-pg-pins {
++				pins = "PG15", "PG16";
++				function = "i2c4";
++			};
++
++			/omit-if-no-ref/
++			i2c4_ph_pins: i2c4-ph-pins {
++				pins = "PH6", "PH7";
++				function = "i2c4";
++			};
++
+ 			ir_rx_pin: ir-rx-pin {
+ 				pins = "PH10";
+ 				function = "ir_rx";
+@@ -453,6 +490,36 @@ uart1_rts_cts_pins: uart1-rts-cts-pins {
+ 				function = "uart1";
+ 			};
+ 
++			/omit-if-no-ref/
++			uart2_pg_pins: uart2-pg-pins {
++				pins = "PG15", "PG16";
++				function = "uart2";
++			};
++
++			/omit-if-no-ref/
++			uart2_pg_rts_cts_pins: uart2-pg-rts-cts-pins {
++				pins = "PG17", "PG18";
++				function = "uart2";
++			};
++
++			/omit-if-no-ref/
++			uart2_ph_pins: uart2-ph-pins {
++				pins = "PH5", "PH6";
++				function = "uart2";
++			};
++
++			/omit-if-no-ref/
++			uart2_ph_rts_cts_pins: uart2-ph-rts-cts-pins {
++				pins = "PH7", "PH8";
++				function = "uart2";
++			};
++
++			/omit-if-no-ref/
++			uart5_pins: uart5-pins {
++				pins = "PH2", "PH3";
++				function = "uart5";
++			};
++
+ 			/omit-if-no-ref/
+ 			x32clk_fanout_pin: x32clk-fanout-pin {
+ 				pins = "PG10";
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/cb1-overlay.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/cb1-overlay.patch
new file mode 100644
index 000000000000..123f2df9c9b2
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/cb1-overlay.patch
@@ -0,0 +1,491 @@
+From ce19656781252e0d532425ee4858734d5634cb1f Mon Sep 17 00:00:00 2001
+From: Your Name <you@example.com>
+Date: Tue, 30 May 2023 12:04:55 +0800
+Subject: cb1-overlay
+
+---
+ .../arm64/boot/dts/allwinner/overlay/Makefile |  15 ++-
+ .../overlay/sun50i-h616-fixup.scr-cmd         | 110 ++++++++++++++++++
+ .../dts/allwinner/overlay/sun50i-h616-ir.dtso |  13 +++
+ .../allwinner/overlay/sun50i-h616-light.dtso  |  20 ++++
+ .../overlay/sun50i-h616-mcp2515.dtso          |  18 +++
+ .../overlay/sun50i-h616-spi-spidev.dtso       |  42 +++++++
+ .../overlay/sun50i-h616-spidev0_0.dtso        |  28 +++++
+ .../overlay/sun50i-h616-spidev1_0.dtso        |  28 +++++
+ .../overlay/sun50i-h616-spidev1_1.dtso        |  28 +++++
+ .../overlay/sun50i-h616-spidev1_2.dtso        |  28 +++++
+ .../overlay/sun50i-h616-tft35_spi.dtso        |  33 ++++++
+ .../allwinner/overlay/sun50i-h616-ws2812.dtso |  13 +++
+ 12 files changed, 374 insertions(+), 2 deletions(-)
+ create mode 100755 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-fixup.scr-cmd
+ create mode 100755 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-ir.dtso
+ create mode 100755 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-light.dtso
+ create mode 100755 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-mcp2515.dtso
+ create mode 100755 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spi-spidev.dtso
+ create mode 100755 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev0_0.dtso
+ create mode 100755 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev1_0.dtso
+ create mode 100755 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev1_1.dtso
+ create mode 100755 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev1_2.dtso
+ create mode 100755 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-tft35_spi.dtso
+ create mode 100755 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-ws2812.dtso
+
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/Makefile b/arch/arm64/boot/dts/allwinner/overlay/Makefile
+index 40d67ebb5932..fb6b30d5753e 100644
+--- a/arch/arm64/boot/dts/allwinner/overlay/Makefile
++++ b/arch/arm64/boot/dts/allwinner/overlay/Makefile
+@@ -47,12 +47,23 @@ dtb-$(CONFIG_ARCH_SUNXI) += \
+ 	sun50i-h6-uart1.dtbo \
+ 	sun50i-h6-uart2.dtbo \
+ 	sun50i-h6-uart3.dtbo \
+-	sun50i-h6-w1-gpio.dtbo
++	sun50i-h6-w1-gpio.dtbo \
++	sun50i-h616-spi-spidev.dtbo \
++	sun50i-h616-spidev0_0.dtbo \
++	sun50i-h616-spidev1_0.dtbo \
++	sun50i-h616-spidev1_1.dtbo \
++	sun50i-h616-spidev1_2.dtbo \
++	sun50i-h616-ir.dtbo \
++	sun50i-h616-tft35_spi.dtbo \
++	sun50i-h616-mcp2515.dtbo \
++	sun50i-h616-ws2812.dtbo \
++	sun50i-h616-light.dtbo
+ 
+ scr-$(CONFIG_ARCH_SUNXI) += \
+ 	sun50i-a64-fixup.scr \
+ 	sun50i-h5-fixup.scr \
+-	sun50i-h6-fixup.scr
++	sun50i-h6-fixup.scr \
++	sun50i-h616-fixup.scr
+ 
+ dtbotxt-$(CONFIG_ARCH_SUNXI) += \
+ 	README.sun50i-a64-overlays \
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-fixup.scr-cmd b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-fixup.scr-cmd
+new file mode 100755
+index 000000000000..2bde77cb082d
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-fixup.scr-cmd
+@@ -0,0 +1,110 @@
++# overlays fixup script
++# implements (or rather substitutes) overlay arguments functionality
++# using u-boot scripting, environment variables and "fdt" command
++
++# setexpr test_var ${tmp_bank} - A
++# works only for hex numbers (A-F)
++
++setenv decompose_pin 'setexpr tmp_bank sub "P(C|G|H|I)\\d+" "\\1";
++setexpr tmp_pin sub "P\\S(\\d+)" "\\1";
++test "${tmp_bank}" = "C" && setenv tmp_bank 2;
++test "${tmp_bank}" = "G" && setenv tmp_bank 6'
++test "${tmp_bank}" = "H" && setenv tmp_bank 7;
++test "${tmp_bank}" = "I" && setenv tmp_bank 8;
++
++if test -n "${param_spinor_spi_bus}"; then
++	test "${param_spinor_spi_bus}" = "0" && setenv tmp_spi_path "spi@5010000"
++	test "${param_spinor_spi_bus}" = "1" && setenv tmp_spi_path "spi@5011000"
++	fdt set /soc/${tmp_spi_path} status "okay"
++	fdt set /soc/${tmp_spi_path}/spiflash@0 status "okay"
++	if test -n "${param_spinor_max_freq}"; then
++		fdt set /soc/${tmp_spi_path}/spiflash@0 spi-max-frequency "<${param_spinor_max_freq}>"
++	fi
++	if test "${param_spinor_spi_cs}" = "1"; then
++		fdt set /soc/${tmp_spi_path}/spiflash@0 reg "<1>"
++	fi
++	env delete tmp_spi_path
++fi
++
++if test -n "${param_spidev_spi_bus}"; then
++	test "${param_spidev_spi_bus}" = "0" && setenv tmp_spi_path "spi@5010000"
++	test "${param_spidev_spi_bus}" = "1" && setenv tmp_spi_path "spi@5011000"
++	fdt set /soc/${tmp_spi_path} status "okay"
++	fdt set /soc/${tmp_spi_path}/spidev status "okay"
++	if test -n "${param_spidev_max_freq}"; then
++		fdt set /soc/${tmp_spi_path}/spidev spi-max-frequency "<${param_spidev_max_freq}>"
++	fi
++	if test "${param_spidev_spi_cs}" = "1"; then
++		fdt set /soc/${tmp_spi_path}/spidev reg "<1>"
++	fi
++	env delete tmp_spi_path
++fi
++
++if test -n "${param_pps_pin}"; then
++	setenv tmp_bank "${param_pps_pin}"
++	setenv tmp_pin "${param_pps_pin}"
++	run decompose_pin
++	fdt set /soc/pinctrl@300b000/pps_pins pins "${param_pps_pin}"
++	fdt get value tmp_phandle /soc/pinctrl@300b000 phandle
++	fdt set /pps@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>"
++	env delete tmp_pin tmp_bank tmp_phandle
++fi
++
++if test "${param_pps_falling_edge}" = "1"; then
++	fdt set /pps@0 assert-falling-edge
++fi
++
++for f in ${overlays}; do
++	if test "${f}" = "pwm34"; then
++		setenv bootargs_new ""
++		for arg in ${bootargs}; do
++			if test "${arg}" = "console=ttyS0,115200"; then
++				echo "Warning: Disabling ttyS0 console due to enabled PWM3 and PWM4 overlay"
++			else
++				setenv bootargs_new "${bootargs_new} ${arg}"
++			fi
++		done
++		setenv bootargs "${bootargs_new}"
++	fi
++done
++
++if test -n "${param_w1_pin}"; then
++	setenv tmp_bank "${param_w1_pin}"
++	setenv tmp_pin "${param_w1_pin}"
++	run decompose_pin
++	fdt set /soc/pinctrl@300b000/w1_pins pins "${param_w1_pin}"
++	fdt get value tmp_phandle /soc/pinctrl@300b000 phandle
++	fdt set /onewire@0 gpios "<${tmp_phandle} ${tmp_bank} ${tmp_pin} 0>"
++	env delete tmp_pin tmp_bank tmp_phandle
++fi
++
++if test "${param_w1_pin_int_pullup}" = "1"; then
++	fdt set /soc/pinctrl@300b000/w1_pins bias-pull-up
++fi
++
++if test "${param_uart1_rtscts}" = "1"; then
++	fdt get value tmp_phandle1 /soc/pinctrl@300b000/uart1-pins phandle
++	fdt get value tmp_phandle2 /soc/pinctrl@300b000/uart1-rts-cts-pins phandle
++	fdt set /soc/serial@5000400 pinctrl-names "default" "default"
++	fdt set /soc/serial@5000400 pinctrl-0 "<${tmp_phandle1}>"
++	fdt set /soc/serial@5000400 pinctrl-1 "<${tmp_phandle2}>"
++	env delete tmp_phandle1 tmp_phandle2
++fi
++
++if test "${param_uart2_rtscts}" = "1"; then
++	fdt get value tmp_phandle1 /soc/pinctrl@300b000/uart2-pins phandle
++	fdt get value tmp_phandle2 /soc/pinctrl@300b000/uart2-rts-cts-pins phandle
++	fdt set /soc/serial@5000800 pinctrl-names "default" "default"
++	fdt set /soc/serial@5000800 pinctrl-0 "<${tmp_phandle1}>"
++	fdt set /soc/serial@5000800 pinctrl-1 "<${tmp_phandle2}>"
++	env delete tmp_phandle1 tmp_phandle2
++fi
++
++if test "${param_uart3_rtscts}" = "1"; then
++	fdt get value tmp_phandle1 /soc/pinctrl@300b000/uart3-pins phandle
++	fdt get value tmp_phandle2 /soc/pinctrl@300b000/uart3-rts-cts-pins phandle
++	fdt set /soc/serial@5000c00 pinctrl-names "default" "default"
++	fdt set /soc/serial@5000c00 pinctrl-0 "<${tmp_phandle1}>"
++	fdt set /soc/serial@5000c00 pinctrl-1 "<${tmp_phandle2}>"
++	env delete tmp_phandle1 tmp_phandle2
++fi
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-ir.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-ir.dtso
+new file mode 100755
+index 000000000000..825433add1c3
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-ir.dtso
+@@ -0,0 +1,13 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h616";
++
++	fragment@0 {
++		target = <&ir>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-light.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-light.dtso
+new file mode 100755
+index 000000000000..4ab9dc9527e7
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-light.dtso
+@@ -0,0 +1,20 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h616";
++
++	fragment@0 {
++		target = <&i2c_gpio>;
++		 __overlay__ {
++			status = "okay";
++		};
++	};
++
++	fragment@1 {
++		target = <&uart0>;
++		__overlay__ {
++			status = "disabled";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-mcp2515.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-mcp2515.dtso
+new file mode 100755
+index 000000000000..64841956e568
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-mcp2515.dtso
+@@ -0,0 +1,18 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++    fragment@0 {
++		target = <&spi1>;
++		 __overlay__ {
++			status = "okay";
++		};
++	};
++
++    fragment@1 {
++		target = <&can>;
++		__overlay__ {
++            status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spi-spidev.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spi-spidev.dtso
+new file mode 100755
+index 000000000000..e0ceed71965f
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spi-spidev.dtso
+@@ -0,0 +1,42 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h616";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi0 = "/soc/spi@5010000";
++			spi1 = "/soc/spi@5011000";
++		};
++	};
++
++	fragment@1 {
++		target = <&spi0>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spidev@0 {
++				compatible = "rohm,dh2228fv";
++				status = "disabled";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++
++	fragment@2 {
++		target = <&spi1>;
++		__overlay__ {
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spidev@0 {
++				compatible = "rohm,dh2228fv";
++				status = "disabled";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev0_0.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev0_0.dtso
+new file mode 100755
+index 000000000000..a5a89707c3dd
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev0_0.dtso
+@@ -0,0 +1,28 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h616";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi0 = "/soc/spi@5010000";
++		};
++	};
++
++	fragment@1 {
++		target = <&spi0>;
++		__overlay__ {
++            status = "okay";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spidev0_0: spidev@0 {
++				compatible = "rohm,dh2228fv";
++				status = "okay";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev1_0.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev1_0.dtso
+new file mode 100755
+index 000000000000..20a0486442cc
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev1_0.dtso
+@@ -0,0 +1,28 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h616";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi1 = "/soc/spi@5011000";
++		};
++	};
++
++	fragment@1 {
++		target = <&spi1>;
++		__overlay__ {
++            status = "okay";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spidev1_0: spidev@0 {
++				compatible = "rohm,dh2228fv";
++				status = "okay";
++				reg = <0>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev1_1.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev1_1.dtso
+new file mode 100755
+index 000000000000..a9ae45e84063
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev1_1.dtso
+@@ -0,0 +1,28 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h616";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi1 = "/soc/spi@5011000";
++		};
++	};
++
++	fragment@1 {
++		target = <&spi1>;
++		__overlay__ {
++            status = "okay";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spidev1_1: spidev@1 {
++				compatible = "rohm,dh2228fv";
++				status = "okay";
++				reg = <1>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev1_2.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev1_2.dtso
+new file mode 100755
+index 000000000000..efe5a8949b3a
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-spidev1_2.dtso
+@@ -0,0 +1,28 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h616";
++
++	fragment@0 {
++		target-path = "/aliases";
++		__overlay__ {
++			spi1 = "/soc/spi@5011000";
++		};
++	};
++
++	fragment@1 {
++		target = <&spi1>;
++		__overlay__ {
++            status = "okay";
++			#address-cells = <1>;
++			#size-cells = <0>;
++			spidev1_2: spidev@2 {
++				compatible = "rohm,dh2228fv";
++				status = "okay";
++				reg = <2>;
++				spi-max-frequency = <1000000>;
++			};
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-tft35_spi.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-tft35_spi.dtso
+new file mode 100755
+index 000000000000..e96582bcbed5
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-tft35_spi.dtso
+@@ -0,0 +1,33 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	fragment@0 {
++		target = <&i2c_gpio>;
++		 __overlay__ {
++			status = "okay";
++		};
++	};
++
++    fragment@1 {
++		target = <&spi1>;
++		 __overlay__ {
++			status = "okay";
++		};
++	};
++
++    fragment@2 {
++		target = <&tft_35>;
++		__overlay__ {
++            status = "okay";
++            spi-max-frequency = <12500000>;
++		};
++	};
++
++    fragment@3 {
++		target = <&tft_tp>;
++		__overlay__ {
++            status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-ws2812.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-ws2812.dtso
+new file mode 100755
+index 000000000000..4e43907cb0ce
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-ws2812.dtso
+@@ -0,0 +1,13 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun50i-h616";
++
++	fragment@0 {
++		target = <&ws2812>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/clk-gate-add-support-for-regmap-based-gates.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/clk-gate-add-support-for-regmap-based-gates.patch
new file mode 100644
index 000000000000..451139871e46
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/clk-gate-add-support-for-regmap-based-gates.patch
@@ -0,0 +1,251 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Andre Przywara <andre.przywara@arm.com>
+Date: Fri, 10 Jun 2022 18:20:29 +0100
+Subject: clk: gate: add support for regmap based gates
+
+While we have nice wrappers for simple bit-flip MMIO based clock gates,
+a single bit to toggle in a regmap still requires to write a lot of clock
+framework boilerplate.
+
+Support generic wrappers for regmap based clock gates, by adding them to
+the existing clock-gates.c file. Since a read-modify-write operation in a
+regmap can be much more complex than a readl/writel pair, we cannot use
+the .enable/.disable ops members, but do the actual flipping already in
+.prepare/.unprepare, where we can sleep. Also we cannot provide an
+.is_enabled function, since this must not sleep as well.
+On the upside all the locking for the r/m/w operation is provided by
+regmap already, so we can skip that.
+The rest of the CCF boilerplate code can be shared.
+
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+---
+ drivers/clk/clk-gate.c       | 60 +++++++++-
+ include/linux/clk-provider.h | 36 +++++-
+ 2 files changed, 89 insertions(+), 7 deletions(-)
+
+diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
+index 111111111111..222222222222 100644
+--- a/drivers/clk/clk-gate.c
++++ b/drivers/clk/clk-gate.c
+@@ -9,6 +9,7 @@
+ #include <linux/clk-provider.h>
+ #include <linux/device.h>
+ #include <linux/module.h>
++#include <linux/regmap.h>
+ #include <linux/slab.h>
+ #include <linux/io.h>
+ #include <linux/err.h>
+@@ -124,11 +125,42 @@ const struct clk_ops clk_gate_ops = {
+ };
+ EXPORT_SYMBOL_GPL(clk_gate_ops);
+ 
++static int clk_gate_regmap_setclrbit(struct clk_hw *hw, bool enable)
++{
++	struct clk_gate *gate = to_clk_gate(hw);
++	bool set = gate->flags & CLK_GATE_SET_TO_DISABLE;
++
++	set ^= enable;
++
++	if (set)
++		return regmap_set_bits(gate->regmap, gate->regmap_offs,
++				       BIT(gate->bit_idx));
++	else
++		return regmap_clear_bits(gate->regmap, gate->regmap_offs,
++					 BIT(gate->bit_idx));
++}
++
++static int clk_gate_regmap_prepare(struct clk_hw *hw)
++{
++	return clk_gate_regmap_setclrbit(hw, true);
++}
++
++static void clk_gate_regmap_unprepare(struct clk_hw *hw)
++{
++	clk_gate_regmap_setclrbit(hw, false);
++}
++
++const struct clk_ops clk_gate_regmap_ops = {
++	.prepare = clk_gate_regmap_prepare,
++	.unprepare = clk_gate_regmap_unprepare,
++};
++
+ struct clk_hw *__clk_hw_register_gate(struct device *dev,
+ 		struct device_node *np, const char *name,
+ 		const char *parent_name, const struct clk_hw *parent_hw,
+ 		const struct clk_parent_data *parent_data,
+ 		unsigned long flags,
++		struct regmap *regmap, unsigned int regmap_offs,
+ 		void __iomem *reg, u8 bit_idx,
+ 		u8 clk_gate_flags, spinlock_t *lock)
+ {
+@@ -150,7 +182,10 @@ struct clk_hw *__clk_hw_register_gate(struct device *dev,
+ 		return ERR_PTR(-ENOMEM);
+ 
+ 	init.name = name;
+-	init.ops = &clk_gate_ops;
++	if (regmap)
++		init.ops = &clk_gate_regmap_ops;
++	else
++		init.ops = &clk_gate_ops;
+ 	init.flags = flags;
+ 	init.parent_names = parent_name ? &parent_name : NULL;
+ 	init.parent_hws = parent_hw ? &parent_hw : NULL;
+@@ -162,6 +197,8 @@ struct clk_hw *__clk_hw_register_gate(struct device *dev,
+ 
+ 	/* struct clk_gate assignments */
+ 	gate->reg = reg;
++	gate->regmap = regmap;
++	gate->regmap_offs = regmap_offs;
+ 	gate->bit_idx = bit_idx;
+ 	gate->flags = clk_gate_flags;
+ 	gate->lock = lock;
+@@ -197,6 +234,22 @@ struct clk *clk_register_gate(struct device *dev, const char *name,
+ }
+ EXPORT_SYMBOL_GPL(clk_register_gate);
+ 
++struct clk *clk_register_regmap_gate(struct device *dev, const char *name,
++		const char *parent_name, unsigned long flags,
++		struct regmap *regmap, unsigned int regmap_offs,
++		u8 bit_idx, u8 clk_gate_flags)
++{
++	struct clk_hw *hw;
++
++	hw = clk_hw_register_regmap_gate(dev, name, parent_name, flags, regmap,
++					 regmap_offs, bit_idx, clk_gate_flags);
++
++	if (IS_ERR(hw))
++		return ERR_CAST(hw);
++	return hw->clk;
++}
++EXPORT_SYMBOL_GPL(clk_register_regmap_gate);
++
+ void clk_unregister_gate(struct clk *clk)
+ {
+ 	struct clk_gate *gate;
+@@ -234,6 +287,7 @@ struct clk_hw *__devm_clk_hw_register_gate(struct device *dev,
+ 		const char *parent_name, const struct clk_hw *parent_hw,
+ 		const struct clk_parent_data *parent_data,
+ 		unsigned long flags,
++		struct regmap *regmap, unsigned int regmap_offs,
+ 		void __iomem *reg, u8 bit_idx,
+ 		u8 clk_gate_flags, spinlock_t *lock)
+ {
+@@ -244,8 +298,8 @@ struct clk_hw *__devm_clk_hw_register_gate(struct device *dev,
+ 		return ERR_PTR(-ENOMEM);
+ 
+ 	hw = __clk_hw_register_gate(dev, np, name, parent_name, parent_hw,
+-				    parent_data, flags, reg, bit_idx,
+-				    clk_gate_flags, lock);
++				    parent_data, flags, regmap, regmap_offs,
++				    reg, bit_idx, clk_gate_flags, lock);
+ 
+ 	if (!IS_ERR(hw)) {
+ 		*ptr = hw;
+diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
+index 2e6e603b7493..a9a731ebb8f6 100644
+--- a/include/linux/clk-provider.h
++++ b/include/linux/clk-provider.h
+@@ -8,6 +8,7 @@
+ 
+ #include <linux/of.h>
+ #include <linux/of_clk.h>
++#include <linux/regmap.h>
+ 
+ /*
+  * flags used across common struct clk.  these flags should only affect the
+@@ -526,6 +527,8 @@ void of_fixed_clk_setup(struct device_node *np);
+ struct clk_gate {
+ 	struct clk_hw hw;
+ 	void __iomem	*reg;
++	struct regmap	*regmap;
++	unsigned int	regmap_offs;
+ 	u8		bit_idx;
+ 	u8		flags;
+ 	spinlock_t	*lock;
+@@ -543,6 +546,7 @@ struct clk_hw *__clk_hw_register_gate(struct device *dev,
+ 		const char *parent_name, const struct clk_hw *parent_hw,
+ 		const struct clk_parent_data *parent_data,
+ 		unsigned long flags,
++		struct regmap *regmap, unsigned int regmap_offs,
+ 		void __iomem *reg, u8 bit_idx,
+ 		u8 clk_gate_flags, spinlock_t *lock);
+ struct clk_hw *__devm_clk_hw_register_gate(struct device *dev,
+@@ -550,12 +554,17 @@ struct clk_hw *__devm_clk_hw_register_gate(struct device *dev,
+ 		const char *parent_name, const struct clk_hw *parent_hw,
+ 		const struct clk_parent_data *parent_data,
+ 		unsigned long flags,
++		struct regmap *regmap, unsigned int regmap_offs,
+ 		void __iomem *reg, u8 bit_idx,
+ 		u8 clk_gate_flags, spinlock_t *lock);
+ struct clk *clk_register_gate(struct device *dev, const char *name,
+ 		const char *parent_name, unsigned long flags,
+ 		void __iomem *reg, u8 bit_idx,
+ 		u8 clk_gate_flags, spinlock_t *lock);
++struct clk *clk_register_regmap_gate(struct device *dev, const char *name,
++		const char *parent_name, unsigned long flags,
++		struct regmap *regmap, unsigned int regmap_offs,
++		u8 bit_idx, u8 clk_gate_flags);
+ /**
+  * clk_hw_register_gate - register a gate clock with the clock framework
+  * @dev: device that is registering this clock
+@@ -570,8 +579,14 @@ struct clk *clk_register_gate(struct device *dev, const char *name,
+ #define clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx,     \
+ 			     clk_gate_flags, lock)			      \
+ 	__clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL,      \
+-			       NULL, (flags), (reg), (bit_idx),		      \
++			       NULL, (flags), NULL, 0, (reg), (bit_idx),      \
+ 			       (clk_gate_flags), (lock))
++
++#define clk_hw_register_regmap_gate(dev, name, parent_name, flags, regmap,    \
++				    regmap_offs, bit_idx, clk_gate_flags)     \
++	__clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL,      \
++			       NULL, (flags), regmap, regmap_offs, NULL,      \
++			       (bit_idx), (clk_gate_flags), NULL)
+ /**
+  * clk_hw_register_gate_parent_hw - register a gate clock with the clock
+  * framework
+@@ -587,8 +602,15 @@ struct clk *clk_register_gate(struct device *dev, const char *name,
+ #define clk_hw_register_gate_parent_hw(dev, name, parent_hw, flags, reg,      \
+ 				       bit_idx, clk_gate_flags, lock)	      \
+ 	__clk_hw_register_gate((dev), NULL, (name), NULL, (parent_hw),        \
+-			       NULL, (flags), (reg), (bit_idx),		      \
++			       NULL, (flags), NULL, 0, (reg), (bit_idx),      \
+ 			       (clk_gate_flags), (lock))
++
++#define clk_hw_register_regmap_gate_parent_hw(dev, name, parent_hw, flags,    \
++					      regmap, regmap_offs, bit_idx,   \
++					      clk_gate_flags)		      \
++	__clk_hw_register_gate((dev), NULL, (name), NULL, (parent_hw),        \
++			       NULL, (flags), regmap, regmap_offs, NULL,      \
++			       (bit_idx), (clk_gate_flags), NULL)
+ /**
+  * clk_hw_register_gate_parent_data - register a gate clock with the clock
+  * framework
+@@ -604,7 +626,7 @@ struct clk *clk_register_gate(struct device *dev, const char *name,
+ #define clk_hw_register_gate_parent_data(dev, name, parent_data, flags, reg,  \
+ 				       bit_idx, clk_gate_flags, lock)	      \
+ 	__clk_hw_register_gate((dev), NULL, (name), NULL, NULL, (parent_data), \
+-			       (flags), (reg), (bit_idx),		      \
++			       (flags), NULL, 0, (reg), (bit_idx),	      \
+ 			       (clk_gate_flags), (lock))
+ /**
+  * devm_clk_hw_register_gate - register a gate clock with the clock framework
+@@ -620,8 +642,14 @@ struct clk *clk_register_gate(struct device *dev, const char *name,
+ #define devm_clk_hw_register_gate(dev, name, parent_name, flags, reg, bit_idx,\
+ 				  clk_gate_flags, lock)			      \
+ 	__devm_clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \
+-			       NULL, (flags), (reg), (bit_idx),		      \
++			       NULL, (flags), NULL, 0, (reg), (bit_idx),      \
+ 			       (clk_gate_flags), (lock))
++#define devm_clk_hw_register_regmap_gate(dev, name, parent_name, flags,	      \
++					 regmap, regmap_offs, bit_idx,	      \
++					 clk_gate_flags)		      \
++	__devm_clk_hw_register_gate((dev), NULL, (name), (parent_name), NULL, \
++			       NULL, (flags), (regmap), (regmap_offs), NULL,  \
++			       (bit_idx), (clk_gate_flags), NULL)
+ /**
+  * devm_clk_hw_register_gate_parent_hw - register a gate clock with the clock
+  * framework
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/driver-allwinner-h618-emac.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/driver-allwinner-h618-emac.patch
new file mode 100644
index 000000000000..dee2b56d2bd1
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/driver-allwinner-h618-emac.patch
@@ -0,0 +1,4514 @@
+From 73d5c27e53e0a2ee71cbd060f19029957fc551a5 Mon Sep 17 00:00:00 2001
+From: chraac <chraac@gmail.com>
+Date: Fri, 16 Aug 2024 16:44:41 +0800
+Subject: driver: allwinner h618 emac
+
+---
+ drivers/gpio/gpiolib-of.c                     |   29 +-
+ drivers/mfd/Kconfig                           |   10 +
+ drivers/mfd/Makefile                          |    1 +
+ drivers/mfd/sunxi-ac200.c                     |  289 +++
+ drivers/net/ethernet/allwinner/Kconfig        |    8 +
+ drivers/net/ethernet/allwinner/Makefile       |    2 +
+ drivers/net/ethernet/allwinner/sunxi-gmac.c   | 2217 +++++++++++++++++
+ drivers/net/ethernet/allwinner/sunxi-gmac.h   |  270 ++
+ .../net/ethernet/allwinner/sunxi_gmac_ops.c   |  768 ++++++
+ drivers/net/phy/Kconfig                       |    8 +
+ drivers/net/phy/Makefile                      |    1 +
+ drivers/net/phy/sunxi-ephy.c                  |  516 ++++
+ include/linux/mfd/ac200.h                     |  213 ++
+ include/linux/of_gpio.h                       |   18 +
+ 14 files changed, 4335 insertions(+), 15 deletions(-)
+ create mode 100644 drivers/mfd/sunxi-ac200.c
+ create mode 100644 drivers/net/ethernet/allwinner/sunxi-gmac.c
+ create mode 100644 drivers/net/ethernet/allwinner/sunxi-gmac.h
+ create mode 100644 drivers/net/ethernet/allwinner/sunxi_gmac_ops.c
+ create mode 100644 drivers/net/phy/sunxi-ephy.c
+ create mode 100644 include/linux/mfd/ac200.h
+
+diff --git a/drivers/gpio/gpiolib-of.c b/drivers/gpio/gpiolib-of.c
+index 176e9142fd8f..b9f82442a985 100644
+--- a/drivers/gpio/gpiolib-of.c
++++ b/drivers/gpio/gpiolib-of.c
+@@ -25,21 +25,6 @@
+ #include "gpiolib.h"
+ #include "gpiolib-of.h"
+ 
+-/*
+- * This is Linux-specific flags. By default controllers' and Linux' mapping
+- * match, but GPIO controllers are free to translate their own flags to
+- * Linux-specific in their .xlate callback. Though, 1:1 mapping is recommended.
+- */
+-enum of_gpio_flags {
+-	OF_GPIO_ACTIVE_LOW = 0x1,
+-	OF_GPIO_SINGLE_ENDED = 0x2,
+-	OF_GPIO_OPEN_DRAIN = 0x4,
+-	OF_GPIO_TRANSITORY = 0x8,
+-	OF_GPIO_PULL_UP = 0x10,
+-	OF_GPIO_PULL_DOWN = 0x20,
+-	OF_GPIO_PULL_DISABLE = 0x40,
+-};
+-
+ /**
+  * of_gpio_named_count() - Count GPIOs for a device
+  * @np:		device node to count GPIOs for
+@@ -428,6 +413,20 @@ static struct gpio_desc *of_get_named_gpiod_flags(const struct device_node *np,
+ 	return desc;
+ }
+ 
++int of_get_named_gpio_flags(const struct device_node *np, const char *list_name,
++			    int index, enum of_gpio_flags *flags)
++{
++	struct gpio_desc *desc;
++
++	desc = of_get_named_gpiod_flags(np, list_name, index, flags);
++
++	if (IS_ERR(desc))
++		return PTR_ERR(desc);
++	else
++		return desc_to_gpio(desc);
++}
++EXPORT_SYMBOL_GPL(of_get_named_gpio_flags);
++
+ /**
+  * of_get_named_gpio() - Get a GPIO number to use with GPIO API
+  * @np:		device node to get GPIO from
+diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
+index 77ab69463ae8..5ab57bf43741 100644
+--- a/drivers/mfd/Kconfig
++++ b/drivers/mfd/Kconfig
+@@ -215,6 +215,16 @@ config MFD_AC200
+ 	  This driver include only the core APIs. You have to select individual
+ 	  components like Ethernet PHY or codec under the corresponding menus.
+ 
++config MFD_AC200_SUNXI
++	tristate "X-Powers AC200 (Sunxi)"
++	select MFD_CORE
++	depends on I2C
++	depends on PWM_SUNXI_ENHANCE
++	help
++	  If you say Y here you get support for the X-Powers AC200 IC.
++	  This driver include only the core APIs. You have to select individual
++	  components like Ethernet PHY or RTC under the corresponding menus.
++
+ config MFD_AXP20X
+ 	tristate
+ 	select MFD_CORE
+diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
+index 568ca7b227db..3ba1fcdbbbbd 100644
+--- a/drivers/mfd/Makefile
++++ b/drivers/mfd/Makefile
+@@ -147,6 +147,7 @@ obj-$(CONFIG_MFD_DA9052_I2C)	+= da9052-i2c.o
+ 
+ obj-$(CONFIG_MFD_AC100)		+= ac100.o
+ obj-$(CONFIG_MFD_AC200)		+= ac200.o
++obj-$(CONFIG_MFD_AC200_SUNXI)		+= sunxi-ac200.o
+ obj-$(CONFIG_MFD_AXP20X)	+= axp20x.o
+ obj-$(CONFIG_MFD_AXP20X_I2C)	+= axp20x-i2c.o
+ obj-$(CONFIG_MFD_AXP20X_RSB)	+= axp20x-rsb.o
+diff --git a/drivers/mfd/sunxi-ac200.c b/drivers/mfd/sunxi-ac200.c
+new file mode 100644
+index 000000000000..75c032ce147f
+--- /dev/null
++++ b/drivers/mfd/sunxi-ac200.c
+@@ -0,0 +1,289 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * MFD core driver for X-Powers' AC200 IC
++ *
++ * The AC200 is a chip which is co-packaged with Allwinner H6 SoC and
++ * includes analog audio codec, analog TV encoder, ethernet PHY, eFuse
++ * and RTC.
++ *
++ * Copyright (c) 2020 Jernej Skrabec <jernej.skrabec@siol.net>
++ */
++
++#include <linux/i2c.h>
++#include <linux/interrupt.h>
++#include <linux/kernel.h>
++#include <linux/mfd/core.h>
++#include <linux/mfd/ac200.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/nvmem-consumer.h>
++
++#define SUNXI_AC300_KEY	(0x1 << 8)
++
++/* Interrupts */
++#define AC200_IRQ_RTC  0
++#define AC200_IRQ_EPHY 1
++#define AC200_IRQ_TVE  2
++
++/* IRQ enable register */
++#define AC200_SYS_IRQ_ENABLE_OUT_EN BIT(15)
++#define AC200_SYS_IRQ_ENABLE_RTC    BIT(12)
++#define AC200_SYS_IRQ_ENABLE_EPHY   BIT(8)
++#define AC200_SYS_IRQ_ENABLE_TVE    BIT(4)
++
++static const struct regmap_range_cfg ac200_range_cfg[] = {
++	{
++		.range_min = AC200_SYS_VERSION,
++		.range_max = AC200_IC_CHARA1,
++		.selector_reg = AC200_TWI_REG_ADDR_H,
++		.selector_mask = 0xff,
++		.selector_shift = 0,
++		.window_start = 0,
++		.window_len = 256,
++	}
++};
++
++static const struct regmap_config ac200_regmap_config = {
++	.name = "ac200",
++	.reg_bits	= 8,
++	.val_bits	= 16,
++	.ranges		= ac200_range_cfg,
++	.num_ranges	= ARRAY_SIZE(ac200_range_cfg),
++	.max_register	= AC200_IC_CHARA1,
++};
++
++static const struct regmap_irq ac200_regmap_irqs[] = {
++	REGMAP_IRQ_REG(AC200_IRQ_RTC,  0, AC200_SYS_IRQ_ENABLE_RTC),
++	REGMAP_IRQ_REG(AC200_IRQ_EPHY, 0, AC200_SYS_IRQ_ENABLE_EPHY),
++	REGMAP_IRQ_REG(AC200_IRQ_TVE,  0, AC200_SYS_IRQ_ENABLE_TVE),
++};
++
++static const struct regmap_irq_chip ac200_regmap_irq_chip = {
++	.name			= "ac200_irq_chip",
++	.status_base		= AC200_SYS_IRQ_STATUS,
++	.mask_base		= AC200_SYS_IRQ_ENABLE,
++	.irqs			= ac200_regmap_irqs,
++	.num_irqs		= ARRAY_SIZE(ac200_regmap_irqs),
++	.num_regs		= 1,
++};
++
++static const struct resource ephy_resource[] = {
++	DEFINE_RES_IRQ(AC200_IRQ_EPHY),
++};
++
++static const struct mfd_cell ac200_cells[] = {
++	{
++		.name		= "ac200-ephy-sunxi",
++		.num_resources	= ARRAY_SIZE(ephy_resource),
++		.resources	= ephy_resource,
++		.of_compatible	= "x-powers,ac200-ephy-sunxi",
++	},
++	{
++		.name = "acx00-codec",
++		.of_compatible	= "x-powers,ac200-codec-sunxi",
++	},
++};
++
++atomic_t ac200_en;
++
++int ac200_enable(void)
++{
++    return atomic_read(&ac200_en);
++}
++
++EXPORT_SYMBOL(ac200_enable);
++
++static uint16_t ephy_caldata = 0;
++
++static int sun50i_ephy_get_calibrate(struct device *dev)
++{
++	struct nvmem_cell *calcell;
++	uint16_t *caldata;
++	size_t callen;
++	int ret = 0;
++
++	calcell = devm_nvmem_cell_get(dev, "calibration");
++	if (IS_ERR(calcell)) {
++		dev_err_probe(dev, PTR_ERR(calcell),
++			      "Failed to get calibration nvmem cell (%pe)\n",
++			      calcell);
++
++		if (PTR_ERR(calcell) == -EPROBE_DEFER)
++			return -EPROBE_DEFER;
++		goto out;
++	}
++
++	caldata = nvmem_cell_read(calcell, &callen);
++	if (IS_ERR(caldata)) {
++		ret = PTR_ERR(caldata);
++		dev_err(dev, "Failed to read calibration data (%pe)\n",
++			caldata);
++		goto out;
++	}
++
++    ephy_caldata = *caldata;
++	kfree(caldata);
++out:
++	return ret;
++}
++
++uint16_t sun50i_ephy_calibrate_value(void)
++{
++    return ephy_caldata;
++}
++
++EXPORT_SYMBOL(sun50i_ephy_calibrate_value);
++
++static int ac200_i2c_probe(struct i2c_client *i2c)
++{
++    struct device *dev = &i2c->dev;
++    struct ac200_dev *ac200;
++    uint32_t ephy_cal;
++    int ret;
++
++    // 24Mhz clock for both ac200 and ac300 devices
++    ac200 = devm_kzalloc(dev, sizeof(*ac200), GFP_KERNEL);
++    if (!ac200)
++        return -ENOMEM;
++
++    ac200->clk = devm_clk_get(dev, NULL);
++    if (IS_ERR(ac200->clk)) {
++        dev_err(dev, "Can't obtain the clock!\n");
++        return PTR_ERR(ac200->clk);
++    }
++
++    ret = clk_prepare_enable(ac200->clk);
++    if (ret) {
++        dev_err(dev, "rclk_prepare_enable failed! \n");
++        return ret;
++    }
++
++    ret = sun50i_ephy_get_calibrate(dev);
++	if (ret) {
++        dev_err(dev, "sun50i get ephy id failed\n");
++        return ret;
++    }
++    ephy_cal = sun50i_ephy_calibrate_value();
++
++    if (ephy_cal & SUNXI_AC300_KEY) {
++        pr_warn("it's ac300, skip the ac200 init!\n");
++        return -EINVAL;
++    } else {
++        pr_warn("it's ac200, ac200 init start!\n");
++    }
++
++    i2c_set_clientdata(i2c, ac200);
++
++    ac200->regmap = devm_regmap_init_i2c(i2c, &ac200_regmap_config);
++    if (IS_ERR(ac200->regmap))
++    {
++        ret = PTR_ERR(ac200->regmap);
++        dev_err(dev, "regmap init failed: %d\n", ret);
++        return ret;
++    }
++
++    /* do a reset to put chip in a known state */
++    ret = regmap_write(ac200->regmap, AC200_SYS_CONTROL, 0);
++    if (ret)
++    {
++        dev_err(dev, "AC200_SYS_CONTROL 0 failed! \n");
++        return ret;
++    }
++	atomic_set(&ac200_en, 0);
++
++    ret = regmap_write(ac200->regmap, AC200_SYS_CONTROL, 1);
++    if (ret)
++    {
++        dev_err(dev, "AC200_SYS_CONTROL 1 failed! \n");
++        return ret;
++    }
++	atomic_set(&ac200_en, 1);
++
++    ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE, ac200_cells,
++                               ARRAY_SIZE(ac200_cells), NULL, 0, NULL);
++    if (ret)
++    {
++        dev_err(dev, "failed to add MFD devices: %d\n", ret);
++        return ret;
++    }
++    else
++    {
++        dev_err(dev, "add MFD devices success! \n");
++    }
++
++    return 0;
++}
++
++static void ac200_i2c_remove(struct i2c_client *i2c)
++{
++	struct ac200_dev *ac200 = i2c_get_clientdata(i2c);
++
++	regmap_write(ac200->regmap, AC200_SYS_CONTROL, 0);
++	mfd_remove_devices(&i2c->dev);
++}
++
++static void ac200_i2c_shutdown(struct i2c_client *i2c)
++{
++    struct ac200_dev *ac200 = i2c_get_clientdata(i2c);
++
++    regmap_write(ac200->regmap, AC200_SYS_CONTROL, 0);
++}
++
++static int ac200_i2c_suspend(struct device *dev)
++{
++	struct ac200_dev *ac200 = dev_get_drvdata(dev);
++
++	if (!IS_ERR_OR_NULL(ac200->clk))
++		clk_disable_unprepare(ac200->clk);
++
++	atomic_set(&ac200_en, 0);
++	return 0;
++}
++
++static int ac200_i2c_resume(struct device *dev)
++{
++	struct ac200_dev *ac200 = dev_get_drvdata(dev);
++
++	if (!IS_ERR_OR_NULL(ac200->clk))
++		clk_prepare_enable(ac200->clk);
++
++	atomic_set(&ac200_en, 0);
++	msleep(40);
++    regmap_write(ac200->regmap, AC200_SYS_CONTROL, 1);
++	atomic_set(&ac200_en, 1);
++	return 0;
++}
++
++static const struct dev_pm_ops ac200_core_pm_ops = {
++	.suspend_late = ac200_i2c_suspend,
++	.resume_early = ac200_i2c_resume,
++};
++
++static const struct i2c_device_id ac200_ids[] = {
++	{ "ac200", },
++	{ /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(i2c, ac200_ids);
++
++static const struct of_device_id ac200_of_match[] = {
++	{ .compatible = "x-powers,ac200-sunxi" },
++	{ /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, ac200_of_match);
++
++static struct i2c_driver ac200_i2c_driver = {
++	.driver = {
++		.name	= "ac200-sunxi",
++		.of_match_table	= of_match_ptr(ac200_of_match),
++        .pm = &ac200_core_pm_ops,
++	},
++	.probe	= ac200_i2c_probe,
++	.remove = ac200_i2c_remove,
++	.shutdown = ac200_i2c_shutdown,
++	.id_table = ac200_ids,
++};
++module_i2c_driver(ac200_i2c_driver);
++
++MODULE_DESCRIPTION("MFD core driver for AC200");
++MODULE_AUTHOR("Jernej Skrabec <jernej.skrabec@siol.net>");
++MODULE_LICENSE("GPL v2");
+diff --git a/drivers/net/ethernet/allwinner/Kconfig b/drivers/net/ethernet/allwinner/Kconfig
+index 3e81059f8693..36d808810ca4 100644
+--- a/drivers/net/ethernet/allwinner/Kconfig
++++ b/drivers/net/ethernet/allwinner/Kconfig
+@@ -34,4 +34,12 @@ config SUN4I_EMAC
+ 	  To compile this driver as a module, choose M here.  The module
+ 	  will be called sun4i-emac.
+ 
++config SUNXI_GMAC
++    tristate "Allwinner GMAC support"
++	depends on ARCH_SUNXI
++	depends on OF
++	depends on AC200_PHY_SUNXI
++	select CRC32
++	select MII
++
+ endif # NET_VENDOR_ALLWINNER
+diff --git a/drivers/net/ethernet/allwinner/Makefile b/drivers/net/ethernet/allwinner/Makefile
+index ddd5a5079e8a..56b9c434a5b8 100644
+--- a/drivers/net/ethernet/allwinner/Makefile
++++ b/drivers/net/ethernet/allwinner/Makefile
+@@ -4,3 +4,5 @@
+ #
+ 
+ obj-$(CONFIG_SUN4I_EMAC) += sun4i-emac.o
++sunxi_gmac-objs := sunxi_gmac_ops.o sunxi-gmac.o
++obj-$(CONFIG_SUNXI_GMAC) += sunxi_gmac.o
+diff --git a/drivers/net/ethernet/allwinner/sunxi-gmac.c b/drivers/net/ethernet/allwinner/sunxi-gmac.c
+new file mode 100644
+index 000000000000..249cee0607e3
+--- /dev/null
++++ b/drivers/net/ethernet/allwinner/sunxi-gmac.c
+@@ -0,0 +1,2217 @@
++/*
++ * linux/drivers/net/ethernet/allwinner/sunxi_gmac.c
++ *
++ * Copyright © 2016-2018, fuzhaoke
++ *		Author: fuzhaoke <fuzhaoke@allwinnertech.com>
++ *
++ * This file is provided under a dual BSD/GPL license.  When using or
++ * redistributing this file, you may do so under either license.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
++ * GNU General Public License for more details.
++ */
++#include <linux/clk.h>
++#include <linux/clk-provider.h>
++#include <linux/mii.h>
++#include <linux/gpio.h>
++#include <linux/crc32.h>
++#include <linux/skbuff.h>
++#include <linux/module.h>
++#include <linux/kernel.h>
++#include <linux/interrupt.h>
++#include <linux/dma-mapping.h>
++#include <linux/platform_device.h>
++#include <linux/pinctrl/consumer.h>
++#include <linux/pinctrl/pinctrl.h>
++#include <linux/crypto.h>
++#include <crypto/algapi.h>
++#include <crypto/hash.h>
++#include <linux/err.h>
++#include <linux/scatterlist.h>
++#include <linux/regulator/consumer.h>
++#include <linux/of_net.h>
++#include <linux/of_gpio.h>
++#include <linux/io.h>
++#include "sunxi-gmac.h"
++#include <linux/timer.h>
++#include <linux/phylink.h>
++#include <linux/reset.h>
++
++
++int sunxi_get_soc_chipid(unsigned char *chipid);
++
++#define DMA_DESC_RX 256
++#define DMA_DESC_TX 256
++#define BUDGET      (dma_desc_rx / 4)
++#define TX_THRESH   (dma_desc_tx / 4)
++
++#define HASH_TABLE_SIZE 64
++#define MAX_BUF_SZ      (SZ_2K - 1)
++
++#define POWER_CHAN_NUM  3
++
++#undef PKT_DEBUG
++#undef DESC_PRINT
++
++#define circ_cnt(head, tail, size) (((head) > (tail)) ? ((head) - (tail)) : ((head) - (tail)) & ((size) - 1))
++
++#define circ_space(head, tail, size) circ_cnt((tail), ((head) + 1), (size))
++
++#define circ_inc(n, s) (((n) + 1) % (s))
++
++#define GETH_MAC_ADDRESS "01:02:03:04:05:06"
++static char *mac_str = GETH_MAC_ADDRESS;
++module_param(mac_str, charp, S_IRUGO | S_IWUSR);
++MODULE_PARM_DESC(mac_str, "MAC Address String.(xx:xx:xx:xx:xx:xx)");
++
++static int rxmode = 1;
++module_param(rxmode, int, S_IRUGO | S_IWUSR);
++MODULE_PARM_DESC(rxmode, "DMA threshold control value");
++
++static int txmode = 1;
++module_param(txmode, int, S_IRUGO | S_IWUSR);
++MODULE_PARM_DESC(txmode, "DMA threshold control value");
++
++static int pause = 0x400;
++module_param(pause, int, S_IRUGO | S_IWUSR);
++MODULE_PARM_DESC(pause, "Flow Control Pause Time");
++
++#define TX_TIMEO 5000
++static int watchdog = TX_TIMEO;
++module_param(watchdog, int, S_IRUGO | S_IWUSR);
++MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds");
++
++static int dma_desc_rx = DMA_DESC_RX;
++module_param(dma_desc_rx, int, S_IRUGO | S_IWUSR);
++MODULE_PARM_DESC(watchdog, "The number of receive's descriptors");
++
++static int dma_desc_tx = DMA_DESC_TX;
++module_param(dma_desc_tx, int, S_IRUGO | S_IWUSR);
++MODULE_PARM_DESC(watchdog, "The number of transmit's descriptors");
++
++/* - 0: Flow Off
++ * - 1: Rx Flow
++ * - 2: Tx Flow
++ * - 3: Rx & Tx Flow
++ */
++static int flow_ctrl;
++module_param(flow_ctrl, int, S_IRUGO | S_IWUSR);
++MODULE_PARM_DESC(flow_ctrl, "Flow control [0: off, 1: rx, 2: tx, 3: both]");
++
++static unsigned long tx_delay;
++module_param(tx_delay, ulong, S_IRUGO | S_IWUSR);
++MODULE_PARM_DESC(tx_delay, "Adjust transmit clock delay, value: 0~7");
++
++static unsigned long rx_delay;
++module_param(rx_delay, ulong, S_IRUGO | S_IWUSR);
++MODULE_PARM_DESC(rx_delay, "Adjust receive clock delay, value: 0~31");
++
++/* whether using ephy_clk */
++static int g_use_ephy_clk;
++static int g_phy_addr;
++
++struct geth_priv {
++    struct dma_desc *dma_tx;
++    struct sk_buff **tx_sk;
++    unsigned int tx_clean;
++    unsigned int tx_dirty;
++    dma_addr_t dma_tx_phy;
++
++    struct reset_control *ephy_rst;
++
++    unsigned long buf_sz;
++
++    struct dma_desc *dma_rx;
++    struct sk_buff **rx_sk;
++    unsigned int rx_clean;
++    unsigned int rx_dirty;
++    dma_addr_t dma_rx_phy;
++
++    struct net_device *ndev;
++    struct device *dev;
++    struct napi_struct napi;
++
++    struct geth_extra_stats xstats;
++
++    struct mii_bus *mii;
++    int link;
++    int speed;
++    int duplex;
++#define INT_PHY 0
++#define EXT_PHY 1
++    int phy_ext;
++    int phy_interface;
++
++    void __iomem *base;
++    void __iomem *base_phy;
++    struct clk *geth_clk;
++    struct clk *ephy_clk;
++    struct pinctrl *pinctrl;
++
++    struct regulator *gmac_power[POWER_CHAN_NUM];
++    bool is_suspend;
++    int phyrst;
++    u8 rst_active_low;
++    /* definition spinlock */
++    spinlock_t lock;
++    spinlock_t tx_lock;
++
++    /* resume work */
++    struct work_struct eth_work;
++};
++
++static u64 geth_dma_mask = DMA_BIT_MASK(32);
++
++void sunxi_udelay(int n)
++{
++    udelay(n);
++}
++
++static int geth_stop(struct net_device *ndev);
++static int geth_open(struct net_device *ndev);
++static void geth_tx_complete(struct geth_priv *priv);
++static void geth_rx_refill(struct net_device *ndev);
++
++#ifdef CONFIG_GETH_ATTRS
++static ssize_t adjust_bgs_show(struct device *dev, struct device_attribute *attr, char *buf)
++{
++    int value = 0;
++    u32 efuse_value;
++    struct net_device *ndev = to_net_dev(dev);
++    struct geth_priv *priv = netdev_priv(ndev);
++
++    if (priv->phy_ext == INT_PHY) {
++        value = readl(priv->base_phy) >> 28;
++        if (sunxi_efuse_read(EFUSE_OEM_NAME, &efuse_value) != 0)
++            pr_err("get PHY efuse fail!\n");
++        else
++#if defined(CONFIG_ARCH_SUN50IW2)
++            value = value - ((efuse_value >> 24) & 0x0F);
++#else
++            pr_warn("miss config come from efuse!\n");
++#endif
++    }
++
++    return sprintf(buf, "bgs: %d\n", value);
++}
++
++static ssize_t adjust_bgs_write(struct device *dev, struct device_attribute *attr,
++                                const char *buf, size_t count)
++{
++    unsigned int out = 0;
++    struct net_device *ndev = to_net_dev(dev);
++    struct geth_priv *priv = netdev_priv(ndev);
++    u32 clk_value = readl(priv->base_phy);
++    u32 efuse_value;
++
++    out = simple_strtoul(buf, NULL, 10);
++
++    if (priv->phy_ext == INT_PHY) {
++        clk_value &= ~(0xF << 28);
++        if (sunxi_efuse_read(EFUSE_OEM_NAME, &efuse_value) != 0)
++            pr_err("get PHY efuse fail!\n");
++        else
++#if defined(CONFIG_ARCH_SUN50IW2)
++            clk_value |= (((efuse_value >> 24) & 0x0F) + out) << 28;
++#else
++            pr_warn("miss config come from efuse!\n");
++#endif
++    }
++
++    writel(clk_value, priv->base_phy);
++
++    return count;
++}
++
++static struct device_attribute adjust_reg[] = {
++    __ATTR(adjust_bgs, 0664, adjust_bgs_show, adjust_bgs_write),
++};
++
++static int geth_create_attrs(struct net_device *ndev)
++{
++    int j, ret;
++
++    for (j = 0; j < ARRAY_SIZE(adjust_reg); j++) {
++        ret = device_create_file(&ndev->dev, &adjust_reg[j]);
++        if (ret)
++            goto sysfs_failed;
++    }
++    goto succeed;
++
++sysfs_failed:
++    while (j--)
++        device_remove_file(&ndev->dev, &adjust_reg[j]);
++succeed:
++    return ret;
++}
++#endif
++
++#ifdef DEBUG
++static void desc_print(struct dma_desc *desc, int size)
++{
++#ifdef DESC_PRINT
++    int i;
++
++    for (i = 0; i < size; i++) {
++        u32 *x = (u32 *)(desc + i);
++
++        pr_info("\t%d [0x%08lx]: %08x %08x %08x %08x\n",
++                i, (unsigned long)(&desc[i]),
++                x[0], x[1], x[2], x[3]);
++    }
++    pr_info("\n");
++#endif
++}
++#endif
++
++static ssize_t gphy_test_show(struct device *dev,
++                              struct device_attribute *attr, char *buf)
++{
++    struct net_device *ndev = dev_get_drvdata(dev);
++
++    if (!dev) {
++        pr_err("Argment is invalid\n");
++        return 0;
++    }
++
++    if (!ndev) {
++        pr_err("Net device is null\n");
++        return 0;
++    }
++
++    return sprintf(buf, "Usage:\necho [0/1/2/3/4] > gphy_test\n"
++                        "0 - Normal Mode\n"
++                        "1 - Transmit Jitter Test\n"
++                        "2 - Transmit Jitter Test(MASTER mode)\n"
++                        "3 - Transmit Jitter Test(SLAVE mode)\n"
++                        "4 - Transmit Distortion Test\n\n");
++}
++
++static ssize_t gphy_test_store(struct device *dev,
++                               struct device_attribute *attr, const char *buf, size_t count)
++{
++    struct net_device *ndev = dev_get_drvdata(dev);
++    struct geth_priv *priv = netdev_priv(ndev);
++    u16 value = 0;
++    int ret = 0;
++    u16 data = 0;
++
++    if (!dev) {
++        pr_err("Argument is invalid\n");
++        return count;
++    }
++
++    if (!ndev) {
++        pr_err("Net device is null\n");
++        return count;
++    }
++
++    data = sunxi_mdio_read(priv->base, g_phy_addr, MII_CTRL1000);
++
++    ret = kstrtou16(buf, 0, &value);
++    if (ret)
++        return ret;
++
++    if (value >= 0 && value <= 4) {
++        data &= ~(0x7 << 13);
++        data |= value << 13;
++        sunxi_mdio_write(priv->base, g_phy_addr, MII_CTRL1000, data);
++        pr_info("Set MII_CTRL1000(0x09) Reg: 0x%x\n", data);
++    } else {
++        pr_info("unknown value (%d)\n", value);
++    }
++
++    return count;
++}
++
++static DEVICE_ATTR(gphy_test, 0664, gphy_test_show, gphy_test_store);
++
++static struct mii_reg_dump mii_reg;
++
++static ssize_t mii_read_show(struct device *dev,
++                             struct device_attribute *attr, char *buf)
++{
++    struct net_device *ndev;
++    struct geth_priv *priv;
++
++    if (!dev) {
++        pr_err("Argment is invalid\n");
++        return 0;
++    }
++
++    ndev = dev_get_drvdata(dev);
++    if (!ndev) {
++        pr_err("Net device is null\n");
++        return 0;
++    }
++
++    priv = netdev_priv(ndev);
++    if (!priv) {
++        pr_err("geth_priv is null\n");
++        return 0;
++    }
++
++    if (!netif_running(ndev)) {
++        pr_warn("eth is down!\n");
++        return 0;
++    }
++
++    mii_reg.value = sunxi_mdio_read(priv->base, mii_reg.addr, mii_reg.reg);
++    return sprintf(buf, "ADDR[0x%02x]:REG[0x%02x] = 0x%04x\n",
++               mii_reg.addr, mii_reg.reg, mii_reg.value);
++}
++
++static ssize_t mii_read_store(struct device *dev,
++                              struct device_attribute *attr, const char *buf, size_t count)
++{
++    struct net_device *ndev;
++    struct geth_priv *priv;
++    int ret = 0;
++    u16 reg, addr;
++    char *ptr;
++
++    ptr = (char *)buf;
++
++    if (!dev) {
++        pr_err("Argment is invalid\n");
++        return count;
++    }
++
++    ndev = dev_get_drvdata(dev);
++    if (!ndev) {
++        pr_err("Net device is null\n");
++        return count;
++    }
++
++    priv = netdev_priv(ndev);
++    if (!priv) {
++        pr_err("geth_priv is null\n");
++        return count;
++    }
++
++    if (!netif_running(ndev)) {
++        pr_warn("eth is down!\n");
++        return count;
++    }
++
++    ret = sunxi_parse_read_str(ptr, &addr, &reg);
++    if (ret)
++        return ret;
++
++    mii_reg.addr = addr;
++    mii_reg.reg = reg;
++
++    return count;
++}
++
++static DEVICE_ATTR(mii_read, 0664, mii_read_show, mii_read_store);
++
++static ssize_t mii_write_show(struct device *dev,
++                              struct device_attribute *attr, char *buf)
++{
++    struct net_device *ndev;
++    struct geth_priv *priv;
++    u16 bef_val, aft_val;
++
++    if (!dev) {
++        pr_err("Argment is invalid\n");
++        return 0;
++    }
++
++    ndev = dev_get_drvdata(dev);
++    if (!ndev) {
++        pr_err("Net device is null\n");
++        return 0;
++    }
++
++    priv = netdev_priv(ndev);
++    if (!priv) {
++        pr_err("geth_priv is null\n");
++        return 0;
++    }
++
++    if (!netif_running(ndev)) {
++        pr_warn("eth is down!\n");
++        return 0;
++    }
++
++    bef_val = sunxi_mdio_read(priv->base, mii_reg.addr, mii_reg.reg);
++    sunxi_mdio_write(priv->base, mii_reg.addr, mii_reg.reg, mii_reg.value);
++    aft_val = sunxi_mdio_read(priv->base, mii_reg.addr, mii_reg.reg);
++    return sprintf(buf, "before ADDR[0x%02x]:REG[0x%02x] = 0x%04x\n"
++                "after  ADDR[0x%02x]:REG[0x%02x] = 0x%04x\n",
++                mii_reg.addr, mii_reg.reg, bef_val,
++                mii_reg.addr, mii_reg.reg, aft_val);
++}
++
++static ssize_t mii_write_store(struct device *dev,
++                               struct device_attribute *attr, const char *buf, size_t count)
++{
++    struct net_device *ndev;
++    struct geth_priv *priv;
++    int ret = 0;
++    u16 reg, addr, val;
++    char *ptr;
++
++    ptr = (char *)buf;
++
++    if (!dev) {
++        pr_err("Argment is invalid\n");
++        return count;
++    }
++
++    ndev = dev_get_drvdata(dev);
++    if (!ndev) {
++        pr_err("Net device is null\n");
++        return count;
++    }
++
++    priv = netdev_priv(ndev);
++    if (!priv) {
++        pr_err("geth_priv is null\n");
++        return count;
++    }
++
++    if (!netif_running(ndev)) {
++        pr_warn("eth is down!\n");
++        return count;
++    }
++
++    ret = sunxi_parse_write_str(ptr, &addr, &reg, &val);
++    if (ret)
++        return ret;
++
++    mii_reg.reg = reg;
++    mii_reg.addr = addr;
++    mii_reg.value = val;
++
++    return count;
++}
++
++static DEVICE_ATTR(mii_write, 0664, mii_write_show, mii_write_store);
++
++static int geth_power_on(struct geth_priv *priv)
++{
++    int value;
++    int i;
++
++    value = readl(priv->base_phy);
++    if (priv->phy_ext == INT_PHY) {
++        value |= (1 << 15);
++        value &= ~(1 << 16);
++        value |= (3 << 17);
++    } else {
++        value &= ~(1 << 15);
++
++        for (i = 0; i < POWER_CHAN_NUM; i++) {
++            if (IS_ERR_OR_NULL(priv->gmac_power[i]))
++                continue;
++            if (regulator_enable(priv->gmac_power[i]) != 0) {
++                pr_err("gmac-power%d enable error\n", i);
++                return -EINVAL;
++            }
++        }
++    }
++
++    writel(value, priv->base_phy);
++
++    return 0;
++}
++
++static void geth_power_off(struct geth_priv *priv)
++{
++    int value;
++    int i;
++
++    if (priv->phy_ext == INT_PHY) {
++        value = readl(priv->base_phy);
++        value |= (1 << 16);
++        writel(value, priv->base_phy);
++    } else {
++        for (i = 0; i < POWER_CHAN_NUM; i++) {
++            if (IS_ERR_OR_NULL(priv->gmac_power[i]))
++                continue;
++            regulator_disable(priv->gmac_power[i]);
++        }
++    }
++}
++
++/* PHY interface operations */
++static int geth_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg)
++{
++    struct net_device *ndev = bus->priv;
++    struct geth_priv *priv = netdev_priv(ndev);
++
++    return (int)sunxi_mdio_read(priv->base, phyaddr, phyreg);
++}
++
++static int geth_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg, u16 data)
++{
++    struct net_device *ndev = bus->priv;
++    struct geth_priv *priv = netdev_priv(ndev);
++
++    sunxi_mdio_write(priv->base, phyaddr, phyreg, data);
++
++    return 0;
++}
++
++static int geth_mdio_reset(struct mii_bus *bus)
++{
++    struct net_device *ndev = bus->priv;
++    struct geth_priv *priv = netdev_priv(ndev);
++
++    return sunxi_mdio_reset(priv->base);
++}
++
++static void geth_adjust_link(struct net_device *ndev)
++{
++    struct geth_priv *priv = netdev_priv(ndev);
++    struct phy_device *phydev = ndev->phydev;
++    unsigned long flags;
++    int new_state = 0;
++
++    if (!phydev)
++        return;
++
++    spin_lock_irqsave(&priv->lock, flags);
++    if (phydev->link) {
++        /* Now we make sure that we can be in full duplex mode.
++         * If not, we operate in half-duplex mode.
++         */
++        if (phydev->duplex != priv->duplex) {
++            new_state = 1;
++            priv->duplex = phydev->duplex;
++        }
++        /* Flow Control operation */
++        if (phydev->pause)
++            sunxi_flow_ctrl(priv->base, phydev->duplex, flow_ctrl, pause);
++
++        if (phydev->speed != priv->speed) {
++            new_state = 1;
++            priv->speed = phydev->speed;
++        }
++
++        if (priv->link == 0) {
++            new_state = 1;
++            priv->link = phydev->link;
++        }
++
++        if (new_state)
++            sunxi_set_link_mode(priv->base, priv->duplex, priv->speed);
++
++#ifdef LOOPBACK_DEBUG
++        phydev->state = PHY_FORCING;
++#endif
++
++    } else if (priv->link != phydev->link) {
++        new_state = 1;
++        priv->link = 0;
++        priv->speed = 0;
++        priv->duplex = -1;
++    }
++
++    if (new_state)
++        phy_print_status(phydev);
++
++    spin_unlock_irqrestore(&priv->lock, flags);
++}
++
++static int geth_phy_init(struct net_device *ndev)
++{
++    int value;
++    struct mii_bus *new_bus;
++    struct geth_priv *priv = netdev_priv(ndev);
++    struct phy_device *phydev = ndev->phydev;
++    u32 supported = 0, advertising = 0;
++
++    /* Fixup the phy interface type */
++    if (priv->phy_ext == INT_PHY) {
++        priv->phy_interface = PHY_INTERFACE_MODE_MII;
++    } else {
++        /* If config gpio to reset the phy device, we should reset it */
++        if (gpio_is_valid(priv->phyrst)) {
++            gpio_direction_output(priv->phyrst, priv->rst_active_low);
++            msleep(50);
++            gpio_direction_output(priv->phyrst, !priv->rst_active_low);
++            msleep(50);
++        }
++    }
++
++    new_bus = mdiobus_alloc();
++    if (!new_bus) {
++        netdev_err(ndev, "Failed to alloc new mdio bus\n");
++        return -ENOMEM;
++    }
++
++    new_bus->name = dev_name(priv->dev);
++    new_bus->read = &geth_mdio_read;
++    new_bus->write = &geth_mdio_write;
++    new_bus->reset = &geth_mdio_reset;
++    snprintf(new_bus->id, MII_BUS_ID_SIZE, "%s-%x", new_bus->name, 0);
++
++    new_bus->parent = priv->dev;
++    new_bus->priv = ndev;
++
++    if (mdiobus_register(new_bus)) {
++        pr_err("%s: Cannot register as MDIO bus\n", new_bus->name);
++        goto reg_fail;
++    }
++
++    priv->mii = new_bus;
++
++    {
++        int addr;
++        for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
++            struct phy_device *phydev_tmp = mdiobus_get_phy(new_bus, addr);
++
++            if (IS_ERR_OR_NULL(phydev_tmp) || phydev_tmp->phy_id == 0xffff) {
++                if (!IS_ERR_OR_NULL(phydev_tmp))
++                    phy_device_remove(phydev_tmp);
++                phydev_tmp = mdiobus_scan_c22(new_bus, addr);
++            }
++
++            if (IS_ERR_OR_NULL(phydev_tmp) || phydev_tmp->phy_id == 0xffff ||
++                phydev_tmp->phy_id == 0x00 || phydev_tmp->phy_id == AC300_ID)
++                continue;
++
++            if (phydev_tmp->phy_id == EPHY_ID || phydev_tmp->phy_id == IP101G_ID) {
++                phydev = phydev_tmp;
++                g_phy_addr = addr;
++                break;
++            }
++        }
++    }
++
++    if (!phydev) {
++        netdev_err(ndev, "No PHY found!\n");
++        goto err;
++    }
++
++    phy_write(phydev, MII_BMCR, BMCR_RESET);
++    while (BMCR_RESET & phy_read(phydev, MII_BMCR))
++        msleep(30);
++
++    value = phy_read(phydev, MII_BMCR);
++    phy_write(phydev, MII_BMCR, (value & ~BMCR_PDOWN));
++
++    phydev->irq = PHY_POLL;
++
++    value = phy_connect_direct(ndev, phydev, &geth_adjust_link, priv->phy_interface);
++    if (value) {
++        netdev_err(ndev, "Could not attach to PHY\n");
++        goto err;
++    } else {
++        netdev_info(ndev, "%s: Type(%d) PHY ID %08x at %d IRQ %s (%s)\n",
++                ndev->name, phydev->interface, phydev->phy_id,
++                phydev->mdio.addr, "poll", dev_name(&phydev->mdio.dev));
++    }
++
++#if 0
++    phydev->supported &= PHY_GBIT_FEATURES; //kandy 000002cf
++    phydev->advertising = phydev->supported;
++#else
++
++    ethtool_convert_link_mode_to_legacy_u32(&supported, phydev->supported);
++
++    advertising = supported &= *PHY_BASIC_FEATURES; // kandy 000002cf
++
++    ethtool_convert_legacy_u32_to_link_mode(phydev->supported, supported);
++    ethtool_convert_legacy_u32_to_link_mode(phydev->advertising, advertising);
++#endif
++
++    if (priv->phy_ext == INT_PHY) {
++        /* EPHY Initial */
++        phy_write(phydev, 0x1f, 0x0100); /* switch to page 1 */
++        phy_write(phydev, 0x12, 0x4824); /* Disable APS */
++        phy_write(phydev, 0x1f, 0x0200); /* switchto page 2 */
++        phy_write(phydev, 0x18, 0x0000); /* PHYAFE TRX optimization */
++        phy_write(phydev, 0x1f, 0x0600); /* switchto page 6 */
++        phy_write(phydev, 0x14, 0x708F); /* PHYAFE TX optimization */
++        phy_write(phydev, 0x19, 0x0000);
++        phy_write(phydev, 0x13, 0xf000); /* PHYAFE RX optimization */
++        phy_write(phydev, 0x15, 0x1530);
++        phy_write(phydev, 0x1f, 0x0800); /* switch to page 8 */
++        phy_write(phydev, 0x18, 0x00bc); /* PHYAFE TRX optimization */
++        phy_write(phydev, 0x1f, 0x0100); /* switchto page 1 */
++        /* reg 0x17 bit3,set 0 to disable iEEE */
++        phy_write(phydev, 0x17, phy_read(phydev, 0x17) & (~(1<<3)));
++        phy_write(phydev, 0x1f, 0x0000); /* switch to page 0 */
++    }
++
++    return 0;
++
++err:
++    mdiobus_unregister(new_bus);
++reg_fail:
++    mdiobus_free(new_bus);
++
++    return -EINVAL;
++}
++
++static int geth_phy_release(struct net_device *ndev)
++{
++    struct geth_priv *priv = netdev_priv(ndev);
++    struct phy_device *phydev = ndev->phydev;
++    int value = 0;
++
++    /* Stop and disconnect the PHY */
++    if (phydev)
++        phy_stop(phydev);
++
++    priv->link = PHY_DOWN;
++    priv->speed = 0;
++    priv->duplex = -1;
++
++    if (phydev) {
++        value = phy_read(phydev, MII_BMCR);
++        phy_write(phydev, MII_BMCR, (value | BMCR_PDOWN));
++        phy_disconnect(phydev);
++        ndev->phydev = NULL;
++    }
++
++#if 1 // defined(CONFIG_SUNXI_EPHY)
++    gmac_ephy_shutdown(); /* Turn off the clock of PHY for low power consumption  */
++#endif
++
++    if (priv->mii) {
++        mdiobus_unregister(priv->mii);
++        priv->mii->priv = NULL;
++        mdiobus_free(priv->mii);
++        priv->mii = NULL;
++    }
++
++    return 0;
++}
++
++static void geth_rx_refill(struct net_device *ndev)
++{
++    struct geth_priv *priv = netdev_priv(ndev);
++    struct dma_desc *desc;
++    struct sk_buff *sk = NULL;
++    dma_addr_t paddr;
++
++    while (circ_space(priv->rx_clean, priv->rx_dirty, dma_desc_rx) > 0) {
++        int entry = priv->rx_clean;
++
++        /* Find the dirty's desc and clean it */
++        desc = priv->dma_rx + entry;
++
++        if (priv->rx_sk[entry] == NULL) {
++            sk = netdev_alloc_skb_ip_align(ndev, priv->buf_sz);
++
++            if (unlikely(sk == NULL))
++                break;
++
++            priv->rx_sk[entry] = sk;
++            paddr = dma_map_single(priv->dev, sk->data,
++                           priv->buf_sz, DMA_FROM_DEVICE);
++            desc_buf_set(desc, paddr, priv->buf_sz);
++        }
++
++        /* sync memery */
++        wmb();
++        desc_set_own(desc);
++        priv->rx_clean = circ_inc(priv->rx_clean, dma_desc_rx);
++    }
++}
++
++/* geth_dma_desc_init - initialize the RX/TX descriptor list
++ * @ndev: net device structure
++ * Description: initialize the list for dma.
++ */
++static int geth_dma_desc_init(struct net_device *ndev)
++{
++    struct geth_priv *priv = netdev_priv(ndev);
++    unsigned int buf_sz;
++
++    priv->rx_sk = kzalloc(sizeof(struct sk_buff *) * dma_desc_rx, GFP_KERNEL);
++    if (!priv->rx_sk)
++        return -ENOMEM;
++
++    priv->tx_sk = kzalloc(sizeof(struct sk_buff *) * dma_desc_tx, GFP_KERNEL);
++    if (!priv->tx_sk)
++        goto tx_sk_err;
++
++    /* Set the size of buffer depend on the MTU & max buf size */
++    buf_sz = MAX_BUF_SZ;
++
++    priv->dma_tx = dma_alloc_coherent(priv->dev,
++                                      dma_desc_tx * sizeof(struct dma_desc),
++                                      &priv->dma_tx_phy,
++                                      GFP_KERNEL);
++    if (!priv->dma_tx)
++        goto dma_tx_err;
++
++    priv->dma_rx = dma_alloc_coherent(priv->dev,
++                                      dma_desc_rx * sizeof(struct dma_desc),
++                                      &priv->dma_rx_phy,
++                                      GFP_KERNEL);
++    if (!priv->dma_rx)
++        goto dma_rx_err;
++
++    priv->buf_sz = buf_sz;
++
++    return 0;
++
++dma_rx_err:
++    dma_free_coherent(priv->dev, dma_desc_rx * sizeof(struct dma_desc), priv->dma_tx, priv->dma_tx_phy);
++dma_tx_err:
++    kfree(priv->tx_sk);
++tx_sk_err:
++    kfree(priv->rx_sk);
++
++    return -ENOMEM;
++}
++
++static void geth_free_rx_sk(struct geth_priv *priv)
++{
++    int i;
++
++    for (i = 0; i < dma_desc_rx; i++) {
++        if (priv->rx_sk[i] != NULL) {
++            struct dma_desc *desc = priv->dma_rx + i;
++
++            dma_unmap_single(priv->dev, (u32)desc_buf_get_addr(desc), desc_buf_get_len(desc), DMA_FROM_DEVICE);
++            dev_kfree_skb_any(priv->rx_sk[i]);
++            priv->rx_sk[i] = NULL;
++        }
++    }
++}
++
++static void geth_free_tx_sk(struct geth_priv *priv)
++{
++    int i;
++
++    for (i = 0; i < dma_desc_tx; i++) {
++        if (priv->tx_sk[i] != NULL) {
++            struct dma_desc *desc = priv->dma_tx + i;
++
++            if (desc_buf_get_addr(desc))
++                dma_unmap_single(priv->dev, (u32)desc_buf_get_addr(desc), desc_buf_get_len(desc), DMA_TO_DEVICE);
++            dev_kfree_skb_any(priv->tx_sk[i]);
++            priv->tx_sk[i] = NULL;
++        }
++    }
++}
++
++static void geth_free_dma_desc(struct geth_priv *priv)
++{
++    /* Free the region of consistent memory previously allocated for the DMA */
++    dma_free_coherent(priv->dev, dma_desc_tx * sizeof(struct dma_desc), priv->dma_tx, priv->dma_tx_phy);
++    dma_free_coherent(priv->dev, dma_desc_rx * sizeof(struct dma_desc), priv->dma_rx, priv->dma_rx_phy);
++
++    kfree(priv->rx_sk);
++    kfree(priv->tx_sk);
++}
++
++#ifdef CONFIG_PM
++static int geth_select_gpio_state(struct pinctrl *pctrl, char *name)
++{
++    int ret = 0;
++    struct pinctrl_state *pctrl_state = NULL;
++
++    pctrl_state = pinctrl_lookup_state(pctrl, name);
++    if (IS_ERR(pctrl_state)) {
++        pr_err("gmac pinctrl_lookup_state(%s) failed! return %p\n", name, pctrl_state);
++        return -EINVAL;
++    }
++
++    ret = pinctrl_select_state(pctrl, pctrl_state);
++    if (ret < 0)
++        pr_err("gmac pinctrl_select_state(%s) failed! return %d\n", name, ret);
++
++    return ret;
++}
++
++static int geth_suspend(struct device *dev)
++{
++    struct net_device *ndev = dev_get_drvdata(dev);
++    struct geth_priv *priv = netdev_priv(ndev);
++
++    cancel_work_sync(&priv->eth_work);
++
++    if (!ndev || !netif_running(ndev))
++        return 0;
++
++    spin_lock(&priv->lock);
++    netif_device_detach(ndev);
++    spin_unlock(&priv->lock);
++
++    geth_stop(ndev);
++
++    if (priv->phy_ext == EXT_PHY)
++        geth_select_gpio_state(priv->pinctrl, PINCTRL_STATE_SLEEP);
++
++    return 0;
++}
++
++static void geth_resume_work(struct work_struct *work)
++{
++    struct geth_priv *priv = container_of(work, struct geth_priv, eth_work);
++    struct net_device *ndev = priv->ndev;
++
++    if (!netif_running(ndev))
++        return;
++
++    if (priv->phy_ext == EXT_PHY)
++        geth_select_gpio_state(priv->pinctrl, PINCTRL_STATE_DEFAULT);
++
++    geth_open(ndev);
++
++#if 1 //defined(CONFIG_SUNXI_EPHY)
++    if (!ephy_is_enable()) {
++        pr_info("[geth_resume] ephy is not enable, waiting...\n");
++        msleep(2000);
++        if (!ephy_is_enable()) {
++            netdev_err(ndev, "Wait for ephy resume timeout.\n");
++            return;
++        }
++    }
++#endif
++
++    spin_lock(&priv->lock);
++    netif_device_attach(ndev);
++    spin_unlock(&priv->lock);
++
++}
++
++static void geth_resume(struct device *dev)
++{
++    struct net_device *ndev = dev_get_drvdata(dev);
++    struct geth_priv *priv = netdev_priv(ndev);
++
++    schedule_work(&priv->eth_work);
++}
++
++
++
++static int ucc_geth_suspend(struct platform_device *ofdev, pm_message_t state)
++{
++	struct net_device *ndev = platform_get_drvdata(ofdev);
++    struct geth_priv *priv = netdev_priv(ndev);
++
++    cancel_work_sync(&priv->eth_work);
++
++    if (!ndev || !netif_running(ndev))
++        return 0;
++
++    spin_lock(&priv->lock);
++    netif_device_detach(ndev);
++    spin_unlock(&priv->lock);
++
++    geth_stop(ndev);
++
++    if (priv->phy_ext == EXT_PHY)
++        geth_select_gpio_state(priv->pinctrl, PINCTRL_STATE_SLEEP);
++
++
++	return 0;
++}
++
++static int ucc_geth_resume(struct platform_device *ofdev)
++{
++	struct net_device *ndev = platform_get_drvdata(ofdev);
++    struct geth_priv *priv = netdev_priv(ndev);
++
++    schedule_work(&priv->eth_work);
++
++
++	return 0;
++}
++
++static int geth_freeze(struct device *dev)
++{
++    return 0;
++}
++
++static int geth_restore(struct device *dev)
++{
++    return 0;
++}
++
++static const struct dev_pm_ops geth_pm_ops = {
++    .complete = geth_resume,
++    .prepare = geth_suspend,
++    .suspend = NULL,
++    .resume = NULL,
++    .freeze = geth_freeze,
++    .restore = geth_restore,
++};
++#else
++static const struct dev_pm_ops geth_pm_ops;
++#endif /* CONFIG_PM */
++
++/*#define sunxi_get_soc_chipid(x) {}*/
++static void geth_chip_hwaddr(u8 *addr)
++{
++#define MD5_SIZE 16
++#define CHIP_SIZE 16
++
++    struct crypto_ahash *tfm;
++    struct ahash_request *req;
++    struct scatterlist sg;
++    u8 result[MD5_SIZE];
++    u8 chipid[CHIP_SIZE];
++    int i = 0;
++    int ret = -1;
++
++    memset(chipid, 0, sizeof(chipid));
++    memset(result, 0, sizeof(result));
++
++    sunxi_get_soc_chipid((u8 *)chipid);
++
++    tfm = crypto_alloc_ahash("md5", 0, CRYPTO_ALG_ASYNC);
++    if (IS_ERR(tfm)) {
++        pr_err("Failed to alloc md5\n");
++        return;
++    }
++
++    req = ahash_request_alloc(tfm, GFP_KERNEL);
++    if (!req)
++        goto out;
++
++    ahash_request_set_callback(req, 0, NULL, NULL);
++
++    ret = crypto_ahash_init(req);
++    if (ret) {
++        pr_err("crypto_ahash_init() failed\n");
++        goto out;
++    }
++
++    sg_init_one(&sg, chipid, sizeof(chipid));
++    ahash_request_set_crypt(req, &sg, result, sizeof(chipid));
++    ret = crypto_ahash_update(req);
++    if (ret) {
++        pr_err("crypto_ahash_update() failed for id\n");
++        goto out;
++    }
++
++    ret = crypto_ahash_final(req);
++    if (ret) {
++        pr_err("crypto_ahash_final() failed for result\n");
++        goto out;
++    }
++
++    ahash_request_free(req);
++
++    /* Choose md5 result's [0][2][4][6][8][10] byte as mac address */
++    for (i = 0; i < ETH_ALEN; i++)
++        addr[i] = result[2 * i];
++    addr[0] &= 0xfe; /* clear multicast bit */
++    addr[0] |= 0x02; /* set local assignment bit (IEEE802) */
++
++out:
++    crypto_free_ahash(tfm);
++}
++
++static void geth_check_addr(struct net_device *ndev, unsigned char *mac)
++{
++    int i;
++    char *p = mac;
++    u8 addr[ETH_ALEN];
++
++    if (!is_valid_ether_addr(ndev->dev_addr)) {
++        for (i = 0; i < ETH_ALEN; i++, p++)
++            addr[i] = simple_strtoul(p, &p, 16);
++
++        if (!is_valid_ether_addr(addr))
++            geth_chip_hwaddr(addr);
++
++        if (!is_valid_ether_addr(addr)) {
++            eth_random_addr(addr);
++            pr_warn("%s: Use random mac address\n", ndev->name);
++        }
++    }
++
++    eth_hw_addr_set(ndev, addr);
++}
++
++static void geth_clk_enable(struct geth_priv *priv)
++{
++    int phy_interface = 0;
++    u32 clk_value;
++    u32 efuse_value;
++
++    if (clk_prepare_enable(priv->geth_clk))
++        pr_err("try to enable geth_clk failed!\n");
++
++    if (((priv->phy_ext == INT_PHY) || g_use_ephy_clk) && !IS_ERR_OR_NULL(priv->ephy_clk)) {
++        if (clk_prepare_enable(priv->ephy_clk))
++            pr_err("try to enable ephy_clk failed!\n");
++    }
++
++    phy_interface = priv->phy_interface;
++
++    clk_value = readl(priv->base_phy);
++    if (phy_interface == PHY_INTERFACE_MODE_RGMII)
++        clk_value |= 0x00000004;
++    else
++        clk_value &= (~0x00000004);
++
++    clk_value &= (~0x00002003);
++    if (phy_interface == PHY_INTERFACE_MODE_RGMII || phy_interface == PHY_INTERFACE_MODE_GMII)
++        clk_value |= 0x00000002;
++    else if (phy_interface == PHY_INTERFACE_MODE_RMII)
++        clk_value |= 0x00002001;
++
++    if (priv->phy_ext == INT_PHY) {
++//         if (0 != sunxi_efuse_read(EFUSE_OEM_NAME, &efuse_value))
++//             pr_err("get PHY efuse fail!\n");
++//         else
++// #if defined(CONFIG_ARCH_SUN50IW2)
++//             clk_value |= (((efuse_value >> 24) & 0x0F) + 3) << 28;
++// #else
++//             pr_warn("miss config come from efuse!\n");
++// #endif
++    }
++
++    /* Adjust Tx/Rx clock delay */
++    clk_value &= ~(0x07 << 10);
++    clk_value |= ((tx_delay & 0x07) << 10);
++    clk_value &= ~(0x1F << 5);
++    clk_value |= ((rx_delay & 0x1F) << 5);
++
++    writel(clk_value, priv->base_phy);
++}
++
++static void geth_clk_disable(struct geth_priv *priv)
++{
++    if (((priv->phy_ext == INT_PHY) || g_use_ephy_clk) && !IS_ERR_OR_NULL(priv->ephy_clk))
++        clk_disable_unprepare(priv->ephy_clk);
++
++    clk_disable_unprepare(priv->geth_clk);
++}
++
++static void geth_tx_err(struct geth_priv *priv)
++{
++    netif_stop_queue(priv->ndev);
++
++    sunxi_stop_tx(priv->base);
++
++    geth_free_tx_sk(priv);
++    memset(priv->dma_tx, 0, dma_desc_tx * sizeof(struct dma_desc));
++    desc_init_chain(priv->dma_tx, (unsigned long)priv->dma_tx_phy, dma_desc_tx);
++    priv->tx_dirty = 0;
++    priv->tx_clean = 0;
++    sunxi_start_tx(priv->base, priv->dma_tx_phy);
++
++    priv->ndev->stats.tx_errors++;
++    netif_wake_queue(priv->ndev);
++}
++
++static inline void geth_schedule(struct geth_priv *priv)
++{
++    if (likely(napi_schedule_prep(&priv->napi))) {
++        sunxi_int_disable(priv->base);
++        __napi_schedule(&priv->napi);
++    }
++}
++
++static irqreturn_t geth_interrupt(int irq, void *dev_id)
++{
++    struct net_device *ndev = (struct net_device *)dev_id;
++    struct geth_priv *priv = netdev_priv(ndev);
++    int status;
++
++    if (unlikely(!ndev)) {
++        pr_err("%s: invalid ndev pointer\n", __func__);
++        return IRQ_NONE;
++    }
++
++    status = sunxi_int_status(priv->base, (void *)(&priv->xstats));
++
++    if (likely(status == handle_tx_rx))
++        geth_schedule(priv);
++    else if (unlikely(status == tx_hard_error_bump_tc))
++        netdev_info(ndev, "Do nothing for bump tc\n");
++    else if (unlikely(status == tx_hard_error))
++        geth_tx_err(priv);
++    else
++        netdev_info(ndev, "Do nothing.....\n");
++
++    return IRQ_HANDLED;
++}
++
++static int geth_open(struct net_device *ndev)
++{
++    struct geth_priv *priv = netdev_priv(ndev);
++    int ret = 0;
++
++    ret = geth_dma_desc_init(ndev);
++    if (ret) {
++        ret = -EINVAL;
++        return ret;
++    }
++
++    ret = geth_power_on(priv);
++    if (ret) {
++        netdev_err(ndev, "Power on is failed\n");
++        ret = -EINVAL;
++        goto power_err;
++    }
++
++    geth_clk_enable(priv);
++
++    ret = geth_phy_init(ndev);
++    if (ret) {
++        netdev_err(ndev, "phy init again...\n");
++        ret = geth_phy_init(ndev);
++        if (ret) {
++            netdev_err(ndev, "phy init failed\n");
++            ret = -EINVAL;
++            goto phy_err;
++        }
++    }
++
++    ret = sunxi_mac_reset((void *)priv->base, &sunxi_udelay, 10000);
++    if (ret) {
++        netdev_err(ndev, "Initialize hardware error\n");
++        goto mac_err;
++    }
++
++    sunxi_mac_init(priv->base, txmode, rxmode);
++    sunxi_set_umac(priv->base, ndev->dev_addr, 0);
++
++    memset(priv->dma_tx, 0, dma_desc_tx * sizeof(struct dma_desc));
++    memset(priv->dma_rx, 0, dma_desc_rx * sizeof(struct dma_desc));
++
++    desc_init_chain(priv->dma_rx, (unsigned long)priv->dma_rx_phy, dma_desc_rx);
++    desc_init_chain(priv->dma_tx, (unsigned long)priv->dma_tx_phy, dma_desc_tx);
++
++    priv->rx_clean = 0;
++    priv->rx_dirty = 0;
++    priv->tx_clean = 0;
++    priv->tx_dirty = 0;
++    geth_rx_refill(ndev);
++
++    /* Extra statistics */
++    memset(&priv->xstats, 0, sizeof(struct geth_extra_stats));
++
++    if (ndev->phydev)
++        phy_start(ndev->phydev);
++
++    sunxi_start_rx(priv->base, (unsigned long)((struct dma_desc *)priv->dma_rx_phy + priv->rx_dirty));
++    sunxi_start_tx(priv->base, (unsigned long)((struct dma_desc *)priv->dma_tx_phy + priv->tx_clean));
++
++    /* Enable the Rx/Tx */
++    sunxi_mac_enable(priv->base);
++
++    netif_carrier_on(ndev);
++
++    napi_enable(&priv->napi);
++    netif_start_queue(ndev);
++
++    return 0;
++
++mac_err:
++    geth_phy_release(ndev);
++phy_err:
++    geth_clk_disable(priv);
++
++    geth_power_off(priv);
++
++power_err:
++    geth_free_dma_desc(priv);
++
++    return ret;
++}
++
++static int geth_stop(struct net_device *ndev)
++{
++    struct geth_priv *priv = netdev_priv(ndev);
++
++    netif_stop_queue(ndev);
++    napi_disable(&priv->napi);
++
++    netif_carrier_off(ndev);
++
++    /* Release PHY resources */
++    geth_phy_release(ndev);
++
++    /* Disable Rx/Tx */
++    sunxi_mac_disable(priv->base);
++
++    geth_clk_disable(priv);
++    geth_power_off(priv);
++
++    netif_tx_lock_bh(ndev);
++    /* Release the DMA TX/RX socket buffers */
++    geth_free_rx_sk(priv);
++    geth_free_tx_sk(priv);
++    netif_tx_unlock_bh(ndev);
++
++    /* Ensure that hareware have been stopped */
++    geth_free_dma_desc(priv);
++
++    return 0;
++}
++
++static void geth_tx_complete(struct geth_priv *priv)
++{
++    unsigned int entry = 0;
++    struct sk_buff *skb = NULL;
++    struct dma_desc *desc = NULL;
++    int tx_stat;
++
++    spin_lock(&priv->tx_lock);
++    while (circ_cnt(priv->tx_dirty, priv->tx_clean, dma_desc_tx) > 0) {
++        entry = priv->tx_clean;
++        desc = priv->dma_tx + entry;
++
++        /* Check if the descriptor is owned by the DMA. */
++        if (desc_get_own(desc))
++            break;
++
++        /* Verify tx error by looking at the last segment */
++        if (desc_get_tx_ls(desc)) {
++            tx_stat = desc_get_tx_status(desc, (void *)(&priv->xstats));
++
++            if (likely(!tx_stat))
++                priv->ndev->stats.tx_packets++;
++            else
++                priv->ndev->stats.tx_errors++;
++        }
++
++        dma_unmap_single(priv->dev, (u32)desc_buf_get_addr(desc), desc_buf_get_len(desc), DMA_TO_DEVICE);
++
++        skb = priv->tx_sk[entry];
++        priv->tx_sk[entry] = NULL;
++        desc_init(desc);
++
++        /* Find next dirty desc */
++        priv->tx_clean = circ_inc(entry, dma_desc_tx);
++
++        if (unlikely(skb == NULL))
++            continue;
++
++        dev_kfree_skb(skb);
++    }
++
++    if (unlikely(netif_queue_stopped(priv->ndev)) && circ_space(priv->tx_dirty, priv->tx_clean, dma_desc_tx) > TX_THRESH) {
++        netif_wake_queue(priv->ndev);
++    }
++    spin_unlock(&priv->tx_lock);
++}
++
++static netdev_tx_t geth_xmit(struct sk_buff *skb, struct net_device *ndev)
++{
++    struct geth_priv  *priv = netdev_priv(ndev);
++    unsigned int entry;
++    struct dma_desc *desc, *first;
++    unsigned int len, tmp_len = 0;
++    int i, csum_insert;
++    int nfrags = skb_shinfo(skb)->nr_frags;
++    dma_addr_t paddr;
++
++    spin_lock(&priv->tx_lock);
++    if (unlikely(circ_space(priv->tx_dirty, priv->tx_clean, dma_desc_tx) < (nfrags + 1))) {
++        if (!netif_queue_stopped(ndev)) {
++            netdev_err(ndev, "%s: BUG! Tx Ring full when queue awake\n", __func__);
++            netif_stop_queue(ndev);
++        }
++        spin_unlock(&priv->tx_lock);
++
++        return NETDEV_TX_BUSY;
++    }
++
++    csum_insert = (skb->ip_summed == CHECKSUM_PARTIAL);
++    entry = priv->tx_dirty;
++    first = priv->dma_tx + entry;
++    desc = priv->dma_tx + entry;
++
++    len = skb_headlen(skb);
++    priv->tx_sk[entry] = skb;
++
++#ifdef PKT_DEBUG
++    printk("======TX PKT DATA: ============\n");
++    /* dump the packet */
++    print_hex_dump(KERN_DEBUG, "skb->data: ", DUMP_PREFIX_NONE,
++                   16, 1, skb->data, 64, true);
++#endif
++
++    /* Every desc max size is 2K */
++    while (len != 0) {
++        desc = priv->dma_tx + entry;
++        tmp_len = ((len > MAX_BUF_SZ) ? MAX_BUF_SZ : len);
++
++        paddr = dma_map_single(priv->dev, skb->data, tmp_len, DMA_TO_DEVICE);
++        if (dma_mapping_error(priv->dev, paddr)) {
++            dev_kfree_skb(skb);
++            return -EIO;
++        }
++        desc_buf_set(desc, paddr, tmp_len);
++        /* Don't set the first's own bit, here */
++        if (first != desc) {
++            priv->tx_sk[entry] = NULL;
++            desc_set_own(desc);
++        }
++
++        entry = circ_inc(entry, dma_desc_tx);
++        len -= tmp_len;
++    }
++
++    for (i = 0; i < nfrags; i++) {
++        const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
++
++        len = skb_frag_size(frag);
++        desc = priv->dma_tx + entry;
++        paddr = skb_frag_dma_map(priv->dev, frag, 0, len, DMA_TO_DEVICE);
++        if (dma_mapping_error(priv->dev, paddr)) {
++            dev_kfree_skb(skb);
++            return -EIO;
++        }
++
++        desc_buf_set(desc, paddr, len);
++        desc_set_own(desc);
++        priv->tx_sk[entry] = NULL;
++        entry = circ_inc(entry, dma_desc_tx);
++    }
++
++    ndev->stats.tx_bytes += skb->len;
++    priv->tx_dirty = entry;
++    desc_tx_close(first, desc, csum_insert);
++
++    desc_set_own(first);
++    spin_unlock(&priv->tx_lock);
++
++    if (circ_space(priv->tx_dirty, priv->tx_clean, dma_desc_tx) <= (MAX_SKB_FRAGS + 1)) {
++        netif_stop_queue(ndev);
++        if (circ_space(priv->tx_dirty, priv->tx_clean, dma_desc_tx) > TX_THRESH)
++            netif_wake_queue(ndev);
++    }
++
++#ifdef DEBUG
++    printk("=======TX Descriptor DMA: 0x%08llx\n", priv->dma_tx_phy);
++    printk("Tx pointor: dirty: %d, clean: %d\n", priv->tx_dirty, priv->tx_clean);
++    desc_print(priv->dma_tx, dma_desc_tx);
++#endif
++    sunxi_tx_poll(priv->base);
++    geth_tx_complete(priv);
++
++    return NETDEV_TX_OK;
++}
++
++static int geth_rx(struct geth_priv *priv, int limit)
++{
++    unsigned int rxcount = 0;
++    unsigned int entry;
++    struct dma_desc *desc;
++    struct sk_buff *skb;
++    int status;
++    int frame_len;
++
++    while (rxcount < limit) {
++        entry = priv->rx_dirty;
++        desc = priv->dma_rx + entry;
++
++        if (desc_get_own(desc))
++            break;
++
++        rxcount++;
++        priv->rx_dirty = circ_inc(priv->rx_dirty, dma_desc_rx);
++
++        /* Get length & status from hardware */
++        frame_len = desc_rx_frame_len(desc);
++        status = desc_get_rx_status(desc, (void *)(&priv->xstats));
++
++        netdev_dbg(priv->ndev, "Rx frame size %d, status: %d\n", frame_len, status);
++
++        skb = priv->rx_sk[entry];
++        if (unlikely(!skb)) {
++            netdev_err(priv->ndev, "Skb is null\n");
++            priv->ndev->stats.rx_dropped++;
++            break;
++        }
++
++#ifdef PKT_DEBUG
++        printk("======RX PKT DATA: ============\n");
++        /* dump the packet */
++        print_hex_dump(KERN_DEBUG, "skb->data: ", DUMP_PREFIX_NONE,
++                       16, 1, skb->data, 64, true);
++#endif
++
++        if (status == discard_frame) {
++            netdev_dbg(priv->ndev, "Get error pkt\n");
++            priv->ndev->stats.rx_errors++;
++            continue;
++        }
++
++        if (unlikely(status != llc_snap))
++            frame_len -= ETH_FCS_LEN;
++
++        priv->rx_sk[entry] = NULL;
++
++        skb_put(skb, frame_len);
++        dma_unmap_single(priv->dev, (u32)desc_buf_get_addr(desc), desc_buf_get_len(desc), DMA_FROM_DEVICE);
++
++        skb->protocol = eth_type_trans(skb, priv->ndev);
++
++        skb->ip_summed = CHECKSUM_UNNECESSARY;
++        napi_gro_receive(&priv->napi, skb);
++
++        priv->ndev->stats.rx_packets++;
++        priv->ndev->stats.rx_bytes += frame_len;
++    }
++
++#ifdef DEBUG
++    if (rxcount > 0) {
++        printk("======RX Descriptor DMA: 0x%08llx=\n", priv->dma_rx_phy);
++        printk("RX pointor: dirty: %d, clean: %d\n", priv->rx_dirty, priv->rx_clean);
++        desc_print(priv->dma_rx, dma_desc_rx);
++    }
++#endif
++    geth_rx_refill(priv->ndev);
++
++    return rxcount;
++}
++
++static int geth_poll(struct napi_struct *napi, int budget)
++{
++    struct geth_priv *priv = container_of(napi, struct geth_priv, napi);
++    int work_done = 0;
++
++    geth_tx_complete(priv);
++    work_done = geth_rx(priv, budget);
++
++    if (work_done < budget) {
++        napi_complete(napi);
++        sunxi_int_enable(priv->base);
++    }
++
++    return work_done;
++}
++
++static int geth_change_mtu(struct net_device *ndev, int new_mtu)
++{
++    int max_mtu;
++
++    if (netif_running(ndev)) {
++        pr_err("%s: must be stopped to change its MTU\n", ndev->name);
++        return -EBUSY;
++    }
++
++    max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN);
++
++    if ((new_mtu < 46) || (new_mtu > max_mtu)) {
++        pr_err("%s: invalid MTU, max MTU is: %d\n", ndev->name, max_mtu);
++        return -EINVAL;
++    }
++
++    ndev->mtu = new_mtu;
++    netdev_update_features(ndev);
++
++    return 0;
++}
++
++static netdev_features_t geth_fix_features(struct net_device *ndev, netdev_features_t features)
++{
++    return features;
++}
++
++static void geth_set_rx_mode(struct net_device *ndev)
++{
++    struct geth_priv *priv = netdev_priv(ndev);
++    unsigned int value = 0;
++
++    pr_debug("%s: # mcasts %d, # unicast %d\n",
++             __func__, netdev_mc_count(ndev), netdev_uc_count(ndev));
++
++    spin_lock(&priv->lock);
++    if (ndev->flags & IFF_PROMISC) {
++        value = GETH_FRAME_FILTER_PR;
++    } else if ((netdev_mc_count(ndev) > HASH_TABLE_SIZE) ||
++               (ndev->flags & IFF_ALLMULTI)) {
++        value = GETH_FRAME_FILTER_PM; /* pass all multi */
++        sunxi_hash_filter(priv->base, ~0UL, ~0UL);
++    } else if (!netdev_mc_empty(ndev)) {
++        u32 mc_filter[2];
++        struct netdev_hw_addr *ha;
++
++        /* Hash filter for multicast */
++        value = GETH_FRAME_FILTER_HMC;
++
++        memset(mc_filter, 0, sizeof(mc_filter));
++        netdev_for_each_mc_addr(ha, ndev) {
++            /* The upper 6 bits of the calculated CRC are used to
++             *  index the contens of the hash table
++             */
++            int bit_nr = bitrev32(~crc32_le(~0, ha->addr, 6)) >> 26;
++            /* The most significant bit determines the register to
++             * use (H/L) while the other 5 bits determine the bit
++             * within the register.
++             */
++            mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
++        }
++        sunxi_hash_filter(priv->base, mc_filter[0], mc_filter[1]);
++    }
++
++    /* Handle multiple unicast addresses (perfect filtering)*/
++    if (netdev_uc_count(ndev) > 16) {
++        /* Switch to promiscuous mode is more than 8 addrs are required */
++        value |= GETH_FRAME_FILTER_PR;
++    } else {
++        int reg = 1;
++        struct netdev_hw_addr *ha;
++
++        netdev_for_each_uc_addr(ha, ndev) {
++            sunxi_set_umac(priv->base, ha->addr, reg);
++            reg++;
++        }
++    }
++
++#ifdef FRAME_FILTER_DEBUG
++    /* Enable Receive all mode (to debug filtering_fail errors) */
++    value |= GETH_FRAME_FILTER_RA;
++#endif
++    sunxi_set_filter(priv->base, value);
++    spin_unlock(&priv->lock);
++}
++
++static void geth_tx_timeout(struct net_device *ndev, unsigned int txqueue)
++{
++    struct geth_priv *priv = netdev_priv(ndev);
++
++    geth_tx_err(priv);
++}
++
++static int geth_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
++{
++    if (!netif_running(ndev))
++        return -EINVAL;
++
++    if (!ndev->phydev)
++        return -EINVAL;
++
++    return phy_mii_ioctl(ndev->phydev, rq, cmd);
++}
++
++/* Configuration changes (passed on by ifconfig) */
++static int geth_config(struct net_device *ndev, struct ifmap *map)
++{
++    if (ndev->flags & IFF_UP) /* can't act on a running interface */
++        return -EBUSY;
++
++    /* Don't allow changing the I/O address */
++    if (map->base_addr != ndev->base_addr) {
++        pr_warn("%s: can't change I/O address\n", ndev->name);
++        return -EOPNOTSUPP;
++    }
++
++    /* Don't allow changing the IRQ */
++    if (map->irq != ndev->irq) {
++        pr_warn("%s: can't change IRQ number %d\n", ndev->name, ndev->irq);
++        return -EOPNOTSUPP;
++    }
++
++    return 0;
++}
++
++static int geth_set_mac_address(struct net_device *ndev, void *p)
++{
++    struct geth_priv *priv = netdev_priv(ndev);
++    struct sockaddr *addr = p;
++
++    if (!is_valid_ether_addr(addr->sa_data))
++        return -EADDRNOTAVAIL;
++
++	eth_hw_addr_set(ndev, addr->sa_data);
++
++    sunxi_set_umac(priv->base, ndev->dev_addr, 0);
++
++    return 0;
++}
++
++int geth_set_features(struct net_device *ndev, netdev_features_t features)
++{
++    struct geth_priv *priv = netdev_priv(ndev);
++
++    if (features & NETIF_F_LOOPBACK && netif_running(ndev))
++        sunxi_mac_loopback(priv->base, 1);
++    else
++        sunxi_mac_loopback(priv->base, 0);
++
++    return 0;
++}
++
++#ifdef CONFIG_NET_POLL_CONTROLLER
++/* Polling receive - used by NETCONSOLE and other diagnostic tools
++ * to allow network I/O with interrupts disabled.
++ */
++static void geth_poll_controller(struct net_device *dev)
++{
++    disable_irq(dev->irq);
++    geth_interrupt(dev->irq, dev);
++    enable_irq(dev->irq);
++}
++#endif
++
++static const struct net_device_ops geth_netdev_ops = {
++    .ndo_init = NULL,
++    .ndo_open = geth_open,
++    .ndo_start_xmit = geth_xmit,
++    .ndo_stop = geth_stop,
++    .ndo_change_mtu = geth_change_mtu,
++    .ndo_fix_features = geth_fix_features,
++    .ndo_set_rx_mode = geth_set_rx_mode,
++    .ndo_tx_timeout = geth_tx_timeout,
++    .ndo_do_ioctl = geth_ioctl,
++    .ndo_set_config = geth_config,
++#ifdef CONFIG_NET_POLL_CONTROLLER
++    .ndo_poll_controller = geth_poll_controller,
++#endif
++    .ndo_set_mac_address = geth_set_mac_address,
++    .ndo_set_features = geth_set_features,
++};
++
++static int geth_check_if_running(struct net_device *ndev)
++{
++    if (!netif_running(ndev))
++        return -EBUSY;
++    return 0;
++}
++
++static int geth_get_sset_count(struct net_device *netdev, int sset)
++{
++    int len;
++
++    switch (sset) {
++    case ETH_SS_STATS:
++        len = 0;
++        return len;
++    default:
++        return -EOPNOTSUPP;
++    }
++}
++
++#if 0
++static int geth_ethtool_getsettings(struct net_device *ndev,
++                    struct ethtool_cmd *cmd)
++{
++    struct geth_priv *priv = netdev_priv(ndev);
++    struct phy_device *phy = ndev->phydev;
++    int rc;
++
++    if (phy == NULL) {
++        netdev_err(ndev, "%s: %s: PHY is not registered\n",
++               __func__, ndev->name);
++        return -ENODEV;
++    }
++
++    if (!netif_running(ndev)) {
++        pr_err("%s: interface is disabled: we cannot track "
++               "link speed / duplex setting\n", ndev->name);
++        return -EBUSY;
++    }
++
++    cmd->transceiver = XCVR_INTERNAL;
++    spin_lock_irq(&priv->lock);
++    rc = phy_ethtool_gset(phy, cmd);
++    spin_unlock_irq(&priv->lock);
++
++    return rc;
++}
++
++static int geth_ethtool_setsettings(struct net_device *ndev,
++                    struct ethtool_cmd *cmd)
++{
++    struct geth_priv *priv = netdev_priv(ndev);
++    struct phy_device *phy = ndev->phydev;
++    int rc;
++
++    spin_lock(&priv->lock);
++    rc = phy_ethtool_sset(phy, cmd);
++    spin_unlock(&priv->lock);
++
++    return rc;
++}
++#endif
++
++static void geth_ethtool_getdrvinfo(struct net_device *ndev,
++                                    struct ethtool_drvinfo *info)
++{
++    strscpy(info->driver, "sunxi_geth", sizeof(info->driver));
++
++#define DRV_MODULE_VERSION "SUNXI Gbgit driver V1.1"
++
++    strcpy(info->version, DRV_MODULE_VERSION);
++    info->fw_version[0] = '\0';
++}
++
++static const struct ethtool_ops geth_ethtool_ops = {
++    .begin = geth_check_if_running,
++    // .get_settings = geth_ethtool_getsettings,
++    // .set_settings = geth_ethtool_setsettings,
++    .get_link_ksettings = phy_ethtool_get_link_ksettings,
++    .set_link_ksettings = phy_ethtool_set_link_ksettings,
++    .get_link = ethtool_op_get_link,
++    .get_pauseparam = NULL,
++    .set_pauseparam = NULL,
++    .get_ethtool_stats = NULL,
++    .get_strings = NULL,
++    .get_wol = NULL,
++    .set_wol = NULL,
++    .get_sset_count = geth_get_sset_count,
++    .get_drvinfo = geth_ethtool_getdrvinfo,
++};
++
++struct gpio_config {
++	u32	gpio;
++	u32	mul_sel;
++	u32	pull;
++	u32	drv_level;
++	u32	data;
++};
++
++/* config hardware resource */
++static int geth_hw_init(struct platform_device *pdev)
++{
++    struct net_device *ndev = platform_get_drvdata(pdev);
++    struct geth_priv *priv = netdev_priv(ndev);
++    struct device_node *np = pdev->dev.of_node;
++    int ret = 0;
++    struct resource *res;
++    u32 value;
++    struct gpio_config cfg;
++    const char *gmac_power;
++    char power[20];
++    int i;
++
++// #ifdef CONFIG_SUNXI_EXT_PHY
++    priv->phy_ext = EXT_PHY;
++// #else
++//     priv->phy_ext = INT_PHY;
++// #endif
++
++    /* config memery resource */
++    res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++    if (unlikely(!res)) {
++        pr_err("%s: ERROR: get gmac memory failed", __func__);
++        return -ENODEV;
++    }
++
++    priv->base = devm_ioremap_resource(&pdev->dev, res);
++    if (!priv->base) {
++        pr_err("%s: ERROR: gmac memory mapping failed", __func__);
++        return -ENOMEM;
++    }
++
++    res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
++    if (unlikely(!res)) {
++        pr_err("%s: ERROR: get phy memory failed", __func__);
++        ret = -ENODEV;
++        goto mem_err;
++    }
++
++    priv->base_phy = devm_ioremap_resource(&pdev->dev, res);
++    if (unlikely(!priv->base_phy)) {
++        pr_err("%s: ERROR: phy memory mapping failed", __func__);
++        ret = -ENOMEM;
++        goto mem_err;
++    }
++
++    /* config IRQ */
++    ndev->irq = platform_get_irq_byname(pdev, "gmacirq");
++    if (ndev->irq == -ENXIO) {
++        pr_err("%s: ERROR: MAC IRQ not found\n", __func__);
++        ret = -ENXIO;
++        goto irq_err;
++    }
++
++    ret = request_irq(ndev->irq, geth_interrupt, IRQF_SHARED, dev_name(&pdev->dev), ndev);
++    if (unlikely(ret < 0)) {
++        pr_err("Could not request irq %d, error: %d\n", ndev->irq, ret);
++        goto irq_err;
++    }
++
++    /* config clock */
++    priv->geth_clk = of_clk_get_by_name(np, "bus-emac1");
++    if (unlikely(!priv->geth_clk || IS_ERR(priv->geth_clk))) {
++        pr_err("Get gmac clock failed!\n");
++        ret = -EINVAL;
++        goto clk_err;
++    }
++
++    if (INT_PHY == priv->phy_ext) {
++        priv->ephy_clk = of_clk_get_by_name(np, "emac-25m");
++        if (unlikely(IS_ERR_OR_NULL(priv->ephy_clk))) {
++            pr_err("Get ephy clock failed!\n");
++            ret = -EINVAL;
++            goto clk_err;
++        }
++    }
++#if 1 // defined(CONFIG_ARCH_SUN8IW12) || defined(CONFIG_ARCH_SUN50IW9)
++    else {
++        if (!of_property_read_u32(np, "use_ephy25m", &g_use_ephy_clk)
++                && g_use_ephy_clk) {
++            priv->ephy_clk = of_clk_get_by_name(np, "ephy");
++            if (unlikely(IS_ERR_OR_NULL(priv->ephy_clk))) {
++                pr_err("Get ephy clk failed!\n");
++                ret = -EINVAL;
++                goto clk_err;
++            }
++        }
++    }
++#endif
++
++    /* config power regulator */
++    if (EXT_PHY == priv->phy_ext) {
++        for (i = 0; i < POWER_CHAN_NUM; i++) {
++            snprintf(power, 15, "gmac-power%d", i);
++            ret = of_property_read_string(np, power, &gmac_power);
++            if (ret) {
++                priv->gmac_power[i] = NULL;
++                pr_info("gmac-power%d: NULL\n", i);
++                continue;
++            }
++            priv->gmac_power[i] = regulator_get(NULL, gmac_power);
++            if (IS_ERR(priv->gmac_power[i])) {
++                pr_err("gmac-power%d get error!\n", i);
++                ret = -EINVAL;
++                goto clk_err;
++            }
++        }
++    }
++
++    // /* config other parameters */
++    // priv->phy_interface = of_get_phy_mode(np);
++    // if (priv->phy_interface != PHY_INTERFACE_MODE_MII &&
++    //     priv->phy_interface != PHY_INTERFACE_MODE_RGMII &&
++    //     priv->phy_interface != PHY_INTERFACE_MODE_RMII) {
++    //     pr_err("Not support phy type!\n");
++    //     priv->phy_interface = PHY_INTERFACE_MODE_MII;
++    // }
++
++    priv->phy_interface = PHY_INTERFACE_MODE_RMII;
++
++    if (!of_property_read_u32(np, "tx-delay", &value))
++        tx_delay = value;
++
++    if (!of_property_read_u32(np, "rx-delay", &value))
++        rx_delay = value;
++
++    /* config pinctrl */
++    if (EXT_PHY == priv->phy_ext) {
++        priv->phyrst = of_get_named_gpio_flags(np, "phy-rst", 0, (enum of_gpio_flags *)&cfg);
++        priv->rst_active_low = (cfg.data == OF_GPIO_ACTIVE_LOW) ? 1 : 0;
++
++        if (gpio_is_valid(priv->phyrst)) {
++            if (gpio_request(priv->phyrst, "phy-rst") < 0) {
++                pr_err("gmac gpio request fail!\n");
++                ret = -EINVAL;
++                goto pin_err;
++            }
++        }
++
++        priv->pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
++        if (IS_ERR_OR_NULL(priv->pinctrl)) {
++            pr_err("gmac pinctrl error!\n");
++            priv->pinctrl = NULL;
++            ret = -EINVAL;
++            goto pin_err;
++        }
++    }
++
++    priv->ephy_rst = devm_reset_control_get_optional(&pdev->dev, "stmmaceth");
++    reset_control_assert(priv->ephy_rst);
++    reset_control_deassert(priv->ephy_rst);
++
++    msleep(800);
++
++    return 0;
++
++pin_err:
++    if (EXT_PHY == priv->phy_ext) {
++        for (i = 0; i < POWER_CHAN_NUM; i++) {
++            if (IS_ERR_OR_NULL(priv->gmac_power[i]))
++                continue;
++            regulator_put(priv->gmac_power[i]);
++        }
++    }
++clk_err:
++    free_irq(ndev->irq, ndev);
++irq_err:
++    devm_iounmap(&pdev->dev, priv->base_phy);
++mem_err:
++    devm_iounmap(&pdev->dev, priv->base);
++
++    return ret;
++}
++
++static void geth_hw_release(struct platform_device *pdev)
++{
++    struct net_device *ndev = platform_get_drvdata(pdev);
++    struct geth_priv *priv = netdev_priv(ndev);
++    int i;
++
++    devm_iounmap(&pdev->dev, (priv->base_phy));
++    devm_iounmap(&pdev->dev, priv->base);
++    free_irq(ndev->irq, ndev);
++    if (priv->geth_clk)
++        clk_put(priv->geth_clk);
++
++    if (EXT_PHY == priv->phy_ext) {
++        for (i = 0; i < POWER_CHAN_NUM; i++) {
++            if (IS_ERR_OR_NULL(priv->gmac_power[i]))
++                continue;
++            regulator_put(priv->gmac_power[i]);
++        }
++
++        if (!IS_ERR_OR_NULL(priv->pinctrl))
++            devm_pinctrl_put(priv->pinctrl);
++
++        if (gpio_is_valid(priv->phyrst))
++            gpio_free(priv->phyrst);
++    }
++
++    if (!IS_ERR_OR_NULL(priv->ephy_clk))
++        clk_put(priv->ephy_clk);
++}
++
++/**
++ * geth_probe
++ * @pdev: platform device pointer
++ * Description: the driver is initialized through platform_device.
++ */
++static int geth_probe(struct platform_device *pdev)
++{
++    int ret = 0;
++    struct net_device *ndev = NULL;
++    struct geth_priv *priv;
++
++#ifdef CONFIG_OF
++    pdev->dev.dma_mask = &geth_dma_mask;
++    pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
++#endif
++
++    ndev = alloc_etherdev(sizeof(struct geth_priv));
++    if (!ndev) {
++        dev_err(&pdev->dev, "could not allocate device.\n");
++        return -ENOMEM;
++    }
++    SET_NETDEV_DEV(ndev, &pdev->dev);
++
++    priv = netdev_priv(ndev);
++    platform_set_drvdata(pdev, ndev);
++
++    /* Must set private data to pdev, before call it */
++    ret = geth_hw_init(pdev);
++    if (0 != ret) {
++        pr_err("geth_hw_init fail!\n");
++        goto hw_err;
++    }
++
++    /* setup the netdevice, fill the field of netdevice */
++    ether_setup(ndev);
++    ndev->netdev_ops = &geth_netdev_ops;
++    netdev_set_default_ethtool_ops(ndev, &geth_ethtool_ops);
++    ndev->base_addr = (unsigned long)priv->base;
++
++    priv->ndev = ndev;
++    priv->dev = &pdev->dev;
++
++    /* TODO: support the VLAN frames */
++    ndev->hw_features = NETIF_F_SG | NETIF_F_HIGHDMA | NETIF_F_IP_CSUM |
++                        NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM;
++
++    ndev->features |= ndev->hw_features;
++    ndev->hw_features |= NETIF_F_LOOPBACK;
++    ndev->priv_flags |= IFF_UNICAST_FLT;
++
++    ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
++
++    netif_napi_add(ndev, &priv->napi, geth_poll);
++
++    spin_lock_init(&priv->lock);
++    spin_lock_init(&priv->tx_lock);
++
++    /* The last val is mdc clock ratio */
++    sunxi_geth_register((void *)ndev->base_addr, HW_VERSION, 0x03);
++
++    ret = register_netdev(ndev);
++    if (ret) {
++        netif_napi_del(&priv->napi);
++        pr_err("Error: Register %s failed\n", ndev->name);
++        goto reg_err;
++    }
++
++    /* Before open the device, the mac address should be set */
++    geth_check_addr(ndev, mac_str);
++
++#ifdef CONFIG_GETH_ATTRS
++    geth_create_attrs(ndev);
++#endif
++    device_create_file(&pdev->dev, &dev_attr_gphy_test);
++    device_create_file(&pdev->dev, &dev_attr_mii_read);
++    device_create_file(&pdev->dev, &dev_attr_mii_write);
++
++    device_enable_async_suspend(&pdev->dev);
++
++#ifdef CONFIG_PM
++    INIT_WORK(&priv->eth_work, geth_resume_work);
++#endif
++
++    return 0;
++
++reg_err:
++    geth_hw_release(pdev);
++hw_err:
++    platform_set_drvdata(pdev, NULL);
++    free_netdev(ndev);
++
++    return ret;
++}
++
++static void geth_remove(struct platform_device *pdev)
++{
++    struct net_device *ndev = platform_get_drvdata(pdev);
++    struct geth_priv *priv = netdev_priv(ndev);
++
++    device_remove_file(&pdev->dev, &dev_attr_gphy_test);
++    device_remove_file(&pdev->dev, &dev_attr_mii_read);
++    device_remove_file(&pdev->dev, &dev_attr_mii_write);
++
++    netif_napi_del(&priv->napi);
++    unregister_netdev(ndev);
++    geth_hw_release(pdev);
++    platform_set_drvdata(pdev, NULL);
++    free_netdev(ndev);
++}
++
++static const struct of_device_id geth_of_match[] = {
++    {.compatible = "allwinner,sunxi-gmac",},
++    {},
++};
++MODULE_DEVICE_TABLE(of, geth_of_match);
++
++static struct platform_driver geth_driver = {
++    .probe = geth_probe,
++    .remove = geth_remove,
++	.suspend	= ucc_geth_suspend,
++	.resume		= ucc_geth_resume,
++    .driver = {
++        .name = "sunxi-gmac",
++        .owner = THIS_MODULE,
++        .pm = &geth_pm_ops,
++        .of_match_table = geth_of_match,
++    },
++};
++module_platform_driver(geth_driver);
++
++#ifndef MODULE
++static int __init set_mac_addr(char *str)
++{
++    char *p = str;
++
++    if (str && strlen(str))
++        memcpy(mac_str, p, 18);
++
++    return 0;
++}
++__setup("mac_addr=", set_mac_addr);
++#endif
++
++MODULE_DESCRIPTION("Allwinner Gigabit Ethernet driver");
++MODULE_AUTHOR("fuzhaoke <fuzhaoke@allwinnertech.com>");
++MODULE_LICENSE("Dual BSD/GPL");
+diff --git a/drivers/net/ethernet/allwinner/sunxi-gmac.h b/drivers/net/ethernet/allwinner/sunxi-gmac.h
+new file mode 100644
+index 000000000000..0ba8977d28f4
+--- /dev/null
++++ b/drivers/net/ethernet/allwinner/sunxi-gmac.h
+@@ -0,0 +1,270 @@
++/*
++ * linux/drivers/net/ethernet/allwinner/sunxi_gmac.h
++ *
++ * Copyright © 2016-2018, fuzhaoke
++ *		Author: fuzhaoke <fuzhaoke@allwinnertech.com>
++ *
++ * This file is provided under a dual BSD/GPL license.  When using or
++ * redistributing this file, you may do so under either license.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
++ * GNU General Public License for more details.
++ */
++#ifndef __SUNXI_GETH_H__
++#define __SUNXI_GETH_H__
++
++#include <linux/etherdevice.h>
++#include <linux/netdevice.h>
++#include <linux/phy.h>
++#include <linux/module.h>
++#include <linux/init.h>
++
++/* GETH_FRAME_FILTER  register value */
++#define GETH_FRAME_FILTER_PR	0x00000001	/* Promiscuous Mode */
++#define GETH_FRAME_FILTER_HUC	0x00000002	/* Hash Unicast */
++#define GETH_FRAME_FILTER_HMC	0x00000004	/* Hash Multicast */
++#define GETH_FRAME_FILTER_DAIF	0x00000008	/* DA Inverse Filtering */
++#define GETH_FRAME_FILTER_PM	0x00000010	/* Pass all multicast */
++#define GETH_FRAME_FILTER_DBF	0x00000020	/* Disable Broadcast frames */
++#define GETH_FRAME_FILTER_SAIF	0x00000100	/* Inverse Filtering */
++#define GETH_FRAME_FILTER_SAF	0x00000200	/* Source Address Filter */
++#define GETH_FRAME_FILTER_HPF	0x00000400	/* Hash or perfect Filter */
++#define GETH_FRAME_FILTER_RA	0x80000000	/* Receive all mode */
++
++/* Default tx descriptor */
++#define TX_SINGLE_DESC0		0x80000000
++#define TX_SINGLE_DESC1		0x63000000
++
++/* Default rx descriptor */
++#define RX_SINGLE_DESC0		0x80000000
++#define RX_SINGLE_DESC1		0x83000000
++
++#define EPHY_ID			0x00441400
++#define AC300_ID		0xc0000000
++#define EPHY_ID_RTL8211F	0x001CC916
++#define IP101G_ID		0x02430c54
++
++typedef union {
++	struct {
++		/* TDES0 */
++		unsigned int deferred:1;	/* Deferred bit (only half-duplex) */
++		unsigned int under_err:1;	/* Underflow error */
++		unsigned int ex_deferral:1;	/* Excessive deferral */
++		unsigned int coll_cnt:4;	/* Collision count */
++		unsigned int vlan_tag:1;	/* VLAN Frame */
++		unsigned int ex_coll:1;		/* Excessive collision */
++		unsigned int late_coll:1;	/* Late collision */
++		unsigned int no_carr:1;		/* No carrier */
++		unsigned int loss_carr:1;	/* Loss of collision */
++		unsigned int ipdat_err:1;	/* IP payload error */
++		unsigned int frm_flu:1;		/* Frame flushed */
++		unsigned int jab_timeout:1;	/* Jabber timeout */
++		unsigned int err_sum:1;		/* Error summary */
++		unsigned int iphead_err:1;	/* IP header error */
++		unsigned int ttss:1;		/* Transmit time stamp status */
++		unsigned int reserved0:13;
++		unsigned int own:1;		/* Own bit. CPU:0, DMA:1 */
++	} tx;
++
++	/* bits 5 7 0 | Frame status
++	 * ----------------------------------------------------------
++	 *      0 0 0 | IEEE 802.3 Type frame (length < 1536 octects)
++	 *      1 0 0 | IPv4/6 No CSUM errorS.
++	 *      1 0 1 | IPv4/6 CSUM PAYLOAD error
++	 *      1 1 0 | IPv4/6 CSUM IP HR error
++	 *      1 1 1 | IPv4/6 IP PAYLOAD AND HEADER errorS
++	 *      0 0 1 | IPv4/6 unsupported IP PAYLOAD
++	 *      0 1 1 | COE bypassed.. no IPv4/6 frame
++	 *      0 1 0 | Reserved.
++	 */
++	struct {
++		/* RDES0 */
++		unsigned int chsum_err:1;	/* Payload checksum error */
++		unsigned int crc_err:1;		/* CRC error */
++		unsigned int dribbling:1;	/* Dribble bit error */
++		unsigned int mii_err:1;		/* Received error (bit3) */
++		unsigned int recv_wt:1;		/* Received watchdog timeout */
++		unsigned int frm_type:1;	/* Frame type */
++		unsigned int late_coll:1;	/* Late Collision */
++		unsigned int ipch_err:1;	/* IPv header checksum error (bit7) */
++		unsigned int last_desc:1;	/* Laset descriptor */
++		unsigned int first_desc:1;	/* First descriptor */
++		unsigned int vlan_tag:1;	/* VLAN Tag */
++		unsigned int over_err:1;	/* Overflow error (bit11) */
++		unsigned int len_err:1;		/* Length error */
++		unsigned int sou_filter:1;	/* Source address filter fail */
++		unsigned int desc_err:1;	/* Descriptor error */
++		unsigned int err_sum:1;		/* Error summary (bit15) */
++		unsigned int frm_len:14;	/* Frame length */
++		unsigned int des_filter:1;	/* Destination address filter fail */
++		unsigned int own:1;		/* Own bit. CPU:0, DMA:1 */
++	#define RX_PKT_OK		0x7FFFB77C
++	#define RX_LEN			0x3FFF0000
++	} rx;
++
++	unsigned int all;
++} desc0_u;
++
++typedef union {
++	struct {
++		/* TDES1 */
++		unsigned int buf1_size:11;	/* Transmit buffer1 size */
++		unsigned int buf2_size:11;	/* Transmit buffer2 size */
++		unsigned int ttse:1;		/* Transmit time stamp enable */
++		unsigned int dis_pad:1;		/* Disable pad (bit23) */
++		unsigned int adr_chain:1;	/* Second address chained */
++		unsigned int end_ring:1;	/* Transmit end of ring */
++		unsigned int crc_dis:1;		/* Disable CRC */
++		unsigned int cic:2;		/* Checksum insertion control (bit27:28) */
++		unsigned int first_sg:1;	/* First Segment */
++		unsigned int last_seg:1;	/* Last Segment */
++		unsigned int interrupt:1;	/* Interrupt on completion */
++	} tx;
++
++	struct {
++		/* RDES1 */
++		unsigned int buf1_size:11;	/* Received buffer1 size */
++		unsigned int buf2_size:11;	/* Received buffer2 size */
++		unsigned int reserved1:2;
++		unsigned int adr_chain:1;	/* Second address chained */
++		unsigned int end_ring:1;		/* Received end of ring */
++		unsigned int reserved2:5;
++		unsigned int dis_ic:1;		/* Disable interrupt on completion */
++	} rx;
++
++	unsigned int all;
++} desc1_u;
++
++typedef struct dma_desc {
++	desc0_u desc0;
++	desc1_u desc1;
++	/* The address of buffers */
++	unsigned int	desc2;
++	/* Next desc's address */
++	unsigned int	desc3;
++} __attribute__((packed)) dma_desc_t;
++
++enum rx_frame_status { /* IPC status */
++	good_frame = 0,
++	discard_frame = 1,
++	csum_none = 2,
++	llc_snap = 4,
++};
++
++enum tx_dma_irq_status {
++	tx_hard_error = 1,
++	tx_hard_error_bump_tc = 2,
++	handle_tx_rx = 3,
++};
++
++struct geth_extra_stats {
++	/* Transmit errors */
++	unsigned long tx_underflow;
++	unsigned long tx_carrier;
++	unsigned long tx_losscarrier;
++	unsigned long vlan_tag;
++	unsigned long tx_deferred;
++	unsigned long tx_vlan;
++	unsigned long tx_jabber;
++	unsigned long tx_frame_flushed;
++	unsigned long tx_payload_error;
++	unsigned long tx_ip_header_error;
++
++	/* Receive errors */
++	unsigned long rx_desc;
++	unsigned long sa_filter_fail;
++	unsigned long overflow_error;
++	unsigned long ipc_csum_error;
++	unsigned long rx_collision;
++	unsigned long rx_crc;
++	unsigned long dribbling_bit;
++	unsigned long rx_length;
++	unsigned long rx_mii;
++	unsigned long rx_multicast;
++	unsigned long rx_gmac_overflow;
++	unsigned long rx_watchdog;
++	unsigned long da_rx_filter_fail;
++	unsigned long sa_rx_filter_fail;
++	unsigned long rx_missed_cntr;
++	unsigned long rx_overflow_cntr;
++	unsigned long rx_vlan;
++
++	/* Tx/Rx IRQ errors */
++	unsigned long tx_undeflow_irq;
++	unsigned long tx_process_stopped_irq;
++	unsigned long tx_jabber_irq;
++	unsigned long rx_overflow_irq;
++	unsigned long rx_buf_unav_irq;
++	unsigned long rx_process_stopped_irq;
++	unsigned long rx_watchdog_irq;
++	unsigned long tx_early_irq;
++	unsigned long fatal_bus_error_irq;
++
++	/* Extra info */
++	unsigned long threshold;
++	unsigned long tx_pkt_n;
++	unsigned long rx_pkt_n;
++	unsigned long poll_n;
++	unsigned long sched_timer_n;
++	unsigned long normal_irq_n;
++};
++
++struct mii_reg_dump {
++	u32 addr;
++	u16 reg;
++	u16 value;
++};
++
++int sunxi_mdio_read(void *,  int, int);
++int sunxi_mdio_write(void *, int, int, unsigned short);
++int sunxi_mdio_reset(void *);
++void sunxi_set_link_mode(void *iobase, int duplex, int speed);
++void sunxi_int_disable(void *);
++int sunxi_int_status(void *, struct geth_extra_stats *x);
++int sunxi_mac_init(void *, int txmode, int rxmode);
++void sunxi_set_umac(void *, unsigned char *, int);
++void sunxi_mac_enable(void *);
++void sunxi_mac_disable(void *);
++void sunxi_tx_poll(void *);
++void sunxi_int_enable(void *);
++void sunxi_start_rx(void *, unsigned long);
++void sunxi_start_tx(void *, unsigned long);
++void sunxi_stop_tx(void *);
++void sunxi_stop_rx(void *);
++void sunxi_hash_filter(void *iobase, unsigned long low, unsigned long high);
++void sunxi_set_filter(void *iobase, unsigned long flags);
++void sunxi_flow_ctrl(void *iobase, int duplex, int fc, int pause);
++void sunxi_mac_loopback(void *iobase, int enable);
++
++void desc_buf_set(struct dma_desc *p, unsigned long paddr, int size);
++void desc_set_own(struct dma_desc *p);
++void desc_init_chain(struct dma_desc *p, unsigned long paddr,  unsigned int size);
++void desc_tx_close(struct dma_desc *first, struct dma_desc *end, int csum_insert);
++void desc_init(struct dma_desc *p);
++int desc_get_tx_status(struct dma_desc *desc, struct geth_extra_stats *x);
++int desc_buf_get_len(struct dma_desc *desc);
++int desc_buf_get_addr(struct dma_desc *desc);
++int desc_get_rx_status(struct dma_desc *desc, struct geth_extra_stats *x);
++int desc_get_own(struct dma_desc *desc);
++int desc_get_tx_ls(struct dma_desc *desc);
++int desc_rx_frame_len(struct dma_desc *desc);
++
++int sunxi_mac_reset(void *iobase, void (*mdelay)(int), int n);
++int sunxi_geth_register(void *iobase, int version, unsigned int div);
++
++int sunxi_parse_read_str(char *str, u16 *addr, u16 *reg);
++int sunxi_parse_write_str(char *str, u16 *addr, u16 *reg, u16 *val);
++extern int ephy_is_enable(void);
++extern int gmac_ephy_shutdown(void);
++
++#if defined(CONFIG_ARCH_SUN8IW3) \
++	|| defined(CONFIG_ARCH_SUN9IW1) \
++	|| defined(CONFIG_ARCH_SUN7I)
++#define HW_VERSION	0
++#else
++#define HW_VERSION	1
++#endif
++
++#endif
+diff --git a/drivers/net/ethernet/allwinner/sunxi_gmac_ops.c b/drivers/net/ethernet/allwinner/sunxi_gmac_ops.c
+new file mode 100644
+index 000000000000..926516835023
+--- /dev/null
++++ b/drivers/net/ethernet/allwinner/sunxi_gmac_ops.c
+@@ -0,0 +1,768 @@
++/*
++ * linux/drivers/net/ethernet/allwinner/sunxi_gmac_ops.c
++ *
++ * Copyright © 2016-2018, fuzhaoke
++ *		Author: fuzhaoke <fuzhaoke@allwinnertech.com>
++ *
++ * This file is provided under a dual BSD/GPL license.  When using or
++ * redistributing this file, you may do so under either license.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
++ * GNU General Public License for more details.
++ */
++#include <linux/kernel.h>
++#include <linux/ctype.h>
++#include <linux/printk.h>
++#include <linux/io.h>
++#include "sunxi-gmac.h"
++
++/******************************************************************************
++ *	sun8iw6 operations
++ *****************************************************************************/
++#define GETH_BASIC_CTL0		0x00
++#define GETH_BASIC_CTL1		0x04
++#define GETH_INT_STA		0x08
++#define GETH_INT_EN		0x0C
++#define GETH_TX_CTL0		0x10
++#define GETH_TX_CTL1		0x14
++#define GETH_TX_FLOW_CTL	0x1C
++#define GETH_TX_DESC_LIST	0x20
++#define GETH_RX_CTL0		0x24
++#define GETH_RX_CTL1		0x28
++#define GETH_RX_DESC_LIST	0x34
++#define GETH_RX_FRM_FLT		0x38
++#define GETH_RX_HASH0		0x40
++#define GETH_RX_HASH1		0x44
++#define GETH_MDIO_ADDR		0x48
++#define GETH_MDIO_DATA		0x4C
++#define GETH_ADDR_HI(reg)	(0x50 + ((reg) << 3))
++#define GETH_ADDR_LO(reg)	(0x54 + ((reg) << 3))
++#define GETH_TX_DMA_STA		0xB0
++#define GETH_TX_CUR_DESC	0xB4
++#define GETH_TX_CUR_BUF		0xB8
++#define GETH_RX_DMA_STA		0xC0
++#define GETH_RX_CUR_DESC	0xC4
++#define GETH_RX_CUR_BUF		0xC8
++#define GETH_RGMII_STA		0xD0
++
++#define RGMII_IRQ		0x00000001
++
++#define	CTL0_LM			0x02
++#define CTL0_DM			0x01
++#define CTL0_SPEED		0x04
++
++#define BURST_LEN		0x3F000000
++#define RX_TX_PRI		0x02
++#define SOFT_RST		0x01
++
++#define TX_FLUSH		0x01
++#define TX_MD			0x02
++#define TX_NEXT_FRM		0x04
++#define TX_TH			0x0700
++
++#define RX_FLUSH		0x01
++#define RX_MD			0x02
++#define RX_RUNT_FRM		0x04
++#define RX_TH			0x0030
++
++#define TX_INT			0x00001
++#define TX_STOP_INT		0x00002
++#define TX_UA_INT		0x00004
++#define TX_TOUT_INT		0x00008
++#define TX_UNF_INT		0x00010
++#define TX_EARLY_INT		0x00020
++#define RX_INT			0x00100
++#define RX_UA_INT		0x00200
++#define RX_STOP_INT		0x00400
++#define RX_TOUT_INT		0x00800
++#define RX_OVF_INT		0x01000
++#define RX_EARLY_INT		0x02000
++#define LINK_STA_INT		0x10000
++
++#define DISCARD_FRAME	-1
++#define GOOD_FRAME	0
++#define CSUM_NONE	2
++#define LLC_SNAP	4
++
++#define SF_DMA_MODE		1
++
++/* Flow Control defines */
++#define FLOW_OFF	0
++#define FLOW_RX		1
++#define FLOW_TX		2
++#define FLOW_AUTO	(FLOW_TX | FLOW_RX)
++
++#define HASH_TABLE_SIZE 64
++#define PAUSE_TIME 0x200
++#define GMAC_MAX_UNICAST_ADDRESSES	8
++
++/* PHY address */
++#define PHY_ADDR		0x01
++#define PHY_DM			0x0010
++#define PHY_AUTO_NEG		0x0020
++#define PHY_POWERDOWN		0x0080
++#define PHY_NEG_EN		0x1000
++
++#define MII_BUSY		0x00000001
++#define MII_WRITE		0x00000002
++#define MII_PHY_MASK		0x0000FFC0
++#define MII_CR_MASK		0x0000001C
++#define MII_CLK			0x00000008
++/* bits 4 3 2 | AHB1 Clock	| MDC Clock
++ * -------------------------------------------------------
++ *      0 0 0 | 60 ~ 100 MHz	| div-42
++ *      0 0 1 | 100 ~ 150 MHz	| div-62
++ *      0 1 0 | 20 ~ 35 MHz	| div-16
++ *      0 1 1 | 35 ~ 60 MHz	| div-26
++ *      1 0 0 | 150 ~ 250 MHz	| div-102
++ *      1 0 1 | 250 ~ 300 MHz	| div-124
++ *      1 1 x | Reserved	|
++ */
++
++enum csum_insertion {
++	cic_dis		= 0, /* Checksum Insertion Control */
++	cic_ip		= 1, /* Only IP header */
++	cic_no_pse	= 2, /* IP header but not pseudoheader */
++	cic_full	= 3, /* IP header and pseudoheader */
++};
++
++struct gethdev {
++	void *iobase;
++	unsigned int ver;
++	unsigned int mdc_div;
++};
++
++static struct gethdev hwdev;
++
++/***************************************************************************
++ * External interface
++ **************************************************************************/
++/* Set a ring desc buffer */
++void desc_init_chain(struct dma_desc *desc, unsigned long addr, unsigned int size)
++{
++	/* In chained mode the desc3 points to the next element in the ring.
++	 * The latest element has to point to the head.
++	 */
++	int i;
++	struct dma_desc *p = desc;
++	unsigned long dma_phy = addr;
++
++	for (i = 0; i < (size - 1); i++) {
++		dma_phy += sizeof(struct dma_desc);
++		p->desc3 = (unsigned int)dma_phy;
++		/* Chain mode */
++		p->desc1.all |= (1 << 24);
++		p++;
++	}
++	p->desc1.all |= (1 << 24);
++	p->desc3 = (unsigned int)addr;
++}
++
++int sunxi_mdio_read(void *iobase, int phyaddr, int phyreg)
++{
++	unsigned int value = 0;
++
++	/* Mask the MDC_DIV_RATIO */
++	value |= ((hwdev.mdc_div & 0x07) << 20);
++	value |= (((phyaddr << 12) & (0x0001F000)) |
++			((phyreg << 4) & (0x000007F0)) |
++			MII_BUSY);
++
++	while (((readl(iobase + GETH_MDIO_ADDR)) & MII_BUSY) == 1)
++		;
++
++	writel(value, iobase + GETH_MDIO_ADDR);
++	while (((readl(iobase + GETH_MDIO_ADDR)) & MII_BUSY) == 1)
++		;
++
++	return (int)readl(iobase + GETH_MDIO_DATA);
++}
++
++int sunxi_mdio_write(void *iobase, int phyaddr, int phyreg, unsigned short data)
++{
++	unsigned int value;
++
++	value = ((0x07 << 20) & readl(iobase + GETH_MDIO_ADDR)) |
++		 (hwdev.mdc_div << 20);
++	value |= (((phyaddr << 12) & (0x0001F000)) |
++		  ((phyreg << 4) & (0x000007F0))) |
++		  MII_WRITE | MII_BUSY;
++
++	/* Wait until any existing MII operation is complete */
++	while (((readl(iobase + GETH_MDIO_ADDR)) & MII_BUSY) == 1)
++		;
++
++	/* Set the MII address register to write */
++	writel(data, iobase + GETH_MDIO_DATA);
++	writel(value, iobase + GETH_MDIO_ADDR);
++
++	/* Wait until any existing MII operation is complete */
++	while (((readl(iobase + GETH_MDIO_ADDR)) & MII_BUSY) == 1)
++		;
++
++	return 0;
++}
++
++int sunxi_mdio_reset(void *iobase)
++{
++	writel((4 << 2), iobase + GETH_MDIO_ADDR);
++	return 0;
++}
++
++void sunxi_set_link_mode(void *iobase, int duplex, int speed)
++{
++	unsigned int ctrl = readl(iobase + GETH_BASIC_CTL0);
++
++	if (!duplex)
++		ctrl &= ~CTL0_DM;
++	else
++		ctrl |= CTL0_DM;
++
++	switch (speed) {
++	case 1000:
++		ctrl &= ~0x0C;
++		break;
++	case 100:
++	case 10:
++	default:
++		ctrl |= 0x08;
++		if (speed == 100)
++			ctrl |= 0x04;
++		else
++			ctrl &= ~0x04;
++		break;
++	}
++
++	writel(ctrl, iobase + GETH_BASIC_CTL0);
++}
++
++void sunxi_mac_loopback(void *iobase, int enable)
++{
++	int reg;
++
++	reg = readl(iobase + GETH_BASIC_CTL0);
++	if (enable)
++		reg |= 0x02;
++	else
++		reg &= ~0x02;
++	writel(reg, iobase + GETH_BASIC_CTL0);
++}
++
++void sunxi_flow_ctrl(void *iobase, int duplex, int fc, int pause)
++{
++	unsigned int flow = 0;
++
++	if (fc & FLOW_RX) {
++		flow = readl(iobase + GETH_RX_CTL0);
++		flow |= 0x10000;
++		writel(flow, iobase + GETH_RX_CTL0);
++	}
++
++	if (fc & FLOW_TX) {
++		flow = readl(iobase + GETH_TX_FLOW_CTL);
++		flow |= 0x00001;
++		writel(flow, iobase + GETH_TX_FLOW_CTL);
++	}
++
++	if (duplex) {
++		flow = readl(iobase + GETH_TX_FLOW_CTL);
++		flow |= (pause << 4);
++		writel(flow, iobase + GETH_TX_FLOW_CTL);
++	}
++}
++
++int sunxi_int_status(void *iobase, struct geth_extra_stats *x)
++{
++	int ret = 0;
++	/* read the status register (CSR5) */
++	unsigned int intr_status;
++
++	intr_status = readl(iobase + GETH_RGMII_STA);
++	if (intr_status & RGMII_IRQ)
++		readl(iobase + GETH_RGMII_STA);
++
++	intr_status = readl(iobase + GETH_INT_STA);
++
++	/* ABNORMAL interrupts */
++	if (intr_status & TX_UNF_INT) {
++		ret = tx_hard_error_bump_tc;
++		x->tx_undeflow_irq++;
++	}
++	if (intr_status & TX_TOUT_INT) {
++		x->tx_jabber_irq++;
++	}
++	if (intr_status & RX_OVF_INT) {
++		x->rx_overflow_irq++;
++	}
++	if (intr_status & RX_UA_INT) {
++		x->rx_buf_unav_irq++;
++	}
++	if (intr_status & RX_STOP_INT) {
++		x->rx_process_stopped_irq++;
++	}
++	if (intr_status & RX_TOUT_INT) {
++		x->rx_watchdog_irq++;
++	}
++	if (intr_status & TX_EARLY_INT) {
++		x->tx_early_irq++;
++	}
++	if (intr_status & TX_STOP_INT) {
++		x->tx_process_stopped_irq++;
++		ret = tx_hard_error;
++	}
++
++	/* TX/RX NORMAL interrupts */
++	if (intr_status & (TX_INT | RX_INT | RX_EARLY_INT | TX_UA_INT)) {
++		x->normal_irq_n++;
++		if (intr_status & (TX_INT | RX_INT))
++			ret = handle_tx_rx;
++	}
++	/* Clear the interrupt by writing a logic 1 to the CSR5[15-0] */
++	writel(intr_status & 0x3FFF, iobase + GETH_INT_STA);
++
++	return ret;
++}
++
++void sunxi_start_rx(void *iobase, unsigned long rxbase)
++{
++	unsigned int value;
++
++	/* Write the base address of Rx descriptor lists into registers */
++	writel(rxbase, iobase + GETH_RX_DESC_LIST);
++
++	value = readl(iobase + GETH_RX_CTL1);
++	value |= 0x40000000;
++	writel(value, iobase + GETH_RX_CTL1);
++}
++
++void sunxi_stop_rx(void *iobase)
++{
++	unsigned int value;
++
++	value = readl(iobase + GETH_RX_CTL1);
++	value &= ~0x40000000;
++	writel(value, iobase + GETH_RX_CTL1);
++}
++
++void sunxi_start_tx(void *iobase, unsigned long txbase)
++{
++	unsigned int value;
++
++	/* Write the base address of Tx descriptor lists into registers */
++	writel(txbase, iobase + GETH_TX_DESC_LIST);
++
++	value = readl(iobase + GETH_TX_CTL1);
++	value |= 0x40000000;
++	writel(value, iobase + GETH_TX_CTL1);
++}
++
++void sunxi_stop_tx(void *iobase)
++{
++	unsigned int value = readl(iobase + GETH_TX_CTL1);
++
++	value &= ~0x40000000;
++	writel(value, iobase + GETH_TX_CTL1);
++}
++
++static int sunxi_dma_init(void *iobase)
++{
++	unsigned int value;
++
++	/* Burst should be 8 */
++	value = (8 << 24);
++
++#ifdef CONFIG_GMAC_DA
++	value |= RX_TX_PRI;	/* Rx has priority over tx */
++#endif
++	writel(value, iobase + GETH_BASIC_CTL1);
++
++	/* Mask interrupts by writing to CSR7 */
++	writel(RX_INT | TX_INT | TX_UNF_INT, iobase + GETH_INT_EN);
++
++	return 0;
++}
++
++int sunxi_mac_init(void *iobase, int txmode, int rxmode)
++{
++	unsigned int value;
++
++	sunxi_dma_init(iobase);
++
++	/* Initialize the core component */
++	value = readl(iobase + GETH_TX_CTL0);
++	value |= (1 << 30);	/* Jabber Disable */
++	writel(value, iobase + GETH_TX_CTL0);
++
++	value = readl(iobase + GETH_RX_CTL0);
++	value |= (1 << 27);	/* Enable CRC & IPv4 Header Checksum */
++	value |= (1 << 28);	/* Automatic Pad/CRC Stripping */
++	value |= (1 << 29);	/* Jumbo Frame Enable */
++	writel(value, iobase + GETH_RX_CTL0);
++
++	writel((hwdev.mdc_div << 20), iobase + GETH_MDIO_ADDR); /* MDC_DIV_RATIO */
++
++	/* Set the Rx&Tx mode */
++	value = readl(iobase + GETH_TX_CTL1);
++	if (txmode == SF_DMA_MODE) {
++		/* Transmit COE type 2 cannot be done in cut-through mode. */
++		value |= TX_MD;
++		/* Operating on second frame increase the performance
++		 * especially when transmit store-and-forward is used.
++		 */
++		value |= TX_NEXT_FRM;
++	} else {
++		value &= ~TX_MD;
++		value &= ~TX_TH;
++		/* Set the transmit threshold */
++		if (txmode <= 64)
++			value |= 0x00000000;
++		else if (txmode <= 128)
++			value |= 0x00000100;
++		else if (txmode <= 192)
++			value |= 0x00000200;
++		else
++			value |= 0x00000300;
++	}
++	writel(value, iobase + GETH_TX_CTL1);
++
++	value = readl(iobase + GETH_RX_CTL1);
++	if (rxmode == SF_DMA_MODE) {
++		value |= RX_MD;
++	} else {
++		value &= ~RX_MD;
++		value &= ~RX_TH;
++		if (rxmode <= 32)
++			value |= 0x10;
++		else if (rxmode <= 64)
++			value |= 0x00;
++		else if (rxmode <= 96)
++			value |= 0x20;
++		else
++			value |= 0x30;
++	}
++	writel(value, iobase + GETH_RX_CTL1);
++
++	return 0;
++}
++
++void sunxi_hash_filter(void *iobase, unsigned long low, unsigned long high)
++{
++	writel(high, iobase + GETH_RX_HASH0);
++	writel(low, iobase + GETH_RX_HASH1);
++}
++
++void sunxi_set_filter(void *iobase, unsigned long flags)
++{
++	int tmp_flags;
++
++	tmp_flags = readl(iobase + GETH_RX_FRM_FLT);
++
++	tmp_flags |= ((flags >> 31) |
++			((flags >> 9) & 0x00000002) |
++			((flags << 1) & 0x00000010) |
++			((flags >> 3) & 0x00000060) |
++			((flags << 7) & 0x00000300) |
++			((flags << 6) & 0x00003000) |
++			((flags << 12) & 0x00030000) |
++			(flags << 31));
++
++	writel(tmp_flags, iobase + GETH_RX_FRM_FLT);
++}
++
++void sunxi_set_umac(void *iobase, unsigned char *addr, int index)
++{
++	unsigned long data;
++
++	data = (addr[5] << 8) | addr[4];
++	writel(data, iobase + GETH_ADDR_HI(index));
++	data = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
++	writel(data, iobase + GETH_ADDR_LO(index));
++}
++
++void sunxi_mac_enable(void *iobase)
++{
++	unsigned long value;
++
++	value = readl(iobase + GETH_TX_CTL0);
++	value |= (1 << 31);
++	writel(value, iobase + GETH_TX_CTL0);
++
++	value = readl(iobase + GETH_RX_CTL0);
++	value |= (1 << 31);
++	writel(value, iobase + GETH_RX_CTL0);
++}
++
++void sunxi_mac_disable(void *iobase)
++{
++	unsigned long value;
++
++	value = readl(iobase + GETH_TX_CTL0);
++	value &= ~(1 << 31);
++	writel(value, iobase + GETH_TX_CTL0);
++
++	value = readl(iobase + GETH_RX_CTL0);
++	value &= ~(1 << 31);
++	writel(value, iobase + GETH_RX_CTL0);
++}
++
++void sunxi_tx_poll(void *iobase)
++{
++	unsigned int value;
++
++	value = readl(iobase + GETH_TX_CTL1);
++	writel(value | 0x80000000, iobase + GETH_TX_CTL1);
++}
++
++void sunxi_rx_poll(void *iobase)
++{
++	unsigned int value;
++
++	value = readl(iobase + GETH_RX_CTL1);
++	writel(value | 0x80000000, iobase + GETH_RX_CTL1);
++}
++
++void sunxi_int_enable(void *iobase)
++{
++	writel(RX_INT | TX_INT | TX_UNF_INT, iobase + GETH_INT_EN);
++}
++
++void sunxi_int_disable(void *iobase)
++{
++	writel(0, iobase + GETH_INT_EN);
++}
++
++void desc_buf_set(struct dma_desc *desc, unsigned long paddr, int size)
++{
++	desc->desc1.all &= (~((1 << 11) - 1));
++	desc->desc1.all |= (size & ((1 << 11) - 1));
++	desc->desc2 = paddr;
++}
++
++void desc_set_own(struct dma_desc *desc)
++{
++	desc->desc0.all |= 0x80000000;
++}
++
++void desc_tx_close(struct dma_desc *first, struct dma_desc *end, int csum_insert)
++{
++	struct dma_desc *desc = first;
++
++	first->desc1.tx.first_sg = 1;
++	end->desc1.tx.last_seg = 1;
++	end->desc1.tx.interrupt = 1;
++
++	if (csum_insert)
++		do {
++			desc->desc1.tx.cic = 3;
++			desc++;
++		} while (desc <= end);
++}
++
++void desc_init(struct dma_desc *desc)
++{
++	desc->desc1.all = 0;
++	desc->desc2  = 0;
++
++	desc->desc1.all |= (1 << 24);
++}
++
++int desc_get_tx_status(struct dma_desc *desc, struct geth_extra_stats *x)
++{
++	int ret = 0;
++
++	if (desc->desc0.tx.under_err) {
++		x->tx_underflow++;
++		ret = -1;
++	}
++	if (desc->desc0.tx.no_carr) {
++		x->tx_carrier++;
++		ret = -1;
++	}
++	if (desc->desc0.tx.loss_carr) {
++		x->tx_losscarrier++;
++		ret = -1;
++	}
++
++#if 0
++	if ((desc->desc0.tx.ex_deferral) ||
++			(desc->desc0.tx.ex_coll) ||
++			(desc->desc0.tx.late_coll))
++		stats->collisions += desc->desc0.tx.coll_cnt;
++#endif
++
++	if (desc->desc0.tx.deferred)
++		x->tx_deferred++;
++
++	return ret;
++}
++
++int desc_buf_get_len(struct dma_desc *desc)
++{
++	return (desc->desc1.all & ((1 << 11) - 1));
++}
++
++int desc_buf_get_addr(struct dma_desc *desc)
++{
++	return desc->desc2;
++}
++
++int desc_rx_frame_len(struct dma_desc *desc)
++{
++	return desc->desc0.rx.frm_len;
++}
++
++int desc_get_rx_status(struct dma_desc *desc, struct geth_extra_stats *x)
++{
++	int ret = good_frame;
++
++	if (desc->desc0.rx.last_desc == 0) {
++		return discard_frame;
++	}
++
++	if (desc->desc0.rx.err_sum) {
++		if (desc->desc0.rx.desc_err)
++			x->rx_desc++;
++
++		if (desc->desc0.rx.sou_filter)
++			x->sa_filter_fail++;
++
++		if (desc->desc0.rx.over_err)
++			x->overflow_error++;
++
++		if (desc->desc0.rx.ipch_err)
++			x->ipc_csum_error++;
++
++		if (desc->desc0.rx.late_coll)
++			x->rx_collision++;
++
++		if (desc->desc0.rx.crc_err)
++			x->rx_crc++;
++
++		ret = discard_frame;
++	}
++
++	if (desc->desc0.rx.len_err) {
++		ret = discard_frame;
++	}
++	if (desc->desc0.rx.mii_err) {
++		ret = discard_frame;
++	}
++
++	return ret;
++}
++
++int desc_get_own(struct dma_desc *desc)
++{
++	return desc->desc0.all & 0x80000000;
++}
++
++int desc_get_tx_ls(struct dma_desc *desc)
++{
++	return desc->desc1.tx.last_seg;
++}
++
++int sunxi_geth_register(void *iobase, int version, unsigned int div)
++{
++	hwdev.ver = version;
++	hwdev.iobase = iobase;
++	hwdev.mdc_div = div;
++
++	return 0;
++}
++
++int sunxi_mac_reset(void *iobase, void (*delay)(int), int n)
++{
++	unsigned int value;
++
++	/* DMA SW reset */
++	value = readl(iobase + GETH_BASIC_CTL1);
++	value |= SOFT_RST;
++	writel(value, iobase + GETH_BASIC_CTL1);
++
++	delay(n);
++
++	return !!(readl(iobase + GETH_BASIC_CTL1) & SOFT_RST);
++}
++
++/**
++ * sunxi_parse_read_str - parse the input string for write attri.
++ * @str: string to be parsed, eg: "0x00 0x01".
++ * @addr: store the reg address. eg: 0x00.
++ * @reg: store the expect value. eg: 0x01.
++ *
++ * return 0 if success, otherwise failed.
++ */
++int sunxi_parse_read_str(char *str, u16 *addr, u16 *reg)
++{
++	char *ptr = str;
++	char *tstr = NULL;
++	int ret;
++
++	/*
++	 * Skip the leading whitespace, find the true split symbol.
++	 * And it must be 'address value'.
++	 */
++	tstr = strim(str);
++	ptr = strchr(tstr, ' ');
++	if (!ptr)
++		return -EINVAL;
++
++	/*
++	 * Replaced split symbol with a %NUL-terminator temporary.
++	 * Will be fixed at end.
++	 */
++	*ptr = '\0';
++	ret = kstrtos16(tstr, 16, addr);
++	if (ret)
++		goto out;
++
++	ret = kstrtos16(skip_spaces(ptr + 1), 16, reg);
++
++out:
++	return ret;
++}
++
++/**
++ * sunxi_parse_write_str - parse the input string for compare attri.
++ * @str: string to be parsed, eg: "0x00 0x11 0x11".
++ * @addr: store the address. eg: 0x00.
++ * @reg: store the reg. eg: 0x11.
++ * @val: store the value. eg: 0x11.
++ *
++ * return 0 if success, otherwise failed.
++ */
++int sunxi_parse_write_str(char *str, u16 *addr,
++			  u16 *reg, u16 *val)
++{
++	u16 result_addr[3] = { 0 };
++	char *ptr = str;
++	char *ptr2 = NULL;
++	int i, ret = 0;
++
++	for (i = 0; i < ARRAY_SIZE(result_addr); i++) {
++		ptr = skip_spaces(ptr);
++		ptr2 = strchr(ptr, ' ');
++		if (ptr2)
++			*ptr2 = '\0';
++
++		ret = kstrtou16(ptr, 16, &result_addr[i]);
++		if (!ptr2)
++			break;
++
++		*ptr2 = ' ';
++
++		if (ret)
++			break;
++
++		ptr = ptr2 + 1;
++	}
++
++	*addr = result_addr[0];
++	*reg = result_addr[1];
++	*val = result_addr[2];
++
++	return ret;
++}
++MODULE_LICENSE("Dual BSD/GPL");
+diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
+index 9e73ab1b2fbb..782fb4445e55 100644
+--- a/drivers/net/phy/Kconfig
++++ b/drivers/net/phy/Kconfig
+@@ -91,6 +91,14 @@ config AC200_PHY
+ 	help
+ 	  Fast ethernet PHY as found in X-Powers AC200 multi-function device.
+ 
++config AC200_PHY_SUNXI
++	tristate "AC200 EPHY(Sunxi)"
++	depends on NVMEM
++	depends on OF
++	depends on MFD_AC200_SUNXI
++	help
++	  Fast ethernet PHY as found in X-Powers AC200(Sunxi) multi-function device.
++
+ config AMD_PHY
+ 	tristate "AMD and Altima PHYs"
+ 	help
+diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
+index 828de189d7ae..88597adfcebb 100644
+--- a/drivers/net/phy/Makefile
++++ b/drivers/net/phy/Makefile
+@@ -34,6 +34,7 @@ sfp-obj-$(CONFIG_SFP)		+= sfp-bus.o
+ obj-y				+= $(sfp-obj-y) $(sfp-obj-m)
+ 
+ obj-$(CONFIG_AC200_PHY)		+= ac200-phy.o
++obj-$(CONFIG_AC200_PHY_SUNXI)		+= sunxi-ephy.o
+ obj-$(CONFIG_ADIN_PHY)		+= adin.o
+ obj-$(CONFIG_ADIN1100_PHY)	+= adin1100.o
+ obj-$(CONFIG_AIR_EN8811H_PHY)   += air_en8811h.o
+diff --git a/drivers/net/phy/sunxi-ephy.c b/drivers/net/phy/sunxi-ephy.c
+new file mode 100644
+index 000000000000..44eb2790ea62
+--- /dev/null
++++ b/drivers/net/phy/sunxi-ephy.c
+@@ -0,0 +1,516 @@
++/*
++ * Copyright © 2015-2016, Shuge
++ *		Author: Sugar <shugeLinux@gmail.com>
++ *
++ * This file is provided under a dual BSD/GPL license.  When using or
++ * redistributing this file, you may do so under either license.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
++ * GNU General Public License for more details.
++ *
++ */
++#include <linux/kernel.h>
++#include <linux/string.h>
++#include <linux/errno.h>
++#include <linux/unistd.h>
++#include <linux/interrupt.h>
++#include <linux/init.h>
++#include <linux/delay.h>
++#include <linux/netdevice.h>
++#include <linux/etherdevice.h>
++#include <linux/skbuff.h>
++#include <linux/spinlock.h>
++#include <linux/mm.h>
++#include <linux/module.h>
++#include <linux/mii.h>
++#include <linux/ethtool.h>
++#include <linux/phy.h>
++#include <linux/platform_device.h>
++
++#include <asm/io.h>
++#include <asm/irq.h>
++
++#include <linux/mfd/ac200.h>
++
++#define EPHY_AC200 1
++#define EPHY_AC300 2
++
++#define WAIT_MAX_COUNT 200
++
++struct ephy_res {
++	struct phy_device *ac300;
++	struct ac200_dev *ac200;
++	atomic_t ephy_en;
++};
++
++static struct ephy_res ac200_ephy;
++static struct ephy_res ac300_ephy;
++u8 ephy_type;
++
++static int ac200_reg_read(struct ac200_dev *ac200, unsigned short reg)
++{
++	unsigned int val;
++	int ret;
++
++	ret = regmap_read(ac200->regmap, reg, &val);
++
++	if (ret < 0)
++		return ret;
++	else
++		return val;
++}
++
++static int ac200_reg_write(struct ac200_dev *ac200, unsigned short reg, unsigned short val)
++{
++	return regmap_write(ac200->regmap, reg, val);
++}
++
++int ephy_is_enable(void)
++{
++	if (ephy_type == EPHY_AC200)
++		return atomic_read(&ac200_ephy.ephy_en);
++	else if (ephy_type == EPHY_AC300)
++		return atomic_read(&ac300_ephy.ephy_en);
++	return 0;
++}
++EXPORT_SYMBOL_GPL(ephy_is_enable);
++
++static void disable_intelligent_ieee(struct phy_device *phydev)
++{
++	unsigned int value;
++
++	phy_write(phydev, 0x1f, 0x0100); /* switch to page 1 */
++	value = phy_read(phydev, 0x17);  /* read address 0 0x17 register */
++	value &= ~(1 << 3);			  /* reg 0x17 bit 3, set 0 to disable IEEE */
++	phy_write(phydev, 0x17, value);
++	phy_write(phydev, 0x1f, 0x0000); /* switch to page 0 */
++}
++
++static void disable_802_3az_ieee(struct phy_device *phydev)
++{
++	unsigned int value;
++
++	phy_write(phydev, 0xd, 0x7);
++	phy_write(phydev, 0xe, 0x3c);
++	phy_write(phydev, 0xd, 0x1 << 14 | 0x7);
++	value = phy_read(phydev, 0xe);
++	value &= ~(0x1 << 1);
++	phy_write(phydev, 0xd, 0x7);
++	phy_write(phydev, 0xe, 0x3c);
++	phy_write(phydev, 0xd, 0x1 << 14 | 0x7);
++	phy_write(phydev, 0xe, value);
++
++	phy_write(phydev, 0x1f, 0x0200); /* switch to page 2 */
++	phy_write(phydev, 0x18, 0x0000);
++}
++
++static void ephy_config_default(struct phy_device *phydev)
++{
++	phy_write(phydev, 0x1f, 0x0100); /* Switch to Page 1 */
++	phy_write(phydev, 0x12, 0x4824); /* Disable APS */
++
++	phy_write(phydev, 0x1f, 0x0200); /* Switch to Page 2 */
++	phy_write(phydev, 0x18, 0x0000); /* PHYAFE TRX optimization */
++
++	phy_write(phydev, 0x1f, 0x0600); /* Switch to Page 6 */
++	phy_write(phydev, 0x14, 0x708b); /* PHYAFE TX optimization */
++	phy_write(phydev, 0x13, 0xF000); /* PHYAFE RX optimization */
++	phy_write(phydev, 0x15, 0x1530);
++
++	phy_write(phydev, 0x1f, 0x0800); /* Switch to Page 8 */
++	phy_write(phydev, 0x18, 0x00bc); /* PHYAFE TRX optimization */
++}
++
++static void __maybe_unused ephy_config_fixed(struct phy_device *phydev)
++{
++	phy_write(phydev, 0x1f, 0x0100); /*switch to Page 1 */
++	phy_write(phydev, 0x12, 0x4824); /*Disable APS */
++
++	phy_write(phydev, 0x1f, 0x0200); /*switch to Page 2 */
++	phy_write(phydev, 0x18, 0x0000); /*PHYAFE TRX optimization */
++
++	phy_write(phydev, 0x1f, 0x0600); /*switch to Page 6 */
++	phy_write(phydev, 0x14, 0x7809); /*PHYAFE TX optimization */
++	phy_write(phydev, 0x13, 0xf000); /*PHYAFE RX optimization */
++	phy_write(phydev, 0x10, 0x5523);
++	phy_write(phydev, 0x15, 0x3533);
++
++	phy_write(phydev, 0x1f, 0x0800); /*switch to Page 8 */
++	phy_write(phydev, 0x1d, 0x0844); /*disable auto offset */
++	phy_write(phydev, 0x18, 0x00bc); /*PHYAFE TRX optimization */
++}
++
++static void __maybe_unused ephy_config_cali(struct phy_device *phydev, u16 ephy_cali)
++{
++	int value;
++	value = phy_read(phydev, 0x06);
++	value &= ~(0x0F << 12);
++	value |= (0x0F & (0x03 + ephy_cali)) << 12;
++	phy_write(phydev, 0x06, value);
++
++	return;
++}
++
++int ephy_config_init(struct phy_device *phydev)
++{
++	int value;
++#if 1 //defined(CONFIG_ARCH_SUN50IW9)
++	if (ephy_type == EPHY_AC300) {
++		int ret;
++		u16 ephy_cali = 0;
++		ephy_cali = sun50i_ephy_calibrate_value();
++		if (ret) {
++			pr_err("ephy cali efuse read fail!\n");
++			return -1;
++		}
++		ephy_config_cali(ac300_ephy.ac300, ephy_cali);
++		/*
++		* BIT9: the flag of calibration value
++		* 0: Normal
++		* 1: Low level of calibration value
++		*/
++		if (ephy_cali & BIT(9)) {
++			pr_debug("ac300:ephy cali efuse read: fixed!\n");
++			ephy_config_fixed(phydev);
++		} else {
++			pr_debug("ac300:ephy cali efuse read: default!\n");
++			ephy_config_default(phydev);
++		}
++	} else {
++		pr_debug("ac200:ephy cali efuse read: default!\n");
++		ephy_config_default(phydev);
++	}
++#else
++	ephy_config_default(phydev);
++#endif
++
++#if 0
++	/* Disable Auto Power Saving mode */
++	phy_write(phydev, 0x1f, 0x0100); /* Switch to Page 1 */
++	value = phy_read(phydev, 0x17);
++	value &= ~BIT(13);
++	phy_write(phydev, 0x17, value);
++#endif
++	disable_intelligent_ieee(phydev); /* Disable Intelligent IEEE */
++	disable_802_3az_ieee(phydev);  /* Disable 802.3az IEEE */
++	phy_write(phydev, 0x1f, 0x0000); /* Switch to Page 0 */
++
++#if 1 // def CONFIG_MFD_ACX00
++	if (ephy_type == EPHY_AC200) {
++		value = ac200_reg_read(ac200_ephy.ac200, AC200_EPHY_CTL);
++		if (phydev->interface == PHY_INTERFACE_MODE_RMII)
++			value |= (1 << 11);
++		else
++			value &= (~(1 << 11));
++		ac200_reg_write(ac200_ephy.ac200, AC200_EPHY_CTL, value | (1 << 11));
++	} else
++#endif
++	if (ephy_type == EPHY_AC300) {
++		value = phy_read(ac300_ephy.ac300, 0x06);
++		if (phydev->interface == PHY_INTERFACE_MODE_RMII)
++			value |= (1 << 11);
++		else
++			value &= (~(1 << 11));
++		phy_write(ac300_ephy.ac300, 0x06, value | (1 << 1)); /*LED_POL 1:Low active*/
++	}
++
++#if defined(CONFIG_ARCH_SUN50IW6)
++	value = phy_read(phydev, 0x13);
++	value |= 1 << 12;
++	phy_write(phydev, 0x13, value);
++#endif
++
++	return 0;
++}
++EXPORT_SYMBOL(ephy_config_init);
++
++static int ephy_probe(struct phy_device *phydev)
++{
++	return 0;
++}
++
++#if 0
++static int ephy_ack_interrupt(struct phy_device *phydev)
++{
++	int err = phy_read(phydev, IP101A_G_IRQ_CONF_STATUS);
++
++	if (err < 0)
++		return err;
++
++	return 0;
++}
++#endif
++
++
++static struct phy_driver sunxi_phy_driver = {
++	.phy_id = 0x00441400,
++	.name = "ephy",
++	.phy_id_mask = 0x0ffffff0,
++	.features = PHY_BASIC_FEATURES, //| SUPPORTED_Pause |SUPPORTED_Asym_Pause,
++#if 0
++	.flags = PHY_HAS_INTERRUPT,
++	.ack_interrupt = ephy_ack_interrupt,
++#endif
++	.config_init = &ephy_config_init,
++	.config_aneg = &genphy_config_aneg,
++	.read_status = &genphy_read_status,
++	.suspend = genphy_suspend,
++	.resume = genphy_resume,
++	.probe = ephy_probe,
++};
++
++static void ac300_ephy_enable(struct ephy_res *priv)
++{
++	phy_write(priv->ac300, 0x00, 0x1f83); /* release reset */
++
++	phy_write(priv->ac300, 0x00, 0x1fb7); /* clk gating (24MHz clock)*/
++
++	//phy_write(priv->ac300, 0x05, 0xa81f);
++	phy_write(priv->ac300, 0x05, 0xa819);
++
++	phy_write(priv->ac300, 0x06, 0x00);
++
++	msleep(1000); /* FIXME: fix some board compatible issues. */
++
++	atomic_set(&ac300_ephy.ephy_en, 1);
++}
++
++static void ac300_ephy_disable(struct ephy_res *priv)
++{
++	phy_write(priv->ac300, 0x00, 0x1f40);
++	phy_write(priv->ac300, 0x05, 0xa800);
++
++	phy_write(priv->ac300, 0x06, 0x01);
++
++	atomic_set(&ac300_ephy.ephy_en, 0);
++}
++
++static int ac300_ephy_probe(struct phy_device *phydev)
++{
++	ac300_ephy.ac300 = phydev;
++
++	atomic_set(&ac300_ephy.ephy_en, 0);
++	ac300_ephy_enable(&ac300_ephy);
++
++	ephy_type = EPHY_AC300;
++
++	return 0;
++}
++
++static void ac300_ephy_shutdown(struct phy_device *phydev)
++{
++	ac300_ephy.ac300 = phydev;
++
++	phy_write(ac300_ephy.ac300, 0x00, 0x1f40);
++	phy_write(ac300_ephy.ac300, 0x05, 0xa800);
++	phy_write(ac300_ephy.ac300, 0x06, 0x01);
++}
++
++int gmac_ephy_shutdown(void)
++{
++	if (ephy_type == EPHY_AC300)
++		ac300_ephy_disable(&ac300_ephy);
++
++	return 0;
++}
++EXPORT_SYMBOL_GPL(gmac_ephy_shutdown);
++
++static int ac300_ephy_suspend(struct phy_device *phydev)
++{
++	ac300_ephy_disable(&ac300_ephy);
++
++	return 0;
++}
++
++static int ac300_ephy_resume(struct phy_device *phydev)
++{
++	ac300_ephy_enable(&ac300_ephy);
++
++	return 0;
++}
++
++static struct phy_driver ac300_ephy_driver = {
++	.phy_id = 0xc0000000,
++	.name = "ac300",
++	.phy_id_mask = 0xffffffff,
++	.suspend = ac300_ephy_suspend,
++	.resume = ac300_ephy_resume,
++	.probe = ac300_ephy_probe,
++	// .shutdown = ac300_ephy_shutdown,
++};
++
++
++static void ac200_ephy_enable(struct ephy_res *priv)
++{
++#if 1 //ifdef CONFIG_MFD_ACX00
++	int value;
++	unsigned char i = 0;
++#if 1 // defined(CONFIG_ARCH_SUN50IW6) || defined(CONFIG_ARCH_SUN50IW9)
++	u16 ephy_cali = 0;
++#endif
++
++	if (!ac200_enable()) {
++		for (i = 0; i < WAIT_MAX_COUNT; i++) {
++			msleep(10);
++			if (ac200_enable())
++			break;
++		}
++		if (i == WAIT_MAX_COUNT) {
++			pr_err("acx00 is no enable, and ac200_ephy_enable is fail\n");
++			return;
++		}
++	}
++
++	value = ac200_reg_read(priv->ac200, AC200_SYS_EPHY_CTL0);
++	value |= 0x03;
++	ac200_reg_write(priv->ac200, AC200_SYS_EPHY_CTL0, value);
++	value = ac200_reg_read(priv->ac200, AC200_SYS_EPHY_CTL1);
++
++	value |= 0x0f;
++
++	ac200_reg_write(priv->ac200, AC200_SYS_EPHY_CTL1, value);
++	ac200_reg_write(priv->ac200, AC200_EPHY_CTL, 0x06);
++
++	/*for ephy */
++	value = ac200_reg_read(priv->ac200, AC200_EPHY_CTL);
++	value &= ~(0xf << 12);
++
++#if 1 // defined(CONFIG_ARCH_SUN50IW6) || defined(CONFIG_ARCH_SUN50IW9)
++
++	ephy_cali = sun50i_ephy_calibrate_value();
++	value |= (0x0F & (0x03 + ephy_cali)) << 12;
++#else
++	value |= (0x0F & (0x03 + ac200_reg_read(priv->ac200, AC200_SID))) << 12;
++#endif
++
++	ac200_reg_write(priv->ac200, AC200_EPHY_CTL, value);
++
++	atomic_set(&ac200_ephy.ephy_en, 1);
++#endif
++}
++
++static void ac200_ephy_disable(struct ephy_res *priv)
++{
++	int value;
++
++	/* reset ephy */
++	value = ac200_reg_read(priv->ac200, AC200_SYS_EPHY_CTL0);
++	value &= ~0x01;
++	ac200_reg_write(priv->ac200, AC200_SYS_EPHY_CTL0, value);
++
++	/* shutdown ephy */
++	value = ac200_reg_read(priv->ac200, AC200_EPHY_CTL);
++	value |= 0x01;
++	ac200_reg_write(priv->ac200, AC200_EPHY_CTL, value);
++
++	atomic_set(&priv->ephy_en, 0);
++}
++
++static const struct platform_device_id ac200_ephy_id[] = {
++	{ "ac200-ephy", 0},
++	{ },
++};
++MODULE_DEVICE_TABLE(platform, ac200_ephy_id);
++
++static int ac200_ephy_probe(struct platform_device *pdev)
++{
++	struct ac200_dev *ax = dev_get_drvdata(pdev->dev.parent);
++
++	if (!ax)
++		return -ENODEV;
++
++	ac200_ephy.ac200 = ax;
++	ephy_type = EPHY_AC200;
++	platform_set_drvdata(pdev, &ac200_ephy);
++
++	atomic_set(&ac200_ephy.ephy_en, 0);
++	ac200_ephy_enable(&ac200_ephy);
++
++	return 0;
++}
++
++static void ac200_ephy_remove(struct platform_device *pdev)
++{
++	ac200_ephy_disable(&ac200_ephy);
++}
++
++static int ac200_ephy_suspend(struct device *dev)
++{
++	ac200_ephy_disable(&ac200_ephy);
++
++	return 0;
++}
++
++static int ac200_ephy_resume(struct device *dev)
++{
++	ac200_ephy_enable(&ac200_ephy);
++
++	return 0;
++}
++
++/* Suspend hook structures */
++static const struct dev_pm_ops ac200_ephy_pm_ops = {
++	.suspend = ac200_ephy_suspend,
++	.resume = ac200_ephy_resume,
++};
++
++static struct platform_driver ac200_ephy_driver = {
++	.driver = {
++		.name = "ac200-ephy-sunxi",
++		.owner = THIS_MODULE,
++		.pm = &ac200_ephy_pm_ops,
++	},
++	.probe = ac200_ephy_probe,
++	.remove = ac200_ephy_remove,
++	.id_table = ac200_ephy_id,
++};
++
++static int ephy_init(void)
++{
++	int ret = 0;
++
++	ret = platform_driver_register(&ac200_ephy_driver);
++	if (ret)
++		return ret;
++
++	ret = phy_driver_register(&ac300_ephy_driver, THIS_MODULE);
++	if (ret)
++		goto ac300_ephy_error;
++
++	ret = phy_driver_register(&sunxi_phy_driver, THIS_MODULE);
++	if (ret)
++		goto ephy_driver_error;
++
++	return ret;
++
++ephy_driver_error:
++	phy_driver_unregister(&ac300_ephy_driver);
++
++ac300_ephy_error:
++	platform_driver_unregister(&ac200_ephy_driver);
++
++	return ret;
++}
++
++static void ephy_exit(void)
++{
++	phy_driver_unregister(&sunxi_phy_driver);
++	phy_driver_unregister(&ac300_ephy_driver);
++	platform_driver_unregister(&ac200_ephy_driver);
++}
++
++module_init(ephy_init);
++module_exit(ephy_exit);
++
++static struct mdio_device_id __maybe_unused ephy_tbl[] = {
++	{ 0x00441400, 0x0ffffff0 },
++	{ }
++};
++
++MODULE_DEVICE_TABLE(mdio, ephy_tbl);
++
++MODULE_DESCRIPTION("Allwinner EPHY drivers");
++MODULE_AUTHOR("Sugar <shugeLinux@gmail.com>");
++MODULE_LICENSE("GPL");
+diff --git a/include/linux/mfd/ac200.h b/include/linux/mfd/ac200.h
+new file mode 100644
+index 000000000000..84d89cbfbd3d
+--- /dev/null
++++ b/include/linux/mfd/ac200.h
+@@ -0,0 +1,213 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++/*
++ * AC200 register list
++ *
++ * Copyright (C) 2019 Jernej Skrabec <jernej.skrabec@siol.net>
++ */
++
++#ifndef __LINUX_MFD_AC200_H
++#define __LINUX_MFD_AC200_H
++
++#include <linux/regmap.h>
++#include <linux/clk.h>
++
++/* interface registers (can be accessed from any page) */
++#define AC200_TWI_CHANGE_TO_RSB		0x3E
++#define AC200_TWI_PAD_DELAY		0xC4
++#define AC200_TWI_REG_ADDR_H		0xFE
++
++/* General registers */
++#define AC200_SYS_VERSION		0x0000
++#define AC200_SYS_CONTROL		0x0002
++#define AC200_SYS_IRQ_ENABLE		0x0004
++#define AC200_SYS_IRQ_STATUS		0x0006
++#define AC200_SYS_CLK_CTL		0x0008
++#define AC200_SYS_DLDO_OSC_CTL		0x000A
++#define AC200_SYS_PLL_CTL0		0x000C
++#define AC200_SYS_PLL_CTL1		0x000E
++#define AC200_SYS_AUDIO_CTL0		0x0010
++#define AC200_SYS_AUDIO_CTL1		0x0012
++#define AC200_SYS_EPHY_CTL0		0x0014
++#define AC200_SYS_EPHY_CTL1		0x0016
++#define AC200_SYS_TVE_CTL0		0x0018
++#define AC200_SYS_TVE_CTL1		0x001A
++
++/* Audio Codec registers */
++#define AC200_AC_SYS_CLK_CTL		0x2000
++#define AC200_SYS_MOD_RST		0x2002
++#define AC200_SYS_SAMP_CTL		0x2004
++#define AC200_I2S_CTL			0x2100
++#define AC200_I2S_CLK			0x2102
++#define AC200_I2S_FMT0			0x2104
++#define AC200_I2S_FMT1			0x2108
++#define AC200_I2S_MIX_SRC		0x2114
++#define AC200_I2S_MIX_GAIN		0x2116
++#define AC200_I2S_DACDAT_DVC		0x2118
++#define AC200_I2S_ADCDAT_DVC		0x211A
++#define AC200_AC_DAC_DPC		0x2200
++#define AC200_AC_DAC_MIX_SRC		0x2202
++#define AC200_AC_DAC_MIX_GAIN		0x2204
++#define AC200_DACA_OMIXER_CTRL		0x2220
++#define AC200_OMIXER_SR			0x2222
++#define AC200_LINEOUT_CTRL		0x2224
++#define AC200_AC_ADC_DPC		0x2300
++#define AC200_MBIAS_CTRL		0x2310
++#define AC200_ADC_MIC_CTRL		0x2320
++#define AC200_ADCMIXER_SR		0x2322
++#define AC200_ANALOG_TUNING0		0x232A
++#define AC200_ANALOG_TUNING1		0x232C
++#define AC200_AC_AGC_SEL		0x2480
++#define AC200_ADC_DAPLCTRL		0x2500
++#define AC200_ADC_DAPRCTRL		0x2502
++#define AC200_ADC_DAPLSTA		0x2504
++#define AC200_ADC_DAPRSTA		0x2506
++#define AC200_ADC_DAPLTL		0x2508
++#define AC200_ADC_DAPRTL		0x250A
++#define AC200_ADC_DAPLHAC		0x250C
++#define AC200_ADC_DAPLLAC		0x250E
++#define AC200_ADC_DAPRHAC		0x2510
++#define AC200_ADC_DAPRLAC		0x2512
++#define AC200_ADC_DAPLDT		0x2514
++#define AC200_ADC_DAPLAT		0x2516
++#define AC200_ADC_DAPRDT		0x2518
++#define AC200_ADC_DAPRAT		0x251A
++#define AC200_ADC_DAPNTH		0x251C
++#define AC200_ADC_DAPLHNAC		0x251E
++#define AC200_ADC_DAPLLNAC		0x2520
++#define AC200_ADC_DAPRHNAC		0x2522
++#define AC200_ADC_DAPRLNAC		0x2524
++#define AC200_AC_DAPHHPFC		0x2526
++#define AC200_AC_DAPLHPFC		0x2528
++#define AC200_AC_DAPOPT			0x252A
++#define AC200_AC_DAC_DAPCTRL		0x3000
++#define AC200_AC_DRC_HHPFC		0x3002
++#define AC200_AC_DRC_LHPFC		0x3004
++#define AC200_AC_DRC_CTRL		0x3006
++#define AC200_AC_DRC_LPFHAT		0x3008
++#define AC200_AC_DRC_LPFLAT		0x300A
++#define AC200_AC_DRC_RPFHAT		0x300C
++#define AC200_AC_DRC_RPFLAT		0x300E
++#define AC200_AC_DRC_LPFHRT		0x3010
++#define AC200_AC_DRC_LPFLRT		0x3012
++#define AC200_AC_DRC_RPFHRT		0x3014
++#define AC200_AC_DRC_RPFLRT		0x3016
++#define AC200_AC_DRC_LRMSHAT		0x3018
++#define AC200_AC_DRC_LRMSLAT		0x301A
++#define AC200_AC_DRC_RRMSHAT		0x301C
++#define AC200_AC_DRC_RRMSLAT		0x301E
++#define AC200_AC_DRC_HCT		0x3020
++#define AC200_AC_DRC_LCT		0x3022
++#define AC200_AC_DRC_HKC		0x3024
++#define AC200_AC_DRC_LKC		0x3026
++#define AC200_AC_DRC_HOPC		0x3028
++#define AC200_AC_DRC_LOPC		0x302A
++#define AC200_AC_DRC_HLT		0x302C
++#define AC200_AC_DRC_LLT		0x302E
++#define AC200_AC_DRC_HKI		0x3030
++#define AC200_AC_DRC_LKI		0x3032
++#define AC200_AC_DRC_HOPL		0x3034
++#define AC200_AC_DRC_LOPL		0x3036
++#define AC200_AC_DRC_HET		0x3038
++#define AC200_AC_DRC_LET		0x303A
++#define AC200_AC_DRC_HKE		0x303C
++#define AC200_AC_DRC_LKE		0x303E
++#define AC200_AC_DRC_HOPE		0x3040
++#define AC200_AC_DRC_LOPE		0x3042
++#define AC200_AC_DRC_HKN		0x3044
++#define AC200_AC_DRC_LKN		0x3046
++#define AC200_AC_DRC_SFHAT		0x3048
++#define AC200_AC_DRC_SFLAT		0x304A
++#define AC200_AC_DRC_SFHRT		0x304C
++#define AC200_AC_DRC_SFLRT		0x304E
++#define AC200_AC_DRC_MXGHS		0x3050
++#define AC200_AC_DRC_MXGLS		0x3052
++#define AC200_AC_DRC_MNGHS		0x3054
++#define AC200_AC_DRC_MNGLS		0x3056
++#define AC200_AC_DRC_EPSHC		0x3058
++#define AC200_AC_DRC_EPSLC		0x305A
++#define AC200_AC_DRC_HPFHGAIN		0x305E
++#define AC200_AC_DRC_HPFLGAIN		0x3060
++#define AC200_AC_DRC_BISTCR		0x3100
++#define AC200_AC_DRC_BISTST		0x3102
++
++/* TVE registers */
++#define AC200_TVE_CTL0			0x4000
++#define AC200_TVE_CTL1			0x4002
++#define AC200_TVE_MOD0			0x4004
++#define AC200_TVE_MOD1			0x4006
++#define AC200_TVE_DAC_CFG0		0x4008
++#define AC200_TVE_DAC_CFG1		0x400A
++#define AC200_TVE_YC_DELAY		0x400C
++#define AC200_TVE_YC_FILTER		0x400E
++#define AC200_TVE_BURST_FRQ0		0x4010
++#define AC200_TVE_BURST_FRQ1		0x4012
++#define AC200_TVE_FRONT_PORCH		0x4014
++#define AC200_TVE_BACK_PORCH		0x4016
++#define AC200_TVE_TOTAL_LINE		0x401C
++#define AC200_TVE_FIRST_ACTIVE		0x401E
++#define AC200_TVE_BLACK_LEVEL		0x4020
++#define AC200_TVE_BLANK_LEVEL		0x4022
++#define AC200_TVE_PLUG_EN		0x4030
++#define AC200_TVE_PLUG_IRQ_EN		0x4032
++#define AC200_TVE_PLUG_IRQ_STA		0x4034
++#define AC200_TVE_PLUG_STA		0x4038
++#define AC200_TVE_PLUG_DEBOUNCE		0x4040
++#define AC200_TVE_DAC_TEST		0x4042
++#define AC200_TVE_PLUG_PULSE_LEVEL	0x40F4
++#define AC200_TVE_PLUG_PULSE_START	0x40F8
++#define AC200_TVE_PLUG_PULSE_PERIOD	0x40FA
++#define AC200_TVE_IF_CTL		0x5000
++#define AC200_TVE_IF_TIM0		0x5008
++#define AC200_TVE_IF_TIM1		0x500A
++#define AC200_TVE_IF_TIM2		0x500C
++#define AC200_TVE_IF_TIM3		0x500E
++#define AC200_TVE_IF_SYNC0		0x5010
++#define AC200_TVE_IF_SYNC1		0x5012
++#define AC200_TVE_IF_SYNC2		0x5014
++#define AC200_TVE_IF_TIM4		0x5016
++#define AC200_TVE_IF_STATUS		0x5018
++
++/* EPHY registers */
++#define AC200_EPHY_CTL			0x6000
++#define AC200_EPHY_BIST			0x6002
++
++/* eFuse registers (0x8000 - 0x9FFF, layout unknown) */
++
++/* RTC registers */
++#define AC200_LOSC_CTRL0		0xA000
++#define AC200_LOSC_CTRL1		0xA002
++#define AC200_LOSC_AUTO_SWT_STA		0xA004
++#define AC200_INTOSC_CLK_PRESCAL	0xA008
++#define AC200_RTC_YY_MM_DD0		0xA010
++#define AC200_RTC_YY_MM_DD1		0xA012
++#define AC200_RTC_HH_MM_SS0		0xA014
++#define AC200_RTC_HH_MM_SS1		0xA016
++#define AC200_ALARM0_CUR_VLU0		0xA024
++#define AC200_ALARM0_CUR_VLU1		0xA026
++#define AC200_ALARM0_ENABLE		0xA028
++#define AC200_ALARM0_IRQ_EN		0xA02C
++#define AC200_ALARM0_IRQ_STA		0xA030
++#define AC200_ALARM1_WK_HH_MM_SS0	0xA040
++#define AC200_ALARM1_WK_HH_MM_SS1	0xA042
++#define AC200_ALARM1_ENABLE		0xA044
++#define AC200_ALARM1_IRQ_EN		0xA048
++#define AC200_ALARM1_IRQ_STA		0xA04C
++#define AC200_ALARM_CONFIG		0xA050
++#define AC200_LOSC_OUT_GATING		0xA060
++#define AC200_GP_DATA(x)		(0xA100 + (x) * 2)
++#define AC200_RTC_DEB			0xA170
++#define AC200_GPL_HOLD_OUTPUT		0xA180
++#define AC200_VDD_RTC			0xA190
++#define AC200_IC_CHARA0			0xA1F0
++#define AC200_IC_CHARA1			0xA1F2
++
++struct ac200_dev {
++	struct clk			*clk;
++	struct regmap			*regmap;
++	struct regmap_irq_chip_data	*regmap_irqc;
++};
++
++extern int ac200_enable(void);
++extern uint16_t sun50i_ephy_calibrate_value(void);
++
++#endif /* __LINUX_MFD_AC200_H */
+diff --git a/include/linux/of_gpio.h b/include/linux/of_gpio.h
+index d0f66a5e1b2a..71349cac1a67 100644
+--- a/include/linux/of_gpio.h
++++ b/include/linux/of_gpio.h
+@@ -15,6 +15,21 @@
+ #include <linux/gpio.h>		/* FIXME: Shouldn't be here */
+ #include <linux/of.h>
+ 
++/*
++ * This is Linux-specific flags. By default controllers' and Linux' mapping
++ * match, but GPIO controllers are free to translate their own flags to
++ * Linux-specific in their .xlate callback. Though, 1:1 mapping is recommended.
++ */
++enum of_gpio_flags {
++	OF_GPIO_ACTIVE_LOW = 0x1,
++	OF_GPIO_SINGLE_ENDED = 0x2,
++	OF_GPIO_OPEN_DRAIN = 0x4,
++	OF_GPIO_TRANSITORY = 0x8,
++	OF_GPIO_PULL_UP = 0x10,
++	OF_GPIO_PULL_DOWN = 0x20,
++	OF_GPIO_PULL_DISABLE = 0x40,
++};
++
+ struct device_node;
+ 
+ #ifdef CONFIG_OF_GPIO
+@@ -22,6 +37,9 @@ struct device_node;
+ extern int of_get_named_gpio(const struct device_node *np,
+ 			     const char *list_name, int index);
+ 
++extern int of_get_named_gpio_flags(const struct device_node *np,
++		const char *list_name, int index, enum of_gpio_flags *flags);
++
+ #else /* CONFIG_OF_GPIO */
+ 
+ #include <linux/errno.h>
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/drivers-devfreq-sun8i-a33-mbus-disable-autorefresh.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/drivers-devfreq-sun8i-a33-mbus-disable-autorefresh.patch
new file mode 100644
index 000000000000..2e27903b8612
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/drivers-devfreq-sun8i-a33-mbus-disable-autorefresh.patch
@@ -0,0 +1,27 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Gunjan Gupta <viraniac@gmail.com>
+Date: Tue, 5 Sep 2023 11:16:07 +0000
+Subject: drivers: devfreq: sun8i-a33-mbus: disable autorefresh
+
+---
+ drivers/devfreq/sun8i-a33-mbus.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/devfreq/sun8i-a33-mbus.c b/drivers/devfreq/sun8i-a33-mbus.c
+index 111111111111..222222222222 100644
+--- a/drivers/devfreq/sun8i-a33-mbus.c
++++ b/drivers/devfreq/sun8i-a33-mbus.c
+@@ -202,8 +202,8 @@ static int sun8i_a33_mbus_set_dram_freq(struct sun8i_a33_mbus *priv,
+ 	writel_relaxed(vtfcr, priv->reg_dram + DRAM_VTFCR);
+ 
+ 	/* Enable automatic self-refresh at the lowest frequency only. */
+-	if (freq == priv->freq_table[0])
+-		pwrctl |= DRAM_PWRCTL_SELFREF_EN;
++	// if (freq == priv->freq_table[0])
++	//	pwrctl |= DRAM_PWRCTL_SELFREF_EN;
+ 	writel_relaxed(pwrctl, priv->reg_dram + DRAM_PWRCTL);
+ 
+ 	sun8i_a33_mbus_restart_pmu_counters(priv);
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/drivers-pwm-Add-pwm-sunxi-enhance-driver-for-h616.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/drivers-pwm-Add-pwm-sunxi-enhance-driver-for-h616.patch
new file mode 100644
index 000000000000..462611b54ec7
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/drivers-pwm-Add-pwm-sunxi-enhance-driver-for-h616.patch
@@ -0,0 +1,1315 @@
+From d09971d1f6971b3035599d77bfcf4374084bb3d9 Mon Sep 17 00:00:00 2001
+From: chraac <chraac@gmail.com>
+Date: Thu, 15 Aug 2024 23:38:44 +0800
+Subject: drivers: pwm: Add pwm-sunxi-enhance driver for h616
+
+---
+ drivers/pwm/Kconfig             |    9 +
+ drivers/pwm/Makefile            |    1 +
+ drivers/pwm/pwm-sunxi-enhance.c | 1194 +++++++++++++++++++++++++++++++
+ drivers/pwm/pwm-sunxi-enhance.h |   60 ++
+ 4 files changed, 1264 insertions(+)
+ create mode 100644 drivers/pwm/pwm-sunxi-enhance.c
+ create mode 100644 drivers/pwm/pwm-sunxi-enhance.h
+
+diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
+index 0915c1e7df16..1f1ff7af5b5a 100644
+--- a/drivers/pwm/Kconfig
++++ b/drivers/pwm/Kconfig
+@@ -652,6 +652,15 @@ config PWM_SUN4I
+ 	  To compile this driver as a module, choose M here: the module
+ 	  will be called pwm-sun4i.
+ 
++config PWM_SUNXI_ENHANCE
++	tristate "Sunxi Enhance PWM support"
++	depends on PWM && ARCH_SUNXI
++	help
++	Enhance PWM framework driver for sunxi.
++
++	To compile this driver as a module, choose M here: the module
++	will be called pwm-sunxi.
++
+ config PWM_SUNPLUS
+ 	tristate "Sunplus PWM support"
+ 	depends on ARCH_SUNPLUS || COMPILE_TEST
+diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile
+index 9081e0c0e9e0..b729ae59db56 100644
+--- a/drivers/pwm/Makefile
++++ b/drivers/pwm/Makefile
+@@ -60,6 +60,7 @@ obj-$(CONFIG_PWM_STM32)		+= pwm-stm32.o
+ obj-$(CONFIG_PWM_STM32_LP)	+= pwm-stm32-lp.o
+ obj-$(CONFIG_PWM_STMPE)		+= pwm-stmpe.o
+ obj-$(CONFIG_PWM_SUN4I)		+= pwm-sun4i.o
++obj-$(CONFIG_PWM_SUNXI_ENHANCE)		+= pwm-sunxi-enhance.o
+ obj-$(CONFIG_PWM_SUNPLUS)	+= pwm-sunplus.o
+ obj-$(CONFIG_PWM_TEGRA)		+= pwm-tegra.o
+ obj-$(CONFIG_PWM_TIECAP)	+= pwm-tiecap.o
+diff --git a/drivers/pwm/pwm-sunxi-enhance.c b/drivers/pwm/pwm-sunxi-enhance.c
+new file mode 100644
+index 000000000000..6604c447b3b0
+--- /dev/null
++++ b/drivers/pwm/pwm-sunxi-enhance.c
+@@ -0,0 +1,1194 @@
++/*
++ * Allwinnertech pulse-width-modulation controller driver
++ *
++ * Copyright (C) 2015 AllWinner
++ *
++ *
++ * This file is licensed under the terms of the GNU General Public
++ * License version 2. This program is licensed "as is" without any
++ * warranty of any kind, whether express or implied.
++ */
++#include <linux/types.h>
++#include <linux/module.h>
++#include <linux/init.h>
++#include <linux/cdev.h>
++#include <linux/pwm.h>
++#include <linux/platform_device.h>
++#include <linux/slab.h>
++#include <linux/err.h>
++#include <linux/fs.h>
++#include <linux/device.h>
++#include <linux/gpio.h>
++#include <linux/pinctrl/pinconf.h>
++#include <linux/pinctrl/consumer.h>
++#include <linux/of_irq.h>
++#include <linux/of_address.h>
++#include <linux/of_iommu.h>
++#include <linux/of_device.h>
++#include <linux/of_platform.h>
++#include <linux/printk.h>
++#include <linux/io.h>
++#include <linux/clk.h>
++#include <linux/reset.h>
++#include "pwm-sunxi-enhance.h"
++
++#define PWM_NUM_MAX 4
++#define PWM_BIND_NUM 2
++#define PWM_PIN_STATE_ACTIVE "default"
++//#define PWM_PIN_STATE_SLEEP "sleep"
++
++#define SETMASK(width, shift) ((width ? ((-1U) >> (32 - width)) : 0) << (shift))
++#define CLRMASK(width, shift) (~(SETMASK(width, shift)))
++#define GET_BITS(shift, width, reg) \
++    (((reg)&SETMASK(width, shift)) >> (shift))
++#define SET_BITS(shift, width, reg, val) \
++    (((reg)&CLRMASK(width, shift)) | (val << (shift)))
++
++static int pwm_debug = 0;
++module_param(pwm_debug, int, 0644);
++MODULE_PARM_DESC(pwm_debug, "enable pwm debug");
++
++#define pwm_debug(fmt, ...) \
++    if (pwm_debug)          \
++    printk(KERN_WARNING pr_fmt(fmt), ##__VA_ARGS__)
++
++struct sunxi_pwm_config
++{
++    unsigned int dead_time;
++    unsigned int bind_pwm;
++
++    unsigned int clk_bypass_output;
++};
++
++struct sunxi_pwm_chip
++{
++    void __iomem *base;
++    struct sunxi_pwm_config *config;
++    struct clk *bus_clk;
++    struct clk *clk;
++    struct reset_control *pwm_rst_clk;
++};
++
++static inline struct sunxi_pwm_chip *to_sunxi_pwm_chip(struct pwm_chip *chip)
++{
++    return pwmchip_get_drvdata(chip);
++}
++
++static inline u32 sunxi_pwm_readl(struct pwm_chip *chip, u32 offset)
++{
++    struct sunxi_pwm_chip *pc = to_sunxi_pwm_chip(chip);
++    u32 value = 0;
++
++    value = readl(pc->base + offset);
++
++    return value;
++}
++
++static inline u32 sunxi_pwm_writel(struct pwm_chip *chip, u32 offset, u32 value)
++{
++    struct sunxi_pwm_chip *pc = to_sunxi_pwm_chip(chip);
++
++    writel(value, pc->base + offset);
++
++    return 0;
++}
++
++static int sunxi_pwm_pin_set_state(struct device *dev, char *name)
++{
++    struct pinctrl *pctl;
++    struct pinctrl_state *state;
++    int ret = -1;
++
++    pctl = devm_pinctrl_get(dev);
++    if (IS_ERR(pctl))
++    {
++        dev_err(dev, "pinctrl_get failed!\n");
++        ret = PTR_ERR(pctl);
++        goto exit;
++    }
++
++    state = pinctrl_lookup_state(pctl, name);
++    if (IS_ERR(state))
++    {
++        dev_err(dev, "pinctrl_lookup_state(%s) failed!\n", name);
++        ret = PTR_ERR(state);
++        goto exit;
++    }
++
++    ret = pinctrl_select_state(pctl, state);
++    if (ret < 0)
++    {
++        dev_err(dev, "pinctrl_select_state(%s) failed!\n", name);
++        goto exit;
++    }
++    ret = 0;
++
++exit:
++    return ret;
++}
++
++static int sunxi_pwm_get_config(struct platform_device *pdev, struct sunxi_pwm_config *config)
++{
++    struct device_node *np = pdev->dev.of_node;
++    int ret = 0;
++
++    /* read register config */
++    ret = of_property_read_u32(np, "bind_pwm", &config->bind_pwm);
++    if (ret < 0)
++    {
++        /*if there is no bind pwm,set 255, dual pwm invalid!*/
++        config->bind_pwm = 255;
++        ret = 0;
++    }
++
++    ret = of_property_read_u32(np, "dead_time", &config->dead_time);
++    if (ret < 0)
++    {
++        /*if there is  bind pwm, but not set dead time,set bind pwm 255,dual pwm invalid!*/
++        config->bind_pwm = 255;
++        ret = 0;
++    }
++
++    ret = of_property_read_u32(np, "clk_bypass_output", &config->clk_bypass_output);
++    if (ret < 0)
++    {
++        /*if use pwm as the internal clock source!*/
++        config->clk_bypass_output = 0;
++        ret = 0;
++    }
++
++    of_node_put(np);
++
++    return ret;
++}
++
++static int sunxi_pwm_set_polarity_single(struct pwm_chip *chip, struct pwm_device *pwm, enum pwm_polarity polarity)
++{
++    u32 temp;
++    unsigned int reg_offset, reg_shift, reg_width;
++    u32 sel = 0;
++
++    sel = pwm->hwpwm;
++    reg_offset = PWM_PCR_BASE + sel * 0x20;
++    reg_shift = PWM_ACT_STA_SHIFT;
++    reg_width = PWM_ACT_STA_WIDTH;
++    temp = sunxi_pwm_readl(chip, reg_offset);
++    if (polarity == PWM_POLARITY_NORMAL)
++        temp = SET_BITS(reg_shift, 1, temp, 1);
++    else
++        temp = SET_BITS(reg_shift, 1, temp, 0);
++
++    sunxi_pwm_writel(chip, reg_offset, temp);
++
++    return 0;
++}
++
++static int sunxi_pwm_set_polarity_dual(struct pwm_chip *chip, struct pwm_device *pwm, enum pwm_polarity polarity, int bind_num)
++{
++    u32 temp[2];
++    unsigned int reg_offset[2], reg_shift[2], reg_width[2];
++    u32 sel[2] = {0};
++
++    sel[0] = pwm->hwpwm;
++    sel[1] = bind_num - (int)chip->id;
++    /* config current pwm*/
++    reg_offset[0] = PWM_PCR_BASE + sel[0] * 0x20;
++    reg_shift[0] = PWM_ACT_STA_SHIFT;
++    reg_width[0] = PWM_ACT_STA_WIDTH;
++    temp[0] = sunxi_pwm_readl(chip, reg_offset[0]);
++    if (polarity == PWM_POLARITY_NORMAL)
++        temp[0] = SET_BITS(reg_shift[0], 1, temp[0], 1);
++    else
++        temp[0] = SET_BITS(reg_shift[0], 1, temp[0], 0);
++
++    /* config bind pwm*/
++    reg_offset[1] = PWM_PCR_BASE + sel[1] * 0x20;
++    reg_shift[1] = PWM_ACT_STA_SHIFT;
++    reg_width[1] = PWM_ACT_STA_WIDTH;
++    temp[1] = sunxi_pwm_readl(chip, reg_offset[1]);
++
++    /*bind pwm's polarity is reverse compare with the  current pwm*/
++    if (polarity == PWM_POLARITY_NORMAL)
++        temp[1] = SET_BITS(reg_shift[0], 1, temp[1], 0);
++    else
++        temp[1] = SET_BITS(reg_shift[0], 1, temp[1], 1);
++
++    /*config register at the same time*/
++    sunxi_pwm_writel(chip, reg_offset[0], temp[0]);
++    sunxi_pwm_writel(chip, reg_offset[1], temp[1]);
++
++    return 0;
++}
++
++static int sunxi_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm, enum pwm_polarity polarity)
++{
++    int bind_num;
++    struct sunxi_pwm_chip *pc = to_sunxi_pwm_chip(chip);
++
++    bind_num = pc->config[pwm->hwpwm].bind_pwm;
++    if (bind_num == 255)
++        sunxi_pwm_set_polarity_single(chip, pwm, polarity);
++    else
++        sunxi_pwm_set_polarity_dual(chip, pwm, polarity, bind_num);
++
++    return 0;
++}
++
++static u32 get_pccr_reg_offset(u32 sel, u32 *reg_offset)
++{
++    switch (sel)
++    {
++    case 0:
++    case 1:
++        *reg_offset = PWM_PCCR01;
++        break;
++    case 2:
++    case 3:
++        *reg_offset = PWM_PCCR23;
++        break;
++    case 4:
++    case 5:
++        *reg_offset = PWM_PCCR45;
++        break;
++    case 6:
++    case 7:
++        *reg_offset = PWM_PCCR67;
++        break;
++    case 8:
++        *reg_offset = PWM_PCCR8;
++        break;
++    default:
++        pr_err("%s:Not supported!\n", __func__);
++        break;
++    }
++    return 0;
++}
++
++static u32 get_pdzcr_reg_offset(u32 sel, u32 *reg_offset)
++{
++    switch (sel)
++    {
++    case 0:
++    case 1:
++        *reg_offset = PWM_PDZCR01;
++        break;
++    case 2:
++    case 3:
++        *reg_offset = PWM_PDZCR23;
++        break;
++    case 4:
++    case 5:
++        *reg_offset = PWM_PDZCR45;
++        break;
++    case 6:
++    case 7:
++        *reg_offset = PWM_PDZCR67;
++        break;
++    default:
++        pr_err("%s:Not supported!\n", __func__);
++        break;
++    }
++    return 0;
++}
++
++#define PRESCALE_MAX 256
++
++static int sunxi_pwm_config_single(struct pwm_chip *chip, struct pwm_device *pwm,
++                                   int duty_ns, int period_ns)
++{
++    unsigned int temp;
++    unsigned long long c = 0;
++    unsigned long entire_cycles = 256, active_cycles = 192;
++    struct sunxi_pwm_chip *pc = to_sunxi_pwm_chip(chip);
++    unsigned int reg_offset, reg_shift, reg_width;
++    unsigned int reg_bypass_shift;
++    unsigned int reg_clk_src_shift, reg_clk_src_width;
++    unsigned int reg_div_m_shift, reg_div_m_width;
++    unsigned int pre_scal_id = 0, div_m = 0, prescale = 0;
++    u32 sel = 0;
++    u32 pre_scal[][2] = {
++
++        /* reg_value  clk_pre_div */
++        {0, 1},
++        {1, 2},
++        {2, 4},
++        {3, 8},
++        {4, 16},
++        {5, 32},
++        {6, 64},
++        {7, 128},
++        {8, 256},
++    };
++
++    sel = pwm->hwpwm;
++
++    get_pccr_reg_offset(sel, &reg_offset);
++    if ((sel % 2) == 0)
++        reg_bypass_shift = 0x5;
++    else
++        reg_bypass_shift = 0x6;
++    /*src clk reg*/
++    reg_clk_src_shift = PWM_CLK_SRC_SHIFT;
++    reg_clk_src_width = PWM_CLK_SRC_WIDTH;
++
++    if (period_ns > 0 && period_ns <= 10)
++    {
++        /* if freq lt 100M, then direct output 100M clock,set by pass. */
++        c = 100000000;
++        /*bypass reg*/
++        temp = sunxi_pwm_readl(chip, reg_offset);
++        temp = SET_BITS(reg_bypass_shift, 1, temp, 1);
++        sunxi_pwm_writel(chip, reg_offset, temp);
++
++        /*clk_src_reg*/
++        temp = sunxi_pwm_readl(chip, reg_offset);
++        temp = SET_BITS(reg_clk_src_shift, reg_clk_src_width, temp, 1);
++        sunxi_pwm_writel(chip, reg_offset, temp);
++
++        return 0;
++    }
++    else if (period_ns > 10 && period_ns <= 334)
++    {
++        /* if freq between 3M~100M, then select 100M as clock */
++        c = 100000000;
++        /*set clk bypass_output reg to 1 when pwm is used as the internal clock source.*/
++        if (pc->config[pwm->hwpwm].clk_bypass_output == 1) {
++            temp = sunxi_pwm_readl(chip, reg_offset);
++            temp = SET_BITS(reg_bypass_shift, 1, temp, 1);
++            sunxi_pwm_writel(chip, reg_offset, temp);
++        }
++        /*clk_src_reg*/
++        temp = sunxi_pwm_readl(chip, reg_offset);
++        temp = SET_BITS(reg_clk_src_shift, reg_clk_src_width, temp, 1);
++        sunxi_pwm_writel(chip, reg_offset, temp);
++    }
++    else if (period_ns > 334)
++    {
++        /* if freq < 3M, then select 24M clock */
++        c = 24000000;
++        /*set clk bypass_output reg to 1 when pwm is used as the internal clock source.*/
++        if (pc->config[pwm->hwpwm].clk_bypass_output == 1) {
++            temp = sunxi_pwm_readl(chip, reg_offset);
++            temp = SET_BITS(reg_bypass_shift, 1, temp, 1);
++            sunxi_pwm_writel(chip, reg_offset, temp);
++        }
++        /*clk_src_reg*/
++        temp = sunxi_pwm_readl(chip, reg_offset);
++        temp = SET_BITS(reg_clk_src_shift, reg_clk_src_width, temp, 0);
++        sunxi_pwm_writel(chip, reg_offset, temp);
++    }
++    pwm_debug("duty_ns=%d period_ns=%d c =%llu.\n", duty_ns, period_ns, c);
++
++    c = c * period_ns;
++    do_div(c, 1000000000);
++    entire_cycles = (unsigned long)c;
++
++    for (pre_scal_id = 0; pre_scal_id < 9; pre_scal_id++)
++    {
++        if (entire_cycles <= 65536)
++            break;
++        for (prescale = 0; prescale < PRESCALE_MAX + 1; prescale++)
++        {
++            entire_cycles = ((unsigned long)c / pre_scal[pre_scal_id][1]) / (prescale + 1);
++            if (entire_cycles <= 65536)
++            {
++                div_m = pre_scal[pre_scal_id][0];
++                break;
++            }
++        }
++    }
++
++    c = (unsigned long long)entire_cycles * duty_ns;
++    do_div(c, period_ns);
++    active_cycles = c;
++    if (entire_cycles == 0)
++        entire_cycles++;
++
++    /* config  clk div_m*/
++    reg_div_m_shift = PWM_DIV_M_SHIFT;
++    reg_div_m_width = PWM_DIV_M_WIDTH;
++    temp = sunxi_pwm_readl(chip, reg_offset);
++    temp = SET_BITS(reg_div_m_shift, reg_div_m_width, temp, div_m);
++    sunxi_pwm_writel(chip, reg_offset, temp);
++
++    /* config prescal */
++    reg_offset = PWM_PCR_BASE + 0x20 * sel;
++    reg_shift = PWM_PRESCAL_SHIFT;
++    reg_width = PWM_PRESCAL_WIDTH;
++    temp = sunxi_pwm_readl(chip, reg_offset);
++    temp = SET_BITS(reg_shift, reg_width, temp, prescale);
++    sunxi_pwm_writel(chip, reg_offset, temp);
++
++    /* config active cycles */
++    reg_offset = PWM_PPR_BASE + 0x20 * sel;
++    reg_shift = PWM_ACT_CYCLES_SHIFT;
++    reg_width = PWM_ACT_CYCLES_WIDTH;
++    temp = sunxi_pwm_readl(chip, reg_offset);
++    temp = SET_BITS(reg_shift, reg_width, temp, active_cycles);
++    sunxi_pwm_writel(chip, reg_offset, temp);
++
++    /* config period cycles */
++    reg_offset = PWM_PPR_BASE + 0x20 * sel;
++    reg_shift = PWM_PERIOD_CYCLES_SHIFT;
++    reg_width = PWM_PERIOD_CYCLES_WIDTH;
++    temp = sunxi_pwm_readl(chip, reg_offset);
++    temp = SET_BITS(reg_shift, reg_width, temp, (entire_cycles - 1));
++
++    sunxi_pwm_writel(chip, reg_offset, temp);
++
++    pwm_debug("active_cycles=%lu entire_cycles=%lu prescale=%u div_m=%u\n",
++              active_cycles, entire_cycles, prescale, div_m);
++    return 0;
++}
++
++static int sunxi_pwm_config_dual(struct pwm_chip *chip, struct pwm_device *pwm,
++                                 int duty_ns, int period_ns, int bind_num)
++{
++    u32 value[2] = {0};
++    unsigned int temp;
++    unsigned long long c = 0, clk = 0, clk_temp = 0;
++    unsigned long entire_cycles = 256, active_cycles = 192;
++    unsigned int reg_offset[2], reg_shift[2], reg_width[2];
++    unsigned int reg_bypass_shift;
++    unsigned int reg_dz_en_offset[2], reg_dz_en_shift[2], reg_dz_en_width[2];
++    unsigned int pre_scal_id = 0, div_m = 0, prescale = 0;
++    int src_clk_sel = 0;
++    int i = 0;
++    unsigned int dead_time = 0, duty = 0;
++    u32 pre_scal[][2] = {
++
++        /* reg_value  clk_pre_div */
++        {0, 1},
++        {1, 2},
++        {2, 4},
++        {3, 8},
++        {4, 16},
++        {5, 32},
++        {6, 64},
++        {7, 128},
++        {8, 256},
++    };
++    unsigned int pwm_index[2] = {0};
++    struct sunxi_pwm_chip *pc = to_sunxi_pwm_chip(chip);
++
++    pwm_index[0] = pwm->hwpwm;
++    pwm_index[1] = bind_num - (int)chip->id;
++
++    /* if duty time < dead time,it is wrong. */
++    dead_time = pc->config[pwm_index[0]].dead_time;
++    duty = (unsigned int)duty_ns;
++    /* judge if the pwm eanble dead zone */
++    get_pdzcr_reg_offset(pwm_index[0], &reg_dz_en_offset[0]);
++    reg_dz_en_shift[0] = PWM_DZ_EN_SHIFT;
++    reg_dz_en_width[0] = PWM_DZ_EN_WIDTH;
++
++    value[0] = sunxi_pwm_readl(chip, reg_dz_en_offset[0]);
++    value[0] = SET_BITS(reg_dz_en_shift[0], reg_dz_en_width[0], value[0], 1);
++    sunxi_pwm_writel(chip, reg_dz_en_offset[0], value[0]);
++    temp = sunxi_pwm_readl(chip, reg_dz_en_offset[0]);
++    temp &= (1u << reg_dz_en_shift[0]);
++    if (duty < dead_time || temp == 0)
++    {
++        pr_err("[PWM]duty time or dead zone error.\n");
++        return -EINVAL;
++    }
++
++    for (i = 0; i < PWM_BIND_NUM; i++)
++    {
++        if ((i % 2) == 0)
++            reg_bypass_shift = 0x5;
++        else
++            reg_bypass_shift = 0x6;
++        get_pccr_reg_offset(pwm_index[i], &reg_offset[i]);
++        reg_shift[i] = reg_bypass_shift;
++        reg_width[i] = PWM_BYPASS_WIDTH;
++    }
++
++    if (period_ns > 0 && period_ns <= 10)
++    {
++        /* if freq lt 100M, then direct output 100M clock,set by pass */
++        clk = 100000000;
++        src_clk_sel = 1;
++
++        /* config the two pwm bypass */
++        for (i = 0; i < PWM_BIND_NUM; i++)
++        {
++            temp = sunxi_pwm_readl(chip, reg_offset[i]);
++            temp = SET_BITS(reg_shift[i], reg_width[i], temp, 1);
++            sunxi_pwm_writel(chip, reg_offset[i], temp);
++
++            reg_shift[i] = PWM_CLK_SRC_SHIFT;
++            reg_width[i] = PWM_CLK_SRC_WIDTH;
++            temp = sunxi_pwm_readl(chip, reg_offset[i]);
++            temp = SET_BITS(reg_shift[i], reg_width[i], temp, 1);
++            sunxi_pwm_writel(chip, reg_offset[i], temp);
++        }
++
++        return 0;
++    }
++    else if (period_ns > 10 && period_ns <= 334)
++    {
++        clk = 100000000;
++        src_clk_sel = 1;
++    }
++    else if (period_ns > 334)
++    {
++        /* if freq < 3M, then select 24M clock */
++        clk = 24000000;
++        src_clk_sel = 0;
++    }
++
++    for (i = 0; i < PWM_BIND_NUM; i++)
++    {
++        reg_shift[i] = PWM_CLK_SRC_SHIFT;
++        reg_width[i] = PWM_CLK_SRC_WIDTH;
++
++        temp = sunxi_pwm_readl(chip, reg_offset[i]);
++        temp = SET_BITS(reg_shift[i], reg_width[i], temp, src_clk_sel);
++        sunxi_pwm_writel(chip, reg_offset[i], temp);
++    }
++
++    c = clk;
++    c *= period_ns;
++    do_div(c, 1000000000);
++    entire_cycles = (unsigned long)c;
++
++    /* get div_m and prescale,which satisfy: deat_val <= 256, entire <= 65536 */
++    for (pre_scal_id = 0; pre_scal_id < 9; pre_scal_id++)
++    {
++        for (prescale = 0; prescale < PRESCALE_MAX + 1; prescale++)
++        {
++            entire_cycles = ((unsigned long)c / pre_scal[pre_scal_id][1]) / (prescale + 1);
++            clk_temp = clk;
++            do_div(clk_temp, pre_scal[pre_scal_id][1] * (prescale + 1));
++            clk_temp *= dead_time;
++            do_div(clk_temp, 1000000000);
++            if (entire_cycles <= 65536 && clk_temp <= 256)
++            {
++                div_m = pre_scal[pre_scal_id][0];
++                break;
++            }
++        }
++        if (entire_cycles <= 65536 && clk_temp <= 256)
++            break;
++        else
++        {
++            pr_err("%s:config dual err.entire_cycles=%lu, dead_zone_val=%llu",
++                   __func__, entire_cycles, clk_temp);
++            return -EINVAL;
++        }
++    }
++
++    c = (unsigned long long)entire_cycles * duty_ns;
++    do_div(c, period_ns);
++    active_cycles = c;
++    if (entire_cycles == 0)
++        entire_cycles++;
++
++    /* config  clk div_m*/
++    for (i = 0; i < PWM_BIND_NUM; i++)
++    {
++        reg_shift[i] = PWM_DIV_M_SHIFT;
++        reg_width[i] = PWM_DIV_M_SHIFT;
++        temp = sunxi_pwm_readl(chip, reg_offset[i]);
++        temp = SET_BITS(reg_shift[i], reg_width[i], temp, div_m);
++        sunxi_pwm_writel(chip, reg_offset[i], temp);
++    }
++
++    /* config prescal */
++    for (i = 0; i < PWM_BIND_NUM; i++)
++    {
++        reg_offset[i] = PWM_PCR_BASE + 0x20 * pwm_index[i];
++        reg_shift[i] = PWM_PRESCAL_SHIFT;
++        reg_width[i] = PWM_PRESCAL_WIDTH;
++        temp = sunxi_pwm_readl(chip, reg_offset[i]);
++        temp = SET_BITS(reg_shift[i], reg_width[i], temp, prescale);
++        sunxi_pwm_writel(chip, reg_offset[i], temp);
++    }
++
++    /* config active cycles */
++    for (i = 0; i < PWM_BIND_NUM; i++)
++    {
++        reg_offset[i] = PWM_PPR_BASE + 0x20 * pwm_index[i];
++        reg_shift[i] = PWM_ACT_CYCLES_SHIFT;
++        reg_width[i] = PWM_ACT_CYCLES_WIDTH;
++        temp = sunxi_pwm_readl(chip, reg_offset[i]);
++        temp = SET_BITS(reg_shift[i], reg_width[i], temp, active_cycles);
++        sunxi_pwm_writel(chip, reg_offset[i], temp);
++    }
++
++    /* config period cycles */
++    for (i = 0; i < PWM_BIND_NUM; i++)
++    {
++        reg_offset[i] = PWM_PPR_BASE + 0x20 * pwm_index[i];
++        reg_shift[i] = PWM_PERIOD_CYCLES_SHIFT;
++        reg_width[i] = PWM_PERIOD_CYCLES_WIDTH;
++        temp = sunxi_pwm_readl(chip, reg_offset[i]);
++        temp = SET_BITS(reg_shift[i], reg_width[i], temp, (entire_cycles - 1));
++        sunxi_pwm_writel(chip, reg_offset[i], temp);
++    }
++
++    pwm_debug("active_cycles=%lu entire_cycles=%lu prescale=%u div_m=%u\n",
++              active_cycles, entire_cycles, prescale, div_m);
++
++    /* config dead zone, one config for two pwm */
++    reg_offset[0] = reg_dz_en_offset[0];
++    reg_shift[0] = PWM_PDZINTV_SHIFT;
++    reg_width[0] = PWM_PDZINTV_WIDTH;
++    temp = sunxi_pwm_readl(chip, reg_offset[0]);
++    temp = SET_BITS(reg_shift[0], reg_width[0], temp, (unsigned int)clk_temp);
++    sunxi_pwm_writel(chip, reg_offset[0], temp);
++
++    return 0;
++}
++
++static int sunxi_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
++                            int duty_ns, int period_ns)
++{
++    int bind_num;
++
++    struct sunxi_pwm_chip *pc = to_sunxi_pwm_chip(chip);
++
++    bind_num = pc->config[pwm->hwpwm].bind_pwm;
++    if (bind_num == 255) {
++        sunxi_pwm_config_single(chip, pwm, duty_ns, period_ns);
++    }
++    else {
++        sunxi_pwm_config_dual(chip, pwm, duty_ns, period_ns, bind_num);
++    }
++
++    return 0;
++}
++
++static int sunxi_pwm_enable_single(struct pwm_chip *chip, struct pwm_device *pwm)
++{
++    unsigned int value = 0, index = 0;
++    unsigned int reg_offset, reg_shift;
++    struct device_node *sub_np;
++    struct platform_device *pwm_pdevice;
++    int ret;
++
++    index = pwm->hwpwm;
++    sub_np = of_parse_phandle(pwmchip_parent(chip)->of_node, "sunxi-pwms", index);
++    if (IS_ERR_OR_NULL(sub_np))
++    {
++        pr_err("%s: can't parse \"sunxi-pwms\" property\n", __func__);
++        return -ENODEV;
++    }
++    pwm_pdevice = of_find_device_by_node(sub_np);
++    if (IS_ERR_OR_NULL(pwm_pdevice))
++    {
++        pr_err("%s: can't parse pwm device\n", __func__);
++        return -ENODEV;
++    }
++    ret = sunxi_pwm_pin_set_state(&pwm_pdevice->dev, PWM_PIN_STATE_ACTIVE);
++    if (ret != 0)
++        return ret;
++
++    /* enable clk for pwm controller */
++    get_pccr_reg_offset(index, &reg_offset);
++    reg_shift = PWM_CLK_GATING_SHIFT;
++    value = sunxi_pwm_readl(chip, reg_offset);
++    value = SET_BITS(reg_shift, 1, value, 1);
++    sunxi_pwm_writel(chip, reg_offset, value);
++
++    /* enable pwm controller */
++    reg_offset = PWM_PER;
++    reg_shift = index;
++    value = sunxi_pwm_readl(chip, reg_offset);
++    value = SET_BITS(reg_shift, 1, value, 1);
++    sunxi_pwm_writel(chip, reg_offset, value);
++
++    return 0;
++}
++
++static int sunxi_pwm_enable_dual(struct pwm_chip *chip, struct pwm_device *pwm, int bind_num)
++{
++    u32 value[2] = {0};
++    unsigned int reg_offset[2], reg_shift[2], reg_width[2];
++    struct device_node *sub_np[2];
++    struct platform_device *pwm_pdevice[2];
++    int i = 0, ret = 0;
++    unsigned int pwm_index[2] = {0};
++
++    pwm_index[0] = pwm->hwpwm;
++    pwm_index[1] = bind_num - (int)chip->id;
++
++    /*set current pwm pin state*/
++    sub_np[0] = of_parse_phandle(pwmchip_parent(chip)->of_node, "sunxi-pwms", pwm_index[0]);
++    if (IS_ERR_OR_NULL(sub_np[0]))
++    {
++        pr_err("%s: can't parse \"sunxi-pwms\" property\n", __func__);
++        return -ENODEV;
++    }
++    pwm_pdevice[0] = of_find_device_by_node(sub_np[0]);
++    if (IS_ERR_OR_NULL(pwm_pdevice[0]))
++    {
++        pr_err("%s: can't parse pwm device\n", __func__);
++        return -ENODEV;
++    }
++
++    /*set bind pwm pin state*/
++    sub_np[1] = of_parse_phandle(pwmchip_parent(chip)->of_node, "sunxi-pwms", pwm_index[1]);
++    if (IS_ERR_OR_NULL(sub_np[1]))
++    {
++        pr_err("%s: can't parse \"sunxi-pwms\" property\n", __func__);
++        return -ENODEV;
++    }
++    pwm_pdevice[1] = of_find_device_by_node(sub_np[1]);
++    if (IS_ERR_OR_NULL(pwm_pdevice[1]))
++    {
++        pr_err("%s: can't parse pwm device\n", __func__);
++        return -ENODEV;
++    }
++
++    ret = sunxi_pwm_pin_set_state(&pwm_pdevice[0]->dev, PWM_PIN_STATE_ACTIVE);
++    if (ret != 0)
++        return ret;
++    ret = sunxi_pwm_pin_set_state(&pwm_pdevice[1]->dev, PWM_PIN_STATE_ACTIVE);
++    if (ret != 0)
++        return ret;
++
++    /* enable clk for pwm controller */
++    for (i = 0; i < PWM_BIND_NUM; i++)
++    {
++        get_pccr_reg_offset(pwm_index[i], &reg_offset[i]);
++        reg_shift[i] = PWM_CLK_GATING_SHIFT;
++        reg_width[i] = PWM_CLK_GATING_WIDTH;
++        value[i] = sunxi_pwm_readl(chip, reg_offset[i]);
++        value[i] = SET_BITS(reg_shift[i], reg_width[i], value[i], 1);
++        sunxi_pwm_writel(chip, reg_offset[i], value[i]);
++    }
++
++    /* enable pwm controller */
++    for (i = 0; i < PWM_BIND_NUM; i++)
++    {
++        reg_offset[i] = PWM_PER;
++        reg_shift[i] = pwm_index[i];
++        reg_width[i] = 0x1;
++        value[i] = sunxi_pwm_readl(chip, reg_offset[i]);
++        value[i] = SET_BITS(reg_shift[i], reg_width[i], value[i], 1);
++        sunxi_pwm_writel(chip, reg_offset[i], value[i]);
++    }
++
++    return 0;
++}
++
++static int sunxi_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
++{
++    int bind_num;
++    int ret = 0;
++    struct sunxi_pwm_chip *pc = to_sunxi_pwm_chip(chip);
++
++    bind_num = pc->config[pwm->hwpwm].bind_pwm;
++    if (bind_num == 255)
++        ret = sunxi_pwm_enable_single(chip, pwm);
++    else
++        ret = sunxi_pwm_enable_dual(chip, pwm, bind_num);
++
++    sunxi_pwm_set_polarity(chip, pwm, PWM_POLARITY_NORMAL);
++
++    return ret;
++}
++
++static void sunxi_pwm_disable_single(struct pwm_chip *chip, struct pwm_device *pwm)
++{
++    u32 value = 0, index = 0;
++    unsigned int reg_offset, reg_shift, reg_width;
++    struct device_node *sub_np;
++    struct platform_device *pwm_pdevice;
++
++    index = pwm->hwpwm;
++    sub_np = of_parse_phandle(pwmchip_parent(chip)->of_node, "sunxi-pwms", index);
++    if (IS_ERR_OR_NULL(sub_np))
++    {
++        pr_err("%s: can't parse \"sunxi-pwms\" property\n", __func__);
++        return;
++    }
++    pwm_pdevice = of_find_device_by_node(sub_np);
++    if (IS_ERR_OR_NULL(pwm_pdevice))
++    {
++        pr_err("%s: can't parse pwm device\n", __func__);
++        return;
++    }
++
++    /* disable pwm controller */
++    reg_offset = PWM_PER;
++    reg_shift = index;
++    reg_width = 0x1;
++    value = sunxi_pwm_readl(chip, reg_offset);
++    value = SET_BITS(reg_shift, reg_width, value, 0);
++    sunxi_pwm_writel(chip, reg_offset, value);
++
++    /*
++     * 0 , 1 --> 0
++     * 2 , 3 --> 2
++     * 4 , 5 --> 4
++     * 6 , 7 --> 6
++     */
++    reg_shift &= ~(1);
++
++    if (GET_BITS(reg_shift, 2, value) == 0)
++    {
++        /* disable clk for pwm controller. */
++        get_pccr_reg_offset(index, &reg_offset);
++        reg_shift = PWM_CLK_GATING_SHIFT;
++        reg_width = 0x1;
++        value = sunxi_pwm_readl(chip, reg_offset);
++        value = SET_BITS(reg_shift, reg_width, value, 0);
++        sunxi_pwm_writel(chip, reg_offset, value);
++    }
++
++    // sunxi_pwm_pin_set_state(&pwm_pdevice->dev, PWM_PIN_STATE_SLEEP);
++}
++
++static void sunxi_pwm_disable_dual(struct pwm_chip *chip, struct pwm_device *pwm, int bind_num)
++{
++    u32 value[2] = {0};
++    unsigned int reg_offset[2], reg_shift[2], reg_width[2];
++    struct device_node *sub_np[2];
++    struct platform_device *pwm_pdevice[2];
++    int i = 0;
++    unsigned int pwm_index[2] = {0};
++
++    pwm_index[0] = pwm->hwpwm;
++    pwm_index[1] = bind_num - (int)chip->id;
++
++    /* get current index pwm device */
++    sub_np[0] = of_parse_phandle(pwmchip_parent(chip)->of_node, "pwms", pwm_index[0]);
++    if (IS_ERR_OR_NULL(sub_np[0]))
++    {
++        pr_err("%s: can't parse \"pwms\" property\n", __func__);
++        return;
++    }
++    pwm_pdevice[0] = of_find_device_by_node(sub_np[0]);
++    if (IS_ERR_OR_NULL(pwm_pdevice[0]))
++    {
++        pr_err("%s: can't parse pwm device\n", __func__);
++        return;
++    }
++    /* get bind pwm device */
++    sub_np[1] = of_parse_phandle(pwmchip_parent(chip)->of_node, "pwms", pwm_index[1]);
++    if (IS_ERR_OR_NULL(sub_np[1]))
++    {
++        pr_err("%s: can't parse \"pwms\" property\n", __func__);
++        return;
++    }
++    pwm_pdevice[1] = of_find_device_by_node(sub_np[1]);
++    if (IS_ERR_OR_NULL(pwm_pdevice[1]))
++    {
++        pr_err("%s: can't parse pwm device\n", __func__);
++        return;
++    }
++
++    /* disable pwm controller */
++    for (i = 0; i < PWM_BIND_NUM; i++)
++    {
++        reg_offset[i] = PWM_PER;
++        reg_shift[i] = pwm_index[i];
++        reg_width[i] = 0x1;
++        value[i] = sunxi_pwm_readl(chip, reg_offset[i]);
++        value[i] = SET_BITS(reg_shift[i], reg_width[i], value[i], 0);
++        sunxi_pwm_writel(chip, reg_offset[i], value[i]);
++    }
++
++    /* disable pwm clk gating */
++    for (i = 0; i < PWM_BIND_NUM; i++)
++    {
++        get_pccr_reg_offset(pwm_index[i], &reg_offset[i]);
++        reg_shift[i] = PWM_CLK_GATING_SHIFT;
++        reg_width[i] = 0x1;
++        value[i] = sunxi_pwm_readl(chip, reg_offset[i]);
++        value[i] = SET_BITS(reg_shift[i], reg_width[i], value[i], 0);
++        sunxi_pwm_writel(chip, reg_offset[i], value[i]);
++    }
++
++    /* disable pwm dead zone,one for the two pwm */
++    get_pdzcr_reg_offset(pwm_index[0], &reg_offset[0]);
++    reg_shift[0] = PWM_DZ_EN_SHIFT;
++    reg_width[0] = PWM_DZ_EN_WIDTH;
++    value[0] = sunxi_pwm_readl(chip, reg_offset[0]);
++    value[0] = SET_BITS(reg_shift[0], reg_width[0], value[0], 0);
++    sunxi_pwm_writel(chip, reg_offset[0], value[0]);
++
++    /* config pin sleep */
++    // sunxi_pwm_pin_set_state(&pwm_pdevice[0]->dev, PWM_PIN_STATE_SLEEP);
++    // sunxi_pwm_pin_set_state(&pwm_pdevice[1]->dev, PWM_PIN_STATE_SLEEP);
++}
++
++static void sunxi_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
++{
++    int bind_num;
++    struct sunxi_pwm_chip *pc = to_sunxi_pwm_chip(chip);
++
++    bind_num = pc->config[pwm->hwpwm].bind_pwm;
++    if (bind_num == 255)
++        sunxi_pwm_disable_single(chip, pwm);
++    else
++        sunxi_pwm_disable_dual(chip, pwm, bind_num);
++}
++
++static int sunxi_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
++			    const struct pwm_state *state)
++{
++	int err;
++	bool enabled = pwm->state.enabled;
++
++	if (state->polarity != pwm->state.polarity) {
++		/*
++		 * Changing the polarity of a running PWM is only allowed when
++		 * the PWM driver implements ->apply().
++		 */
++		if (enabled) {
++			sunxi_pwm_disable(chip, pwm);
++
++			enabled = false;
++		}
++
++		err = sunxi_pwm_set_polarity(chip, pwm, state->polarity);
++		if (err)
++			return err;
++	}
++
++
++	if (!state->enabled) {
++		if (enabled) {
++			sunxi_pwm_disable(chip, pwm);
++        }
++
++		return 0;
++	}
++
++	/*
++	 * We cannot skip calling ->config even if state->period ==
++	 * pwm->state.period && state->duty_cycle == pwm->state.duty_cycle
++	 * because we might have exited early in the last call to
++	 * pwm_apply_state because of !state->enabled and so the two values in
++	 * pwm->state might not be configured in hardware.
++	 */
++	err = sunxi_pwm_config(pwm->chip, pwm, state->duty_cycle, state->period);
++	if (err) {
++		return err;
++    }
++
++	if (!enabled)
++		err = sunxi_pwm_enable(chip, pwm);
++
++	return err;
++}
++
++static const struct pwm_ops sunxi_pwm_ops = {
++	.apply = sunxi_pwm_apply,
++};
++
++static int sunxi_pwm_probe(struct platform_device *pdev)
++{
++    int ret;
++    unsigned int npwm;
++    struct pwm_chip *chip;
++    struct sunxi_pwm_chip *pwm;
++    struct device_node *np = pdev->dev.of_node;
++    int i;
++    struct platform_device *pwm_pdevice;
++    struct device_node *sub_np;
++
++    /* read property pwm-number */
++    ret = of_property_read_u32(np, "pwm-number", &npwm);
++    if (ret < 0)
++    {
++        dev_err(&pdev->dev, "failed to get pwm number: %d, force to one!\n", ret);
++        /* force to one pwm if read property fail */
++        npwm = 1;
++    }
++
++    chip = devm_pwmchip_alloc(&pdev->dev, npwm, sizeof(*pwm));
++    if (IS_ERR(chip)) {
++        return PTR_ERR(chip);
++    }
++
++    pwm = to_sunxi_pwm_chip(chip);
++
++    /* io map pwm base */
++    pwm->base = (void __iomem *)of_iomap(pdev->dev.of_node, 0);
++    if (!pwm->base)
++    {
++        dev_err(&pdev->dev, "unable to map pwm registers\n");
++        ret = -EINVAL;
++        goto err_iomap;
++    }
++
++    /* read property pwm-base */
++    ret = of_property_read_u32(np, "pwm-base", &chip->id);
++    if (ret < 0)
++    {
++        dev_err(&pdev->dev, "failed to get pwm-base: %d, force to -1 !\n", ret);
++        /* force to one pwm if read property fail */
++        chip->id = -1;
++    }
++
++    chip->dev.parent = &pdev->dev;
++    chip->ops = &sunxi_pwm_ops;
++
++    /* add pwm chip to pwm-core */
++    ret = pwmchip_add(chip);
++    if (ret < 0)
++    {
++        dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
++        goto err_add;
++    }
++    platform_set_drvdata(pdev, chip);
++
++    pwm->config = devm_kzalloc(&pdev->dev, sizeof(*pwm->config) * npwm, GFP_KERNEL);
++    if (!pwm->config)
++    {
++        dev_err(&pdev->dev, "failed to allocate memory!\n");
++        goto err_alloc;
++    }
++
++    for (i = 0; i < npwm; i++)
++    {
++        sub_np = of_parse_phandle(np, "sunxi-pwms", i);
++        if (IS_ERR_OR_NULL(sub_np))
++        {
++            pr_err("%s: can't parse \"sunxi-pwms\" property\n", __func__);
++            return -EINVAL;
++        }
++
++        pwm_pdevice = of_find_device_by_node(sub_np);
++        ret = sunxi_pwm_get_config(pwm_pdevice, &pwm->config[i]);
++        if (ret)
++        {
++            pr_err("Get config failed,exit!\n");
++            goto err_get_config;
++        }
++    }
++
++    pwm->clk = devm_clk_get_optional(&pdev->dev, "mod");
++    if (IS_ERR(pwm->clk))
++        return dev_err_probe(&pdev->dev, PTR_ERR(pwm->clk),
++                             "get mod clock failed\n");
++
++    pwm->bus_clk = devm_clk_get_optional(&pdev->dev, "bus");
++    if (IS_ERR(pwm->bus_clk))
++        return dev_err_probe(&pdev->dev, PTR_ERR(pwm->bus_clk),
++                             "get bus clock failed\n");
++
++    pwm->pwm_rst_clk = devm_reset_control_get_optional_shared(&pdev->dev, NULL);
++    if (IS_ERR(pwm->pwm_rst_clk))
++        return dev_err_probe(&pdev->dev, PTR_ERR(pwm->pwm_rst_clk),
++                             "get reset failed\n");
++
++    /* Deassert reset */
++    ret = reset_control_deassert(pwm->pwm_rst_clk);
++    if (ret)
++    {
++        dev_err(&pdev->dev, "cannot deassert reset control: %pe\n",
++                ERR_PTR(ret));
++        return ret;
++    }
++
++    ret = clk_prepare_enable(pwm->clk);
++    if (ret)
++    {
++        dev_err(&pdev->dev, "cannot prepare and enable clk %pe\n",
++                ERR_PTR(ret));
++        goto err_alloc;
++    }
++
++    ret = clk_prepare_enable(pwm->bus_clk);
++    if (ret)
++    {
++        dev_err(&pdev->dev, "cannot prepare and enable bus_clk %pe\n",
++                ERR_PTR(ret));
++        goto err_alloc;
++    }
++
++    return 0;
++
++err_get_config:
++err_alloc:
++    pwmchip_remove(chip);
++err_add:
++    iounmap(pwm->base);
++err_iomap:
++    return ret;
++}
++
++static void sunxi_pwm_remove(struct platform_device *pdev)
++{
++    struct pwm_chip *chip = platform_get_drvdata(pdev);
++    struct sunxi_pwm_chip *pwm = to_sunxi_pwm_chip(chip);
++    clk_disable(pwm->clk);
++    clk_disable(pwm->bus_clk);
++    reset_control_assert(pwm->pwm_rst_clk);
++    pwmchip_remove(chip);
++}
++
++static int sunxi_pwm_suspend(struct platform_device *pdev, pm_message_t state)
++{
++    return 0;
++}
++
++static int sunxi_pwm_resume(struct platform_device *pdev)
++{
++    return 0;
++}
++
++#if !IS_ENABLED(CONFIG_OF)
++struct platform_device sunxi_pwm_device = {
++    .name = "sunxi_pwm",
++    .id = -1,
++};
++#else
++static const struct of_device_id sunxi_pwm_match[] = {
++    {
++        .compatible = "allwinner,sun50i-h616-pwm",
++    },
++    {},
++};
++MODULE_DEVICE_TABLE(of, sunxi_pwm_match);
++#endif
++
++static struct platform_driver sunxi_pwm_driver = {
++    .probe = sunxi_pwm_probe,
++    .remove = sunxi_pwm_remove,
++    .suspend = sunxi_pwm_suspend,
++    .resume = sunxi_pwm_resume,
++    .driver = {
++        .name = "sunxi_pwm",
++        .owner = THIS_MODULE,
++        .of_match_table = sunxi_pwm_match,
++    },
++};
++
++static int __init pwm_module_init(void)
++{
++    int ret = 0;
++
++#if !IS_ENABLED(CONFIG_OF)
++    ret = platform_device_register(&sunxi_pwm_device);
++#endif
++    if (ret == 0)
++    {
++        ret = platform_driver_register(&sunxi_pwm_driver);
++    }
++
++    return ret;
++}
++
++static void __exit pwm_module_exit(void)
++{
++    platform_driver_unregister(&sunxi_pwm_driver);
++#if !IS_ENABLED(CONFIG_OF)
++    platform_device_unregister(&sunxi_pwm_device);
++#endif
++}
++
++subsys_initcall(pwm_module_init);
++module_exit(pwm_module_exit);
++
++MODULE_AUTHOR("zengqi");
++MODULE_AUTHOR("liuli");
++MODULE_DESCRIPTION("pwm driver");
++MODULE_LICENSE("GPL");
++MODULE_ALIAS("platform:sunxi-pwm");
+diff --git a/drivers/pwm/pwm-sunxi-enhance.h b/drivers/pwm/pwm-sunxi-enhance.h
+new file mode 100644
+index 000000000000..e25e10bf5a3d
+--- /dev/null
++++ b/drivers/pwm/pwm-sunxi-enhance.h
+@@ -0,0 +1,60 @@
++/*
++ * drivers/pwm/pwm-sunxi-new.h
++ *
++ * Allwinnertech pulse-width-modulation controller driver
++ *
++ * Copyright (C) 2018 AllWinner
++ *
++ *
++ * This file is licensed under the terms of the GNU General Public
++ * License version 2. This program is licensed "as is" without any
++ * warranty of any kind, whether express or implied.
++ */
++#ifndef __PWM_SUNXI_NEW__H__
++#define __PWM_SUNXI_NEW__H__
++
++#define PWM_PIER	(0x0000)
++#define PWM_PISR	(0x0004)
++#define	PWM_CIER	(0x0010)
++#define	PWM_CISR	(0x0014)
++#define PWM_PCCR01	(0x0020)
++#define PWM_PCCR23	(0x0024)
++#define PWM_PCCR45	(0x0028)
++#define PWM_PCCR67	(0x002c)
++#define PWM_PDZCR01	(0x0030)
++#define PWM_PDZCR23	(0x0034)
++#define	PWM_PDZCR45	(0x0038)
++#define	PWM_PDZCR67	(0x003c)
++#define PWM_PER		(0x0040)
++#define PWM_CER		(0x0044)
++
++#define PWM_PCR_BASE	(0x0060 + 0x0000)
++#define PWM_PPR_BASE	(0x0060 + 0x0004)
++#define PWM_PCNTR_BASE	(0x0060 + 0x0008)
++#define PWM_CCR_BASE	(0x0060 + 0x000c)
++#define	PWM_CRLR_BASE	(0x0060 + 0x0010)
++#define PWM_CFLR_BASE	(0x0060 + 0x0014)
++#define PWM_PCCR8	(0x0300)
++
++#define PWM_ACT_STA_SHIFT	0x8
++#define PWM_ACT_STA_WIDTH	0x1
++#define PWM_CLK_SRC_SHIFT	0x7
++#define PWM_CLK_SRC_WIDTH	0x2
++#define PWM_DIV_M_SHIFT		0x0
++#define PWM_DIV_M_WIDTH		0x4
++#define PWM_PRESCAL_SHIFT	0x0
++#define PWM_PRESCAL_WIDTH	0x8
++#define PWM_ACT_CYCLES_SHIFT	0x0
++#define PWM_ACT_CYCLES_WIDTH	0x10
++#define PWM_PERIOD_CYCLES_SHIFT	0x10
++#define PWM_PERIOD_CYCLES_WIDTH	0x10
++#define PWM_DZ_EN_SHIFT		0x0
++#define PWM_DZ_EN_WIDTH		0x1
++#define PWM_PDZINTV_SHIFT	0x8
++#define PWM_PDZINTV_WIDTH	0x8
++#define PWM_BYPASS_WIDTH	0x1
++#define PWM_CLK_GATING_SHIFT	0x4
++#define PWM_CLK_GATING_WIDTH	0x1
++
++#endif
++
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-clocksource-arm_arch_timer-fix-a64-timejump.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-clocksource-arm_arch_timer-fix-a64-timejump.patch
new file mode 100644
index 000000000000..493e768792a9
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-clocksource-arm_arch_timer-fix-a64-timejump.patch
@@ -0,0 +1,48 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Fri, 28 Jan 2022 14:18:17 +0300
+Subject: drv:clocksource:arm_arch_timer fix a64 timejump
+
+---
+ drivers/clocksource/arm_arch_timer.c | 25 ++++++----
+ 1 file changed, 14 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
+index 111111111111..222222222222 100644
+--- a/drivers/clocksource/arm_arch_timer.c
++++ b/drivers/clocksource/arm_arch_timer.c
+@@ -383,17 +383,20 @@ static u64 notrace arm64_858921_read_cntvct_el0(void)
+  * with all ones or all zeros in the low bits. Bound the loop by the maximum
+  * number of CPU cycles in 3 consecutive 24 MHz counter periods.
+  */
+-#define __sun50i_a64_read_reg(reg) ({					\
+-	u64 _val;							\
+-	int _retries = 150;						\
+-									\
+-	do {								\
+-		_val = read_sysreg(reg);				\
+-		_retries--;						\
+-	} while (((_val + 1) & GENMASK(8, 0)) <= 1 && _retries);	\
+-									\
+-	WARN_ON_ONCE(!_retries);					\
+-	_val;								\
++#define __sun50i_a64_read_reg(reg) ({                                                 \
++    register u64 _tries = 5, _old, _new;                                              \
++                                                                                      \
++    do {                                                                              \
++        if (unlikely(_tries < 3))                                                     \
++            isb();                                                                    \
++        _old = read_sysreg(reg);                                                      \
++        _new = read_sysreg(reg);                                                      \
++    } while (unlikely((_new - _old) >> 4) && --_tries);                               \
++                                                                                      \
++    if (unlikely(!_tries))                                                            \
++        pr_err("(cpu %d) returning possibly incorrect counter value %llx (%llx)\n",   \
++                smp_processor_id() + 1, _new, _old);                                  \
++   _new;                                                                              \
+ })
+ 
+ static u64 notrace sun50i_a64_read_cntpct_el0(void)
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-gpu-drm-gem-dma-Export-with-handle-allocator.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-gpu-drm-gem-dma-Export-with-handle-allocator.patch
new file mode 100644
index 000000000000..6ce7c9c275c5
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-gpu-drm-gem-dma-Export-with-handle-allocator.patch
@@ -0,0 +1,51 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Maxime Ripard <maxime.ripard@free-electrons.com>
+Date: Mon, 7 Dec 2015 09:33:28 +0100
+Subject: drv:gpu:drm: gem: dma: Export with handle allocator
+
+Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
+Signed-off-by: The-going <48602507+The-going@users.noreply.github.com>
+---
+ drivers/gpu/drm/drm_gem_dma_helper.c | 3 ++-
+ include/drm/drm_gem_dma_helper.h     | 4 ++++
+ 2 files changed, 6 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/gpu/drm/drm_gem_dma_helper.c b/drivers/gpu/drm/drm_gem_dma_helper.c
+index 111111111111..222222222222 100644
+--- a/drivers/gpu/drm/drm_gem_dma_helper.c
++++ b/drivers/gpu/drm/drm_gem_dma_helper.c
+@@ -187,7 +187,7 @@ EXPORT_SYMBOL_GPL(drm_gem_dma_create);
+  * A struct drm_gem_dma_object * on success or an ERR_PTR()-encoded negative
+  * error code on failure.
+  */
+-static struct drm_gem_dma_object *
++struct drm_gem_dma_object *
+ drm_gem_dma_create_with_handle(struct drm_file *file_priv,
+ 			       struct drm_device *drm, size_t size,
+ 			       uint32_t *handle)
+@@ -214,6 +214,7 @@ drm_gem_dma_create_with_handle(struct drm_file *file_priv,
+ 
+ 	return dma_obj;
+ }
++EXPORT_SYMBOL_GPL(drm_gem_dma_create_with_handle);
+ 
+ /**
+  * drm_gem_dma_free - free resources associated with a DMA GEM object
+diff --git a/include/drm/drm_gem_dma_helper.h b/include/drm/drm_gem_dma_helper.h
+index 111111111111..222222222222 100644
+--- a/include/drm/drm_gem_dma_helper.h
++++ b/include/drm/drm_gem_dma_helper.h
+@@ -34,6 +34,10 @@ struct drm_gem_dma_object {
+ 
+ struct drm_gem_dma_object *drm_gem_dma_create(struct drm_device *drm,
+ 					      size_t size);
++struct drm_gem_dma_object *
++drm_gem_dma_create_with_handle(struct drm_file *file_priv,
++			       struct drm_device *drm, size_t size,
++			       uint32_t *handle);
+ void drm_gem_dma_free(struct drm_gem_dma_object *dma_obj);
+ void drm_gem_dma_print_info(const struct drm_gem_dma_object *dma_obj,
+ 			    struct drm_printer *p, unsigned int indent);
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-gpu-drm-panel-simple-Add-compability-olinuxino-lcd.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-gpu-drm-panel-simple-Add-compability-olinuxino-lcd.patch
new file mode 100644
index 000000000000..90f969f07bc8
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-gpu-drm-panel-simple-Add-compability-olinuxino-lcd.patch
@@ -0,0 +1,169 @@
+From 3a3f2d1162880ac679dc6b3aaefa2b161ae694de Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Wed, 2 Feb 2022 19:34:55 +0300
+Subject: drv:gpu:drm: panel-simple Add compability olinuxino lcd
+
+---
+ drivers/gpu/drm/panel/panel-simple.c | 125 ++++++++++++++++++++++++++-
+ 1 file changed, 121 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
+index 9b2f128fd309..ff15e05c85b4 100644
+--- a/drivers/gpu/drm/panel/panel-simple.c
++++ b/drivers/gpu/drm/panel/panel-simple.c
+@@ -3550,6 +3550,42 @@ static const struct panel_desc okaya_rs800480t_7x0gp = {
+ 	.bus_format = MEDIA_BUS_FMT_RGB666_1X18,
+ };
+ 
++static const struct drm_display_mode olimex_vga_olinuxino_800_mode = {
++	.clock = 40000,
++	.hdisplay = 800,
++	.hsync_start = 800 + 40,
++	.hsync_end = 800 + 40 + 128,
++	.htotal = 800 + 40 + 128 + 88,
++	.vdisplay = 600,
++	.vsync_start = 600 + 5,
++	.vsync_end = 600 + 5 + 4,
++	.vtotal = 600 + 5 + 4 + 19,
++};
++
++static const struct drm_display_mode olimex_vga_olinuxino_1024_mode = {
++	.clock = 45000,
++	.hdisplay = 1024,
++	.hsync_start = 1024 + 16,
++	.hsync_end = 1024 + 16 + 10,
++	.htotal = 1024 + 16 + 10 + 150,
++	.vdisplay = 600,
++	.vsync_start = 600 + 2,
++	.vsync_end = 600 + 2 + 21,
++	.vtotal = 600 + 2 + 21 + 2,
++};
++
++static const struct drm_display_mode olimex_lcd_olinuxino_43_mode = {
++	.clock = 12000,
++	.hdisplay = 480,
++	.hsync_start = 480 + 8,
++	.hsync_end = 480 + 8 + 20,
++	.htotal = 480 + 8 + 20 + 23,
++	.vdisplay = 272,
++	.vsync_start = 272 + 4,
++	.vsync_end = 272 + 4 + 10,
++	.vtotal = 272 + 4 + 10 + 13,
++};
++
+ static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
+ 	.clock = 9000,
+ 	.hdisplay = 480,
+@@ -3562,8 +3598,8 @@ static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
+ 	.vtotal = 272 + 8 + 5 + 3,
+ };
+ 
+-static const struct panel_desc olimex_lcd_olinuxino_43ts = {
+-	.modes = &olimex_lcd_olinuxino_43ts_mode,
++static const struct panel_desc olimex_lcd_olinuxino_43 = {
++	.modes = &olimex_lcd_olinuxino_43_mode,
+ 	.num_modes = 1,
+ 	.size = {
+ 		.width = 95,
+@@ -3605,6 +3641,72 @@ static const struct panel_desc ontat_kd50g21_40nt_a1 = {
+ 	.connector_type = DRM_MODE_CONNECTOR_DPI,
+ };
+ 
++static const struct drm_display_mode olimex_lcd_olinuxino_5_mode = {
++	.clock = 33300,
++	.hdisplay = 800,
++	.hsync_start = 800 + 210,
++	.hsync_end = 800 + 210 + 20,
++	.htotal = 800 + 210 + 20 + 26,
++	.vdisplay = 480,
++	.vsync_start = 480 + 22,
++	.vsync_end = 480 + 22 + 10,
++	.vtotal = 480 + 22 + 10 + 13,
++};
++
++static const struct panel_desc olimex_lcd_olinuxino_5 = {
++	.modes = &olimex_lcd_olinuxino_5_mode,
++	.num_modes = 1,
++	.size = {
++		.width = 154,
++		.height = 86,
++	},
++	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
++};
++
++static const struct drm_display_mode olimex_lcd_olinuxino_7_mode = {
++	.clock = 33300,
++	.hdisplay = 800,
++	.hsync_start = 800 + 210,
++	.hsync_end = 800 + 210 + 20,
++	.htotal = 800 + 210 + 20 + 26,
++	.vdisplay = 480,
++	.vsync_start = 480 + 22,
++	.vsync_end = 480 + 22 + 10,
++	.vtotal = 480 + 22 + 10 + 13,
++};
++
++static const struct panel_desc olimex_lcd_olinuxino_7 = {
++	.modes = &olimex_lcd_olinuxino_7_mode,
++	.num_modes = 1,
++	.size = {
++		.width = 154,
++		.height = 86,
++	},
++	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
++};
++
++static const struct drm_display_mode olimex_lcd_olinuxino_10_mode = {
++	.clock = 45000,
++	.hdisplay = 1024,
++	.hsync_start = 1024 + 16,
++	.hsync_end = 1024 + 16 + 1,
++	.htotal = 1024 + 10 + 6 + 160,
++	.vdisplay = 600,
++	.vsync_start = 600 + 1,
++	.vsync_end = 600 + 1 + 1,
++	.vtotal = 600 + 1 + 1 + 22,
++};
++
++static const struct panel_desc olimex_lcd_olinuxino_10 = {
++	.modes = &olimex_lcd_olinuxino_10_mode,
++	.num_modes = 1,
++	.size = {
++		.width = 222,
++		.height = 143,
++	},
++	.bus_format = MEDIA_BUS_FMT_RGB888_1X24,
++};
++
+ /*
+  * 800x480 CVT. The panel appears to be quite accepting, at least as far as
+  * pixel clocks, but this is the timing that was being used in the Adafruit
+@@ -5066,8 +5168,23 @@ static const struct of_device_id platform_of_match[] = {
+ 		.compatible = "okaya,rs800480t-7x0gp",
+ 		.data = &okaya_rs800480t_7x0gp,
+ 	}, {
+-		.compatible = "olimex,lcd-olinuxino-43-ts",
+-		.data = &olimex_lcd_olinuxino_43ts,
++		.compatible = "olimex,olinuxino-vga-800x600",
++		.data = &olimex_vga_olinuxino_800_mode,
++	}, {
++		.compatible = "olimex,olinuxino-vga-1024x768",
++		.data = &olimex_vga_olinuxino_1024_mode,
++	}, {
++		.compatible = "olimex,lcd-olinuxino-4.3",
++		.data = &olimex_lcd_olinuxino_43,
++	}, {
++		.compatible = "olimex,lcd-olinuxino-5",
++		.data = &olimex_lcd_olinuxino_5,
++	}, {
++		.compatible = "olimex,lcd-olinuxino-7",
++		.data = &olimex_lcd_olinuxino_7,
++	}, {
++		.compatible = "olimex,lcd-olinuxino-10",
++		.data = &olimex_lcd_olinuxino_10,
+ 	}, {
+ 		.compatible = "ontat,kd50g21-40nt-a1",
+ 		.data = &ontat_kd50g21_40nt_a1,
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-gpu-drm-sun4i-Add-GEM-allocator.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-gpu-drm-sun4i-Add-GEM-allocator.patch
new file mode 100644
index 000000000000..a75bb1654b83
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-gpu-drm-sun4i-Add-GEM-allocator.patch
@@ -0,0 +1,103 @@
+From c4ff09ffb5ec28fe119e3fa89dbd464b5d208637 Mon Sep 17 00:00:00 2001
+From: Maxime Ripard <maxime.ripard@free-electrons.com>
+Date: Mon, 7 Dec 2015 09:47:34 +0100
+Subject: drv:gpu:drm:sun4i: Add GEM allocator
+
+Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
+Signed-off-by: The-going <48602507+The-going@users.noreply.github.com>
+---
+ drivers/gpu/drm/sun4i/sun4i_drv.c | 27 +++++++++++++++++++++++++++
+ include/uapi/drm/sun4i_drm.h      | 29 +++++++++++++++++++++++++++++
+ 2 files changed, 56 insertions(+)
+ create mode 100644 include/uapi/drm/sun4i_drm.h
+
+diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c b/drivers/gpu/drm/sun4i/sun4i_drv.c
+index c11dfb2739fa..9389a8a075dd 100644
+--- a/drivers/gpu/drm/sun4i/sun4i_drv.c
++++ b/drivers/gpu/drm/sun4i/sun4i_drv.c
+@@ -25,6 +25,8 @@
+ #include <drm/drm_probe_helper.h>
+ #include <drm/drm_vblank.h>
+ 
++#include <uapi/drm/sun4i_drm.h>
++
+ #include "sun4i_drv.h"
+ #include "sun4i_frontend.h"
+ #include "sun4i_framebuffer.h"
+@@ -43,6 +45,27 @@ static int drm_sun4i_gem_dumb_create(struct drm_file *file_priv,
+ 
+ DEFINE_DRM_GEM_DMA_FOPS(sun4i_drv_fops);
+ 
++static int sun4i_gem_create_ioctl(struct drm_device *drm, void *data,
++				  struct drm_file *file_priv)
++{
++	struct drm_sun4i_gem_create *args = data;
++	struct drm_gem_dma_object *dma_obj;
++	size_t size;
++
++	/* The Mali requires a 64 bytes alignment */
++	size = ALIGN(args->size, 64);
++
++	dma_obj = drm_gem_dma_create_with_handle(file_priv, drm, size,
++						 &args->handle);
++
++	return PTR_ERR_OR_ZERO(dma_obj);
++}
++
++static const struct drm_ioctl_desc sun4i_drv_ioctls[] = {
++	DRM_IOCTL_DEF_DRV(SUN4I_GEM_CREATE, sun4i_gem_create_ioctl,
++			  DRM_AUTH),
++};
++
+ static const struct drm_driver sun4i_drv_driver = {
+ 	.driver_features	= DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
+ 
+@@ -53,6 +76,10 @@ static const struct drm_driver sun4i_drv_driver = {
+ 	.major			= 1,
+ 	.minor			= 0,
+ 
++	/* Custom ioctls */
++	.ioctls			= sun4i_drv_ioctls,
++	.num_ioctls		= ARRAY_SIZE(sun4i_drv_ioctls),
++
+ 	/* GEM Operations */
+ 	DRM_GEM_DMA_DRIVER_OPS_WITH_DUMB_CREATE(drm_sun4i_gem_dumb_create),
+ 	DRM_FBDEV_DMA_DRIVER_OPS,
+diff --git a/include/uapi/drm/sun4i_drm.h b/include/uapi/drm/sun4i_drm.h
+new file mode 100644
+index 000000000000..67b9dd4ee594
+--- /dev/null
++++ b/include/uapi/drm/sun4i_drm.h
+@@ -0,0 +1,29 @@
++/*
++ * Copyright (C) 2015 Free Electrons
++ * Copyright (C) 2015 NextThing Co
++ *
++ * Maxime Ripard <maxime.ripard@free-electrons.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ */
++
++#ifndef _UAPI_SUN4I_DRM_H_
++#define _UAPI_SUN4I_DRM_H_
++
++#include <drm/drm.h>
++
++struct drm_sun4i_gem_create {
++	__u64 size;
++	__u32 flags;
++	__u32 handle;
++};
++
++#define DRM_SUN4I_GEM_CREATE		0x00
++
++#define DRM_IOCTL_SUN4I_GEM_CREATE	DRM_IOWR(DRM_COMMAND_BASE + DRM_SUN4I_GEM_CREATE, \
++						 struct drm_sun4i_gem_create)
++
++#endif
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-gpu-drm-sun4i-Add-HDMI-audio-sun4i-hdmi-encoder.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-gpu-drm-sun4i-Add-HDMI-audio-sun4i-hdmi-encoder.patch
new file mode 100644
index 000000000000..45d5e4211ca7
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-gpu-drm-sun4i-Add-HDMI-audio-sun4i-hdmi-encoder.patch
@@ -0,0 +1,633 @@
+From c7f9993fb9fa967e80d5b2dc2d422b5dc8ce9f7c Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Mon, 24 Jan 2022 13:07:16 +0300
+Subject: drv:gpu:drm:sun4i: Add HDMI audio sun4i-hdmi encoder
+
+Add HDMI audio support for the sun4i-hdmi encoder, used on
+the older Allwinner chips - A10, A20, A31.
+
+Most of the code is based on the BSP implementation. In it
+dditional formats are supported (S20_3LE and S24_LE), however
+there where some problems with them and only S16_LE is left.
+
+Signed-off-by: Stefan Mavrodiev <stefan@olimex.com>
+---
+ drivers/gpu/drm/sun4i/Kconfig            |  11 +
+ drivers/gpu/drm/sun4i/Makefile           |   3 +
+ drivers/gpu/drm/sun4i/sun4i_hdmi.h       |  36 ++
+ drivers/gpu/drm/sun4i/sun4i_hdmi_audio.c | 450 +++++++++++++++++++++++
+ drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c   |  16 +
+ 5 files changed, 516 insertions(+)
+ create mode 100644 drivers/gpu/drm/sun4i/sun4i_hdmi_audio.c
+
+diff --git a/drivers/gpu/drm/sun4i/Kconfig b/drivers/gpu/drm/sun4i/Kconfig
+index b56ba00aabca..0d1f37fcd51a 100644
+--- a/drivers/gpu/drm/sun4i/Kconfig
++++ b/drivers/gpu/drm/sun4i/Kconfig
+@@ -27,6 +27,17 @@ config DRM_SUN4I_HDMI
+ 	  Choose this option if you have an Allwinner A10/A10s/A20/A31
+ 	  SoC with an HDMI controller.
+ 
++config DRM_SUN4I_HDMI_AUDIO
++	bool "Allwinner A10 HDMI Audio Support"
++	default y
++	depends on DRM_SUN4I_HDMI
++	depends on SND_SOC=y || SND_SOC=DRM_SUN4I_HDMI
++	select SND_PCM_ELD
++	select SND_SOC_GENERIC_DMAENGINE_PCM
++	help
++	  Choose this option if you have an Allwinner SoC with an HDMI
++	  controller and want to use audio.
++
+ config DRM_SUN4I_HDMI_CEC
+ 	bool "Allwinner A10/A10s/A20/A31 HDMI CEC Support"
+ 	depends on DRM_SUN4I_HDMI
+diff --git a/drivers/gpu/drm/sun4i/Makefile b/drivers/gpu/drm/sun4i/Makefile
+index 78290f1660fb..8ffddaa3e069 100644
+--- a/drivers/gpu/drm/sun4i/Makefile
++++ b/drivers/gpu/drm/sun4i/Makefile
+@@ -5,6 +5,9 @@ sun4i-frontend-y		+= sun4i_frontend.o
+ sun4i-drm-y			+= sun4i_drv.o
+ sun4i-drm-y			+= sun4i_framebuffer.o
+ 
++ifdef CONFIG_DRM_SUN4I_HDMI_AUDIO
++sun4i-drm-hdmi-y		+= sun4i_hdmi_audio.o
++endif
+ sun4i-drm-hdmi-y		+= sun4i_hdmi_ddc_clk.o
+ sun4i-drm-hdmi-y		+= sun4i_hdmi_enc.o
+ sun4i-drm-hdmi-y		+= sun4i_hdmi_i2c.o
+diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi.h b/drivers/gpu/drm/sun4i/sun4i_hdmi.h
+index 65c801cd6f35..2edced4eb5d5 100644
+--- a/drivers/gpu/drm/sun4i/sun4i_hdmi.h
++++ b/drivers/gpu/drm/sun4i/sun4i_hdmi.h
+@@ -42,7 +42,32 @@
+ #define SUN4I_HDMI_VID_TIMING_POL_VSYNC		BIT(1)
+ #define SUN4I_HDMI_VID_TIMING_POL_HSYNC		BIT(0)
+ 
++#define SUN4I_HDMI_AUDIO_CTRL_REG	0x040
++#define SUN4I_HDMI_AUDIO_CTRL_ENABLE		BIT(31)
++#define SUN4I_HDMI_AUDIO_CTRL_RESET		BIT(30)
++
++#define SUN4I_HDMI_AUDIO_FMT_REG	0x048
++#define SUN4I_HDMI_AUDIO_FMT_SRC		BIT(31)
++#define SUN4I_HDMI_AUDIO_FMT_LAYOUT		BIT(3)
++#define SUN4I_HDMI_AUDIO_FMT_CH_CFG(n)		((n) - 1)
++#define SUN4I_HDMI_AUDIO_FMT_CH_CFG_MASK	GENMASK(2, 0)
++
++#define SUN4I_HDMI_AUDIO_PCM_REG	0x4c
++#define SUN4I_HDMI_AUDIO_PCM_CH_MAP(n, m)	(((m) - 1) << ((n) * 4))
++#define SUN4I_HDMI_AUDIO_PCM_CH_MAP_MASK(n)	(GENMASK(2, 0) << ((n) * 4))
++
++#define SUN4I_HDMI_AUDIO_CTS_REG	0x050
++#define SUN4I_HDMI_AUDIO_CTS(n)			((n) & GENMASK(19, 0))
++
++#define SUN4I_HDMI_AUDIO_N_REG		0x054
++#define SUN4I_HDMI_AUDIO_N(n)			((n) & GENMASK(19, 0))
++
++#define SUN4I_HDMI_AUDIO_STAT0_REG	0x58
++#define SUN4I_HDMI_AUDIO_STAT0_FREQ(n)		((n) << 24)
++#define SUN4I_HDMI_AUDIO_STAT0_FREQ_MASK	GENMASK(27, 24)
++
+ #define SUN4I_HDMI_AVI_INFOFRAME_REG(n)	(0x080 + (n))
++#define SUN4I_HDMI_AUDIO_INFOFRAME_REG(n)	(0x0a0 + (n))
+ 
+ #define SUN4I_HDMI_PAD_CTRL0_REG	0x200
+ #define SUN4I_HDMI_PAD_CTRL0_BIASEN		BIT(31)
+@@ -242,6 +267,11 @@ struct sun4i_hdmi_variant {
+ 	bool			ddc_fifo_has_dir;
+ };
+ 
++struct sun4i_hdmi_audio {
++	struct snd_soc_card		*card;
++	u8				channels;
++};
++
+ struct sun4i_hdmi {
+ 	struct drm_connector	connector;
+ 	struct drm_encoder	encoder;
+@@ -285,6 +315,10 @@ struct sun4i_hdmi {
+ 
+ 	struct sun4i_drv	*drv;
+ 
++	bool			hdmi_audio;
++
++	struct sun4i_hdmi_audio audio;
++
+ 	struct cec_adapter	*cec_adap;
+ 
+ 	const struct sun4i_hdmi_variant	*variant;
+@@ -293,5 +327,7 @@ struct sun4i_hdmi {
+ int sun4i_ddc_create(struct sun4i_hdmi *hdmi, struct clk *clk);
+ int sun4i_tmds_create(struct sun4i_hdmi *hdmi);
+ int sun4i_hdmi_i2c_create(struct device *dev, struct sun4i_hdmi *hdmi);
++int sun4i_hdmi_audio_create(struct sun4i_hdmi *hdmi);
++void sun4i_hdmi_audio_destroy(struct sun4i_hdmi *hdmi);
+ 
+ #endif /* _SUN4I_HDMI_H_ */
+diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_audio.c b/drivers/gpu/drm/sun4i/sun4i_hdmi_audio.c
+new file mode 100644
+index 000000000000..a66b6c51947a
+--- /dev/null
++++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_audio.c
+@@ -0,0 +1,450 @@
++// SPDX-License-Identifier: GPL-2.0-or-later
++/*
++ * Copyright (C) 2020 Olimex Ltd.
++ *   Author: Stefan Mavrodiev <stefan@olimex.com>
++ */
++#include <linux/dma-mapping.h>
++#include <linux/dmaengine.h>
++#include <linux/module.h>
++#include <linux/of_dma.h>
++#include <linux/regmap.h>
++
++#include <drm/drm_print.h>
++
++#include <sound/dmaengine_pcm.h>
++#include <sound/pcm_drm_eld.h>
++#include <sound/pcm_params.h>
++#include <sound/soc.h>
++
++#include "sun4i_hdmi.h"
++
++static int sun4i_hdmi_audio_ctl_eld_info(struct snd_kcontrol *kcontrol,
++					 struct snd_ctl_elem_info *uinfo)
++{
++	uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
++	uinfo->count = MAX_ELD_BYTES;
++	return 0;
++}
++
++static int sun4i_hdmi_audio_ctl_eld_get(struct snd_kcontrol *kcontrol,
++					struct snd_ctl_elem_value *ucontrol)
++{
++	struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
++	struct snd_soc_card *card = snd_soc_component_get_drvdata(component);
++	struct sun4i_hdmi *hdmi = snd_soc_card_get_drvdata(card);
++
++	memcpy(ucontrol->value.bytes.data,
++	       hdmi->connector.eld,
++	       MAX_ELD_BYTES);
++
++	return 0;
++}
++
++static const struct snd_kcontrol_new sun4i_hdmi_audio_controls[] = {
++	{
++		.access = SNDRV_CTL_ELEM_ACCESS_READ |
++			  SNDRV_CTL_ELEM_ACCESS_VOLATILE,
++		.iface = SNDRV_CTL_ELEM_IFACE_PCM,
++		.name = "ELD",
++		.info = sun4i_hdmi_audio_ctl_eld_info,
++		.get = sun4i_hdmi_audio_ctl_eld_get,
++	},
++};
++
++static const struct snd_soc_dapm_widget sun4i_hdmi_audio_widgets[] = {
++	SND_SOC_DAPM_OUTPUT("TX"),
++};
++
++static const struct snd_soc_dapm_route sun4i_hdmi_audio_routes[] = {
++	{ "TX", NULL, "Playback" },
++};
++
++static const struct snd_soc_component_driver sun4i_hdmi_audio_component = {
++	.controls               = sun4i_hdmi_audio_controls,
++	.num_controls           = ARRAY_SIZE(sun4i_hdmi_audio_controls),
++	.dapm_widgets		= sun4i_hdmi_audio_widgets,
++	.num_dapm_widgets	= ARRAY_SIZE(sun4i_hdmi_audio_widgets),
++	.dapm_routes		= sun4i_hdmi_audio_routes,
++	.num_dapm_routes	= ARRAY_SIZE(sun4i_hdmi_audio_routes),
++};
++
++static int sun4i_hdmi_audio_startup(struct snd_pcm_substream *substream,
++				    struct snd_soc_dai *dai)
++{
++	struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
++	struct sun4i_hdmi *hdmi = snd_soc_card_get_drvdata(card);
++	u32 reg;
++	int ret;
++
++	regmap_write(hdmi->regmap, SUN4I_HDMI_AUDIO_CTRL_REG, 0);
++	regmap_write(hdmi->regmap,
++		     SUN4I_HDMI_AUDIO_CTRL_REG,
++		     SUN4I_HDMI_AUDIO_CTRL_RESET);
++	ret = regmap_read_poll_timeout(hdmi->regmap,
++				       SUN4I_HDMI_AUDIO_CTRL_REG,
++				       reg, !reg, 100, 50000);
++	if (ret < 0) {
++		DRM_ERROR("Failed to reset HDMI Audio\n");
++		return ret;
++	}
++
++	regmap_write(hdmi->regmap,
++		     SUN4I_HDMI_AUDIO_CTRL_REG,
++		     SUN4I_HDMI_AUDIO_CTRL_ENABLE);
++
++	return snd_pcm_hw_constraint_eld(substream->runtime,
++					hdmi->connector.eld);
++}
++
++static void sun4i_hdmi_audio_shutdown(struct snd_pcm_substream *substream,
++				      struct snd_soc_dai *dai)
++{
++	struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
++	struct sun4i_hdmi *hdmi = snd_soc_card_get_drvdata(card);
++
++	regmap_write(hdmi->regmap, SUN4I_HDMI_AUDIO_CTRL_REG, 0);
++}
++
++static int sun4i_hdmi_setup_audio_infoframes(struct sun4i_hdmi *hdmi)
++{
++	union hdmi_infoframe frame;
++	u8 buffer[14];
++	int i, ret;
++
++	ret = hdmi_audio_infoframe_init(&frame.audio);
++	if (ret < 0) {
++		DRM_ERROR("Failed to init HDMI audio infoframe\n");
++		return ret;
++	}
++
++	frame.audio.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM;
++	frame.audio.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM;
++	frame.audio.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM;
++	frame.audio.channels = hdmi->audio.channels;
++
++	ret = hdmi_infoframe_pack(&frame, buffer, sizeof(buffer));
++	if (ret < 0) {
++		DRM_ERROR("Failed to pack HDMI audio infoframe\n");
++		return ret;
++	}
++
++	for (i = 0; i < sizeof(buffer); i++)
++		writeb(buffer[i],
++		       hdmi->base + SUN4I_HDMI_AUDIO_INFOFRAME_REG(i));
++
++	return 0;
++}
++
++static void sun4i_hdmi_audio_set_cts_n(struct sun4i_hdmi *hdmi,
++				       struct snd_pcm_hw_params *params)
++{
++	struct drm_encoder *encoder = &hdmi->encoder;
++	struct drm_crtc *crtc = encoder->crtc;
++	const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
++	u32 rate = params_rate(params);
++	u32 n, cts;
++	u64 tmp;
++
++	/**
++	 * Calculate Cycle Time Stamp (CTS) and Numerator (N):
++	 *
++	 * N = 128 * Samplerate / 1000
++	 * CTS = (Ftdms * N) / (128 * Samplerate)
++	 */
++
++	n = 128 * rate / 1000;
++	tmp = (u64)(mode->clock * 1000) * n;
++	do_div(tmp, 128 * rate);
++	cts = tmp;
++
++	regmap_write(hdmi->regmap,
++		     SUN4I_HDMI_AUDIO_CTS_REG,
++		     SUN4I_HDMI_AUDIO_CTS(cts));
++
++	regmap_write(hdmi->regmap,
++		     SUN4I_HDMI_AUDIO_N_REG,
++		     SUN4I_HDMI_AUDIO_N(n));
++}
++
++static int sun4i_hdmi_audio_set_hw_rate(struct sun4i_hdmi *hdmi,
++					struct snd_pcm_hw_params *params)
++{
++	u32 rate = params_rate(params);
++	u32 val;
++
++	switch (rate) {
++	case 44100:
++		val = 0x0;
++		break;
++	case 48000:
++		val = 0x2;
++		break;
++	case 32000:
++		val = 0x3;
++		break;
++	case 88200:
++		val = 0x8;
++		break;
++	case 96000:
++		val = 0x9;
++		break;
++	case 176400:
++		val = 0xc;
++		break;
++	case 192000:
++		val = 0xe;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	regmap_update_bits(hdmi->regmap,
++			   SUN4I_HDMI_AUDIO_STAT0_REG,
++			   SUN4I_HDMI_AUDIO_STAT0_FREQ_MASK,
++			   SUN4I_HDMI_AUDIO_STAT0_FREQ(val));
++
++	return 0;
++}
++
++static int sun4i_hdmi_audio_set_hw_channels(struct sun4i_hdmi *hdmi,
++					    struct snd_pcm_hw_params *params)
++{
++	u32 channels = params_channels(params);
++
++	if (channels > 8)
++		return -EINVAL;
++
++	hdmi->audio.channels = channels;
++
++	regmap_update_bits(hdmi->regmap,
++			   SUN4I_HDMI_AUDIO_FMT_REG,
++			   SUN4I_HDMI_AUDIO_FMT_LAYOUT,
++			   (channels > 2) ? SUN4I_HDMI_AUDIO_FMT_LAYOUT : 0);
++
++	regmap_update_bits(hdmi->regmap,
++			   SUN4I_HDMI_AUDIO_FMT_REG,
++			   SUN4I_HDMI_AUDIO_FMT_CH_CFG_MASK,
++			   SUN4I_HDMI_AUDIO_FMT_CH_CFG(channels));
++
++	regmap_write(hdmi->regmap, SUN4I_HDMI_AUDIO_PCM_REG, 0x76543210);
++
++	/**
++	 * If only one channel is required, send the same sample
++	 * to the sink device as a left and right channel.
++	 */
++	if (channels == 1)
++		regmap_update_bits(hdmi->regmap,
++				   SUN4I_HDMI_AUDIO_PCM_REG,
++				   SUN4I_HDMI_AUDIO_PCM_CH_MAP_MASK(1),
++				   SUN4I_HDMI_AUDIO_PCM_CH_MAP(1, 1));
++
++	return 0;
++}
++
++static int sun4i_hdmi_audio_hw_params(struct snd_pcm_substream *substream,
++				      struct snd_pcm_hw_params *params,
++				      struct snd_soc_dai *dai)
++{
++	struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
++	struct sun4i_hdmi *hdmi = snd_soc_card_get_drvdata(card);
++	int ret;
++
++	ret = sun4i_hdmi_audio_set_hw_rate(hdmi, params);
++	if (ret < 0)
++		return ret;
++
++	ret = sun4i_hdmi_audio_set_hw_channels(hdmi, params);
++	if (ret < 0)
++		return ret;
++
++	sun4i_hdmi_audio_set_cts_n(hdmi, params);
++
++	return 0;
++}
++
++static int sun4i_hdmi_audio_trigger(struct snd_pcm_substream *substream,
++				    int cmd,
++				    struct snd_soc_dai *dai)
++{
++	struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
++	struct sun4i_hdmi *hdmi = snd_soc_card_get_drvdata(card);
++	int ret = 0;
++
++	switch (cmd) {
++	case SNDRV_PCM_TRIGGER_START:
++		ret = sun4i_hdmi_setup_audio_infoframes(hdmi);
++		break;
++	default:
++		break;
++	}
++
++	return ret;
++}
++
++static int sun4i_hdmi_audio_dai_probe(struct snd_soc_dai *dai)
++{
++	struct snd_dmaengine_dai_dma_data *dma_data;
++
++	dma_data = devm_kzalloc(dai->dev, sizeof(*dma_data), GFP_KERNEL);
++	if (!dma_data)
++		return -ENOMEM;
++
++	dma_data->addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
++	dma_data->maxburst = 8;
++
++	snd_soc_dai_init_dma_data(dai, dma_data, NULL);
++
++	return 0;
++}
++
++static const struct snd_soc_dai_ops sun4i_hdmi_audio_dai_ops = {
++	.probe = sun4i_hdmi_audio_dai_probe,
++	.startup = sun4i_hdmi_audio_startup,
++	.shutdown = sun4i_hdmi_audio_shutdown,
++	.hw_params = sun4i_hdmi_audio_hw_params,
++	.trigger = sun4i_hdmi_audio_trigger,
++};
++
++static struct snd_soc_dai_driver sun4i_hdmi_audio_dai = {
++	.name = "HDMI",
++	.ops = &sun4i_hdmi_audio_dai_ops,
++	.playback = {
++		.stream_name	= "Playback",
++		.channels_min	= 1,
++		.channels_max	= 8,
++		.formats	= SNDRV_PCM_FMTBIT_S16_LE,
++		.rates		= SNDRV_PCM_RATE_8000_192000,
++	},
++};
++
++static const struct snd_pcm_hardware sun4i_hdmi_audio_pcm_hardware = {
++	.info			= SNDRV_PCM_INFO_INTERLEAVED |
++				  SNDRV_PCM_INFO_BLOCK_TRANSFER |
++				  SNDRV_PCM_INFO_MMAP |
++				  SNDRV_PCM_INFO_MMAP_VALID |
++				  SNDRV_PCM_INFO_PAUSE |
++				  SNDRV_PCM_INFO_RESUME,
++	.formats		= SNDRV_PCM_FMTBIT_S16_LE,
++	.rates                  = SNDRV_PCM_RATE_8000_192000,
++	.rate_min               = 8000,
++	.rate_max               = 192000,
++	.channels_min           = 1,
++	.channels_max           = 8,
++	.buffer_bytes_max	= 128 * 1024,
++	.period_bytes_min	= 4 * 1024,
++	.period_bytes_max	= 32 * 1024,
++	.periods_min		= 2,
++	.periods_max		= 8,
++	.fifo_size		= 128,
++};
++
++static const struct snd_dmaengine_pcm_config sun4i_hdmi_audio_pcm_config = {
++	.chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-tx",
++	.pcm_hardware = &sun4i_hdmi_audio_pcm_hardware,
++	.prealloc_buffer_size = 128 * 1024,
++	.prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
++};
++
++struct snd_soc_card sun4i_hdmi_audio_card = {
++	.name = "sun4i-hdmi",
++};
++
++int sun4i_hdmi_audio_create(struct sun4i_hdmi *hdmi)
++{
++	struct snd_soc_card *card = &sun4i_hdmi_audio_card;
++	struct snd_soc_dai_link_component *comp;
++	struct snd_soc_dai_link *link;
++	int ret;
++
++	ret = snd_dmaengine_pcm_register(hdmi->dev,
++					 &sun4i_hdmi_audio_pcm_config, 0);
++	if (ret < 0) {
++		DRM_ERROR("Could not register PCM\n");
++		return ret;
++	}
++
++	ret = snd_soc_register_component(hdmi->dev,
++					 &sun4i_hdmi_audio_component,
++					 &sun4i_hdmi_audio_dai, 1);
++	if (ret < 0) {
++		DRM_ERROR("Could not register DAI\n");
++		goto unregister_pcm;
++	}
++
++	link = devm_kzalloc(hdmi->dev, sizeof(*link), GFP_KERNEL);
++	if (!link) {
++		ret = -ENOMEM;
++		goto unregister_component;
++	}
++
++	comp = devm_kzalloc(hdmi->dev, sizeof(*comp) * 3, GFP_KERNEL);
++	if (!comp) {
++		ret = -ENOMEM;
++		goto unregister_component;
++	}
++
++	link->cpus = &comp[0];
++	link->codecs = &comp[1];
++	link->platforms = &comp[2];
++
++	link->num_cpus = 1;
++	link->num_codecs = 1;
++	link->num_platforms = 1;
++
++	link->playback_only = 1;
++
++	link->name = "SUN4I-HDMI";
++	link->stream_name = "SUN4I-HDMI PCM";
++
++	link->codecs->name = dev_name(hdmi->dev);
++	link->codecs->dai_name	= sun4i_hdmi_audio_dai.name;
++
++	link->cpus->dai_name = dev_name(hdmi->dev);
++
++	link->platforms->name = dev_name(hdmi->dev);
++
++	link->dai_fmt = SND_SOC_DAIFMT_I2S;
++
++	card->dai_link = link;
++	card->num_links = 1;
++	card->dev = hdmi->dev;
++
++	hdmi->audio.card = card;
++
++	/**
++	 * snd_soc_register_card() will overwrite the driver_data pointer.
++	 * So before registering the card, store the original pointer in
++	 * card->drvdata.
++	 */
++	snd_soc_card_set_drvdata(card, hdmi);
++	ret = snd_soc_register_card(card);
++	if (ret)
++		goto unregister_component;
++
++	return 0;
++
++unregister_component:
++	snd_soc_unregister_component(hdmi->dev);
++unregister_pcm:
++	snd_dmaengine_pcm_unregister(hdmi->dev);
++	return ret;
++}
++
++void sun4i_hdmi_audio_destroy(struct sun4i_hdmi *hdmi)
++{
++	struct snd_soc_card *card = hdmi->audio.card;
++	void *data;
++
++	/**
++	 * Before removing the card, restore the previously stored driver_data.
++	 * This will ensure proper removal of the sun4i-hdmi module, since it
++	 * uses dev_get_drvdata() in the unbind function.
++	 */
++	data = snd_soc_card_get_drvdata(card);
++
++	snd_soc_unregister_card(card);
++	snd_soc_unregister_component(hdmi->dev);
++	snd_dmaengine_pcm_unregister(hdmi->dev);
++
++	dev_set_drvdata(hdmi->dev, data);
++}
+diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c b/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
+index 22024fd34b2b..18be76f66829 100644
+--- a/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
++++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_enc.c
+@@ -29,6 +29,8 @@
+ #include <drm/display/drm_hdmi_helper.h>
+ #include <drm/display/drm_hdmi_state_helper.h>
+ 
++#include <sound/soc.h>
++
+ #include "sun4i_backend.h"
+ #include "sun4i_crtc.h"
+ #include "sun4i_drv.h"
+@@ -68,6 +70,11 @@ static void sun4i_hdmi_disable(struct drm_encoder *encoder,
+ 
+ 	DRM_DEBUG_DRIVER("Disabling the HDMI Output\n");
+ 
++#ifdef CONFIG_DRM_SUN4I_HDMI_AUDIO
++	if (hdmi->hdmi_audio)
++		sun4i_hdmi_audio_destroy(hdmi);
++#endif
++
+ 	val = readl(hdmi->base + SUN4I_HDMI_VID_CTRL_REG);
+ 	val &= ~SUN4I_HDMI_VID_CTRL_ENABLE;
+ 	writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG);
+@@ -155,6 +162,11 @@ static void sun4i_hdmi_enable(struct drm_encoder *encoder,
+ 		val |= SUN4I_HDMI_VID_CTRL_HDMI_MODE;
+ 
+ 	writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG);
++
++#ifdef CONFIG_DRM_SUN4I_HDMI_AUDIO
++	if (hdmi->hdmi_audio && sun4i_hdmi_audio_create(hdmi))
++		DRM_ERROR("Couldn't create the HDMI audio adapter\n");
++#endif
+ }
+ 
+ static const struct drm_encoder_helper_funcs sun4i_hdmi_helper_funcs = {
+@@ -197,6 +209,10 @@ static int sun4i_hdmi_get_modes(struct drm_connector *connector)
+ 	if (!edid)
+ 		return 0;
+ 
++#ifdef CONFIG_DRM_SUN4I_HDMI_AUDIO
++	hdmi->hdmi_audio = drm_detect_monitor_audio(edid);
++#endif
++
+ 	DRM_DEBUG_DRIVER("Monitor is %s monitor\n",
+ 			 connector->display_info.is_hdmi ? "an HDMI" : "a DVI");
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-gpu-drm-sun4i-sun8i_mixer.c-add-h3-mixer1.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-gpu-drm-sun4i-sun8i_mixer.c-add-h3-mixer1.patch
new file mode 100644
index 000000000000..1b207cd0d44d
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-gpu-drm-sun4i-sun8i_mixer.c-add-h3-mixer1.patch
@@ -0,0 +1,42 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Tue, 1 Feb 2022 19:37:03 +0300
+Subject: drv:gpu:drm:sun4i:sun8i_mixer.c add h3 mixer1
+
+---
+ drivers/gpu/drm/sun4i/sun8i_mixer.c | 12 ++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
+index 111111111111..222222222222 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
++++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
+@@ -769,6 +769,14 @@ static const struct sun8i_mixer_cfg sun8i_h3_mixer0_cfg = {
+ 	.vi_num		= 1,
+ };
+ 
++static const struct sun8i_mixer_cfg sun8i_h3_mixer1_cfg = {
++	.ccsc		= CCSC_MIXER1_LAYOUT,
++	.mod_rate	= 432000000,
++	.scaler_mask	= 0xf,
++	.ui_num		= 3,
++	.vi_num		= 1,
++};
++
+ static const struct sun8i_mixer_cfg sun8i_r40_mixer0_cfg = {
+ 	.ccsc		= CCSC_MIXER0_LAYOUT,
+ 	.de_type	= sun8i_mixer_de2,
+@@ -875,6 +883,10 @@ static const struct of_device_id sun8i_mixer_of_table[] = {
+ 		.compatible = "allwinner,sun8i-h3-de2-mixer-0",
+ 		.data = &sun8i_h3_mixer0_cfg,
+ 	},
++	{
++		.compatible = "allwinner,sun8i-h3-de2-mixer-1",
++		.data = &sun8i_h3_mixer1_cfg,
++	},
+ 	{
+ 		.compatible = "allwinner,sun8i-r40-de2-mixer-0",
+ 		.data = &sun8i_r40_mixer0_cfg,
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-iio-adc-axp20x_adc-arm64-dts-axp803-hwmon-enable-thermal.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-iio-adc-axp20x_adc-arm64-dts-axp803-hwmon-enable-thermal.patch
new file mode 100644
index 000000000000..29eedec9bfa7
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-iio-adc-axp20x_adc-arm64-dts-axp803-hwmon-enable-thermal.patch
@@ -0,0 +1,184 @@
+From 5a07c1d98dd498c01308407c5a3fbd9291f2278a Mon Sep 17 00:00:00 2001
+From: Mitko Gamishev <hehopmajieh@debian.bg>
+Date: Wed, 5 Feb 2020 14:57:10 +0200
+Subject: drv:iio:adc:axp20x_adc arm64:dts:axp803 hwmon enable thermal
+
+---
+ arch/arm64/boot/dts/allwinner/axp803.dtsi |  1 +
+ drivers/iio/adc/axp20x_adc.c              | 90 +++++++++++++++++++++++
+ 2 files changed, 91 insertions(+)
+
+diff --git a/arch/arm64/boot/dts/allwinner/axp803.dtsi b/arch/arm64/boot/dts/allwinner/axp803.dtsi
+index a6b4b87f185d..422be59f5d88 100644
+--- a/arch/arm64/boot/dts/allwinner/axp803.dtsi
++++ b/arch/arm64/boot/dts/allwinner/axp803.dtsi
+@@ -19,6 +19,7 @@ ac_power_supply: ac-power {
+ 	axp_adc: adc {
+ 		compatible = "x-powers,axp803-adc", "x-powers,axp813-adc";
+ 		#io-channel-cells = <1>;
++		#thermal-sensor-cells = <0>;
+ 	};
+ 
+ 	axp_gpio: gpio {
+diff --git a/drivers/iio/adc/axp20x_adc.c b/drivers/iio/adc/axp20x_adc.c
+index 50eef565df2c..dda093076c1d 100644
+--- a/drivers/iio/adc/axp20x_adc.c
++++ b/drivers/iio/adc/axp20x_adc.c
+@@ -8,6 +8,7 @@
+ #include <linux/unaligned.h>
+ #include <linux/bitfield.h>
+ #include <linux/completion.h>
++#include <linux/hwmon.h>
+ #include <linux/interrupt.h>
+ #include <linux/io.h>
+ #include <linux/module.h>
+@@ -1005,6 +1006,73 @@ static int axp813_adc_rate(struct axp20x_adc_iio *info, int rate)
+ 				 AXP813_ADC_RATE_HZ(rate));
+ }
+ 
++static umode_t axp813_adc_hwmon_is_visible(const void *data,
++					   enum hwmon_sensor_types type,
++					   u32 attr, int channel)
++{
++	return (type == hwmon_temp && attr == hwmon_temp_input) ? 0444 : 0;
++}
++
++static int axp813_adc_hwmon_read(struct device *dev,
++				 enum hwmon_sensor_types type,
++				 u32 attr, int channel, long *temp)
++{
++	struct axp20x_adc_iio *info = dev_get_drvdata(dev);
++	int ret;
++	int raw;
++
++	switch (attr) {
++		case hwmon_temp_input:
++		raw = axp20x_read_variable_width(info->regmap, AXP22X_PMIC_TEMP_H, 12);
++		*temp = (raw - 2667) * 100;
++		ret = 0;
++		break;
++	default:
++		ret = -EOPNOTSUPP;
++		break;
++	}
++
++	return ret;
++}
++
++static u32 axp813_adc_hwmon_chip_config[] = {
++	HWMON_C_REGISTER_TZ,
++	0
++};
++
++static const struct hwmon_channel_info axp813_adc_hwmon_chip = {
++	.type = hwmon_chip,
++	.config = axp813_adc_hwmon_chip_config,
++};
++
++static u32 axp813_adc_hwmon_temp_config[] = {
++	HWMON_T_INPUT,
++	0
++};
++
++
++static const struct hwmon_channel_info axp813_adc_hwmon_temp = {
++	.type = hwmon_temp,
++	.config = axp813_adc_hwmon_temp_config,
++};
++
++
++static const struct hwmon_channel_info *axp813_adc_hwmon_info[] = {
++	&axp813_adc_hwmon_chip,
++	&axp813_adc_hwmon_temp,
++	NULL
++};
++
++static const struct hwmon_ops axp813_adc_hwmon_hwmon_ops = {
++	.is_visible = axp813_adc_hwmon_is_visible,
++	.read = axp813_adc_hwmon_read,
++};
++
++static const struct hwmon_chip_info axp813_adc_hwmon_chip_info = {
++	.ops = &axp813_adc_hwmon_hwmon_ops,
++	.info = axp813_adc_hwmon_info,
++};
++
+ struct axp_data {
+ 	const struct iio_info		*iio_info;
+ 	int				num_channels;
+@@ -1015,6 +1083,7 @@ struct axp_data {
+ 	unsigned long			adc_en2_mask;
+ 	int				(*adc_rate)(struct axp20x_adc_iio *info,
+ 						    int rate);
++	bool				hwmon_en;
+ 	const struct iio_map		*maps;
+ };
+ 
+@@ -1025,6 +1094,7 @@ static const struct axp_data axp192_data = {
+ 	.adc_en1_mask = AXP192_ADC_EN1_MASK,
+ 	.adc_en2_mask = AXP192_ADC_EN2_MASK,
+ 	.adc_rate = axp20x_adc_rate,
++	.hwmon_en = false,
+ 	.maps = axp20x_maps,
+ };
+ 
+@@ -1037,6 +1107,7 @@ static const struct axp_data axp20x_data = {
+ 	.adc_en2 = AXP20X_ADC_EN2,
+ 	.adc_en2_mask = AXP20X_ADC_EN2_MASK,
+ 	.adc_rate = axp20x_adc_rate,
++	.hwmon_en = false,
+ 	.maps = axp20x_maps,
+ };
+ 
+@@ -1047,6 +1118,7 @@ static const struct axp_data axp22x_data = {
+ 	.adc_en1 = AXP20X_ADC_EN1,
+ 	.adc_en1_mask = AXP22X_ADC_EN1_MASK,
+ 	.adc_rate = axp22x_adc_rate,
++	.hwmon_en = false,
+ 	.maps = axp22x_maps,
+ };
+ 
+@@ -1056,6 +1128,7 @@ static const struct axp_data axp717_data = {
+ 	.channels = axp717_adc_channels,
+ 	.adc_en1 = AXP717_ADC_CH_EN_CONTROL,
+ 	.adc_en1_mask = AXP717_ADC_EN1_MASK,
++	.hwmon_en = false,
+ 	.maps = axp717_maps,
+ };
+ 
+@@ -1066,6 +1139,7 @@ static const struct axp_data axp813_data = {
+ 	.adc_en1 = AXP20X_ADC_EN1,
+ 	.adc_en1_mask = AXP22X_ADC_EN1_MASK,
+ 	.adc_rate = axp813_adc_rate,
++	.hwmon_en = true,
+ 	.maps = axp22x_maps,
+ };
+ 
+@@ -1153,8 +1227,24 @@ static int axp20x_probe(struct platform_device *pdev)
+ 		goto fail_register;
+ 	}
+ 
++	if (info->data->hwmon_en) {
++		/* Register hwmon device */
++		struct device *hwmon_dev;
++
++		hwmon_dev = devm_hwmon_device_register_with_info(&pdev->dev, "axp813_adc",
++								 info, &axp813_adc_hwmon_chip_info, NULL);
++		if (IS_ERR(hwmon_dev)) {
++			ret = PTR_ERR(hwmon_dev);
++			dev_err(&pdev->dev, "unable to register hwmon device %d\n", ret);
++			goto fail_hwmon;
++		}
++	}
++
+ 	return 0;
+ 
++fail_hwmon:
++	iio_device_unregister(indio_dev);
++
+ fail_register:
+ 	iio_map_array_unregister(indio_dev);
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-input-touchscreen-sun4i-ts-Enable-parsing.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-input-touchscreen-sun4i-ts-Enable-parsing.patch
new file mode 100644
index 000000000000..210420d21880
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-input-touchscreen-sun4i-ts-Enable-parsing.patch
@@ -0,0 +1,63 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Mitko Gamishev <hehopmajieh@debian.bg>
+Date: Wed, 5 Feb 2020 15:18:04 +0200
+Subject: drv:input:touchscreen:sun4i-ts Enable parsing
+
+---
+ drivers/input/touchscreen/sun4i-ts.c | 19 ++++++++--
+ 1 file changed, 15 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/input/touchscreen/sun4i-ts.c b/drivers/input/touchscreen/sun4i-ts.c
+index 111111111111..222222222222 100644
+--- a/drivers/input/touchscreen/sun4i-ts.c
++++ b/drivers/input/touchscreen/sun4i-ts.c
+@@ -32,6 +32,7 @@
+ #include <linux/thermal.h>
+ #include <linux/init.h>
+ #include <linux/input.h>
++#include <linux/input/touchscreen.h>
+ #include <linux/interrupt.h>
+ #include <linux/io.h>
+ #include <linux/module.h>
+@@ -106,6 +107,7 @@
+ struct sun4i_ts_data {
+ 	struct device *dev;
+ 	struct input_dev *input;
++	struct touchscreen_properties prop;
+ 	void __iomem *base;
+ 	unsigned int irq;
+ 	bool ignore_fifo_data;
+@@ -123,8 +125,8 @@ static void sun4i_ts_irq_handle_input(struct sun4i_ts_data *ts, u32 reg_val)
+ 		y = readl(ts->base + TP_DATA);
+ 		/* The 1st location reported after an up event is unreliable */
+ 		if (!ts->ignore_fifo_data) {
+-			input_report_abs(ts->input, ABS_X, x);
+-			input_report_abs(ts->input, ABS_Y, y);
++			touchscreen_report_pos(ts->input, &ts->prop, x, y, false);
++
+ 			/*
+ 			 * The hardware has a separate down status bit, but
+ 			 * that gets set before we get the first location,
+@@ -296,8 +298,17 @@ static int sun4i_ts_probe(struct platform_device *pdev)
+ 		ts->input->id.version = 0x0100;
+ 		ts->input->evbit[0] =  BIT(EV_SYN) | BIT(EV_KEY) | BIT(EV_ABS);
+ 		__set_bit(BTN_TOUCH, ts->input->keybit);
+-		input_set_abs_params(ts->input, ABS_X, 0, 4095, 0, 0);
+-		input_set_abs_params(ts->input, ABS_Y, 0, 4095, 0, 0);
++
++		touchscreen_parse_properties(ts->input, false, &ts->prop);
++
++		if (!ts->prop.max_x || !ts->prop.max_y) {
++			dev_info(&pdev->dev, "Invalid configuration, using defaults\n");
++			ts->prop.max_x = 4095;
++			ts->prop.max_y = 4095;
++		}
++
++		input_set_abs_params(ts->input, ABS_X, 0, ts->prop.max_x, 0, 0);
++		input_set_abs_params(ts->input, ABS_Y, 0, ts->prop.max_y, 0, 0);
+ 		input_set_drvdata(ts->input, ts);
+ 	}
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-media-dvb-frontends-si2168-fix-cmd-timeout.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-media-dvb-frontends-si2168-fix-cmd-timeout.patch
new file mode 100644
index 000000000000..9072473622ad
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-media-dvb-frontends-si2168-fix-cmd-timeout.patch
@@ -0,0 +1,28 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Koumes <koumes@centrum.cz>
+Date: Sat, 1 Jun 2019 21:20:26 +0000
+Subject: drv:media:dvb-frontends:si2168: fix cmd timeout
+
+Some demuxer si2168 commands may take 130-140 ms.
+(DVB-T/T2 tuner MyGica T230C v2).
+Details: https://github.com/CoreELEC/CoreELEC/pull/208
+---
+ drivers/media/dvb-frontends/si2168.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/media/dvb-frontends/si2168.c b/drivers/media/dvb-frontends/si2168.c
+index 111111111111..222222222222 100644
+--- a/drivers/media/dvb-frontends/si2168.c
++++ b/drivers/media/dvb-frontends/si2168.c
+@@ -40,7 +40,7 @@ static int si2168_cmd_execute(struct i2c_client *client, struct si2168_cmd *cmd)
+ 
+ 	if (cmd->rlen) {
+ 		/* wait cmd execution terminate */
+-		#define TIMEOUT 70
++		#define TIMEOUT 200
+ 		timeout = jiffies + msecs_to_jiffies(TIMEOUT);
+ 		while (!time_after(jiffies, timeout)) {
+ 			ret = i2c_master_recv(client, cmd->args, cmd->rlen);
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-mfd-axp20x-add-sysfs-interface.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-mfd-axp20x-add-sysfs-interface.patch
new file mode 100644
index 000000000000..f9c3539405d6
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-mfd-axp20x-add-sysfs-interface.patch
@@ -0,0 +1,658 @@
+From e9c514407dd29d289792d6b84aa8da0b7a5cae8f Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Tue, 1 Feb 2022 21:38:26 +0300
+Subject: drv:mfd:axp20x add sysfs interface
+
+---
+ drivers/mfd/axp20x.c | 614 +++++++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 614 insertions(+)
+
+diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
+index 9be321c8aeae..3625cf1533c3 100644
+--- a/drivers/mfd/axp20x.c
++++ b/drivers/mfd/axp20x.c
+@@ -85,6 +85,7 @@ static const struct regmap_range axp20x_volatile_ranges[] = {
+ 	regmap_reg_range(AXP20X_IRQ1_EN, AXP20X_IRQ5_STATE),
+ 	regmap_reg_range(AXP20X_ACIN_V_ADC_H, AXP20X_IPSOUT_V_HIGH_L),
+ 	regmap_reg_range(AXP20X_GPIO20_SS, AXP20X_GPIO3_CTRL),
++	regmap_reg_range(AXP20X_CHRG_CC_31_24, AXP20X_DISCHRG_CC_7_0),
+ 	regmap_reg_range(AXP20X_FG_RES, AXP20X_RDC_L),
+ };
+ 
+@@ -1300,6 +1301,611 @@ static int axp20x_power_off(struct sys_off_data *data)
+ 	return NOTIFY_DONE;
+ }
+ 
++#define kobj_to_device(x) container_of(x, struct device, kobj)
++
++int axp20x_get_adc_freq(struct axp20x_dev *axp)
++{
++	unsigned int res;
++	int ret, freq = 25;
++
++	ret = regmap_read(axp->regmap, AXP20X_ADC_RATE, &res);
++	if (ret < 0) {
++		dev_warn(axp->dev, "Unable to read ADC sampling frequency: %d\n", ret);
++		return freq;
++	}
++	switch ((res & 0xC0) >> 6) {
++	case 0:
++		freq = 25;
++		break;
++	case 1:
++		freq = 50;
++		break;
++	case 2:
++		freq = 100;
++		break;
++	case 3:
++		freq = 200;
++		break;
++	}
++	return freq;
++}
++
++static ssize_t axp20x_sysfs_read_bin_file(struct file *filp,
++				struct kobject *kobj,
++				struct bin_attribute *bin_attr,
++				char *buf, loff_t off, size_t count)
++{
++	int ret;
++
++	struct device *dev = kobj_to_device(kobj);
++	struct axp20x_dev *axp = dev_get_drvdata(dev);
++
++	ret = regmap_raw_read(axp->regmap, AXP20X_OCV(off), buf, count);
++	if (ret < 0)
++	{
++		dev_warn(axp->dev, "read_bin_file: error reading: %d\n", ret);
++		return ret;
++	}
++	return count;
++}
++
++static ssize_t axp20x_sysfs_write_bin_file(struct file *filp,
++				struct kobject *kobj,
++				struct bin_attribute *bin_attr,
++				char *buf, loff_t off, size_t count)
++{
++	int ret;
++
++	struct device *dev = kobj_to_device(kobj);
++	struct axp20x_dev *axp = dev_get_drvdata(dev);
++
++	ret = regmap_raw_write(axp->regmap, AXP20X_OCV(off), buf, count);
++	if (ret < 0)
++	{
++		dev_warn(axp->dev, "write_bin_file: error writing: %d\n", ret);
++		return ret;
++	}
++	return count;
++}
++
++static ssize_t axp20x_read_special(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
++{
++	int i, freq, ret = 0;
++	unsigned int res;
++	u32 lval1, lval2;
++	s64 llval;
++	u64 ullval;
++
++	const char *subsystem = kobject_name(kobj);
++	struct device *dev = kobj_to_device(kobj->parent);
++	struct axp20x_dev *axp = dev_get_drvdata(dev);
++
++	dev_dbg(axp->dev, "read_special: reading attribute %s of object %s\n", attr->attr.name, subsystem);
++
++	if (strcmp(subsystem, "battery") == 0) {
++		if (strcmp(attr->attr.name, "power") == 0) {
++			lval1 = 0;
++			for (i = 0; i < 3; i++) {
++				ret |= regmap_read(axp->regmap, AXP20X_PWR_BATT_H + i, &res);
++				lval1 |= res << ((2 - i) * 8);
++			}
++			llval = lval1 * 1100 / 1000;
++		} else if (strcmp(attr->attr.name, "charge") == 0) {
++			ret = regmap_raw_read(axp->regmap, AXP20X_CHRG_CC_31_24, &lval1, sizeof(lval1));
++			ret |= regmap_raw_read(axp->regmap, AXP20X_DISCHRG_CC_31_24, &lval2, sizeof(lval2));
++			be32_to_cpus(&lval1);
++			be32_to_cpus(&lval2);
++			ullval = abs((s64)lval1 - (s64)lval2) * 65536 * 500;
++			freq = axp20x_get_adc_freq(axp);
++			do_div(ullval, 3600 * freq);
++			llval = (lval1 < lval2) ? -ullval : ullval;
++		} else if (strcmp(attr->attr.name, "capacity") == 0) {
++			ret = regmap_read(axp->regmap, AXP20X_FG_RES, &res);
++			llval = res & 0x7f;
++		} else
++			return -EINVAL;
++	} else
++		return -EINVAL;
++
++	if (ret < 0) {
++		dev_warn(axp->dev, "Unable to read parameter: %d\n", ret);
++		return ret;
++	}
++	return sprintf(buf, "%lld\n", llval);
++}
++
++static ssize_t axp20x_write_int(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, size_t count)
++{
++	int reg, var, ret = 0, scale, width = 12, offset = 0;
++	unsigned int res;
++
++	const char *subsystem = kobject_name(kobj);
++	struct device *dev = kobj_to_device(kobj->parent);
++	struct axp20x_dev *axp = dev_get_drvdata(dev);
++
++	dev_dbg(axp->dev, "write_int: writing attribute %s of object %s\n", attr->attr.name, subsystem);
++
++	ret = kstrtoint(buf, 10, &var);
++	if (ret < 0)
++		return ret;
++
++	if (strcmp(subsystem, "control") == 0) {
++		if (strcmp(attr->attr.name, "battery_rdc") == 0) {
++			reg = AXP20X_RDC_H;
++			scale = 1074;
++			width = 13;
++			offset = 537;
++			/* TODO: Disable & enable fuel gauge */
++		} else
++			return -EINVAL;
++	} else
++		return -EINVAL;
++
++	res = (var + offset) / scale;
++
++	ret = regmap_write_bits(axp->regmap, reg, (1U << (width - 8)) - 1, (res >> 8) & 0xFF);
++	ret |= regmap_write_bits(axp->regmap, reg + 1, 0xFF, res & 0xFF);
++
++	if (ret < 0) {
++		dev_warn(axp->dev, "Unable to write parameter: %d\n", ret);
++		return ret;
++	}
++	return count;
++}
++
++static ssize_t axp20x_read_bool(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
++{
++	int val, ret, reg, bit;
++	unsigned int res;
++
++	const char *subsystem = kobject_name(kobj);
++	struct device *dev = kobj_to_device(kobj->parent);
++	struct axp20x_dev *axp = dev_get_drvdata(dev);
++
++	dev_dbg(axp->dev, "read_bool: reading attribute %s of object %s\n", attr->attr.name, subsystem);
++
++	if (strcmp(subsystem, "ac") == 0) {
++		if (strcmp(attr->attr.name, "connected") == 0) {
++			reg = AXP20X_PWR_INPUT_STATUS;
++			bit = 7;
++		} else if (strcmp(attr->attr.name, "used") == 0) {
++			reg = AXP20X_PWR_INPUT_STATUS;
++			bit = 6;
++		} else
++			return -EINVAL;
++	} else if (strcmp(subsystem, "vbus") == 0) {
++		if (strcmp(attr->attr.name, "connected") == 0) {
++			reg = AXP20X_PWR_INPUT_STATUS;
++			bit = 5;
++		} else if (strcmp(attr->attr.name, "used") == 0) {
++			reg = AXP20X_PWR_INPUT_STATUS;
++			bit = 4;
++		} else if (strcmp(attr->attr.name, "strong") == 0) {
++			reg = AXP20X_PWR_INPUT_STATUS;
++			bit = 3;
++		} else
++			return -EINVAL;
++	} else if (strcmp(subsystem, "battery") == 0) {
++		if (strcmp(attr->attr.name, "connected") == 0) {
++			reg = AXP20X_PWR_OP_MODE;
++			bit = 5;
++		} else if (strcmp(attr->attr.name, "charging") == 0) {
++			reg = AXP20X_PWR_INPUT_STATUS;
++			bit = 2;
++		} else
++			return -EINVAL;
++	} else if (strcmp(subsystem, "pmu") == 0) {
++		if (strcmp(attr->attr.name, "overheat") == 0) {
++			reg = AXP20X_PWR_OP_MODE;
++			bit = 7;
++		} else
++			return -EINVAL;
++	} else if (strcmp(subsystem, "charger") == 0) {
++		if (strcmp(attr->attr.name, "charging") == 0) {
++			reg = AXP20X_PWR_OP_MODE;
++			bit = 6;
++		} else if (strcmp(attr->attr.name, "cell_activation") == 0) {
++			reg = AXP20X_PWR_OP_MODE;
++			bit = 3;
++		} else if (strcmp(attr->attr.name, "low_power") == 0) {
++			reg = AXP20X_PWR_OP_MODE;
++			bit = 2;
++		} else
++			return -EINVAL;
++	} else if (strcmp(subsystem, "control") == 0) {
++		if (strcmp(attr->attr.name, "set_vbus_direct_mode") == 0) {
++			reg = AXP20X_VBUS_IPSOUT_MGMT;
++			bit = 6;
++		} else if (strcmp(attr->attr.name, "reset_charge_counter") == 0) {
++			reg = AXP20X_CC_CTRL;
++			bit = 5;
++		} else if (strcmp(attr->attr.name, "charge_rtc_battery") == 0) {
++			reg = AXP20X_CHRG_BAK_CTRL;
++			bit = 7;
++		} else if (strcmp(attr->attr.name, "disable_fuel_gauge") == 0) {
++			reg = AXP20X_FG_RES;
++			bit = 7;
++		} else
++			return -EINVAL;
++	} else
++		return -EINVAL;
++
++	ret = regmap_read(axp->regmap, reg, &res);
++	if (ret < 0) {
++		dev_warn(axp->dev, "Unable to read parameter: %d\n", ret);
++		return ret;
++	}
++	val = (res & BIT(bit)) == BIT(bit) ? 1 : 0;
++	return sprintf(buf, "%d\n", val);
++}
++
++static ssize_t axp20x_write_bool(struct kobject *kobj, struct kobj_attribute *attr, const char *buf, size_t count)
++{
++	int var, ret, reg, bit;
++
++	const char *subsystem = kobject_name(kobj);
++	struct device *dev = kobj_to_device(kobj->parent);
++	struct axp20x_dev *axp = dev_get_drvdata(dev);
++
++	dev_dbg(axp->dev, "write_bool: writing attribute %s of object %s", attr->attr.name, subsystem);
++
++	ret = kstrtoint(buf, 10, &var);
++	if (ret < 0)
++		return ret;
++
++	if (strcmp(subsystem, "control") == 0) {
++		if (strcmp(attr->attr.name, "set_vbus_direct_mode") == 0) {
++			reg = AXP20X_VBUS_IPSOUT_MGMT;
++			bit = 6;
++		} else if (strcmp(attr->attr.name, "reset_charge_counter") == 0) {
++			reg = AXP20X_CC_CTRL;
++			bit = 5;
++		} else if (strcmp(attr->attr.name, "charge_rtc_battery") == 0) {
++			reg = AXP20X_CHRG_BAK_CTRL;
++			bit = 7;
++		} else if (strcmp(attr->attr.name, "disable_fuel_gauge") == 0) {
++			reg = AXP20X_FG_RES;
++			bit = 7;
++		} else
++			return -EINVAL;
++	} else
++		return -EINVAL;
++
++	ret = regmap_update_bits(axp->regmap, reg, BIT(bit), var ? BIT(bit) : 0);
++	if (ret)
++		dev_warn(axp->dev, "Unable to write value: %d", ret);
++	return count;
++}
++
++static int axp20x_averaging_helper(struct regmap *reg_map, int reg_h,
++	int width)
++{
++	long acc = 0;
++	int ret, i;
++
++	for (i = 0; i < 3; i++) {
++		ret = axp20x_read_variable_width(reg_map, reg_h, width);
++		if (ret < 0)
++			return ret;
++		acc += ret;
++		msleep(20); /* For 100Hz sampling frequency */
++	}
++	return (int)(acc / 3);
++}
++
++static ssize_t axp20x_read_int(struct kobject *kobj, struct kobj_attribute *attr, char *buf)
++{
++	int val, ret, scale, reg, width = 12, offset = 0;
++
++	const char *subsystem = kobject_name(kobj);
++	struct device *dev = kobj_to_device(kobj->parent);
++	struct axp20x_dev *axp = dev_get_drvdata(dev);
++
++	dev_dbg(axp->dev, "read_int: reading attribute %s of object %s\n", attr->attr.name, subsystem);
++
++	if (strcmp(subsystem, "ac") == 0) {
++		if (strcmp(attr->attr.name, "voltage") == 0) {
++			reg = AXP20X_ACIN_V_ADC_H;
++			scale = 1700;
++		} else if (strcmp(attr->attr.name, "amperage") == 0) {
++			reg = AXP20X_ACIN_I_ADC_H;
++			scale = 625;
++		} else
++			return -EINVAL;
++	} else if (strcmp(subsystem, "vbus") == 0) {
++		if (strcmp(attr->attr.name, "voltage") == 0) {
++			reg = AXP20X_VBUS_V_ADC_H;
++			scale = 1700;
++		} else if (strcmp(attr->attr.name, "amperage") == 0) {
++			reg = AXP20X_VBUS_I_ADC_H;
++			scale = 375;
++		} else
++			return -EINVAL;
++	} else if (strcmp(subsystem, "battery") == 0) {
++		if (strcmp(attr->attr.name, "voltage") == 0) {
++			reg = AXP20X_BATT_V_H;
++			scale = 1100;
++		} else if (strcmp(attr->attr.name, "amperage") == 0) {
++			reg = AXP20X_BATT_DISCHRG_I_H;
++			scale = 500;
++			width = 13;
++		} else if (strcmp(attr->attr.name, "ts_voltage") == 0) {
++			reg = AXP20X_TS_IN_H;
++			scale = 800;
++		} else
++			return -EINVAL;
++	} else if (strcmp(subsystem, "pmu") == 0) {
++		if (strcmp(attr->attr.name, "temp") == 0) {
++			reg = AXP20X_TEMP_ADC_H;
++			scale = 100;
++			offset = 144700;
++		} else if (strcmp(attr->attr.name, "voltage") == 0) {
++			reg = AXP20X_IPSOUT_V_HIGH_H;
++			scale = 1400;
++		} else
++			return -EINVAL;
++	} else if (strcmp(subsystem, "charger") == 0) {
++		if (strcmp(attr->attr.name, "amperage") == 0) {
++			reg = AXP20X_BATT_CHRG_I_H;
++			scale = 500;
++		} else
++			return -EINVAL;
++	} else if (strcmp(subsystem, "control") == 0) {
++		if (strcmp(attr->attr.name, "battery_rdc") == 0) {
++			reg = AXP20X_RDC_H;
++			width = 13;
++			scale = 1074;
++			offset = 537;
++		} else
++			return -EINVAL;
++	} else
++		return -EINVAL;
++
++	ret = axp20x_averaging_helper(axp->regmap, reg, width);
++
++	if (ret < 0) {
++		dev_warn(axp->dev, "Unable to read parameter: %d\n", ret);
++		return ret;
++	}
++	val = ret * scale - offset;
++	return sprintf(buf, "%d\n", val);
++}
++
++/* AC IN */
++static struct kobj_attribute ac_in_voltage = __ATTR(voltage, S_IRUGO, axp20x_read_int, NULL);
++static struct kobj_attribute ac_in_amperage = __ATTR(amperage, S_IRUGO, axp20x_read_int, NULL);
++static struct kobj_attribute ac_in_connected = __ATTR(connected, S_IRUGO, axp20x_read_bool, NULL);
++static struct kobj_attribute ac_in_used = __ATTR(used, S_IRUGO, axp20x_read_bool, NULL);
++
++static struct attribute *axp20x_attributes_ac[] = {
++	&ac_in_voltage.attr,
++	&ac_in_amperage.attr,
++	&ac_in_connected.attr,
++	&ac_in_used.attr,
++	NULL,
++};
++
++static const struct attribute_group axp20x_group_ac = {
++	.attrs = axp20x_attributes_ac,
++};
++
++/* Vbus */
++static struct kobj_attribute vbus_voltage = __ATTR(voltage, S_IRUGO, axp20x_read_int, NULL);
++static struct kobj_attribute vbus_amperage = __ATTR(amperage, S_IRUGO, axp20x_read_int, NULL);
++static struct kobj_attribute vbus_connected = __ATTR(connected, S_IRUGO, axp20x_read_bool, NULL);
++static struct kobj_attribute vbus_used = __ATTR(used, S_IRUGO, axp20x_read_bool, NULL);
++static struct kobj_attribute vbus_strong = __ATTR(strong, S_IRUGO, axp20x_read_bool, NULL);
++
++static struct attribute *axp20x_attributes_vbus[] = {
++	&vbus_voltage.attr,
++	&vbus_amperage.attr,
++	&vbus_connected.attr,
++	&vbus_used.attr,
++	&vbus_strong.attr,
++	NULL,
++};
++
++static const struct attribute_group axp20x_group_vbus = {
++	.attrs = axp20x_attributes_vbus,
++};
++
++/* Battery */
++static struct kobj_attribute batt_voltage = __ATTR(voltage, S_IRUGO, axp20x_read_int, NULL);
++static struct kobj_attribute batt_amperage = __ATTR(amperage, S_IRUGO, axp20x_read_int, NULL);
++static struct kobj_attribute batt_ts_voltage = __ATTR(ts_voltage, S_IRUGO, axp20x_read_int, NULL);
++static struct kobj_attribute batt_power = __ATTR(power, S_IRUGO, axp20x_read_special, NULL);
++static struct kobj_attribute batt_charge = __ATTR(charge, S_IRUGO, axp20x_read_special, NULL);
++static struct kobj_attribute batt_capacity = __ATTR(capacity, S_IRUGO, axp20x_read_special, NULL);
++static struct kobj_attribute batt_connected = __ATTR(connected, S_IRUGO, axp20x_read_bool, NULL);
++static struct kobj_attribute batt_charging = __ATTR(charging, S_IRUGO, axp20x_read_bool, NULL);
++
++static struct attribute *axp20x_attributes_battery[] = {
++	&batt_voltage.attr,
++	&batt_amperage.attr,
++	&batt_ts_voltage.attr,
++	&batt_power.attr,
++	&batt_charge.attr,
++	&batt_capacity.attr,
++	&batt_connected.attr,
++	&batt_charging.attr,
++	NULL,
++};
++
++static const struct attribute_group axp20x_group_battery = {
++	.attrs = axp20x_attributes_battery,
++};
++
++/* PMU */
++static struct kobj_attribute pmu_temp = __ATTR(temp, S_IRUGO, axp20x_read_int, NULL);
++static struct kobj_attribute pmu_voltage = __ATTR(voltage, S_IRUGO, axp20x_read_int, NULL);
++static struct kobj_attribute pmu_overheat = __ATTR(overheat, S_IRUGO, axp20x_read_bool, NULL);
++
++static struct attribute *axp20x_attributes_pmu[] = {
++	&pmu_temp.attr,
++	&pmu_voltage.attr,
++	&pmu_overheat.attr,
++	NULL,
++};
++
++static const struct attribute_group axp20x_group_pmu = {
++	.attrs = axp20x_attributes_pmu,
++};
++
++/* Charger */
++static struct kobj_attribute charger_amperage = __ATTR(amperage, S_IRUGO, axp20x_read_int, NULL);
++static struct kobj_attribute charger_charging = __ATTR(charging, S_IRUGO, axp20x_read_bool, NULL);
++static struct kobj_attribute charger_cell_activation = __ATTR(cell_activation, S_IRUGO, axp20x_read_bool, NULL);
++static struct kobj_attribute charger_low_power = __ATTR(low_power, S_IRUGO, axp20x_read_bool, NULL);
++
++static struct attribute *axp20x_attributes_charger[] = {
++	&charger_amperage.attr,
++	&charger_charging.attr,
++	&charger_cell_activation.attr,
++	&charger_low_power.attr,
++	NULL,
++};
++
++static const struct attribute_group axp20x_group_charger = {
++	.attrs = axp20x_attributes_charger,
++};
++
++/* Control (writeable) */
++static struct kobj_attribute control_vbus_direct_mode = __ATTR(set_vbus_direct_mode, (S_IRUGO | S_IWUSR),
++	axp20x_read_bool, axp20x_write_bool);
++static struct kobj_attribute control_reset_charge_counter = __ATTR(reset_charge_counter, (S_IRUGO | S_IWUSR),
++	axp20x_read_bool, axp20x_write_bool);
++static struct kobj_attribute control_charge_rtc_battery = __ATTR(charge_rtc_battery, (S_IRUGO | S_IWUSR),
++	axp20x_read_bool, axp20x_write_bool);
++static struct kobj_attribute control_disable_fuel_gauge = __ATTR(disable_fuel_gauge, (S_IRUGO | S_IWUSR),
++	axp20x_read_bool, axp20x_write_bool);
++static struct kobj_attribute control_battery_rdc = __ATTR(battery_rdc, (S_IRUGO | S_IWUSR),
++	axp20x_read_int, axp20x_write_int);
++
++static struct attribute *axp20x_attributes_control[] = {
++	&control_vbus_direct_mode.attr,
++	&control_reset_charge_counter.attr,
++	&control_charge_rtc_battery.attr,
++	&control_disable_fuel_gauge.attr,
++	&control_battery_rdc.attr,
++	NULL,
++};
++
++static const struct attribute_group axp20x_group_control = {
++	.attrs = axp20x_attributes_control,
++};
++
++static struct {
++	struct kobject *ac;
++	struct kobject *vbus;
++	struct kobject *battery;
++	struct kobject *pmu;
++	struct kobject *charger;
++	struct kobject *control;
++} subsystems;
++
++static struct bin_attribute axp20x_ocv_curve = __BIN_ATTR(ocv_curve, S_IRUGO | S_IWUSR,
++	axp20x_sysfs_read_bin_file, axp20x_sysfs_write_bin_file, AXP20X_OCV_MAX + 1);
++
++static void axp20x_sysfs_create_subgroup(const char name[], struct axp20x_dev *axp,
++	struct kobject *subgroup, const struct attribute_group *attrs)
++{
++	int ret;
++	struct kobject *parent = &axp->dev->kobj;
++	subgroup = kobject_create_and_add(name, parent);
++	if (subgroup != NULL) {
++		ret = sysfs_create_group(subgroup, attrs);
++		if (ret) {
++			dev_warn(axp->dev, "Unable to register sysfs group: %s: %d", name, ret);
++			kobject_put(subgroup);
++		}
++	}
++}
++
++static void axp20x_sysfs_remove_subgroup(struct kobject *subgroup,
++	const struct attribute_group *attrs)
++{
++	sysfs_remove_group(subgroup, attrs);
++	kobject_put(subgroup);
++}
++
++static int axp20x_sysfs_init(struct axp20x_dev *axp)
++{
++	int ret;
++	unsigned int res;
++
++	/* Enable all ADC channels in the first register */
++	ret = regmap_write(axp->regmap, AXP20X_ADC_EN1, 0xFF);
++	if (ret)
++		dev_warn(axp->dev, "Unable to enable ADC: %d", ret);
++
++	/*
++	 * Set ADC sampling frequency to 100Hz (default is 25)
++	 * Always measure battery temperature (default: only when charging)
++	 */
++	ret = regmap_update_bits(axp->regmap, AXP20X_ADC_RATE, 0xC3, 0x82);
++	if (ret)
++		dev_warn(axp->dev, "Unable to set ADC frequency and TS current output: %d", ret);
++
++	/* Enable fuel gauge and charge counter */
++	ret = regmap_update_bits(axp->regmap, AXP20X_FG_RES, 0x80, 0x00);
++	if (ret)
++		dev_warn(axp->dev, "Unable to enable battery fuel gauge: %d", ret);
++	/* ret = regmap_update_bits(axp->regmap, AXP20X_CC_CTRL, 0xC0, 0x00); */
++	ret |= regmap_update_bits(axp->regmap, AXP20X_CC_CTRL, 0xC0, 0x80);
++	if (ret)
++		dev_warn(axp->dev, "Unable to enable battery charge counter: %d", ret);
++
++	/* Enable battery detection */
++	ret = regmap_read(axp->regmap, AXP20X_OFF_CTRL, &res);
++	if (ret == 0) {
++		if ((res & 0x40) != 0x40) {
++			dev_info(axp->dev, "Battery detection is disabled, enabling");
++			ret = regmap_update_bits(axp->regmap, AXP20X_OFF_CTRL, 0x40, 0x40);
++			if (ret)
++				dev_warn(axp->dev, "Unable to enable battery detection: %d", ret);
++		}
++	} else
++		dev_warn(axp->dev, "Unable to read register AXP20X_OFF_CTRL: %d", ret);
++
++	/* Get info about backup (RTC) battery */
++	ret = regmap_read(axp->regmap, AXP20X_CHRG_BAK_CTRL, &res);
++	if (ret == 0) {
++		dev_info(axp->dev, "Backup (RTC) battery charging is %s",
++			(res & 0x80) == 0x80 ? "enabled" : "disabled");
++		if ((res & 0x60) != 0x20)
++			dev_warn(axp->dev, "Backup (RTC) battery target voltage is not 3.0V");
++	} else
++		dev_warn(axp->dev, "Unable to read register AXP20X_CHRG_BAK_CTRL: %d", ret);
++
++	axp20x_sysfs_create_subgroup("ac", axp, subsystems.ac, &axp20x_group_ac);
++	axp20x_sysfs_create_subgroup("vbus", axp, subsystems.vbus, &axp20x_group_vbus);
++	axp20x_sysfs_create_subgroup("battery", axp, subsystems.battery, &axp20x_group_battery);
++	axp20x_sysfs_create_subgroup("pmu", axp, subsystems.pmu, &axp20x_group_pmu);
++	axp20x_sysfs_create_subgroup("charger", axp, subsystems.charger, &axp20x_group_charger);
++	axp20x_sysfs_create_subgroup("control", axp, subsystems.control, &axp20x_group_control);
++
++	ret = sysfs_create_bin_file(&axp->dev->kobj, &axp20x_ocv_curve);
++	if (ret)
++		dev_warn(axp->dev, "Unable to create sysfs ocv_curve file: %d", ret);
++
++	ret = sysfs_create_link_nowarn(power_kobj, &axp->dev->kobj, "axp_pmu");
++	if (ret)
++		dev_warn(axp->dev, "Unable to create sysfs symlink: %d", ret);
++	return ret;
++}
++
++static void axp20x_sysfs_exit(struct axp20x_dev *axp)
++{
++	sysfs_delete_link(power_kobj, &axp->dev->kobj, "axp_pmu");
++	sysfs_remove_bin_file(&axp->dev->kobj, &axp20x_ocv_curve);
++	axp20x_sysfs_remove_subgroup(subsystems.control, &axp20x_group_control);
++	axp20x_sysfs_remove_subgroup(subsystems.charger, &axp20x_group_charger);
++	axp20x_sysfs_remove_subgroup(subsystems.pmu, &axp20x_group_pmu);
++	axp20x_sysfs_remove_subgroup(subsystems.battery, &axp20x_group_battery);
++	axp20x_sysfs_remove_subgroup(subsystems.vbus, &axp20x_group_vbus);
++	axp20x_sysfs_remove_subgroup(subsystems.ac, &axp20x_group_ac);
++}
++
+ int axp20x_match_device(struct axp20x_dev *axp20x)
+ {
+ 	struct device *dev = axp20x->dev;
+@@ -1500,6 +2106,10 @@ int axp20x_device_probe(struct axp20x_dev *axp20x)
+ 	if (axp20x->variant != AXP288_ID)
+ 		devm_register_power_off_handler(axp20x->dev, axp20x_power_off, axp20x);
+ 
++	if (axp20x->variant == AXP209_ID || axp20x->variant == AXP202_ID) {
++		axp20x_sysfs_init(axp20x);
++	}
++
+ 	dev_info(axp20x->dev, "AXP20X driver loaded\n");
+ 
+ 	return 0;
+@@ -1508,6 +2118,10 @@ EXPORT_SYMBOL(axp20x_device_probe);
+ 
+ void axp20x_device_remove(struct axp20x_dev *axp20x)
+ {
++	if (axp20x->variant == AXP209_ID || axp20x->variant == AXP202_ID) {
++		axp20x_sysfs_exit(axp20x);
++	}
++
+ 	mfd_remove_devices(axp20x->dev);
+ 	regmap_del_irq_chip(axp20x->irq, axp20x->regmap_irqc);
+ }
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-mmc-host-sunxi-mmc-Disable-DDR52-mode-on-all-A20-based-boar.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-mmc-host-sunxi-mmc-Disable-DDR52-mode-on-all-A20-based-boar.patch
new file mode 100644
index 000000000000..a13b28d3af2c
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-mmc-host-sunxi-mmc-Disable-DDR52-mode-on-all-A20-based-boar.patch
@@ -0,0 +1,27 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Mitko Gamishev <hehopmajieh@debian.bg>
+Date: Wed, 5 Feb 2020 15:31:25 +0200
+Subject: drv:mmc:host:sunxi-mmc Disable DDR52 mode on all A20 based boards
+
+---
+ drivers/mmc/host/sunxi-mmc.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
+index 111111111111..222222222222 100644
+--- a/drivers/mmc/host/sunxi-mmc.c
++++ b/drivers/mmc/host/sunxi-mmc.c
+@@ -1452,7 +1452,9 @@ static int sunxi_mmc_probe(struct platform_device *pdev)
+ 	 */
+ 	if ((host->cfg->clk_delays || host->use_new_timings) &&
+ 	    !of_device_is_compatible(pdev->dev.of_node,
+-				     "allwinner,sun50i-h5-emmc"))
++				     "allwinner,sun50i-h5-emmc") &&
++	    !of_machine_is_compatible("allwinner,sun7i-a20") &&
++	    !of_machine_is_compatible("olimex,a64-olinuxino-2ge8g"))
+ 		mmc->caps      |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR;
+ 
+ 	ret = mmc_of_parse(mmc);
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-mmc-host-sunxi-mmc-add-h5-emmc-compatible.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-mmc-host-sunxi-mmc-add-h5-emmc-compatible.patch
new file mode 100644
index 000000000000..5ad258142a8c
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-mmc-host-sunxi-mmc-add-h5-emmc-compatible.patch
@@ -0,0 +1,38 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Mon, 24 Jan 2022 13:26:03 +0300
+Subject: drv:mmc:host:sunxi-mmc: add h5 emmc compatible
+
+---
+ drivers/mmc/host/sunxi-mmc.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
+index 111111111111..222222222222 100644
+--- a/drivers/mmc/host/sunxi-mmc.c
++++ b/drivers/mmc/host/sunxi-mmc.c
+@@ -1197,6 +1197,13 @@ static const struct sunxi_mmc_cfg sun50i_a64_emmc_cfg = {
+ 	.needs_new_timings = true,
+ };
+ 
++static const struct sunxi_mmc_cfg sun50i_h5_emmc_cfg = {
++	.idma_des_size_bits = 13,
++	.clk_delays = NULL,
++	.can_calibrate = true,
++	.needs_new_timings = false,
++};
++
+ static const struct sunxi_mmc_cfg sun50i_h616_cfg = {
+ 	.idma_des_size_bits = 16,
+ 	.idma_des_shift = 2,
+@@ -1224,6 +1231,7 @@ static const struct of_device_id sunxi_mmc_of_match[] = {
+ 	{ .compatible = "allwinner,sun50i-a64-emmc", .data = &sun50i_a64_emmc_cfg },
+ 	{ .compatible = "allwinner,sun50i-a100-mmc", .data = &sun20i_d1_cfg },
+ 	{ .compatible = "allwinner,sun50i-a100-emmc", .data = &sun50i_a100_emmc_cfg },
++	{ .compatible = "allwinner,sun50i-h5-emmc", .data = &sun50i_h5_emmc_cfg },
+ 	{ .compatible = "allwinner,sun50i-h616-mmc", .data = &sun50i_h616_cfg },
+ 	{ /* sentinel */ }
+ };
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-mtd-nand-raw-nand_ids.c-add-H27UBG8T2BTR-BC-nand.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-mtd-nand-raw-nand_ids.c-add-H27UBG8T2BTR-BC-nand.patch
new file mode 100644
index 000000000000..d9516effcbd4
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-mtd-nand-raw-nand_ids.c-add-H27UBG8T2BTR-BC-nand.patch
@@ -0,0 +1,27 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Tue, 1 Feb 2022 19:47:29 +0300
+Subject: drv:mtd:nand:raw:nand_ids.c add H27UBG8T2BTR-BC nand
+
+---
+ drivers/mtd/nand/raw/nand_ids.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+diff --git a/drivers/mtd/nand/raw/nand_ids.c b/drivers/mtd/nand/raw/nand_ids.c
+index 111111111111..222222222222 100644
+--- a/drivers/mtd/nand/raw/nand_ids.c
++++ b/drivers/mtd/nand/raw/nand_ids.c
+@@ -50,6 +50,10 @@ struct nand_flash_dev nand_flash_ids[] = {
+ 	{"SDTNRGAMA 64G 3.3V 8-bit",
+ 		{ .id = {0x45, 0xde, 0x94, 0x93, 0x76, 0x50} },
+ 		  SZ_16K, SZ_8K, SZ_4M, 0, 6, 1280, NAND_ECC_INFO(40, SZ_1K) },
++	{"H27UBG8T2BTR-BC 32G 3.3V 8-bit",
++		{ .id = {0xad, 0xd7, 0x94, 0xda, 0x74, 0xc3} },
++		  SZ_8K, SZ_4K, SZ_2M, NAND_NEED_SCRAMBLING, 6, 640,
++		  NAND_ECC_INFO(40, SZ_1K) },
+ 	{"H27UCG8T2ATR-BC 64G 3.3V 8-bit",
+ 		{ .id = {0xad, 0xde, 0x94, 0xda, 0x74, 0xc4} },
+ 		  SZ_8K, SZ_8K, SZ_2M, NAND_NEED_SCRAMBLING, 6, 640,
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-net-stmmac-dwmac-sun8i-second-EMAC-clock-register.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-net-stmmac-dwmac-sun8i-second-EMAC-clock-register.patch
new file mode 100644
index 000000000000..a0c641833a85
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-net-stmmac-dwmac-sun8i-second-EMAC-clock-register.patch
@@ -0,0 +1,64 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Andre Przywara <andre.przywara@arm.com>
+Date: Thu, 10 Dec 2020 14:42:12 +0000
+Subject: drv:net:stmmac:dwmac-sun8i: second EMAC clock register
+
+The Allwinner H616 SoC has two EMAC controllers, with the second one
+being tied to the internal PHY, but also using a separate EMAC clock
+register.
+
+To tell the driver about which clock register to use, we add a parameter
+to our syscon phandle. The driver will use this value as an index into
+the regmap, so that we can address more than the first register, if
+needed.
+
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+---
+ drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 12 ++++++++--
+ 1 file changed, 10 insertions(+), 2 deletions(-)
+
+diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+index 111111111111..222222222222 100644
+--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
+@@ -1163,11 +1163,13 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
+ 	struct stmmac_resources stmmac_res;
+ 	struct sunxi_priv_data *gmac;
+ 	struct device *dev = &pdev->dev;
++	struct reg_field syscon_field;
+ 	phy_interface_t interface;
+ 	int ret;
+ 	struct stmmac_priv *priv;
+ 	struct net_device *ndev;
+ 	struct regmap *regmap;
++	u32 syscon_idx = 0;
+ 
+ 	ret = stmmac_get_platform_resources(pdev, &stmmac_res);
+ 	if (ret)
+@@ -1222,8 +1224,12 @@ static int sun8i_dwmac_probe(struct platform_device *pdev)
+ 		return ret;
+ 	}
+ 
+-	gmac->regmap_field = devm_regmap_field_alloc(dev, regmap,
+-						     *gmac->variant->syscon_field);
++	syscon_field = *gmac->variant->syscon_field;
++	ret = of_property_read_u32_index(pdev->dev.of_node, "syscon", 1,
++					 &syscon_idx);
++	if (!ret)
++		syscon_field.reg += syscon_idx * sizeof(u32);
++	gmac->regmap_field = devm_regmap_field_alloc(dev, regmap, syscon_field);
+ 	if (IS_ERR(gmac->regmap_field)) {
+ 		ret = PTR_ERR(gmac->regmap_field);
+ 		dev_err(dev, "Unable to map syscon register: %d\n", ret);
+@@ -1348,6 +1354,8 @@ static const struct of_device_id sun8i_dwmac_match[] = {
+ 		.data = &emac_variant_a64 },
+ 	{ .compatible = "allwinner,sun50i-h6-emac",
+ 		.data = &emac_variant_h6 },
++	{ .compatible = "allwinner,sun50i-h616-emac",
++		.data = &emac_variant_h6 },
+ 	{ }
+ };
+ MODULE_DEVICE_TABLE(of, sun8i_dwmac_match);
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-nvmem-sunxi_sid-Support-SID-on-H616.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-nvmem-sunxi_sid-Support-SID-on-H616.patch
new file mode 100644
index 000000000000..42f18986aa34
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-nvmem-sunxi_sid-Support-SID-on-H616.patch
@@ -0,0 +1,41 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Kali Prasad <kprasadvnsi@protonmail.com>
+Date: Sun, 19 Sep 2021 08:02:27 +0000
+Subject: drv:nvmem:sunxi_sid: Support SID on H616
+
+Add support for H616's SID controller. It supports 4K-bit
+EFUSE.
+
+Signed-off-by: Kali Prasad <kprasadvnsi@protonmail.com>
+---
+ drivers/nvmem/sunxi_sid.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/drivers/nvmem/sunxi_sid.c b/drivers/nvmem/sunxi_sid.c
+index 111111111111..222222222222 100644
+--- a/drivers/nvmem/sunxi_sid.c
++++ b/drivers/nvmem/sunxi_sid.c
+@@ -205,6 +205,12 @@ static const struct sunxi_sid_cfg sun50i_h6_cfg = {
+ 	.size = 0x200,
+ };
+ 
++static const struct sunxi_sid_cfg sun50i_h616_cfg = {
++	.value_offset = 0x200,
++	.size = 0x100,
++	.need_register_readout = true,
++};
++
+ static const struct of_device_id sunxi_sid_of_match[] = {
+ 	{ .compatible = "allwinner,sun4i-a10-sid", .data = &sun4i_a10_cfg },
+ 	{ .compatible = "allwinner,sun7i-a20-sid", .data = &sun7i_a20_cfg },
+@@ -214,6 +220,7 @@ static const struct of_device_id sunxi_sid_of_match[] = {
+ 	{ .compatible = "allwinner,sun50i-a64-sid", .data = &sun50i_a64_cfg },
+ 	{ .compatible = "allwinner,sun50i-h5-sid", .data = &sun50i_a64_cfg },
+ 	{ .compatible = "allwinner,sun50i-h6-sid", .data = &sun50i_h6_cfg },
++	{ .compatible = "allwinner,sun50i-h616-sid", .data = &sun50i_h616_cfg },
+ 	{/* sentinel */},
+ };
+ MODULE_DEVICE_TABLE(of, sunxi_sid_of_match);
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-of-Device-Tree-Overlay-ConfigFS-interface.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-of-Device-Tree-Overlay-ConfigFS-interface.patch
new file mode 100644
index 000000000000..c7240c78a743
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-of-Device-Tree-Overlay-ConfigFS-interface.patch
@@ -0,0 +1,343 @@
+From 0bfb8399d8b4f46ac87a2ae980126ca2c6c6cb1f Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Tue, 1 Feb 2022 19:22:21 +0300
+Subject: drv:of: Device Tree Overlay ConfigFS interface
+
+---
+ drivers/of/Kconfig       |   7 +
+ drivers/of/Makefile      |   1 +
+ drivers/of/configfs.c    | 278 +++++++++++++++++++++++++++++++++++++++
+ drivers/of/fdt_address.c |   2 +-
+ 4 files changed, 287 insertions(+), 1 deletion(-)
+ create mode 100644 drivers/of/configfs.c
+
+diff --git a/drivers/of/Kconfig b/drivers/of/Kconfig
+index 50697cc3b07e..f9d2fc56fc41 100644
+--- a/drivers/of/Kconfig
++++ b/drivers/of/Kconfig
+@@ -123,6 +123,13 @@ config OF_OVERLAY_KUNIT_TEST
+ 
+ 	  If unsure, say N here, but this option is safe to enable.
+ 
++config OF_CONFIGFS
++        bool "Device Tree Overlay ConfigFS interface"
++        select CONFIGFS_FS
++        depends on OF_OVERLAY
++        help
++          Enable a simple user-space driven DT overlay interface.
++
+ config OF_NUMA
+ 	bool
+ 
+diff --git a/drivers/of/Makefile b/drivers/of/Makefile
+index 379a0afcbdc0..2be9021017ba 100644
+--- a/drivers/of/Makefile
++++ b/drivers/of/Makefile
+@@ -11,6 +11,7 @@ obj-$(CONFIG_OF_UNITTEST) += unittest.o
+ obj-$(CONFIG_OF_RESERVED_MEM) += of_reserved_mem.o
+ obj-$(CONFIG_OF_RESOLVE)  += resolver.o
+ obj-$(CONFIG_OF_OVERLAY) += overlay.o
++obj-$(CONFIG_OF_CONFIGFS) += configfs.o
+ obj-$(CONFIG_OF_NUMA) += of_numa.o
+ 
+ ifdef CONFIG_KEXEC_FILE
+diff --git a/drivers/of/configfs.c b/drivers/of/configfs.c
+new file mode 100644
+index 000000000000..87974779561f
+--- /dev/null
++++ b/drivers/of/configfs.c
+@@ -0,0 +1,278 @@
++/*
++ * Configfs entries for device-tree
++ *
++ * Copyright (C) 2013 - Pantelis Antoniou <panto@antoniou-consulting.com>
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version
++ * 2 of the License, or (at your option) any later version.
++ */
++#include <linux/ctype.h>
++#include <linux/cpu.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_fdt.h>
++#include <linux/spinlock.h>
++#include <linux/slab.h>
++#include <linux/proc_fs.h>
++#include <linux/configfs.h>
++#include <linux/types.h>
++#include <linux/stat.h>
++#include <linux/limits.h>
++#include <linux/file.h>
++#include <linux/vmalloc.h>
++#include <linux/firmware.h>
++#include <linux/sizes.h>
++
++#include "of_private.h"
++
++struct cfs_overlay_item {
++	struct config_item	item;
++
++	char			path[PATH_MAX];
++
++	const struct firmware	*fw;
++	struct device_node	*overlay;
++	int			ov_id;
++
++	void			*dtbo;
++	int			dtbo_size;
++};
++
++static inline struct cfs_overlay_item *to_cfs_overlay_item(
++		struct config_item *item)
++{
++	return item ? container_of(item, struct cfs_overlay_item, item) : NULL;
++}
++
++static ssize_t cfs_overlay_item_path_show(struct config_item *item,
++		char *page)
++{
++	struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
++	return sprintf(page, "%s\n", overlay->path);
++}
++
++static ssize_t cfs_overlay_item_path_store(struct config_item *item,
++		const char *page, size_t count)
++{
++	struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
++	const char *p = page;
++	char *s;
++	int err;
++
++	/* if it's set do not allow changes */
++	if (overlay->path[0] != '\0' || overlay->dtbo_size > 0)
++		return -EPERM;
++
++	/* copy to path buffer (and make sure it's always zero terminated */
++	count = snprintf(overlay->path, sizeof(overlay->path) - 1, "%s", p);
++	overlay->path[sizeof(overlay->path) - 1] = '\0';
++
++	/* strip trailing newlines */
++	s = overlay->path + strlen(overlay->path);
++	while (s > overlay->path && *--s == '\n')
++		*s = '\0';
++
++	pr_debug("%s: path is '%s'\n", __func__, overlay->path);
++
++	err = request_firmware(&overlay->fw, overlay->path, NULL);
++	if (err != 0)
++		goto out_err;
++
++	err = of_overlay_fdt_apply((void *)overlay->fw->data,
++				   (u32)overlay->fw->size,
++				   &overlay->ov_id, NULL);
++	if (err != 0)
++		goto out_err;
++
++	return count;
++
++out_err:
++
++	release_firmware(overlay->fw);
++	overlay->fw = NULL;
++
++	overlay->path[0] = '\0';
++	return err;
++}
++
++static ssize_t cfs_overlay_item_status_show(struct config_item *item,
++		char *page)
++{
++	struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
++
++	return sprintf(page, "%s\n",
++			overlay->ov_id > 0 ? "applied" : "unapplied");
++}
++
++CONFIGFS_ATTR(cfs_overlay_item_, path);
++CONFIGFS_ATTR_RO(cfs_overlay_item_, status);
++
++static struct configfs_attribute *cfs_overlay_attrs[] = {
++	&cfs_overlay_item_attr_path,
++	&cfs_overlay_item_attr_status,
++	NULL,
++};
++
++ssize_t cfs_overlay_item_dtbo_read(struct config_item *item,
++		void *buf, size_t max_count)
++{
++	struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
++
++	pr_debug("%s: buf=%p max_count=%zu\n", __func__,
++			buf, max_count);
++
++	if (overlay->dtbo == NULL)
++		return 0;
++
++	/* copy if buffer provided */
++	if (buf != NULL) {
++		/* the buffer must be large enough */
++		if (overlay->dtbo_size > max_count)
++			return -ENOSPC;
++
++		memcpy(buf, overlay->dtbo, overlay->dtbo_size);
++	}
++
++	return overlay->dtbo_size;
++}
++
++ssize_t cfs_overlay_item_dtbo_write(struct config_item *item,
++		const void *buf, size_t count)
++{
++	struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
++	int err;
++
++	/* if it's set do not allow changes */
++	if (overlay->path[0] != '\0' || overlay->dtbo_size > 0)
++		return -EPERM;
++
++	/* copy the contents */
++	overlay->dtbo = kmemdup(buf, count, GFP_KERNEL);
++	if (overlay->dtbo == NULL)
++		return -ENOMEM;
++
++	overlay->dtbo_size = count;
++
++	err = of_overlay_fdt_apply(overlay->dtbo, overlay->dtbo_size,
++				   &overlay->ov_id, NULL);
++	if (err != 0)
++		goto out_err;
++
++	return count;
++
++out_err:
++	kfree(overlay->dtbo);
++	overlay->dtbo = NULL;
++	overlay->dtbo_size = 0;
++	overlay->ov_id = 0;
++
++	return err;
++}
++
++CONFIGFS_BIN_ATTR(cfs_overlay_item_, dtbo, NULL, SZ_1M);
++
++static struct configfs_bin_attribute *cfs_overlay_bin_attrs[] = {
++	&cfs_overlay_item_attr_dtbo,
++	NULL,
++};
++
++static void cfs_overlay_release(struct config_item *item)
++{
++	struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
++
++	if (overlay->ov_id > 0)
++		of_overlay_remove(&overlay->ov_id);
++	if (overlay->fw)
++		release_firmware(overlay->fw);
++	/* kfree with NULL is safe */
++	kfree(overlay->dtbo);
++	kfree(overlay);
++}
++
++static struct configfs_item_operations cfs_overlay_item_ops = {
++	.release	= cfs_overlay_release,
++};
++
++static struct config_item_type cfs_overlay_type = {
++	.ct_item_ops	= &cfs_overlay_item_ops,
++	.ct_attrs	= cfs_overlay_attrs,
++	.ct_bin_attrs	= cfs_overlay_bin_attrs,
++	.ct_owner	= THIS_MODULE,
++};
++
++static struct config_item *cfs_overlay_group_make_item(
++		struct config_group *group, const char *name)
++{
++	struct cfs_overlay_item *overlay;
++
++	overlay = kzalloc(sizeof(*overlay), GFP_KERNEL);
++	if (!overlay)
++		return ERR_PTR(-ENOMEM);
++
++	config_item_init_type_name(&overlay->item, name, &cfs_overlay_type);
++	return &overlay->item;
++}
++
++static void cfs_overlay_group_drop_item(struct config_group *group,
++		struct config_item *item)
++{
++	struct cfs_overlay_item *overlay = to_cfs_overlay_item(item);
++
++	config_item_put(&overlay->item);
++}
++
++static struct configfs_group_operations overlays_ops = {
++	.make_item	= cfs_overlay_group_make_item,
++	.drop_item	= cfs_overlay_group_drop_item,
++};
++
++static struct config_item_type overlays_type = {
++	.ct_group_ops   = &overlays_ops,
++	.ct_owner       = THIS_MODULE,
++};
++
++static struct configfs_group_operations of_cfs_ops = {
++	/* empty - we don't allow anything to be created */
++};
++
++static struct config_item_type of_cfs_type = {
++	.ct_group_ops   = &of_cfs_ops,
++	.ct_owner       = THIS_MODULE,
++};
++
++struct config_group of_cfs_overlay_group;
++
++static struct configfs_subsystem of_cfs_subsys = {
++	.su_group = {
++		.cg_item = {
++			.ci_namebuf = "device-tree",
++			.ci_type = &of_cfs_type,
++		},
++	},
++	.su_mutex = __MUTEX_INITIALIZER(of_cfs_subsys.su_mutex),
++};
++
++static int __init of_cfs_init(void)
++{
++	int ret;
++
++	pr_info("%s\n", __func__);
++
++	config_group_init(&of_cfs_subsys.su_group);
++	config_group_init_type_name(&of_cfs_overlay_group, "overlays",
++			&overlays_type);
++	configfs_add_default_group(&of_cfs_overlay_group,
++			&of_cfs_subsys.su_group);
++
++	ret = configfs_register_subsystem(&of_cfs_subsys);
++	if (ret != 0) {
++		pr_err("%s: failed to register subsys\n", __func__);
++		goto out;
++	}
++	pr_info("%s: OK\n", __func__);
++out:
++	return ret;
++}
++late_initcall(of_cfs_init);
+diff --git a/drivers/of/fdt_address.c b/drivers/of/fdt_address.c
+index f358d2c80754..e1353d7a58e6 100644
+--- a/drivers/of/fdt_address.c
++++ b/drivers/of/fdt_address.c
+@@ -147,7 +147,7 @@ static int __init fdt_translate_one(const void *blob, int parent,
+  * that can be mapped to a cpu physical address). This is not really specified
+  * that way, but this is traditionally the way IBM at least do things
+  */
+-static u64 __init fdt_translate_address(const void *blob, int node_offset)
++u64 __init fdt_translate_address(const void *blob, int node_offset)
+ {
+ 	int parent, len;
+ 	const struct of_bus *bus, *pbus;
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-phy-sun4i-usb-Allow-reset-line-to-be-shared.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-phy-sun4i-usb-Allow-reset-line-to-be-shared.patch
new file mode 100644
index 000000000000..3076b4b20931
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-phy-sun4i-usb-Allow-reset-line-to-be-shared.patch
@@ -0,0 +1,36 @@
+From 711fd07f4f2fb4697271dd78076e2d4c6092c685 Mon Sep 17 00:00:00 2001
+From: Andre Przywara <andre.przywara@arm.com>
+Date: Mon, 10 May 2021 11:01:31 +0100
+Subject: drv:phy: sun4i-usb: Allow reset line to be shared
+
+The USB HCIs (and PHYs?) in Allwinner's newer generation SoCs (H616)
+rely on the reset line of USB PHY 2 to be de-asserted, even when only
+one of the other PHYs is actually in use.
+
+To make those ports work, we include this reset line in the HCIs' resets
+property, which requires this line to be shareable.
+
+Change the call to allocate the reset line to mark it as shared, to
+enable the other ports on those SoCs.
+
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+---
+ drivers/phy/allwinner/phy-sun4i-usb.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c
+index 3d8d94594bc5..79bce901fa21 100644
+--- a/drivers/phy/allwinner/phy-sun4i-usb.c
++++ b/drivers/phy/allwinner/phy-sun4i-usb.c
+@@ -865,7 +865,7 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
+ 		}
+ 
+ 		snprintf(name, sizeof(name), "usb%d_reset", i);
+-		phy->reset = devm_reset_control_get(dev, name);
++		phy->reset = devm_reset_control_get_shared(dev, name);
+ 		if (IS_ERR(phy->reset)) {
+ 			dev_err(dev, "failed to get reset %s\n", name);
+ 			return PTR_ERR(phy->reset);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-pinctrl-pinctrl-sun50i-a64-disable_strict_mode.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-pinctrl-pinctrl-sun50i-a64-disable_strict_mode.patch
new file mode 100644
index 000000000000..71e8109b7e26
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-pinctrl-pinctrl-sun50i-a64-disable_strict_mode.patch
@@ -0,0 +1,30 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: WaterByWind <WaterByWind@users.noreply.github.com>
+Date: Sun, 14 Apr 2019 16:16:09 -0400
+Subject: drv:pinctrl: pinctrl-sun50i-a64 disable_strict_mode
+
+With kernel 4.15.y (and later):
+*  Strict mode was enabled by default via commit 1396007286b1e2fd5dd10ae6a5ccaaaed51ab762 which can/will cause breakage with existing implementations.
+* The ability to configure strict mode was added via commit aae842a3ff3385f27f1df8a9ee1494a416ec032d to allow older drivers to maintain existing behavior and avoid breakage.
+* Commit cd70387f892205bcd7b8093b0837269b0739cbe0 had then explicitly disabled strict mode for most other existing SoCs but did not include A64.
+
+This change is to update the A64 pinctrl driver similar to the other pre-existing SoC pinctrl drivers.
+---
+ drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c
+index 111111111111..222222222222 100644
+--- a/drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c
++++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-a64.c
+@@ -577,6 +577,7 @@ static const struct sunxi_pinctrl_desc a64_pinctrl_data = {
+ 	.pins = a64_pins,
+ 	.npins = ARRAY_SIZE(a64_pins),
+ 	.irq_banks = 3,
++	.disable_strict_mode = true,
+ };
+ 
+ static int a64_pinctrl_probe(struct platform_device *pdev)
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-pinctrl-sunxi-pinctrl-sun50i-h6.c-GPIO-disable_strict_mode.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-pinctrl-sunxi-pinctrl-sun50i-h6.c-GPIO-disable_strict_mode.patch
new file mode 100644
index 000000000000..a747b73c35cd
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-pinctrl-sunxi-pinctrl-sun50i-h6.c-GPIO-disable_strict_mode.patch
@@ -0,0 +1,24 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Tue, 1 Feb 2022 19:11:11 +0300
+Subject: drv:pinctrl:sunxi:pinctrl-sun50i-h6.c GPIO disable_strict_mode
+
+---
+ drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c
+index 111111111111..222222222222 100644
+--- a/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c
++++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c
+@@ -587,6 +587,7 @@ static const unsigned int h6_irq_bank_map[] = { 1, 5, 6, 7 };
+ static const struct sunxi_pinctrl_desc h6_pinctrl_data = {
+ 	.pins = h6_pins,
+ 	.npins = ARRAY_SIZE(h6_pins),
++	.disable_strict_mode = true,
+ 	.irq_banks = 4,
+ 	.irq_bank_map = h6_irq_bank_map,
+ 	.irq_read_needs_mux = true,
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-rtc-sun6i-Add-Allwinner-H616-support.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-rtc-sun6i-Add-Allwinner-H616-support.patch
new file mode 100644
index 000000000000..2c5347b664e5
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-rtc-sun6i-Add-Allwinner-H616-support.patch
@@ -0,0 +1,45 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Andre Przywara <andre.przywara@arm.com>
+Date: Wed, 21 Apr 2021 12:46:43 +0100
+Subject: drv:rtc: sun6i: Add Allwinner H616 support
+
+The H616 RTC changes its day storage to the newly introduced linear day
+scheme, so pair the new compatible string with this feature flag.
+The clock part is missing an external 32768 Hz oscillator input pin,
+for future expansion we must thus ignore any provided clock for now.
+
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+---
+ drivers/rtc/rtc-sun6i.c | 16 ++++++++++
+ 1 file changed, 16 insertions(+)
+
+diff --git a/drivers/rtc/rtc-sun6i.c b/drivers/rtc/rtc-sun6i.c
+index 111111111111..222222222222 100644
+--- a/drivers/rtc/rtc-sun6i.c
++++ b/drivers/rtc/rtc-sun6i.c
+@@ -389,6 +389,22 @@ static void __init sun50i_h6_rtc_clk_init(struct device_node *node)
+ CLK_OF_DECLARE_DRIVER(sun50i_h6_rtc_clk, "allwinner,sun50i-h6-rtc",
+ 		      sun50i_h6_rtc_clk_init);
+ 
++static const struct sun6i_rtc_clk_data sun50i_h616_rtc_data = {
++	.rc_osc_rate = 16000000,
++	.fixed_prescaler = 32,
++	.has_prescaler = 1,
++	.has_out_clk = 1,
++	.no_ext_losc = 1,
++};
++
++static void __init sun50i_h616_rtc_clk_init(struct device_node *node)
++{
++	sun6i_rtc_clk_init(node, &sun50i_h616_rtc_data);
++}
++
++CLK_OF_DECLARE_DRIVER(sun50i_h616_rtc_clk, "allwinner,sun50i-h616-rtc",
++		      sun50i_h616_rtc_clk_init);
++
+ /*
+  * The R40 user manual is self-conflicting on whether the prescaler is
+  * fixed or configurable. The clock diagram shows it as fixed, but there
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-rtc-sun6i-support-RTCs-without-external-LOSCs.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-rtc-sun6i-support-RTCs-without-external-LOSCs.patch
new file mode 100644
index 000000000000..0b461ac43e04
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-rtc-sun6i-support-RTCs-without-external-LOSCs.patch
@@ -0,0 +1,68 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Andre Przywara <andre.przywara@arm.com>
+Date: Mon, 14 Jun 2021 23:02:45 +0100
+Subject: drv:rtc:sun6i: support RTCs without external LOSCs
+
+Some newer Allwinner RTCs (for instance the one in the H616 SoC) lack
+a pin for an external 32768 Hz oscillator. As a consequence, this LOSC
+can't be selected as the RTC clock source, and we must rely on the
+internal RC oscillator.
+To allow additions of clocks to the RTC node, add a feature bit to ignore
+any provided clocks for now (the current code would think this is the
+external LOSC). Later DTs and code can then for instance add the PLL
+based clock input, and older kernel won't get confused.
+
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ drivers/rtc/rtc-sun6i.c | 16 +++++++---
+ 1 file changed, 11 insertions(+), 5 deletions(-)
+
+diff --git a/drivers/rtc/rtc-sun6i.c b/drivers/rtc/rtc-sun6i.c
+index 111111111111..222222222222 100644
+--- a/drivers/rtc/rtc-sun6i.c
++++ b/drivers/rtc/rtc-sun6i.c
+@@ -137,6 +137,7 @@ struct sun6i_rtc_clk_data {
+ 	unsigned int has_out_clk : 1;
+ 	unsigned int has_losc_en : 1;
+ 	unsigned int has_auto_swt : 1;
++	unsigned int no_ext_losc : 1;
+ };
+ 
+ #define RTC_LINEAR_DAY	BIT(0)
+@@ -260,7 +261,7 @@ static void __init sun6i_rtc_clk_init(struct device_node *node,
+ 	}
+ 
+ 	/* Switch to the external, more precise, oscillator, if present */
+-	if (of_property_present(node, "clocks")) {
++	if (!rtc->data->no_ext_losc && of_get_property(node, "clocks", NULL)) {
+ 		reg |= SUN6I_LOSC_CTRL_EXT_OSC;
+ 		if (rtc->data->has_losc_en)
+ 			reg |= SUN6I_LOSC_CTRL_EXT_LOSC_EN;
+@@ -284,14 +285,19 @@ static void __init sun6i_rtc_clk_init(struct device_node *node,
+ 	}
+ 
+ 	parents[0] = clk_hw_get_name(rtc->int_osc);
+-	/* If there is no external oscillator, this will be NULL and ... */
+-	parents[1] = of_clk_get_parent_name(node, 0);
++	if (rtc->data->no_ext_losc) {
++		parents[1] = NULL;
++		init.num_parents = 1;
++	} else {
++		/* If there is no external oscillator, this will be NULL and */
++		parents[1] = of_clk_get_parent_name(node, 0);
++		/* ... number of clock parents will be 1. */
++		init.num_parents = of_clk_get_parent_count(node) + 1;
++	}
+ 
+ 	rtc->hw.init = &init;
+ 
+ 	init.parent_names = parents;
+-	/* ... number of clock parents will be 1. */
+-	init.num_parents = of_clk_get_parent_count(node) + 1;
+ 	of_property_read_string_index(node, "clock-output-names", 0,
+ 				      &init.name);
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-soc-sunxi-sram-Add-SRAM-C1-H616-handling.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-soc-sunxi-sram-Add-SRAM-C1-H616-handling.patch
new file mode 100644
index 000000000000..5f140dd858c0
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-soc-sunxi-sram-Add-SRAM-C1-H616-handling.patch
@@ -0,0 +1,41 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Sat, 16 Oct 2021 21:26:41 +0200
+Subject: drv:soc: sunxi: sram: Add SRAM C1 H616 handling
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ drivers/soc/sunxi/sunxi_sram.c | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+diff --git a/drivers/soc/sunxi/sunxi_sram.c b/drivers/soc/sunxi/sunxi_sram.c
+index 111111111111..222222222222 100644
+--- a/drivers/soc/sunxi/sunxi_sram.c
++++ b/drivers/soc/sunxi/sunxi_sram.c
+@@ -69,6 +69,12 @@ static struct sunxi_sram_desc sun4i_a10_sram_c1 = {
+ 				  SUNXI_SRAM_MAP(0x7fffffff, 1, "ve")),
+ };
+ 
++static struct sunxi_sram_desc sun50i_h616_sram_c1 = {
++	.data	= SUNXI_SRAM_DATA("C1", 0x0, 0x0, 31,
++				  SUNXI_SRAM_MAP(0x7fffffff, 0, "cpu"),
++				  SUNXI_SRAM_MAP(0, 1, "ve")),
++};
++
+ static struct sunxi_sram_desc sun4i_a10_sram_d = {
+ 	.data	= SUNXI_SRAM_DATA("D", 0x4, 0x0, 1,
+ 				  SUNXI_SRAM_MAP(0, 0, "cpu"),
+@@ -98,6 +104,10 @@ static const struct of_device_id sunxi_sram_dt_ids[] = {
+ 		.compatible	= "allwinner,sun50i-a64-sram-c",
+ 		.data		= &sun50i_a64_sram_c.data,
+ 	},
++	{
++		.compatible	= "allwinner,sun50i-h616-sram-c1",
++		.data		= &sun50i_h616_sram_c1.data,
++	},
+ 	{}
+ };
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-spi-spi-sun4i.c-spi-bug-low-on-sck.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-spi-spi-sun4i.c-spi-bug-low-on-sck.patch
new file mode 100644
index 000000000000..1635a395fd9a
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-spi-spi-sun4i.c-spi-bug-low-on-sck.patch
@@ -0,0 +1,36 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Wed, 2 Feb 2022 14:16:31 +0300
+Subject: drv:spi:spi-sun4i.c spi bug low on sck
+
+---
+ drivers/spi/spi-sun4i.c | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/spi/spi-sun4i.c b/drivers/spi/spi-sun4i.c
+index 111111111111..222222222222 100644
+--- a/drivers/spi/spi-sun4i.c
++++ b/drivers/spi/spi-sun4i.c
+@@ -390,6 +390,7 @@ static int sun4i_spi_runtime_resume(struct device *dev)
+ 	struct spi_controller *host = dev_get_drvdata(dev);
+ 	struct sun4i_spi *sspi = spi_controller_get_devdata(host);
+ 	int ret;
++	u32 reg;
+ 
+ 	ret = clk_prepare_enable(sspi->hclk);
+ 	if (ret) {
+@@ -402,9 +403,10 @@ static int sun4i_spi_runtime_resume(struct device *dev)
+ 		dev_err(dev, "Couldn't enable module clock\n");
+ 		goto err;
+ 	}
++	reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
+ 
+ 	sun4i_spi_write(sspi, SUN4I_CTL_REG,
+-			SUN4I_CTL_ENABLE | SUN4I_CTL_MASTER | SUN4I_CTL_TP);
++			reg | SUN4I_CTL_ENABLE | SUN4I_CTL_MASTER | SUN4I_CTL_TP);
+ 
+ 	return 0;
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-spi-spidev-Add-armbian-spi-dev-compatible.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-spi-spidev-Add-armbian-spi-dev-compatible.patch
new file mode 100644
index 000000000000..2106cf3994de
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-spi-spidev-Add-armbian-spi-dev-compatible.patch
@@ -0,0 +1,37 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Wed, 2 Feb 2022 11:56:51 +0300
+Subject: drv:spi:spidev Add armbian spi-dev compatible
+
+---
+ drivers/spi/spidev.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c
+index 58ae4304fdab..c4c73a61a571 100644
+--- a/drivers/spi/spidev.c
++++ b/drivers/spi/spidev.c
+@@ -703,6 +703,7 @@ static const struct class spidev_class = {
+  * spidev_dt_ids array below. Both arrays are kept in the same ordering.
+  */
+ static const struct spi_device_id spidev_spi_ids[] = {
++	{ .name = /* armbian */ "spi-dev" },
+ 	{ .name = /* cisco */ "spi-petra" },
+ 	{ .name = /* dh */ "dhcom-board" },
+ 	{ .name = /* elgin */ "jg10309-01" },
+@@ -730,10 +731,12 @@ static int spidev_of_check(struct device *dev)
+ 		return 0;
+ 
+ 	dev_err(dev, "spidev listed directly in DT is not supported\n");
++	dev_info(dev, "Use a compatible alias string like spi-dev in DT\n");
+ 	return -EINVAL;
+ }
+ 
+ static const struct of_device_id spidev_dt_ids[] = {
++	{ .compatible = "armbian,spi-dev", .data = &spidev_of_check },
+ 	{ .compatible = "cisco,spi-petra", .data = &spidev_of_check },
+ 	{ .compatible = "dh,dhcom-board", .data = &spidev_of_check },
+ 	{ .compatible = "elgin,jg10309-01", .data = &spidev_of_check },
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-staging-media-sunxi-cedrus-add-H616-variant.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-staging-media-sunxi-cedrus-add-H616-variant.patch
new file mode 100644
index 000000000000..3bcfe4605532
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-staging-media-sunxi-cedrus-add-H616-variant.patch
@@ -0,0 +1,44 @@
+From bb7878b3cdbebd2e3c5975b65f92f59141bd76b9 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@gmail.com>
+Date: Fri, 15 Oct 2021 21:49:45 +0200
+Subject: drv:staging:media:sunxi:cedrus: add H616 variant
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+---
+ drivers/staging/media/sunxi/cedrus/cedrus.c | 13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+
+diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.c b/drivers/staging/media/sunxi/cedrus/cedrus.c
+index 08f8d994c99c..191bb30ae1e8 100644
+--- a/drivers/staging/media/sunxi/cedrus/cedrus.c
++++ b/drivers/staging/media/sunxi/cedrus/cedrus.c
+@@ -651,6 +651,15 @@ static const struct cedrus_variant sun50i_h6_cedrus_variant = {
+ 	.mod_rate	= 648000000,
+ };
+ 
++static const struct cedrus_variant sun50i_h616_cedrus_variant = {
++	.capabilities	= CEDRUS_CAPABILITY_UNTILED |
++			  CEDRUS_CAPABILITY_MPEG2_DEC |
++			  CEDRUS_CAPABILITY_H264_DEC |
++			  CEDRUS_CAPABILITY_H265_DEC |
++			  CEDRUS_CAPABILITY_VP8_DEC,
++	.mod_rate	= 600000000,
++};
++
+ static const struct of_device_id cedrus_dt_match[] = {
+ 	{
+ 		.compatible = "allwinner,sun4i-a10-video-engine",
+@@ -696,6 +705,10 @@ static const struct of_device_id cedrus_dt_match[] = {
+ 		.compatible = "allwinner,sun50i-h6-video-engine",
+ 		.data = &sun50i_h6_cedrus_variant,
+ 	},
++	{
++		.compatible = "allwinner,sun50i-h616-video-engine",
++		.data = &sun50i_h6_cedrus_variant,
++	},
+ 	{ /* sentinel */ }
+ };
+ MODULE_DEVICE_TABLE(of, cedrus_dt_match);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-staging-rtl8723bs-AP-bugfix.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-staging-rtl8723bs-AP-bugfix.patch
new file mode 100644
index 000000000000..14ad1e2edc3d
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-staging-rtl8723bs-AP-bugfix.patch
@@ -0,0 +1,25 @@
+From 426ff5c4a9a47d9da2701ce9365af6fd64ca50c9 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Mon, 7 Feb 2022 17:00:50 +0300
+Subject: drv:staging:rtl8723bs: AP bugfix
+
+---
+ drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c b/drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c
+index 7fcc46a0bb48..97616c2d34e1 100644
+--- a/drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c
++++ b/drivers/staging/rtl8723bs/os_dep/ioctl_cfg80211.c
+@@ -1922,7 +1922,7 @@ void rtw_cfg80211_indicate_sta_assoc(struct adapter *padapter, u8 *pmgmt_frame,
+ 		else /*  WIFI_REASSOCREQ */
+ 			ie_offset = _REASOCREQ_IE_OFFSET_;
+ 
+-		sinfo.filled = 0;
++		sinfo.pertid = 0;
+ 		sinfo.assoc_req_ies = pmgmt_frame + WLAN_HDR_A3_LEN + ie_offset;
+ 		sinfo.assoc_req_ies_len = frame_len - WLAN_HDR_A3_LEN - ie_offset;
+ 		cfg80211_new_sta(ndev, GetAddr2Ptr(pmgmt_frame), &sinfo, GFP_ATOMIC);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-usb-gadget-composite-rename-gadget-serial-console-manufactu.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-usb-gadget-composite-rename-gadget-serial-console-manufactu.patch
new file mode 100644
index 000000000000..eaa5c24e3ce4
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/drv-usb-gadget-composite-rename-gadget-serial-console-manufactu.patch
@@ -0,0 +1,27 @@
+From 1bd66ae2c914290b56e258b62b798e29a5af2a77 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Wed, 2 Feb 2022 20:08:50 +0300
+Subject: drv:usb:gadget:composite rename gadget serial console manufacturer
+
+rename the manufacturer of gadgets for serial consoles
+to the Armbian brand.
+---
+ drivers/usb/gadget/composite.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/usb/gadget/composite.c b/drivers/usb/gadget/composite.c
+index 869ad99afb48..9f111be98fd1 100644
+--- a/drivers/usb/gadget/composite.c
++++ b/drivers/usb/gadget/composite.c
+@@ -2777,7 +2777,7 @@ EXPORT_SYMBOL_GPL(usb_composite_setup_continue);
+ 
+ static char *composite_default_mfr(struct usb_gadget *gadget)
+ {
+-	return kasprintf(GFP_KERNEL, "%s %s with %s", init_utsname()->sysname,
++	return kasprintf(GFP_KERNEL, "%s %s with %s", "Armbian Linux",
+ 			 init_utsname()->release, gadget->name);
+ }
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/enable-TV-Output-on-OrangePi-Zero-LTE.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/enable-TV-Output-on-OrangePi-Zero-LTE.patch
new file mode 100644
index 000000000000..a9d4dba025b9
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/enable-TV-Output-on-OrangePi-Zero-LTE.patch
@@ -0,0 +1,647 @@
+From 6d80f39a376532c5d54fd72686534e2cd5d59652 Mon Sep 17 00:00:00 2001
+From: Radoslav <radoslavv@centrum.sk>
+Date: Sat, 15 Apr 2023 22:47:26 +0200
+Subject: enable TV Output on OrangePi Zero LTE
+
+Credits to sorce https://github.com/robertojguerra/orangepi-zero-full-setup/blob/main/README2.md
+Merged:
+1. sunxi-6.1/0036-wip-h3-h5-cvbs-armbian.patch : makes additions to the "dts", which tells the kernel where are the new devices. Adds kernel code to interact with the tv encoder. With my modifications, now it is applicable to Armbian (this patch came from the LibreElec github).
+    https://github.com/robertojguerra/orangepi-zero-full-setup/blob/main/sunxi-6.1/0036-wip-h3-h5-cvbs-armbian.patch
+2. sunxi-6.1/zzzz2-tv.patch : by Armbian user "gleam2003", adds directives to make sure that the dtbo (device tree binary overlay) is compiled
+    https://github.com/robertojguerra/orangepi-zero-full-setup/blob/main/sunxi-6.1/zzzz2-tv.patch
+3. sunxi-6.1/zzzz3-tv.patch : more additions to the "dts" and "dtsi" (like C include files), which I noticed were included in "yam" patch, but missing from the LibreElec patch
+    https://github.com/robertojguerra/orangepi-zero-full-setup/blob/main/sunxi-6.1/zzzz3-tv.patch
+
+> X-Git-Archeology: - Revision 41260ac309b487d241fec97ffbdeced730bc2d04: https://github.com/armbian/build/commit/41260ac309b487d241fec97ffbdeced730bc2d04
+> X-Git-Archeology:   Date: Sat, 15 Apr 2023 22:47:26 +0200
+> X-Git-Archeology:   From: Radoslav <radoslavv@centrum.sk>
+> X-Git-Archeology:   Subject: h3-tve (arm-dts-sun8i-h3-orangepizero-add_tve.patch)
+---
+ arch/arm/boot/dts/allwinner/overlay/Makefile  |  1 +
+ .../overlay/README.sun8i-h3-overlays          | 10 ++
+ .../dts/allwinner/overlay/sun8i-h3-tve.dtso   | 34 +++++++
+ .../allwinner/sun8i-h2-plus-orangepi-zero.dts |  4 +
+ .../dts/allwinner/sun8i-h3-orangepi-pc.dts    |  4 +
+ arch/arm/boot/dts/allwinner/sun8i-h3.dtsi     | 22 +++++
+ arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi  | 95 ++++++++++++++++++-
+ .../arm64/boot/dts/allwinner/overlay/Makefile |  1 +
+ .../overlay/README.sun50i-h5-overlays         |  5 +
+ .../dts/allwinner/overlay/sun50i-h5-tve.dtso  | 34 +++++++
+ arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi  | 22 +++++
+ drivers/clk/sunxi-ng/ccu-sun8i-h3.c           | 14 ++-
+ drivers/gpu/drm/sun4i/Makefile                |  2 +-
+ drivers/gpu/drm/sun4i/sun4i_tv.c              | 35 ++++++-
+ drivers/gpu/drm/sun4i/sun8i_mixer.c           | 30 +++++-
+ drivers/gpu/drm/sun4i/sun8i_mixer.h           |  2 +
+ 16 files changed, 305 insertions(+), 10 deletions(-)
+ create mode 100644 arch/arm/boot/dts/allwinner/overlay/sun8i-h3-tve.dtso
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-tve.dtso
+
+diff --git a/arch/arm/boot/dts/allwinner/overlay/Makefile b/arch/arm/boot/dts/allwinner/overlay/Makefile
+index 560f926b7018..23ecb62e2478 100644
+--- a/arch/arm/boot/dts/allwinner/overlay/Makefile
++++ b/arch/arm/boot/dts/allwinner/overlay/Makefile
+@@ -80,6 +80,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
+ 	sun8i-h3-usbhost2.dtbo \
+ 	sun8i-h3-usbhost3.dtbo \
+ 	sun8i-h3-w1-gpio.dtbo \
++        sun8i-h3-tve.dtbo \
+ 	sun8i-r40-i2c2.dtbo \
+ 	sun8i-r40-i2c3.dtbo \
+ 	sun8i-r40-spi-spidev0.dtbo \
+diff --git a/arch/arm/boot/dts/allwinner/overlay/README.sun8i-h3-overlays b/arch/arm/boot/dts/allwinner/overlay/README.sun8i-h3-overlays
+index 302973491051..a347fe7b0e81 100644
+--- a/arch/arm/boot/dts/allwinner/overlay/README.sun8i-h3-overlays
++++ b/arch/arm/boot/dts/allwinner/overlay/README.sun8i-h3-overlays
+@@ -34,6 +34,7 @@ adding fixed software (GPIO) chip selects is possible with a separate overlay
+ - usbhost2
+ - usbhost3
+ - w1-gpio
++- tve
+ 
+ ### Overlay details:
+ 
+@@ -248,3 +249,12 @@ param_w1_pin_int_pullup (bool)
+ 	Set to 1 to enable the pull-up
+ 	This option should not be used with multiple devices, parasite power setup
+ 		or long wires -	please use external pull-up resistor instead
++
++### tve
++
++Activates Composite TV Encoder
++
++Parameters:
++	Unknown at this stage. 
++	Maybe none. 
++	Not sure how to change the mode between PAL/NTSC.
+diff --git a/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-tve.dtso b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-tve.dtso
+new file mode 100644
+index 000000000000..07ba7ba713dd
+--- /dev/null
++++ b/arch/arm/boot/dts/allwinner/overlay/sun8i-h3-tve.dtso
+@@ -0,0 +1,34 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun8i-h3";
++	
++	fragment@0 {
++		target = <&de>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++
++	fragment@1 {
++		target = <&mixer1>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++
++	fragment@2 {
++		target = <&tcon1>;
++		 __overlay__ {
++			status = "okay";
++		};
++	};
++
++	fragment@3 {
++		target = <&tve>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-zero.dts
+index c9e84ad69113..1bb54edb00ce 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-zero.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h2-plus-orangepi-zero.dts
+@@ -180,6 +180,10 @@ flash@0 {
+ 	};
+ };
+ 
++&tve {
++        status = "okay";
++};
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_pa_pins>;
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc.dts
+index 624e248e3ffc..01c3a7f7620a 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc.dts
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3-orangepi-pc.dts
+@@ -214,6 +214,10 @@ &sound_hdmi {
+ 	status = "okay";
+ };
+ 
++&tve {
++	status = "okay";
++};
++
+ &uart0 {
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&uart0_pa_pins>;
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi b/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi
+index 8c2f597772fe..35c864fe4823 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-h3.dtsi
+@@ -295,6 +295,20 @@ ths: thermal-sensor@1c25000 {
+ 			nvmem-cell-names = "calibration";
+ 			#thermal-sensor-cells = <0>;
+ 		};
++
++		tve: tv-encoder@1e00000 {
++			compatible = "allwinner,sun8i-h3-tv-encoder";
++			reg = <0x01e00000 0x1000>;
++			clocks = <&ccu CLK_BUS_TVE>;
++			resets = <&ccu RST_BUS_TVE>;
++			status = "disabled";
++
++			port {
++				tve_in_tcon1: endpoint {
++					remote-endpoint = <&tcon1_out_tve>;
++				};
++			};
++		};
+ 	};
+ 
+ 	thermal-zones {
+@@ -384,6 +398,10 @@ &mbus {
+ 	compatible = "allwinner,sun8i-h3-mbus";
+ };
+ 
++&mixer1 {
++	resets = <&display_clocks RST_WB>;
++};
++
+ &mmc0 {
+ 	compatible = "allwinner,sun7i-a20-mmc";
+ 	clocks = <&ccu CLK_BUS_MMC0>,
+@@ -431,3 +449,7 @@ &rtc {
+ &sid {
+ 	compatible = "allwinner,sun8i-h3-sid";
+ };
++
++&tcon1_out_tve {
++	remote-endpoint = <&tve_in_tcon1>;
++};
+diff --git a/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi
+index 4137aee6568b..ef9744b92e42 100644
+--- a/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi
++++ b/arch/arm/boot/dts/allwinner/sunxi-h3-h5.dtsi
+@@ -116,7 +116,7 @@ cpu {
+ 
+ 	de: display-engine {
+ 		compatible = "allwinner,sun8i-h3-display-engine";
+-		allwinner,pipelines = <&mixer0>;
++		allwinner,pipelines = <&mixer0>, <&mixer1>;
+ 		status = "disabled";
+ 	};
+ 
+@@ -160,11 +160,50 @@ ports {
+ 				#size-cells = <0>;
+ 
+ 				mixer0_out: port@1 {
++					#address-cells = <1>;
++					#size-cells = <0>;
+ 					reg = <1>;
+ 
+-					mixer0_out_tcon0: endpoint {
++					mixer0_out_tcon0: endpoint@0 {
++						reg = <0>;
+ 						remote-endpoint = <&tcon0_in_mixer0>;
+ 					};
++
++					mixer0_out_tcon1: endpoint@1 {
++						reg = <1>;
++						remote-endpoint = <&tcon1_in_mixer0>;
++					};
++				};
++			};
++		};
++
++		mixer1: mixer@1200000 {
++			compatible = "allwinner,sun8i-h3-de2-mixer-1";
++			reg = <0x01200000 0x100000>;
++			clocks = <&display_clocks CLK_BUS_MIXER1>,
++				 <&display_clocks CLK_MIXER1>;
++			clock-names = "bus",
++				      "mod";
++			/* reset is added by SoC dtsi */
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				mixer1_out: port@1 {
++					#address-cells = <1>;
++					#size-cells = <0>;
++					reg = <1>;
++
++					mixer1_out_tcon0: endpoint@0 {
++						reg = <0>;
++						remote-endpoint = <&tcon0_in_mixer1>;
++					};
++
++					mixer1_out_tcon1: endpoint@1 {
++						reg = <1>;
++						remote-endpoint = <&tcon1_in_mixer1>;
++					};
+ 				};
+ 			};
+ 		};
+@@ -193,11 +232,19 @@ ports {
+ 				#size-cells = <0>;
+ 
+ 				tcon0_in: port@0 {
++					#address-cells = <1>;
++					#size-cells = <0>;
+ 					reg = <0>;
+ 
+-					tcon0_in_mixer0: endpoint {
++					tcon0_in_mixer0: endpoint@0 {
++						reg = <0>;
+ 						remote-endpoint = <&mixer0_out_tcon0>;
+ 					};
++
++					tcon0_in_mixer1: endpoint@1 {
++						reg = <1>;
++						remote-endpoint = <&mixer1_out_tcon0>;
++					};
+ 				};
+ 
+ 				tcon0_out: port@1 {
+@@ -213,6 +260,48 @@ tcon0_out_hdmi: endpoint@1 {
+ 			};
+ 		};
+ 
++		tcon1: lcd-controller@1c0d000 {
++			compatible = "allwinner,sun8i-h3-tcon-tv",
++				     "allwinner,sun8i-a83t-tcon-tv";
++			reg = <0x01c0d000 0x1000>;
++			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
++			clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TVE>;
++			clock-names = "ahb", "tcon-ch1";
++			resets = <&ccu RST_BUS_TCON1>;
++			reset-names = "lcd";
++
++			ports {
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				tcon1_in: port@0 {
++					#address-cells = <1>;
++					#size-cells = <0>;
++					reg = <0>;
++
++					tcon1_in_mixer0: endpoint@0 {
++						reg = <0>;
++						remote-endpoint = <&mixer0_out_tcon1>;
++					};
++
++					tcon1_in_mixer1: endpoint@1 {
++						reg = <1>;
++						remote-endpoint = <&mixer1_out_tcon1>;
++					};
++				};
++
++				tcon1_out: port@1 {
++					#address-cells = <1>;
++					#size-cells = <0>;
++					reg = <1>;
++
++					tcon1_out_tve: endpoint@1 {
++						reg = <1>;
++					};
++				};
++			};
++		};
++
+ 		mmc0: mmc@1c0f000 {
+ 			/* compatible and clocks are in per SoC .dtsi file */
+ 			reg = <0x01c0f000 0x1000>;
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/Makefile b/arch/arm64/boot/dts/allwinner/overlay/Makefile
+index fb6b30d5753e..84711585fc86 100644
+--- a/arch/arm64/boot/dts/allwinner/overlay/Makefile
++++ b/arch/arm64/boot/dts/allwinner/overlay/Makefile
+@@ -27,6 +27,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += \
+ 	sun50i-h5-spi-add-cs1.dtbo \
+ 	sun50i-h5-spi-jedec-nor.dtbo \
+ 	sun50i-h5-spi-spidev.dtbo \
++	sun50i-h5-tve.dtbo \
+ 	sun50i-h5-uart1.dtbo \
+ 	sun50i-h5-uart2.dtbo \
+ 	sun50i-h5-uart3.dtbo \
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/README.sun50i-h5-overlays b/arch/arm64/boot/dts/allwinner/overlay/README.sun50i-h5-overlays
+index 1ac7fbcf62d1..a2ef4427c65b 100644
+--- a/arch/arm64/boot/dts/allwinner/overlay/README.sun50i-h5-overlays
++++ b/arch/arm64/boot/dts/allwinner/overlay/README.sun50i-h5-overlays
+@@ -26,6 +26,7 @@ adding fixed software (GPIO) chip selects is possible with a separate overlay
+ - spi-add-cs1
+ - spi-jedec-nor
+ - spi-spidev
++- tve
+ - uart1
+ - uart2
+ - uart3
+@@ -170,6 +171,10 @@ param_spidev_max_freq (int)
+ 	Default: 1000000
+ 	Range: 3000 - 100000000
+ 
++### tve
++
++Activates Composite TV Encoder
++
+ ### uart1
+ 
+ Activates serial port 1 (/dev/ttyS1)
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-tve.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-tve.dtso
+new file mode 100644
+index 000000000000..73e6e1215a5a
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h5-tve.dtso
+@@ -0,0 +1,34 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "allwinner,sun8i-h5";
++
++	fragment@0 {
++		target = <&de>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++
++	fragment@1 {
++		target = <&mixer1>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++
++	fragment@2 {
++		target = <&tcon1>;
++		 __overlay__ {
++			status = "okay";
++		};
++	};
++
++	fragment@3 {
++		target = <&tve>;
++		__overlay__ {
++			status = "okay";
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
+index c63e0871658e..fee2d680d2ca 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
+@@ -203,6 +203,20 @@ ths: thermal-sensor@1c25000 {
+ 			nvmem-cell-names = "calibration";
+ 			#thermal-sensor-cells = <1>;
+ 		};
++
++		tve: tv-encoder@1e40000 {
++			compatible = "allwinner,sun50i-h5-tv-encoder";
++			reg = <0x01e40000 0x1000>;
++			clocks = <&ccu CLK_BUS_TVE>;
++			resets = <&ccu RST_BUS_TVE>;
++			status = "disabled";
++
++			port {
++				tve_in_tcon1: endpoint {
++					remote-endpoint = <&tcon1_out_tve>;
++				};
++			};
++		};
+ 	};
+ 
+ 	thermal-zones {
+@@ -307,6 +321,10 @@ &mbus {
+ 	compatible = "allwinner,sun50i-h5-mbus";
+ };
+ 
++&mixer1 {
++	resets = <&display_clocks RST_MIXER1>;
++};
++
+ &mmc0 {
+ 	compatible = "allwinner,sun50i-h5-mmc",
+ 		     "allwinner,sun50i-a64-mmc";
+@@ -342,3 +360,7 @@ &rtc {
+ &sid {
+ 	compatible = "allwinner,sun50i-h5-sid";
+ };
++
++&tcon1_out_tve {
++	remote-endpoint = <&tve_in_tcon1>;
++};
+diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+index 9bd05a0488ff..4a80c04c369b 100644
+--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
++++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+@@ -469,8 +469,18 @@ static SUNXI_CCU_M_WITH_MUX_GATE(tcon_clk, "tcon", tcon_parents,
+ 				 CLK_SET_RATE_PARENT);
+ 
+ static const char * const tve_parents[] = { "pll-de", "pll-periph1" };
+-static SUNXI_CCU_M_WITH_MUX_GATE(tve_clk, "tve", tve_parents,
+-				 0x120, 0, 4, 24, 3, BIT(31), 0);
++struct ccu_div tve_clk = {
++	.enable	= BIT(31),
++	.div	= _SUNXI_CCU_DIV(0, 4),
++	.mux	= _SUNXI_CCU_MUX(24, 3),
++	.fixed_post_div = 16,
++	.common	= {
++		.reg		= 0x120,
++		.features	= CCU_FEATURE_FIXED_POSTDIV,
++		.hw.init	= CLK_HW_INIT_PARENTS("tve", tve_parents,
++						      &ccu_div_ops, 0),
++	},
++};
+ 
+ static const char * const deinterlace_parents[] = { "pll-periph0", "pll-periph1" };
+ static SUNXI_CCU_M_WITH_MUX_GATE(deinterlace_clk, "deinterlace", deinterlace_parents,
+diff --git a/drivers/gpu/drm/sun4i/Makefile b/drivers/gpu/drm/sun4i/Makefile
+index 8ffddaa3e069..e557b9cd51ff 100644
+--- a/drivers/gpu/drm/sun4i/Makefile
++++ b/drivers/gpu/drm/sun4i/Makefile
+@@ -20,7 +20,7 @@ sun8i-drm-hdmi-y		+= sun8i_hdmi_phy_clk.o
+ sun8i-mixer-y			+= sun8i_mixer.o sun8i_ui_layer.o \
+ 				   sun8i_vi_layer.o sun8i_ui_scaler.o \
+ 				   sun8i_vi_scaler.o sun8i_csc.o \
+-				   sun50i_fmt.o sun50i_afbc.o
++				   sun50i_fmt.o sun50i_afbc.o sun4i_tv.o
+ 
+ sun4i-tcon-y			+= sun4i_crtc.o
+ sun4i-tcon-y			+= sun4i_tcon_dclk.o
+diff --git a/drivers/gpu/drm/sun4i/sun4i_tv.c b/drivers/gpu/drm/sun4i/sun4i_tv.c
+index cce4e38789b9..de3498ab2c58 100644
+--- a/drivers/gpu/drm/sun4i/sun4i_tv.c
++++ b/drivers/gpu/drm/sun4i/sun4i_tv.c
+@@ -10,6 +10,7 @@
+ #include <linux/component.h>
+ #include <linux/module.h>
+ #include <linux/of_address.h>
++#include <linux/of_device.h>
+ #include <linux/platform_device.h>
+ #include <linux/regmap.h>
+ #include <linux/reset.h>
+@@ -159,6 +160,11 @@ struct tv_mode {
+ 	const struct resync_parameters	*resync_params;
+ };
+ 
++struct sun4i_tv_quirks {
++	unsigned int calibration;
++	unsigned int unknown : 1;
++};
++
+ struct sun4i_tv {
+ 	struct drm_connector	connector;
+ 	struct drm_encoder	encoder;
+@@ -419,7 +425,7 @@ static const struct regmap_config sun4i_tv_regmap_config = {
+ 	.reg_bits	= 32,
+ 	.val_bits	= 32,
+ 	.reg_stride	= 4,
+-	.max_register	= SUN4I_TVE_WSS_DATA2_REG,
++	.max_register	= 0x400,
+ 	.name		= "tv-encoder",
+ };
+ 
+@@ -429,13 +435,19 @@ static int sun4i_tv_bind(struct device *dev, struct device *master,
+ 	struct platform_device *pdev = to_platform_device(dev);
+ 	struct drm_device *drm = data;
+ 	struct sun4i_drv *drv = drm->dev_private;
++	const struct sun4i_tv_quirks *quirks;
+ 	struct sun4i_tv *tv;
+ 	void __iomem *regs;
+ 	int ret;
+ 
++	quirks = of_device_get_match_data(dev);
++	if (!quirks)
++		return -EINVAL;
++
+ 	tv = devm_kzalloc(dev, sizeof(*tv), GFP_KERNEL);
+ 	if (!tv)
+ 		return -ENOMEM;
++
+ 	tv->drv = drv;
+ 	dev_set_drvdata(dev, tv);
+ 
+@@ -472,6 +484,11 @@ static int sun4i_tv_bind(struct device *dev, struct device *master,
+ 	}
+ 	clk_prepare_enable(tv->clk);
+ 
++	if (quirks->calibration)
++		regmap_write(tv->regs, 0x304, quirks->calibration);
++	if (quirks->unknown)
++		regmap_write(tv->regs, 0x30c, 0x00101110);
++
+ 	drm_encoder_helper_add(&tv->encoder,
+ 			       &sun4i_tv_helper_funcs);
+ 	ret = drm_simple_encoder_init(drm, &tv->encoder,
+@@ -551,8 +568,22 @@ static void sun4i_tv_remove(struct platform_device *pdev)
+ 	component_del(&pdev->dev, &sun4i_tv_ops);
+ }
+ 
++static const struct sun4i_tv_quirks a10_quirks = {
++};
++
++static const struct sun4i_tv_quirks h3_quirks = {
++	.calibration = 0x02000c00,
++};
++
++static const struct sun4i_tv_quirks h5_quirks = {
++	.calibration = 0x02850000,
++	.unknown = 1,
++};
++
+ static const struct of_device_id sun4i_tv_of_table[] = {
+-	{ .compatible = "allwinner,sun4i-a10-tv-encoder" },
++	{ .compatible = "allwinner,sun4i-a10-tv-encoder", .data = &a10_quirks },
++	{ .compatible = "allwinner,sun8i-h3-tv-encoder", .data = &h3_quirks },
++	{ .compatible = "allwinner,sun50i-h5-tv-encoder", .data = &h5_quirks },
+ 	{ }
+ };
+ MODULE_DEVICE_TABLE(of, sun4i_tv_of_table);
+diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
+index b8bd520a9292..b0f7df6fa883 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
++++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
+@@ -37,6 +37,12 @@ struct de2_fmt_info {
+ 	u32	de2_fmt;
+ };
+ 
++static const u32 sun8i_rgb2yuv_coef[12] = {
++	0x00000107, 0x00000204, 0x00000064, 0x00004200,
++	0x00001f68, 0x00001ed6, 0x000001c2, 0x00020200,
++	0x000001c2, 0x00001e87, 0x00001fb7, 0x00020200,
++};
++
+ static const struct de2_fmt_info de2_formats[] = {
+ 	{
+ 		.drm_fmt = DRM_FORMAT_ARGB8888,
+@@ -445,11 +451,30 @@ static u32 *sun8i_mixer_get_supported_fmts(struct sunxi_engine *engine, u32 *num
+ 	return formats;
+ }
+ 
++static void sun8i_mixer_apply_color_correction(struct sunxi_engine *engine)
++{
++	DRM_DEBUG_DRIVER("Applying RGB to YUV color correction\n");
++
++	regmap_bulk_write(engine->regs, SUN8I_MIXER_DCSC_COEF_REG(0),
++			  sun8i_rgb2yuv_coef, 12);
++	regmap_write(engine->regs, SUN8I_MIXER_DCSC_EN, 1);
++}
++
++static void sun8i_mixer_disable_color_correction(struct sunxi_engine *engine)
++{
++	DRM_DEBUG_DRIVER("Disabling color correction\n");
++
++	/* Disable color correction */
++	regmap_write(engine->regs, SUN8I_MIXER_DCSC_EN, 0);
++}
++
+ static const struct sunxi_engine_ops sun8i_engine_ops = {
+ 	.commit			= sun8i_mixer_commit,
+ 	.layers_init		= sun8i_layers_init,
+ 	.mode_set		= sun8i_mixer_mode_set,
+ 	.get_supported_fmts	= sun8i_mixer_get_supported_fmts,
++	.apply_color_correction		= sun8i_mixer_apply_color_correction,
++	.disable_color_correction	= sun8i_mixer_disable_color_correction,
+ };
+ 
+ static const struct regmap_config sun8i_mixer_regmap_config = {
+@@ -772,8 +797,9 @@ static const struct sun8i_mixer_cfg sun8i_h3_mixer0_cfg = {
+ static const struct sun8i_mixer_cfg sun8i_h3_mixer1_cfg = {
+ 	.ccsc		= CCSC_MIXER1_LAYOUT,
+ 	.mod_rate	= 432000000,
+-	.scaler_mask	= 0xf,
+-	.ui_num		= 3,
++	.scaler_mask	= 0x3,
++	.scanline_yuv	= 2048,
++	.ui_num		= 1,
+ 	.vi_num		= 1,
+ };
+ 
+diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h
+index 26b001164647..85e46e3c185b 100644
+--- a/drivers/gpu/drm/sun4i/sun8i_mixer.h
++++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h
+@@ -134,6 +134,8 @@
+ #define SUN8I_MIXER_ASE_EN			0xa8000
+ #define SUN8I_MIXER_FCC_EN			0xaa000
+ #define SUN8I_MIXER_DCSC_EN			0xb0000
++/* The DCSC sub-engine is used to do color space conversation */
++#define SUN8I_MIXER_DCSC_COEF_REG(x)		(0xb0010 + 0x4 * (x))
+ 
+ #define SUN50I_MIXER_FCE_EN			0x70000
+ #define SUN50I_MIXER_PEAK_EN			0x70800
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/fix-cpu-opp-table-sun8i-a83t.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/fix-cpu-opp-table-sun8i-a83t.patch
new file mode 100644
index 000000000000..c245c0e5e6a4
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/fix-cpu-opp-table-sun8i-a83t.patch
@@ -0,0 +1,115 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Fri, 27 May 2022 14:45:59 +0300
+Subject: fix: cpu opp table sun8i-a83t
+
+cpu opp table can only be a multiple of the integer 24 * 8 * n
+---
+ arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi | 52 ++++++----
+ 1 file changed, 32 insertions(+), 20 deletions(-)
+
+diff --git a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+index 111111111111..222222222222 100644
+--- a/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
++++ b/arch/arm/boot/dts/allwinner/sun8i-a83t.dtsi
+@@ -224,32 +224,38 @@ cpu0_opp_table: opp-table-cluster0 {
+ 		compatible = "operating-points-v2";
+ 		opp-shared;
+ 
+-		opp-480000000 {
+-			opp-hz = /bits/ 64 <480000000>;
++		opp-576000000 {
++			opp-hz = /bits/ 64 <576000000>; /* 24x8x3 */
+ 			opp-microvolt = <840000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+-		opp-1008000000 {
+-			opp-hz = /bits/ 64 <1008000000>;
++		opp-768000000 {
++			opp-hz = /bits/ 64 <768000000>; /* 24x8x4 */
+ 			opp-microvolt = <840000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+-		opp-1412000000 {
+-			opp-hz = /bits/ 64 <1412000000>;
++		opp-1152000000 {
++			opp-hz = /bits/ 64 <1152000000>; /* 24x8x6 */
++			opp-microvolt = <900000>;
++			clock-latency-ns = <244144>; /* 8 32k periods */
++		};
++
++		opp-1344000000 {
++			opp-hz = /bits/ 64 <1344000000>; /* 24x8x7 */
+ 			opp-microvolt = <920000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+-		opp-1608000000 {
+-			opp-hz = /bits/ 64 <1608000000>;
++		opp-1536000000 {
++			opp-hz = /bits/ 64 <1536000000>; /* 24x8x8 */
+ 			opp-microvolt = <1000000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+-		opp-1800000000 {
+-			opp-hz = /bits/ 64 <1800000000>;
++		opp-1728000000 {
++			opp-hz = /bits/ 64 <1728000000>; /* 24x8x9 */
+ 			opp-microvolt = <1080000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+@@ -259,32 +265,38 @@ cpu1_opp_table: opp-table-cluster1 {
+ 		compatible = "operating-points-v2";
+ 		opp-shared;
+ 
+-		opp-480000000 {
+-			opp-hz = /bits/ 64 <480000000>;
++		opp-576000000 {
++			opp-hz = /bits/ 64 <576000000>; /* 24x8x3 */
+ 			opp-microvolt = <840000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+-		opp-1008000000 {
+-			opp-hz = /bits/ 64 <1008000000>;
++		opp-768000000 {
++			opp-hz = /bits/ 64 <768000000>; /* 24x8x4 */
+ 			opp-microvolt = <840000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+-		opp-1412000000 {
+-			opp-hz = /bits/ 64 <1412000000>;
++		opp-1152000000 {
++			opp-hz = /bits/ 64 <1152000000>; /* 24x8x6 */
++			opp-microvolt = <900000>;
++			clock-latency-ns = <244144>; /* 8 32k periods */
++		};
++
++		opp-1344000000 {
++			opp-hz = /bits/ 64 <1344000000>; /* 24x8x7 */
+ 			opp-microvolt = <920000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+-		opp-1608000000 {
+-			opp-hz = /bits/ 64 <1608000000>;
++		opp-1536000000 {
++			opp-hz = /bits/ 64 <1536000000>; /* 24x8x8 */
+ 			opp-microvolt = <1000000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+ 
+-		opp-1800000000 {
+-			opp-hz = /bits/ 64 <1800000000>;
++		opp-1728000000 {
++			opp-hz = /bits/ 64 <1728000000>; /* 24x8x9 */
+ 			opp-microvolt = <1080000>;
+ 			clock-latency-ns = <244144>; /* 8 32k periods */
+ 		};
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/include-uapi-drm_fourcc-add-ARM-tiled-format-modifier.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/include-uapi-drm_fourcc-add-ARM-tiled-format-modifier.patch
new file mode 100644
index 000000000000..6920a49b1bc5
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/include-uapi-drm_fourcc-add-ARM-tiled-format-modifier.patch
@@ -0,0 +1,35 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Qiang Yu <yuq825@gmail.com>
+Date: Tue, 19 Jun 2018 13:51:17 +0800
+Subject: include:uapi:drm_fourcc: add ARM tiled format modifier
+
+Signed-off-by: Qiang Yu <yuq825@gmail.com>
+
+Signed-off-by: The-going <48602507+The-going@users.noreply.github.com>
+---
+ include/uapi/drm/drm_fourcc.h | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
+index 111111111111..222222222222 100644
+--- a/include/uapi/drm/drm_fourcc.h
++++ b/include/uapi/drm/drm_fourcc.h
+@@ -1349,6 +1349,15 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
+  */
+ #define AFRC_FORMAT_MOD_LAYOUT_SCAN (1ULL << 8)
+ 
++/*
++ * ARM tiled format
++ *
++ * This is used by ARM Mali Utgard/Midgard GPU. It divides buffer into
++ * 16x16 pixel blocks. Blocks are stored linearly in order, but pixels
++ * in the block are reordered.
++ */
++#define DRM_FORMAT_MOD_ARM_TILED fourcc_mod_code(ARM, 1)
++
+ /*
+  * Arm 16x16 Block U-Interleaved modifier
+  *
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/mfd-Add-support-for-X-Powers-AC200-EPHY-syscon.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/mfd-Add-support-for-X-Powers-AC200-EPHY-syscon.patch
new file mode 100644
index 000000000000..fccc7bbe2b1f
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/mfd-Add-support-for-X-Powers-AC200-EPHY-syscon.patch
@@ -0,0 +1,373 @@
+From 95a8f4f5c78481e12ca0be354835531ae71f3f25 Mon Sep 17 00:00:00 2001
+From: Andre Przywara <andre.przywara@arm.com>
+Date: Mon, 13 Jun 2022 17:37:19 +0100
+Subject: mfd: Add support for X-Powers AC200 EPHY syscon
+
+The X-Powers AC200 mixed signal chip contains a 100Mbit/s Ethernet PHY.
+While the PHY is using the standard MDIO and MII/RMII interfaces to
+the MAC, there are some registers in the AC200 that need to be setup to
+make the PHY functional:
+- The MDIO PHY address needs to set.
+- The LED polarity needs to be configured.
+- The MII interface mode needs to be set (MII or RMII).
+- There is a reset line that controls the PHY operation.
+- There is a clock gate that blocks or forwards the AC200's internal clock
+  to the PHY.
+
+This driver here takes care of those setup needs, but does not cover the
+actual PHY operation. Once the PHY is set up and enabled, it behaves like
+a standard MDIO/MII controlled PHY, and can be driven by the IEEE802.3-C22
+driver.
+
+To some degree those parameters mimic the typical wired setup of a
+physical PHY chip: the LED polarity, MII interface mode and PHY address
+are typically configued via connecting certain pins. We use the
+devicetree to learn those parameters, which depend on the board setup.
+
+This driver is a child of the AC200 MFD parent device, and uses its
+regmap and input clock. It also provides a reset and clock controller,
+which the actual PHY device (node) needs to refer to. This ensures that
+this PHY control device is initialised before the PHY is expected to work.
+
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+---
+ drivers/phy/allwinner/Kconfig          |   9 +
+ drivers/phy/allwinner/Makefile         |   1 +
+ drivers/phy/allwinner/ac200-ephy-ctl.c | 299 +++++++++++++++++++++++++
+ 3 files changed, 309 insertions(+)
+ create mode 100644 drivers/phy/allwinner/ac200-ephy-ctl.c
+
+diff --git a/drivers/phy/allwinner/Kconfig b/drivers/phy/allwinner/Kconfig
+index e93a53139460..d3614169de5c 100644
+--- a/drivers/phy/allwinner/Kconfig
++++ b/drivers/phy/allwinner/Kconfig
+@@ -58,3 +58,12 @@ config PHY_SUN50I_USB3
+ 	  part of Allwinner H6 SoC.
+ 
+ 	  This driver controls each individual USB 2+3 host PHY combo.
++
++config AC200_PHY_CTL
++	tristate "X-Power AC200 PHY control driver"
++	depends on MFD_AC200
++	depends on RESET_CONTROLLER
++	help
++	  Enable this to support the Ethernet PHY operation of the AC200
++	  mixed signal chip. This driver just enables and configures the
++	  PHY, the PHY itself is supported by a standard driver.
+diff --git a/drivers/phy/allwinner/Makefile b/drivers/phy/allwinner/Makefile
+index bd74901a1255..0eecec7a908a 100644
+--- a/drivers/phy/allwinner/Makefile
++++ b/drivers/phy/allwinner/Makefile
+@@ -3,3 +3,4 @@ obj-$(CONFIG_PHY_SUN4I_USB)		+= phy-sun4i-usb.o
+ obj-$(CONFIG_PHY_SUN6I_MIPI_DPHY)	+= phy-sun6i-mipi-dphy.o
+ obj-$(CONFIG_PHY_SUN9I_USB)		+= phy-sun9i-usb.o
+ obj-$(CONFIG_PHY_SUN50I_USB3)		+= phy-sun50i-usb3.o
++obj-$(CONFIG_AC200_PHY_CTL)		+= ac200-ephy-ctl.o
+diff --git a/drivers/phy/allwinner/ac200-ephy-ctl.c b/drivers/phy/allwinner/ac200-ephy-ctl.c
+new file mode 100644
+index 000000000000..f721ea72223c
+--- /dev/null
++++ b/drivers/phy/allwinner/ac200-ephy-ctl.c
+@@ -0,0 +1,299 @@
++// SPDX-License-Identifier: GPL-2.0+
++/**
++ * syscon driver to control and configure AC200 Ethernet PHY
++ * Copyright (c) 2022 Arm Ltd.
++ *
++ * TODO's and questions:
++ * =========================
++ * - This driver is something like a syscon driver, as it controls various
++ *   bits and registers that effect other devices (the actual PHY). It's
++ *   unclear where it should live, though:
++ *   - it could be integrated into the MFD driver, but this looks messy
++ *   - it could live at the current location (drivers/phy/allwinner), but that
++ *     sounds wrong
++ *   - it could be a separate file, but in drivers/mfd
++ *   - anything else
++ *
++ */
++
++#include <dt-bindings/gpio/gpio.h>
++
++#include <linux/clk.h>
++#include <linux/clk-provider.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/nvmem-consumer.h>
++#include <linux/of.h>
++#include <linux/of_net.h>
++#include <linux/phy.h>
++#include <linux/platform_device.h>
++#include <linux/reset-controller.h>
++
++/* macros for system ephy control 0 register */
++#define AC200_SYS_EPHY_CTL0		0x0014
++#define AC200_EPHY_RESET_INVALID	BIT(0)
++#define AC200_EPHY_SYSCLK_GATING	1
++
++/* macros for system ephy control 1 register */
++#define AC200_SYS_EPHY_CTL1		0x0016
++#define AC200_EPHY_E_EPHY_MII_IO_EN	BIT(0)
++#define AC200_EPHY_E_LNK_LED_IO_EN	BIT(1)
++#define AC200_EPHY_E_SPD_LED_IO_EN	BIT(2)
++#define AC200_EPHY_E_DPX_LED_IO_EN	BIT(3)
++
++/* macros for ephy control register */
++#define AC200_EPHY_CTL			0x6000
++#define AC200_EPHY_SHUTDOWN		BIT(0)
++#define AC200_EPHY_LED_POL		BIT(1)
++#define AC200_EPHY_CLK_SEL		BIT(2)
++#define AC200_EPHY_ADDR(x)		(((x) & 0x1F) << 4)
++#define AC200_EPHY_XMII_SEL		BIT(11)
++#define AC200_EPHY_CALIB(x)		(((x) & 0xF) << 12)
++
++struct ac200_ephy_ctl_dev {
++	struct reset_controller_dev	rcdev;
++	struct clk_hw			*gate_clk;
++	struct regmap			*regmap;
++};
++
++static struct ac200_ephy_ctl_dev *to_phy_dev(struct reset_controller_dev *rcdev)
++{
++	return container_of(rcdev, struct ac200_ephy_ctl_dev, rcdev);
++}
++
++static int ephy_ctl_reset(struct reset_controller_dev *rcdev, unsigned long id)
++{
++	struct ac200_ephy_ctl_dev *ac200 = to_phy_dev(rcdev);
++	int ret;
++
++	ret = regmap_clear_bits(ac200->regmap, AC200_SYS_EPHY_CTL0,
++				AC200_EPHY_RESET_INVALID);
++	if (ret)
++		return ret;
++
++	/* This is going via I2C, so there is plenty of built-in delay. */
++	return regmap_set_bits(ac200->regmap, AC200_SYS_EPHY_CTL0,
++			       AC200_EPHY_RESET_INVALID);
++}
++
++static int ephy_ctl_assert(struct reset_controller_dev *rcdev, unsigned long id)
++{
++	struct ac200_ephy_ctl_dev *ac200 = to_phy_dev(rcdev);
++
++	return regmap_clear_bits(ac200->regmap, AC200_SYS_EPHY_CTL0,
++				 AC200_EPHY_RESET_INVALID);
++}
++
++static int ephy_ctl_deassert(struct reset_controller_dev *rcdev,
++			     unsigned long id)
++{
++	struct ac200_ephy_ctl_dev *ac200 = to_phy_dev(rcdev);
++
++	return regmap_set_bits(ac200->regmap, AC200_SYS_EPHY_CTL0,
++			       AC200_EPHY_RESET_INVALID);
++}
++
++static int ephy_ctl_status(struct reset_controller_dev *rcdev, unsigned long id)
++{
++	struct ac200_ephy_ctl_dev *ac200 = to_phy_dev(rcdev);
++
++	return regmap_test_bits(ac200->regmap, AC200_SYS_EPHY_CTL0,
++				AC200_EPHY_RESET_INVALID);
++}
++
++static int ephy_ctl_reset_of_xlate(struct reset_controller_dev *rcdev,
++				   const struct of_phandle_args *reset_spec)
++{
++	if (WARN_ON(reset_spec->args_count != 0))
++		return -EINVAL;
++
++	return 0;
++}
++
++const struct reset_control_ops ephy_ctl_reset_ops = {
++	.assert		= ephy_ctl_assert,
++	.deassert	= ephy_ctl_deassert,
++	.reset		= ephy_ctl_reset,
++	.status		= ephy_ctl_status,
++};
++
++static void ac200_ephy_ctl_disable(struct ac200_ephy_ctl_dev *priv)
++{
++	regmap_write(priv->regmap, AC200_EPHY_CTL, AC200_EPHY_SHUTDOWN);
++	regmap_write(priv->regmap, AC200_SYS_EPHY_CTL1, 0);
++	regmap_write(priv->regmap, AC200_SYS_EPHY_CTL0, 0);
++}
++
++static int ac200_ephy_ctl_probe(struct platform_device *pdev)
++{
++	struct reset_controller_dev *rcdev;
++	struct device *dev = &pdev->dev;
++	struct ac200_ephy_ctl_dev *priv;
++	struct nvmem_cell *calcell;
++	const char *parent_name;
++	phy_interface_t phy_if;
++	u16 *caldata, ephy_ctl;
++	struct clk *clk;
++	size_t callen;
++	u32 value;
++	int ret;
++
++	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
++	if (!priv)
++		return -ENOMEM;
++
++	platform_set_drvdata(pdev, priv);
++
++	priv->regmap = dev_get_regmap(dev->parent, NULL);
++	if (!priv->regmap)
++		return -EPROBE_DEFER;
++
++	calcell = devm_nvmem_cell_get(dev, "calibration");
++	if (IS_ERR(calcell))
++		return dev_err_probe(dev, PTR_ERR(calcell),
++				     "Unable to find calibration data!\n");
++
++	caldata = nvmem_cell_read(calcell, &callen);
++	if (IS_ERR(caldata)) {
++		dev_err(dev, "Unable to read calibration data!\n");
++		return PTR_ERR(caldata);
++	}
++
++	if (callen != 2) {
++		dev_err(dev, "Calibration data length must be 2 bytes!\n");
++		kfree(caldata);
++		return -EINVAL;
++	}
++
++	ephy_ctl = AC200_EPHY_CALIB(*caldata + 3);
++	kfree(caldata);
++
++	ret = of_get_phy_mode(dev->of_node, &phy_if);
++	if (ret) {
++		dev_err(dev, "Unable to read PHY connection mode\n");
++		return ret;
++	}
++
++	switch (phy_if) {
++	case PHY_INTERFACE_MODE_MII:
++		break;
++	case PHY_INTERFACE_MODE_RMII:
++		ephy_ctl |= AC200_EPHY_XMII_SEL;
++		break;
++	default:
++		dev_err(dev, "Illegal PHY connection mode (%d), only RMII or MII supported\n",
++			phy_if);
++		return -EINVAL;
++	}
++
++	ret = of_property_read_u32(dev->of_node, "x-powers,led-polarity",
++				   &value);
++	if (ret) {
++		dev_err(dev, "Unable to read LED polarity setting\n");
++		return ret;
++	}
++
++	if (value == GPIO_ACTIVE_LOW)
++		ephy_ctl |= AC200_EPHY_LED_POL;
++
++	ret = of_property_read_u32(dev->of_node, "phy-address", &value);
++	if (ret) {
++		dev_err(dev, "Unable to read PHY address value\n");
++		return ret;
++	}
++
++	ephy_ctl |= AC200_EPHY_ADDR(value);
++
++	clk = clk_get(dev->parent, NULL);
++	if (IS_ERR(clk))
++		return dev_err_probe(dev, PTR_ERR(clk),
++				     "Unable to obtain the clock\n");
++
++	if (clk_get_rate(clk) == 24000000)
++		ephy_ctl |= AC200_EPHY_CLK_SEL;
++
++	clk_put(clk);
++
++	/* Assert reset and gate clock, to disable PHY for now */
++	ret = regmap_write(priv->regmap, AC200_SYS_EPHY_CTL0, 0);
++	if (ret)
++		return ret;
++
++	ret = regmap_write(priv->regmap, AC200_SYS_EPHY_CTL1,
++			   AC200_EPHY_E_EPHY_MII_IO_EN |
++			   AC200_EPHY_E_LNK_LED_IO_EN |
++			   AC200_EPHY_E_SPD_LED_IO_EN |
++			   AC200_EPHY_E_DPX_LED_IO_EN);
++	if (ret)
++		return ret;
++
++	ret = regmap_write(priv->regmap, AC200_EPHY_CTL, ephy_ctl);
++	if (ret)
++		return ret;
++
++	rcdev = &priv->rcdev;
++	rcdev->owner = dev->driver->owner;
++	rcdev->nr_resets = 1;
++	rcdev->ops = &ephy_ctl_reset_ops;
++	rcdev->of_node = dev->of_node;
++	rcdev->of_reset_n_cells = 0;
++	rcdev->of_xlate = ephy_ctl_reset_of_xlate;
++
++	ret = devm_reset_controller_register(dev, rcdev);
++	if (ret) {
++		dev_err(dev, "Unable to register reset controller: %d\n", ret);
++		goto err_disable_ephy;
++	}
++
++	parent_name = of_clk_get_parent_name(dev->parent->of_node, 0);
++	priv->gate_clk = devm_clk_hw_register_regmap_gate(dev,
++				"ac200-ephy-ctl-gate", parent_name, 0,
++				priv->regmap, AC200_SYS_EPHY_CTL0,
++				AC200_EPHY_SYSCLK_GATING, 0);
++	if (IS_ERR(priv->gate_clk)) {
++		ret = PTR_ERR(priv->gate_clk);
++		dev_err(dev, "Unable to register gate clock: %d\n", ret);
++		goto err_disable_ephy;
++	}
++
++	ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
++					  priv->gate_clk);
++	if (ret) {
++		dev_err(dev, "Unable to register clock provider: %d\n", ret);
++		goto err_disable_ephy;
++	}
++
++	return 0;
++
++err_disable_ephy:
++	ac200_ephy_ctl_disable(priv);
++
++	return ret;
++}
++
++static void ac200_ephy_ctl_remove(struct platform_device *pdev)
++{
++	struct ac200_ephy_ctl_dev *priv = platform_get_drvdata(pdev);
++
++	ac200_ephy_ctl_disable(priv);
++}
++
++static const struct of_device_id ac200_ephy_ctl_match[] = {
++	{ .compatible = "x-powers,ac200-ephy-ctl" },
++	{ /* sentinel */ }
++};
++MODULE_DEVICE_TABLE(of, ac200_ephy_ctl_match);
++
++static struct platform_driver ac200_ephy_ctl_driver = {
++	.probe		= ac200_ephy_ctl_probe,
++	.remove		= ac200_ephy_ctl_remove,
++	.driver		= {
++		.name		= "ac200-ephy-ctl",
++		.of_match_table	= ac200_ephy_ctl_match,
++	},
++};
++module_platform_driver(ac200_ephy_ctl_driver);
++
++MODULE_AUTHOR("Andre Przywara <andre.przywara@arm.com>");
++MODULE_DESCRIPTION("AC200 Ethernet PHY control driver");
++MODULE_LICENSE("GPL");
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/mfd-Add-support-for-X-Powers-AC200.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/mfd-Add-support-for-X-Powers-AC200.patch
new file mode 100644
index 000000000000..63b23ac5d640
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/mfd-Add-support-for-X-Powers-AC200.patch
@@ -0,0 +1,266 @@
+From 22de4391bc6b69c42ebf7c0a380e566d17810f0f Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@siol.net>
+Date: Fri, 16 Aug 2019 16:38:21 +0200
+Subject: mfd: Add support for X-Powers AC200
+
+The X-Powers AC200 is a mixed signal multi-purpose chip, which provides
+audio DAC/ADCs, a CVBS video encoder, a 100Mbit/s Ethernet PHY and a
+real-time clock. Its control registers can be accessed via I2C or
+Allwinner's RSB bus.
+Beside this chip being used on some older boards (for instance the Remix
+Mini PC), it is quite wide spread due to its die being co-packaged on the
+Allwinner H6 and H616 SoCs, which use its audio, video and PHY
+functionality.
+
+Aside from the RTC, the other functions do not need constant
+hand-holding via the I2C registers, but rather need to be configured and
+enabled only once.
+
+We model the control side of this chip using the MFD subsystem. This
+driver here just provides the parent device for the various subfunctions,
+and takes care of enabling clocks and reset, but also provides the regmap,
+which the respective child drivers will use.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+---
+ drivers/mfd/Kconfig  |  12 +++
+ drivers/mfd/Makefile |   1 +
+ drivers/mfd/ac200.c  | 190 +++++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 203 insertions(+)
+ create mode 100644 drivers/mfd/ac200.c
+
+diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
+index ae23b317a64e..85f0eb5f764e 100644
+--- a/drivers/mfd/Kconfig
++++ b/drivers/mfd/Kconfig
+@@ -203,6 +203,18 @@ config MFD_AC100
+ 	  This driver include only the core APIs. You have to select individual
+ 	  components like codecs or RTC under the corresponding menus.
+ 
++config MFD_AC200
++	tristate "X-Powers AC200"
++	select MFD_CORE
++	select REGMAP_I2C
++	depends on COMMON_CLK
++	depends on I2C
++	depends on OF
++	help
++	  If you say Y here you get support for the X-Powers AC200 IC.
++	  This driver include only the core APIs. You have to select individual
++	  components like Ethernet PHY or codec under the corresponding menus.
++
+ config MFD_AXP20X
+ 	tristate
+ 	select MFD_CORE
+diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
+index e057d6d6faef..03244b2c7306 100644
+--- a/drivers/mfd/Makefile
++++ b/drivers/mfd/Makefile
+@@ -146,6 +146,7 @@ obj-$(CONFIG_MFD_DA9052_SPI)	+= da9052-spi.o
+ obj-$(CONFIG_MFD_DA9052_I2C)	+= da9052-i2c.o
+ 
+ obj-$(CONFIG_MFD_AC100)		+= ac100.o
++obj-$(CONFIG_MFD_AC200)		+= ac200.o
+ obj-$(CONFIG_MFD_AXP20X)	+= axp20x.o
+ obj-$(CONFIG_MFD_AXP20X_I2C)	+= axp20x-i2c.o
+ obj-$(CONFIG_MFD_AXP20X_RSB)	+= axp20x-rsb.o
+diff --git a/drivers/mfd/ac200.c b/drivers/mfd/ac200.c
+new file mode 100644
+index 000000000000..ad28c380c880
+--- /dev/null
++++ b/drivers/mfd/ac200.c
+@@ -0,0 +1,190 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * MFD core driver for X-Powers' AC200 IC
++ *
++ * The AC200 is a chip which is co-packaged with Allwinner H6 SoC and
++ * includes analog audio codec, analog TV encoder, ethernet PHY, eFuse
++ * and RTC.
++ *
++ * Copyright (c) 2019 Jernej Skrabec <jernej.skrabec@gmail.com>
++ *
++ * Based on AC100 driver with following copyrights:
++ * Copyright (2016) Chen-Yu Tsai
++ */
++
++#include <linux/clk.h>
++#include <linux/delay.h>
++#include <linux/i2c.h>
++#include <linux/kernel.h>
++#include <linux/mfd/core.h>
++#include <linux/module.h>
++#include <linux/nvmem-consumer.h>
++#include <linux/of.h>
++#include <linux/regmap.h>
++
++struct ac200_dev {
++	struct clk	*clk;
++	struct regmap	*regmap;
++};
++
++#define AC200_SYS_CONTROL	0x0002
++#define AC200_SYS_BG_CTL	0x0050
++
++/* interface register (can be accessed from any page) */
++#define AC200_TWI_REG_ADDR_H	0xFE
++
++#define AC200_MAX_REG		0xA1F2
++
++static const struct regmap_range_cfg ac200_range_cfg[] = {
++	{
++		.range_max = AC200_MAX_REG,
++		.selector_reg = AC200_TWI_REG_ADDR_H,
++		.selector_mask = 0xff,
++		.selector_shift = 0,
++		.window_start = 0,
++		.window_len = 256,
++	}
++};
++
++static const struct regmap_config ac200_regmap_config = {
++	.name		= "AC200",
++	.reg_bits	= 8,
++	.reg_stride	= 2,
++	.val_bits	= 16,
++	.ranges		= ac200_range_cfg,
++	.num_ranges	= ARRAY_SIZE(ac200_range_cfg),
++	.max_register	= AC200_MAX_REG,
++};
++
++static struct mfd_cell ac200_cells[] = {
++	{
++		.name		= "ac200-codec",
++		.of_compatible	= "x-powers,ac200-codec",
++	}, {
++		.name		= "ac200-ephy-ctl",
++		.of_compatible	= "x-powers,ac200-ephy-ctl",
++	},
++};
++
++static int ac200_i2c_probe(struct i2c_client *i2c)
++{
++	struct device *dev = &i2c->dev;
++	struct nvmem_cell *bgcell;
++	struct ac200_dev *ac200;
++	u16 *bgdata, bgval;
++	size_t bglen;
++	int ret;
++
++	ac200 = devm_kzalloc(dev, sizeof(*ac200), GFP_KERNEL);
++	if (!ac200)
++		return -ENOMEM;
++
++	i2c_set_clientdata(i2c, ac200);
++
++	ac200->clk = devm_clk_get(dev, NULL);
++	if (IS_ERR(ac200->clk))
++		return dev_err_probe(dev, PTR_ERR(ac200->clk),
++				     "Can't obtain the clock\n");
++
++	ac200->regmap = devm_regmap_init_i2c(i2c, &ac200_regmap_config);
++	if (IS_ERR(ac200->regmap)) {
++		ret = PTR_ERR(ac200->regmap);
++		dev_err(dev, "Regmap init failed: %d\n", ret);
++		return ret;
++	}
++
++	bgcell = devm_nvmem_cell_get(dev, "bandgap");
++	if (IS_ERR(bgcell))
++		return dev_err_probe(dev, PTR_ERR(bgcell),
++				     "Unable to find bandgap data!\n");
++
++	bgdata = nvmem_cell_read(bgcell, &bglen);
++	if (IS_ERR(bgdata)) {
++		dev_err(dev, "Unable to read bandgap data!\n");
++		return PTR_ERR(bgdata);
++	}
++
++	if (bglen != 2) {
++		dev_err(dev, "Invalid nvmem bandgap length!\n");
++		kfree(bgdata);
++		return -EINVAL;
++	}
++
++	bgval = *bgdata;
++	kfree(bgdata);
++
++	ret = clk_prepare_enable(ac200->clk);
++	if (ret)
++		return ret;
++
++	/*
++	 * There is no documentation on how long we have to wait before
++	 * executing first operation. Vendor driver sleeps for 40 ms.
++	 */
++	msleep(40);
++
++	ret = regmap_write(ac200->regmap, AC200_SYS_CONTROL, 0);
++	if (ret)
++		goto err;
++
++	ret = regmap_write(ac200->regmap, AC200_SYS_CONTROL, 1);
++	if (ret)
++		goto err;
++
++	if (bgval) {
++		/* bandgap register is not documented */
++		ret = regmap_write(ac200->regmap, AC200_SYS_BG_CTL,
++				   0x8280 | bgval);
++		if (ret)
++			goto err;
++	}
++
++	ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE, ac200_cells,
++				   ARRAY_SIZE(ac200_cells), NULL, 0, NULL);
++	if (ret) {
++		dev_err(dev, "Failed to add MFD devices: %d\n", ret);
++		goto err;
++	}
++
++	return 0;
++
++err:
++	clk_disable_unprepare(ac200->clk);
++	return ret;
++}
++
++static void ac200_i2c_remove(struct i2c_client *i2c)
++{
++	struct ac200_dev *ac200 = i2c_get_clientdata(i2c);
++
++	regmap_write(ac200->regmap, AC200_SYS_CONTROL, 0);
++
++	clk_disable_unprepare(ac200->clk);
++}
++
++static const struct i2c_device_id ac200_ids[] = {
++	{ "ac200", },
++	{ }
++};
++MODULE_DEVICE_TABLE(i2c, ac200_ids);
++
++static const struct of_device_id ac200_of_match[] = {
++	{ .compatible = "x-powers,ac200" },
++	{ }
++};
++MODULE_DEVICE_TABLE(of, ac200_of_match);
++
++static struct i2c_driver ac200_i2c_driver = {
++	.driver = {
++		.name	= "ac200",
++		.of_match_table	= of_match_ptr(ac200_of_match),
++	},
++	.probe	= ac200_i2c_probe,
++	.remove = ac200_i2c_remove,
++	.id_table = ac200_ids,
++};
++module_i2c_driver(ac200_i2c_driver);
++
++MODULE_DESCRIPTION("MFD core driver for AC200");
++MODULE_AUTHOR("Jernej Skrabec <jernej.skrabec@gmail.com>");
++MODULE_LICENSE("GPL v2");
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/mmc-host-sunxi-mmc-Fix-H6-emmc.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/mmc-host-sunxi-mmc-Fix-H6-emmc.patch
new file mode 100644
index 000000000000..aa046be2b446
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/mmc-host-sunxi-mmc-Fix-H6-emmc.patch
@@ -0,0 +1,43 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: Ukhellfire <afaulkner420@gmail.com>
+Date: Thu, 24 Mar 2022 22:21:00 +0000
+Subject: mmc/host/sunxi-mmc: Fix H6 emmc
+
+We have the wrong MMC CAP voltage for the emmc on this board
+---
+ drivers/mmc/host/sunxi-mmc.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
+index 111111111111..222222222222 100644
+--- a/drivers/mmc/host/sunxi-mmc.c
++++ b/drivers/mmc/host/sunxi-mmc.c
+@@ -1232,6 +1232,7 @@ static const struct of_device_id sunxi_mmc_of_match[] = {
+ 	{ .compatible = "allwinner,sun50i-a100-mmc", .data = &sun20i_d1_cfg },
+ 	{ .compatible = "allwinner,sun50i-a100-emmc", .data = &sun50i_a100_emmc_cfg },
+ 	{ .compatible = "allwinner,sun50i-h5-emmc", .data = &sun50i_h5_emmc_cfg },
++	{ .compatible = "allwinner,sun50i-h6-emmc", .data = &sun50i_a64_emmc_cfg },
+ 	{ .compatible = "allwinner,sun50i-h616-mmc", .data = &sun50i_h616_cfg },
+ 	{ /* sentinel */ }
+ };
+@@ -1444,7 +1445,7 @@ static int sunxi_mmc_probe(struct platform_device *pdev)
+ 				  MMC_CAP_SDIO_IRQ;
+ 
+ 	/*
+-	 * Some H5 devices do not have signal traces precise enough to
++	 * Some H5 and H6 devices do not have signal traces precise enough to
+ 	 * use HS DDR mode for their eMMC chips.
+ 	 *
+ 	 * We still enable HS DDR modes for all the other controller
+@@ -1453,6 +1454,8 @@ static int sunxi_mmc_probe(struct platform_device *pdev)
+ 	if ((host->cfg->clk_delays || host->use_new_timings) &&
+ 	    !of_device_is_compatible(pdev->dev.of_node,
+ 				     "allwinner,sun50i-h5-emmc") &&
++	    !of_device_is_compatible(pdev->dev.of_node,
++				     "allwinner,sun50i-h6-emmc") &&
+ 	    !of_machine_is_compatible("allwinner,sun7i-a20") &&
+ 	    !of_machine_is_compatible("olimex,a64-olinuxino-2ge8g"))
+ 		mmc->caps      |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR;
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/net-phy-Add-support-for-AC200-EPHY.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/net-phy-Add-support-for-AC200-EPHY.patch
new file mode 100644
index 000000000000..04d079c551bf
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/net-phy-Add-support-for-AC200-EPHY.patch
@@ -0,0 +1,143 @@
+From 9ea339d70cfa03d39fecfc3d980c758ed67c4639 Mon Sep 17 00:00:00 2001
+From: Jernej Skrabec <jernej.skrabec@siol.net>
+Date: Fri, 16 Aug 2019 16:38:57 +0200
+Subject: net: phy: Add support for AC200 EPHY
+
+The X-Powers AC200 mixed signal chip contains a 100Mbit/s Ethernet PHY.
+While its sporting a usable default setup, and can be controlled by the
+generic IEEE802.3-C22 PHY driver, the BSP sets up some extra registers,
+which this driver here covers.
+
+Add a PHY driver matching the AC200 EPHY ID registers, and which
+programs some PHY registers according to the BSP code.
+
+Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+---
+ drivers/net/phy/Kconfig     |  7 ++++
+ drivers/net/phy/Makefile    |  1 +
+ drivers/net/phy/ac200-phy.c | 82 +++++++++++++++++++++++++++++++++++++
+ 3 files changed, 90 insertions(+)
+ create mode 100644 drivers/net/phy/ac200-phy.c
+
+diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
+index 01b235b3bb7e..be4670e6b266 100644
+--- a/drivers/net/phy/Kconfig
++++ b/drivers/net/phy/Kconfig
+@@ -84,6 +84,13 @@ config AIR_EN8811H_PHY
+ 	help
+ 	  Currently supports the Airoha EN8811H PHY.
+ 
++config AC200_PHY
++	tristate "AC200 EPHY"
++	depends on NVMEM
++	depends on OF
++	help
++	  Fast ethernet PHY as found in X-Powers AC200 multi-function device.
++
+ config AMD_PHY
+ 	tristate "AMD and Altima PHYs"
+ 	help
+diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
+index 90f886844381..4bba8c64bcc9 100644
+--- a/drivers/net/phy/Makefile
++++ b/drivers/net/phy/Makefile
+@@ -33,6 +33,7 @@ obj-$(CONFIG_SFP)		+= sfp.o
+ sfp-obj-$(CONFIG_SFP)		+= sfp-bus.o
+ obj-y				+= $(sfp-obj-y) $(sfp-obj-m)
+ 
++obj-$(CONFIG_AC200_PHY)		+= ac200-phy.o
+ obj-$(CONFIG_ADIN_PHY)		+= adin.o
+ obj-$(CONFIG_ADIN1100_PHY)	+= adin1100.o
+ obj-$(CONFIG_AIR_EN8811H_PHY)   += air_en8811h.o
+diff --git a/drivers/net/phy/ac200-phy.c b/drivers/net/phy/ac200-phy.c
+new file mode 100644
+index 000000000000..8499914f49b8
+--- /dev/null
++++ b/drivers/net/phy/ac200-phy.c
+@@ -0,0 +1,82 @@
++// SPDX-License-Identifier: GPL-2.0+
++/**
++ * Driver for AC200 Ethernet PHY
++ *
++ * Copyright (c) 2019 Jernej Skrabec <jernej.skrabec@gmail.com>
++ */
++
++#include <linux/clk.h>
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/phy.h>
++
++#define AC200_EPHY_ID			0x00441400
++#define AC200_EPHY_ID_MASK		0x0ffffff0
++
++static int ac200_ephy_config_init(struct phy_device *phydev)
++{
++	phy_write(phydev, 0x1f, 0x0100);	/* Switch to Page 1 */
++	phy_write(phydev, 0x12, 0x4824);	/* Disable APS */
++
++	phy_write(phydev, 0x1f, 0x0200);	/* Switch to Page 2 */
++	phy_write(phydev, 0x18, 0x0000);	/* PHYAFE TRX optimization */
++
++	phy_write(phydev, 0x1f, 0x0600);	/* Switch to Page 6 */
++	phy_write(phydev, 0x14, 0x708f);	/* PHYAFE TX optimization */
++	phy_write(phydev, 0x13, 0xF000);	/* PHYAFE RX optimization */
++	phy_write(phydev, 0x15, 0x1530);
++
++	phy_write(phydev, 0x1f, 0x0800);	/* Switch to Page 8 */
++	phy_write(phydev, 0x18, 0x00bc);	/* PHYAFE TRX optimization */
++
++	phy_write(phydev, 0x1f, 0x0100);	/* switch to page 1 */
++	phy_clear_bits(phydev, 0x17, BIT(3));	/* disable intelligent EEE */
++
++	/* disable 802.3az EEE */
++	phy_write(phydev, 0x1f, 0x0200);	/* switch to page 2 */
++	phy_write(phydev, 0x18, 0x0000);
++	phy_write(phydev, 0x1f, 0x0000);	/* switch to page 0 */
++	phy_clear_bits_mmd(phydev, 0x7, 0x3c, BIT(1));
++
++	/* FIXME: This is probably H6 specific */
++	phy_set_bits(phydev, 0x13, BIT(12));
++
++	return 0;
++}
++
++static int ac200_ephy_probe(struct phy_device *phydev)
++{
++	struct device *dev = &phydev->mdio.dev;
++	struct clk *clk;
++
++	clk = devm_clk_get_optional_enabled(dev, NULL);
++	if (IS_ERR(clk))
++		return dev_err_probe(dev, PTR_ERR(clk),
++				     "Failed to request clock\n");
++
++	return 0;
++}
++
++static struct phy_driver ac200_ephy_driver[] = {
++	{
++		.phy_id		= AC200_EPHY_ID,
++		.phy_id_mask	= AC200_EPHY_ID_MASK,
++		.name		= "Allwinner AC200 EPHY",
++		.soft_reset	= genphy_soft_reset,
++		.config_init	= ac200_ephy_config_init,
++		.probe		= ac200_ephy_probe,
++		.suspend	= genphy_suspend,
++		.resume		= genphy_resume,
++	}
++};
++module_phy_driver(ac200_ephy_driver);
++
++MODULE_AUTHOR("Jernej Skrabec <jernej.skrabec@gmail.com>");
++MODULE_DESCRIPTION("AC200 Ethernet PHY driver");
++MODULE_LICENSE("GPL");
++
++static const struct mdio_device_id __maybe_unused ac200_ephy_phy_tbl[] = {
++	{ AC200_EPHY_ID, AC200_EPHY_ID_MASK },
++	{ }
++};
++MODULE_DEVICE_TABLE(mdio, ac200_ephy_phy_tbl);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/net-usb-r8152-add-LED-configuration-from-OF.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/net-usb-r8152-add-LED-configuration-from-OF.patch
new file mode 100644
index 000000000000..79fdb8110f40
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/net-usb-r8152-add-LED-configuration-from-OF.patch
@@ -0,0 +1,79 @@
+From cacd7fedb13ba5cdc79835a8eaceb1c57425b8e5 Mon Sep 17 00:00:00 2001
+From: David Bauer <mail@david-bauer.net>
+Date: Sun, 26 Jul 2020 02:38:31 +0200
+Subject: net: usb: r8152: add LED configuration from OF
+
+This adds the ability to configure the LED configuration register using
+OF. This way, the correct value for board specific LED configuration can
+be determined.
+
+Signed-off-by: David Bauer <mail@david-bauer.net>
+---
+ drivers/net/usb/r8152.c | 23 +++++++++++++++++++++++
+ 1 file changed, 23 insertions(+)
+
+diff --git a/drivers/net/usb/r8152.c b/drivers/net/usb/r8152.c
+index 96fa3857d8e2..08f353953bbd 100644
+--- a/drivers/net/usb/r8152.c
++++ b/drivers/net/usb/r8152.c
+@@ -12,6 +12,7 @@
+ #include <linux/ethtool.h>
+ #include <linux/phy.h>
+ #include <linux/usb.h>
++#include <linux/of.h>
+ #include <linux/crc32.h>
+ #include <linux/if_vlan.h>
+ #include <linux/uaccess.h>
+@@ -7047,6 +7048,22 @@ static void rtl_tally_reset(struct r8152 *tp)
+ 	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
+ }
+ 
++static int r8152_led_configuration(struct r8152 *tp)
++{
++	u32 led_data;
++	int ret;
++
++	ret = of_property_read_u32(tp->udev->dev.of_node, "realtek,led-data",
++								&led_data);
++
++	if (ret)
++		return ret;
++	
++	ocp_write_word(tp, MCU_TYPE_PLA, PLA_LEDSEL, led_data);
++
++	return 0;
++}
++
+ static void r8152b_init(struct r8152 *tp)
+ {
+ 	u32 ocp_data;
+@@ -7088,6 +7105,8 @@ static void r8152b_init(struct r8152 *tp)
+ 	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
+ 	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
+ 	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
++
++	r8152_led_configuration(tp);
+ }
+ 
+ static void r8153_init(struct r8152 *tp)
+@@ -7228,6 +7247,8 @@ static void r8153_init(struct r8152 *tp)
+ 		tp->coalesce = COALESCE_SLOW;
+ 		break;
+ 	}
++
++	r8152_led_configuration(tp);
+ }
+ 
+ static void r8153b_init(struct r8152 *tp)
+@@ -7310,6 +7331,8 @@ static void r8153b_init(struct r8152 *tp)
+ 	rtl_tally_reset(tp);
+ 
+ 	tp->coalesce = 15000;	/* 15 us */
++
++	r8152_led_configuration(tp);
+ }
+ 
+ static void r8153c_init(struct r8152 *tp)
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/nvmem-sunxi_sid-add-sunxi_get_soc_chipid-sunxi_get_serial.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/nvmem-sunxi_sid-add-sunxi_get_soc_chipid-sunxi_get_serial.patch
new file mode 100644
index 000000000000..dc3a53160be9
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/nvmem-sunxi_sid-add-sunxi_get_soc_chipid-sunxi_get_serial.patch
@@ -0,0 +1,58 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Sat, 16 Apr 2022 11:19:05 +0300
+Subject: nvmem: sunxi_sid: add sunxi_get_soc_chipid, sunxi_get_serial
+
+---
+ drivers/nvmem/sunxi_sid.c | 28 ++++++++++
+ 1 file changed, 28 insertions(+)
+
+diff --git a/drivers/nvmem/sunxi_sid.c b/drivers/nvmem/sunxi_sid.c
+index 111111111111..222222222222 100644
+--- a/drivers/nvmem/sunxi_sid.c
++++ b/drivers/nvmem/sunxi_sid.c
+@@ -36,6 +36,25 @@ struct sunxi_sid {
+ 	u32			value_offset;
+ };
+ 
++static unsigned int sunxi_soc_chipid[4];
++static unsigned int sunxi_serial[4];
++
++int sunxi_get_soc_chipid(unsigned char *chipid)
++{
++	memcpy(chipid, sunxi_soc_chipid, 16);
++
++	return 0;
++}
++EXPORT_SYMBOL(sunxi_get_soc_chipid);
++
++int sunxi_get_serial(unsigned       char *serial)
++{
++	memcpy(serial, sunxi_serial, 16);
++
++	return 0;
++}
++EXPORT_SYMBOL(sunxi_get_serial);
++
+ static int sunxi_sid_read(void *context, unsigned int offset,
+ 			  void *val, size_t bytes)
+ {
+@@ -178,6 +197,15 @@ static int sunxi_sid_probe(struct platform_device *pdev)
+ 
+ 	platform_set_drvdata(pdev, nvmem);
+ 
++	nvmem_cfg->reg_read(sid, 0, &sunxi_soc_chipid[0], sizeof(int));
++	nvmem_cfg->reg_read(sid, 4, &sunxi_soc_chipid[1], sizeof(int));
++	nvmem_cfg->reg_read(sid, 8, &sunxi_soc_chipid[2], sizeof(int));
++	nvmem_cfg->reg_read(sid, 12, &sunxi_soc_chipid[3], sizeof(int));
++
++	sunxi_serial[0] = sunxi_soc_chipid[3];
++	sunxi_serial[1] = sunxi_soc_chipid[2];
++	sunxi_serial[2] = (sunxi_soc_chipid[1] >> 16) & 0x0ffff;
++
+ 	return 0;
+ }
+ 
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/scripts-add-overlay-compilation-support.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/scripts-add-overlay-compilation-support.patch
new file mode 100644
index 000000000000..1d71a347f7f1
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/scripts-add-overlay-compilation-support.patch
@@ -0,0 +1,86 @@
+From 2be34e5c09556a6c5304b36c03c5616856fdf73e Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Tue, 1 Feb 2022 21:04:08 +0300
+Subject: scripts: add overlay compilation support
+
+---
+ .gitignore               |  1 +
+ scripts/Makefile.dtbinst | 12 +++++++++++-
+ scripts/Makefile.lib     | 12 ++++++++++++
+ 3 files changed, 24 insertions(+), 1 deletion(-)
+
+diff --git a/.gitignore b/.gitignore
+index 5937c74d3dc1..3a2bea98567d 100644
+--- a/.gitignore
++++ b/.gitignore
+@@ -44,6 +44,7 @@
+ *.rpm
+ *.rsi
+ *.s
++*.scr
+ *.so
+ *.so.dbg
+ *.su
+diff --git a/scripts/Makefile.dtbinst b/scripts/Makefile.dtbinst
+index 9d920419a62c..dc0c8da28494 100644
+--- a/scripts/Makefile.dtbinst
++++ b/scripts/Makefile.dtbinst
+@@ -23,6 +23,11 @@ $(dst)/%: $(obj)/%
+ 	$(call cmd,dtb_install)
+ 
+ dtbs := $(patsubst $(obj)/%,%,$(call read-file, $(obj)/dtbs-list))
++vendor := $(sort $(dir $(filter %.dtb, $(dtbs))))
++subdir := $(sort $(dir $(filter %.dtbo, $(dtbs))))
++
++dtbs += $(patsubst $(obj)/%,%,$(if $(subdir), $(shell cd $(srctree)/$(obj) && find $(subdir) -name '*.scr')))
++dtbs += $(patsubst $(obj)/%,%,$(if $(subdir), $(shell cd $(srctree)/$(obj) && find $(subdir) -name 'README.*-overlays')))
+ 
+ ifdef CONFIG_ARCH_WANT_FLAT_DTB_INSTALL
+ 
+@@ -33,7 +38,12 @@ endef
+ 
+ $(foreach d, $(sort $(dir $(dtbs))), $(eval $(call gen_install_rules,$(d))))
+ 
+-dtbs := $(notdir $(dtbs))
++# Armbian uses subdirectories <overlay> for arm
++# and <allwinner/overlay> for arm64.
++# delete the vendor's directory if the target architecture is an arm.
++ifdef CONFIG_ARM
++dtbs := $(patsubst $(vendor)%,%,$(dtbs))
++endif
+ 
+ endif # CONFIG_ARCH_WANT_FLAT_DTB_INSTALL
+ 
+diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
+index cad20f0e66ee..2d8b0b41d5f0 100644
+--- a/scripts/Makefile.lib
++++ b/scripts/Makefile.lib
+@@ -75,6 +75,9 @@ always-y += $(hostprogs-always-y) $(hostprogs-always-m)
+ userprogs += $(userprogs-always-y) $(userprogs-always-m)
+ always-y += $(userprogs-always-y) $(userprogs-always-m)
+ 
++# Overlay Fixup script targets
++extra-y				+= $(scr-y) $(dtbotxt-y)
++
+ # Add subdir path
+ 
+ ifneq ($(obj),.)
+@@ -436,6 +439,15 @@ quiet_cmd_lz4_with_size = LZ4     $@
+       cmd_lz4_with_size = { cat $(real-prereqs) | $(LZ4) -l -9 - -; \
+                   $(size_append); } > $@
+ 
++# Fixup script mkimage provided by Armbian
++# ---------------------------------------------------------------------------
++
++quiet_cmd_scr = FIXUP IMAGE $@
++      cmd_scr = mkimage -C none -A $(ARCH) -T script -d $< $@
++
++$(obj)/%.scr: $(src)/%.scr-cmd FORCE
++	$(call if_changed,scr)
++
+ # U-Boot mkimage
+ # ---------------------------------------------------------------------------
+ 
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/sound-soc-sunxi-Provoke-the-early-load-of-sun8i-codec-analog.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/sound-soc-sunxi-Provoke-the-early-load-of-sun8i-codec-analog.patch
new file mode 100644
index 000000000000..2a65f4d8d43b
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/sound-soc-sunxi-Provoke-the-early-load-of-sun8i-codec-analog.patch
@@ -0,0 +1,27 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: wuweidong <625769020@qq.com>
+Date: Tue, 28 Nov 2017 17:25:19 +0800
+Subject: sound:soc:sunxi: Provoke the early load of sun8i-codec-analog
+
+---
+ sound/soc/sunxi/Makefile | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/sound/soc/sunxi/Makefile b/sound/soc/sunxi/Makefile
+index 111111111111..222222222222 100644
+--- a/sound/soc/sunxi/Makefile
++++ b/sound/soc/sunxi/Makefile
+@@ -1,9 +1,9 @@
+ # SPDX-License-Identifier: GPL-2.0
++obj-$(CONFIG_SND_SUN8I_CODEC_ANALOG) += sun8i-codec-analog.o
+ obj-$(CONFIG_SND_AC100_CODEC) += ac100-codec.o
+ obj-$(CONFIG_SND_SUN4I_CODEC) += sun4i-codec.o
+ obj-$(CONFIG_SND_SUN4I_I2S) += sun4i-i2s.o
+ obj-$(CONFIG_SND_SUN4I_SPDIF) += sun4i-spdif.o
+-obj-$(CONFIG_SND_SUN8I_CODEC_ANALOG) += sun8i-codec-analog.o
+ obj-$(CONFIG_SND_SUN50I_CODEC_ANALOG) += sun50i-codec-analog.o
+ obj-$(CONFIG_SND_SUN8I_CODEC) += sun8i-codec.o
+ obj-$(CONFIG_SND_SUN8I_ADDA_PR_REGMAP) += sun8i-adda-pr-regmap.o
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/sound-soc-sunxi-sun4i-codec-adcis-select-capture-source.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/sound-soc-sunxi-sun4i-codec-adcis-select-capture-source.patch
new file mode 100644
index 000000000000..4d4a87b9f43a
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/sound-soc-sunxi-sun4i-codec-adcis-select-capture-source.patch
@@ -0,0 +1,120 @@
+From 98c6b31384477c771ba47a5f34384d0b8c7dcfc4 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Wed, 2 Feb 2022 21:42:37 +0300
+Subject: sound:soc:sunxi:sun4i-codec adcis select capture source
+
+---
+ sound/soc/sunxi/sun4i-codec.c | 51 ++++++++++++++++++++++++++++++++---
+ 1 file changed, 47 insertions(+), 4 deletions(-)
+
+diff --git a/sound/soc/sunxi/sun4i-codec.c b/sound/soc/sunxi/sun4i-codec.c
+index 886b3fa537d2..5b67e2905a44 100644
+--- a/sound/soc/sunxi/sun4i-codec.c
++++ b/sound/soc/sunxi/sun4i-codec.c
+@@ -6,6 +6,7 @@
+  * Copyright 2015 Adam Sampson <ats@offog.org>
+  * Copyright 2016 Chen-Yu Tsai <wens@csie.org>
+  * Copyright 2018 Mesih Kilinc <mesihkilinc@gmail.com>
++ * Copyright 2021 gryzun <gryzun_an@rambler.ru>
+  *
+  * Based on the Allwinner SDK driver, released under the GPL.
+  */
+@@ -743,6 +744,16 @@ static struct snd_soc_dai_driver sun4i_codec_dai = {
+ };
+ 
+ /*** sun4i Codec ***/
++
++static const char *adcis_text[] = {"Line In", "FM In", "Mic1 Mono", "Mic2 Mono",
++			"Mic1,Mic2", "Mic1+2 Mono", "MIX Out", "Line,Mic1"};
++
++static SOC_ENUM_SINGLE_DECL(adcis_mixer, SUN4I_CODEC_ADC_ACTL,
++					SUN4I_CODEC_ADC_ACTL_ADCIS, adcis_text);
++
++static const struct snd_kcontrol_new sun4i_codec_mux_controls =
++	SOC_DAPM_ENUM("Capture Source Capture Route", adcis_mixer);
++
+ static const struct snd_kcontrol_new sun4i_codec_pa_mute =
+ 	SOC_DAPM_SINGLE("Switch", SUN4I_CODEC_DAC_ACTL,
+ 			SUN4I_CODEC_DAC_ACTL_PA_MUTE, 1, 0);
+@@ -756,6 +767,8 @@ static DECLARE_TLV_DB_SCALE(sun4i_codec_fmin_loopback_gain_scale, -450, 150,
+ 			    0);
+ static DECLARE_TLV_DB_SCALE(sun4i_codec_micin_loopback_gain_scale, -450, 150,
+ 			    0);
++static DECLARE_TLV_DB_SCALE(sun4i_codec_capture_gain_scale, -450, 150,
++			    0);
+ static DECLARE_TLV_DB_RANGE(sun4i_codec_micin_preamp_gain_scale,
+ 			    0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
+ 			    1, 7, TLV_DB_SCALE_ITEM(3500, 300, 0));
+@@ -809,6 +822,9 @@ static const struct snd_kcontrol_new sun7i_codec_controls[] = {
+ 	SOC_SINGLE_TLV("Mic2 Boost Volume", SUN7I_CODEC_AC_MIC_PHONE_CAL,
+ 		       SUN7I_CODEC_AC_MIC_PHONE_CAL_PREG2, 7, 0,
+ 		       sun7i_codec_micin_preamp_gain_scale),
++	SOC_SINGLE_TLV("Capture Boost Capture Volume", SUN4I_CODEC_ADC_ACTL,
++		       SUN4I_CODEC_ADC_ACTL_VADCG, 7, 0,
++		       sun4i_codec_capture_gain_scale),
+ };
+ 
+ static const struct snd_kcontrol_new sun4i_codec_mixer_controls[] = {
+@@ -887,6 +903,13 @@ static const struct snd_soc_dapm_widget sun4i_codec_codec_dapm_widgets[] = {
+ 	SND_SOC_DAPM_PGA("MIC2 Pre-Amplifier", SUN4I_CODEC_ADC_ACTL,
+ 			 SUN4I_CODEC_ADC_ACTL_PREG2EN, 0, NULL, 0),
+ 
++	/* ADC Mux */
++	SND_SOC_DAPM_MUX("Right Capture Source Capture Route", SND_SOC_NOPM, 0, 0,
++		&sun4i_codec_mux_controls),
++
++	SND_SOC_DAPM_MUX("Left Capture Source Capture Route", SND_SOC_NOPM, 0, 0,
++		&sun4i_codec_mux_controls),
++
+ 	/* Power Amplifier */
+ 	SND_SOC_DAPM_MIXER("Power Amplifier", SUN4I_CODEC_ADC_ACTL,
+ 			   SUN4I_CODEC_ADC_ACTL_PA_EN, 0,
+@@ -915,6 +938,30 @@ static const struct snd_soc_dapm_route sun4i_codec_codec_dapm_routes[] = {
+ 	{ "Right ADC", NULL, "ADC" },
+ 	{ "Right DAC", NULL, "DAC" },
+ 
++	/* Left Mux Capture Routes */
++	{ "Left Capture Source Capture Route", "Mic1 Mono", "MIC1 Pre-Amplifier" },
++	{ "Left Capture Source Capture Route", "Mic2 Mono", "MIC2 Pre-Amplifier" },
++	{ "Left Capture Source Capture Route", "Line In", "Line Left" },
++	{ "Left Capture Source Capture Route", "FM In", "FM Left" },
++	{ "Left Capture Source Capture Route", "MIX Out", "Left Mixer" },
++	{ "Left Capture Source Capture Route", "Mic1,Mic2", "MIC1 Pre-Amplifier" },
++	{ "Left Capture Source Capture Route", "Mic1+2 Mono", "MIC1 Pre-Amplifier" },
++	{ "Left Capture Source Capture Route", "Mic1+2 Mono", "MIC2 Pre-Amplifier" },
++	{ "Left Capture Source Capture Route", "Line,Mic1", "Line Left" },
++	{ "Left ADC", NULL, "Left Capture Source Capture Route" },
++
++	/* Right Mux Capture Routes */
++	{ "Right Capture Source Capture Route", "Mic1 Mono", "MIC1 Pre-Amplifier" },
++	{ "Right Capture Source Capture Route", "Mic2 Mono", "MIC2 Pre-Amplifier" },
++	{ "Right Capture Source Capture Route", "Line In", "Line Right" },
++	{ "Right Capture Source Capture Route", "FM In", "FM Right" },
++	{ "Right Capture Source Capture Route", "MIX Out", "Right Mixer" },
++	{ "Right Capture Source Capture Route", "Mic1,Mic2", "MIC2 Pre-Amplifier" },
++	{ "Right Capture Source Capture Route", "Mic1+2 Mono", "MIC1 Pre-Amplifier" },
++	{ "Right Capture Source Capture Route", "Mic1+2 Mono", "MIC2 Pre-Amplifier" },
++	{ "Right Capture Source Capture Route", "Line,Mic1", "MIC1 Pre-Amplifier" },
++	{ "Right ADC", NULL, "Right Capture Source Capture Route" },
++
+ 	/* Right Mixer Routes */
+ 	{ "Right Mixer", NULL, "Mixer Enable" },
+ 	{ "Right Mixer", "Right Mixer Left DAC Playback Switch", "Left DAC" },
+@@ -944,14 +991,10 @@ static const struct snd_soc_dapm_route sun4i_codec_codec_dapm_routes[] = {
+ 	{ "HP Left", NULL, "Power Amplifier Mute" },
+ 
+ 	/* Mic1 Routes */
+-	{ "Left ADC", NULL, "MIC1 Pre-Amplifier" },
+-	{ "Right ADC", NULL, "MIC1 Pre-Amplifier" },
+ 	{ "MIC1 Pre-Amplifier", NULL, "Mic1"},
+ 	{ "Mic1", NULL, "VMIC" },
+ 
+ 	/* Mic2 Routes */
+-	{ "Left ADC", NULL, "MIC2 Pre-Amplifier" },
+-	{ "Right ADC", NULL, "MIC2 Pre-Amplifier" },
+ 	{ "MIC2 Pre-Amplifier", NULL, "Mic2"},
+ 	{ "Mic2", NULL, "VMIC" },
+ };
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/sound-soc-sunxi-sun8i-codec-analog-enable-sound.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/sound-soc-sunxi-sun8i-codec-analog-enable-sound.patch
new file mode 100644
index 000000000000..0430a51895fb
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/sound-soc-sunxi-sun8i-codec-analog-enable-sound.patch
@@ -0,0 +1,31 @@
+From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
+From: The-going <48602507+The-going@users.noreply.github.com>
+Date: Fri, 28 Jan 2022 13:04:18 +0300
+Subject: sound:soc:sunxi:sun8i-codec-analog enable sound
+
+---
+ sound/soc/sunxi/sun8i-codec-analog.c | 8 ++++++--
+ 1 file changed, 6 insertions(+), 2 deletions(-)
+
+diff --git a/sound/soc/sunxi/sun8i-codec-analog.c b/sound/soc/sunxi/sun8i-codec-analog.c
+index 111111111111..222222222222 100644
+--- a/sound/soc/sunxi/sun8i-codec-analog.c
++++ b/sound/soc/sunxi/sun8i-codec-analog.c
+@@ -728,8 +728,12 @@ static int sun8i_codec_analog_add_mixer(struct snd_soc_component *cmpnt,
+ }
+ 
+ static const struct sun8i_codec_analog_quirks sun8i_v3s_quirks = {
+-	.has_headphone	= true,
+-	.has_hmic	= true,
++	.has_headphone  = true,
++	.has_hmic       = true,
++	.has_linein     = true,
++	.has_lineout    = true,
++	.has_mbias      = true,
++	.has_mic2       = true,
+ };
+ 
+ static int sun8i_codec_analog_cmpnt_probe(struct snd_soc_component *cmpnt)
+-- 
+Armbian
+
diff --git a/patch/kernel/archive/sunxi-6.14/series.armbian b/patch/kernel/archive/sunxi-6.14/series.armbian
new file mode 100644
index 000000000000..cec3991ad8e4
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/series.armbian
@@ -0,0 +1,182 @@
+################################################################################
+#
+#                  Armbian patches
+#
+################################################################################
+	patches.armbian/Doc-dt-bindings-usb-add-binding-for-DWC3-controller-on-Allwinne.patch
+	patches.armbian/drv-pinctrl-pinctrl-sun50i-a64-disable_strict_mode.patch
+	patches.armbian/drv-rtc-sun6i-support-RTCs-without-external-LOSCs.patch
+	patches.armbian/drv-gpu-drm-gem-dma-Export-with-handle-allocator.patch
+	patches.armbian/drv-gpu-drm-sun4i-Add-GEM-allocator.patch
+	patches.armbian/Revert-drm-sun4i-hdmi-switch-to-struct-drm_edid.patch
+	patches.armbian/drv-gpu-drm-sun4i-Add-HDMI-audio-sun4i-hdmi-encoder.patch
+	patches.armbian/drv-net-stmmac-dwmac-sun8i-second-EMAC-clock-register.patch
+	patches.armbian/drv-phy-sun4i-usb-Allow-reset-line-to-be-shared.patch
+	patches.armbian/drv-staging-media-sunxi-cedrus-add-H616-variant.patch
+	patches.armbian/drv-soc-sunxi-sram-Add-SRAM-C1-H616-handling.patch
+	patches.armbian/drv-media-dvb-frontends-si2168-fix-cmd-timeout.patch
+	patches.armbian/include-uapi-drm_fourcc-add-ARM-tiled-format-modifier.patch
+	patches.armbian/drv-clocksource-arm_arch_timer-fix-a64-timejump.patch
+	patches.armbian/sound-soc-sunxi-sun8i-codec-analog-enable-sound.patch
+	patches.armbian/sound-soc-sunxi-Provoke-the-early-load-of-sun8i-codec-analog.patch
+	patches.armbian/sound-soc-sunxi-sun4i-codec-adcis-select-capture-source.patch
+	patches.armbian/drv-mmc-host-sunxi-mmc-add-h5-emmc-compatible.patch
+	patches.armbian/drv-pinctrl-sunxi-pinctrl-sun50i-h6.c-GPIO-disable_strict_mode.patch
+	patches.armbian/drv-gpu-drm-sun4i-sun8i_mixer.c-add-h3-mixer1.patch
+	patches.armbian/drv-mtd-nand-raw-nand_ids.c-add-H27UBG8T2BTR-BC-nand.patch
+	patches.armbian/drv-mfd-axp20x-add-sysfs-interface.patch
+	patches.armbian/drv-spi-spidev-Add-armbian-spi-dev-compatible.patch
+	patches.armbian/drv-spi-spi-sun4i.c-spi-bug-low-on-sck.patch
+	patches.armbian/drv-rtc-sun6i-Add-Allwinner-H616-support.patch
+	patches.armbian/drv-nvmem-sunxi_sid-Support-SID-on-H616.patch
+	patches.armbian/drv-iio-adc-axp20x_adc-arm64-dts-axp803-hwmon-enable-thermal.patch
+	patches.armbian/drv-gpu-drm-panel-simple-Add-compability-olinuxino-lcd.patch
+	patches.armbian/drv-input-touchscreen-sun4i-ts-Enable-parsing.patch
+	patches.armbian/drv-mmc-host-sunxi-mmc-Disable-DDR52-mode-on-all-A20-based-boar.patch
+	patches.armbian/drv-usb-gadget-composite-rename-gadget-serial-console-manufactu.patch
+	patches.armbian/Add-FB_TFT-ST7796S-driver.patch
+	patches.armbian/Optimize-TSC2007-touchscreen-add-polling-method.patch
+	patches.armbian/Add-ws2812-RGB-driver-for-allwinner-H616.patch
+	patches.armbian/drv-staging-rtl8723bs-AP-bugfix.patch
+	patches.armbian/Fix-include-uapi-spi-spidev-module.patch
+	patches.armbian/Add-dump_reg-and-sunxi-sysinfo-drivers.patch
+	patches.armbian/Add-sunxi-addr-driver-Used-to-fix-uwe5622-bluetooth-MAC-address.patch
+	patches.armbian/nvmem-sunxi_sid-add-sunxi_get_soc_chipid-sunxi_get_serial.patch
+	patches.armbian/mmc-host-sunxi-mmc-Fix-H6-emmc.patch
+	patches.armbian/net-usb-r8152-add-LED-configuration-from-OF.patch
+	patches.armbian/drivers-devfreq-sun8i-a33-mbus-disable-autorefresh.patch
+	patches.armbian/clk-gate-add-support-for-regmap-based-gates.patch
+	patches.armbian/mfd-Add-support-for-X-Powers-AC200.patch
+	patches.armbian/mfd-Add-support-for-X-Powers-AC200-EPHY-syscon.patch
+	patches.armbian/net-phy-Add-support-for-AC200-EPHY.patch
+	patches.armbian/ASoC-AC200-Initial-driver.patch
+	patches.armbian/Input-axp20x-pek-allow-wakeup-after-shutdown.patch
+	patches.armbian/driver-allwinner-h618-emac.patch
+	patches.armbian/drivers-pwm-Add-pwm-sunxi-enhance-driver-for-h616.patch
+	patches.armbian/arm-patch-call-flush_icache-ASAP-after-writing-new-instruction.patch
+	patches.armbian/arm-arm64-dts-Add-leds-axp20x-charger.patch
+	patches.armbian/arm-dts-sun9i-a80-add-thermal-sensor.patch
+	patches.armbian/arm-dts-sun9i-a80-add-thermal-zone.patch
+	patches.armbian/arm-dts-sun7i-a20-Disable-OOB-IRQ-for-brcm-wifi-on-Cubietruck-a.patch
+	patches.armbian/arm-dts-a20-orangepi-and-mini-fix-phy-mode-hdmi.patch
+	patches.armbian/arm-dts-sun8i-h3-nanopi-add-leds-pio-pins.patch
+	patches.armbian/arm-dts-a10-cubiebord-a20-cubietruck-green-LED-mmc0-default-tri.patch
+	patches.armbian/arm-dts-Add-sun8i-h2-plus-nanopi-duo-device.patch
+	patches.armbian/arm-dts-Add-sun8i-h2-plus-sunvell-r69-device.patch
+	patches.armbian/arm-dts-h3-nanopi-neo-Add-regulator-leds-mmc2.patch
+	patches.armbian/arm-dts-h3-nanopi-neo-air-Add-regulator-camera-wifi-bluetooth-o.patch
+	patches.armbian/arm-dts-h3-orangepi-2-Add-regulator-vdd-cpu.patch
+	patches.armbian/arm-dts-sun8i-r40-bananapi-m2-ultra-add-codec-analog.patch
+	patches.armbian/arm-dts-sun7i-a20-cubietruck-add-alias-uart2.patch
+	patches.armbian/arm-dts-sun8i-v3s-s3-pinecube-enable-sound-codec.patch
+	patches.armbian/arm-dts-sun8i-r40-add-clk_out_a-fix-bananam2ultra.patch
+	patches.armbian/arm-dts-sun8i-h3-bananapi-m2-plus-add-wifi_pwrseq.patch
+	patches.armbian/arm-dts-sun7i-a20-bananapro-add-hdmi-connector-de.patch
+	patches.armbian/arm-dts-sun7i-a20-bananapro-add-AXP209-regulators.patch
+	patches.armbian/arm-dts-sunxi-h3-h5.dtsi-force-mmc0-bus-width.patch
+	patches.armbian/fix-cpu-opp-table-sun8i-a83t.patch
+	patches.armbian/arm64-dts-sun50i-a64-pine64-enable-wifi-mmc1.patch
+	patches.armbian/arm64-dts-sun50i-a64-sopine-baseboard-Add-i2s2-mmc1.patch
+	patches.armbian/arm64-dts-sun50i-h6-Add-r_uart-uart2-3-pins.patch
+	patches.armbian/arm64-dts-sun50i-h616.dtsi-reserved-memory-512K-for-BL31.patch
+	patches.armbian/arm64-dts-sun50i-h616-orangepi-zero2-reg_usb1_vbus-status-ok.patch
+	patches.armbian/arm64-dts-sun50i-h616-orangepi-zero2-Enable-GPU-mali.patch
+	patches.armbian/arm64-dts-allwinner-sun50i-h616-Add-VPU-node.patch
+	patches.armbian/arm64-dts-sun50i-h616-x96-mate-T95-eth-sd-card-hack.patch
+	patches.armbian/arm64-dts-sun50i-h616-x96-mate-add-hdmi.patch
+	patches.armbian/arm64-dts-allwinner-Add-axp313a.dtsi.patch
+	patches.armbian/arm64-dts-add-sun50i-h618-cpu-dvfs.dtsi.patch
+	patches.armbian/LED-green_power_on-red_status_heartbeat-arch-arm64-boot-dts-all.patch
+	patches.armbian/arm64-dts-allwinner-h616-orangepi-zero2-Enable-expansion-board-.patch
+	patches.armbian/arm64-dts-sun50i-a64-pine64-enable-Bluetooth.patch
+	patches.armbian/arm64-dts-sun50i-a64-sopine-baseboard-enable-Bluetooth.patch
+	patches.armbian/arm64-dts-nanopi-a64-set-right-phy-mode-to-rgmii-id.patch
+	patches.armbian/arm64-dts-FIXME-a64-olinuxino-add-regulator-audio-mmc.patch
+	patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-k1-plus-device.patch
+	patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-neo-core2-device.patch
+	patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-neo2-v1.1-device.patch
+	patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-m1-plus2-device.patch
+	patches.armbian/arm64-dts-sun50i-h5-nanopi-neo2-add-regulator-led-triger.patch
+	patches.armbian/arm64-dts-sun50i-h5-orangepi-pc2-add-spi-flash.patch
+	patches.armbian/arm64-dts-sun50i-h5-orangepi-prime-add-regulator.patch
+	patches.armbian/arm64-dts-sun50i-h5-orangepi-zero-plus-add-regulator.patch
+	patches.armbian/arm64-dts-sun50i-h6.dtsi-improve-thermals.patch
+	patches.armbian/arm64-dts-sun50i-h6-orangepi-3-delete-node-spi0.patch
+	patches.armbian/arm64-dts-sun50i-h6-orangepi-lite2-spi0-usb3phy-dwc3-enable.patch
+	patches.armbian/arm64-dts-sun50i-h6-pine-h64-add-wifi-rtl8723cs.patch
+	patches.armbian/arm64-dts-sun50i-h6-pine-h64-add-dwc3-usb3phy.patch
+	patches.armbian/arm64-dts-sun50i-a64-pine64-add-spi0.patch
+	patches.armbian/arm64-dts-sun50i-h6.dtsi-add-pinctrl-pins-for-spi.patch
+	patches.armbian/arm64-dts-sun50i-a64-orangepi-win-add-aliase-ethernet1.patch
+	patches.armbian/arm64-dts-sun50i-a64-force-mmc0-bus-width.patch
+	patches.armbian/drv-of-Device-Tree-Overlay-ConfigFS-interface.patch
+	patches.armbian/scripts-add-overlay-compilation-support.patch
+	patches.armbian/Enable-creation-of-__symbols__-node.patch
+	patches.armbian/Makefile-CONFIG_SHELL-fix-for-builddeb-packaging.patch
+	patches.armbian/arm-dts-overlay-Add-Overlays-for-sunxi.patch
+	patches.armbian/arm64-dts-allwinner-overlay-Add-Overlays-for-sunxi64.patch
+	patches.armbian/arm-dts-overlay-sun8i-h3-cpu-clock-add-overclock.patch
+	patches.armbian/arm64-dts-overlay-sun50i-a64-pine64-7inch-lcd.patch
+	patches.armbian/arm64-dts-overlay-sun50i-h5-add-gpio-regulator-overclock.patch
+	patches.armbian/Move-sun50i-h6-pwm-settings-to-its-own-overlay.patch
+	patches.armbian/Compile-the-pwm-overlay.patch
+	patches.armbian/cb1-overlay.patch
+	patches.armbian/Correct-perf-interrupt-source-number-as-referenced-in-the-Allwi.patch
+	patches.armbian/Enable-DMA-support-for-the-Allwinner-A10-EMAC-which-already-exi.patch
+	patches.armbian/arm-dts-sunxi-h3-h5.dtsi-add-i2s0-i2s1-pins.patch
+	patches.armbian/arm-dts-sun5i-a13-olinuxino-micro-add-panel-lcd-olinuxino-4.3.patch
+	patches.armbian/arm-dts-sun5i-a13-olinuxino-Add-panel-lcd-olinuxino-4.3-needed-.patch
+	patches.armbian/arm-dts-sun7i-a20-olinuxino-micro-emmc-Add-vqmmc-node.patch
+	patches.armbian/arm-dts-sun7i-a20-olinuxino-lime2-enable-audio-codec.patch
+	patches.armbian/arm-dts-sun7i-a20-olinuxino-lime2-enable-ldo3-always-on.patch
+	patches.armbian/arm-dts-sun7i-a20-olimex-som-204-evb-olinuxino-micro-decrease-d.patch
+	patches.armbian/arm-dts-sun8i-h3-add-thermal-zones.patch
+	patches.armbian/arm64-dts-sun50i-a64-olinuxino-add-boards.patch
+	patches.armbian/arm64-dts-sun50i-a64-olinuxino-emmc-enable-bluetooth.patch
+	patches.armbian/arm64-dts-sun50i-a64-olinuxino-1Ge16GW-enable-bluetooth.patch
+	patches.armbian/arm64-dts-sun50i-a64.dtsi-adjust-thermal-trip-points.patch
+	patches.armbian/arm64-dts-sun50i-a64-olinuxino-1Ge16GW-Disable-clock-phase-and-.patch
+	patches.armbian/Temp_fix-mailbox-arch-arm64-boot-dts-allwinner-sun50i-a64-pinep.patch
+	patches.armbian/arm64-dts-sun50i-h6-orangepi-3-add-r_uart-aliase.patch
+	patches.armbian/arm64-dts-sun50i-h5-add-cpu-opp-refs.patch
+	patches.armbian/arm64-dts-sun50i-h5-add-termal-zones.patch
+	patches.armbian/arm64-dts-sun50i-h6-orangepi-add-cpu-opp-refs.patch
+	patches.armbian/arm64-dts-sun50i-h6-orangepi-enable-higher-clock-regulator-max-.patch
+	patches.armbian/arm-dts-sun8i-h3-orangepi-pc-plus-add-wifi_pwrseq.patch
+	patches.armbian/arm64-dts-sun50i-h5-orangepi-prime-add-rtl8723cs.patch
+	patches.armbian/arm-dts-sun8i-h2-plus-orangepi-zero-fix-xradio-interrupt.patch
+	patches.armbian/arm64-dts-allwinner-sun50i-h6-Fix-H6-emmc.patch
+	patches.armbian/arm64-dts-sun50i-h5-nanopi-r1s-h5-add-rtl8153-support.patch
+	patches.armbian/arm64-dts-sun50i-h6-orangepi.dtsi-Rollback-r_rsb-to-r_i2c.patch
+	patches.armbian/arm64-dts-sun50i-h616-bigtreetech-cb1-sd-emmc.patch
+	patches.armbian/ARM-dts-sun8i-nanopiduo2-Use-key-0-as-power-button.patch
+	patches.armbian/ARM-dts-sun8i-nanopiduo2-enable-ethernet.patch
+	patches.armbian/arm-dts-sun8i-h3-reduce-opp-microvolt-to-prevent-not-supported-.patch
+	patches.armbian/arm64-dts-sun50i-h5-enable-power-button-for-orangepi-prime.patch
+	patches.armbian/enable-TV-Output-on-OrangePi-Zero-LTE.patch
+	patches.armbian/arm64-dts-allwinner-h6-Add-AC200-EPHY-nodes.patch
+	patches.armbian/arm64-dts-allwinner-h6-tanix-enable-Ethernet.patch
+	patches.armbian/arm64-dts-allwinner-h6-add-AC200-codec-nodes.patch
+	patches.armbian/arm64-dts-allwinner-h6-enable-AC200-codec.patch
+	patches.armbian/add-nodes-for-sunxi-info-sunxi-addr-and-sunxi-dump-reg.patch
+	patches.armbian/add-initial-support-for-orangepi3-lts.patch
+	patches.armbian/Add-wifi-nodes-for-Inovato-Quadra.patch
+	patches.armbian/arm64-dts-h616-add-wifi-support-for-orange-pi-zero-2-and-zero3.patch
+	patches.armbian/arm64-dts-sun50i-h618-orangepi-zero3-Enable-GPU-mali.patch
+	patches.armbian/arm64-dts-h616-add-hdmi-support-for-zero2-and-zero3.patch
+	patches.armbian/arm64-sun50i-h616-Add-i2c-2-3-4-uart-2-5-pins.patch
+	patches.armbian/arm64-dts-sun50i-h616-add-pwm-nodes-support.patch
+	patches.armbian/arm64-dts-h616-8-Add-overlays-i2c-pwm-uart.patch
+	patches.armbian/arm64-dts-sun50i-h618-orangepi-zero2w-Add-missing-nodes.patch
+	patches.armbian/add-dtb-overlay-for-zero2w.patch
+	patches.armbian/Sound-for-H616-H618-Allwinner-SOCs.patch
+	patches.armbian/ARM64-dts-sun50i-h616-BigTreeTech-CB1-Enable-HDMI.patch
+	patches.armbian/ARM64-dts-sun50i-h616-BigTreeTech-CB1-Enable-EMAC1.patch
+	patches.armbian/arm64-dts-sun50i-h313-x96q-lpddr3.patch
+	patches.armbian/Add-board-BananaPi-BPI-M4-Zero.patch
+	patches.armbian/Add-BananaPi-BPI-M4-Zero-pinctrl.patch
+	patches.armbian/Add-BananaPi-BPI-M4-Zero-overlays.patch
+	patches.armbian/Fix-ghost-touches-on-tsc2007-tft-screen.patch
+	patches.armbian/arm-dts-sun8i-h2-plus-orangepi-zero-fix-usb_otg-dr_mode.patch
+	patches.armbian/BigTreeTech-CB1-dts-i2c-gpio-mode-adjustment-and-ws2812-rgb_val.patch
+	patches.armbian/arm64-allwinner-Add-sun50i-h618-bananapi-m4-berry-support.patch
diff --git a/patch/kernel/archive/sunxi-6.14/series.conf b/patch/kernel/archive/sunxi-6.14/series.conf
index 01aee915e783..48216cde788a 100644
--- a/patch/kernel/archive/sunxi-6.14/series.conf
+++ b/patch/kernel/archive/sunxi-6.14/series.conf
@@ -300,3 +300,186 @@
 	patches.media/media-cedrus-Implement-AFBC-YUV420-formats-for-H265.patch
 	patches.media/media-cedrus-Increase-H6-clock-rate.patch
 	patches.media/dma-sun6i-dma-add-sun50i-h616-support.patch
+
+################################################################################
+#
+#                  Armbian patches
+#
+################################################################################
+	patches.armbian/Doc-dt-bindings-usb-add-binding-for-DWC3-controller-on-Allwinne.patch
+	patches.armbian/drv-pinctrl-pinctrl-sun50i-a64-disable_strict_mode.patch
+	patches.armbian/drv-rtc-sun6i-support-RTCs-without-external-LOSCs.patch
+	patches.armbian/drv-gpu-drm-gem-dma-Export-with-handle-allocator.patch
+	patches.armbian/drv-gpu-drm-sun4i-Add-GEM-allocator.patch
+	patches.armbian/Revert-drm-sun4i-hdmi-switch-to-struct-drm_edid.patch
+	patches.armbian/drv-gpu-drm-sun4i-Add-HDMI-audio-sun4i-hdmi-encoder.patch
+	patches.armbian/drv-net-stmmac-dwmac-sun8i-second-EMAC-clock-register.patch
+	patches.armbian/drv-phy-sun4i-usb-Allow-reset-line-to-be-shared.patch
+	patches.armbian/drv-staging-media-sunxi-cedrus-add-H616-variant.patch
+	patches.armbian/drv-soc-sunxi-sram-Add-SRAM-C1-H616-handling.patch
+	patches.armbian/drv-media-dvb-frontends-si2168-fix-cmd-timeout.patch
+	patches.armbian/include-uapi-drm_fourcc-add-ARM-tiled-format-modifier.patch
+	patches.armbian/drv-clocksource-arm_arch_timer-fix-a64-timejump.patch
+	patches.armbian/sound-soc-sunxi-sun8i-codec-analog-enable-sound.patch
+	patches.armbian/sound-soc-sunxi-Provoke-the-early-load-of-sun8i-codec-analog.patch
+	patches.armbian/sound-soc-sunxi-sun4i-codec-adcis-select-capture-source.patch
+	patches.armbian/drv-mmc-host-sunxi-mmc-add-h5-emmc-compatible.patch
+	patches.armbian/drv-pinctrl-sunxi-pinctrl-sun50i-h6.c-GPIO-disable_strict_mode.patch
+	patches.armbian/drv-gpu-drm-sun4i-sun8i_mixer.c-add-h3-mixer1.patch
+	patches.armbian/drv-mtd-nand-raw-nand_ids.c-add-H27UBG8T2BTR-BC-nand.patch
+	patches.armbian/drv-mfd-axp20x-add-sysfs-interface.patch
+	patches.armbian/drv-spi-spidev-Add-armbian-spi-dev-compatible.patch
+	patches.armbian/drv-spi-spi-sun4i.c-spi-bug-low-on-sck.patch
+	patches.armbian/drv-rtc-sun6i-Add-Allwinner-H616-support.patch
+	patches.armbian/drv-nvmem-sunxi_sid-Support-SID-on-H616.patch
+	patches.armbian/drv-iio-adc-axp20x_adc-arm64-dts-axp803-hwmon-enable-thermal.patch
+	patches.armbian/drv-gpu-drm-panel-simple-Add-compability-olinuxino-lcd.patch
+	patches.armbian/drv-input-touchscreen-sun4i-ts-Enable-parsing.patch
+	patches.armbian/drv-mmc-host-sunxi-mmc-Disable-DDR52-mode-on-all-A20-based-boar.patch
+	patches.armbian/drv-usb-gadget-composite-rename-gadget-serial-console-manufactu.patch
+	patches.armbian/Add-FB_TFT-ST7796S-driver.patch
+	patches.armbian/Optimize-TSC2007-touchscreen-add-polling-method.patch
+	patches.armbian/Add-ws2812-RGB-driver-for-allwinner-H616.patch
+	patches.armbian/drv-staging-rtl8723bs-AP-bugfix.patch
+	patches.armbian/Fix-include-uapi-spi-spidev-module.patch
+	patches.armbian/Add-dump_reg-and-sunxi-sysinfo-drivers.patch
+	patches.armbian/Add-sunxi-addr-driver-Used-to-fix-uwe5622-bluetooth-MAC-address.patch
+	patches.armbian/nvmem-sunxi_sid-add-sunxi_get_soc_chipid-sunxi_get_serial.patch
+	patches.armbian/mmc-host-sunxi-mmc-Fix-H6-emmc.patch
+	patches.armbian/net-usb-r8152-add-LED-configuration-from-OF.patch
+	patches.armbian/drivers-devfreq-sun8i-a33-mbus-disable-autorefresh.patch
+	patches.armbian/clk-gate-add-support-for-regmap-based-gates.patch
+	patches.armbian/mfd-Add-support-for-X-Powers-AC200.patch
+	patches.armbian/mfd-Add-support-for-X-Powers-AC200-EPHY-syscon.patch
+	patches.armbian/net-phy-Add-support-for-AC200-EPHY.patch
+	patches.armbian/ASoC-AC200-Initial-driver.patch
+	patches.armbian/Input-axp20x-pek-allow-wakeup-after-shutdown.patch
+	patches.armbian/driver-allwinner-h618-emac.patch
+	patches.armbian/drivers-pwm-Add-pwm-sunxi-enhance-driver-for-h616.patch
+	patches.armbian/arm-patch-call-flush_icache-ASAP-after-writing-new-instruction.patch
+	patches.armbian/arm-arm64-dts-Add-leds-axp20x-charger.patch
+	patches.armbian/arm-dts-sun9i-a80-add-thermal-sensor.patch
+	patches.armbian/arm-dts-sun9i-a80-add-thermal-zone.patch
+	patches.armbian/arm-dts-sun7i-a20-Disable-OOB-IRQ-for-brcm-wifi-on-Cubietruck-a.patch
+	patches.armbian/arm-dts-a20-orangepi-and-mini-fix-phy-mode-hdmi.patch
+	patches.armbian/arm-dts-sun8i-h3-nanopi-add-leds-pio-pins.patch
+	patches.armbian/arm-dts-a10-cubiebord-a20-cubietruck-green-LED-mmc0-default-tri.patch
+	patches.armbian/arm-dts-Add-sun8i-h2-plus-nanopi-duo-device.patch
+	patches.armbian/arm-dts-Add-sun8i-h2-plus-sunvell-r69-device.patch
+	patches.armbian/arm-dts-h3-nanopi-neo-Add-regulator-leds-mmc2.patch
+	patches.armbian/arm-dts-h3-nanopi-neo-air-Add-regulator-camera-wifi-bluetooth-o.patch
+	patches.armbian/arm-dts-h3-orangepi-2-Add-regulator-vdd-cpu.patch
+	patches.armbian/arm-dts-sun8i-r40-bananapi-m2-ultra-add-codec-analog.patch
+	patches.armbian/arm-dts-sun7i-a20-cubietruck-add-alias-uart2.patch
+	patches.armbian/arm-dts-sun8i-v3s-s3-pinecube-enable-sound-codec.patch
+	patches.armbian/arm-dts-sun8i-r40-add-clk_out_a-fix-bananam2ultra.patch
+	patches.armbian/arm-dts-sun8i-h3-bananapi-m2-plus-add-wifi_pwrseq.patch
+	patches.armbian/arm-dts-sun7i-a20-bananapro-add-hdmi-connector-de.patch
+	patches.armbian/arm-dts-sun7i-a20-bananapro-add-AXP209-regulators.patch
+	patches.armbian/arm-dts-sunxi-h3-h5.dtsi-force-mmc0-bus-width.patch
+	patches.armbian/fix-cpu-opp-table-sun8i-a83t.patch
+	patches.armbian/arm64-dts-sun50i-a64-pine64-enable-wifi-mmc1.patch
+	patches.armbian/arm64-dts-sun50i-a64-sopine-baseboard-Add-i2s2-mmc1.patch
+	patches.armbian/arm64-dts-sun50i-h6-Add-r_uart-uart2-3-pins.patch
+	patches.armbian/arm64-dts-sun50i-h616.dtsi-reserved-memory-512K-for-BL31.patch
+	patches.armbian/arm64-dts-sun50i-h616-orangepi-zero2-reg_usb1_vbus-status-ok.patch
+	patches.armbian/arm64-dts-sun50i-h616-orangepi-zero2-Enable-GPU-mali.patch
+	patches.armbian/arm64-dts-allwinner-sun50i-h616-Add-VPU-node.patch
+	patches.armbian/arm64-dts-sun50i-h616-x96-mate-T95-eth-sd-card-hack.patch
+	patches.armbian/arm64-dts-sun50i-h616-x96-mate-add-hdmi.patch
+	patches.armbian/arm64-dts-allwinner-Add-axp313a.dtsi.patch
+	patches.armbian/arm64-dts-add-sun50i-h618-cpu-dvfs.dtsi.patch
+	patches.armbian/LED-green_power_on-red_status_heartbeat-arch-arm64-boot-dts-all.patch
+	patches.armbian/arm64-dts-allwinner-h616-orangepi-zero2-Enable-expansion-board-.patch
+	patches.armbian/arm64-dts-sun50i-a64-pine64-enable-Bluetooth.patch
+	patches.armbian/arm64-dts-sun50i-a64-sopine-baseboard-enable-Bluetooth.patch
+	patches.armbian/arm64-dts-nanopi-a64-set-right-phy-mode-to-rgmii-id.patch
+	patches.armbian/arm64-dts-FIXME-a64-olinuxino-add-regulator-audio-mmc.patch
+	patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-k1-plus-device.patch
+	patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-neo-core2-device.patch
+	patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-neo2-v1.1-device.patch
+	patches.armbian/arm64-dts-Add-sun50i-h5-nanopi-m1-plus2-device.patch
+	patches.armbian/arm64-dts-sun50i-h5-nanopi-neo2-add-regulator-led-triger.patch
+	patches.armbian/arm64-dts-sun50i-h5-orangepi-pc2-add-spi-flash.patch
+	patches.armbian/arm64-dts-sun50i-h5-orangepi-prime-add-regulator.patch
+	patches.armbian/arm64-dts-sun50i-h5-orangepi-zero-plus-add-regulator.patch
+	patches.armbian/arm64-dts-sun50i-h6.dtsi-improve-thermals.patch
+	patches.armbian/arm64-dts-sun50i-h6-orangepi-3-delete-node-spi0.patch
+	patches.armbian/arm64-dts-sun50i-h6-orangepi-lite2-spi0-usb3phy-dwc3-enable.patch
+	patches.armbian/arm64-dts-sun50i-h6-pine-h64-add-wifi-rtl8723cs.patch
+	patches.armbian/arm64-dts-sun50i-h6-pine-h64-add-dwc3-usb3phy.patch
+	patches.armbian/arm64-dts-sun50i-a64-pine64-add-spi0.patch
+	patches.armbian/arm64-dts-sun50i-h6.dtsi-add-pinctrl-pins-for-spi.patch
+	patches.armbian/arm64-dts-sun50i-a64-orangepi-win-add-aliase-ethernet1.patch
+	patches.armbian/arm64-dts-sun50i-a64-force-mmc0-bus-width.patch
+	patches.armbian/drv-of-Device-Tree-Overlay-ConfigFS-interface.patch
+	patches.armbian/scripts-add-overlay-compilation-support.patch
+	patches.armbian/Enable-creation-of-__symbols__-node.patch
+	patches.armbian/Makefile-CONFIG_SHELL-fix-for-builddeb-packaging.patch
+	patches.armbian/arm-dts-overlay-Add-Overlays-for-sunxi.patch
+	patches.armbian/arm64-dts-allwinner-overlay-Add-Overlays-for-sunxi64.patch
+	patches.armbian/arm-dts-overlay-sun8i-h3-cpu-clock-add-overclock.patch
+	patches.armbian/arm64-dts-overlay-sun50i-a64-pine64-7inch-lcd.patch
+	patches.armbian/arm64-dts-overlay-sun50i-h5-add-gpio-regulator-overclock.patch
+	patches.armbian/Move-sun50i-h6-pwm-settings-to-its-own-overlay.patch
+	patches.armbian/Compile-the-pwm-overlay.patch
+	patches.armbian/cb1-overlay.patch
+	patches.armbian/Correct-perf-interrupt-source-number-as-referenced-in-the-Allwi.patch
+	patches.armbian/Enable-DMA-support-for-the-Allwinner-A10-EMAC-which-already-exi.patch
+	patches.armbian/arm-dts-sunxi-h3-h5.dtsi-add-i2s0-i2s1-pins.patch
+	patches.armbian/arm-dts-sun5i-a13-olinuxino-micro-add-panel-lcd-olinuxino-4.3.patch
+	patches.armbian/arm-dts-sun5i-a13-olinuxino-Add-panel-lcd-olinuxino-4.3-needed-.patch
+	patches.armbian/arm-dts-sun7i-a20-olinuxino-micro-emmc-Add-vqmmc-node.patch
+	patches.armbian/arm-dts-sun7i-a20-olinuxino-lime2-enable-audio-codec.patch
+	patches.armbian/arm-dts-sun7i-a20-olinuxino-lime2-enable-ldo3-always-on.patch
+	patches.armbian/arm-dts-sun7i-a20-olimex-som-204-evb-olinuxino-micro-decrease-d.patch
+	patches.armbian/arm-dts-sun8i-h3-add-thermal-zones.patch
+	patches.armbian/arm64-dts-sun50i-a64-olinuxino-add-boards.patch
+	patches.armbian/arm64-dts-sun50i-a64-olinuxino-emmc-enable-bluetooth.patch
+	patches.armbian/arm64-dts-sun50i-a64-olinuxino-1Ge16GW-enable-bluetooth.patch
+	patches.armbian/arm64-dts-sun50i-a64.dtsi-adjust-thermal-trip-points.patch
+	patches.armbian/arm64-dts-sun50i-a64-olinuxino-1Ge16GW-Disable-clock-phase-and-.patch
+	patches.armbian/Temp_fix-mailbox-arch-arm64-boot-dts-allwinner-sun50i-a64-pinep.patch
+	patches.armbian/arm64-dts-sun50i-h6-orangepi-3-add-r_uart-aliase.patch
+	patches.armbian/arm64-dts-sun50i-h5-add-cpu-opp-refs.patch
+	patches.armbian/arm64-dts-sun50i-h5-add-termal-zones.patch
+	patches.armbian/arm64-dts-sun50i-h6-orangepi-add-cpu-opp-refs.patch
+	patches.armbian/arm64-dts-sun50i-h6-orangepi-enable-higher-clock-regulator-max-.patch
+	patches.armbian/arm-dts-sun8i-h3-orangepi-pc-plus-add-wifi_pwrseq.patch
+	patches.armbian/arm64-dts-sun50i-h5-orangepi-prime-add-rtl8723cs.patch
+	patches.armbian/arm-dts-sun8i-h2-plus-orangepi-zero-fix-xradio-interrupt.patch
+	patches.armbian/arm64-dts-allwinner-sun50i-h6-Fix-H6-emmc.patch
+	patches.armbian/arm64-dts-sun50i-h5-nanopi-r1s-h5-add-rtl8153-support.patch
+	patches.armbian/arm64-dts-sun50i-h6-orangepi.dtsi-Rollback-r_rsb-to-r_i2c.patch
+	patches.armbian/arm64-dts-sun50i-h616-bigtreetech-cb1-sd-emmc.patch
+	patches.armbian/ARM-dts-sun8i-nanopiduo2-Use-key-0-as-power-button.patch
+	patches.armbian/ARM-dts-sun8i-nanopiduo2-enable-ethernet.patch
+	patches.armbian/arm-dts-sun8i-h3-reduce-opp-microvolt-to-prevent-not-supported-.patch
+	patches.armbian/arm64-dts-sun50i-h5-enable-power-button-for-orangepi-prime.patch
+	patches.armbian/enable-TV-Output-on-OrangePi-Zero-LTE.patch
+	patches.armbian/arm64-dts-allwinner-h6-Add-AC200-EPHY-nodes.patch
+	patches.armbian/arm64-dts-allwinner-h6-tanix-enable-Ethernet.patch
+	patches.armbian/arm64-dts-allwinner-h6-add-AC200-codec-nodes.patch
+	patches.armbian/arm64-dts-allwinner-h6-enable-AC200-codec.patch
+	patches.armbian/add-nodes-for-sunxi-info-sunxi-addr-and-sunxi-dump-reg.patch
+	patches.armbian/add-initial-support-for-orangepi3-lts.patch
+	patches.armbian/Add-wifi-nodes-for-Inovato-Quadra.patch
+	patches.armbian/arm64-dts-h616-add-wifi-support-for-orange-pi-zero-2-and-zero3.patch
+	patches.armbian/arm64-dts-sun50i-h618-orangepi-zero3-Enable-GPU-mali.patch
+	patches.armbian/arm64-dts-h616-add-hdmi-support-for-zero2-and-zero3.patch
+	patches.armbian/arm64-sun50i-h616-Add-i2c-2-3-4-uart-2-5-pins.patch
+	patches.armbian/arm64-dts-sun50i-h616-add-pwm-nodes-support.patch
+	patches.armbian/arm64-dts-h616-8-Add-overlays-i2c-pwm-uart.patch
+	patches.armbian/arm64-dts-sun50i-h618-orangepi-zero2w-Add-missing-nodes.patch
+	patches.armbian/add-dtb-overlay-for-zero2w.patch
+	patches.armbian/Sound-for-H616-H618-Allwinner-SOCs.patch
+	patches.armbian/ARM64-dts-sun50i-h616-BigTreeTech-CB1-Enable-HDMI.patch
+	patches.armbian/ARM64-dts-sun50i-h616-BigTreeTech-CB1-Enable-EMAC1.patch
+	patches.armbian/arm64-dts-sun50i-h313-x96q-lpddr3.patch
+	patches.armbian/Add-board-BananaPi-BPI-M4-Zero.patch
+	patches.armbian/Add-BananaPi-BPI-M4-Zero-pinctrl.patch
+	patches.armbian/Add-BananaPi-BPI-M4-Zero-overlays.patch
+	patches.armbian/Fix-ghost-touches-on-tsc2007-tft-screen.patch
+	patches.armbian/arm-dts-sun8i-h2-plus-orangepi-zero-fix-usb_otg-dr_mode.patch
+	patches.armbian/BigTreeTech-CB1-dts-i2c-gpio-mode-adjustment-and-ws2812-rgb_val.patch
+	patches.armbian/arm64-allwinner-Add-sun50i-h618-bananapi-m4-berry-support.patch

From 70fb8dabdf12dfc8b8bd8d22b68f8880c8b8c5ba Mon Sep 17 00:00:00 2001
From: The-going <48602507+The-going@users.noreply.github.com>
Date: Wed, 30 Apr 2025 15:08:24 +0300
Subject: [PATCH 5/7] sunxi-6.14: Switching EDGE to v6.14.4

---
 config/sources/families/include/sunxi64_common.inc | 4 ++--
 config/sources/families/include/sunxi_common.inc   | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/config/sources/families/include/sunxi64_common.inc b/config/sources/families/include/sunxi64_common.inc
index 2edad427281a..999fcaec4f4e 100644
--- a/config/sources/families/include/sunxi64_common.inc
+++ b/config/sources/families/include/sunxi64_common.inc
@@ -35,8 +35,8 @@ case $BRANCH in
 		;;
 
 	edge)
-		declare -g KERNEL_MAJOR_MINOR="6.13" # Major and minor versions of this kernel.
-		declare -g KERNELBRANCH="tag:v6.13.11"
+		declare -g KERNEL_MAJOR_MINOR="6.14" # Major and minor versions of this kernel.
+		declare -g KERNELBRANCH="tag:v6.14.4"
 		;;
 esac
 
diff --git a/config/sources/families/include/sunxi_common.inc b/config/sources/families/include/sunxi_common.inc
index c2f19cdc4923..6eea68583741 100644
--- a/config/sources/families/include/sunxi_common.inc
+++ b/config/sources/families/include/sunxi_common.inc
@@ -36,8 +36,8 @@ case $BRANCH in
 		;;
 
 	edge)
-		declare -g KERNEL_MAJOR_MINOR="6.13" # Major and minor versions of this kernel.
-		declare -g KERNELBRANCH="tag:v6.13.11"
+		declare -g KERNEL_MAJOR_MINOR="6.14" # Major and minor versions of this kernel.
+		declare -g KERNELBRANCH="tag:v6.14.4"
 		;;
 esac
 

From 5bbc92b7eb0237e213ef4b9b9ef626563992a091 Mon Sep 17 00:00:00 2001
From: The-going <48602507+The-going@users.noreply.github.com>
Date: Sat, 3 May 2025 11:39:42 +0300
Subject: [PATCH 6/7] sunxi-6.14: Swtching to v6.14.5 and re-export patches

---
 .../families/include/sunxi64_common.inc       |  2 +-
 .../sources/families/include/sunxi_common.inc |  2 +-
 ...tch-parent-of-MIPI-DSI-to-periph0-1x.patch |  6 ++---
 ...etected-CPU-bin-for-easier-debugging.patch |  6 ++---
 ...ing-dclk-rate-upon-ancestor-clock-ch.patch | 24 +++++++++----------
 ...2145-Galaxycore-camera-module-driver.patch |  6 ++---
 ...river-for-Himax-HM5065-camera-sensor.patch |  6 ++---
 ..._probe-to-handle-EPROBE_DEFER-errors.patch | 10 ++++----
 ...set_resume-callback-for-WWAN-devices.patch |  6 ++---
 9 files changed, 34 insertions(+), 34 deletions(-)

diff --git a/config/sources/families/include/sunxi64_common.inc b/config/sources/families/include/sunxi64_common.inc
index 999fcaec4f4e..60f13316b0ff 100644
--- a/config/sources/families/include/sunxi64_common.inc
+++ b/config/sources/families/include/sunxi64_common.inc
@@ -36,7 +36,7 @@ case $BRANCH in
 
 	edge)
 		declare -g KERNEL_MAJOR_MINOR="6.14" # Major and minor versions of this kernel.
-		declare -g KERNELBRANCH="tag:v6.14.4"
+		declare -g KERNELBRANCH="tag:v6.14.5"
 		;;
 esac
 
diff --git a/config/sources/families/include/sunxi_common.inc b/config/sources/families/include/sunxi_common.inc
index 6eea68583741..56430d14ba02 100644
--- a/config/sources/families/include/sunxi_common.inc
+++ b/config/sources/families/include/sunxi_common.inc
@@ -37,7 +37,7 @@ case $BRANCH in
 
 	edge)
 		declare -g KERNEL_MAJOR_MINOR="6.14" # Major and minor versions of this kernel.
-		declare -g KERNELBRANCH="tag:v6.14.4"
+		declare -g KERNELBRANCH="tag:v6.14.5"
 		;;
 esac
 
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/clk-sunxi-ng-sun50i-a64-Switch-parent-of-MIPI-DSI-to-periph0-1x.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/clk-sunxi-ng-sun50i-a64-Switch-parent-of-MIPI-DSI-to-periph0-1x.patch
index b12fb911ef18..d754dc1acd8f 100644
--- a/patch/kernel/archive/sunxi-6.14/patches.megous/clk-sunxi-ng-sun50i-a64-Switch-parent-of-MIPI-DSI-to-periph0-1x.patch
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/clk-sunxi-ng-sun50i-a64-Switch-parent-of-MIPI-DSI-to-periph0-1x.patch
@@ -1,4 +1,4 @@
-From 99e1ff82c84ee35099cd1dade28df0c963fdbf20 Mon Sep 17 00:00:00 2001
+From ca29006df14a1f3d0f292e207753bd5925604259 Mon Sep 17 00:00:00 2001
 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
 Date: Mon, 14 Aug 2023 07:28:11 +0200
 Subject: clk: sunxi-ng: sun50i-a64: Switch parent of MIPI-DSI to periph0(1x)
@@ -9,8 +9,8 @@ and HDMI output at once.
 
 Signed-off-by: Ondrej Jirman <megi@xff.cz>
 ---
- drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 11 ++++++++++-
- 1 file changed, 10 insertions(+), 1 deletion(-)
+ drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 13 ++++++++++++-
+ 1 file changed, 12 insertions(+), 1 deletion(-)
 
 diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
 index 4b3068bdfdf2..e76a1c10f390 100644
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/cpufreq-sun50i-Show-detected-CPU-bin-for-easier-debugging.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/cpufreq-sun50i-Show-detected-CPU-bin-for-easier-debugging.patch
index 208baf6df17f..491989f8f35c 100644
--- a/patch/kernel/archive/sunxi-6.14/patches.megous/cpufreq-sun50i-Show-detected-CPU-bin-for-easier-debugging.patch
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/cpufreq-sun50i-Show-detected-CPU-bin-for-easier-debugging.patch
@@ -1,4 +1,4 @@
-From 2489a1cedce4d285ac0f18f5ff39ecb07e178f4a Mon Sep 17 00:00:00 2001
+From dd65bf79988be12849efef080d4ecb86e225cd2e Mon Sep 17 00:00:00 2001
 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
 Date: Thu, 31 Oct 2019 18:31:32 +0100
 Subject: cpufreq: sun50i: Show detected CPU bin, for easier debugging
@@ -12,10 +12,10 @@ Signed-off-by: Ondrej Jirman <megi@xff.cz>
  1 file changed, 2 insertions(+)
 
 diff --git a/drivers/cpufreq/sun50i-cpufreq-nvmem.c b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
-index 47d6840b3489..8992d281a818 100644
+index 744312a44279..d8c1be2b30fb 100644
 --- a/drivers/cpufreq/sun50i-cpufreq-nvmem.c
 +++ b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
-@@ -262,6 +262,8 @@ static int sun50i_cpufreq_nvmem_probe(struct platform_device *pdev)
+@@ -268,6 +268,8 @@ static int sun50i_cpufreq_nvmem_probe(struct platform_device *pdev)
  	snprintf(name, sizeof(name), "speed%d", speed);
  	config.prop_name = name;
  
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/drm-sun4i-tcon-Support-keeping-dclk-rate-upon-ancestor-clock-ch.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/drm-sun4i-tcon-Support-keeping-dclk-rate-upon-ancestor-clock-ch.patch
index cbfa0952d5fa..733079732090 100644
--- a/patch/kernel/archive/sunxi-6.14/patches.megous/drm-sun4i-tcon-Support-keeping-dclk-rate-upon-ancestor-clock-ch.patch
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/drm-sun4i-tcon-Support-keeping-dclk-rate-upon-ancestor-clock-ch.patch
@@ -1,4 +1,4 @@
-From 47d49fbc4a674b45279c3dbc20ab911e3ea470fe Mon Sep 17 00:00:00 2001
+From acc83b9c1798eb38d27e8bb273d5fd1f79f8c33a Mon Sep 17 00:00:00 2001
 From: Frank Oltmanns <frank@oltmanns.dev>
 Date: Sun, 10 Mar 2024 14:32:29 +0100
 Subject: drm/sun4i: tcon: Support keeping dclk rate upon ancestor clock
@@ -23,10 +23,10 @@ Signed-off-by: Frank Oltmanns <frank@oltmanns.dev>
  2 files changed, 76 insertions(+), 6 deletions(-)
 
 diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
-index b36c1ea0948c..221df37406d8 100644
+index fca95b76e258..0a493142b100 100644
 --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
 +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
-@@ -110,9 +110,11 @@ static void sun4i_tcon_channel_set_status(struct sun4i_tcon *tcon, int channel,
+@@ -108,9 +108,11 @@ static void sun4i_tcon_channel_set_status(struct sun4i_tcon *tcon, int channel,
  
  	if (enabled) {
  		clk_prepare_enable(clk);
@@ -40,7 +40,7 @@ index b36c1ea0948c..221df37406d8 100644
  		clk_disable_unprepare(clk);
  	}
  }
-@@ -373,6 +375,53 @@ static void sun4i_tcon0_mode_set_dithering(struct sun4i_tcon *tcon,
+@@ -343,6 +345,53 @@ static void sun4i_tcon0_mode_set_dithering(struct sun4i_tcon *tcon,
  	regmap_write(tcon->regs, SUN4I_TCON_FRM_CTL_REG, val);
  }
  
@@ -94,7 +94,7 @@ index b36c1ea0948c..221df37406d8 100644
  static void sun4i_tcon0_mode_set_cpu(struct sun4i_tcon *tcon,
  				     const struct drm_encoder *encoder,
  				     const struct drm_display_mode *mode)
-@@ -390,8 +439,8 @@ static void sun4i_tcon0_mode_set_cpu(struct sun4i_tcon *tcon,
+@@ -360,8 +409,8 @@ static void sun4i_tcon0_mode_set_cpu(struct sun4i_tcon *tcon,
  	 */
  	tcon->dclk_min_div = SUN6I_DSI_TCON_DIV;
  	tcon->dclk_max_div = SUN6I_DSI_TCON_DIV;
@@ -105,7 +105,7 @@ index b36c1ea0948c..221df37406d8 100644
  
  	/* Set the resolution */
  	regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
-@@ -464,7 +513,7 @@ static void sun4i_tcon0_mode_set_lvds(struct sun4i_tcon *tcon,
+@@ -434,7 +483,7 @@ static void sun4i_tcon0_mode_set_lvds(struct sun4i_tcon *tcon,
  
  	tcon->dclk_min_div = 7;
  	tcon->dclk_max_div = 7;
@@ -114,7 +114,7 @@ index b36c1ea0948c..221df37406d8 100644
  
  	/* Set the resolution */
  	regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
-@@ -548,7 +597,7 @@ static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon,
+@@ -518,7 +567,7 @@ static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon,
  
  	tcon->dclk_min_div = tcon->quirks->dclk_min_div;
  	tcon->dclk_max_div = 127;
@@ -123,7 +123,7 @@ index b36c1ea0948c..221df37406d8 100644
  
  	/* Set the resolution */
  	regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
-@@ -1561,6 +1610,14 @@ static const struct sun4i_tcon_quirks sun8i_a33_quirks = {
+@@ -1505,6 +1554,14 @@ static const struct sun4i_tcon_quirks sun8i_a33_quirks = {
  	.supports_lvds		= true,
  };
  
@@ -138,7 +138,7 @@ index b36c1ea0948c..221df37406d8 100644
  static const struct sun4i_tcon_quirks sun8i_a83t_lcd_quirks = {
  	.supports_lvds		= true,
  	.has_channel_0		= true,
-@@ -1619,6 +1676,7 @@ const struct of_device_id sun4i_tcon_of_table[] = {
+@@ -1563,6 +1620,7 @@ const struct of_device_id sun4i_tcon_of_table[] = {
  	{ .compatible = "allwinner,sun9i-a80-tcon-tv", .data = &sun9i_a80_tcon_tv_quirks },
  	{ .compatible = "allwinner,sun20i-d1-tcon-lcd", .data = &sun20i_d1_lcd_quirks },
  	{ .compatible = "allwinner,sun20i-d1-tcon-tv", .data = &sun8i_r40_tv_quirks },
@@ -147,10 +147,10 @@ index b36c1ea0948c..221df37406d8 100644
  };
  MODULE_DEVICE_TABLE(of, sun4i_tcon_of_table);
 diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/sun4i_tcon.h
-index 864d70b9d242..729d64b78846 100644
+index fa23aa23fe4a..bd4abc90062b 100644
 --- a/drivers/gpu/drm/sun4i/sun4i_tcon.h
 +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h
-@@ -250,6 +250,7 @@ struct sun4i_tcon_quirks {
+@@ -243,6 +243,7 @@ struct sun4i_tcon_quirks {
  	bool    needs_edp_reset; /* a80 edp reset needed for tcon0 access */
  	bool	supports_lvds;   /* Does the TCON support an LVDS output? */
  	bool	polarity_in_ch0; /* some tcon1 channels have polarity bits in tcon0 pol register */
@@ -158,7 +158,7 @@ index 864d70b9d242..729d64b78846 100644
  	u8	dclk_min_div;	/* minimum divider for TCON0 DCLK */
  
  	/* callback to handle tcon muxing options */
-@@ -312,4 +313,15 @@ void sun4i_tcon_enable_gamma(struct sun4i_tcon *tcon, bool enable);
+@@ -300,4 +301,15 @@ void sun4i_tcon_set_status(struct sun4i_tcon *crtc,
  
  extern const struct of_device_id sun4i_tcon_of_table[];
  
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/media-gc2145-Galaxycore-camera-module-driver.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/media-gc2145-Galaxycore-camera-module-driver.patch
index 8c14e25c5c13..3ea449ebef15 100644
--- a/patch/kernel/archive/sunxi-6.14/patches.megous/media-gc2145-Galaxycore-camera-module-driver.patch
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/media-gc2145-Galaxycore-camera-module-driver.patch
@@ -1,4 +1,4 @@
-From 3226585412fac36bbcb0dc88f54020aeb25feadb Mon Sep 17 00:00:00 2001
+From 57c06d951021ac23bc4850ca6bbf1513848a6a06 Mon Sep 17 00:00:00 2001
 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
 Date: Tue, 23 Jun 2020 19:51:18 +0200
 Subject: media: gc2145: Galaxycore camera module driver
@@ -14,10 +14,10 @@ Signed-off-by: Ondrej Jirman <megi@xff.cz>
  create mode 100644 drivers/media/i2c/gc2145.c
 
 diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig
-index 43be07cc5b37..2b3b4635c2f0 100644
+index 0cc793fc7910..017d993a8c49 100644
 --- a/drivers/media/i2c/Kconfig
 +++ b/drivers/media/i2c/Kconfig
-@@ -711,6 +711,16 @@ config VIDEO_HM5065
+@@ -712,6 +712,16 @@ config VIDEO_HM5065
  	  This is a V4L2 sensor-level driver for Himax HM5065
  	  5 Mpixel camera.
  
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/media-hm5065-Add-subdev-driver-for-Himax-HM5065-camera-sensor.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/media-hm5065-Add-subdev-driver-for-Himax-HM5065-camera-sensor.patch
index 9b7294ef167c..a9b0d8c5af26 100644
--- a/patch/kernel/archive/sunxi-6.14/patches.megous/media-hm5065-Add-subdev-driver-for-Himax-HM5065-camera-sensor.patch
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/media-hm5065-Add-subdev-driver-for-Himax-HM5065-camera-sensor.patch
@@ -1,4 +1,4 @@
-From b6f1f790b9f8dafcf115391cb36d80c8d7b75fb2 Mon Sep 17 00:00:00 2001
+From 198b881fede9a9acae6cf9dc4e100735985e2785 Mon Sep 17 00:00:00 2001
 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
 Date: Sat, 30 Sep 2017 02:39:48 +0200
 Subject: media: hm5065: Add subdev driver for Himax HM5065 camera sensor
@@ -21,10 +21,10 @@ Signed-off-by: Ondrej Jirman <megi@xff.cz>
  create mode 100644 drivers/media/i2c/hm5065.c
 
 diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig
-index 8ba096b8ebca..e7da18f3da3c 100644
+index 85ecb2aeefdb..2be73870045c 100644
 --- a/drivers/media/i2c/Kconfig
 +++ b/drivers/media/i2c/Kconfig
-@@ -701,6 +701,16 @@ config VIDEO_VGXY61
+@@ -702,6 +702,16 @@ config VIDEO_VGXY61
  source "drivers/media/i2c/ccs/Kconfig"
  source "drivers/media/i2c/et8ek8/Kconfig"
  
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/sunxi-Use-dev_err_probe-to-handle-EPROBE_DEFER-errors.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/sunxi-Use-dev_err_probe-to-handle-EPROBE_DEFER-errors.patch
index 7ae868ce5db9..34bc969e904c 100644
--- a/patch/kernel/archive/sunxi-6.14/patches.megous/sunxi-Use-dev_err_probe-to-handle-EPROBE_DEFER-errors.patch
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/sunxi-Use-dev_err_probe-to-handle-EPROBE_DEFER-errors.patch
@@ -1,4 +1,4 @@
-From d4a21d660b3fd92157aef4a08d0451c171c529e9 Mon Sep 17 00:00:00 2001
+From a30a50421a3d54842e8f42974617c24aa7512fe6 Mon Sep 17 00:00:00 2001
 From: =?UTF-8?q?Ond=C5=99ej=20Jirman?= <megi@xff.cz>
 Date: Mon, 2 Sep 2019 14:51:17 +0200
 Subject: sunxi: Use dev_err_probe to handle EPROBE_DEFER errors
@@ -28,10 +28,10 @@ index 2336ee2aa44a..20efde3cb1c2 100644
  		}
  
 diff --git a/drivers/gpu/drm/panel/panel-sitronix-st7703.c b/drivers/gpu/drm/panel/panel-sitronix-st7703.c
-index 8e359c9e0a09..ff6871e93730 100644
+index 6d3ad83be141..18afc2aff29c 100644
 --- a/drivers/gpu/drm/panel/panel-sitronix-st7703.c
 +++ b/drivers/gpu/drm/panel/panel-sitronix-st7703.c
-@@ -904,7 +904,7 @@ static int st7703_probe(struct mipi_dsi_device *dsi)
+@@ -887,7 +887,7 @@ static int st7703_probe(struct mipi_dsi_device *dsi)
  
  	ret = mipi_dsi_attach(dsi);
  	if (ret < 0) {
@@ -124,10 +124,10 @@ index 3a42865f9a5b..3d8d94594bc5 100644
  		}
  
 diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
-index a19a27cea860..0107514e7d2b 100644
+index 36eab95271b2..f83df7554aac 100644
 --- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
 +++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
-@@ -584,13 +584,15 @@ static int sun6i_dphy_probe(struct platform_device *pdev)
+@@ -570,13 +570,15 @@ static int sun6i_dphy_probe(struct platform_device *pdev)
  	dphy->regs = devm_regmap_init_mmio_clk(&pdev->dev, "bus",
  					       regs, &sun6i_dphy_regmap_config);
  	if (IS_ERR(dphy->regs)) {
diff --git a/patch/kernel/archive/sunxi-6.14/patches.megous/usb-serial-option-add-reset_resume-callback-for-WWAN-devices.patch b/patch/kernel/archive/sunxi-6.14/patches.megous/usb-serial-option-add-reset_resume-callback-for-WWAN-devices.patch
index 9001f922ab63..6bba1f6bd702 100644
--- a/patch/kernel/archive/sunxi-6.14/patches.megous/usb-serial-option-add-reset_resume-callback-for-WWAN-devices.patch
+++ b/patch/kernel/archive/sunxi-6.14/patches.megous/usb-serial-option-add-reset_resume-callback-for-WWAN-devices.patch
@@ -1,4 +1,4 @@
-From 0e8b72e264443819a1e8674ac9318ec382c84050 Mon Sep 17 00:00:00 2001
+From cf701dfb5650ddb3cd4b83baa0715c6cb7c3fc5e Mon Sep 17 00:00:00 2001
 From: Thomas Thorne <Thomas.Thorne@Net2Edge.com>
 Date: Tue, 20 Sep 2022 20:34:57 -0400
 Subject: usb: serial: option: add 'reset_resume' callback for WWAN devices
@@ -17,10 +17,10 @@ However the rest of the patch is not needed/already upstreamed.
  1 file changed, 1 insertion(+)
 
 diff --git a/drivers/usb/serial/option.c b/drivers/usb/serial/option.c
-index 5cd26dac2069..f65c1d78a2cc 100644
+index 27879cc57536..4adc2f535ce4 100644
 --- a/drivers/usb/serial/option.c
 +++ b/drivers/usb/serial/option.c
-@@ -2471,6 +2471,7 @@ static struct usb_serial_driver option_1port_device = {
+@@ -2474,6 +2474,7 @@ static struct usb_serial_driver option_1port_device = {
  #ifdef CONFIG_PM
  	.suspend           = usb_wwan_suspend,
  	.resume            = usb_wwan_resume,

From 0f45ac516272e99ff0bcec555506c35486d65938 Mon Sep 17 00:00:00 2001
From: Exodus <zjemcikolege@protonmail.com>
Date: Sat, 3 May 2025 12:41:06 +0300
Subject: [PATCH 7/7] sunxi-6.14: Add volume up/down keyboard overlay for h616,
 h618

Signed-off-by: The-going <48602507+The-going@users.noreply.github.com>
---
 .../patches.armbian/h616-add-keys.patch       | 101 ++++++++++++++++++
 .../kernel/archive/sunxi-6.14/series.armbian  |   1 +
 patch/kernel/archive/sunxi-6.14/series.conf   |   1 +
 3 files changed, 103 insertions(+)
 create mode 100644 patch/kernel/archive/sunxi-6.14/patches.armbian/h616-add-keys.patch

diff --git a/patch/kernel/archive/sunxi-6.14/patches.armbian/h616-add-keys.patch b/patch/kernel/archive/sunxi-6.14/patches.armbian/h616-add-keys.patch
new file mode 100644
index 000000000000..7667b8e5a18e
--- /dev/null
+++ b/patch/kernel/archive/sunxi-6.14/patches.armbian/h616-add-keys.patch
@@ -0,0 +1,101 @@
+From b0d0e0e7cbe9d70a50a8a9cfdcfdffb028d6cef7 Mon Sep 17 00:00:00 2001
+From: Exodus <zjemcikolege@protonmail.com>
+Date: Wed, 30 Apr 2025 23:55:25 +0200
+Subject: [PATCH 1/6] h616: add keys
+
+KEY1 and KEY2 VOL +/-
+---
+ .../arm64/boot/dts/allwinner/overlay/Makefile |  1 +
+ .../allwinner/overlay/sun50i-h616-keys.dtso   | 28 +++++++++++++++++++
+ .../arm64/boot/dts/allwinner/sun50i-h616.dtsi |  1 +
+ drivers/input/keyboard/sun4i-lradc-keys.c     |  8 ++++++
+ 4 files changed, 38 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-keys.dtso
+
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/Makefile b/arch/arm64/boot/dts/allwinner/overlay/Makefile
+index 3b0e2393552d..f637933c003f 100644
+--- a/arch/arm64/boot/dts/allwinner/overlay/Makefile
++++ b/arch/arm64/boot/dts/allwinner/overlay/Makefile
+@@ -71,6 +71,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += \
+ 	sun50i-h616-i2c3-ph.dtbo \
+ 	sun50i-h616-i2c4-pg.dtbo \
+ 	sun50i-h616-i2c4-ph.dtbo \
++	sun50i-h616-keys.dtbo \
+ 	sun50i-h616-pwm1-ph3.dtbo \
+ 	sun50i-h616-pwm1-pi11.dtbo \
+ 	sun50i-h616-pwm4-ph1.dtbo \
+diff --git a/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-keys.dtso b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-keys.dtso
+new file mode 100644
+index 000000000000..e8a5665d77ce
+--- /dev/null
++++ b/arch/arm64/boot/dts/allwinner/overlay/sun50i-h616-keys.dtso
+@@ -0,0 +1,28 @@
++/dts-v1/;
++/plugin/;
++
++/ {
++	compatible = "xunlong,orangepi-zero2w", "allwinner,sun50i-h616", "allwinner,sun50i-h618";
++
++	fragment@0 {
++		target = <&lradc>;
++		__overlay__ {
++			vref-supply = <&reg_aldo1>;
++			status = "okay";
++
++			button-500 {
++				label = "KEY_VOLUMEUP";
++				linux,code = <115>;    // KEY_VOLUMEUP
++				channel = <0>;
++				voltage = <500000>;
++			};
++
++			button-800 {
++				label = "KEY_VOLUMEDOWN";
++				linux,code = <114>; // KEY_VOLUMEDOWN
++				channel = <0>;
++				voltage = <800000>;
++			};
++		};
++	};
++};
+diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+index 0f4587be1c0e..7ccc45ff3446 100644
+--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
++++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+@@ -13,6 +13,7 @@
+ #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
+ #include <dt-bindings/reset/sun8i-de2.h>
+ #include <dt-bindings/thermal/thermal.h>
++#include <dt-bindings/input/input.h>
+ 
+ / {
+ 	interrupt-parent = <&gic>;
+diff --git a/drivers/input/keyboard/sun4i-lradc-keys.c b/drivers/input/keyboard/sun4i-lradc-keys.c
+index 5730f08f82d7..0ee681630f9c 100644
+--- a/drivers/input/keyboard/sun4i-lradc-keys.c
++++ b/drivers/input/keyboard/sun4i-lradc-keys.c
+@@ -86,6 +86,12 @@ static const struct lradc_variant lradc_variant_r329 = {
+ 	.has_clock_reset = true,
+ };
+ 
++static const struct lradc_variant lradc_variant_h616 = {
++	.divisor_numerator = 3,
++	.divisor_denominator = 4,
++	.has_clock_reset = true,
++};
++
+ struct sun4i_lradc_keymap {
+ 	u32 voltage;
+ 	u32 keycode;
+@@ -341,6 +347,8 @@ static const struct of_device_id sun4i_lradc_of_match[] = {
+ 		.data = &r_lradc_variant_a83t },
+ 	{ .compatible = "allwinner,sun50i-r329-lradc",
+ 		.data = &lradc_variant_r329 },
++	{ .compatible = "allwinner,sun50i-h616-lradc",
++		.data = &lradc_variant_h616 },
+ 	{ /* sentinel */ }
+ };
+ MODULE_DEVICE_TABLE(of, sun4i_lradc_of_match);
+-- 
+2.35.3
+
diff --git a/patch/kernel/archive/sunxi-6.14/series.armbian b/patch/kernel/archive/sunxi-6.14/series.armbian
index cec3991ad8e4..e6855667a510 100644
--- a/patch/kernel/archive/sunxi-6.14/series.armbian
+++ b/patch/kernel/archive/sunxi-6.14/series.armbian
@@ -180,3 +180,4 @@
 	patches.armbian/arm-dts-sun8i-h2-plus-orangepi-zero-fix-usb_otg-dr_mode.patch
 	patches.armbian/BigTreeTech-CB1-dts-i2c-gpio-mode-adjustment-and-ws2812-rgb_val.patch
 	patches.armbian/arm64-allwinner-Add-sun50i-h618-bananapi-m4-berry-support.patch
+	patches.armbian/h616-add-keys.patch
diff --git a/patch/kernel/archive/sunxi-6.14/series.conf b/patch/kernel/archive/sunxi-6.14/series.conf
index 48216cde788a..25d29f18fa5f 100644
--- a/patch/kernel/archive/sunxi-6.14/series.conf
+++ b/patch/kernel/archive/sunxi-6.14/series.conf
@@ -483,3 +483,4 @@
 	patches.armbian/arm-dts-sun8i-h2-plus-orangepi-zero-fix-usb_otg-dr_mode.patch
 	patches.armbian/BigTreeTech-CB1-dts-i2c-gpio-mode-adjustment-and-ws2812-rgb_val.patch
 	patches.armbian/arm64-allwinner-Add-sun50i-h618-bananapi-m4-berry-support.patch
+	patches.armbian/h616-add-keys.patch