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aryan-programmer/axi_gen_and_sum_primes_fpga

A Vitis & Vivado project (for the Basys3 board (Atrix-7 FPGA)) that generates primes and sums them up over an AXI memory interface.

embedded

fpga

hls

xilinx

vivado

• TeX
·
• 3
·
• Updated
  on Nov 21, 2023

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