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# toolchain.lock -- the single source of truth for ONE exact AIE toolchain.
# Sourced by scripts/toolchain_up.sh. Change this file = change the toolchain (deliberately).
# Phase 2: mlir-aie built from a CLEAN atassis/mlir-aie fork integration-branch commit (no dirty working tree),
# with the route_b kernels overlaid by sync_kernels.sh (policy B). The base 8373e49 + our 14-patch stack are
# the commits ON this branch; bump it by rebasing the branch onto upstream + re-pinning here.
MLIR_AIE_FORK_COMMIT=7e00b57955e108fe9d8e9419f5828a0c7e650858 # Xilinx/mlir-aie upstream/main tip 2026-08-17, pure upstream, ZERO carries. 17 commits past the prev pin d91f899ea9d2 (2026-08-11); prev pin is a clean ANCESTOR of this tip, so nothing was rebased and nothing dropped -- the integration branch stays zero-carry. WHY NOW: (1) #3538 adds BD ITERATION to `aie.dma_bd` -- the hardware BD-chain on-chip loop becomes expressible from the dialect AND from IRON (new python/iron/dataflow/tile_dma.py; AIEAttrs/AIEOps/AIETargetModel + AIERT.cpp + AIETargetXAIEV2.cpp emitters; npu-xrt/bd_iteration device test; +1019/-6). That is the MOVEMENT brick the decode-dispatch work (lever3-dispatch-coalesce, block-loop-decode) needs, and it did not exist at the prev pin. (2) OUR #3540 (aiecc: stop stripping GEP nuw when downgrading for Peano) merged in this window -- the prev pin shipped WITHOUT our own fix. (3) correctness: #3549/#3550 (do not vectorize scalar arith inside runtime_sequence), #3547 (lower aievec.neg to LLVM for AIE2 and AIE2p), #3545 (hrx: retain the executable per kernel handle, fixing a run_chain use-after-free). CODEGEN-AFFECTING CROSSINGS (why the device gate was mandatory, no byte-identical skip): #3298 makes ObjectFIFO FULLY DYNAMIC -- it deletes the custom unrolling logic and adds a new unrolling pass, 167 files / +3323/-3562, rewriting the lowering all 48 of our objectFIFO generators sit on; #3377 moves lock-ID allocation OUT of the ObjectFIFO pass (111 files); #3530 bumps the aie-rt pin to 8849e208 (release/main_aig) -- the same runtime component whose PT_LOAD p_memsz gap (#3532) motivated the prev pin; #3551 changes the place-tiles centroid rule (a non-core peer's known column now decides it, so placement can move); #3555 tightens the AIEX set_lock verifier to require a runtime_sequence ANCESTOR rather than a parent. MLIR CORE UNCHANGED: utils/clone-llvm.sh is BYTE-IDENTICAL across the window, so MLIR_DISTRO_WHEEL stays at 24.0.0.2026080106+56bcc187 -- no re-provision, no 1GB download; NANOBIND unchanged. NO BREAKING API FOR US -- checked statically against all 177 route_b_kernels generators before pinning: every `aie.*` symbol they import resolves at this tip (Worker, Runtime, Program, ObjectFifo, Kernel, range_, TensorTiler2D, TaskGroup, TensorAccessSequence/Pattern, str_to_dtype, DefaultNPURuntime, create_npu_kernel, CoreEvent, add_runtime_args, Buffer, WireBundle, ParameterScratchpad, ExternalFunction, CompileTime, XRTTensor, WorkerRuntimeBarrier, ObjectFifoHandle, PortEvent, MemTilePortEvent, NPU1/NPU2/NPU1Col1/NPU2Col1, AnyComputeTile, Tile, from_name). The #3298 rework does NOT reach the Python surface: the WHOLE window's python/ diff is +125/-29 and additive (tile_dma.py, config.py AIECC_PATH override, hrxruntime), and python/iron/dataflow/objectfifo.py is untouched -- #3298 is C++ passes plus FileCheck tests. PRE-EXISTING DEFECT surfaced by that audit, NOT a regression from this bump: 4 whole_array_fused generators import NPU1Col2, which does not exist at the PREV pin either (upstream defines only NPU1Col1). PEANO NOT BUMPED with this: both carries were re-verified OPEN via `gh pr view` at pin time (#1148 adjustSPReg, #1155 VST_dmx_sts_x_spill), so there is no carry-drop trigger, and b892afe21 is ALREADY an ancestor of the pinned 0c8fe2df -- the delay-slot payoff the /repin doc still cites was resolved at the 2026-07-20 re-pin. Prev pin d91f899ea9d2 (upstream tip 08-11, 0 carries). Prev-prev 62be3ea3133. PRIOR PIN HISTORY: Xilinx/mlir-aie upstream/main tip 2026-08-11, pure upstream, ZERO carries. 38 commits past the prev pin 62be3ea3133. WHY NOW: (1) #3532 zeroes the p_memsz-p_filesz gap in aie-rt's PT_LOAD loader -- the ordinary mixed .data+.bss segment was DMA'ing trailing ELF bytes (.comment/.symtab) into tile data memory where zero-init statics live; it was ABSENT from the prev pin (not an ancestor of 62be3ea; it lived only on branch fix/aie-rt-elfloader-bss-gap), so every build on that pin carried the corruption. (2) #3528 + #3533 teach aiecc to downgrade LLVM 24 narrow-float decimal literals and keep the merged module's alignment for Peano -- that is the failure that took out the fused-decode attention kernels via their exp2 LUT. MLIR CORE MOVED IN THIS WINDOW: #3491 bumped utils/clone-llvm.sh 46fcb339/23.0.0 -> 56bcc187/24.0.0, so MLIR_DISTRO_WHEEL moves with it (wheel was already provisioned in the cache -- no 1GB download). NO BREAKING API FOR US -- checked statically against all 176 route_b_kernels generator files before pinning: every `aie.*` symbol they import resolves at this tip (DefaultNPURuntime; XRTTensor, ctor still `(shape_or_data, dtype=...)` with `group_id` added as a KEYWORD; ParameterScratchpad; add_runtime_args; create_npu_kernel; CoreEvent -- note trace/events is now a PACKAGE re-exporting `CoreEvent = CoreEventAIE2`, not a removed module; WorkerRuntimeBarrier; from_name; ExternalFunction; TensorAccessPattern; NpuTensor.from_torch). #3512 IS a breaking IR change (pad_value moves off `aie.dma_bd` onto the channel ops `aie.dma_start`/`aie.dma`; geometry stays per-BD) but no generator of ours emits pad_value, so it does not reach us. OUR merged work landing in this pin (11 of the 38): #3494 (find the Python interpreter regardless of AIE_ENABLE_BINDINGS_PYTHON), #3495 (test_lib tile-address bugs), #3496 (core stack-size default onto AIETargetModel), #3497 (aiecc fails on a missing backend dir), #3499 (ci: lock the device, not the whole test), #3461 (column control overlay for intermediate columns), #3501 (aiecc defaults the core backend to Peano), #3505 (block_datatypes matmuls with Peano), #3500 (ATB artifact suite nightly), #3507 (do not abort on an unplaced tile in the DMA passes), #3462 (aie2p mm_activation_epilogue). CODEGEN-AFFECTING CROSSINGS (why the device gate was mandatory, no byte-identical skip): #3491 MLIR core 23->24, #3489 + #3503 AIEVec operand signedness through vector.contract lowering, #3512 dma_bd dialect change, #3472 + #3514 packet-flow router fixes, #3496 stack-size default, #3461 column control overlay. Prev pin 62be3ea3133 (upstream tip 08-01, 0 carries). Prev-prev 94537df8ecc2. NO BREAKING API IN THIS WINDOW -- checked statically against all 82 route_b_kernels generators before pinning: every `aie.*` module they import is present and signature-compatible at this tip. The two that looked risky are not: #3399 (inline external kernels into the core) is purely ADDITIVE -- `ExternalFunction(inline=False)` / `Kernel(link_with_mode=None)` are the defaults and reproduce the old object-link behaviour exactly, so all 76 `Kernel(` + 4 `ExternalFunction(` call sites are untouched; #3430 (hostruntime NpuTensor/Storage, +2469 lines) reworks internals only -- `XRTTensor.__init__` is byte-identical, `ParameterScratchpad` and `add_runtime_args` are unchanged, and `from_torch` is still inherited from tensor_class.py. OUR merged work landing in this pin (11 of the 23): #3490 (block_datatypes ATB chess reason), #3487 (stop re-testing merged commits on the NPU runners), #3464 (coremem_events from a single traced tile), #3457 (JIT cache: validate a recorded dependency manifest), #3465 (cmake: validate PEANO_INSTALL_DIR), #3458 (AIEX bulk-reset loop doc + re-arm pointer), #3474 (ccache via COMPILER_LAUNCHER), #3456 (AIEX reset registers via the register database), #3440 (aiecc legal start-column set for virtualized partitions), #3451 (state each test's backend, move off Chess where not needed), #3455 (getTargetModel rejects an unknown AIEDevice), #3430. UPSTREAM codegen-affecting: #3399 (aiecc gains an llvm-link merge path for inline kernels), #3451 (Chess->Peano test moves). LLVM core UNCHANGED across the window (utils/clone-llvm.sh byte-identical) => MLIR_DISTRO_WHEEL reused, no 1GB download; NANOBIND unchanged. Prev pin 94537df8ecc2 (upstream tip 07-29, 0 carries). Prev-prev a079d8b0a87. EARLIER BOUNDARY still in force: #3387 reworked iron Runtime into an eager callback body -- `Runtime()` + `with rt.sequence(...)` is GONE, the constructor now REQUIRES `Runtime(seq_fn, fn_args)`, fill/drain moved onto the ObjectFifo handle, workers moved to `Program(..., workers=)`, `rt.task_group()`->`TaskGroup()`, `rt.finish_task_group(tg)`->`tg.finish()`, `rt.set_barrier(b,v)`->`b.set(v)`, `rt.inline_ops(fn,args)`->call fn directly (the 40 generators were migrated at the 94537df8 pin; the two spellings cannot coexist across that boundary). ALSO still in force: #3364 unified aiecc's output-selection flags under --get-<name>, removing --aie-generate-xclbin / --aie-generate-npu-insts / --aie-generate-input-with-addresses -- do not reintroduce the old spelling.
MLIR_DISTRO_WHEEL=mlir-24.0.0.2026080106+56bcc187 # FORCED by the mlir-aie bump above, not a taste choice: #3491 moved utils/clone-llvm.sh to LLVM_PROJECT_COMMIT=56bcc1871734e6c375a254dec0ec74eb18d04a2e and the major version 23 -> 24, so the 068c6c5c core no longer matches the tree. Already provisioned at $XDNA_CACHE/mlir-distro/24.0.0.2026080106+56bcc187 (mlir/bin/mlir-tblgen present) -- no 1GB download. Prev pin mlir-23.0.0.2026060107+068c6c5c. Rollback: restore that value + toolchain_up.sh (the 23.0.0 cache dir is retained).
PEANO_DIST=llvm_aie-21.0.0.2026062301+cb664e8c # SUPERSEDED as the active Peano by PEANO_FORK_COMMIT below (2026-07-20 re-pin). Retained as the upstream-nightly REFERENCE only (the cp310 wheel is excluded from the py3.14 install anyway -- see setup_route_b.sh; the active Peano is the local build symlinked into .venv-iron). Prior note: bumped 2026052701 -> afc887f; decode WER 0.0842 == old-Peano baseline (17-clip A/B).
PEANO_FORK_COMMIT=0c8fe2df9d36aaa1ba4666f5f3721397701aa8a8 # ACTIVE Peano = local build of atassis/llvm-aie `integ-2026-07-31` (built by scripts/build_peano_fast.sh; installed via install_peano_local.sh --from the prior install so it carries the full dist's llvm-ar/headers/runtimes -- a raw build-fast tree has NO llvm-ar and can never be activated directly). Base = Xilinx/llvm-aie upstream/aie-public 706c8d9ea6b1, UNCHANGED from the prev pin -- this is a CHERRY-PICK bump, not a base advance. CARRIES the same 2 commits: #1148 (adjustSPReg large stack frames) + #1155 (VST_dmx_sts_x_spill reg-offset; fixes the rope-lut ROT=64 backend crash), both still OPEN. ADDS the 3-commit Xilinx/llvm-aie#1184 series (e66575e82361 / 20e646d33668 / 0c8fe2df9d36), each patch-id identical to its upstream twin 69efb0d1bbea / 1b1ff85251bb / c9c5ecb725fc, with AIELegalizerHelper.cpp byte-identical to aie-public. WHY: `aie_kernels/aie2p/mm_bfp.cc` fails on the prev pin with `unable to legalize instruction: %55:_(<8 x s8>) = G_BUILD_VECTOR` in matmul_vectorized_bfp16 (= issue #995) and compiles clean here, emitting that function as a global text symbol -- verified on BOTH arms, so the fix is load-bearing rather than assumed. This unblocks block-datatypes-peano-flip. Delta vs the prev pin is 4 source files / ~110 lines, all build-vector legalization, plus 4 test files; aie-public's own tip is 5413 commits and 46 AIE-backend files further on and crossing it was unnecessary. DEVICE-GATED 2026-08-01: clean two-arm A/B with all 4 encoder xclbin dirs emptied and rebuilt from scratch under EACH pin, then 17-clip encode + encoder_parity.py -- output BIT-IDENTICAL between arms (sha 016fff923d1a), PASS on all five statistics (mean 0.0836, worst-frame 0.7057, worst-burst 0.3568, new-burst 0.0000, cliff 0). The first A/B run FAILED and that was a methodology defect, not the pin: the baseline arm reused xclbins already in the persistent build tree, so the gate scored build drift as a regression -- see method-device-gate-both-arms-fresh, and note the MEAN passed in that false-positive case, which is why the gate is four statistics and not one. STILL DROPPED: #1058 (merged upstream), #1054 (superseded by b892afe21), #1060 (build-breaking against aie-public's own qwh0 register; diagnostic-only). Prev pin dfadd0855266 (integ-2026-07-29). Rollback: scripts/install_peano_local.sh --activate .cache/peano-local/integ-2026-07-29 (retained) + git checkout toolchain.lock + toolchain_up.sh.
NANOBIND=2.12.0 # the dep that silently broke us at 2.13.0