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ianrreesianrrees
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fix: Update clock v2 docstring rate types
1 parent 391f1c1 commit 233094c

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3 files changed

+34
-34
lines changed

3 files changed

+34
-34
lines changed

‎hal/src/peripherals/clock/d5x/v2/dfll.rs

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -66,7 +66,7 @@
6666
//! clock::v2::{clock_system_at_reset, dfll::Dfll, xosc::Xosc},
6767
//! gpio::Pins,
6868
//! pac::Peripherals,
69-
//! time::U32Ext,
69+
//! fugit::RateExtU32,
7070
//! };
7171
//! let mut pac = Peripherals::take().unwrap();
7272
//! let pins = Pins::new(pac.port);
@@ -87,7 +87,7 @@
8787
//! # clock::v2::{clock_system_at_reset, dfll::Dfll, xosc::Xosc},
8888
//! # gpio::Pins,
8989
//! # pac::Peripherals,
90-
//! # time::U32Ext,
90+
//! # fugit::RateExtU32,
9191
//! # };
9292
//! # let mut pac = Peripherals::take().unwrap();
9393
//! # let pins = Pins::new(pac.port);
@@ -98,7 +98,7 @@
9898
//! # pac.mclk,
9999
//! # &mut pac.nvmctrl,
100100
//! # );
101-
//! let xosc0 = Xosc::from_clock(tokens.xosc0, pins.pa14, 24.mhz()).enable();
101+
//! let xosc0 = Xosc::from_clock(tokens.xosc0, pins.pa14, 24.MHz()).enable();
102102
//! ```
103103
//!
104104
//! We can then swap [`Gclk0`] from the [`EnabledDfll`] to the [`EnabledXosc`].
@@ -110,7 +110,7 @@
110110
//! # clock::v2::{clock_system_at_reset, dfll::Dfll, xosc::Xosc},
111111
//! # gpio::Pins,
112112
//! # pac::Peripherals,
113-
//! # time::U32Ext,
113+
//! # fugit::RateExtU32,
114114
//! # };
115115
//! # let mut pac = Peripherals::take().unwrap();
116116
//! # let pins = Pins::new(pac.port);
@@ -121,7 +121,7 @@
121121
//! # pac.mclk,
122122
//! # &mut pac.nvmctrl,
123123
//! # );
124-
//! # let xosc0 = Xosc::from_clock(tokens.xosc0, pins.pa14, 24.mhz()).enable();
124+
//! # let xosc0 = Xosc::from_clock(tokens.xosc0, pins.pa14, 24.MHz()).enable();
125125
//! let (gclk0, dfll, xosc0) = clocks.gclk0.swap_sources(clocks.dfll, xosc0);
126126
//! let token_dfll = dfll.disable().free();
127127
//! ```
@@ -137,7 +137,7 @@
137137
//! # clock::v2::{clock_system_at_reset, dfll::Dfll, pclk::Pclk, xosc::Xosc},
138138
//! # gpio::Pins,
139139
//! # pac::Peripherals,
140-
//! # time::U32Ext,
140+
//! # fugit::RateExtU32,
141141
//! # };
142142
//! # let mut pac = Peripherals::take().unwrap();
143143
//! # let pins = Pins::new(pac.port);
@@ -148,7 +148,7 @@
148148
//! # pac.mclk,
149149
//! # &mut pac.nvmctrl,
150150
//! # );
151-
//! # let xosc0 = Xosc::from_clock(tokens.xosc0, pins.pa14, 24.mhz()).enable();
151+
//! # let xosc0 = Xosc::from_clock(tokens.xosc0, pins.pa14, 24.MHz()).enable();
152152
//! # let (gclk0, dfll, xosc0) = clocks.gclk0.swap_sources(clocks.dfll, xosc0);
153153
//! # let token_dfll = dfll.disable().free();
154154
//! let (pclk_dfll, gclk0) = Pclk::enable(tokens.pclks.dfll, gclk0);
@@ -166,7 +166,7 @@
166166
//! clock::v2::{clock_system_at_reset, dfll::Dfll, pclk::Pclk, xosc::Xosc},
167167
//! gpio::Pins,
168168
//! pac::Peripherals,
169-
//! time::U32Ext,
169+
//! fugit::RateExtU32,
170170
//! };
171171
//! let mut pac = Peripherals::take().unwrap();
172172
//! let pins = Pins::new(pac.port);
@@ -177,7 +177,7 @@
177177
//! pac.mclk,
178178
//! &mut pac.nvmctrl,
179179
//! );
180-
//! let xosc0 = Xosc::from_clock(tokens.xosc0, pins.pa14, 24.mhz()).enable();
180+
//! let xosc0 = Xosc::from_clock(tokens.xosc0, pins.pa14, 24.MHz()).enable();
181181
//! let (gclk0, dfll, xosc0) = clocks.gclk0.swap_sources(clocks.dfll, xosc0);
182182
//! let token_dfll = dfll.disable().free();
183183
//! let (pclk_dfll, gclk0) = Pclk::enable(tokens.pclks.dfll, gclk0);
@@ -231,7 +231,7 @@
231231
//! },
232232
//! gpio::Pins,
233233
//! pac::Peripherals,
234-
//! time::U32Ext,
234+
//! fugit::RateExtU32,
235235
//! };
236236
//! let mut pac = Peripherals::take().unwrap();
237237
//! let pins = Pins::new(pac.port);

‎hal/src/peripherals/clock/d5x/v2/gclk.rs

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -64,7 +64,7 @@
6464
//! },
6565
//! gpio::Pins,
6666
//! pac::Peripherals,
67-
//! time::U32Ext,
67+
//! fugit::RateExtU32,
6868
//! };
6969
//! let mut pac = Peripherals::take().unwrap();
7070
//! let (mut buses, clocks, tokens) = clock_system_at_reset(
@@ -98,7 +98,7 @@
9898
//! # },
9999
//! # gpio::Pins,
100100
//! # pac::Peripherals,
101-
//! # time::U32Ext,
101+
//! # fugit::RateExtU32,
102102
//! # };
103103
//! # let mut pac = Peripherals::take().unwrap();
104104
//! # let (mut buses, clocks, tokens) = clock_system_at_reset(
@@ -109,7 +109,7 @@
109109
//! # &mut pac.nvmctrl,
110110
//! # );
111111
//! # let pins = Pins::new(pac.port);
112-
//! let gclk1 = Gclk::from_pin(tokens.gclks.gclk1, pins.pb15, 24.mhz());
112+
//! let gclk1 = Gclk::from_pin(tokens.gclks.gclk1, pins.pb15, 24.MHz());
113113
//! ```
114114
//!
115115
//! While we have created a [`Gclk`], we have not yet enabled it. But before
@@ -126,7 +126,7 @@
126126
//! # },
127127
//! # gpio::Pins,
128128
//! # pac::Peripherals,
129-
//! # time::U32Ext,
129+
//! # fugit::RateExtU32,
130130
//! # };
131131
//! # let mut pac = Peripherals::take().unwrap();
132132
//! # let (mut buses, clocks, tokens) = clock_system_at_reset(
@@ -137,7 +137,7 @@
137137
//! # &mut pac.nvmctrl,
138138
//! # );
139139
//! # let pins = Pins::new(pac.port);
140-
//! # let gclk1 = Gclk::from_pin(tokens.gclks.gclk1, pins.pb15, 24.mhz());
140+
//! # let gclk1 = Gclk::from_pin(tokens.gclks.gclk1, pins.pb15, 24.MHz());
141141
//! let gclk1 = gclk1.div(GclkDiv16::Div(2)).enable();
142142
//! ```
143143
//!
@@ -163,7 +163,7 @@
163163
//! # },
164164
//! # gpio::Pins,
165165
//! # pac::Peripherals,
166-
//! # time::U32Ext,
166+
//! # fugit::RateExtU32,
167167
//! # };
168168
//! # let mut pac = Peripherals::take().unwrap();
169169
//! # let (mut buses, clocks, tokens) = clock_system_at_reset(
@@ -174,7 +174,7 @@
174174
//! # &mut pac.nvmctrl,
175175
//! # );
176176
//! # let pins = Pins::new(pac.port);
177-
//! # let gclk1 = Gclk::from_pin(tokens.gclks.gclk1, pins.pb15, 24.mhz());
177+
//! # let gclk1 = Gclk::from_pin(tokens.gclks.gclk1, pins.pb15, 24.MHz());
178178
//! # let gclk1 = gclk1.div(GclkDiv16::Div(2)).enable();
179179
//! let (pclk_sercom0, gclk1) = Pclk::enable(tokens.pclks.sercom0, gclk1);
180180
//! ```
@@ -193,7 +193,7 @@
193193
//! # },
194194
//! # gpio::Pins,
195195
//! # pac::Peripherals,
196-
//! # time::U32Ext,
196+
//! # fugit::RateExtU32,
197197
//! # };
198198
//! # let mut pac = Peripherals::take().unwrap();
199199
//! # let (mut buses, clocks, tokens) = clock_system_at_reset(
@@ -204,7 +204,7 @@
204204
//! # &mut pac.nvmctrl,
205205
//! # );
206206
//! # let pins = Pins::new(pac.port);
207-
//! # let gclk1 = Gclk::from_pin(tokens.gclks.gclk1, pins.pb15, 24.mhz());
207+
//! # let gclk1 = Gclk::from_pin(tokens.gclks.gclk1, pins.pb15, 24.MHz());
208208
//! # let gclk1 = gclk1.div(GclkDiv16::Div(2)).enable();
209209
//! # let (pclk_sercom0, gclk1) = Pclk::enable(tokens.pclks.sercom0, gclk1);
210210
//! let (gclk2, gclk1) = Gclk::from_source(tokens.gclks.gclk2, gclk1);
@@ -223,7 +223,7 @@
223223
//! # },
224224
//! # gpio::Pins,
225225
//! # pac::Peripherals,
226-
//! # time::U32Ext,
226+
//! # fugit::RateExtU32,
227227
//! # };
228228
//! # let mut pac = Peripherals::take().unwrap();
229229
//! # let (mut buses, clocks, tokens) = clock_system_at_reset(
@@ -234,7 +234,7 @@
234234
//! # &mut pac.nvmctrl,
235235
//! # );
236236
//! # let pins = Pins::new(pac.port);
237-
//! # let gclk1 = Gclk::from_pin(tokens.gclks.gclk1, pins.pb15, 24.mhz());
237+
//! # let gclk1 = Gclk::from_pin(tokens.gclks.gclk1, pins.pb15, 24.MHz());
238238
//! # let gclk1 = gclk1.div(GclkDiv16::Div(2)).enable();
239239
//! # let (pclk_sercom0, gclk1) = Pclk::enable(tokens.pclks.sercom0, gclk1);
240240
//! # let (gclk2, gclk1) = Gclk::from_source(tokens.gclks.gclk2, gclk1);
@@ -254,7 +254,7 @@
254254
//! # },
255255
//! # gpio::Pins,
256256
//! # pac::Peripherals,
257-
//! # time::U32Ext,
257+
//! # fugit::RateExtU32,
258258
//! # };
259259
//! # let mut pac = Peripherals::take().unwrap();
260260
//! # let (mut buses, clocks, tokens) = clock_system_at_reset(
@@ -265,7 +265,7 @@
265265
//! # &mut pac.nvmctrl,
266266
//! # );
267267
//! # let pins = Pins::new(pac.port);
268-
//! # let gclk1 = Gclk::from_pin(tokens.gclks.gclk1, pins.pb15, 24.mhz());
268+
//! # let gclk1 = Gclk::from_pin(tokens.gclks.gclk1, pins.pb15, 24.MHz());
269269
//! # let gclk1 = gclk1.div(GclkDiv16::Div(2)).enable();
270270
//! # let (pclk_sercom0, gclk1) = Pclk::enable(tokens.pclks.sercom0, gclk1);
271271
//! # let (gclk2, gclk1) = Gclk::from_source(tokens.gclks.gclk2, gclk1);
@@ -285,7 +285,7 @@
285285
//! },
286286
//! gpio::Pins,
287287
//! pac::Peripherals,
288-
//! time::U32Ext,
288+
//! fugit::RateExtU32,
289289
//! };
290290
//! let mut pac = Peripherals::take().unwrap();
291291
//! let (mut buses, clocks, tokens) = clock_system_at_reset(
@@ -296,7 +296,7 @@
296296
//! &mut pac.nvmctrl,
297297
//! );
298298
//! let pins = Pins::new(pac.port);
299-
//! let gclk1 = Gclk::from_pin(tokens.gclks.gclk1, pins.pb15, 24.mhz());
299+
//! let gclk1 = Gclk::from_pin(tokens.gclks.gclk1, pins.pb15, 24.MHz());
300300
//! let gclk1 = gclk1.div(GclkDiv16::Div(2)).enable();
301301
//! let (pclk_sercom0, gclk1) = Pclk::enable(tokens.pclks.sercom0, gclk1);
302302
//! let (gclk2, gclk1) = Gclk::from_source(tokens.gclks.gclk2, gclk1);

‎hal/src/peripherals/clock/d5x/v2/xosc.rs

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -39,7 +39,7 @@
3939
//! },
4040
//! gpio::Pins,
4141
//! pac::Peripherals,
42-
//! time::U32Ext,
42+
//! fugit::RateExtU32,
4343
//! };
4444
//! let mut pac = Peripherals::take().unwrap();
4545
//! let pins = Pins::new(pac.port);
@@ -65,7 +65,7 @@
6565
//! # },
6666
//! # gpio::Pins,
6767
//! # pac::Peripherals,
68-
//! # time::U32Ext,
68+
//! # fugit::RateExtU32,
6969
//! # };
7070
//! # let mut pac = Peripherals::take().unwrap();
7171
//! # let pins = Pins::new(pac.port);
@@ -76,7 +76,7 @@
7676
//! # pac.mclk,
7777
//! # &mut pac.nvmctrl,
7878
//! # );
79-
//! let mut xosc = Xosc::from_crystal(tokens.xosc0, pins.pa14, pins.pa15, 20.mhz())
79+
//! let mut xosc = Xosc::from_crystal(tokens.xosc0, pins.pa14, pins.pa15, 20.MHz())
8080
//! .current(CrystalCurrent::Medium)
8181
//! .loop_control(true)
8282
//! .low_buf_gain(true)
@@ -106,7 +106,7 @@
106106
//! # },
107107
//! # gpio::Pins,
108108
//! # pac::Peripherals,
109-
//! # time::U32Ext,
109+
//! # fugit::RateExtU32,
110110
//! # };
111111
//! # let mut pac = Peripherals::take().unwrap();
112112
//! # let pins = Pins::new(pac.port);
@@ -117,7 +117,7 @@
117117
//! # pac.mclk,
118118
//! # &mut pac.nvmctrl,
119119
//! # );
120-
//! # let mut xosc = Xosc::from_crystal(tokens.xosc0, pins.pa14, pins.pa15, 20.mhz())
120+
//! # let mut xosc = Xosc::from_crystal(tokens.xosc0, pins.pa14, pins.pa15, 20.MHz())
121121
//! # .current(CrystalCurrent::Medium)
122122
//! # .loop_control(true)
123123
//! # .low_buf_gain(true)
@@ -140,7 +140,7 @@
140140
//! # },
141141
//! # gpio::Pins,
142142
//! # pac::Peripherals,
143-
//! # time::U32Ext,
143+
//! # fugit::RateExtU32,
144144
//! # };
145145
//! # let mut pac = Peripherals::take().unwrap();
146146
//! # let pins = Pins::new(pac.port);
@@ -151,7 +151,7 @@
151151
//! # pac.mclk,
152152
//! # &mut pac.nvmctrl,
153153
//! # );
154-
//! # let mut xosc = Xosc::from_crystal(tokens.xosc0, pins.pa14, pins.pa15, 20.mhz())
154+
//! # let mut xosc = Xosc::from_crystal(tokens.xosc0, pins.pa14, pins.pa15, 20.MHz())
155155
//! # .current(CrystalCurrent::Medium)
156156
//! # .loop_control(true)
157157
//! # .low_buf_gain(true)
@@ -176,7 +176,7 @@
176176
//! },
177177
//! gpio::Pins,
178178
//! pac::Peripherals,
179-
//! time::U32Ext,
179+
//! fugit::RateExtU32,
180180
//! };
181181
//! let mut pac = Peripherals::take().unwrap();
182182
//! let pins = Pins::new(pac.port);
@@ -187,7 +187,7 @@
187187
//! pac.mclk,
188188
//! &mut pac.nvmctrl,
189189
//! );
190-
//! let mut xosc = Xosc::from_crystal(tokens.xosc0, pins.pa14, pins.pa15, 20.mhz())
190+
//! let mut xosc = Xosc::from_crystal(tokens.xosc0, pins.pa14, pins.pa15, 20.MHz())
191191
//! .current(CrystalCurrent::Medium)
192192
//! .loop_control(true)
193193
//! .low_buf_gain(true)

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