diff --git a/pac/atsaml22j/Cargo.toml b/pac/atsaml22j/Cargo.toml new file mode 100644 index 000000000000..17947abce6cf --- /dev/null +++ b/pac/atsaml22j/Cargo.toml @@ -0,0 +1,13 @@ +[package] +name = "atsaml22j" +description = "Peripheral access API for ATSAML22J microcontrollers (generated using svd2rust)" +version = "0.1.0" +edition = "2021" +authors = ["Wesley Ellis "] +keywords = ["no-std", "arm", "cortex-m"] +categories = ["embedded", "hardware-support", "no-std"] +license = "MIT OR Apache-2.0" + +# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html + +[dependencies] diff --git a/pac/atsaml22j/README.md b/pac/atsaml22j/README.md new file mode 100644 index 000000000000..2446dd549e61 --- /dev/null +++ b/pac/atsaml22j/README.md @@ -0,0 +1,3 @@ +A periphreal access crate for the ATSAMDL22J chip from Microship for Rust Embedded Projects. + +TODO diff --git a/pac/atsaml22j/build.rs b/pac/atsaml22j/build.rs new file mode 100644 index 000000000000..597923f50892 --- /dev/null +++ b/pac/atsaml22j/build.rs @@ -0,0 +1,16 @@ +use std::env; +use std::fs::File; +use std::io::Write; +use std::path::PathBuf; +fn main() { + if env::var_os("CARGO_FEATURE_RT").is_some() { + let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap()); + File::create(out.join("device.x")) + .unwrap() + .write_all(include_bytes!("device.x")) + .unwrap(); + println!("cargo:rustc-link-search={}", out.display()); + println!("cargo:rerun-if-changed=device.x"); + } + println!("cargo:rerun-if-changed=build.rs"); +} diff --git a/pac/atsaml22j/device.x b/pac/atsaml22j/device.x new file mode 100644 index 000000000000..5154caa94b77 --- /dev/null +++ b/pac/atsaml22j/device.x @@ -0,0 +1,24 @@ +PROVIDE(SYSTEM = DefaultHandler); +PROVIDE(WDT = DefaultHandler); +PROVIDE(RTC = DefaultHandler); +PROVIDE(EIC = DefaultHandler); +PROVIDE(FREQM = DefaultHandler); +PROVIDE(USB = DefaultHandler); +PROVIDE(NVMCTRL = DefaultHandler); +PROVIDE(DMAC = DefaultHandler); +PROVIDE(EVSYS = DefaultHandler); +PROVIDE(SERCOM0 = DefaultHandler); +PROVIDE(SERCOM1 = DefaultHandler); +PROVIDE(SERCOM2 = DefaultHandler); +PROVIDE(SERCOM3 = DefaultHandler); +PROVIDE(TCC0 = DefaultHandler); +PROVIDE(TC0 = DefaultHandler); +PROVIDE(TC1 = DefaultHandler); +PROVIDE(TC2 = DefaultHandler); +PROVIDE(TC3 = DefaultHandler); +PROVIDE(ADC = DefaultHandler); +PROVIDE(AC = DefaultHandler); +PROVIDE(SLCD = DefaultHandler); +PROVIDE(AES = DefaultHandler); +PROVIDE(TRNG = DefaultHandler); + diff --git a/pac/atsaml22j/src/ac.rs b/pac/atsaml22j/src/ac.rs new file mode 100644 index 000000000000..0abb9da3fbee --- /dev/null +++ b/pac/atsaml22j/src/ac.rs @@ -0,0 +1,85 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: CTRLA, + #[doc = "0x01 - Control B"] + pub ctrlb: CTRLB, + #[doc = "0x02 - Event Control"] + pub evctrl: EVCTRL, + #[doc = "0x04 - Interrupt Enable Clear"] + pub intenclr: INTENCLR, + #[doc = "0x05 - Interrupt Enable Set"] + pub intenset: INTENSET, + #[doc = "0x06 - Interrupt Flag Status and Clear"] + pub intflag: INTFLAG, + #[doc = "0x07 - Status A"] + pub statusa: STATUSA, + #[doc = "0x08 - Status B"] + pub statusb: STATUSB, + #[doc = "0x09 - Debug Control"] + pub dbgctrl: DBGCTRL, + #[doc = "0x0a - Window Control"] + pub winctrl: WINCTRL, + _reserved10: [u8; 0x01], + #[doc = "0x0c - Scaler n"] + pub scaler: [SCALER; 2], + _reserved11: [u8; 0x02], + #[doc = "0x10..0x18 - Comparator Control n"] + pub compctrl: [COMPCTRL; 2], + _reserved12: [u8; 0x08], + #[doc = "0x20 - Synchronization Busy"] + pub syncbusy: SYNCBUSY, +} +#[doc = "CTRLA (rw) register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLB (w) register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B"] +pub mod ctrlb; +#[doc = "EVCTRL (rw) register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR (rw) register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET (rw) register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG (rw) register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUSA (r) register accessor: an alias for `Reg`"] +pub type STATUSA = crate::Reg; +#[doc = "Status A"] +pub mod statusa; +#[doc = "STATUSB (r) register accessor: an alias for `Reg`"] +pub type STATUSB = crate::Reg; +#[doc = "Status B"] +pub mod statusb; +#[doc = "DBGCTRL (rw) register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "WINCTRL (rw) register accessor: an alias for `Reg`"] +pub type WINCTRL = crate::Reg; +#[doc = "Window Control"] +pub mod winctrl; +#[doc = "SCALER (rw) register accessor: an alias for `Reg`"] +pub type SCALER = crate::Reg; +#[doc = "Scaler n"] +pub mod scaler; +#[doc = "COMPCTRL (rw) register accessor: an alias for `Reg`"] +pub type COMPCTRL = crate::Reg; +#[doc = "Comparator Control n"] +pub mod compctrl; +#[doc = "SYNCBUSY (r) register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; diff --git a/pac/atsaml22j/src/ac/compctrl.rs b/pac/atsaml22j/src/ac/compctrl.rs new file mode 100644 index 000000000000..6278ec37e135 --- /dev/null +++ b/pac/atsaml22j/src/ac/compctrl.rs @@ -0,0 +1,808 @@ +#[doc = "Register `COMPCTRL%s` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COMPCTRL%s` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - Enable"] +pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, COMPCTRL_SPEC, bool, O>; +#[doc = "Field `SINGLE` reader - Single-Shot Mode"] +pub type SINGLE_R = crate::BitReader; +#[doc = "Field `SINGLE` writer - Single-Shot Mode"] +pub type SINGLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, COMPCTRL_SPEC, bool, O>; +#[doc = "Field `INTSEL` reader - Interrupt Selection"] +pub type INTSEL_R = crate::FieldReader; +#[doc = "Interrupt Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum INTSELSELECT_A { + #[doc = "0: Interrupt on comparator output toggle"] + TOGGLE = 0, + #[doc = "1: Interrupt on comparator output rising"] + RISING = 1, + #[doc = "2: Interrupt on comparator output falling"] + FALLING = 2, + #[doc = "3: Interrupt on end of comparison (single-shot mode only)"] + EOC = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: INTSELSELECT_A) -> Self { + variant as _ + } +} +impl INTSEL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> INTSELSELECT_A { + match self.bits { + 0 => INTSELSELECT_A::TOGGLE, + 1 => INTSELSELECT_A::RISING, + 2 => INTSELSELECT_A::FALLING, + 3 => INTSELSELECT_A::EOC, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `TOGGLE`"] + #[inline(always)] + pub fn is_toggle(&self) -> bool { + *self == INTSELSELECT_A::TOGGLE + } + #[doc = "Checks if the value of the field is `RISING`"] + #[inline(always)] + pub fn is_rising(&self) -> bool { + *self == INTSELSELECT_A::RISING + } + #[doc = "Checks if the value of the field is `FALLING`"] + #[inline(always)] + pub fn is_falling(&self) -> bool { + *self == INTSELSELECT_A::FALLING + } + #[doc = "Checks if the value of the field is `EOC`"] + #[inline(always)] + pub fn is_eoc(&self) -> bool { + *self == INTSELSELECT_A::EOC + } +} +#[doc = "Field `INTSEL` writer - Interrupt Selection"] +pub type INTSEL_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, COMPCTRL_SPEC, u8, INTSELSELECT_A, 2, O>; +impl<'a, const O: u8> INTSEL_W<'a, O> { + #[doc = "Interrupt on comparator output toggle"] + #[inline(always)] + pub fn toggle(self) -> &'a mut W { + self.variant(INTSELSELECT_A::TOGGLE) + } + #[doc = "Interrupt on comparator output rising"] + #[inline(always)] + pub fn rising(self) -> &'a mut W { + self.variant(INTSELSELECT_A::RISING) + } + #[doc = "Interrupt on comparator output falling"] + #[inline(always)] + pub fn falling(self) -> &'a mut W { + self.variant(INTSELSELECT_A::FALLING) + } + #[doc = "Interrupt on end of comparison (single-shot mode only)"] + #[inline(always)] + pub fn eoc(self) -> &'a mut W { + self.variant(INTSELSELECT_A::EOC) + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub type RUNSTDBY_R = crate::BitReader; +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub type RUNSTDBY_W<'a, const O: u8> = crate::BitWriter<'a, u32, COMPCTRL_SPEC, bool, O>; +#[doc = "Field `MUXNEG` reader - Negative Input Mux Selection"] +pub type MUXNEG_R = crate::FieldReader; +#[doc = "Negative Input Mux Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum MUXNEGSELECT_A { + #[doc = "0: I/O pin 0"] + PIN0 = 0, + #[doc = "1: I/O pin 1"] + PIN1 = 1, + #[doc = "2: I/O pin 2"] + PIN2 = 2, + #[doc = "3: I/O pin 3"] + PIN3 = 3, + #[doc = "4: Ground"] + GND = 4, + #[doc = "5: VDD scaler"] + VSCALE = 5, + #[doc = "6: Internal bandgap voltage"] + BANDGAP = 6, + #[doc = "7: DAC output"] + DAC = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MUXNEGSELECT_A) -> Self { + variant as _ + } +} +impl MUXNEG_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> MUXNEGSELECT_A { + match self.bits { + 0 => MUXNEGSELECT_A::PIN0, + 1 => MUXNEGSELECT_A::PIN1, + 2 => MUXNEGSELECT_A::PIN2, + 3 => MUXNEGSELECT_A::PIN3, + 4 => MUXNEGSELECT_A::GND, + 5 => MUXNEGSELECT_A::VSCALE, + 6 => MUXNEGSELECT_A::BANDGAP, + 7 => MUXNEGSELECT_A::DAC, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PIN0`"] + #[inline(always)] + pub fn is_pin0(&self) -> bool { + *self == MUXNEGSELECT_A::PIN0 + } + #[doc = "Checks if the value of the field is `PIN1`"] + #[inline(always)] + pub fn is_pin1(&self) -> bool { + *self == MUXNEGSELECT_A::PIN1 + } + #[doc = "Checks if the value of the field is `PIN2`"] + #[inline(always)] + pub fn is_pin2(&self) -> bool { + *self == MUXNEGSELECT_A::PIN2 + } + #[doc = "Checks if the value of the field is `PIN3`"] + #[inline(always)] + pub fn is_pin3(&self) -> bool { + *self == MUXNEGSELECT_A::PIN3 + } + #[doc = "Checks if the value of the field is `GND`"] + #[inline(always)] + pub fn is_gnd(&self) -> bool { + *self == MUXNEGSELECT_A::GND + } + #[doc = "Checks if the value of the field is `VSCALE`"] + #[inline(always)] + pub fn is_vscale(&self) -> bool { + *self == MUXNEGSELECT_A::VSCALE + } + #[doc = "Checks if the value of the field is `BANDGAP`"] + #[inline(always)] + pub fn is_bandgap(&self) -> bool { + *self == MUXNEGSELECT_A::BANDGAP + } + #[doc = "Checks if the value of the field is `DAC`"] + #[inline(always)] + pub fn is_dac(&self) -> bool { + *self == MUXNEGSELECT_A::DAC + } +} +#[doc = "Field `MUXNEG` writer - Negative Input Mux Selection"] +pub type MUXNEG_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, COMPCTRL_SPEC, u8, MUXNEGSELECT_A, 3, O>; +impl<'a, const O: u8> MUXNEG_W<'a, O> { + #[doc = "I/O pin 0"] + #[inline(always)] + pub fn pin0(self) -> &'a mut W { + self.variant(MUXNEGSELECT_A::PIN0) + } + #[doc = "I/O pin 1"] + #[inline(always)] + pub fn pin1(self) -> &'a mut W { + self.variant(MUXNEGSELECT_A::PIN1) + } + #[doc = "I/O pin 2"] + #[inline(always)] + pub fn pin2(self) -> &'a mut W { + self.variant(MUXNEGSELECT_A::PIN2) + } + #[doc = "I/O pin 3"] + #[inline(always)] + pub fn pin3(self) -> &'a mut W { + self.variant(MUXNEGSELECT_A::PIN3) + } + #[doc = "Ground"] + #[inline(always)] + pub fn gnd(self) -> &'a mut W { + self.variant(MUXNEGSELECT_A::GND) + } + #[doc = "VDD scaler"] + #[inline(always)] + pub fn vscale(self) -> &'a mut W { + self.variant(MUXNEGSELECT_A::VSCALE) + } + #[doc = "Internal bandgap voltage"] + #[inline(always)] + pub fn bandgap(self) -> &'a mut W { + self.variant(MUXNEGSELECT_A::BANDGAP) + } + #[doc = "DAC output"] + #[inline(always)] + pub fn dac(self) -> &'a mut W { + self.variant(MUXNEGSELECT_A::DAC) + } +} +#[doc = "Field `MUXPOS` reader - Positive Input Mux Selection"] +pub type MUXPOS_R = crate::FieldReader; +#[doc = "Positive Input Mux Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum MUXPOSSELECT_A { + #[doc = "0: I/O pin 0"] + PIN0 = 0, + #[doc = "1: I/O pin 1"] + PIN1 = 1, + #[doc = "2: I/O pin 2"] + PIN2 = 2, + #[doc = "3: I/O pin 3"] + PIN3 = 3, + #[doc = "4: VDD Scaler"] + VSCALE = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MUXPOSSELECT_A) -> Self { + variant as _ + } +} +impl MUXPOS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MUXPOSSELECT_A::PIN0), + 1 => Some(MUXPOSSELECT_A::PIN1), + 2 => Some(MUXPOSSELECT_A::PIN2), + 3 => Some(MUXPOSSELECT_A::PIN3), + 4 => Some(MUXPOSSELECT_A::VSCALE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `PIN0`"] + #[inline(always)] + pub fn is_pin0(&self) -> bool { + *self == MUXPOSSELECT_A::PIN0 + } + #[doc = "Checks if the value of the field is `PIN1`"] + #[inline(always)] + pub fn is_pin1(&self) -> bool { + *self == MUXPOSSELECT_A::PIN1 + } + #[doc = "Checks if the value of the field is `PIN2`"] + #[inline(always)] + pub fn is_pin2(&self) -> bool { + *self == MUXPOSSELECT_A::PIN2 + } + #[doc = "Checks if the value of the field is `PIN3`"] + #[inline(always)] + pub fn is_pin3(&self) -> bool { + *self == MUXPOSSELECT_A::PIN3 + } + #[doc = "Checks if the value of the field is `VSCALE`"] + #[inline(always)] + pub fn is_vscale(&self) -> bool { + *self == MUXPOSSELECT_A::VSCALE + } +} +#[doc = "Field `MUXPOS` writer - Positive Input Mux Selection"] +pub type MUXPOS_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, COMPCTRL_SPEC, u8, MUXPOSSELECT_A, 3, O>; +impl<'a, const O: u8> MUXPOS_W<'a, O> { + #[doc = "I/O pin 0"] + #[inline(always)] + pub fn pin0(self) -> &'a mut W { + self.variant(MUXPOSSELECT_A::PIN0) + } + #[doc = "I/O pin 1"] + #[inline(always)] + pub fn pin1(self) -> &'a mut W { + self.variant(MUXPOSSELECT_A::PIN1) + } + #[doc = "I/O pin 2"] + #[inline(always)] + pub fn pin2(self) -> &'a mut W { + self.variant(MUXPOSSELECT_A::PIN2) + } + #[doc = "I/O pin 3"] + #[inline(always)] + pub fn pin3(self) -> &'a mut W { + self.variant(MUXPOSSELECT_A::PIN3) + } + #[doc = "VDD Scaler"] + #[inline(always)] + pub fn vscale(self) -> &'a mut W { + self.variant(MUXPOSSELECT_A::VSCALE) + } +} +#[doc = "Field `SWAP` reader - Swap Inputs and Invert"] +pub type SWAP_R = crate::BitReader; +#[doc = "Field `SWAP` writer - Swap Inputs and Invert"] +pub type SWAP_W<'a, const O: u8> = crate::BitWriter<'a, u32, COMPCTRL_SPEC, bool, O>; +#[doc = "Field `SPEED` reader - Speed Selection"] +pub type SPEED_R = crate::FieldReader; +#[doc = "Speed Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SPEEDSELECT_A { + #[doc = "0: Low speed"] + LOW = 0, + #[doc = "1: Medium low speed"] + MEDLOW = 1, + #[doc = "2: Medium high speed"] + MEDHIGH = 2, + #[doc = "3: High speed"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SPEEDSELECT_A) -> Self { + variant as _ + } +} +impl SPEED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SPEEDSELECT_A { + match self.bits { + 0 => SPEEDSELECT_A::LOW, + 1 => SPEEDSELECT_A::MEDLOW, + 2 => SPEEDSELECT_A::MEDHIGH, + 3 => SPEEDSELECT_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == SPEEDSELECT_A::LOW + } + #[doc = "Checks if the value of the field is `MEDLOW`"] + #[inline(always)] + pub fn is_medlow(&self) -> bool { + *self == SPEEDSELECT_A::MEDLOW + } + #[doc = "Checks if the value of the field is `MEDHIGH`"] + #[inline(always)] + pub fn is_medhigh(&self) -> bool { + *self == SPEEDSELECT_A::MEDHIGH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == SPEEDSELECT_A::HIGH + } +} +#[doc = "Field `SPEED` writer - Speed Selection"] +pub type SPEED_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, COMPCTRL_SPEC, u8, SPEEDSELECT_A, 2, O>; +impl<'a, const O: u8> SPEED_W<'a, O> { + #[doc = "Low speed"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SPEEDSELECT_A::LOW) + } + #[doc = "Medium low speed"] + #[inline(always)] + pub fn medlow(self) -> &'a mut W { + self.variant(SPEEDSELECT_A::MEDLOW) + } + #[doc = "Medium high speed"] + #[inline(always)] + pub fn medhigh(self) -> &'a mut W { + self.variant(SPEEDSELECT_A::MEDHIGH) + } + #[doc = "High speed"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SPEEDSELECT_A::HIGH) + } +} +#[doc = "Field `HYSTEN` reader - Hysteresis Enable"] +pub type HYSTEN_R = crate::BitReader; +#[doc = "Field `HYSTEN` writer - Hysteresis Enable"] +pub type HYSTEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, COMPCTRL_SPEC, bool, O>; +#[doc = "Field `HYST` reader - Hysteresis Level"] +pub type HYST_R = crate::FieldReader; +#[doc = "Hysteresis Level\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum HYSTSELECT_A { + #[doc = "0: 50mV"] + HYST50 = 0, + #[doc = "1: 70mV"] + HYST70 = 1, + #[doc = "2: 90mV"] + HYST90 = 2, + #[doc = "3: 110mV"] + HYST110 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: HYSTSELECT_A) -> Self { + variant as _ + } +} +impl HYST_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> HYSTSELECT_A { + match self.bits { + 0 => HYSTSELECT_A::HYST50, + 1 => HYSTSELECT_A::HYST70, + 2 => HYSTSELECT_A::HYST90, + 3 => HYSTSELECT_A::HYST110, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `HYST50`"] + #[inline(always)] + pub fn is_hyst50(&self) -> bool { + *self == HYSTSELECT_A::HYST50 + } + #[doc = "Checks if the value of the field is `HYST70`"] + #[inline(always)] + pub fn is_hyst70(&self) -> bool { + *self == HYSTSELECT_A::HYST70 + } + #[doc = "Checks if the value of the field is `HYST90`"] + #[inline(always)] + pub fn is_hyst90(&self) -> bool { + *self == HYSTSELECT_A::HYST90 + } + #[doc = "Checks if the value of the field is `HYST110`"] + #[inline(always)] + pub fn is_hyst110(&self) -> bool { + *self == HYSTSELECT_A::HYST110 + } +} +#[doc = "Field `HYST` writer - Hysteresis Level"] +pub type HYST_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, COMPCTRL_SPEC, u8, HYSTSELECT_A, 2, O>; +impl<'a, const O: u8> HYST_W<'a, O> { + #[doc = "50mV"] + #[inline(always)] + pub fn hyst50(self) -> &'a mut W { + self.variant(HYSTSELECT_A::HYST50) + } + #[doc = "70mV"] + #[inline(always)] + pub fn hyst70(self) -> &'a mut W { + self.variant(HYSTSELECT_A::HYST70) + } + #[doc = "90mV"] + #[inline(always)] + pub fn hyst90(self) -> &'a mut W { + self.variant(HYSTSELECT_A::HYST90) + } + #[doc = "110mV"] + #[inline(always)] + pub fn hyst110(self) -> &'a mut W { + self.variant(HYSTSELECT_A::HYST110) + } +} +#[doc = "Field `FLEN` reader - Filter Length"] +pub type FLEN_R = crate::FieldReader; +#[doc = "Filter Length\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FLENSELECT_A { + #[doc = "0: No filtering"] + OFF = 0, + #[doc = "1: 3-bit majority function (2 of 3)"] + MAJ3 = 1, + #[doc = "2: 5-bit majority function (3 of 5)"] + MAJ5 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FLENSELECT_A) -> Self { + variant as _ + } +} +impl FLEN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FLENSELECT_A::OFF), + 1 => Some(FLENSELECT_A::MAJ3), + 2 => Some(FLENSELECT_A::MAJ5), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == FLENSELECT_A::OFF + } + #[doc = "Checks if the value of the field is `MAJ3`"] + #[inline(always)] + pub fn is_maj3(&self) -> bool { + *self == FLENSELECT_A::MAJ3 + } + #[doc = "Checks if the value of the field is `MAJ5`"] + #[inline(always)] + pub fn is_maj5(&self) -> bool { + *self == FLENSELECT_A::MAJ5 + } +} +#[doc = "Field `FLEN` writer - Filter Length"] +pub type FLEN_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, COMPCTRL_SPEC, u8, FLENSELECT_A, 3, O>; +impl<'a, const O: u8> FLEN_W<'a, O> { + #[doc = "No filtering"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(FLENSELECT_A::OFF) + } + #[doc = "3-bit majority function (2 of 3)"] + #[inline(always)] + pub fn maj3(self) -> &'a mut W { + self.variant(FLENSELECT_A::MAJ3) + } + #[doc = "5-bit majority function (3 of 5)"] + #[inline(always)] + pub fn maj5(self) -> &'a mut W { + self.variant(FLENSELECT_A::MAJ5) + } +} +#[doc = "Field `OUT` reader - Output"] +pub type OUT_R = crate::FieldReader; +#[doc = "Output\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum OUTSELECT_A { + #[doc = "0: The output of COMPn is not routed to the COMPn I/O port"] + OFF = 0, + #[doc = "1: The asynchronous output of COMPn is routed to the COMPn I/O port"] + ASYNC = 1, + #[doc = "2: The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port"] + SYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: OUTSELECT_A) -> Self { + variant as _ + } +} +impl OUT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(OUTSELECT_A::OFF), + 1 => Some(OUTSELECT_A::ASYNC), + 2 => Some(OUTSELECT_A::SYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == OUTSELECT_A::OFF + } + #[doc = "Checks if the value of the field is `ASYNC`"] + #[inline(always)] + pub fn is_async(&self) -> bool { + *self == OUTSELECT_A::ASYNC + } + #[doc = "Checks if the value of the field is `SYNC`"] + #[inline(always)] + pub fn is_sync(&self) -> bool { + *self == OUTSELECT_A::SYNC + } +} +#[doc = "Field `OUT` writer - Output"] +pub type OUT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, COMPCTRL_SPEC, u8, OUTSELECT_A, 2, O>; +impl<'a, const O: u8> OUT_W<'a, O> { + #[doc = "The output of COMPn is not routed to the COMPn I/O port"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(OUTSELECT_A::OFF) + } + #[doc = "The asynchronous output of COMPn is routed to the COMPn I/O port"] + #[inline(always)] + pub fn async_(self) -> &'a mut W { + self.variant(OUTSELECT_A::ASYNC) + } + #[doc = "The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port"] + #[inline(always)] + pub fn sync(self) -> &'a mut W { + self.variant(OUTSELECT_A::SYNC) + } +} +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Single-Shot Mode"] + #[inline(always)] + pub fn single(&self) -> SINGLE_R { + SINGLE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 3:4 - Interrupt Selection"] + #[inline(always)] + pub fn intsel(&self) -> INTSEL_R { + INTSEL_R::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:10 - Negative Input Mux Selection"] + #[inline(always)] + pub fn muxneg(&self) -> MUXNEG_R { + MUXNEG_R::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bits 12:14 - Positive Input Mux Selection"] + #[inline(always)] + pub fn muxpos(&self) -> MUXPOS_R { + MUXPOS_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - Swap Inputs and Invert"] + #[inline(always)] + pub fn swap(&self) -> SWAP_R { + SWAP_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:17 - Speed Selection"] + #[inline(always)] + pub fn speed(&self) -> SPEED_R { + SPEED_R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bit 19 - Hysteresis Enable"] + #[inline(always)] + pub fn hysten(&self) -> HYSTEN_R { + HYSTEN_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bits 20:21 - Hysteresis Level"] + #[inline(always)] + pub fn hyst(&self) -> HYST_R { + HYST_R::new(((self.bits >> 20) & 3) as u8) + } + #[doc = "Bits 24:26 - Filter Length"] + #[inline(always)] + pub fn flen(&self) -> FLEN_R { + FLEN_R::new(((self.bits >> 24) & 7) as u8) + } + #[doc = "Bits 28:29 - Output"] + #[inline(always)] + pub fn out(&self) -> OUT_R { + OUT_R::new(((self.bits >> 28) & 3) as u8) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W<1> { + ENABLE_W::new(self) + } + #[doc = "Bit 2 - Single-Shot Mode"] + #[inline(always)] + #[must_use] + pub fn single(&mut self) -> SINGLE_W<2> { + SINGLE_W::new(self) + } + #[doc = "Bits 3:4 - Interrupt Selection"] + #[inline(always)] + #[must_use] + pub fn intsel(&mut self) -> INTSEL_W<3> { + INTSEL_W::new(self) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + #[must_use] + pub fn runstdby(&mut self) -> RUNSTDBY_W<6> { + RUNSTDBY_W::new(self) + } + #[doc = "Bits 8:10 - Negative Input Mux Selection"] + #[inline(always)] + #[must_use] + pub fn muxneg(&mut self) -> MUXNEG_W<8> { + MUXNEG_W::new(self) + } + #[doc = "Bits 12:14 - Positive Input Mux Selection"] + #[inline(always)] + #[must_use] + pub fn muxpos(&mut self) -> MUXPOS_W<12> { + MUXPOS_W::new(self) + } + #[doc = "Bit 15 - Swap Inputs and Invert"] + #[inline(always)] + #[must_use] + pub fn swap(&mut self) -> SWAP_W<15> { + SWAP_W::new(self) + } + #[doc = "Bits 16:17 - Speed Selection"] + #[inline(always)] + #[must_use] + pub fn speed(&mut self) -> SPEED_W<16> { + SPEED_W::new(self) + } + #[doc = "Bit 19 - Hysteresis Enable"] + #[inline(always)] + #[must_use] + pub fn hysten(&mut self) -> HYSTEN_W<19> { + HYSTEN_W::new(self) + } + #[doc = "Bits 20:21 - Hysteresis Level"] + #[inline(always)] + #[must_use] + pub fn hyst(&mut self) -> HYST_W<20> { + HYST_W::new(self) + } + #[doc = "Bits 24:26 - Filter Length"] + #[inline(always)] + #[must_use] + pub fn flen(&mut self) -> FLEN_W<24> { + FLEN_W::new(self) + } + #[doc = "Bits 28:29 - Output"] + #[inline(always)] + #[must_use] + pub fn out(&mut self) -> OUT_W<28> { + OUT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Comparator Control n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [compctrl](index.html) module"] +pub struct COMPCTRL_SPEC; +impl crate::RegisterSpec for COMPCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [compctrl::R](R) reader structure"] +impl crate::Readable for COMPCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [compctrl::W](W) writer structure"] +impl crate::Writable for COMPCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMPCTRL%s to value 0"] +impl crate::Resettable for COMPCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/ac/ctrla.rs b/pac/atsaml22j/src/ac/ctrla.rs new file mode 100644 index 000000000000..0a806f6d70aa --- /dev/null +++ b/pac/atsaml22j/src/ac/ctrla.rs @@ -0,0 +1,88 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub type SWRST_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLA_SPEC, bool, O>; +#[doc = "Field `ENABLE` reader - Enable"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - Enable"] +pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLA_SPEC, bool, O>; +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + #[must_use] + pub fn swrst(&mut self) -> SWRST_W<0> { + SWRST_W::new(self) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W<1> { + ENABLE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/ac/ctrlb.rs b/pac/atsaml22j/src/ac/ctrlb.rs new file mode 100644 index 000000000000..ebd67c63d551 --- /dev/null +++ b/pac/atsaml22j/src/ac/ctrlb.rs @@ -0,0 +1,60 @@ +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `START0` writer - Comparator 0 Start Comparison"] +pub type START0_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLB_SPEC, bool, O>; +#[doc = "Field `START1` writer - Comparator 1 Start Comparison"] +pub type START1_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLB_SPEC, bool, O>; +impl W { + #[doc = "Bit 0 - Comparator 0 Start Comparison"] + #[inline(always)] + #[must_use] + pub fn start0(&mut self) -> START0_W<0> { + START0_W::new(self) + } + #[doc = "Bit 1 - Comparator 1 Start Comparison"] + #[inline(always)] + #[must_use] + pub fn start1(&mut self) -> START1_W<1> { + START1_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/ac/dbgctrl.rs b/pac/atsaml22j/src/ac/dbgctrl.rs new file mode 100644 index 000000000000..71c6b3e56bf2 --- /dev/null +++ b/pac/atsaml22j/src/ac/dbgctrl.rs @@ -0,0 +1,80 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Run"] +pub type DBGRUN_R = crate::BitReader; +#[doc = "Field `DBGRUN` writer - Debug Run"] +pub type DBGRUN_W<'a, const O: u8> = crate::BitWriter<'a, u8, DBGCTRL_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + #[must_use] + pub fn dbgrun(&mut self) -> DBGRUN_W<0> { + DBGRUN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/ac/evctrl.rs b/pac/atsaml22j/src/ac/evctrl.rs new file mode 100644 index 000000000000..b42e11f20409 --- /dev/null +++ b/pac/atsaml22j/src/ac/evctrl.rs @@ -0,0 +1,170 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMPEO0` reader - Comparator 0 Event Output Enable"] +pub type COMPEO0_R = crate::BitReader; +#[doc = "Field `COMPEO0` writer - Comparator 0 Event Output Enable"] +pub type COMPEO0_W<'a, const O: u8> = crate::BitWriter<'a, u16, EVCTRL_SPEC, bool, O>; +#[doc = "Field `COMPEO1` reader - Comparator 1 Event Output Enable"] +pub type COMPEO1_R = crate::BitReader; +#[doc = "Field `COMPEO1` writer - Comparator 1 Event Output Enable"] +pub type COMPEO1_W<'a, const O: u8> = crate::BitWriter<'a, u16, EVCTRL_SPEC, bool, O>; +#[doc = "Field `WINEO0` reader - Window 0 Event Output Enable"] +pub type WINEO0_R = crate::BitReader; +#[doc = "Field `WINEO0` writer - Window 0 Event Output Enable"] +pub type WINEO0_W<'a, const O: u8> = crate::BitWriter<'a, u16, EVCTRL_SPEC, bool, O>; +#[doc = "Field `COMPEI0` reader - Comparator 0 Event Input Enable"] +pub type COMPEI0_R = crate::BitReader; +#[doc = "Field `COMPEI0` writer - Comparator 0 Event Input Enable"] +pub type COMPEI0_W<'a, const O: u8> = crate::BitWriter<'a, u16, EVCTRL_SPEC, bool, O>; +#[doc = "Field `COMPEI1` reader - Comparator 1 Event Input Enable"] +pub type COMPEI1_R = crate::BitReader; +#[doc = "Field `COMPEI1` writer - Comparator 1 Event Input Enable"] +pub type COMPEI1_W<'a, const O: u8> = crate::BitWriter<'a, u16, EVCTRL_SPEC, bool, O>; +#[doc = "Field `INVEI0` reader - Comparator 0 Input Event Invert Enable"] +pub type INVEI0_R = crate::BitReader; +#[doc = "Field `INVEI0` writer - Comparator 0 Input Event Invert Enable"] +pub type INVEI0_W<'a, const O: u8> = crate::BitWriter<'a, u16, EVCTRL_SPEC, bool, O>; +#[doc = "Field `INVEI1` reader - Comparator 1 Input Event Invert Enable"] +pub type INVEI1_R = crate::BitReader; +#[doc = "Field `INVEI1` writer - Comparator 1 Input Event Invert Enable"] +pub type INVEI1_W<'a, const O: u8> = crate::BitWriter<'a, u16, EVCTRL_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Comparator 0 Event Output Enable"] + #[inline(always)] + pub fn compeo0(&self) -> COMPEO0_R { + COMPEO0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Comparator 1 Event Output Enable"] + #[inline(always)] + pub fn compeo1(&self) -> COMPEO1_R { + COMPEO1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 4 - Window 0 Event Output Enable"] + #[inline(always)] + pub fn wineo0(&self) -> WINEO0_R { + WINEO0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 8 - Comparator 0 Event Input Enable"] + #[inline(always)] + pub fn compei0(&self) -> COMPEI0_R { + COMPEI0_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Comparator 1 Event Input Enable"] + #[inline(always)] + pub fn compei1(&self) -> COMPEI1_R { + COMPEI1_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 12 - Comparator 0 Input Event Invert Enable"] + #[inline(always)] + pub fn invei0(&self) -> INVEI0_R { + INVEI0_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Comparator 1 Input Event Invert Enable"] + #[inline(always)] + pub fn invei1(&self) -> INVEI1_R { + INVEI1_R::new(((self.bits >> 13) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Comparator 0 Event Output Enable"] + #[inline(always)] + #[must_use] + pub fn compeo0(&mut self) -> COMPEO0_W<0> { + COMPEO0_W::new(self) + } + #[doc = "Bit 1 - Comparator 1 Event Output Enable"] + #[inline(always)] + #[must_use] + pub fn compeo1(&mut self) -> COMPEO1_W<1> { + COMPEO1_W::new(self) + } + #[doc = "Bit 4 - Window 0 Event Output Enable"] + #[inline(always)] + #[must_use] + pub fn wineo0(&mut self) -> WINEO0_W<4> { + WINEO0_W::new(self) + } + #[doc = "Bit 8 - Comparator 0 Event Input Enable"] + #[inline(always)] + #[must_use] + pub fn compei0(&mut self) -> COMPEI0_W<8> { + COMPEI0_W::new(self) + } + #[doc = "Bit 9 - Comparator 1 Event Input Enable"] + #[inline(always)] + #[must_use] + pub fn compei1(&mut self) -> COMPEI1_W<9> { + COMPEI1_W::new(self) + } + #[doc = "Bit 12 - Comparator 0 Input Event Invert Enable"] + #[inline(always)] + #[must_use] + pub fn invei0(&mut self) -> INVEI0_W<12> { + INVEI0_W::new(self) + } + #[doc = "Bit 13 - Comparator 1 Input Event Invert Enable"] + #[inline(always)] + #[must_use] + pub fn invei1(&mut self) -> INVEI1_W<13> { + INVEI1_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/ac/intenclr.rs b/pac/atsaml22j/src/ac/intenclr.rs new file mode 100644 index 000000000000..f03fc9bf0bb8 --- /dev/null +++ b/pac/atsaml22j/src/ac/intenclr.rs @@ -0,0 +1,110 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP0` reader - Comparator 0 Interrupt Enable"] +pub type COMP0_R = crate::BitReader; +#[doc = "Field `COMP0` writer - Comparator 0 Interrupt Enable"] +pub type COMP0_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>; +#[doc = "Field `COMP1` reader - Comparator 1 Interrupt Enable"] +pub type COMP1_R = crate::BitReader; +#[doc = "Field `COMP1` writer - Comparator 1 Interrupt Enable"] +pub type COMP1_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>; +#[doc = "Field `WIN0` reader - Window 0 Interrupt Enable"] +pub type WIN0_R = crate::BitReader; +#[doc = "Field `WIN0` writer - Window 0 Interrupt Enable"] +pub type WIN0_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Comparator 0 Interrupt Enable"] + #[inline(always)] + pub fn comp0(&self) -> COMP0_R { + COMP0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Comparator 1 Interrupt Enable"] + #[inline(always)] + pub fn comp1(&self) -> COMP1_R { + COMP1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 4 - Window 0 Interrupt Enable"] + #[inline(always)] + pub fn win0(&self) -> WIN0_R { + WIN0_R::new(((self.bits >> 4) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Comparator 0 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn comp0(&mut self) -> COMP0_W<0> { + COMP0_W::new(self) + } + #[doc = "Bit 1 - Comparator 1 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn comp1(&mut self) -> COMP1_W<1> { + COMP1_W::new(self) + } + #[doc = "Bit 4 - Window 0 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn win0(&mut self) -> WIN0_W<4> { + WIN0_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/ac/intenset.rs b/pac/atsaml22j/src/ac/intenset.rs new file mode 100644 index 000000000000..8aed9c7d2c67 --- /dev/null +++ b/pac/atsaml22j/src/ac/intenset.rs @@ -0,0 +1,110 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP0` reader - Comparator 0 Interrupt Enable"] +pub type COMP0_R = crate::BitReader; +#[doc = "Field `COMP0` writer - Comparator 0 Interrupt Enable"] +pub type COMP0_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENSET_SPEC, bool, O>; +#[doc = "Field `COMP1` reader - Comparator 1 Interrupt Enable"] +pub type COMP1_R = crate::BitReader; +#[doc = "Field `COMP1` writer - Comparator 1 Interrupt Enable"] +pub type COMP1_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENSET_SPEC, bool, O>; +#[doc = "Field `WIN0` reader - Window 0 Interrupt Enable"] +pub type WIN0_R = crate::BitReader; +#[doc = "Field `WIN0` writer - Window 0 Interrupt Enable"] +pub type WIN0_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENSET_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Comparator 0 Interrupt Enable"] + #[inline(always)] + pub fn comp0(&self) -> COMP0_R { + COMP0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Comparator 1 Interrupt Enable"] + #[inline(always)] + pub fn comp1(&self) -> COMP1_R { + COMP1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 4 - Window 0 Interrupt Enable"] + #[inline(always)] + pub fn win0(&self) -> WIN0_R { + WIN0_R::new(((self.bits >> 4) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Comparator 0 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn comp0(&mut self) -> COMP0_W<0> { + COMP0_W::new(self) + } + #[doc = "Bit 1 - Comparator 1 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn comp1(&mut self) -> COMP1_W<1> { + COMP1_W::new(self) + } + #[doc = "Bit 4 - Window 0 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn win0(&mut self) -> WIN0_W<4> { + WIN0_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/ac/intflag.rs b/pac/atsaml22j/src/ac/intflag.rs new file mode 100644 index 000000000000..f86cb26fa32d --- /dev/null +++ b/pac/atsaml22j/src/ac/intflag.rs @@ -0,0 +1,110 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP0` reader - Comparator 0"] +pub type COMP0_R = crate::BitReader; +#[doc = "Field `COMP0` writer - Comparator 0"] +pub type COMP0_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTFLAG_SPEC, bool, O>; +#[doc = "Field `COMP1` reader - Comparator 1"] +pub type COMP1_R = crate::BitReader; +#[doc = "Field `COMP1` writer - Comparator 1"] +pub type COMP1_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTFLAG_SPEC, bool, O>; +#[doc = "Field `WIN0` reader - Window 0"] +pub type WIN0_R = crate::BitReader; +#[doc = "Field `WIN0` writer - Window 0"] +pub type WIN0_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTFLAG_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Comparator 0"] + #[inline(always)] + pub fn comp0(&self) -> COMP0_R { + COMP0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Comparator 1"] + #[inline(always)] + pub fn comp1(&self) -> COMP1_R { + COMP1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 4 - Window 0"] + #[inline(always)] + pub fn win0(&self) -> WIN0_R { + WIN0_R::new(((self.bits >> 4) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Comparator 0"] + #[inline(always)] + #[must_use] + pub fn comp0(&mut self) -> COMP0_W<0> { + COMP0_W::new(self) + } + #[doc = "Bit 1 - Comparator 1"] + #[inline(always)] + #[must_use] + pub fn comp1(&mut self) -> COMP1_W<1> { + COMP1_W::new(self) + } + #[doc = "Bit 4 - Window 0"] + #[inline(always)] + #[must_use] + pub fn win0(&mut self) -> WIN0_W<4> { + WIN0_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/ac/scaler.rs b/pac/atsaml22j/src/ac/scaler.rs new file mode 100644 index 000000000000..e62e91e434b9 --- /dev/null +++ b/pac/atsaml22j/src/ac/scaler.rs @@ -0,0 +1,80 @@ +#[doc = "Register `SCALER%s` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SCALER%s` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VALUE` reader - Scaler Value"] +pub type VALUE_R = crate::FieldReader; +#[doc = "Field `VALUE` writer - Scaler Value"] +pub type VALUE_W<'a, const O: u8> = crate::FieldWriter<'a, u8, SCALER_SPEC, u8, u8, 6, O>; +impl R { + #[doc = "Bits 0:5 - Scaler Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new(self.bits & 0x3f) + } +} +impl W { + #[doc = "Bits 0:5 - Scaler Value"] + #[inline(always)] + #[must_use] + pub fn value(&mut self) -> VALUE_W<0> { + VALUE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Scaler n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [scaler](index.html) module"] +pub struct SCALER_SPEC; +impl crate::RegisterSpec for SCALER_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [scaler::R](R) reader structure"] +impl crate::Readable for SCALER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [scaler::W](W) writer structure"] +impl crate::Writable for SCALER_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SCALER%s to value 0"] +impl crate::Resettable for SCALER_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/ac/statusa.rs b/pac/atsaml22j/src/ac/statusa.rs new file mode 100644 index 000000000000..bfaf734437cc --- /dev/null +++ b/pac/atsaml22j/src/ac/statusa.rs @@ -0,0 +1,95 @@ +#[doc = "Register `STATUSA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `STATE0` reader - Comparator 0 Current State"] +pub type STATE0_R = crate::BitReader; +#[doc = "Field `STATE1` reader - Comparator 1 Current State"] +pub type STATE1_R = crate::BitReader; +#[doc = "Field `WSTATE0` reader - Window 0 Current State"] +pub type WSTATE0_R = crate::FieldReader; +#[doc = "Window 0 Current State\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum WSTATE0SELECT_A { + #[doc = "0: Signal is above window"] + ABOVE = 0, + #[doc = "1: Signal is inside window"] + INSIDE = 1, + #[doc = "2: Signal is below window"] + BELOW = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WSTATE0SELECT_A) -> Self { + variant as _ + } +} +impl WSTATE0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WSTATE0SELECT_A::ABOVE), + 1 => Some(WSTATE0SELECT_A::INSIDE), + 2 => Some(WSTATE0SELECT_A::BELOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `ABOVE`"] + #[inline(always)] + pub fn is_above(&self) -> bool { + *self == WSTATE0SELECT_A::ABOVE + } + #[doc = "Checks if the value of the field is `INSIDE`"] + #[inline(always)] + pub fn is_inside(&self) -> bool { + *self == WSTATE0SELECT_A::INSIDE + } + #[doc = "Checks if the value of the field is `BELOW`"] + #[inline(always)] + pub fn is_below(&self) -> bool { + *self == WSTATE0SELECT_A::BELOW + } +} +impl R { + #[doc = "Bit 0 - Comparator 0 Current State"] + #[inline(always)] + pub fn state0(&self) -> STATE0_R { + STATE0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Comparator 1 Current State"] + #[inline(always)] + pub fn state1(&self) -> STATE1_R { + STATE1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 4:5 - Window 0 Current State"] + #[inline(always)] + pub fn wstate0(&self) -> WSTATE0_R { + WSTATE0_R::new((self.bits >> 4) & 3) + } +} +#[doc = "Status A\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusa](index.html) module"] +pub struct STATUSA_SPEC; +impl crate::RegisterSpec for STATUSA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [statusa::R](R) reader structure"] +impl crate::Readable for STATUSA_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSA to value 0"] +impl crate::Resettable for STATUSA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/ac/statusb.rs b/pac/atsaml22j/src/ac/statusb.rs new file mode 100644 index 000000000000..3406addb4dd4 --- /dev/null +++ b/pac/atsaml22j/src/ac/statusb.rs @@ -0,0 +1,44 @@ +#[doc = "Register `STATUSB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `READY0` reader - Comparator 0 Ready"] +pub type READY0_R = crate::BitReader; +#[doc = "Field `READY1` reader - Comparator 1 Ready"] +pub type READY1_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Comparator 0 Ready"] + #[inline(always)] + pub fn ready0(&self) -> READY0_R { + READY0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Comparator 1 Ready"] + #[inline(always)] + pub fn ready1(&self) -> READY1_R { + READY1_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[doc = "Status B\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusb](index.html) module"] +pub struct STATUSB_SPEC; +impl crate::RegisterSpec for STATUSB_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [statusb::R](R) reader structure"] +impl crate::Readable for STATUSB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSB to value 0"] +impl crate::Resettable for STATUSB_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/ac/syncbusy.rs b/pac/atsaml22j/src/ac/syncbusy.rs new file mode 100644 index 000000000000..f2f0bc54d82b --- /dev/null +++ b/pac/atsaml22j/src/ac/syncbusy.rs @@ -0,0 +1,65 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub type SWRST_R = crate::BitReader; +#[doc = "Field `ENABLE` reader - Enable Synchronization Busy"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `WINCTRL` reader - WINCTRL Synchronization Busy"] +pub type WINCTRL_R = crate::BitReader; +#[doc = "Field `COMPCTRL0` reader - COMPCTRL 0 Synchronization Busy"] +pub type COMPCTRL0_R = crate::BitReader; +#[doc = "Field `COMPCTRL1` reader - COMPCTRL 1 Synchronization Busy"] +pub type COMPCTRL1_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - WINCTRL Synchronization Busy"] + #[inline(always)] + pub fn winctrl(&self) -> WINCTRL_R { + WINCTRL_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - COMPCTRL 0 Synchronization Busy"] + #[inline(always)] + pub fn compctrl0(&self) -> COMPCTRL0_R { + COMPCTRL0_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - COMPCTRL 1 Synchronization Busy"] + #[inline(always)] + pub fn compctrl1(&self) -> COMPCTRL1_R { + COMPCTRL1_R::new(((self.bits >> 4) & 1) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/ac/winctrl.rs b/pac/atsaml22j/src/ac/winctrl.rs new file mode 100644 index 000000000000..0b029efd1d8e --- /dev/null +++ b/pac/atsaml22j/src/ac/winctrl.rs @@ -0,0 +1,170 @@ +#[doc = "Register `WINCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WEN0` reader - Window 0 Mode Enable"] +pub type WEN0_R = crate::BitReader; +#[doc = "Field `WEN0` writer - Window 0 Mode Enable"] +pub type WEN0_W<'a, const O: u8> = crate::BitWriter<'a, u8, WINCTRL_SPEC, bool, O>; +#[doc = "Field `WINTSEL0` reader - Window 0 Interrupt Selection"] +pub type WINTSEL0_R = crate::FieldReader; +#[doc = "Window 0 Interrupt Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum WINTSEL0SELECT_A { + #[doc = "0: Interrupt on signal above window"] + ABOVE = 0, + #[doc = "1: Interrupt on signal inside window"] + INSIDE = 1, + #[doc = "2: Interrupt on signal below window"] + BELOW = 2, + #[doc = "3: Interrupt on signal outside window"] + OUTSIDE = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WINTSEL0SELECT_A) -> Self { + variant as _ + } +} +impl WINTSEL0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WINTSEL0SELECT_A { + match self.bits { + 0 => WINTSEL0SELECT_A::ABOVE, + 1 => WINTSEL0SELECT_A::INSIDE, + 2 => WINTSEL0SELECT_A::BELOW, + 3 => WINTSEL0SELECT_A::OUTSIDE, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `ABOVE`"] + #[inline(always)] + pub fn is_above(&self) -> bool { + *self == WINTSEL0SELECT_A::ABOVE + } + #[doc = "Checks if the value of the field is `INSIDE`"] + #[inline(always)] + pub fn is_inside(&self) -> bool { + *self == WINTSEL0SELECT_A::INSIDE + } + #[doc = "Checks if the value of the field is `BELOW`"] + #[inline(always)] + pub fn is_below(&self) -> bool { + *self == WINTSEL0SELECT_A::BELOW + } + #[doc = "Checks if the value of the field is `OUTSIDE`"] + #[inline(always)] + pub fn is_outside(&self) -> bool { + *self == WINTSEL0SELECT_A::OUTSIDE + } +} +#[doc = "Field `WINTSEL0` writer - Window 0 Interrupt Selection"] +pub type WINTSEL0_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u8, WINCTRL_SPEC, u8, WINTSEL0SELECT_A, 2, O>; +impl<'a, const O: u8> WINTSEL0_W<'a, O> { + #[doc = "Interrupt on signal above window"] + #[inline(always)] + pub fn above(self) -> &'a mut W { + self.variant(WINTSEL0SELECT_A::ABOVE) + } + #[doc = "Interrupt on signal inside window"] + #[inline(always)] + pub fn inside(self) -> &'a mut W { + self.variant(WINTSEL0SELECT_A::INSIDE) + } + #[doc = "Interrupt on signal below window"] + #[inline(always)] + pub fn below(self) -> &'a mut W { + self.variant(WINTSEL0SELECT_A::BELOW) + } + #[doc = "Interrupt on signal outside window"] + #[inline(always)] + pub fn outside(self) -> &'a mut W { + self.variant(WINTSEL0SELECT_A::OUTSIDE) + } +} +impl R { + #[doc = "Bit 0 - Window 0 Mode Enable"] + #[inline(always)] + pub fn wen0(&self) -> WEN0_R { + WEN0_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:2 - Window 0 Interrupt Selection"] + #[inline(always)] + pub fn wintsel0(&self) -> WINTSEL0_R { + WINTSEL0_R::new((self.bits >> 1) & 3) + } +} +impl W { + #[doc = "Bit 0 - Window 0 Mode Enable"] + #[inline(always)] + #[must_use] + pub fn wen0(&mut self) -> WEN0_W<0> { + WEN0_W::new(self) + } + #[doc = "Bits 1:2 - Window 0 Interrupt Selection"] + #[inline(always)] + #[must_use] + pub fn wintsel0(&mut self) -> WINTSEL0_W<1> { + WINTSEL0_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winctrl](index.html) module"] +pub struct WINCTRL_SPEC; +impl crate::RegisterSpec for WINCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [winctrl::R](R) reader structure"] +impl crate::Readable for WINCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winctrl::W](W) writer structure"] +impl crate::Writable for WINCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets WINCTRL to value 0"] +impl crate::Resettable for WINCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/adc.rs b/pac/atsaml22j/src/adc.rs new file mode 100644 index 000000000000..8310ecaef1fb --- /dev/null +++ b/pac/atsaml22j/src/adc.rs @@ -0,0 +1,141 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: CTRLA, + #[doc = "0x01 - Control B"] + pub ctrlb: CTRLB, + #[doc = "0x02 - Reference Control"] + pub refctrl: REFCTRL, + #[doc = "0x03 - Event Control"] + pub evctrl: EVCTRL, + #[doc = "0x04 - Interrupt Enable Clear"] + pub intenclr: INTENCLR, + #[doc = "0x05 - Interrupt Enable Set"] + pub intenset: INTENSET, + #[doc = "0x06 - Interrupt Flag Status and Clear"] + pub intflag: INTFLAG, + #[doc = "0x07 - Sequence Status"] + pub seqstatus: SEQSTATUS, + #[doc = "0x08 - Input Control"] + pub inputctrl: INPUTCTRL, + #[doc = "0x0a - Control C"] + pub ctrlc: CTRLC, + #[doc = "0x0c - Average Control"] + pub avgctrl: AVGCTRL, + #[doc = "0x0d - Sample Time Control"] + pub sampctrl: SAMPCTRL, + #[doc = "0x0e - Window Monitor Lower Threshold"] + pub winlt: WINLT, + #[doc = "0x10 - Window Monitor Upper Threshold"] + pub winut: WINUT, + #[doc = "0x12 - Gain Correction"] + pub gaincorr: GAINCORR, + #[doc = "0x14 - Offset Correction"] + pub offsetcorr: OFFSETCORR, + _reserved16: [u8; 0x02], + #[doc = "0x18 - Software Trigger"] + pub swtrig: SWTRIG, + _reserved17: [u8; 0x03], + #[doc = "0x1c - Debug Control"] + pub dbgctrl: DBGCTRL, + _reserved18: [u8; 0x03], + #[doc = "0x20 - Synchronization Busy"] + pub syncbusy: SYNCBUSY, + _reserved19: [u8; 0x02], + #[doc = "0x24 - Result"] + pub result: RESULT, + _reserved20: [u8; 0x02], + #[doc = "0x28 - Sequence Control"] + pub seqctrl: SEQCTRL, + #[doc = "0x2c - Calibration"] + pub calib: CALIB, +} +#[doc = "CTRLA (rw) register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLB (rw) register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B"] +pub mod ctrlb; +#[doc = "REFCTRL (rw) register accessor: an alias for `Reg`"] +pub type REFCTRL = crate::Reg; +#[doc = "Reference Control"] +pub mod refctrl; +#[doc = "EVCTRL (rw) register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR (rw) register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET (rw) register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG (rw) register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "SEQSTATUS (r) register accessor: an alias for `Reg`"] +pub type SEQSTATUS = crate::Reg; +#[doc = "Sequence Status"] +pub mod seqstatus; +#[doc = "INPUTCTRL (rw) register accessor: an alias for `Reg`"] +pub type INPUTCTRL = crate::Reg; +#[doc = "Input Control"] +pub mod inputctrl; +#[doc = "CTRLC (rw) register accessor: an alias for `Reg`"] +pub type CTRLC = crate::Reg; +#[doc = "Control C"] +pub mod ctrlc; +#[doc = "AVGCTRL (rw) register accessor: an alias for `Reg`"] +pub type AVGCTRL = crate::Reg; +#[doc = "Average Control"] +pub mod avgctrl; +#[doc = "SAMPCTRL (rw) register accessor: an alias for `Reg`"] +pub type SAMPCTRL = crate::Reg; +#[doc = "Sample Time Control"] +pub mod sampctrl; +#[doc = "WINLT (rw) register accessor: an alias for `Reg`"] +pub type WINLT = crate::Reg; +#[doc = "Window Monitor Lower Threshold"] +pub mod winlt; +#[doc = "WINUT (rw) register accessor: an alias for `Reg`"] +pub type WINUT = crate::Reg; +#[doc = "Window Monitor Upper Threshold"] +pub mod winut; +#[doc = "GAINCORR (rw) register accessor: an alias for `Reg`"] +pub type GAINCORR = crate::Reg; +#[doc = "Gain Correction"] +pub mod gaincorr; +#[doc = "OFFSETCORR (rw) register accessor: an alias for `Reg`"] +pub type OFFSETCORR = crate::Reg; +#[doc = "Offset Correction"] +pub mod offsetcorr; +#[doc = "SWTRIG (rw) register accessor: an alias for `Reg`"] +pub type SWTRIG = crate::Reg; +#[doc = "Software Trigger"] +pub mod swtrig; +#[doc = "DBGCTRL (rw) register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY (r) register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; +#[doc = "RESULT (r) register accessor: an alias for `Reg`"] +pub type RESULT = crate::Reg; +#[doc = "Result"] +pub mod result; +#[doc = "SEQCTRL (rw) register accessor: an alias for `Reg`"] +pub type SEQCTRL = crate::Reg; +#[doc = "Sequence Control"] +pub mod seqctrl; +#[doc = "CALIB (rw) register accessor: an alias for `Reg`"] +pub type CALIB = crate::Reg; +#[doc = "Calibration"] +pub mod calib; diff --git a/pac/atsaml22j/src/adc/avgctrl.rs b/pac/atsaml22j/src/adc/avgctrl.rs new file mode 100644 index 000000000000..dce733acc502 --- /dev/null +++ b/pac/atsaml22j/src/adc/avgctrl.rs @@ -0,0 +1,261 @@ +#[doc = "Register `AVGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `AVGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SAMPLENUM` reader - Number of Samples to be Collected"] +pub type SAMPLENUM_R = crate::FieldReader; +#[doc = "Number of Samples to be Collected\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SAMPLENUMSELECT_A { + #[doc = "0: 1 sample"] + _1 = 0, + #[doc = "1: 2 samples"] + _2 = 1, + #[doc = "2: 4 samples"] + _4 = 2, + #[doc = "3: 8 samples"] + _8 = 3, + #[doc = "4: 16 samples"] + _16 = 4, + #[doc = "5: 32 samples"] + _32 = 5, + #[doc = "6: 64 samples"] + _64 = 6, + #[doc = "7: 128 samples"] + _128 = 7, + #[doc = "8: 256 samples"] + _256 = 8, + #[doc = "9: 512 samples"] + _512 = 9, + #[doc = "10: 1024 samples"] + _1024 = 10, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SAMPLENUMSELECT_A) -> Self { + variant as _ + } +} +impl SAMPLENUM_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SAMPLENUMSELECT_A::_1), + 1 => Some(SAMPLENUMSELECT_A::_2), + 2 => Some(SAMPLENUMSELECT_A::_4), + 3 => Some(SAMPLENUMSELECT_A::_8), + 4 => Some(SAMPLENUMSELECT_A::_16), + 5 => Some(SAMPLENUMSELECT_A::_32), + 6 => Some(SAMPLENUMSELECT_A::_64), + 7 => Some(SAMPLENUMSELECT_A::_128), + 8 => Some(SAMPLENUMSELECT_A::_256), + 9 => Some(SAMPLENUMSELECT_A::_512), + 10 => Some(SAMPLENUMSELECT_A::_1024), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_1`"] + #[inline(always)] + pub fn is_1(&self) -> bool { + *self == SAMPLENUMSELECT_A::_1 + } + #[doc = "Checks if the value of the field is `_2`"] + #[inline(always)] + pub fn is_2(&self) -> bool { + *self == SAMPLENUMSELECT_A::_2 + } + #[doc = "Checks if the value of the field is `_4`"] + #[inline(always)] + pub fn is_4(&self) -> bool { + *self == SAMPLENUMSELECT_A::_4 + } + #[doc = "Checks if the value of the field is `_8`"] + #[inline(always)] + pub fn is_8(&self) -> bool { + *self == SAMPLENUMSELECT_A::_8 + } + #[doc = "Checks if the value of the field is `_16`"] + #[inline(always)] + pub fn is_16(&self) -> bool { + *self == SAMPLENUMSELECT_A::_16 + } + #[doc = "Checks if the value of the field is `_32`"] + #[inline(always)] + pub fn is_32(&self) -> bool { + *self == SAMPLENUMSELECT_A::_32 + } + #[doc = "Checks if the value of the field is `_64`"] + #[inline(always)] + pub fn is_64(&self) -> bool { + *self == SAMPLENUMSELECT_A::_64 + } + #[doc = "Checks if the value of the field is `_128`"] + #[inline(always)] + pub fn is_128(&self) -> bool { + *self == SAMPLENUMSELECT_A::_128 + } + #[doc = "Checks if the value of the field is `_256`"] + #[inline(always)] + pub fn is_256(&self) -> bool { + *self == SAMPLENUMSELECT_A::_256 + } + #[doc = "Checks if the value of the field is `_512`"] + #[inline(always)] + pub fn is_512(&self) -> bool { + *self == SAMPLENUMSELECT_A::_512 + } + #[doc = "Checks if the value of the field is `_1024`"] + #[inline(always)] + pub fn is_1024(&self) -> bool { + *self == SAMPLENUMSELECT_A::_1024 + } +} +#[doc = "Field `SAMPLENUM` writer - Number of Samples to be Collected"] +pub type SAMPLENUM_W<'a, const O: u8> = + crate::FieldWriter<'a, u8, AVGCTRL_SPEC, u8, SAMPLENUMSELECT_A, 4, O>; +impl<'a, const O: u8> SAMPLENUM_W<'a, O> { + #[doc = "1 sample"] + #[inline(always)] + pub fn _1(self) -> &'a mut W { + self.variant(SAMPLENUMSELECT_A::_1) + } + #[doc = "2 samples"] + #[inline(always)] + pub fn _2(self) -> &'a mut W { + self.variant(SAMPLENUMSELECT_A::_2) + } + #[doc = "4 samples"] + #[inline(always)] + pub fn _4(self) -> &'a mut W { + self.variant(SAMPLENUMSELECT_A::_4) + } + #[doc = "8 samples"] + #[inline(always)] + pub fn _8(self) -> &'a mut W { + self.variant(SAMPLENUMSELECT_A::_8) + } + #[doc = "16 samples"] + #[inline(always)] + pub fn _16(self) -> &'a mut W { + self.variant(SAMPLENUMSELECT_A::_16) + } + #[doc = "32 samples"] + #[inline(always)] + pub fn _32(self) -> &'a mut W { + self.variant(SAMPLENUMSELECT_A::_32) + } + #[doc = "64 samples"] + #[inline(always)] + pub fn _64(self) -> &'a mut W { + self.variant(SAMPLENUMSELECT_A::_64) + } + #[doc = "128 samples"] + #[inline(always)] + pub fn _128(self) -> &'a mut W { + self.variant(SAMPLENUMSELECT_A::_128) + } + #[doc = "256 samples"] + #[inline(always)] + pub fn _256(self) -> &'a mut W { + self.variant(SAMPLENUMSELECT_A::_256) + } + #[doc = "512 samples"] + #[inline(always)] + pub fn _512(self) -> &'a mut W { + self.variant(SAMPLENUMSELECT_A::_512) + } + #[doc = "1024 samples"] + #[inline(always)] + pub fn _1024(self) -> &'a mut W { + self.variant(SAMPLENUMSELECT_A::_1024) + } +} +#[doc = "Field `ADJRES` reader - Adjusting Result / Division Coefficient"] +pub type ADJRES_R = crate::FieldReader; +#[doc = "Field `ADJRES` writer - Adjusting Result / Division Coefficient"] +pub type ADJRES_W<'a, const O: u8> = crate::FieldWriter<'a, u8, AVGCTRL_SPEC, u8, u8, 3, O>; +impl R { + #[doc = "Bits 0:3 - Number of Samples to be Collected"] + #[inline(always)] + pub fn samplenum(&self) -> SAMPLENUM_R { + SAMPLENUM_R::new(self.bits & 0x0f) + } + #[doc = "Bits 4:6 - Adjusting Result / Division Coefficient"] + #[inline(always)] + pub fn adjres(&self) -> ADJRES_R { + ADJRES_R::new((self.bits >> 4) & 7) + } +} +impl W { + #[doc = "Bits 0:3 - Number of Samples to be Collected"] + #[inline(always)] + #[must_use] + pub fn samplenum(&mut self) -> SAMPLENUM_W<0> { + SAMPLENUM_W::new(self) + } + #[doc = "Bits 4:6 - Adjusting Result / Division Coefficient"] + #[inline(always)] + #[must_use] + pub fn adjres(&mut self) -> ADJRES_W<4> { + ADJRES_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Average Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [avgctrl](index.html) module"] +pub struct AVGCTRL_SPEC; +impl crate::RegisterSpec for AVGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [avgctrl::R](R) reader structure"] +impl crate::Readable for AVGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [avgctrl::W](W) writer structure"] +impl crate::Writable for AVGCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AVGCTRL to value 0"] +impl crate::Resettable for AVGCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/adc/calib.rs b/pac/atsaml22j/src/adc/calib.rs new file mode 100644 index 000000000000..0249b7f18209 --- /dev/null +++ b/pac/atsaml22j/src/adc/calib.rs @@ -0,0 +1,95 @@ +#[doc = "Register `CALIB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CALIB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BIASCOMP` reader - Bias Comparator Scaling"] +pub type BIASCOMP_R = crate::FieldReader; +#[doc = "Field `BIASCOMP` writer - Bias Comparator Scaling"] +pub type BIASCOMP_W<'a, const O: u8> = crate::FieldWriter<'a, u16, CALIB_SPEC, u8, u8, 3, O>; +#[doc = "Field `BIASREFBUF` reader - Bias Reference Buffer Scaling"] +pub type BIASREFBUF_R = crate::FieldReader; +#[doc = "Field `BIASREFBUF` writer - Bias Reference Buffer Scaling"] +pub type BIASREFBUF_W<'a, const O: u8> = crate::FieldWriter<'a, u16, CALIB_SPEC, u8, u8, 3, O>; +impl R { + #[doc = "Bits 0:2 - Bias Comparator Scaling"] + #[inline(always)] + pub fn biascomp(&self) -> BIASCOMP_R { + BIASCOMP_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 8:10 - Bias Reference Buffer Scaling"] + #[inline(always)] + pub fn biasrefbuf(&self) -> BIASREFBUF_R { + BIASREFBUF_R::new(((self.bits >> 8) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Bias Comparator Scaling"] + #[inline(always)] + #[must_use] + pub fn biascomp(&mut self) -> BIASCOMP_W<0> { + BIASCOMP_W::new(self) + } + #[doc = "Bits 8:10 - Bias Reference Buffer Scaling"] + #[inline(always)] + #[must_use] + pub fn biasrefbuf(&mut self) -> BIASREFBUF_W<8> { + BIASREFBUF_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Calibration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [calib](index.html) module"] +pub struct CALIB_SPEC; +impl crate::RegisterSpec for CALIB_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [calib::R](R) reader structure"] +impl crate::Readable for CALIB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [calib::W](W) writer structure"] +impl crate::Writable for CALIB_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CALIB to value 0"] +impl crate::Resettable for CALIB_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/adc/ctrla.rs b/pac/atsaml22j/src/adc/ctrla.rs new file mode 100644 index 000000000000..8b9d8d7b3c9b --- /dev/null +++ b/pac/atsaml22j/src/adc/ctrla.rs @@ -0,0 +1,125 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub type SWRST_R = crate::BitReader; +#[doc = "Field `SWRST` writer - Software Reset"] +pub type SWRST_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLA_SPEC, bool, O>; +#[doc = "Field `ENABLE` reader - Enable"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - Enable"] +pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLA_SPEC, bool, O>; +#[doc = "Field `RUNSTDBY` reader - Run During Standby"] +pub type RUNSTDBY_R = crate::BitReader; +#[doc = "Field `RUNSTDBY` writer - Run During Standby"] +pub type RUNSTDBY_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLA_SPEC, bool, O>; +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub type ONDEMAND_R = crate::BitReader; +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub type ONDEMAND_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLA_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 6 - Run During Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + #[must_use] + pub fn swrst(&mut self) -> SWRST_W<0> { + SWRST_W::new(self) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W<1> { + ENABLE_W::new(self) + } + #[doc = "Bit 6 - Run During Standby"] + #[inline(always)] + #[must_use] + pub fn runstdby(&mut self) -> RUNSTDBY_W<6> { + RUNSTDBY_W::new(self) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + #[must_use] + pub fn ondemand(&mut self) -> ONDEMAND_W<7> { + ONDEMAND_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/adc/ctrlb.rs b/pac/atsaml22j/src/adc/ctrlb.rs new file mode 100644 index 000000000000..1dd87ae3a7fe --- /dev/null +++ b/pac/atsaml22j/src/adc/ctrlb.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PRESCALER` reader - Prescaler Configuration"] +pub type PRESCALER_R = crate::FieldReader; +#[doc = "Prescaler Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum PRESCALERSELECT_A { + #[doc = "0: Peripheral clock divided by 2"] + DIV2 = 0, + #[doc = "1: Peripheral clock divided by 4"] + DIV4 = 1, + #[doc = "2: Peripheral clock divided by 8"] + DIV8 = 2, + #[doc = "3: Peripheral clock divided by 16"] + DIV16 = 3, + #[doc = "4: Peripheral clock divided by 32"] + DIV32 = 4, + #[doc = "5: Peripheral clock divided by 64"] + DIV64 = 5, + #[doc = "6: Peripheral clock divided by 128"] + DIV128 = 6, + #[doc = "7: Peripheral clock divided by 256"] + DIV256 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALERSELECT_A) -> Self { + variant as _ + } +} +impl PRESCALER_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALERSELECT_A { + match self.bits { + 0 => PRESCALERSELECT_A::DIV2, + 1 => PRESCALERSELECT_A::DIV4, + 2 => PRESCALERSELECT_A::DIV8, + 3 => PRESCALERSELECT_A::DIV16, + 4 => PRESCALERSELECT_A::DIV32, + 5 => PRESCALERSELECT_A::DIV64, + 6 => PRESCALERSELECT_A::DIV128, + 7 => PRESCALERSELECT_A::DIV256, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + *self == PRESCALERSELECT_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + *self == PRESCALERSELECT_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + *self == PRESCALERSELECT_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + *self == PRESCALERSELECT_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + *self == PRESCALERSELECT_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + *self == PRESCALERSELECT_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + *self == PRESCALERSELECT_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + *self == PRESCALERSELECT_A::DIV256 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler Configuration"] +pub type PRESCALER_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u8, CTRLB_SPEC, u8, PRESCALERSELECT_A, 3, O>; +impl<'a, const O: u8> PRESCALER_W<'a, O> { + #[doc = "Peripheral clock divided by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV2) + } + #[doc = "Peripheral clock divided by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV4) + } + #[doc = "Peripheral clock divided by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV8) + } + #[doc = "Peripheral clock divided by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV16) + } + #[doc = "Peripheral clock divided by 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV32) + } + #[doc = "Peripheral clock divided by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV64) + } + #[doc = "Peripheral clock divided by 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV128) + } + #[doc = "Peripheral clock divided by 256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV256) + } +} +impl R { + #[doc = "Bits 0:2 - Prescaler Configuration"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(self.bits & 7) + } +} +impl W { + #[doc = "Bits 0:2 - Prescaler Configuration"] + #[inline(always)] + #[must_use] + pub fn prescaler(&mut self) -> PRESCALER_W<0> { + PRESCALER_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/adc/ctrlc.rs b/pac/atsaml22j/src/adc/ctrlc.rs new file mode 100644 index 000000000000..a024b0bb5b4c --- /dev/null +++ b/pac/atsaml22j/src/adc/ctrlc.rs @@ -0,0 +1,397 @@ +#[doc = "Register `CTRLC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIFFMODE` reader - Differential Mode"] +pub type DIFFMODE_R = crate::BitReader; +#[doc = "Field `DIFFMODE` writer - Differential Mode"] +pub type DIFFMODE_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRLC_SPEC, bool, O>; +#[doc = "Field `LEFTADJ` reader - Left-Adjusted Result"] +pub type LEFTADJ_R = crate::BitReader; +#[doc = "Field `LEFTADJ` writer - Left-Adjusted Result"] +pub type LEFTADJ_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRLC_SPEC, bool, O>; +#[doc = "Field `FREERUN` reader - Free Running Mode"] +pub type FREERUN_R = crate::BitReader; +#[doc = "Field `FREERUN` writer - Free Running Mode"] +pub type FREERUN_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRLC_SPEC, bool, O>; +#[doc = "Field `CORREN` reader - Digital Correction Logic Enable"] +pub type CORREN_R = crate::BitReader; +#[doc = "Field `CORREN` writer - Digital Correction Logic Enable"] +pub type CORREN_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRLC_SPEC, bool, O>; +#[doc = "Field `RESSEL` reader - Conversion Result Resolution"] +pub type RESSEL_R = crate::FieldReader; +#[doc = "Conversion Result Resolution\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum RESSELSELECT_A { + #[doc = "0: 12-bit result"] + _12BIT = 0, + #[doc = "1: For averaging mode output"] + _16BIT = 1, + #[doc = "2: 10-bit result"] + _10BIT = 2, + #[doc = "3: 8-bit result"] + _8BIT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RESSELSELECT_A) -> Self { + variant as _ + } +} +impl RESSEL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RESSELSELECT_A { + match self.bits { + 0 => RESSELSELECT_A::_12BIT, + 1 => RESSELSELECT_A::_16BIT, + 2 => RESSELSELECT_A::_10BIT, + 3 => RESSELSELECT_A::_8BIT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `_12BIT`"] + #[inline(always)] + pub fn is_12bit(&self) -> bool { + *self == RESSELSELECT_A::_12BIT + } + #[doc = "Checks if the value of the field is `_16BIT`"] + #[inline(always)] + pub fn is_16bit(&self) -> bool { + *self == RESSELSELECT_A::_16BIT + } + #[doc = "Checks if the value of the field is `_10BIT`"] + #[inline(always)] + pub fn is_10bit(&self) -> bool { + *self == RESSELSELECT_A::_10BIT + } + #[doc = "Checks if the value of the field is `_8BIT`"] + #[inline(always)] + pub fn is_8bit(&self) -> bool { + *self == RESSELSELECT_A::_8BIT + } +} +#[doc = "Field `RESSEL` writer - Conversion Result Resolution"] +pub type RESSEL_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u16, CTRLC_SPEC, u8, RESSELSELECT_A, 2, O>; +impl<'a, const O: u8> RESSEL_W<'a, O> { + #[doc = "12-bit result"] + #[inline(always)] + pub fn _12bit(self) -> &'a mut W { + self.variant(RESSELSELECT_A::_12BIT) + } + #[doc = "For averaging mode output"] + #[inline(always)] + pub fn _16bit(self) -> &'a mut W { + self.variant(RESSELSELECT_A::_16BIT) + } + #[doc = "10-bit result"] + #[inline(always)] + pub fn _10bit(self) -> &'a mut W { + self.variant(RESSELSELECT_A::_10BIT) + } + #[doc = "8-bit result"] + #[inline(always)] + pub fn _8bit(self) -> &'a mut W { + self.variant(RESSELSELECT_A::_8BIT) + } +} +#[doc = "Field `R2R` reader - Rail-to-Rail mode enable"] +pub type R2R_R = crate::BitReader; +#[doc = "Field `R2R` writer - Rail-to-Rail mode enable"] +pub type R2R_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRLC_SPEC, bool, O>; +#[doc = "Field `WINMODE` reader - Window Monitor Mode"] +pub type WINMODE_R = crate::FieldReader; +#[doc = "Window Monitor Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum WINMODESELECT_A { + #[doc = "0: No window mode (default)"] + DISABLE = 0, + #[doc = "1: RESULT > WINLT"] + MODE1 = 1, + #[doc = "2: RESULT < WINUT"] + MODE2 = 2, + #[doc = "3: WINLT < RESULT < WINUT"] + MODE3 = 3, + #[doc = "4: !(WINLT < RESULT < WINUT)"] + MODE4 = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WINMODESELECT_A) -> Self { + variant as _ + } +} +impl WINMODE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WINMODESELECT_A::DISABLE), + 1 => Some(WINMODESELECT_A::MODE1), + 2 => Some(WINMODESELECT_A::MODE2), + 3 => Some(WINMODESELECT_A::MODE3), + 4 => Some(WINMODESELECT_A::MODE4), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == WINMODESELECT_A::DISABLE + } + #[doc = "Checks if the value of the field is `MODE1`"] + #[inline(always)] + pub fn is_mode1(&self) -> bool { + *self == WINMODESELECT_A::MODE1 + } + #[doc = "Checks if the value of the field is `MODE2`"] + #[inline(always)] + pub fn is_mode2(&self) -> bool { + *self == WINMODESELECT_A::MODE2 + } + #[doc = "Checks if the value of the field is `MODE3`"] + #[inline(always)] + pub fn is_mode3(&self) -> bool { + *self == WINMODESELECT_A::MODE3 + } + #[doc = "Checks if the value of the field is `MODE4`"] + #[inline(always)] + pub fn is_mode4(&self) -> bool { + *self == WINMODESELECT_A::MODE4 + } +} +#[doc = "Field `WINMODE` writer - Window Monitor Mode"] +pub type WINMODE_W<'a, const O: u8> = + crate::FieldWriter<'a, u16, CTRLC_SPEC, u8, WINMODESELECT_A, 3, O>; +impl<'a, const O: u8> WINMODE_W<'a, O> { + #[doc = "No window mode (default)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(WINMODESELECT_A::DISABLE) + } + #[doc = "RESULT > WINLT"] + #[inline(always)] + pub fn mode1(self) -> &'a mut W { + self.variant(WINMODESELECT_A::MODE1) + } + #[doc = "RESULT < WINUT"] + #[inline(always)] + pub fn mode2(self) -> &'a mut W { + self.variant(WINMODESELECT_A::MODE2) + } + #[doc = "WINLT < RESULT < WINUT"] + #[inline(always)] + pub fn mode3(self) -> &'a mut W { + self.variant(WINMODESELECT_A::MODE3) + } + #[doc = "!(WINLT < RESULT < WINUT)"] + #[inline(always)] + pub fn mode4(self) -> &'a mut W { + self.variant(WINMODESELECT_A::MODE4) + } +} +#[doc = "Field `DUALSEL` reader - Dual Mode Trigger Selection"] +pub type DUALSEL_R = crate::FieldReader; +#[doc = "Dual Mode Trigger Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum DUALSELSELECT_A { + #[doc = "0: Start event or software trigger will start a conversion on both ADCs"] + BOTH = 0, + #[doc = "1: START event or software trigger will alternatingly start a conversion on ADC0 and ADC1"] + INTERLEAVE = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DUALSELSELECT_A) -> Self { + variant as _ + } +} +impl DUALSEL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(DUALSELSELECT_A::BOTH), + 1 => Some(DUALSELSELECT_A::INTERLEAVE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + *self == DUALSELSELECT_A::BOTH + } + #[doc = "Checks if the value of the field is `INTERLEAVE`"] + #[inline(always)] + pub fn is_interleave(&self) -> bool { + *self == DUALSELSELECT_A::INTERLEAVE + } +} +#[doc = "Field `DUALSEL` writer - Dual Mode Trigger Selection"] +pub type DUALSEL_W<'a, const O: u8> = + crate::FieldWriter<'a, u16, CTRLC_SPEC, u8, DUALSELSELECT_A, 2, O>; +impl<'a, const O: u8> DUALSEL_W<'a, O> { + #[doc = "Start event or software trigger will start a conversion on both ADCs"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(DUALSELSELECT_A::BOTH) + } + #[doc = "START event or software trigger will alternatingly start a conversion on ADC0 and ADC1"] + #[inline(always)] + pub fn interleave(self) -> &'a mut W { + self.variant(DUALSELSELECT_A::INTERLEAVE) + } +} +impl R { + #[doc = "Bit 0 - Differential Mode"] + #[inline(always)] + pub fn diffmode(&self) -> DIFFMODE_R { + DIFFMODE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Left-Adjusted Result"] + #[inline(always)] + pub fn leftadj(&self) -> LEFTADJ_R { + LEFTADJ_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Free Running Mode"] + #[inline(always)] + pub fn freerun(&self) -> FREERUN_R { + FREERUN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Digital Correction Logic Enable"] + #[inline(always)] + pub fn corren(&self) -> CORREN_R { + CORREN_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:5 - Conversion Result Resolution"] + #[inline(always)] + pub fn ressel(&self) -> RESSEL_R { + RESSEL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 7 - Rail-to-Rail mode enable"] + #[inline(always)] + pub fn r2r(&self) -> R2R_R { + R2R_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:10 - Window Monitor Mode"] + #[inline(always)] + pub fn winmode(&self) -> WINMODE_R { + WINMODE_R::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bits 12:13 - Dual Mode Trigger Selection"] + #[inline(always)] + pub fn dualsel(&self) -> DUALSEL_R { + DUALSEL_R::new(((self.bits >> 12) & 3) as u8) + } +} +impl W { + #[doc = "Bit 0 - Differential Mode"] + #[inline(always)] + #[must_use] + pub fn diffmode(&mut self) -> DIFFMODE_W<0> { + DIFFMODE_W::new(self) + } + #[doc = "Bit 1 - Left-Adjusted Result"] + #[inline(always)] + #[must_use] + pub fn leftadj(&mut self) -> LEFTADJ_W<1> { + LEFTADJ_W::new(self) + } + #[doc = "Bit 2 - Free Running Mode"] + #[inline(always)] + #[must_use] + pub fn freerun(&mut self) -> FREERUN_W<2> { + FREERUN_W::new(self) + } + #[doc = "Bit 3 - Digital Correction Logic Enable"] + #[inline(always)] + #[must_use] + pub fn corren(&mut self) -> CORREN_W<3> { + CORREN_W::new(self) + } + #[doc = "Bits 4:5 - Conversion Result Resolution"] + #[inline(always)] + #[must_use] + pub fn ressel(&mut self) -> RESSEL_W<4> { + RESSEL_W::new(self) + } + #[doc = "Bit 7 - Rail-to-Rail mode enable"] + #[inline(always)] + #[must_use] + pub fn r2r(&mut self) -> R2R_W<7> { + R2R_W::new(self) + } + #[doc = "Bits 8:10 - Window Monitor Mode"] + #[inline(always)] + #[must_use] + pub fn winmode(&mut self) -> WINMODE_W<8> { + WINMODE_W::new(self) + } + #[doc = "Bits 12:13 - Dual Mode Trigger Selection"] + #[inline(always)] + #[must_use] + pub fn dualsel(&mut self) -> DUALSEL_W<12> { + DUALSEL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlc](index.html) module"] +pub struct CTRLC_SPEC; +impl crate::RegisterSpec for CTRLC_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrlc::R](R) reader structure"] +impl crate::Readable for CTRLC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlc::W](W) writer structure"] +impl crate::Writable for CTRLC_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRLC to value 0"] +impl crate::Resettable for CTRLC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/adc/dbgctrl.rs b/pac/atsaml22j/src/adc/dbgctrl.rs new file mode 100644 index 000000000000..71c6b3e56bf2 --- /dev/null +++ b/pac/atsaml22j/src/adc/dbgctrl.rs @@ -0,0 +1,80 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Run"] +pub type DBGRUN_R = crate::BitReader; +#[doc = "Field `DBGRUN` writer - Debug Run"] +pub type DBGRUN_W<'a, const O: u8> = crate::BitWriter<'a, u8, DBGCTRL_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + #[must_use] + pub fn dbgrun(&mut self) -> DBGRUN_W<0> { + DBGRUN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/adc/evctrl.rs b/pac/atsaml22j/src/adc/evctrl.rs new file mode 100644 index 000000000000..802489c93370 --- /dev/null +++ b/pac/atsaml22j/src/adc/evctrl.rs @@ -0,0 +1,155 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FLUSHEI` reader - Flush Event Input Enable"] +pub type FLUSHEI_R = crate::BitReader; +#[doc = "Field `FLUSHEI` writer - Flush Event Input Enable"] +pub type FLUSHEI_W<'a, const O: u8> = crate::BitWriter<'a, u8, EVCTRL_SPEC, bool, O>; +#[doc = "Field `STARTEI` reader - Start Conversion Event Input Enable"] +pub type STARTEI_R = crate::BitReader; +#[doc = "Field `STARTEI` writer - Start Conversion Event Input Enable"] +pub type STARTEI_W<'a, const O: u8> = crate::BitWriter<'a, u8, EVCTRL_SPEC, bool, O>; +#[doc = "Field `FLUSHINV` reader - Flush Event Invert Enable"] +pub type FLUSHINV_R = crate::BitReader; +#[doc = "Field `FLUSHINV` writer - Flush Event Invert Enable"] +pub type FLUSHINV_W<'a, const O: u8> = crate::BitWriter<'a, u8, EVCTRL_SPEC, bool, O>; +#[doc = "Field `STARTINV` reader - Satrt Event Invert Enable"] +pub type STARTINV_R = crate::BitReader; +#[doc = "Field `STARTINV` writer - Satrt Event Invert Enable"] +pub type STARTINV_W<'a, const O: u8> = crate::BitWriter<'a, u8, EVCTRL_SPEC, bool, O>; +#[doc = "Field `RESRDYEO` reader - Result Ready Event Out"] +pub type RESRDYEO_R = crate::BitReader; +#[doc = "Field `RESRDYEO` writer - Result Ready Event Out"] +pub type RESRDYEO_W<'a, const O: u8> = crate::BitWriter<'a, u8, EVCTRL_SPEC, bool, O>; +#[doc = "Field `WINMONEO` reader - Window Monitor Event Out"] +pub type WINMONEO_R = crate::BitReader; +#[doc = "Field `WINMONEO` writer - Window Monitor Event Out"] +pub type WINMONEO_W<'a, const O: u8> = crate::BitWriter<'a, u8, EVCTRL_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Flush Event Input Enable"] + #[inline(always)] + pub fn flushei(&self) -> FLUSHEI_R { + FLUSHEI_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Start Conversion Event Input Enable"] + #[inline(always)] + pub fn startei(&self) -> STARTEI_R { + STARTEI_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Flush Event Invert Enable"] + #[inline(always)] + pub fn flushinv(&self) -> FLUSHINV_R { + FLUSHINV_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Satrt Event Invert Enable"] + #[inline(always)] + pub fn startinv(&self) -> STARTINV_R { + STARTINV_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Result Ready Event Out"] + #[inline(always)] + pub fn resrdyeo(&self) -> RESRDYEO_R { + RESRDYEO_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Window Monitor Event Out"] + #[inline(always)] + pub fn winmoneo(&self) -> WINMONEO_R { + WINMONEO_R::new(((self.bits >> 5) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Flush Event Input Enable"] + #[inline(always)] + #[must_use] + pub fn flushei(&mut self) -> FLUSHEI_W<0> { + FLUSHEI_W::new(self) + } + #[doc = "Bit 1 - Start Conversion Event Input Enable"] + #[inline(always)] + #[must_use] + pub fn startei(&mut self) -> STARTEI_W<1> { + STARTEI_W::new(self) + } + #[doc = "Bit 2 - Flush Event Invert Enable"] + #[inline(always)] + #[must_use] + pub fn flushinv(&mut self) -> FLUSHINV_W<2> { + FLUSHINV_W::new(self) + } + #[doc = "Bit 3 - Satrt Event Invert Enable"] + #[inline(always)] + #[must_use] + pub fn startinv(&mut self) -> STARTINV_W<3> { + STARTINV_W::new(self) + } + #[doc = "Bit 4 - Result Ready Event Out"] + #[inline(always)] + #[must_use] + pub fn resrdyeo(&mut self) -> RESRDYEO_W<4> { + RESRDYEO_W::new(self) + } + #[doc = "Bit 5 - Window Monitor Event Out"] + #[inline(always)] + #[must_use] + pub fn winmoneo(&mut self) -> WINMONEO_W<5> { + WINMONEO_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/adc/gaincorr.rs b/pac/atsaml22j/src/adc/gaincorr.rs new file mode 100644 index 000000000000..03fd43d2615f --- /dev/null +++ b/pac/atsaml22j/src/adc/gaincorr.rs @@ -0,0 +1,80 @@ +#[doc = "Register `GAINCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GAINCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GAINCORR` reader - Gain Correction Value"] +pub type GAINCORR_R = crate::FieldReader; +#[doc = "Field `GAINCORR` writer - Gain Correction Value"] +pub type GAINCORR_W<'a, const O: u8> = crate::FieldWriter<'a, u16, GAINCORR_SPEC, u16, u16, 12, O>; +impl R { + #[doc = "Bits 0:11 - Gain Correction Value"] + #[inline(always)] + pub fn gaincorr(&self) -> GAINCORR_R { + GAINCORR_R::new(self.bits & 0x0fff) + } +} +impl W { + #[doc = "Bits 0:11 - Gain Correction Value"] + #[inline(always)] + #[must_use] + pub fn gaincorr(&mut self) -> GAINCORR_W<0> { + GAINCORR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Gain Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gaincorr](index.html) module"] +pub struct GAINCORR_SPEC; +impl crate::RegisterSpec for GAINCORR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [gaincorr::R](R) reader structure"] +impl crate::Readable for GAINCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gaincorr::W](W) writer structure"] +impl crate::Writable for GAINCORR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GAINCORR to value 0"] +impl crate::Resettable for GAINCORR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/adc/inputctrl.rs b/pac/atsaml22j/src/adc/inputctrl.rs new file mode 100644 index 000000000000..53af4ec856f6 --- /dev/null +++ b/pac/atsaml22j/src/adc/inputctrl.rs @@ -0,0 +1,583 @@ +#[doc = "Register `INPUTCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INPUTCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MUXPOS` reader - Positive Mux Input Selection"] +pub type MUXPOS_R = crate::FieldReader; +#[doc = "Positive Mux Input Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum MUXPOSSELECT_A { + #[doc = "0: ADC AIN0 Pin"] + AIN0 = 0, + #[doc = "1: ADC AIN1 Pin"] + AIN1 = 1, + #[doc = "2: ADC AIN2 Pin"] + AIN2 = 2, + #[doc = "3: ADC AIN3 Pin"] + AIN3 = 3, + #[doc = "4: ADC AIN4 Pin"] + AIN4 = 4, + #[doc = "5: ADC AIN5 Pin"] + AIN5 = 5, + #[doc = "6: ADC AIN6 Pin"] + AIN6 = 6, + #[doc = "7: ADC AIN7 Pin"] + AIN7 = 7, + #[doc = "8: ADC AIN8 Pin"] + AIN8 = 8, + #[doc = "9: ADC AIN9 Pin"] + AIN9 = 9, + #[doc = "10: ADC AIN10 Pin"] + AIN10 = 10, + #[doc = "11: ADC AIN11 Pin"] + AIN11 = 11, + #[doc = "12: ADC AIN12 Pin"] + AIN12 = 12, + #[doc = "13: ADC AIN13 Pin"] + AIN13 = 13, + #[doc = "14: ADC AIN14 Pin"] + AIN14 = 14, + #[doc = "15: ADC AIN15 Pin"] + AIN15 = 15, + #[doc = "16: ADC AIN16 Pin"] + AIN16 = 16, + #[doc = "17: ADC AIN17 Pin"] + AIN17 = 17, + #[doc = "18: ADC AIN18 Pin"] + AIN18 = 18, + #[doc = "19: ADC AIN19 Pin"] + AIN19 = 19, + #[doc = "24: Temperature Sensor"] + TEMP = 24, + #[doc = "25: Bandgap Voltage"] + BANDGAP = 25, + #[doc = "26: 1/4 Scaled Core Supply"] + SCALEDCOREVCC = 26, + #[doc = "27: 1/4 Scaled I/O Supply"] + SCALEDIOVCC = 27, + #[doc = "29: 1/4 Scaled VBAT Supply"] + SCALEDVBAT = 29, + #[doc = "30: CTAT output"] + CTAT = 30, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MUXPOSSELECT_A) -> Self { + variant as _ + } +} +impl MUXPOS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MUXPOSSELECT_A::AIN0), + 1 => Some(MUXPOSSELECT_A::AIN1), + 2 => Some(MUXPOSSELECT_A::AIN2), + 3 => Some(MUXPOSSELECT_A::AIN3), + 4 => Some(MUXPOSSELECT_A::AIN4), + 5 => Some(MUXPOSSELECT_A::AIN5), + 6 => Some(MUXPOSSELECT_A::AIN6), + 7 => Some(MUXPOSSELECT_A::AIN7), + 8 => Some(MUXPOSSELECT_A::AIN8), + 9 => Some(MUXPOSSELECT_A::AIN9), + 10 => Some(MUXPOSSELECT_A::AIN10), + 11 => Some(MUXPOSSELECT_A::AIN11), + 12 => Some(MUXPOSSELECT_A::AIN12), + 13 => Some(MUXPOSSELECT_A::AIN13), + 14 => Some(MUXPOSSELECT_A::AIN14), + 15 => Some(MUXPOSSELECT_A::AIN15), + 16 => Some(MUXPOSSELECT_A::AIN16), + 17 => Some(MUXPOSSELECT_A::AIN17), + 18 => Some(MUXPOSSELECT_A::AIN18), + 19 => Some(MUXPOSSELECT_A::AIN19), + 24 => Some(MUXPOSSELECT_A::TEMP), + 25 => Some(MUXPOSSELECT_A::BANDGAP), + 26 => Some(MUXPOSSELECT_A::SCALEDCOREVCC), + 27 => Some(MUXPOSSELECT_A::SCALEDIOVCC), + 29 => Some(MUXPOSSELECT_A::SCALEDVBAT), + 30 => Some(MUXPOSSELECT_A::CTAT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `AIN0`"] + #[inline(always)] + pub fn is_ain0(&self) -> bool { + *self == MUXPOSSELECT_A::AIN0 + } + #[doc = "Checks if the value of the field is `AIN1`"] + #[inline(always)] + pub fn is_ain1(&self) -> bool { + *self == MUXPOSSELECT_A::AIN1 + } + #[doc = "Checks if the value of the field is `AIN2`"] + #[inline(always)] + pub fn is_ain2(&self) -> bool { + *self == MUXPOSSELECT_A::AIN2 + } + #[doc = "Checks if the value of the field is `AIN3`"] + #[inline(always)] + pub fn is_ain3(&self) -> bool { + *self == MUXPOSSELECT_A::AIN3 + } + #[doc = "Checks if the value of the field is `AIN4`"] + #[inline(always)] + pub fn is_ain4(&self) -> bool { + *self == MUXPOSSELECT_A::AIN4 + } + #[doc = "Checks if the value of the field is `AIN5`"] + #[inline(always)] + pub fn is_ain5(&self) -> bool { + *self == MUXPOSSELECT_A::AIN5 + } + #[doc = "Checks if the value of the field is `AIN6`"] + #[inline(always)] + pub fn is_ain6(&self) -> bool { + *self == MUXPOSSELECT_A::AIN6 + } + #[doc = "Checks if the value of the field is `AIN7`"] + #[inline(always)] + pub fn is_ain7(&self) -> bool { + *self == MUXPOSSELECT_A::AIN7 + } + #[doc = "Checks if the value of the field is `AIN8`"] + #[inline(always)] + pub fn is_ain8(&self) -> bool { + *self == MUXPOSSELECT_A::AIN8 + } + #[doc = "Checks if the value of the field is `AIN9`"] + #[inline(always)] + pub fn is_ain9(&self) -> bool { + *self == MUXPOSSELECT_A::AIN9 + } + #[doc = "Checks if the value of the field is `AIN10`"] + #[inline(always)] + pub fn is_ain10(&self) -> bool { + *self == MUXPOSSELECT_A::AIN10 + } + #[doc = "Checks if the value of the field is `AIN11`"] + #[inline(always)] + pub fn is_ain11(&self) -> bool { + *self == MUXPOSSELECT_A::AIN11 + } + #[doc = "Checks if the value of the field is `AIN12`"] + #[inline(always)] + pub fn is_ain12(&self) -> bool { + *self == MUXPOSSELECT_A::AIN12 + } + #[doc = "Checks if the value of the field is `AIN13`"] + #[inline(always)] + pub fn is_ain13(&self) -> bool { + *self == MUXPOSSELECT_A::AIN13 + } + #[doc = "Checks if the value of the field is `AIN14`"] + #[inline(always)] + pub fn is_ain14(&self) -> bool { + *self == MUXPOSSELECT_A::AIN14 + } + #[doc = "Checks if the value of the field is `AIN15`"] + #[inline(always)] + pub fn is_ain15(&self) -> bool { + *self == MUXPOSSELECT_A::AIN15 + } + #[doc = "Checks if the value of the field is `AIN16`"] + #[inline(always)] + pub fn is_ain16(&self) -> bool { + *self == MUXPOSSELECT_A::AIN16 + } + #[doc = "Checks if the value of the field is `AIN17`"] + #[inline(always)] + pub fn is_ain17(&self) -> bool { + *self == MUXPOSSELECT_A::AIN17 + } + #[doc = "Checks if the value of the field is `AIN18`"] + #[inline(always)] + pub fn is_ain18(&self) -> bool { + *self == MUXPOSSELECT_A::AIN18 + } + #[doc = "Checks if the value of the field is `AIN19`"] + #[inline(always)] + pub fn is_ain19(&self) -> bool { + *self == MUXPOSSELECT_A::AIN19 + } + #[doc = "Checks if the value of the field is `TEMP`"] + #[inline(always)] + pub fn is_temp(&self) -> bool { + *self == MUXPOSSELECT_A::TEMP + } + #[doc = "Checks if the value of the field is `BANDGAP`"] + #[inline(always)] + pub fn is_bandgap(&self) -> bool { + *self == MUXPOSSELECT_A::BANDGAP + } + #[doc = "Checks if the value of the field is `SCALEDCOREVCC`"] + #[inline(always)] + pub fn is_scaledcorevcc(&self) -> bool { + *self == MUXPOSSELECT_A::SCALEDCOREVCC + } + #[doc = "Checks if the value of the field is `SCALEDIOVCC`"] + #[inline(always)] + pub fn is_scalediovcc(&self) -> bool { + *self == MUXPOSSELECT_A::SCALEDIOVCC + } + #[doc = "Checks if the value of the field is `SCALEDVBAT`"] + #[inline(always)] + pub fn is_scaledvbat(&self) -> bool { + *self == MUXPOSSELECT_A::SCALEDVBAT + } + #[doc = "Checks if the value of the field is `CTAT`"] + #[inline(always)] + pub fn is_ctat(&self) -> bool { + *self == MUXPOSSELECT_A::CTAT + } +} +#[doc = "Field `MUXPOS` writer - Positive Mux Input Selection"] +pub type MUXPOS_W<'a, const O: u8> = + crate::FieldWriter<'a, u16, INPUTCTRL_SPEC, u8, MUXPOSSELECT_A, 5, O>; +impl<'a, const O: u8> MUXPOS_W<'a, O> { + #[doc = "ADC AIN0 Pin"] + #[inline(always)] + pub fn ain0(self) -> &'a mut W { + self.variant(MUXPOSSELECT_A::AIN0) + } + #[doc = "ADC AIN1 Pin"] + #[inline(always)] + pub fn ain1(self) -> &'a mut W { + self.variant(MUXPOSSELECT_A::AIN1) + } + #[doc = "ADC AIN2 Pin"] + #[inline(always)] + pub fn ain2(self) -> &'a mut W { + self.variant(MUXPOSSELECT_A::AIN2) + } + #[doc = "ADC AIN3 Pin"] + #[inline(always)] + pub fn ain3(self) -> &'a mut W { + self.variant(MUXPOSSELECT_A::AIN3) + } + #[doc = "ADC AIN4 Pin"] + #[inline(always)] + pub fn ain4(self) -> &'a mut W { + self.variant(MUXPOSSELECT_A::AIN4) + } + #[doc = "ADC AIN5 Pin"] + #[inline(always)] + pub fn ain5(self) -> &'a mut W { + self.variant(MUXPOSSELECT_A::AIN5) + } + #[doc = "ADC AIN6 Pin"] + #[inline(always)] + pub fn ain6(self) -> &'a mut W { + self.variant(MUXPOSSELECT_A::AIN6) + } + #[doc = "ADC AIN7 Pin"] + #[inline(always)] + pub fn ain7(self) -> &'a mut W { + self.variant(MUXPOSSELECT_A::AIN7) + } + #[doc = "ADC AIN8 Pin"] + #[inline(always)] + pub fn ain8(self) -> &'a mut W { + self.variant(MUXPOSSELECT_A::AIN8) + } + #[doc = "ADC AIN9 Pin"] + #[inline(always)] + pub fn ain9(self) -> &'a mut W { + self.variant(MUXPOSSELECT_A::AIN9) + } + #[doc = "ADC AIN10 Pin"] + #[inline(always)] + pub fn ain10(self) -> &'a mut W { + self.variant(MUXPOSSELECT_A::AIN10) + } + #[doc = "ADC AIN11 Pin"] + #[inline(always)] + pub fn ain11(self) -> &'a mut W { + self.variant(MUXPOSSELECT_A::AIN11) + } + #[doc = "ADC AIN12 Pin"] + #[inline(always)] + pub fn ain12(self) -> &'a mut W { + self.variant(MUXPOSSELECT_A::AIN12) + } + #[doc = "ADC AIN13 Pin"] + #[inline(always)] + pub fn ain13(self) -> &'a mut W { + self.variant(MUXPOSSELECT_A::AIN13) + } + #[doc = "ADC AIN14 Pin"] + #[inline(always)] + pub fn ain14(self) -> &'a mut W { + self.variant(MUXPOSSELECT_A::AIN14) + } + #[doc = "ADC AIN15 Pin"] + #[inline(always)] + pub fn ain15(self) -> &'a mut W { + self.variant(MUXPOSSELECT_A::AIN15) + } + #[doc = "ADC AIN16 Pin"] + #[inline(always)] + pub fn ain16(self) -> &'a mut W { + self.variant(MUXPOSSELECT_A::AIN16) + } + #[doc = "ADC AIN17 Pin"] + #[inline(always)] + pub fn ain17(self) -> &'a mut W { + self.variant(MUXPOSSELECT_A::AIN17) + } + #[doc = "ADC AIN18 Pin"] + #[inline(always)] + pub fn ain18(self) -> &'a mut W { + self.variant(MUXPOSSELECT_A::AIN18) + } + #[doc = "ADC AIN19 Pin"] + #[inline(always)] + pub fn ain19(self) -> &'a mut W { + self.variant(MUXPOSSELECT_A::AIN19) + } + #[doc = "Temperature Sensor"] + #[inline(always)] + pub fn temp(self) -> &'a mut W { + self.variant(MUXPOSSELECT_A::TEMP) + } + #[doc = "Bandgap Voltage"] + #[inline(always)] + pub fn bandgap(self) -> &'a mut W { + self.variant(MUXPOSSELECT_A::BANDGAP) + } + #[doc = "1/4 Scaled Core Supply"] + #[inline(always)] + pub fn scaledcorevcc(self) -> &'a mut W { + self.variant(MUXPOSSELECT_A::SCALEDCOREVCC) + } + #[doc = "1/4 Scaled I/O Supply"] + #[inline(always)] + pub fn scalediovcc(self) -> &'a mut W { + self.variant(MUXPOSSELECT_A::SCALEDIOVCC) + } + #[doc = "1/4 Scaled VBAT Supply"] + #[inline(always)] + pub fn scaledvbat(self) -> &'a mut W { + self.variant(MUXPOSSELECT_A::SCALEDVBAT) + } + #[doc = "CTAT output"] + #[inline(always)] + pub fn ctat(self) -> &'a mut W { + self.variant(MUXPOSSELECT_A::CTAT) + } +} +#[doc = "Field `MUXNEG` reader - Negative Mux Input Selection"] +pub type MUXNEG_R = crate::FieldReader; +#[doc = "Negative Mux Input Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum MUXNEGSELECT_A { + #[doc = "0: ADC AIN0 Pin"] + AIN0 = 0, + #[doc = "1: ADC AIN1 Pin"] + AIN1 = 1, + #[doc = "2: ADC AIN2 Pin"] + AIN2 = 2, + #[doc = "3: ADC AIN3 Pin"] + AIN3 = 3, + #[doc = "4: ADC AIN4 Pin"] + AIN4 = 4, + #[doc = "5: ADC AIN5 Pin"] + AIN5 = 5, + #[doc = "6: ADC AIN6 Pin"] + AIN6 = 6, + #[doc = "7: ADC AIN7 Pin"] + AIN7 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MUXNEGSELECT_A) -> Self { + variant as _ + } +} +impl MUXNEG_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MUXNEGSELECT_A::AIN0), + 1 => Some(MUXNEGSELECT_A::AIN1), + 2 => Some(MUXNEGSELECT_A::AIN2), + 3 => Some(MUXNEGSELECT_A::AIN3), + 4 => Some(MUXNEGSELECT_A::AIN4), + 5 => Some(MUXNEGSELECT_A::AIN5), + 6 => Some(MUXNEGSELECT_A::AIN6), + 7 => Some(MUXNEGSELECT_A::AIN7), + _ => None, + } + } + #[doc = "Checks if the value of the field is `AIN0`"] + #[inline(always)] + pub fn is_ain0(&self) -> bool { + *self == MUXNEGSELECT_A::AIN0 + } + #[doc = "Checks if the value of the field is `AIN1`"] + #[inline(always)] + pub fn is_ain1(&self) -> bool { + *self == MUXNEGSELECT_A::AIN1 + } + #[doc = "Checks if the value of the field is `AIN2`"] + #[inline(always)] + pub fn is_ain2(&self) -> bool { + *self == MUXNEGSELECT_A::AIN2 + } + #[doc = "Checks if the value of the field is `AIN3`"] + #[inline(always)] + pub fn is_ain3(&self) -> bool { + *self == MUXNEGSELECT_A::AIN3 + } + #[doc = "Checks if the value of the field is `AIN4`"] + #[inline(always)] + pub fn is_ain4(&self) -> bool { + *self == MUXNEGSELECT_A::AIN4 + } + #[doc = "Checks if the value of the field is `AIN5`"] + #[inline(always)] + pub fn is_ain5(&self) -> bool { + *self == MUXNEGSELECT_A::AIN5 + } + #[doc = "Checks if the value of the field is `AIN6`"] + #[inline(always)] + pub fn is_ain6(&self) -> bool { + *self == MUXNEGSELECT_A::AIN6 + } + #[doc = "Checks if the value of the field is `AIN7`"] + #[inline(always)] + pub fn is_ain7(&self) -> bool { + *self == MUXNEGSELECT_A::AIN7 + } +} +#[doc = "Field `MUXNEG` writer - Negative Mux Input Selection"] +pub type MUXNEG_W<'a, const O: u8> = + crate::FieldWriter<'a, u16, INPUTCTRL_SPEC, u8, MUXNEGSELECT_A, 5, O>; +impl<'a, const O: u8> MUXNEG_W<'a, O> { + #[doc = "ADC AIN0 Pin"] + #[inline(always)] + pub fn ain0(self) -> &'a mut W { + self.variant(MUXNEGSELECT_A::AIN0) + } + #[doc = "ADC AIN1 Pin"] + #[inline(always)] + pub fn ain1(self) -> &'a mut W { + self.variant(MUXNEGSELECT_A::AIN1) + } + #[doc = "ADC AIN2 Pin"] + #[inline(always)] + pub fn ain2(self) -> &'a mut W { + self.variant(MUXNEGSELECT_A::AIN2) + } + #[doc = "ADC AIN3 Pin"] + #[inline(always)] + pub fn ain3(self) -> &'a mut W { + self.variant(MUXNEGSELECT_A::AIN3) + } + #[doc = "ADC AIN4 Pin"] + #[inline(always)] + pub fn ain4(self) -> &'a mut W { + self.variant(MUXNEGSELECT_A::AIN4) + } + #[doc = "ADC AIN5 Pin"] + #[inline(always)] + pub fn ain5(self) -> &'a mut W { + self.variant(MUXNEGSELECT_A::AIN5) + } + #[doc = "ADC AIN6 Pin"] + #[inline(always)] + pub fn ain6(self) -> &'a mut W { + self.variant(MUXNEGSELECT_A::AIN6) + } + #[doc = "ADC AIN7 Pin"] + #[inline(always)] + pub fn ain7(self) -> &'a mut W { + self.variant(MUXNEGSELECT_A::AIN7) + } +} +impl R { + #[doc = "Bits 0:4 - Positive Mux Input Selection"] + #[inline(always)] + pub fn muxpos(&self) -> MUXPOS_R { + MUXPOS_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 8:12 - Negative Mux Input Selection"] + #[inline(always)] + pub fn muxneg(&self) -> MUXNEG_R { + MUXNEG_R::new(((self.bits >> 8) & 0x1f) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - Positive Mux Input Selection"] + #[inline(always)] + #[must_use] + pub fn muxpos(&mut self) -> MUXPOS_W<0> { + MUXPOS_W::new(self) + } + #[doc = "Bits 8:12 - Negative Mux Input Selection"] + #[inline(always)] + #[must_use] + pub fn muxneg(&mut self) -> MUXNEG_W<8> { + MUXNEG_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Input Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [inputctrl](index.html) module"] +pub struct INPUTCTRL_SPEC; +impl crate::RegisterSpec for INPUTCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [inputctrl::R](R) reader structure"] +impl crate::Readable for INPUTCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [inputctrl::W](W) writer structure"] +impl crate::Writable for INPUTCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INPUTCTRL to value 0"] +impl crate::Resettable for INPUTCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/adc/intenclr.rs b/pac/atsaml22j/src/adc/intenclr.rs new file mode 100644 index 000000000000..ee95db62897d --- /dev/null +++ b/pac/atsaml22j/src/adc/intenclr.rs @@ -0,0 +1,110 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready Interrupt Disable"] +pub type RESRDY_R = crate::BitReader; +#[doc = "Field `RESRDY` writer - Result Ready Interrupt Disable"] +pub type RESRDY_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>; +#[doc = "Field `OVERRUN` reader - Overrun Interrupt Disable"] +pub type OVERRUN_R = crate::BitReader; +#[doc = "Field `OVERRUN` writer - Overrun Interrupt Disable"] +pub type OVERRUN_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>; +#[doc = "Field `WINMON` reader - Window Monitor Interrupt Disable"] +pub type WINMON_R = crate::BitReader; +#[doc = "Field `WINMON` writer - Window Monitor Interrupt Disable"] +pub type WINMON_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Result Ready Interrupt Disable"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Overrun Interrupt Disable"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Window Monitor Interrupt Disable"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready Interrupt Disable"] + #[inline(always)] + #[must_use] + pub fn resrdy(&mut self) -> RESRDY_W<0> { + RESRDY_W::new(self) + } + #[doc = "Bit 1 - Overrun Interrupt Disable"] + #[inline(always)] + #[must_use] + pub fn overrun(&mut self) -> OVERRUN_W<1> { + OVERRUN_W::new(self) + } + #[doc = "Bit 2 - Window Monitor Interrupt Disable"] + #[inline(always)] + #[must_use] + pub fn winmon(&mut self) -> WINMON_W<2> { + WINMON_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/adc/intenset.rs b/pac/atsaml22j/src/adc/intenset.rs new file mode 100644 index 000000000000..1d62d36c653e --- /dev/null +++ b/pac/atsaml22j/src/adc/intenset.rs @@ -0,0 +1,110 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready Interrupt Enable"] +pub type RESRDY_R = crate::BitReader; +#[doc = "Field `RESRDY` writer - Result Ready Interrupt Enable"] +pub type RESRDY_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENSET_SPEC, bool, O>; +#[doc = "Field `OVERRUN` reader - Overrun Interrupt Enable"] +pub type OVERRUN_R = crate::BitReader; +#[doc = "Field `OVERRUN` writer - Overrun Interrupt Enable"] +pub type OVERRUN_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENSET_SPEC, bool, O>; +#[doc = "Field `WINMON` reader - Window Monitor Interrupt Enable"] +pub type WINMON_R = crate::BitReader; +#[doc = "Field `WINMON` writer - Window Monitor Interrupt Enable"] +pub type WINMON_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENSET_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Result Ready Interrupt Enable"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Overrun Interrupt Enable"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Window Monitor Interrupt Enable"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn resrdy(&mut self) -> RESRDY_W<0> { + RESRDY_W::new(self) + } + #[doc = "Bit 1 - Overrun Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn overrun(&mut self) -> OVERRUN_W<1> { + OVERRUN_W::new(self) + } + #[doc = "Bit 2 - Window Monitor Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn winmon(&mut self) -> WINMON_W<2> { + WINMON_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/adc/intflag.rs b/pac/atsaml22j/src/adc/intflag.rs new file mode 100644 index 000000000000..a74d817da7a7 --- /dev/null +++ b/pac/atsaml22j/src/adc/intflag.rs @@ -0,0 +1,110 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RESRDY` reader - Result Ready Interrupt Flag"] +pub type RESRDY_R = crate::BitReader; +#[doc = "Field `RESRDY` writer - Result Ready Interrupt Flag"] +pub type RESRDY_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTFLAG_SPEC, bool, O>; +#[doc = "Field `OVERRUN` reader - Overrun Interrupt Flag"] +pub type OVERRUN_R = crate::BitReader; +#[doc = "Field `OVERRUN` writer - Overrun Interrupt Flag"] +pub type OVERRUN_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTFLAG_SPEC, bool, O>; +#[doc = "Field `WINMON` reader - Window Monitor Interrupt Flag"] +pub type WINMON_R = crate::BitReader; +#[doc = "Field `WINMON` writer - Window Monitor Interrupt Flag"] +pub type WINMON_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTFLAG_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Result Ready Interrupt Flag"] + #[inline(always)] + pub fn resrdy(&self) -> RESRDY_R { + RESRDY_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Overrun Interrupt Flag"] + #[inline(always)] + pub fn overrun(&self) -> OVERRUN_R { + OVERRUN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Window Monitor Interrupt Flag"] + #[inline(always)] + pub fn winmon(&self) -> WINMON_R { + WINMON_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Result Ready Interrupt Flag"] + #[inline(always)] + #[must_use] + pub fn resrdy(&mut self) -> RESRDY_W<0> { + RESRDY_W::new(self) + } + #[doc = "Bit 1 - Overrun Interrupt Flag"] + #[inline(always)] + #[must_use] + pub fn overrun(&mut self) -> OVERRUN_W<1> { + OVERRUN_W::new(self) + } + #[doc = "Bit 2 - Window Monitor Interrupt Flag"] + #[inline(always)] + #[must_use] + pub fn winmon(&mut self) -> WINMON_W<2> { + WINMON_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/adc/offsetcorr.rs b/pac/atsaml22j/src/adc/offsetcorr.rs new file mode 100644 index 000000000000..6f1032a44edb --- /dev/null +++ b/pac/atsaml22j/src/adc/offsetcorr.rs @@ -0,0 +1,81 @@ +#[doc = "Register `OFFSETCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OFFSETCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OFFSETCORR` reader - Offset Correction Value"] +pub type OFFSETCORR_R = crate::FieldReader; +#[doc = "Field `OFFSETCORR` writer - Offset Correction Value"] +pub type OFFSETCORR_W<'a, const O: u8> = + crate::FieldWriter<'a, u16, OFFSETCORR_SPEC, u16, u16, 12, O>; +impl R { + #[doc = "Bits 0:11 - Offset Correction Value"] + #[inline(always)] + pub fn offsetcorr(&self) -> OFFSETCORR_R { + OFFSETCORR_R::new(self.bits & 0x0fff) + } +} +impl W { + #[doc = "Bits 0:11 - Offset Correction Value"] + #[inline(always)] + #[must_use] + pub fn offsetcorr(&mut self) -> OFFSETCORR_W<0> { + OFFSETCORR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Offset Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [offsetcorr](index.html) module"] +pub struct OFFSETCORR_SPEC; +impl crate::RegisterSpec for OFFSETCORR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [offsetcorr::R](R) reader structure"] +impl crate::Readable for OFFSETCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [offsetcorr::W](W) writer structure"] +impl crate::Writable for OFFSETCORR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OFFSETCORR to value 0"] +impl crate::Resettable for OFFSETCORR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/adc/refctrl.rs b/pac/atsaml22j/src/adc/refctrl.rs new file mode 100644 index 000000000000..a5cca404af90 --- /dev/null +++ b/pac/atsaml22j/src/adc/refctrl.rs @@ -0,0 +1,196 @@ +#[doc = "Register `REFCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `REFCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `REFSEL` reader - Reference Selection"] +pub type REFSEL_R = crate::FieldReader; +#[doc = "Reference Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum REFSELSELECT_A { + #[doc = "0: Internal Bandgap Reference"] + INTREF = 0, + #[doc = "1: 1/1.6 VDDANA"] + INTVCC0 = 1, + #[doc = "2: 1/2 VDDANA"] + INTVCC1 = 2, + #[doc = "3: External Reference"] + AREFA = 3, + #[doc = "4: External Reference"] + AREFB = 4, + #[doc = "5: VCCANA"] + INTVCC2 = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: REFSELSELECT_A) -> Self { + variant as _ + } +} +impl REFSEL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(REFSELSELECT_A::INTREF), + 1 => Some(REFSELSELECT_A::INTVCC0), + 2 => Some(REFSELSELECT_A::INTVCC1), + 3 => Some(REFSELSELECT_A::AREFA), + 4 => Some(REFSELSELECT_A::AREFB), + 5 => Some(REFSELSELECT_A::INTVCC2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `INTREF`"] + #[inline(always)] + pub fn is_intref(&self) -> bool { + *self == REFSELSELECT_A::INTREF + } + #[doc = "Checks if the value of the field is `INTVCC0`"] + #[inline(always)] + pub fn is_intvcc0(&self) -> bool { + *self == REFSELSELECT_A::INTVCC0 + } + #[doc = "Checks if the value of the field is `INTVCC1`"] + #[inline(always)] + pub fn is_intvcc1(&self) -> bool { + *self == REFSELSELECT_A::INTVCC1 + } + #[doc = "Checks if the value of the field is `AREFA`"] + #[inline(always)] + pub fn is_arefa(&self) -> bool { + *self == REFSELSELECT_A::AREFA + } + #[doc = "Checks if the value of the field is `AREFB`"] + #[inline(always)] + pub fn is_arefb(&self) -> bool { + *self == REFSELSELECT_A::AREFB + } + #[doc = "Checks if the value of the field is `INTVCC2`"] + #[inline(always)] + pub fn is_intvcc2(&self) -> bool { + *self == REFSELSELECT_A::INTVCC2 + } +} +#[doc = "Field `REFSEL` writer - Reference Selection"] +pub type REFSEL_W<'a, const O: u8> = + crate::FieldWriter<'a, u8, REFCTRL_SPEC, u8, REFSELSELECT_A, 4, O>; +impl<'a, const O: u8> REFSEL_W<'a, O> { + #[doc = "Internal Bandgap Reference"] + #[inline(always)] + pub fn intref(self) -> &'a mut W { + self.variant(REFSELSELECT_A::INTREF) + } + #[doc = "1/1.6 VDDANA"] + #[inline(always)] + pub fn intvcc0(self) -> &'a mut W { + self.variant(REFSELSELECT_A::INTVCC0) + } + #[doc = "1/2 VDDANA"] + #[inline(always)] + pub fn intvcc1(self) -> &'a mut W { + self.variant(REFSELSELECT_A::INTVCC1) + } + #[doc = "External Reference"] + #[inline(always)] + pub fn arefa(self) -> &'a mut W { + self.variant(REFSELSELECT_A::AREFA) + } + #[doc = "External Reference"] + #[inline(always)] + pub fn arefb(self) -> &'a mut W { + self.variant(REFSELSELECT_A::AREFB) + } + #[doc = "VCCANA"] + #[inline(always)] + pub fn intvcc2(self) -> &'a mut W { + self.variant(REFSELSELECT_A::INTVCC2) + } +} +#[doc = "Field `REFCOMP` reader - Reference Buffer Offset Compensation Enable"] +pub type REFCOMP_R = crate::BitReader; +#[doc = "Field `REFCOMP` writer - Reference Buffer Offset Compensation Enable"] +pub type REFCOMP_W<'a, const O: u8> = crate::BitWriter<'a, u8, REFCTRL_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:3 - Reference Selection"] + #[inline(always)] + pub fn refsel(&self) -> REFSEL_R { + REFSEL_R::new(self.bits & 0x0f) + } + #[doc = "Bit 7 - Reference Buffer Offset Compensation Enable"] + #[inline(always)] + pub fn refcomp(&self) -> REFCOMP_R { + REFCOMP_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Reference Selection"] + #[inline(always)] + #[must_use] + pub fn refsel(&mut self) -> REFSEL_W<0> { + REFSEL_W::new(self) + } + #[doc = "Bit 7 - Reference Buffer Offset Compensation Enable"] + #[inline(always)] + #[must_use] + pub fn refcomp(&mut self) -> REFCOMP_W<7> { + REFCOMP_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Reference Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [refctrl](index.html) module"] +pub struct REFCTRL_SPEC; +impl crate::RegisterSpec for REFCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [refctrl::R](R) reader structure"] +impl crate::Readable for REFCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [refctrl::W](W) writer structure"] +impl crate::Writable for REFCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets REFCTRL to value 0"] +impl crate::Resettable for REFCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/adc/result.rs b/pac/atsaml22j/src/adc/result.rs new file mode 100644 index 000000000000..bd3b462d0d39 --- /dev/null +++ b/pac/atsaml22j/src/adc/result.rs @@ -0,0 +1,37 @@ +#[doc = "Register `RESULT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `RESULT` reader - Result Value"] +pub type RESULT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Result Value"] + #[inline(always)] + pub fn result(&self) -> RESULT_R { + RESULT_R::new(self.bits) + } +} +#[doc = "Result\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [result](index.html) module"] +pub struct RESULT_SPEC; +impl crate::RegisterSpec for RESULT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [result::R](R) reader structure"] +impl crate::Readable for RESULT_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RESULT to value 0"] +impl crate::Resettable for RESULT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/adc/sampctrl.rs b/pac/atsaml22j/src/adc/sampctrl.rs new file mode 100644 index 000000000000..b88d214e8d5e --- /dev/null +++ b/pac/atsaml22j/src/adc/sampctrl.rs @@ -0,0 +1,95 @@ +#[doc = "Register `SAMPCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SAMPCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SAMPLEN` reader - Sampling Time Length"] +pub type SAMPLEN_R = crate::FieldReader; +#[doc = "Field `SAMPLEN` writer - Sampling Time Length"] +pub type SAMPLEN_W<'a, const O: u8> = crate::FieldWriter<'a, u8, SAMPCTRL_SPEC, u8, u8, 6, O>; +#[doc = "Field `OFFCOMP` reader - Comparator Offset Compensation Enable"] +pub type OFFCOMP_R = crate::BitReader; +#[doc = "Field `OFFCOMP` writer - Comparator Offset Compensation Enable"] +pub type OFFCOMP_W<'a, const O: u8> = crate::BitWriter<'a, u8, SAMPCTRL_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:5 - Sampling Time Length"] + #[inline(always)] + pub fn samplen(&self) -> SAMPLEN_R { + SAMPLEN_R::new(self.bits & 0x3f) + } + #[doc = "Bit 7 - Comparator Offset Compensation Enable"] + #[inline(always)] + pub fn offcomp(&self) -> OFFCOMP_R { + OFFCOMP_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:5 - Sampling Time Length"] + #[inline(always)] + #[must_use] + pub fn samplen(&mut self) -> SAMPLEN_W<0> { + SAMPLEN_W::new(self) + } + #[doc = "Bit 7 - Comparator Offset Compensation Enable"] + #[inline(always)] + #[must_use] + pub fn offcomp(&mut self) -> OFFCOMP_W<7> { + OFFCOMP_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Sample Time Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sampctrl](index.html) module"] +pub struct SAMPCTRL_SPEC; +impl crate::RegisterSpec for SAMPCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [sampctrl::R](R) reader structure"] +impl crate::Readable for SAMPCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sampctrl::W](W) writer structure"] +impl crate::Writable for SAMPCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SAMPCTRL to value 0"] +impl crate::Resettable for SAMPCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/adc/seqctrl.rs b/pac/atsaml22j/src/adc/seqctrl.rs new file mode 100644 index 000000000000..671516c04556 --- /dev/null +++ b/pac/atsaml22j/src/adc/seqctrl.rs @@ -0,0 +1,80 @@ +#[doc = "Register `SEQCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SEQCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SEQEN` reader - Enable Positive Input in the Sequence"] +pub type SEQEN_R = crate::FieldReader; +#[doc = "Field `SEQEN` writer - Enable Positive Input in the Sequence"] +pub type SEQEN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SEQCTRL_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - Enable Positive Input in the Sequence"] + #[inline(always)] + pub fn seqen(&self) -> SEQEN_R { + SEQEN_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Enable Positive Input in the Sequence"] + #[inline(always)] + #[must_use] + pub fn seqen(&mut self) -> SEQEN_W<0> { + SEQEN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Sequence Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [seqctrl](index.html) module"] +pub struct SEQCTRL_SPEC; +impl crate::RegisterSpec for SEQCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [seqctrl::R](R) reader structure"] +impl crate::Readable for SEQCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [seqctrl::W](W) writer structure"] +impl crate::Writable for SEQCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SEQCTRL to value 0"] +impl crate::Resettable for SEQCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/adc/seqstatus.rs b/pac/atsaml22j/src/adc/seqstatus.rs new file mode 100644 index 000000000000..5f599db3bfd8 --- /dev/null +++ b/pac/atsaml22j/src/adc/seqstatus.rs @@ -0,0 +1,44 @@ +#[doc = "Register `SEQSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SEQSTATE` reader - Sequence State"] +pub type SEQSTATE_R = crate::FieldReader; +#[doc = "Field `SEQBUSY` reader - Sequence Busy"] +pub type SEQBUSY_R = crate::BitReader; +impl R { + #[doc = "Bits 0:4 - Sequence State"] + #[inline(always)] + pub fn seqstate(&self) -> SEQSTATE_R { + SEQSTATE_R::new(self.bits & 0x1f) + } + #[doc = "Bit 7 - Sequence Busy"] + #[inline(always)] + pub fn seqbusy(&self) -> SEQBUSY_R { + SEQBUSY_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[doc = "Sequence Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [seqstatus](index.html) module"] +pub struct SEQSTATUS_SPEC; +impl crate::RegisterSpec for SEQSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [seqstatus::R](R) reader structure"] +impl crate::Readable for SEQSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SEQSTATUS to value 0"] +impl crate::Resettable for SEQSTATUS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/adc/swtrig.rs b/pac/atsaml22j/src/adc/swtrig.rs new file mode 100644 index 000000000000..153ae0bbc09c --- /dev/null +++ b/pac/atsaml22j/src/adc/swtrig.rs @@ -0,0 +1,95 @@ +#[doc = "Register `SWTRIG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SWTRIG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FLUSH` reader - ADC Flush"] +pub type FLUSH_R = crate::BitReader; +#[doc = "Field `FLUSH` writer - ADC Flush"] +pub type FLUSH_W<'a, const O: u8> = crate::BitWriter<'a, u8, SWTRIG_SPEC, bool, O>; +#[doc = "Field `START` reader - Start ADC Conversion"] +pub type START_R = crate::BitReader; +#[doc = "Field `START` writer - Start ADC Conversion"] +pub type START_W<'a, const O: u8> = crate::BitWriter<'a, u8, SWTRIG_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - ADC Flush"] + #[inline(always)] + pub fn flush(&self) -> FLUSH_R { + FLUSH_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Start ADC Conversion"] + #[inline(always)] + pub fn start(&self) -> START_R { + START_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - ADC Flush"] + #[inline(always)] + #[must_use] + pub fn flush(&mut self) -> FLUSH_W<0> { + FLUSH_W::new(self) + } + #[doc = "Bit 1 - Start ADC Conversion"] + #[inline(always)] + #[must_use] + pub fn start(&mut self) -> START_W<1> { + START_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Software Trigger\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [swtrig](index.html) module"] +pub struct SWTRIG_SPEC; +impl crate::RegisterSpec for SWTRIG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [swtrig::R](R) reader structure"] +impl crate::Readable for SWTRIG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [swtrig::W](W) writer structure"] +impl crate::Writable for SWTRIG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SWTRIG to value 0"] +impl crate::Resettable for SWTRIG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/adc/syncbusy.rs b/pac/atsaml22j/src/adc/syncbusy.rs new file mode 100644 index 000000000000..c54bc2d78424 --- /dev/null +++ b/pac/atsaml22j/src/adc/syncbusy.rs @@ -0,0 +1,107 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - SWRST Synchronization Busy"] +pub type SWRST_R = crate::BitReader; +#[doc = "Field `ENABLE` reader - ENABLE Synchronization Busy"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `INPUTCTRL` reader - INPUTCTRL Synchronization Busy"] +pub type INPUTCTRL_R = crate::BitReader; +#[doc = "Field `CTRLC` reader - CTRLC Synchronization Busy"] +pub type CTRLC_R = crate::BitReader; +#[doc = "Field `AVGCTRL` reader - AVGCTRL Synchronization Busy"] +pub type AVGCTRL_R = crate::BitReader; +#[doc = "Field `SAMPCTRL` reader - SAMPCTRL Synchronization Busy"] +pub type SAMPCTRL_R = crate::BitReader; +#[doc = "Field `WINLT` reader - WINLT Synchronization Busy"] +pub type WINLT_R = crate::BitReader; +#[doc = "Field `WINUT` reader - WINUT Synchronization Busy"] +pub type WINUT_R = crate::BitReader; +#[doc = "Field `GAINCORR` reader - GAINCORR Synchronization Busy"] +pub type GAINCORR_R = crate::BitReader; +#[doc = "Field `OFFSETCORR` reader - OFFSETCTRL Synchronization Busy"] +pub type OFFSETCORR_R = crate::BitReader; +#[doc = "Field `SWTRIG` reader - SWTRG Synchronization Busy"] +pub type SWTRIG_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - SWRST Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - ENABLE Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - INPUTCTRL Synchronization Busy"] + #[inline(always)] + pub fn inputctrl(&self) -> INPUTCTRL_R { + INPUTCTRL_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - CTRLC Synchronization Busy"] + #[inline(always)] + pub fn ctrlc(&self) -> CTRLC_R { + CTRLC_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - AVGCTRL Synchronization Busy"] + #[inline(always)] + pub fn avgctrl(&self) -> AVGCTRL_R { + AVGCTRL_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - SAMPCTRL Synchronization Busy"] + #[inline(always)] + pub fn sampctrl(&self) -> SAMPCTRL_R { + SAMPCTRL_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - WINLT Synchronization Busy"] + #[inline(always)] + pub fn winlt(&self) -> WINLT_R { + WINLT_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - WINUT Synchronization Busy"] + #[inline(always)] + pub fn winut(&self) -> WINUT_R { + WINUT_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - GAINCORR Synchronization Busy"] + #[inline(always)] + pub fn gaincorr(&self) -> GAINCORR_R { + GAINCORR_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - OFFSETCTRL Synchronization Busy"] + #[inline(always)] + pub fn offsetcorr(&self) -> OFFSETCORR_R { + OFFSETCORR_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - SWTRG Synchronization Busy"] + #[inline(always)] + pub fn swtrig(&self) -> SWTRIG_R { + SWTRIG_R::new(((self.bits >> 10) & 1) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/adc/winlt.rs b/pac/atsaml22j/src/adc/winlt.rs new file mode 100644 index 000000000000..2f9731a3d1ec --- /dev/null +++ b/pac/atsaml22j/src/adc/winlt.rs @@ -0,0 +1,80 @@ +#[doc = "Register `WINLT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINLT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WINLT` reader - Window Lower Threshold"] +pub type WINLT_R = crate::FieldReader; +#[doc = "Field `WINLT` writer - Window Lower Threshold"] +pub type WINLT_W<'a, const O: u8> = crate::FieldWriter<'a, u16, WINLT_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - Window Lower Threshold"] + #[inline(always)] + pub fn winlt(&self) -> WINLT_R { + WINLT_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - Window Lower Threshold"] + #[inline(always)] + #[must_use] + pub fn winlt(&mut self) -> WINLT_W<0> { + WINLT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Monitor Lower Threshold\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winlt](index.html) module"] +pub struct WINLT_SPEC; +impl crate::RegisterSpec for WINLT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [winlt::R](R) reader structure"] +impl crate::Readable for WINLT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winlt::W](W) writer structure"] +impl crate::Writable for WINLT_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets WINLT to value 0"] +impl crate::Resettable for WINLT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/adc/winut.rs b/pac/atsaml22j/src/adc/winut.rs new file mode 100644 index 000000000000..1c1e04c4c063 --- /dev/null +++ b/pac/atsaml22j/src/adc/winut.rs @@ -0,0 +1,80 @@ +#[doc = "Register `WINUT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WINUT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WINUT` reader - Window Upper Threshold"] +pub type WINUT_R = crate::FieldReader; +#[doc = "Field `WINUT` writer - Window Upper Threshold"] +pub type WINUT_W<'a, const O: u8> = crate::FieldWriter<'a, u16, WINUT_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - Window Upper Threshold"] + #[inline(always)] + pub fn winut(&self) -> WINUT_R { + WINUT_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - Window Upper Threshold"] + #[inline(always)] + #[must_use] + pub fn winut(&mut self) -> WINUT_W<0> { + WINUT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Window Monitor Upper Threshold\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [winut](index.html) module"] +pub struct WINUT_SPEC; +impl crate::RegisterSpec for WINUT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [winut::R](R) reader structure"] +impl crate::Readable for WINUT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [winut::W](W) writer structure"] +impl crate::Writable for WINUT_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets WINUT to value 0"] +impl crate::Resettable for WINUT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/aes.rs b/pac/atsaml22j/src/aes.rs new file mode 100644 index 000000000000..9da8f1bf7b6c --- /dev/null +++ b/pac/atsaml22j/src/aes.rs @@ -0,0 +1,92 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: CTRLA, + #[doc = "0x04 - Control B"] + pub ctrlb: CTRLB, + #[doc = "0x05 - Interrupt Enable Clear"] + pub intenclr: INTENCLR, + #[doc = "0x06 - Interrupt Enable Set"] + pub intenset: INTENSET, + #[doc = "0x07 - Interrupt Flag Status"] + pub intflag: INTFLAG, + #[doc = "0x08 - Data buffer pointer"] + pub databufptr: DATABUFPTR, + #[doc = "0x09 - Debug control"] + pub dbgctrl: DBGCTRL, + _reserved7: [u8; 0x02], + #[doc = "0x0c..0x2c - Keyword n"] + pub keyword: [KEYWORD; 8], + _reserved8: [u8; 0x0c], + #[doc = "0x38 - Indata"] + pub indata: INDATA, + #[doc = "0x3c..0x4c - Initialisation Vector n"] + pub intvectv: [INTVECTV; 4], + _reserved10: [u8; 0x10], + #[doc = "0x5c..0x6c - Hash key n"] + pub hashkey: [HASHKEY; 4], + #[doc = "0x6c..0x7c - Galois Hash n"] + pub ghash: [GHASH; 4], + _reserved12: [u8; 0x04], + #[doc = "0x80 - Cipher Length"] + pub ciplen: CIPLEN, + #[doc = "0x84 - Random Seed"] + pub randseed: RANDSEED, +} +#[doc = "CTRLA (rw) register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLB (rw) register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B"] +pub mod ctrlb; +#[doc = "INTENCLR (rw) register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET (rw) register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG (rw) register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status"] +pub mod intflag; +#[doc = "DATABUFPTR (rw) register accessor: an alias for `Reg`"] +pub type DATABUFPTR = crate::Reg; +#[doc = "Data buffer pointer"] +pub mod databufptr; +#[doc = "DBGCTRL (w) register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug control"] +pub mod dbgctrl; +#[doc = "KEYWORD (w) register accessor: an alias for `Reg`"] +pub type KEYWORD = crate::Reg; +#[doc = "Keyword n"] +pub mod keyword; +#[doc = "INDATA (rw) register accessor: an alias for `Reg`"] +pub type INDATA = crate::Reg; +#[doc = "Indata"] +pub mod indata; +#[doc = "INTVECTV (w) register accessor: an alias for `Reg`"] +pub type INTVECTV = crate::Reg; +#[doc = "Initialisation Vector n"] +pub mod intvectv; +#[doc = "HASHKEY (rw) register accessor: an alias for `Reg`"] +pub type HASHKEY = crate::Reg; +#[doc = "Hash key n"] +pub mod hashkey; +#[doc = "GHASH (rw) register accessor: an alias for `Reg`"] +pub type GHASH = crate::Reg; +#[doc = "Galois Hash n"] +pub mod ghash; +#[doc = "CIPLEN (rw) register accessor: an alias for `Reg`"] +pub type CIPLEN = crate::Reg; +#[doc = "Cipher Length"] +pub mod ciplen; +#[doc = "RANDSEED (rw) register accessor: an alias for `Reg`"] +pub type RANDSEED = crate::Reg; +#[doc = "Random Seed"] +pub mod randseed; diff --git a/pac/atsaml22j/src/aes/ciplen.rs b/pac/atsaml22j/src/aes/ciplen.rs new file mode 100644 index 000000000000..90115d93e7b6 --- /dev/null +++ b/pac/atsaml22j/src/aes/ciplen.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CIPLEN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CIPLEN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Cipher Length\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ciplen](index.html) module"] +pub struct CIPLEN_SPEC; +impl crate::RegisterSpec for CIPLEN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ciplen::R](R) reader structure"] +impl crate::Readable for CIPLEN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ciplen::W](W) writer structure"] +impl crate::Writable for CIPLEN_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CIPLEN to value 0"] +impl crate::Resettable for CIPLEN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/aes/ctrla.rs b/pac/atsaml22j/src/aes/ctrla.rs new file mode 100644 index 000000000000..5c9531e5c1db --- /dev/null +++ b/pac/atsaml22j/src/aes/ctrla.rs @@ -0,0 +1,230 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub type SWRST_R = crate::BitReader; +#[doc = "Field `SWRST` writer - Software Reset"] +pub type SWRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `ENABLE` reader - Enable"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - Enable"] +pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `AESMODE` reader - AES Modes of operation"] +pub type AESMODE_R = crate::FieldReader; +#[doc = "Field `AESMODE` writer - AES Modes of operation"] +pub type AESMODE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRLA_SPEC, u8, u8, 3, O>; +#[doc = "Field `CFBS` reader - CFB Types"] +pub type CFBS_R = crate::FieldReader; +#[doc = "Field `CFBS` writer - CFB Types"] +pub type CFBS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRLA_SPEC, u8, u8, 3, O>; +#[doc = "Field `KEYSIZE` reader - Keysize"] +pub type KEYSIZE_R = crate::FieldReader; +#[doc = "Field `KEYSIZE` writer - Keysize"] +pub type KEYSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRLA_SPEC, u8, u8, 2, O>; +#[doc = "Field `CIPHER` reader - Cipher mode"] +pub type CIPHER_R = crate::BitReader; +#[doc = "Field `CIPHER` writer - Cipher mode"] +pub type CIPHER_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `STARTMODE` reader - Start mode"] +pub type STARTMODE_R = crate::BitReader; +#[doc = "Field `STARTMODE` writer - Start mode"] +pub type STARTMODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `LOD` reader - LOD Enable"] +pub type LOD_R = crate::BitReader; +#[doc = "Field `LOD` writer - LOD Enable"] +pub type LOD_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `KEYGEN` reader - Last key generation"] +pub type KEYGEN_R = crate::BitReader; +#[doc = "Field `KEYGEN` writer - Last key generation"] +pub type KEYGEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `XORKEY` reader - Xor Key operation"] +pub type XORKEY_R = crate::BitReader; +#[doc = "Field `XORKEY` writer - Xor Key operation"] +pub type XORKEY_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `CTYPE` reader - Counter measure types"] +pub type CTYPE_R = crate::FieldReader; +#[doc = "Field `CTYPE` writer - Counter measure types"] +pub type CTYPE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRLA_SPEC, u8, u8, 4, O>; +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:4 - AES Modes of operation"] + #[inline(always)] + pub fn aesmode(&self) -> AESMODE_R { + AESMODE_R::new(((self.bits >> 2) & 7) as u8) + } + #[doc = "Bits 5:7 - CFB Types"] + #[inline(always)] + pub fn cfbs(&self) -> CFBS_R { + CFBS_R::new(((self.bits >> 5) & 7) as u8) + } + #[doc = "Bits 8:9 - Keysize"] + #[inline(always)] + pub fn keysize(&self) -> KEYSIZE_R { + KEYSIZE_R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bit 10 - Cipher mode"] + #[inline(always)] + pub fn cipher(&self) -> CIPHER_R { + CIPHER_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Start mode"] + #[inline(always)] + pub fn startmode(&self) -> STARTMODE_R { + STARTMODE_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - LOD Enable"] + #[inline(always)] + pub fn lod(&self) -> LOD_R { + LOD_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Last key generation"] + #[inline(always)] + pub fn keygen(&self) -> KEYGEN_R { + KEYGEN_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Xor Key operation"] + #[inline(always)] + pub fn xorkey(&self) -> XORKEY_R { + XORKEY_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bits 16:19 - Counter measure types"] + #[inline(always)] + pub fn ctype(&self) -> CTYPE_R { + CTYPE_R::new(((self.bits >> 16) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + #[must_use] + pub fn swrst(&mut self) -> SWRST_W<0> { + SWRST_W::new(self) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W<1> { + ENABLE_W::new(self) + } + #[doc = "Bits 2:4 - AES Modes of operation"] + #[inline(always)] + #[must_use] + pub fn aesmode(&mut self) -> AESMODE_W<2> { + AESMODE_W::new(self) + } + #[doc = "Bits 5:7 - CFB Types"] + #[inline(always)] + #[must_use] + pub fn cfbs(&mut self) -> CFBS_W<5> { + CFBS_W::new(self) + } + #[doc = "Bits 8:9 - Keysize"] + #[inline(always)] + #[must_use] + pub fn keysize(&mut self) -> KEYSIZE_W<8> { + KEYSIZE_W::new(self) + } + #[doc = "Bit 10 - Cipher mode"] + #[inline(always)] + #[must_use] + pub fn cipher(&mut self) -> CIPHER_W<10> { + CIPHER_W::new(self) + } + #[doc = "Bit 11 - Start mode"] + #[inline(always)] + #[must_use] + pub fn startmode(&mut self) -> STARTMODE_W<11> { + STARTMODE_W::new(self) + } + #[doc = "Bit 12 - LOD Enable"] + #[inline(always)] + #[must_use] + pub fn lod(&mut self) -> LOD_W<12> { + LOD_W::new(self) + } + #[doc = "Bit 13 - Last key generation"] + #[inline(always)] + #[must_use] + pub fn keygen(&mut self) -> KEYGEN_W<13> { + KEYGEN_W::new(self) + } + #[doc = "Bit 14 - Xor Key operation"] + #[inline(always)] + #[must_use] + pub fn xorkey(&mut self) -> XORKEY_W<14> { + XORKEY_W::new(self) + } + #[doc = "Bits 16:19 - Counter measure types"] + #[inline(always)] + #[must_use] + pub fn ctype(&mut self) -> CTYPE_W<16> { + CTYPE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/aes/ctrlb.rs b/pac/atsaml22j/src/aes/ctrlb.rs new file mode 100644 index 000000000000..01704c9871a0 --- /dev/null +++ b/pac/atsaml22j/src/aes/ctrlb.rs @@ -0,0 +1,125 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `START` reader - Manual Start"] +pub type START_R = crate::BitReader; +#[doc = "Field `START` writer - Manual Start"] +pub type START_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLB_SPEC, bool, O>; +#[doc = "Field `NEWMSG` reader - New message"] +pub type NEWMSG_R = crate::BitReader; +#[doc = "Field `NEWMSG` writer - New message"] +pub type NEWMSG_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLB_SPEC, bool, O>; +#[doc = "Field `EOM` reader - End of message"] +pub type EOM_R = crate::BitReader; +#[doc = "Field `EOM` writer - End of message"] +pub type EOM_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLB_SPEC, bool, O>; +#[doc = "Field `GFMUL` reader - GF Multiplication"] +pub type GFMUL_R = crate::BitReader; +#[doc = "Field `GFMUL` writer - GF Multiplication"] +pub type GFMUL_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLB_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Manual Start"] + #[inline(always)] + pub fn start(&self) -> START_R { + START_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - New message"] + #[inline(always)] + pub fn newmsg(&self) -> NEWMSG_R { + NEWMSG_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - End of message"] + #[inline(always)] + pub fn eom(&self) -> EOM_R { + EOM_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - GF Multiplication"] + #[inline(always)] + pub fn gfmul(&self) -> GFMUL_R { + GFMUL_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Manual Start"] + #[inline(always)] + #[must_use] + pub fn start(&mut self) -> START_W<0> { + START_W::new(self) + } + #[doc = "Bit 1 - New message"] + #[inline(always)] + #[must_use] + pub fn newmsg(&mut self) -> NEWMSG_W<1> { + NEWMSG_W::new(self) + } + #[doc = "Bit 2 - End of message"] + #[inline(always)] + #[must_use] + pub fn eom(&mut self) -> EOM_W<2> { + EOM_W::new(self) + } + #[doc = "Bit 3 - GF Multiplication"] + #[inline(always)] + #[must_use] + pub fn gfmul(&mut self) -> GFMUL_W<3> { + GFMUL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/aes/databufptr.rs b/pac/atsaml22j/src/aes/databufptr.rs new file mode 100644 index 000000000000..aabd3adebbc7 --- /dev/null +++ b/pac/atsaml22j/src/aes/databufptr.rs @@ -0,0 +1,80 @@ +#[doc = "Register `DATABUFPTR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATABUFPTR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INDATAPTR` reader - Input Data Pointer"] +pub type INDATAPTR_R = crate::FieldReader; +#[doc = "Field `INDATAPTR` writer - Input Data Pointer"] +pub type INDATAPTR_W<'a, const O: u8> = crate::FieldWriter<'a, u8, DATABUFPTR_SPEC, u8, u8, 2, O>; +impl R { + #[doc = "Bits 0:1 - Input Data Pointer"] + #[inline(always)] + pub fn indataptr(&self) -> INDATAPTR_R { + INDATAPTR_R::new(self.bits & 3) + } +} +impl W { + #[doc = "Bits 0:1 - Input Data Pointer"] + #[inline(always)] + #[must_use] + pub fn indataptr(&mut self) -> INDATAPTR_W<0> { + INDATAPTR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data buffer pointer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [databufptr](index.html) module"] +pub struct DATABUFPTR_SPEC; +impl crate::RegisterSpec for DATABUFPTR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [databufptr::R](R) reader structure"] +impl crate::Readable for DATABUFPTR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [databufptr::W](W) writer structure"] +impl crate::Writable for DATABUFPTR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATABUFPTR to value 0"] +impl crate::Resettable for DATABUFPTR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/aes/dbgctrl.rs b/pac/atsaml22j/src/aes/dbgctrl.rs new file mode 100644 index 000000000000..7eabc9916c62 --- /dev/null +++ b/pac/atsaml22j/src/aes/dbgctrl.rs @@ -0,0 +1,52 @@ +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` writer - Debug Run"] +pub type DBGRUN_W<'a, const O: u8> = crate::BitWriter<'a, u8, DBGCTRL_SPEC, bool, O>; +impl W { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + #[must_use] + pub fn dbgrun(&mut self) -> DBGRUN_W<0> { + DBGRUN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug control\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/aes/ghash.rs b/pac/atsaml22j/src/aes/ghash.rs new file mode 100644 index 000000000000..8b31977b0556 --- /dev/null +++ b/pac/atsaml22j/src/aes/ghash.rs @@ -0,0 +1,63 @@ +#[doc = "Register `GHASH%s` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GHASH%s` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Galois Hash n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ghash](index.html) module"] +pub struct GHASH_SPEC; +impl crate::RegisterSpec for GHASH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ghash::R](R) reader structure"] +impl crate::Readable for GHASH_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ghash::W](W) writer structure"] +impl crate::Writable for GHASH_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GHASH%s to value 0"] +impl crate::Resettable for GHASH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/aes/hashkey.rs b/pac/atsaml22j/src/aes/hashkey.rs new file mode 100644 index 000000000000..e5d6df52702e --- /dev/null +++ b/pac/atsaml22j/src/aes/hashkey.rs @@ -0,0 +1,63 @@ +#[doc = "Register `HASHKEY%s` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `HASHKEY%s` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Hash key n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [hashkey](index.html) module"] +pub struct HASHKEY_SPEC; +impl crate::RegisterSpec for HASHKEY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [hashkey::R](R) reader structure"] +impl crate::Readable for HASHKEY_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [hashkey::W](W) writer structure"] +impl crate::Writable for HASHKEY_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets HASHKEY%s to value 0"] +impl crate::Resettable for HASHKEY_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/aes/indata.rs b/pac/atsaml22j/src/aes/indata.rs new file mode 100644 index 000000000000..d2db11a9e400 --- /dev/null +++ b/pac/atsaml22j/src/aes/indata.rs @@ -0,0 +1,63 @@ +#[doc = "Register `INDATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INDATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Indata\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [indata](index.html) module"] +pub struct INDATA_SPEC; +impl crate::RegisterSpec for INDATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [indata::R](R) reader structure"] +impl crate::Readable for INDATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [indata::W](W) writer structure"] +impl crate::Writable for INDATA_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INDATA to value 0"] +impl crate::Resettable for INDATA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/aes/intenclr.rs b/pac/atsaml22j/src/aes/intenclr.rs new file mode 100644 index 000000000000..31e443ab01b8 --- /dev/null +++ b/pac/atsaml22j/src/aes/intenclr.rs @@ -0,0 +1,95 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENCCMP` reader - Encryption Complete"] +pub type ENCCMP_R = crate::BitReader; +#[doc = "Field `ENCCMP` writer - Encryption Complete"] +pub type ENCCMP_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>; +#[doc = "Field `GFMCMP` reader - GF Multiplication Complete"] +pub type GFMCMP_R = crate::BitReader; +#[doc = "Field `GFMCMP` writer - GF Multiplication Complete"] +pub type GFMCMP_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Encryption Complete"] + #[inline(always)] + pub fn enccmp(&self) -> ENCCMP_R { + ENCCMP_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - GF Multiplication Complete"] + #[inline(always)] + pub fn gfmcmp(&self) -> GFMCMP_R { + GFMCMP_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Encryption Complete"] + #[inline(always)] + #[must_use] + pub fn enccmp(&mut self) -> ENCCMP_W<0> { + ENCCMP_W::new(self) + } + #[doc = "Bit 1 - GF Multiplication Complete"] + #[inline(always)] + #[must_use] + pub fn gfmcmp(&mut self) -> GFMCMP_W<1> { + GFMCMP_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/aes/intenset.rs b/pac/atsaml22j/src/aes/intenset.rs new file mode 100644 index 000000000000..880a73c7188c --- /dev/null +++ b/pac/atsaml22j/src/aes/intenset.rs @@ -0,0 +1,95 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENCCMP` reader - Encryption Complete"] +pub type ENCCMP_R = crate::BitReader; +#[doc = "Field `ENCCMP` writer - Encryption Complete"] +pub type ENCCMP_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENSET_SPEC, bool, O>; +#[doc = "Field `GFMCMP` reader - GF Multiplication Complete"] +pub type GFMCMP_R = crate::BitReader; +#[doc = "Field `GFMCMP` writer - GF Multiplication Complete"] +pub type GFMCMP_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENSET_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Encryption Complete"] + #[inline(always)] + pub fn enccmp(&self) -> ENCCMP_R { + ENCCMP_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - GF Multiplication Complete"] + #[inline(always)] + pub fn gfmcmp(&self) -> GFMCMP_R { + GFMCMP_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Encryption Complete"] + #[inline(always)] + #[must_use] + pub fn enccmp(&mut self) -> ENCCMP_W<0> { + ENCCMP_W::new(self) + } + #[doc = "Bit 1 - GF Multiplication Complete"] + #[inline(always)] + #[must_use] + pub fn gfmcmp(&mut self) -> GFMCMP_W<1> { + GFMCMP_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/aes/intflag.rs b/pac/atsaml22j/src/aes/intflag.rs new file mode 100644 index 000000000000..24d9b8b42ea6 --- /dev/null +++ b/pac/atsaml22j/src/aes/intflag.rs @@ -0,0 +1,95 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENCCMP` reader - Encryption Complete"] +pub type ENCCMP_R = crate::BitReader; +#[doc = "Field `ENCCMP` writer - Encryption Complete"] +pub type ENCCMP_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTFLAG_SPEC, bool, O>; +#[doc = "Field `GFMCMP` reader - GF Multiplication Complete"] +pub type GFMCMP_R = crate::BitReader; +#[doc = "Field `GFMCMP` writer - GF Multiplication Complete"] +pub type GFMCMP_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTFLAG_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Encryption Complete"] + #[inline(always)] + pub fn enccmp(&self) -> ENCCMP_R { + ENCCMP_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - GF Multiplication Complete"] + #[inline(always)] + pub fn gfmcmp(&self) -> GFMCMP_R { + GFMCMP_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Encryption Complete"] + #[inline(always)] + #[must_use] + pub fn enccmp(&mut self) -> ENCCMP_W<0> { + ENCCMP_W::new(self) + } + #[doc = "Bit 1 - GF Multiplication Complete"] + #[inline(always)] + #[must_use] + pub fn gfmcmp(&mut self) -> GFMCMP_W<1> { + GFMCMP_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/aes/intvectv.rs b/pac/atsaml22j/src/aes/intvectv.rs new file mode 100644 index 000000000000..ac073433169b --- /dev/null +++ b/pac/atsaml22j/src/aes/intvectv.rs @@ -0,0 +1,44 @@ +#[doc = "Register `INTVECTV%s` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Initialisation Vector n\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intvectv](index.html) module"] +pub struct INTVECTV_SPEC; +impl crate::RegisterSpec for INTVECTV_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [intvectv::W](W) writer structure"] +impl crate::Writable for INTVECTV_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTVECTV%s to value 0"] +impl crate::Resettable for INTVECTV_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/aes/keyword.rs b/pac/atsaml22j/src/aes/keyword.rs new file mode 100644 index 000000000000..6e2c84251215 --- /dev/null +++ b/pac/atsaml22j/src/aes/keyword.rs @@ -0,0 +1,44 @@ +#[doc = "Register `KEYWORD%s` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Keyword n\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [keyword](index.html) module"] +pub struct KEYWORD_SPEC; +impl crate::RegisterSpec for KEYWORD_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [keyword::W](W) writer structure"] +impl crate::Writable for KEYWORD_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets KEYWORD%s to value 0"] +impl crate::Resettable for KEYWORD_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/aes/randseed.rs b/pac/atsaml22j/src/aes/randseed.rs new file mode 100644 index 000000000000..643bd694ad99 --- /dev/null +++ b/pac/atsaml22j/src/aes/randseed.rs @@ -0,0 +1,63 @@ +#[doc = "Register `RANDSEED` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RANDSEED` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Random Seed\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [randseed](index.html) module"] +pub struct RANDSEED_SPEC; +impl crate::RegisterSpec for RANDSEED_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [randseed::R](R) reader structure"] +impl crate::Readable for RANDSEED_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [randseed::W](W) writer structure"] +impl crate::Writable for RANDSEED_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RANDSEED to value 0"] +impl crate::Resettable for RANDSEED_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/ccl.rs b/pac/atsaml22j/src/ccl.rs new file mode 100644 index 000000000000..f9f1de9aa2b3 --- /dev/null +++ b/pac/atsaml22j/src/ccl.rs @@ -0,0 +1,24 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrl: CTRL, + _reserved1: [u8; 0x03], + #[doc = "0x04 - SEQ Control x"] + pub seqctrl: [SEQCTRL; 2], + _reserved2: [u8; 0x02], + #[doc = "0x08..0x18 - LUT Control x"] + pub lutctrl: [LUTCTRL; 4], +} +#[doc = "CTRL (rw) register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "SEQCTRL (rw) register accessor: an alias for `Reg`"] +pub type SEQCTRL = crate::Reg; +#[doc = "SEQ Control x"] +pub mod seqctrl; +#[doc = "LUTCTRL (rw) register accessor: an alias for `Reg`"] +pub type LUTCTRL = crate::Reg; +#[doc = "LUT Control x"] +pub mod lutctrl; diff --git a/pac/atsaml22j/src/ccl/ctrl.rs b/pac/atsaml22j/src/ccl/ctrl.rs new file mode 100644 index 000000000000..12cb63ffcf1e --- /dev/null +++ b/pac/atsaml22j/src/ccl/ctrl.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub type SWRST_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRL_SPEC, bool, O>; +#[doc = "Field `ENABLE` reader - Enable"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - Enable"] +pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRL_SPEC, bool, O>; +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub type RUNSTDBY_R = crate::BitReader; +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub type RUNSTDBY_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRL_SPEC, bool, O>; +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + #[must_use] + pub fn swrst(&mut self) -> SWRST_W<0> { + SWRST_W::new(self) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W<1> { + ENABLE_W::new(self) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + #[must_use] + pub fn runstdby(&mut self) -> RUNSTDBY_W<6> { + RUNSTDBY_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/ccl/lutctrl.rs b/pac/atsaml22j/src/ccl/lutctrl.rs new file mode 100644 index 000000000000..e35f3194feea --- /dev/null +++ b/pac/atsaml22j/src/ccl/lutctrl.rs @@ -0,0 +1,430 @@ +#[doc = "Register `LUTCTRL%s` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LUTCTRL%s` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - LUT Enable"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - LUT Enable"] +pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, LUTCTRL_SPEC, bool, O>; +#[doc = "Field `FILTSEL` reader - Filter Selection"] +pub type FILTSEL_R = crate::FieldReader; +#[doc = "Filter Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FILTSELSELECT_A { + #[doc = "0: Filter disabled"] + DISABLE = 0, + #[doc = "1: Synchronizer enabled"] + SYNCH = 1, + #[doc = "2: Filter enabled"] + FILTER = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FILTSELSELECT_A) -> Self { + variant as _ + } +} +impl FILTSEL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FILTSELSELECT_A::DISABLE), + 1 => Some(FILTSELSELECT_A::SYNCH), + 2 => Some(FILTSELSELECT_A::FILTER), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == FILTSELSELECT_A::DISABLE + } + #[doc = "Checks if the value of the field is `SYNCH`"] + #[inline(always)] + pub fn is_synch(&self) -> bool { + *self == FILTSELSELECT_A::SYNCH + } + #[doc = "Checks if the value of the field is `FILTER`"] + #[inline(always)] + pub fn is_filter(&self) -> bool { + *self == FILTSELSELECT_A::FILTER + } +} +#[doc = "Field `FILTSEL` writer - Filter Selection"] +pub type FILTSEL_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, LUTCTRL_SPEC, u8, FILTSELSELECT_A, 2, O>; +impl<'a, const O: u8> FILTSEL_W<'a, O> { + #[doc = "Filter disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(FILTSELSELECT_A::DISABLE) + } + #[doc = "Synchronizer enabled"] + #[inline(always)] + pub fn synch(self) -> &'a mut W { + self.variant(FILTSELSELECT_A::SYNCH) + } + #[doc = "Filter enabled"] + #[inline(always)] + pub fn filter(self) -> &'a mut W { + self.variant(FILTSELSELECT_A::FILTER) + } +} +#[doc = "Field `EDGESEL` reader - Edge Selection"] +pub type EDGESEL_R = crate::BitReader; +#[doc = "Field `EDGESEL` writer - Edge Selection"] +pub type EDGESEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, LUTCTRL_SPEC, bool, O>; +#[doc = "Field `INSEL0` reader - Input Selection 0"] +pub type INSEL0_R = crate::FieldReader; +#[doc = "Input Selection 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum INSEL0SELECT_A { + #[doc = "0: Masked input"] + MASK = 0, + #[doc = "1: Feedback input source"] + FEEDBACK = 1, + #[doc = "2: Linked LUT input source"] + LINK = 2, + #[doc = "3: Event in put source"] + EVENT = 3, + #[doc = "4: I/O pin input source"] + IO = 4, + #[doc = "5: AC input source"] + AC = 5, + #[doc = "6: TC input source"] + TC = 6, + #[doc = "7: Alternate TC input source"] + ALTTC = 7, + #[doc = "8: TCC input source"] + TCC = 8, + #[doc = "9: SERCOM inout source"] + SERCOM = 9, +} +impl From for u8 { + #[inline(always)] + fn from(variant: INSEL0SELECT_A) -> Self { + variant as _ + } +} +impl INSEL0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(INSEL0SELECT_A::MASK), + 1 => Some(INSEL0SELECT_A::FEEDBACK), + 2 => Some(INSEL0SELECT_A::LINK), + 3 => Some(INSEL0SELECT_A::EVENT), + 4 => Some(INSEL0SELECT_A::IO), + 5 => Some(INSEL0SELECT_A::AC), + 6 => Some(INSEL0SELECT_A::TC), + 7 => Some(INSEL0SELECT_A::ALTTC), + 8 => Some(INSEL0SELECT_A::TCC), + 9 => Some(INSEL0SELECT_A::SERCOM), + _ => None, + } + } + #[doc = "Checks if the value of the field is `MASK`"] + #[inline(always)] + pub fn is_mask(&self) -> bool { + *self == INSEL0SELECT_A::MASK + } + #[doc = "Checks if the value of the field is `FEEDBACK`"] + #[inline(always)] + pub fn is_feedback(&self) -> bool { + *self == INSEL0SELECT_A::FEEDBACK + } + #[doc = "Checks if the value of the field is `LINK`"] + #[inline(always)] + pub fn is_link(&self) -> bool { + *self == INSEL0SELECT_A::LINK + } + #[doc = "Checks if the value of the field is `EVENT`"] + #[inline(always)] + pub fn is_event(&self) -> bool { + *self == INSEL0SELECT_A::EVENT + } + #[doc = "Checks if the value of the field is `IO`"] + #[inline(always)] + pub fn is_io(&self) -> bool { + *self == INSEL0SELECT_A::IO + } + #[doc = "Checks if the value of the field is `AC`"] + #[inline(always)] + pub fn is_ac(&self) -> bool { + *self == INSEL0SELECT_A::AC + } + #[doc = "Checks if the value of the field is `TC`"] + #[inline(always)] + pub fn is_tc(&self) -> bool { + *self == INSEL0SELECT_A::TC + } + #[doc = "Checks if the value of the field is `ALTTC`"] + #[inline(always)] + pub fn is_alttc(&self) -> bool { + *self == INSEL0SELECT_A::ALTTC + } + #[doc = "Checks if the value of the field is `TCC`"] + #[inline(always)] + pub fn is_tcc(&self) -> bool { + *self == INSEL0SELECT_A::TCC + } + #[doc = "Checks if the value of the field is `SERCOM`"] + #[inline(always)] + pub fn is_sercom(&self) -> bool { + *self == INSEL0SELECT_A::SERCOM + } +} +#[doc = "Field `INSEL0` writer - Input Selection 0"] +pub type INSEL0_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, LUTCTRL_SPEC, u8, INSEL0SELECT_A, 4, O>; +impl<'a, const O: u8> INSEL0_W<'a, O> { + #[doc = "Masked input"] + #[inline(always)] + pub fn mask(self) -> &'a mut W { + self.variant(INSEL0SELECT_A::MASK) + } + #[doc = "Feedback input source"] + #[inline(always)] + pub fn feedback(self) -> &'a mut W { + self.variant(INSEL0SELECT_A::FEEDBACK) + } + #[doc = "Linked LUT input source"] + #[inline(always)] + pub fn link(self) -> &'a mut W { + self.variant(INSEL0SELECT_A::LINK) + } + #[doc = "Event in put source"] + #[inline(always)] + pub fn event(self) -> &'a mut W { + self.variant(INSEL0SELECT_A::EVENT) + } + #[doc = "I/O pin input source"] + #[inline(always)] + pub fn io(self) -> &'a mut W { + self.variant(INSEL0SELECT_A::IO) + } + #[doc = "AC input source"] + #[inline(always)] + pub fn ac(self) -> &'a mut W { + self.variant(INSEL0SELECT_A::AC) + } + #[doc = "TC input source"] + #[inline(always)] + pub fn tc(self) -> &'a mut W { + self.variant(INSEL0SELECT_A::TC) + } + #[doc = "Alternate TC input source"] + #[inline(always)] + pub fn alttc(self) -> &'a mut W { + self.variant(INSEL0SELECT_A::ALTTC) + } + #[doc = "TCC input source"] + #[inline(always)] + pub fn tcc(self) -> &'a mut W { + self.variant(INSEL0SELECT_A::TCC) + } + #[doc = "SERCOM inout source"] + #[inline(always)] + pub fn sercom(self) -> &'a mut W { + self.variant(INSEL0SELECT_A::SERCOM) + } +} +#[doc = "Field `INSEL1` reader - Input Selection 1"] +pub type INSEL1_R = crate::FieldReader; +#[doc = "Field `INSEL1` writer - Input Selection 1"] +pub type INSEL1_W<'a, const O: u8> = crate::FieldWriter<'a, u32, LUTCTRL_SPEC, u8, u8, 4, O>; +#[doc = "Field `INSEL2` reader - Input Selection 2"] +pub type INSEL2_R = crate::FieldReader; +#[doc = "Field `INSEL2` writer - Input Selection 2"] +pub type INSEL2_W<'a, const O: u8> = crate::FieldWriter<'a, u32, LUTCTRL_SPEC, u8, u8, 4, O>; +#[doc = "Field `INVEI` reader - Input Event Invert"] +pub type INVEI_R = crate::BitReader; +#[doc = "Field `INVEI` writer - Input Event Invert"] +pub type INVEI_W<'a, const O: u8> = crate::BitWriter<'a, u32, LUTCTRL_SPEC, bool, O>; +#[doc = "Field `LUTEI` reader - Event Input Enable"] +pub type LUTEI_R = crate::BitReader; +#[doc = "Field `LUTEI` writer - Event Input Enable"] +pub type LUTEI_W<'a, const O: u8> = crate::BitWriter<'a, u32, LUTCTRL_SPEC, bool, O>; +#[doc = "Field `LUTEO` reader - Event Output Enable"] +pub type LUTEO_R = crate::BitReader; +#[doc = "Field `LUTEO` writer - Event Output Enable"] +pub type LUTEO_W<'a, const O: u8> = crate::BitWriter<'a, u32, LUTCTRL_SPEC, bool, O>; +#[doc = "Field `TRUTH` reader - Truth Value"] +pub type TRUTH_R = crate::FieldReader; +#[doc = "Field `TRUTH` writer - Truth Value"] +pub type TRUTH_W<'a, const O: u8> = crate::FieldWriter<'a, u32, LUTCTRL_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bit 1 - LUT Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 4:5 - Filter Selection"] + #[inline(always)] + pub fn filtsel(&self) -> FILTSEL_R { + FILTSEL_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 7 - Edge Selection"] + #[inline(always)] + pub fn edgesel(&self) -> EDGESEL_R { + EDGESEL_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:11 - Input Selection 0"] + #[inline(always)] + pub fn insel0(&self) -> INSEL0_R { + INSEL0_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Input Selection 1"] + #[inline(always)] + pub fn insel1(&self) -> INSEL1_R { + INSEL1_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:19 - Input Selection 2"] + #[inline(always)] + pub fn insel2(&self) -> INSEL2_R { + INSEL2_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 20 - Input Event Invert"] + #[inline(always)] + pub fn invei(&self) -> INVEI_R { + INVEI_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Event Input Enable"] + #[inline(always)] + pub fn lutei(&self) -> LUTEI_R { + LUTEI_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Event Output Enable"] + #[inline(always)] + pub fn luteo(&self) -> LUTEO_R { + LUTEO_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bits 24:31 - Truth Value"] + #[inline(always)] + pub fn truth(&self) -> TRUTH_R { + TRUTH_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bit 1 - LUT Enable"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W<1> { + ENABLE_W::new(self) + } + #[doc = "Bits 4:5 - Filter Selection"] + #[inline(always)] + #[must_use] + pub fn filtsel(&mut self) -> FILTSEL_W<4> { + FILTSEL_W::new(self) + } + #[doc = "Bit 7 - Edge Selection"] + #[inline(always)] + #[must_use] + pub fn edgesel(&mut self) -> EDGESEL_W<7> { + EDGESEL_W::new(self) + } + #[doc = "Bits 8:11 - Input Selection 0"] + #[inline(always)] + #[must_use] + pub fn insel0(&mut self) -> INSEL0_W<8> { + INSEL0_W::new(self) + } + #[doc = "Bits 12:15 - Input Selection 1"] + #[inline(always)] + #[must_use] + pub fn insel1(&mut self) -> INSEL1_W<12> { + INSEL1_W::new(self) + } + #[doc = "Bits 16:19 - Input Selection 2"] + #[inline(always)] + #[must_use] + pub fn insel2(&mut self) -> INSEL2_W<16> { + INSEL2_W::new(self) + } + #[doc = "Bit 20 - Input Event Invert"] + #[inline(always)] + #[must_use] + pub fn invei(&mut self) -> INVEI_W<20> { + INVEI_W::new(self) + } + #[doc = "Bit 21 - Event Input Enable"] + #[inline(always)] + #[must_use] + pub fn lutei(&mut self) -> LUTEI_W<21> { + LUTEI_W::new(self) + } + #[doc = "Bit 22 - Event Output Enable"] + #[inline(always)] + #[must_use] + pub fn luteo(&mut self) -> LUTEO_W<22> { + LUTEO_W::new(self) + } + #[doc = "Bits 24:31 - Truth Value"] + #[inline(always)] + #[must_use] + pub fn truth(&mut self) -> TRUTH_W<24> { + TRUTH_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "LUT Control x\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lutctrl](index.html) module"] +pub struct LUTCTRL_SPEC; +impl crate::RegisterSpec for LUTCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [lutctrl::R](R) reader structure"] +impl crate::Readable for LUTCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [lutctrl::W](W) writer structure"] +impl crate::Writable for LUTCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LUTCTRL%s to value 0"] +impl crate::Resettable for LUTCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/ccl/seqctrl.rs b/pac/atsaml22j/src/ccl/seqctrl.rs new file mode 100644 index 000000000000..c3d9e7795e1c --- /dev/null +++ b/pac/atsaml22j/src/ccl/seqctrl.rs @@ -0,0 +1,168 @@ +#[doc = "Register `SEQCTRL%s` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SEQCTRL%s` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SEQSEL` reader - Sequential Selection"] +pub type SEQSEL_R = crate::FieldReader; +#[doc = "Sequential Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SEQSELSELECT_A { + #[doc = "0: Sequential logic is disabled"] + DISABLE = 0, + #[doc = "1: D flip flop"] + DFF = 1, + #[doc = "2: JK flip flop"] + JK = 2, + #[doc = "3: D latch"] + LATCH = 3, + #[doc = "4: RS latch"] + RS = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SEQSELSELECT_A) -> Self { + variant as _ + } +} +impl SEQSEL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SEQSELSELECT_A::DISABLE), + 1 => Some(SEQSELSELECT_A::DFF), + 2 => Some(SEQSELSELECT_A::JK), + 3 => Some(SEQSELSELECT_A::LATCH), + 4 => Some(SEQSELSELECT_A::RS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == SEQSELSELECT_A::DISABLE + } + #[doc = "Checks if the value of the field is `DFF`"] + #[inline(always)] + pub fn is_dff(&self) -> bool { + *self == SEQSELSELECT_A::DFF + } + #[doc = "Checks if the value of the field is `JK`"] + #[inline(always)] + pub fn is_jk(&self) -> bool { + *self == SEQSELSELECT_A::JK + } + #[doc = "Checks if the value of the field is `LATCH`"] + #[inline(always)] + pub fn is_latch(&self) -> bool { + *self == SEQSELSELECT_A::LATCH + } + #[doc = "Checks if the value of the field is `RS`"] + #[inline(always)] + pub fn is_rs(&self) -> bool { + *self == SEQSELSELECT_A::RS + } +} +#[doc = "Field `SEQSEL` writer - Sequential Selection"] +pub type SEQSEL_W<'a, const O: u8> = + crate::FieldWriter<'a, u8, SEQCTRL_SPEC, u8, SEQSELSELECT_A, 4, O>; +impl<'a, const O: u8> SEQSEL_W<'a, O> { + #[doc = "Sequential logic is disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(SEQSELSELECT_A::DISABLE) + } + #[doc = "D flip flop"] + #[inline(always)] + pub fn dff(self) -> &'a mut W { + self.variant(SEQSELSELECT_A::DFF) + } + #[doc = "JK flip flop"] + #[inline(always)] + pub fn jk(self) -> &'a mut W { + self.variant(SEQSELSELECT_A::JK) + } + #[doc = "D latch"] + #[inline(always)] + pub fn latch(self) -> &'a mut W { + self.variant(SEQSELSELECT_A::LATCH) + } + #[doc = "RS latch"] + #[inline(always)] + pub fn rs(self) -> &'a mut W { + self.variant(SEQSELSELECT_A::RS) + } +} +impl R { + #[doc = "Bits 0:3 - Sequential Selection"] + #[inline(always)] + pub fn seqsel(&self) -> SEQSEL_R { + SEQSEL_R::new(self.bits & 0x0f) + } +} +impl W { + #[doc = "Bits 0:3 - Sequential Selection"] + #[inline(always)] + #[must_use] + pub fn seqsel(&mut self) -> SEQSEL_W<0> { + SEQSEL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SEQ Control x\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [seqctrl](index.html) module"] +pub struct SEQCTRL_SPEC; +impl crate::RegisterSpec for SEQCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [seqctrl::R](R) reader structure"] +impl crate::Readable for SEQCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [seqctrl::W](W) writer structure"] +impl crate::Writable for SEQCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SEQCTRL%s to value 0"] +impl crate::Resettable for SEQCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/dmac.rs b/pac/atsaml22j/src/dmac.rs new file mode 100644 index 000000000000..a7e466eca34c --- /dev/null +++ b/pac/atsaml22j/src/dmac.rs @@ -0,0 +1,148 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrl: CTRL, + #[doc = "0x02 - CRC Control"] + pub crcctrl: CRCCTRL, + #[doc = "0x04 - CRC Data Input"] + pub crcdatain: CRCDATAIN, + #[doc = "0x08 - CRC Checksum"] + pub crcchksum: CRCCHKSUM, + #[doc = "0x0c - CRC Status"] + pub crcstatus: CRCSTATUS, + #[doc = "0x0d - Debug Control"] + pub dbgctrl: DBGCTRL, + #[doc = "0x0e - QOS Control"] + pub qosctrl: QOSCTRL, + _reserved7: [u8; 0x01], + #[doc = "0x10 - Software Trigger Control"] + pub swtrigctrl: SWTRIGCTRL, + #[doc = "0x14 - Priority Control 0"] + pub prictrl0: PRICTRL0, + _reserved9: [u8; 0x08], + #[doc = "0x20 - Interrupt Pending"] + pub intpend: INTPEND, + _reserved10: [u8; 0x02], + #[doc = "0x24 - Interrupt Status"] + pub intstatus: INTSTATUS, + #[doc = "0x28 - Busy Channels"] + pub busych: BUSYCH, + #[doc = "0x2c - Pending Channels"] + pub pendch: PENDCH, + #[doc = "0x30 - Active Channel and Levels"] + pub active: ACTIVE, + #[doc = "0x34 - Descriptor Memory Section Base Address"] + pub baseaddr: BASEADDR, + #[doc = "0x38 - Write-Back Memory Section Base Address"] + pub wrbaddr: WRBADDR, + _reserved16: [u8; 0x03], + #[doc = "0x3f - Channel ID"] + pub chid: CHID, + #[doc = "0x40 - Channel Control A"] + pub chctrla: CHCTRLA, + _reserved18: [u8; 0x03], + #[doc = "0x44 - Channel Control B"] + pub chctrlb: CHCTRLB, + _reserved19: [u8; 0x04], + #[doc = "0x4c - Channel Interrupt Enable Clear"] + pub chintenclr: CHINTENCLR, + #[doc = "0x4d - Channel Interrupt Enable Set"] + pub chintenset: CHINTENSET, + #[doc = "0x4e - Channel Interrupt Flag Status and Clear"] + pub chintflag: CHINTFLAG, + #[doc = "0x4f - Channel Status"] + pub chstatus: CHSTATUS, +} +#[doc = "CTRL (rw) register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "CRCCTRL (rw) register accessor: an alias for `Reg`"] +pub type CRCCTRL = crate::Reg; +#[doc = "CRC Control"] +pub mod crcctrl; +#[doc = "CRCDATAIN (rw) register accessor: an alias for `Reg`"] +pub type CRCDATAIN = crate::Reg; +#[doc = "CRC Data Input"] +pub mod crcdatain; +#[doc = "CRCCHKSUM (rw) register accessor: an alias for `Reg`"] +pub type CRCCHKSUM = crate::Reg; +#[doc = "CRC Checksum"] +pub mod crcchksum; +#[doc = "CRCSTATUS (rw) register accessor: an alias for `Reg`"] +pub type CRCSTATUS = crate::Reg; +#[doc = "CRC Status"] +pub mod crcstatus; +#[doc = "DBGCTRL (rw) register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "QOSCTRL (rw) register accessor: an alias for `Reg`"] +pub type QOSCTRL = crate::Reg; +#[doc = "QOS Control"] +pub mod qosctrl; +#[doc = "SWTRIGCTRL (rw) register accessor: an alias for `Reg`"] +pub type SWTRIGCTRL = crate::Reg; +#[doc = "Software Trigger Control"] +pub mod swtrigctrl; +#[doc = "PRICTRL0 (rw) register accessor: an alias for `Reg`"] +pub type PRICTRL0 = crate::Reg; +#[doc = "Priority Control 0"] +pub mod prictrl0; +#[doc = "INTPEND (rw) register accessor: an alias for `Reg`"] +pub type INTPEND = crate::Reg; +#[doc = "Interrupt Pending"] +pub mod intpend; +#[doc = "INTSTATUS (r) register accessor: an alias for `Reg`"] +pub type INTSTATUS = crate::Reg; +#[doc = "Interrupt Status"] +pub mod intstatus; +#[doc = "BUSYCH (r) register accessor: an alias for `Reg`"] +pub type BUSYCH = crate::Reg; +#[doc = "Busy Channels"] +pub mod busych; +#[doc = "PENDCH (r) register accessor: an alias for `Reg`"] +pub type PENDCH = crate::Reg; +#[doc = "Pending Channels"] +pub mod pendch; +#[doc = "ACTIVE (r) register accessor: an alias for `Reg`"] +pub type ACTIVE = crate::Reg; +#[doc = "Active Channel and Levels"] +pub mod active; +#[doc = "BASEADDR (rw) register accessor: an alias for `Reg`"] +pub type BASEADDR = crate::Reg; +#[doc = "Descriptor Memory Section Base Address"] +pub mod baseaddr; +#[doc = "WRBADDR (rw) register accessor: an alias for `Reg`"] +pub type WRBADDR = crate::Reg; +#[doc = "Write-Back Memory Section Base Address"] +pub mod wrbaddr; +#[doc = "CHID (rw) register accessor: an alias for `Reg`"] +pub type CHID = crate::Reg; +#[doc = "Channel ID"] +pub mod chid; +#[doc = "CHCTRLA (rw) register accessor: an alias for `Reg`"] +pub type CHCTRLA = crate::Reg; +#[doc = "Channel Control A"] +pub mod chctrla; +#[doc = "CHCTRLB (rw) register accessor: an alias for `Reg`"] +pub type CHCTRLB = crate::Reg; +#[doc = "Channel Control B"] +pub mod chctrlb; +#[doc = "CHINTENCLR (rw) register accessor: an alias for `Reg`"] +pub type CHINTENCLR = crate::Reg; +#[doc = "Channel Interrupt Enable Clear"] +pub mod chintenclr; +#[doc = "CHINTENSET (rw) register accessor: an alias for `Reg`"] +pub type CHINTENSET = crate::Reg; +#[doc = "Channel Interrupt Enable Set"] +pub mod chintenset; +#[doc = "CHINTFLAG (rw) register accessor: an alias for `Reg`"] +pub type CHINTFLAG = crate::Reg; +#[doc = "Channel Interrupt Flag Status and Clear"] +pub mod chintflag; +#[doc = "CHSTATUS (r) register accessor: an alias for `Reg`"] +pub type CHSTATUS = crate::Reg; +#[doc = "Channel Status"] +pub mod chstatus; diff --git a/pac/atsaml22j/src/dmac/active.rs b/pac/atsaml22j/src/dmac/active.rs new file mode 100644 index 000000000000..af2a840be67b --- /dev/null +++ b/pac/atsaml22j/src/dmac/active.rs @@ -0,0 +1,79 @@ +#[doc = "Register `ACTIVE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `LVLEX0` reader - Level 0 Channel Trigger Request Executing"] +pub type LVLEX0_R = crate::BitReader; +#[doc = "Field `LVLEX1` reader - Level 1 Channel Trigger Request Executing"] +pub type LVLEX1_R = crate::BitReader; +#[doc = "Field `LVLEX2` reader - Level 2 Channel Trigger Request Executing"] +pub type LVLEX2_R = crate::BitReader; +#[doc = "Field `LVLEX3` reader - Level 3 Channel Trigger Request Executing"] +pub type LVLEX3_R = crate::BitReader; +#[doc = "Field `ID` reader - Active Channel ID"] +pub type ID_R = crate::FieldReader; +#[doc = "Field `ABUSY` reader - Active Channel Busy"] +pub type ABUSY_R = crate::BitReader; +#[doc = "Field `BTCNT` reader - Active Channel Block Transfer Count"] +pub type BTCNT_R = crate::FieldReader; +impl R { + #[doc = "Bit 0 - Level 0 Channel Trigger Request Executing"] + #[inline(always)] + pub fn lvlex0(&self) -> LVLEX0_R { + LVLEX0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Level 1 Channel Trigger Request Executing"] + #[inline(always)] + pub fn lvlex1(&self) -> LVLEX1_R { + LVLEX1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Level 2 Channel Trigger Request Executing"] + #[inline(always)] + pub fn lvlex2(&self) -> LVLEX2_R { + LVLEX2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Level 3 Channel Trigger Request Executing"] + #[inline(always)] + pub fn lvlex3(&self) -> LVLEX3_R { + LVLEX3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 8:12 - Active Channel ID"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bit 15 - Active Channel Busy"] + #[inline(always)] + pub fn abusy(&self) -> ABUSY_R { + ABUSY_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:31 - Active Channel Block Transfer Count"] + #[inline(always)] + pub fn btcnt(&self) -> BTCNT_R { + BTCNT_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +#[doc = "Active Channel and Levels\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [active](index.html) module"] +pub struct ACTIVE_SPEC; +impl crate::RegisterSpec for ACTIVE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [active::R](R) reader structure"] +impl crate::Readable for ACTIVE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets ACTIVE to value 0"] +impl crate::Resettable for ACTIVE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/dmac/baseaddr.rs b/pac/atsaml22j/src/dmac/baseaddr.rs new file mode 100644 index 000000000000..a9a4aaf8d631 --- /dev/null +++ b/pac/atsaml22j/src/dmac/baseaddr.rs @@ -0,0 +1,80 @@ +#[doc = "Register `BASEADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BASEADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BASEADDR` reader - Descriptor Memory Base Address"] +pub type BASEADDR_R = crate::FieldReader; +#[doc = "Field `BASEADDR` writer - Descriptor Memory Base Address"] +pub type BASEADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, BASEADDR_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - Descriptor Memory Base Address"] + #[inline(always)] + pub fn baseaddr(&self) -> BASEADDR_R { + BASEADDR_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Descriptor Memory Base Address"] + #[inline(always)] + #[must_use] + pub fn baseaddr(&mut self) -> BASEADDR_W<0> { + BASEADDR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Descriptor Memory Section Base Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baseaddr](index.html) module"] +pub struct BASEADDR_SPEC; +impl crate::RegisterSpec for BASEADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [baseaddr::R](R) reader structure"] +impl crate::Readable for BASEADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baseaddr::W](W) writer structure"] +impl crate::Writable for BASEADDR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BASEADDR to value 0"] +impl crate::Resettable for BASEADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/dmac/busych.rs b/pac/atsaml22j/src/dmac/busych.rs new file mode 100644 index 000000000000..93b6aa6a4359 --- /dev/null +++ b/pac/atsaml22j/src/dmac/busych.rs @@ -0,0 +1,142 @@ +#[doc = "Register `BUSYCH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `BUSYCH0` reader - Busy Channel 0"] +pub type BUSYCH0_R = crate::BitReader; +#[doc = "Field `BUSYCH1` reader - Busy Channel 1"] +pub type BUSYCH1_R = crate::BitReader; +#[doc = "Field `BUSYCH2` reader - Busy Channel 2"] +pub type BUSYCH2_R = crate::BitReader; +#[doc = "Field `BUSYCH3` reader - Busy Channel 3"] +pub type BUSYCH3_R = crate::BitReader; +#[doc = "Field `BUSYCH4` reader - Busy Channel 4"] +pub type BUSYCH4_R = crate::BitReader; +#[doc = "Field `BUSYCH5` reader - Busy Channel 5"] +pub type BUSYCH5_R = crate::BitReader; +#[doc = "Field `BUSYCH6` reader - Busy Channel 6"] +pub type BUSYCH6_R = crate::BitReader; +#[doc = "Field `BUSYCH7` reader - Busy Channel 7"] +pub type BUSYCH7_R = crate::BitReader; +#[doc = "Field `BUSYCH8` reader - Busy Channel 8"] +pub type BUSYCH8_R = crate::BitReader; +#[doc = "Field `BUSYCH9` reader - Busy Channel 9"] +pub type BUSYCH9_R = crate::BitReader; +#[doc = "Field `BUSYCH10` reader - Busy Channel 10"] +pub type BUSYCH10_R = crate::BitReader; +#[doc = "Field `BUSYCH11` reader - Busy Channel 11"] +pub type BUSYCH11_R = crate::BitReader; +#[doc = "Field `BUSYCH12` reader - Busy Channel 12"] +pub type BUSYCH12_R = crate::BitReader; +#[doc = "Field `BUSYCH13` reader - Busy Channel 13"] +pub type BUSYCH13_R = crate::BitReader; +#[doc = "Field `BUSYCH14` reader - Busy Channel 14"] +pub type BUSYCH14_R = crate::BitReader; +#[doc = "Field `BUSYCH15` reader - Busy Channel 15"] +pub type BUSYCH15_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Busy Channel 0"] + #[inline(always)] + pub fn busych0(&self) -> BUSYCH0_R { + BUSYCH0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Busy Channel 1"] + #[inline(always)] + pub fn busych1(&self) -> BUSYCH1_R { + BUSYCH1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Busy Channel 2"] + #[inline(always)] + pub fn busych2(&self) -> BUSYCH2_R { + BUSYCH2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Busy Channel 3"] + #[inline(always)] + pub fn busych3(&self) -> BUSYCH3_R { + BUSYCH3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Busy Channel 4"] + #[inline(always)] + pub fn busych4(&self) -> BUSYCH4_R { + BUSYCH4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Busy Channel 5"] + #[inline(always)] + pub fn busych5(&self) -> BUSYCH5_R { + BUSYCH5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Busy Channel 6"] + #[inline(always)] + pub fn busych6(&self) -> BUSYCH6_R { + BUSYCH6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Busy Channel 7"] + #[inline(always)] + pub fn busych7(&self) -> BUSYCH7_R { + BUSYCH7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Busy Channel 8"] + #[inline(always)] + pub fn busych8(&self) -> BUSYCH8_R { + BUSYCH8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Busy Channel 9"] + #[inline(always)] + pub fn busych9(&self) -> BUSYCH9_R { + BUSYCH9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Busy Channel 10"] + #[inline(always)] + pub fn busych10(&self) -> BUSYCH10_R { + BUSYCH10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Busy Channel 11"] + #[inline(always)] + pub fn busych11(&self) -> BUSYCH11_R { + BUSYCH11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Busy Channel 12"] + #[inline(always)] + pub fn busych12(&self) -> BUSYCH12_R { + BUSYCH12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Busy Channel 13"] + #[inline(always)] + pub fn busych13(&self) -> BUSYCH13_R { + BUSYCH13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Busy Channel 14"] + #[inline(always)] + pub fn busych14(&self) -> BUSYCH14_R { + BUSYCH14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Busy Channel 15"] + #[inline(always)] + pub fn busych15(&self) -> BUSYCH15_R { + BUSYCH15_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[doc = "Busy Channels\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [busych](index.html) module"] +pub struct BUSYCH_SPEC; +impl crate::RegisterSpec for BUSYCH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [busych::R](R) reader structure"] +impl crate::Readable for BUSYCH_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets BUSYCH to value 0"] +impl crate::Resettable for BUSYCH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/dmac/chctrla.rs b/pac/atsaml22j/src/dmac/chctrla.rs new file mode 100644 index 000000000000..5a97a607ab7e --- /dev/null +++ b/pac/atsaml22j/src/dmac/chctrla.rs @@ -0,0 +1,110 @@ +#[doc = "Register `CHCTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHCTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Channel Software Reset"] +pub type SWRST_R = crate::BitReader; +#[doc = "Field `SWRST` writer - Channel Software Reset"] +pub type SWRST_W<'a, const O: u8> = crate::BitWriter<'a, u8, CHCTRLA_SPEC, bool, O>; +#[doc = "Field `ENABLE` reader - Channel Enable"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - Channel Enable"] +pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u8, CHCTRLA_SPEC, bool, O>; +#[doc = "Field `RUNSTDBY` reader - Channel run in standby"] +pub type RUNSTDBY_R = crate::BitReader; +#[doc = "Field `RUNSTDBY` writer - Channel run in standby"] +pub type RUNSTDBY_W<'a, const O: u8> = crate::BitWriter<'a, u8, CHCTRLA_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Channel Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Channel Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 6 - Channel run in standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel Software Reset"] + #[inline(always)] + #[must_use] + pub fn swrst(&mut self) -> SWRST_W<0> { + SWRST_W::new(self) + } + #[doc = "Bit 1 - Channel Enable"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W<1> { + ENABLE_W::new(self) + } + #[doc = "Bit 6 - Channel run in standby"] + #[inline(always)] + #[must_use] + pub fn runstdby(&mut self) -> RUNSTDBY_W<6> { + RUNSTDBY_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chctrla](index.html) module"] +pub struct CHCTRLA_SPEC; +impl crate::RegisterSpec for CHCTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chctrla::R](R) reader structure"] +impl crate::Readable for CHCTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chctrla::W](W) writer structure"] +impl crate::Writable for CHCTRLA_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CHCTRLA to value 0"] +impl crate::Resettable for CHCTRLA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/dmac/chctrlb.rs b/pac/atsaml22j/src/dmac/chctrlb.rs new file mode 100644 index 000000000000..7067b01c9d64 --- /dev/null +++ b/pac/atsaml22j/src/dmac/chctrlb.rs @@ -0,0 +1,443 @@ +#[doc = "Register `CHCTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHCTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVACT` reader - Event Input Action"] +pub type EVACT_R = crate::FieldReader; +#[doc = "Event Input Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum EVACTSELECT_A { + #[doc = "0: No action"] + NOACT = 0, + #[doc = "1: Transfer and periodic transfer trigger"] + TRIG = 1, + #[doc = "2: Conditional transfer trigger"] + CTRIG = 2, + #[doc = "3: Conditional block transfer"] + CBLOCK = 3, + #[doc = "4: Channel suspend operation"] + SUSPEND = 4, + #[doc = "5: Channel resume operation"] + RESUME = 5, + #[doc = "6: Skip next block suspend action"] + SSKIP = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACTSELECT_A) -> Self { + variant as _ + } +} +impl EVACT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(EVACTSELECT_A::NOACT), + 1 => Some(EVACTSELECT_A::TRIG), + 2 => Some(EVACTSELECT_A::CTRIG), + 3 => Some(EVACTSELECT_A::CBLOCK), + 4 => Some(EVACTSELECT_A::SUSPEND), + 5 => Some(EVACTSELECT_A::RESUME), + 6 => Some(EVACTSELECT_A::SSKIP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NOACT`"] + #[inline(always)] + pub fn is_noact(&self) -> bool { + *self == EVACTSELECT_A::NOACT + } + #[doc = "Checks if the value of the field is `TRIG`"] + #[inline(always)] + pub fn is_trig(&self) -> bool { + *self == EVACTSELECT_A::TRIG + } + #[doc = "Checks if the value of the field is `CTRIG`"] + #[inline(always)] + pub fn is_ctrig(&self) -> bool { + *self == EVACTSELECT_A::CTRIG + } + #[doc = "Checks if the value of the field is `CBLOCK`"] + #[inline(always)] + pub fn is_cblock(&self) -> bool { + *self == EVACTSELECT_A::CBLOCK + } + #[doc = "Checks if the value of the field is `SUSPEND`"] + #[inline(always)] + pub fn is_suspend(&self) -> bool { + *self == EVACTSELECT_A::SUSPEND + } + #[doc = "Checks if the value of the field is `RESUME`"] + #[inline(always)] + pub fn is_resume(&self) -> bool { + *self == EVACTSELECT_A::RESUME + } + #[doc = "Checks if the value of the field is `SSKIP`"] + #[inline(always)] + pub fn is_sskip(&self) -> bool { + *self == EVACTSELECT_A::SSKIP + } +} +#[doc = "Field `EVACT` writer - Event Input Action"] +pub type EVACT_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, CHCTRLB_SPEC, u8, EVACTSELECT_A, 3, O>; +impl<'a, const O: u8> EVACT_W<'a, O> { + #[doc = "No action"] + #[inline(always)] + pub fn noact(self) -> &'a mut W { + self.variant(EVACTSELECT_A::NOACT) + } + #[doc = "Transfer and periodic transfer trigger"] + #[inline(always)] + pub fn trig(self) -> &'a mut W { + self.variant(EVACTSELECT_A::TRIG) + } + #[doc = "Conditional transfer trigger"] + #[inline(always)] + pub fn ctrig(self) -> &'a mut W { + self.variant(EVACTSELECT_A::CTRIG) + } + #[doc = "Conditional block transfer"] + #[inline(always)] + pub fn cblock(self) -> &'a mut W { + self.variant(EVACTSELECT_A::CBLOCK) + } + #[doc = "Channel suspend operation"] + #[inline(always)] + pub fn suspend(self) -> &'a mut W { + self.variant(EVACTSELECT_A::SUSPEND) + } + #[doc = "Channel resume operation"] + #[inline(always)] + pub fn resume(self) -> &'a mut W { + self.variant(EVACTSELECT_A::RESUME) + } + #[doc = "Skip next block suspend action"] + #[inline(always)] + pub fn sskip(self) -> &'a mut W { + self.variant(EVACTSELECT_A::SSKIP) + } +} +#[doc = "Field `EVIE` reader - Channel Event Input Enable"] +pub type EVIE_R = crate::BitReader; +#[doc = "Field `EVIE` writer - Channel Event Input Enable"] +pub type EVIE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHCTRLB_SPEC, bool, O>; +#[doc = "Field `EVOE` reader - Channel Event Output Enable"] +pub type EVOE_R = crate::BitReader; +#[doc = "Field `EVOE` writer - Channel Event Output Enable"] +pub type EVOE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHCTRLB_SPEC, bool, O>; +#[doc = "Field `LVL` reader - Channel Arbitration Level"] +pub type LVL_R = crate::FieldReader; +#[doc = "Field `LVL` writer - Channel Arbitration Level"] +pub type LVL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CHCTRLB_SPEC, u8, u8, 2, O>; +#[doc = "Field `TRIGSRC` reader - Trigger Source"] +pub type TRIGSRC_R = crate::FieldReader; +#[doc = "Trigger Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum TRIGSRCSELECT_A { + #[doc = "0: Only software/event triggers"] + DISABLE = 0, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TRIGSRCSELECT_A) -> Self { + variant as _ + } +} +impl TRIGSRC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(TRIGSRCSELECT_A::DISABLE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == TRIGSRCSELECT_A::DISABLE + } +} +#[doc = "Field `TRIGSRC` writer - Trigger Source"] +pub type TRIGSRC_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, CHCTRLB_SPEC, u8, TRIGSRCSELECT_A, 6, O>; +impl<'a, const O: u8> TRIGSRC_W<'a, O> { + #[doc = "Only software/event triggers"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(TRIGSRCSELECT_A::DISABLE) + } +} +#[doc = "Field `TRIGACT` reader - Trigger Action"] +pub type TRIGACT_R = crate::FieldReader; +#[doc = "Trigger Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum TRIGACTSELECT_A { + #[doc = "0: One trigger required for each block transfer"] + BLOCK = 0, + #[doc = "2: One trigger required for each beat transfer"] + BEAT = 2, + #[doc = "3: One trigger required for each transaction"] + TRANSACTION = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: TRIGACTSELECT_A) -> Self { + variant as _ + } +} +impl TRIGACT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(TRIGACTSELECT_A::BLOCK), + 2 => Some(TRIGACTSELECT_A::BEAT), + 3 => Some(TRIGACTSELECT_A::TRANSACTION), + _ => None, + } + } + #[doc = "Checks if the value of the field is `BLOCK`"] + #[inline(always)] + pub fn is_block(&self) -> bool { + *self == TRIGACTSELECT_A::BLOCK + } + #[doc = "Checks if the value of the field is `BEAT`"] + #[inline(always)] + pub fn is_beat(&self) -> bool { + *self == TRIGACTSELECT_A::BEAT + } + #[doc = "Checks if the value of the field is `TRANSACTION`"] + #[inline(always)] + pub fn is_transaction(&self) -> bool { + *self == TRIGACTSELECT_A::TRANSACTION + } +} +#[doc = "Field `TRIGACT` writer - Trigger Action"] +pub type TRIGACT_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, CHCTRLB_SPEC, u8, TRIGACTSELECT_A, 2, O>; +impl<'a, const O: u8> TRIGACT_W<'a, O> { + #[doc = "One trigger required for each block transfer"] + #[inline(always)] + pub fn block(self) -> &'a mut W { + self.variant(TRIGACTSELECT_A::BLOCK) + } + #[doc = "One trigger required for each beat transfer"] + #[inline(always)] + pub fn beat(self) -> &'a mut W { + self.variant(TRIGACTSELECT_A::BEAT) + } + #[doc = "One trigger required for each transaction"] + #[inline(always)] + pub fn transaction(self) -> &'a mut W { + self.variant(TRIGACTSELECT_A::TRANSACTION) + } +} +#[doc = "Field `CMD` reader - Software Command"] +pub type CMD_R = crate::FieldReader; +#[doc = "Software Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum CMDSELECT_A { + #[doc = "0: No action"] + NOACT = 0, + #[doc = "1: Channel suspend operation"] + SUSPEND = 1, + #[doc = "2: Channel resume operation"] + RESUME = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMDSELECT_A) -> Self { + variant as _ + } +} +impl CMD_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMDSELECT_A::NOACT), + 1 => Some(CMDSELECT_A::SUSPEND), + 2 => Some(CMDSELECT_A::RESUME), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NOACT`"] + #[inline(always)] + pub fn is_noact(&self) -> bool { + *self == CMDSELECT_A::NOACT + } + #[doc = "Checks if the value of the field is `SUSPEND`"] + #[inline(always)] + pub fn is_suspend(&self) -> bool { + *self == CMDSELECT_A::SUSPEND + } + #[doc = "Checks if the value of the field is `RESUME`"] + #[inline(always)] + pub fn is_resume(&self) -> bool { + *self == CMDSELECT_A::RESUME + } +} +#[doc = "Field `CMD` writer - Software Command"] +pub type CMD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CHCTRLB_SPEC, u8, CMDSELECT_A, 2, O>; +impl<'a, const O: u8> CMD_W<'a, O> { + #[doc = "No action"] + #[inline(always)] + pub fn noact(self) -> &'a mut W { + self.variant(CMDSELECT_A::NOACT) + } + #[doc = "Channel suspend operation"] + #[inline(always)] + pub fn suspend(self) -> &'a mut W { + self.variant(CMDSELECT_A::SUSPEND) + } + #[doc = "Channel resume operation"] + #[inline(always)] + pub fn resume(self) -> &'a mut W { + self.variant(CMDSELECT_A::RESUME) + } +} +impl R { + #[doc = "Bits 0:2 - Event Input Action"] + #[inline(always)] + pub fn evact(&self) -> EVACT_R { + EVACT_R::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - Channel Event Input Enable"] + #[inline(always)] + pub fn evie(&self) -> EVIE_R { + EVIE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Channel Event Output Enable"] + #[inline(always)] + pub fn evoe(&self) -> EVOE_R { + EVOE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - Channel Arbitration Level"] + #[inline(always)] + pub fn lvl(&self) -> LVL_R { + LVL_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bits 8:13 - Trigger Source"] + #[inline(always)] + pub fn trigsrc(&self) -> TRIGSRC_R { + TRIGSRC_R::new(((self.bits >> 8) & 0x3f) as u8) + } + #[doc = "Bits 22:23 - Trigger Action"] + #[inline(always)] + pub fn trigact(&self) -> TRIGACT_R { + TRIGACT_R::new(((self.bits >> 22) & 3) as u8) + } + #[doc = "Bits 24:25 - Software Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new(((self.bits >> 24) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Event Input Action"] + #[inline(always)] + #[must_use] + pub fn evact(&mut self) -> EVACT_W<0> { + EVACT_W::new(self) + } + #[doc = "Bit 3 - Channel Event Input Enable"] + #[inline(always)] + #[must_use] + pub fn evie(&mut self) -> EVIE_W<3> { + EVIE_W::new(self) + } + #[doc = "Bit 4 - Channel Event Output Enable"] + #[inline(always)] + #[must_use] + pub fn evoe(&mut self) -> EVOE_W<4> { + EVOE_W::new(self) + } + #[doc = "Bits 5:6 - Channel Arbitration Level"] + #[inline(always)] + #[must_use] + pub fn lvl(&mut self) -> LVL_W<5> { + LVL_W::new(self) + } + #[doc = "Bits 8:13 - Trigger Source"] + #[inline(always)] + #[must_use] + pub fn trigsrc(&mut self) -> TRIGSRC_W<8> { + TRIGSRC_W::new(self) + } + #[doc = "Bits 22:23 - Trigger Action"] + #[inline(always)] + #[must_use] + pub fn trigact(&mut self) -> TRIGACT_W<22> { + TRIGACT_W::new(self) + } + #[doc = "Bits 24:25 - Software Command"] + #[inline(always)] + #[must_use] + pub fn cmd(&mut self) -> CMD_W<24> { + CMD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chctrlb](index.html) module"] +pub struct CHCTRLB_SPEC; +impl crate::RegisterSpec for CHCTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [chctrlb::R](R) reader structure"] +impl crate::Readable for CHCTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chctrlb::W](W) writer structure"] +impl crate::Writable for CHCTRLB_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CHCTRLB to value 0"] +impl crate::Resettable for CHCTRLB_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/dmac/chid.rs b/pac/atsaml22j/src/dmac/chid.rs new file mode 100644 index 000000000000..cf645883fb6a --- /dev/null +++ b/pac/atsaml22j/src/dmac/chid.rs @@ -0,0 +1,80 @@ +#[doc = "Register `CHID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHID` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID` reader - Channel ID"] +pub type ID_R = crate::FieldReader; +#[doc = "Field `ID` writer - Channel ID"] +pub type ID_W<'a, const O: u8> = crate::FieldWriter<'a, u8, CHID_SPEC, u8, u8, 4, O>; +impl R { + #[doc = "Bits 0:3 - Channel ID"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new(self.bits & 0x0f) + } +} +impl W { + #[doc = "Bits 0:3 - Channel ID"] + #[inline(always)] + #[must_use] + pub fn id(&mut self) -> ID_W<0> { + ID_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel ID\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chid](index.html) module"] +pub struct CHID_SPEC; +impl crate::RegisterSpec for CHID_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chid::R](R) reader structure"] +impl crate::Readable for CHID_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chid::W](W) writer structure"] +impl crate::Writable for CHID_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CHID to value 0"] +impl crate::Resettable for CHID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/dmac/chintenclr.rs b/pac/atsaml22j/src/dmac/chintenclr.rs new file mode 100644 index 000000000000..785e25ff6352 --- /dev/null +++ b/pac/atsaml22j/src/dmac/chintenclr.rs @@ -0,0 +1,110 @@ +#[doc = "Register `CHINTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHINTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TERR` reader - Channel Transfer Error Interrupt Enable"] +pub type TERR_R = crate::BitReader; +#[doc = "Field `TERR` writer - Channel Transfer Error Interrupt Enable"] +pub type TERR_W<'a, const O: u8> = crate::BitWriter<'a, u8, CHINTENCLR_SPEC, bool, O>; +#[doc = "Field `TCMPL` reader - Channel Transfer Complete Interrupt Enable"] +pub type TCMPL_R = crate::BitReader; +#[doc = "Field `TCMPL` writer - Channel Transfer Complete Interrupt Enable"] +pub type TCMPL_W<'a, const O: u8> = crate::BitWriter<'a, u8, CHINTENCLR_SPEC, bool, O>; +#[doc = "Field `SUSP` reader - Channel Suspend Interrupt Enable"] +pub type SUSP_R = crate::BitReader; +#[doc = "Field `SUSP` writer - Channel Suspend Interrupt Enable"] +pub type SUSP_W<'a, const O: u8> = crate::BitWriter<'a, u8, CHINTENCLR_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Channel Transfer Error Interrupt Enable"] + #[inline(always)] + pub fn terr(&self) -> TERR_R { + TERR_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Channel Transfer Complete Interrupt Enable"] + #[inline(always)] + pub fn tcmpl(&self) -> TCMPL_R { + TCMPL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Channel Suspend Interrupt Enable"] + #[inline(always)] + pub fn susp(&self) -> SUSP_R { + SUSP_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel Transfer Error Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn terr(&mut self) -> TERR_W<0> { + TERR_W::new(self) + } + #[doc = "Bit 1 - Channel Transfer Complete Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn tcmpl(&mut self) -> TCMPL_W<1> { + TCMPL_W::new(self) + } + #[doc = "Bit 2 - Channel Suspend Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn susp(&mut self) -> SUSP_W<2> { + SUSP_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chintenclr](index.html) module"] +pub struct CHINTENCLR_SPEC; +impl crate::RegisterSpec for CHINTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chintenclr::R](R) reader structure"] +impl crate::Readable for CHINTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chintenclr::W](W) writer structure"] +impl crate::Writable for CHINTENCLR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CHINTENCLR to value 0"] +impl crate::Resettable for CHINTENCLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/dmac/chintenset.rs b/pac/atsaml22j/src/dmac/chintenset.rs new file mode 100644 index 000000000000..d9460d03cc73 --- /dev/null +++ b/pac/atsaml22j/src/dmac/chintenset.rs @@ -0,0 +1,110 @@ +#[doc = "Register `CHINTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHINTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TERR` reader - Channel Transfer Error Interrupt Enable"] +pub type TERR_R = crate::BitReader; +#[doc = "Field `TERR` writer - Channel Transfer Error Interrupt Enable"] +pub type TERR_W<'a, const O: u8> = crate::BitWriter<'a, u8, CHINTENSET_SPEC, bool, O>; +#[doc = "Field `TCMPL` reader - Channel Transfer Complete Interrupt Enable"] +pub type TCMPL_R = crate::BitReader; +#[doc = "Field `TCMPL` writer - Channel Transfer Complete Interrupt Enable"] +pub type TCMPL_W<'a, const O: u8> = crate::BitWriter<'a, u8, CHINTENSET_SPEC, bool, O>; +#[doc = "Field `SUSP` reader - Channel Suspend Interrupt Enable"] +pub type SUSP_R = crate::BitReader; +#[doc = "Field `SUSP` writer - Channel Suspend Interrupt Enable"] +pub type SUSP_W<'a, const O: u8> = crate::BitWriter<'a, u8, CHINTENSET_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Channel Transfer Error Interrupt Enable"] + #[inline(always)] + pub fn terr(&self) -> TERR_R { + TERR_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Channel Transfer Complete Interrupt Enable"] + #[inline(always)] + pub fn tcmpl(&self) -> TCMPL_R { + TCMPL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Channel Suspend Interrupt Enable"] + #[inline(always)] + pub fn susp(&self) -> SUSP_R { + SUSP_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel Transfer Error Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn terr(&mut self) -> TERR_W<0> { + TERR_W::new(self) + } + #[doc = "Bit 1 - Channel Transfer Complete Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn tcmpl(&mut self) -> TCMPL_W<1> { + TCMPL_W::new(self) + } + #[doc = "Bit 2 - Channel Suspend Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn susp(&mut self) -> SUSP_W<2> { + SUSP_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chintenset](index.html) module"] +pub struct CHINTENSET_SPEC; +impl crate::RegisterSpec for CHINTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chintenset::R](R) reader structure"] +impl crate::Readable for CHINTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chintenset::W](W) writer structure"] +impl crate::Writable for CHINTENSET_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CHINTENSET to value 0"] +impl crate::Resettable for CHINTENSET_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/dmac/chintflag.rs b/pac/atsaml22j/src/dmac/chintflag.rs new file mode 100644 index 000000000000..9a055790f252 --- /dev/null +++ b/pac/atsaml22j/src/dmac/chintflag.rs @@ -0,0 +1,110 @@ +#[doc = "Register `CHINTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHINTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TERR` reader - Channel Transfer Error"] +pub type TERR_R = crate::BitReader; +#[doc = "Field `TERR` writer - Channel Transfer Error"] +pub type TERR_W<'a, const O: u8> = crate::BitWriter<'a, u8, CHINTFLAG_SPEC, bool, O>; +#[doc = "Field `TCMPL` reader - Channel Transfer Complete"] +pub type TCMPL_R = crate::BitReader; +#[doc = "Field `TCMPL` writer - Channel Transfer Complete"] +pub type TCMPL_W<'a, const O: u8> = crate::BitWriter<'a, u8, CHINTFLAG_SPEC, bool, O>; +#[doc = "Field `SUSP` reader - Channel Suspend"] +pub type SUSP_R = crate::BitReader; +#[doc = "Field `SUSP` writer - Channel Suspend"] +pub type SUSP_W<'a, const O: u8> = crate::BitWriter<'a, u8, CHINTFLAG_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Channel Transfer Error"] + #[inline(always)] + pub fn terr(&self) -> TERR_R { + TERR_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Channel Transfer Complete"] + #[inline(always)] + pub fn tcmpl(&self) -> TCMPL_R { + TCMPL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Channel Suspend"] + #[inline(always)] + pub fn susp(&self) -> SUSP_R { + SUSP_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel Transfer Error"] + #[inline(always)] + #[must_use] + pub fn terr(&mut self) -> TERR_W<0> { + TERR_W::new(self) + } + #[doc = "Bit 1 - Channel Transfer Complete"] + #[inline(always)] + #[must_use] + pub fn tcmpl(&mut self) -> TCMPL_W<1> { + TCMPL_W::new(self) + } + #[doc = "Bit 2 - Channel Suspend"] + #[inline(always)] + #[must_use] + pub fn susp(&mut self) -> SUSP_W<2> { + SUSP_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chintflag](index.html) module"] +pub struct CHINTFLAG_SPEC; +impl crate::RegisterSpec for CHINTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chintflag::R](R) reader structure"] +impl crate::Readable for CHINTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [chintflag::W](W) writer structure"] +impl crate::Writable for CHINTFLAG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CHINTFLAG to value 0"] +impl crate::Resettable for CHINTFLAG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/dmac/chstatus.rs b/pac/atsaml22j/src/dmac/chstatus.rs new file mode 100644 index 000000000000..52eba9c75d87 --- /dev/null +++ b/pac/atsaml22j/src/dmac/chstatus.rs @@ -0,0 +1,51 @@ +#[doc = "Register `CHSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PEND` reader - Channel Pending"] +pub type PEND_R = crate::BitReader; +#[doc = "Field `BUSY` reader - Channel Busy"] +pub type BUSY_R = crate::BitReader; +#[doc = "Field `FERR` reader - Channel Fetch Error"] +pub type FERR_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Channel Pending"] + #[inline(always)] + pub fn pend(&self) -> PEND_R { + PEND_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Channel Busy"] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Channel Fetch Error"] + #[inline(always)] + pub fn ferr(&self) -> FERR_R { + FERR_R::new(((self.bits >> 2) & 1) != 0) + } +} +#[doc = "Channel Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chstatus](index.html) module"] +pub struct CHSTATUS_SPEC; +impl crate::RegisterSpec for CHSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [chstatus::R](R) reader structure"] +impl crate::Readable for CHSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CHSTATUS to value 0"] +impl crate::Resettable for CHSTATUS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/dmac/crcchksum.rs b/pac/atsaml22j/src/dmac/crcchksum.rs new file mode 100644 index 000000000000..4a967643f68c --- /dev/null +++ b/pac/atsaml22j/src/dmac/crcchksum.rs @@ -0,0 +1,81 @@ +#[doc = "Register `CRCCHKSUM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CRCCHKSUM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CRCCHKSUM` reader - CRC Checksum"] +pub type CRCCHKSUM_R = crate::FieldReader; +#[doc = "Field `CRCCHKSUM` writer - CRC Checksum"] +pub type CRCCHKSUM_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, CRCCHKSUM_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - CRC Checksum"] + #[inline(always)] + pub fn crcchksum(&self) -> CRCCHKSUM_R { + CRCCHKSUM_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - CRC Checksum"] + #[inline(always)] + #[must_use] + pub fn crcchksum(&mut self) -> CRCCHKSUM_W<0> { + CRCCHKSUM_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CRC Checksum\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crcchksum](index.html) module"] +pub struct CRCCHKSUM_SPEC; +impl crate::RegisterSpec for CRCCHKSUM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [crcchksum::R](R) reader structure"] +impl crate::Readable for CRCCHKSUM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [crcchksum::W](W) writer structure"] +impl crate::Writable for CRCCHKSUM_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CRCCHKSUM to value 0"] +impl crate::Resettable for CRCCHKSUM_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/dmac/crcctrl.rs b/pac/atsaml22j/src/dmac/crcctrl.rs new file mode 100644 index 000000000000..21597ad05fee --- /dev/null +++ b/pac/atsaml22j/src/dmac/crcctrl.rs @@ -0,0 +1,270 @@ +#[doc = "Register `CRCCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CRCCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CRCBEATSIZE` reader - CRC Beat Size"] +pub type CRCBEATSIZE_R = crate::FieldReader; +#[doc = "CRC Beat Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum CRCBEATSIZESELECT_A { + #[doc = "0: 8-bit bus transfer"] + BYTE = 0, + #[doc = "1: 16-bit bus transfer"] + HWORD = 1, + #[doc = "2: 32-bit bus transfer"] + WORD = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CRCBEATSIZESELECT_A) -> Self { + variant as _ + } +} +impl CRCBEATSIZE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CRCBEATSIZESELECT_A::BYTE), + 1 => Some(CRCBEATSIZESELECT_A::HWORD), + 2 => Some(CRCBEATSIZESELECT_A::WORD), + _ => None, + } + } + #[doc = "Checks if the value of the field is `BYTE`"] + #[inline(always)] + pub fn is_byte(&self) -> bool { + *self == CRCBEATSIZESELECT_A::BYTE + } + #[doc = "Checks if the value of the field is `HWORD`"] + #[inline(always)] + pub fn is_hword(&self) -> bool { + *self == CRCBEATSIZESELECT_A::HWORD + } + #[doc = "Checks if the value of the field is `WORD`"] + #[inline(always)] + pub fn is_word(&self) -> bool { + *self == CRCBEATSIZESELECT_A::WORD + } +} +#[doc = "Field `CRCBEATSIZE` writer - CRC Beat Size"] +pub type CRCBEATSIZE_W<'a, const O: u8> = + crate::FieldWriter<'a, u16, CRCCTRL_SPEC, u8, CRCBEATSIZESELECT_A, 2, O>; +impl<'a, const O: u8> CRCBEATSIZE_W<'a, O> { + #[doc = "8-bit bus transfer"] + #[inline(always)] + pub fn byte(self) -> &'a mut W { + self.variant(CRCBEATSIZESELECT_A::BYTE) + } + #[doc = "16-bit bus transfer"] + #[inline(always)] + pub fn hword(self) -> &'a mut W { + self.variant(CRCBEATSIZESELECT_A::HWORD) + } + #[doc = "32-bit bus transfer"] + #[inline(always)] + pub fn word(self) -> &'a mut W { + self.variant(CRCBEATSIZESELECT_A::WORD) + } +} +#[doc = "Field `CRCPOLY` reader - CRC Polynomial Type"] +pub type CRCPOLY_R = crate::FieldReader; +#[doc = "CRC Polynomial Type\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum CRCPOLYSELECT_A { + #[doc = "0: CRC-16 (CRC-CCITT)"] + CRC16 = 0, + #[doc = "1: CRC32 (IEEE 802.3)"] + CRC32 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CRCPOLYSELECT_A) -> Self { + variant as _ + } +} +impl CRCPOLY_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CRCPOLYSELECT_A::CRC16), + 1 => Some(CRCPOLYSELECT_A::CRC32), + _ => None, + } + } + #[doc = "Checks if the value of the field is `CRC16`"] + #[inline(always)] + pub fn is_crc16(&self) -> bool { + *self == CRCPOLYSELECT_A::CRC16 + } + #[doc = "Checks if the value of the field is `CRC32`"] + #[inline(always)] + pub fn is_crc32(&self) -> bool { + *self == CRCPOLYSELECT_A::CRC32 + } +} +#[doc = "Field `CRCPOLY` writer - CRC Polynomial Type"] +pub type CRCPOLY_W<'a, const O: u8> = + crate::FieldWriter<'a, u16, CRCCTRL_SPEC, u8, CRCPOLYSELECT_A, 2, O>; +impl<'a, const O: u8> CRCPOLY_W<'a, O> { + #[doc = "CRC-16 (CRC-CCITT)"] + #[inline(always)] + pub fn crc16(self) -> &'a mut W { + self.variant(CRCPOLYSELECT_A::CRC16) + } + #[doc = "CRC32 (IEEE 802.3)"] + #[inline(always)] + pub fn crc32(self) -> &'a mut W { + self.variant(CRCPOLYSELECT_A::CRC32) + } +} +#[doc = "Field `CRCSRC` reader - CRC Input Source"] +pub type CRCSRC_R = crate::FieldReader; +#[doc = "CRC Input Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum CRCSRCSELECT_A { + #[doc = "0: No action"] + NOACT = 0, + #[doc = "1: I/O interface"] + IO = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CRCSRCSELECT_A) -> Self { + variant as _ + } +} +impl CRCSRC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CRCSRCSELECT_A::NOACT), + 1 => Some(CRCSRCSELECT_A::IO), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NOACT`"] + #[inline(always)] + pub fn is_noact(&self) -> bool { + *self == CRCSRCSELECT_A::NOACT + } + #[doc = "Checks if the value of the field is `IO`"] + #[inline(always)] + pub fn is_io(&self) -> bool { + *self == CRCSRCSELECT_A::IO + } +} +#[doc = "Field `CRCSRC` writer - CRC Input Source"] +pub type CRCSRC_W<'a, const O: u8> = + crate::FieldWriter<'a, u16, CRCCTRL_SPEC, u8, CRCSRCSELECT_A, 6, O>; +impl<'a, const O: u8> CRCSRC_W<'a, O> { + #[doc = "No action"] + #[inline(always)] + pub fn noact(self) -> &'a mut W { + self.variant(CRCSRCSELECT_A::NOACT) + } + #[doc = "I/O interface"] + #[inline(always)] + pub fn io(self) -> &'a mut W { + self.variant(CRCSRCSELECT_A::IO) + } +} +impl R { + #[doc = "Bits 0:1 - CRC Beat Size"] + #[inline(always)] + pub fn crcbeatsize(&self) -> CRCBEATSIZE_R { + CRCBEATSIZE_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - CRC Polynomial Type"] + #[inline(always)] + pub fn crcpoly(&self) -> CRCPOLY_R { + CRCPOLY_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 8:13 - CRC Input Source"] + #[inline(always)] + pub fn crcsrc(&self) -> CRCSRC_R { + CRCSRC_R::new(((self.bits >> 8) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - CRC Beat Size"] + #[inline(always)] + #[must_use] + pub fn crcbeatsize(&mut self) -> CRCBEATSIZE_W<0> { + CRCBEATSIZE_W::new(self) + } + #[doc = "Bits 2:3 - CRC Polynomial Type"] + #[inline(always)] + #[must_use] + pub fn crcpoly(&mut self) -> CRCPOLY_W<2> { + CRCPOLY_W::new(self) + } + #[doc = "Bits 8:13 - CRC Input Source"] + #[inline(always)] + #[must_use] + pub fn crcsrc(&mut self) -> CRCSRC_W<8> { + CRCSRC_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CRC Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crcctrl](index.html) module"] +pub struct CRCCTRL_SPEC; +impl crate::RegisterSpec for CRCCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [crcctrl::R](R) reader structure"] +impl crate::Readable for CRCCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [crcctrl::W](W) writer structure"] +impl crate::Writable for CRCCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CRCCTRL to value 0"] +impl crate::Resettable for CRCCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/dmac/crcdatain.rs b/pac/atsaml22j/src/dmac/crcdatain.rs new file mode 100644 index 000000000000..96882d2d2017 --- /dev/null +++ b/pac/atsaml22j/src/dmac/crcdatain.rs @@ -0,0 +1,81 @@ +#[doc = "Register `CRCDATAIN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CRCDATAIN` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CRCDATAIN` reader - CRC Data Input"] +pub type CRCDATAIN_R = crate::FieldReader; +#[doc = "Field `CRCDATAIN` writer - CRC Data Input"] +pub type CRCDATAIN_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, CRCDATAIN_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - CRC Data Input"] + #[inline(always)] + pub fn crcdatain(&self) -> CRCDATAIN_R { + CRCDATAIN_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - CRC Data Input"] + #[inline(always)] + #[must_use] + pub fn crcdatain(&mut self) -> CRCDATAIN_W<0> { + CRCDATAIN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CRC Data Input\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crcdatain](index.html) module"] +pub struct CRCDATAIN_SPEC; +impl crate::RegisterSpec for CRCDATAIN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [crcdatain::R](R) reader structure"] +impl crate::Readable for CRCDATAIN_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [crcdatain::W](W) writer structure"] +impl crate::Writable for CRCDATAIN_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CRCDATAIN to value 0"] +impl crate::Resettable for CRCDATAIN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/dmac/crcstatus.rs b/pac/atsaml22j/src/dmac/crcstatus.rs new file mode 100644 index 000000000000..aa6d78199b8f --- /dev/null +++ b/pac/atsaml22j/src/dmac/crcstatus.rs @@ -0,0 +1,87 @@ +#[doc = "Register `CRCSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CRCSTATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CRCBUSY` reader - CRC Module Busy"] +pub type CRCBUSY_R = crate::BitReader; +#[doc = "Field `CRCBUSY` writer - CRC Module Busy"] +pub type CRCBUSY_W<'a, const O: u8> = crate::BitWriter<'a, u8, CRCSTATUS_SPEC, bool, O>; +#[doc = "Field `CRCZERO` reader - CRC Zero"] +pub type CRCZERO_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - CRC Module Busy"] + #[inline(always)] + pub fn crcbusy(&self) -> CRCBUSY_R { + CRCBUSY_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - CRC Zero"] + #[inline(always)] + pub fn crczero(&self) -> CRCZERO_R { + CRCZERO_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - CRC Module Busy"] + #[inline(always)] + #[must_use] + pub fn crcbusy(&mut self) -> CRCBUSY_W<0> { + CRCBUSY_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CRC Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [crcstatus](index.html) module"] +pub struct CRCSTATUS_SPEC; +impl crate::RegisterSpec for CRCSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [crcstatus::R](R) reader structure"] +impl crate::Readable for CRCSTATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [crcstatus::W](W) writer structure"] +impl crate::Writable for CRCSTATUS_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CRCSTATUS to value 0"] +impl crate::Resettable for CRCSTATUS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/dmac/ctrl.rs b/pac/atsaml22j/src/dmac/ctrl.rs new file mode 100644 index 000000000000..d14b08ad4954 --- /dev/null +++ b/pac/atsaml22j/src/dmac/ctrl.rs @@ -0,0 +1,170 @@ +#[doc = "Register `CTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub type SWRST_R = crate::BitReader; +#[doc = "Field `SWRST` writer - Software Reset"] +pub type SWRST_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRL_SPEC, bool, O>; +#[doc = "Field `DMAENABLE` reader - DMA Enable"] +pub type DMAENABLE_R = crate::BitReader; +#[doc = "Field `DMAENABLE` writer - DMA Enable"] +pub type DMAENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRL_SPEC, bool, O>; +#[doc = "Field `CRCENABLE` reader - CRC Enable"] +pub type CRCENABLE_R = crate::BitReader; +#[doc = "Field `CRCENABLE` writer - CRC Enable"] +pub type CRCENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRL_SPEC, bool, O>; +#[doc = "Field `LVLEN0` reader - Priority Level 0 Enable"] +pub type LVLEN0_R = crate::BitReader; +#[doc = "Field `LVLEN0` writer - Priority Level 0 Enable"] +pub type LVLEN0_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRL_SPEC, bool, O>; +#[doc = "Field `LVLEN1` reader - Priority Level 1 Enable"] +pub type LVLEN1_R = crate::BitReader; +#[doc = "Field `LVLEN1` writer - Priority Level 1 Enable"] +pub type LVLEN1_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRL_SPEC, bool, O>; +#[doc = "Field `LVLEN2` reader - Priority Level 2 Enable"] +pub type LVLEN2_R = crate::BitReader; +#[doc = "Field `LVLEN2` writer - Priority Level 2 Enable"] +pub type LVLEN2_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRL_SPEC, bool, O>; +#[doc = "Field `LVLEN3` reader - Priority Level 3 Enable"] +pub type LVLEN3_R = crate::BitReader; +#[doc = "Field `LVLEN3` writer - Priority Level 3 Enable"] +pub type LVLEN3_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRL_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - DMA Enable"] + #[inline(always)] + pub fn dmaenable(&self) -> DMAENABLE_R { + DMAENABLE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - CRC Enable"] + #[inline(always)] + pub fn crcenable(&self) -> CRCENABLE_R { + CRCENABLE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 8 - Priority Level 0 Enable"] + #[inline(always)] + pub fn lvlen0(&self) -> LVLEN0_R { + LVLEN0_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Priority Level 1 Enable"] + #[inline(always)] + pub fn lvlen1(&self) -> LVLEN1_R { + LVLEN1_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Priority Level 2 Enable"] + #[inline(always)] + pub fn lvlen2(&self) -> LVLEN2_R { + LVLEN2_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Priority Level 3 Enable"] + #[inline(always)] + pub fn lvlen3(&self) -> LVLEN3_R { + LVLEN3_R::new(((self.bits >> 11) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + #[must_use] + pub fn swrst(&mut self) -> SWRST_W<0> { + SWRST_W::new(self) + } + #[doc = "Bit 1 - DMA Enable"] + #[inline(always)] + #[must_use] + pub fn dmaenable(&mut self) -> DMAENABLE_W<1> { + DMAENABLE_W::new(self) + } + #[doc = "Bit 2 - CRC Enable"] + #[inline(always)] + #[must_use] + pub fn crcenable(&mut self) -> CRCENABLE_W<2> { + CRCENABLE_W::new(self) + } + #[doc = "Bit 8 - Priority Level 0 Enable"] + #[inline(always)] + #[must_use] + pub fn lvlen0(&mut self) -> LVLEN0_W<8> { + LVLEN0_W::new(self) + } + #[doc = "Bit 9 - Priority Level 1 Enable"] + #[inline(always)] + #[must_use] + pub fn lvlen1(&mut self) -> LVLEN1_W<9> { + LVLEN1_W::new(self) + } + #[doc = "Bit 10 - Priority Level 2 Enable"] + #[inline(always)] + #[must_use] + pub fn lvlen2(&mut self) -> LVLEN2_W<10> { + LVLEN2_W::new(self) + } + #[doc = "Bit 11 - Priority Level 3 Enable"] + #[inline(always)] + #[must_use] + pub fn lvlen3(&mut self) -> LVLEN3_W<11> { + LVLEN3_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/dmac/dbgctrl.rs b/pac/atsaml22j/src/dmac/dbgctrl.rs new file mode 100644 index 000000000000..71c6b3e56bf2 --- /dev/null +++ b/pac/atsaml22j/src/dmac/dbgctrl.rs @@ -0,0 +1,80 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Run"] +pub type DBGRUN_R = crate::BitReader; +#[doc = "Field `DBGRUN` writer - Debug Run"] +pub type DBGRUN_W<'a, const O: u8> = crate::BitWriter<'a, u8, DBGCTRL_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Run"] + #[inline(always)] + #[must_use] + pub fn dbgrun(&mut self) -> DBGRUN_W<0> { + DBGRUN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/dmac/intpend.rs b/pac/atsaml22j/src/dmac/intpend.rs new file mode 100644 index 000000000000..36b7d1e9d31c --- /dev/null +++ b/pac/atsaml22j/src/dmac/intpend.rs @@ -0,0 +1,146 @@ +#[doc = "Register `INTPEND` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTPEND` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ID` reader - Channel ID"] +pub type ID_R = crate::FieldReader; +#[doc = "Field `ID` writer - Channel ID"] +pub type ID_W<'a, const O: u8> = crate::FieldWriter<'a, u16, INTPEND_SPEC, u8, u8, 4, O>; +#[doc = "Field `TERR` reader - Transfer Error"] +pub type TERR_R = crate::BitReader; +#[doc = "Field `TERR` writer - Transfer Error"] +pub type TERR_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTPEND_SPEC, bool, O>; +#[doc = "Field `TCMPL` reader - Transfer Complete"] +pub type TCMPL_R = crate::BitReader; +#[doc = "Field `TCMPL` writer - Transfer Complete"] +pub type TCMPL_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTPEND_SPEC, bool, O>; +#[doc = "Field `SUSP` reader - Channel Suspend"] +pub type SUSP_R = crate::BitReader; +#[doc = "Field `SUSP` writer - Channel Suspend"] +pub type SUSP_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTPEND_SPEC, bool, O>; +#[doc = "Field `FERR` reader - Fetch Error"] +pub type FERR_R = crate::BitReader; +#[doc = "Field `BUSY` reader - Busy"] +pub type BUSY_R = crate::BitReader; +#[doc = "Field `PEND` reader - Pending"] +pub type PEND_R = crate::BitReader; +impl R { + #[doc = "Bits 0:3 - Channel ID"] + #[inline(always)] + pub fn id(&self) -> ID_R { + ID_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 8 - Transfer Error"] + #[inline(always)] + pub fn terr(&self) -> TERR_R { + TERR_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Transfer Complete"] + #[inline(always)] + pub fn tcmpl(&self) -> TCMPL_R { + TCMPL_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Channel Suspend"] + #[inline(always)] + pub fn susp(&self) -> SUSP_R { + SUSP_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 13 - Fetch Error"] + #[inline(always)] + pub fn ferr(&self) -> FERR_R { + FERR_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Busy"] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Pending"] + #[inline(always)] + pub fn pend(&self) -> PEND_R { + PEND_R::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Channel ID"] + #[inline(always)] + #[must_use] + pub fn id(&mut self) -> ID_W<0> { + ID_W::new(self) + } + #[doc = "Bit 8 - Transfer Error"] + #[inline(always)] + #[must_use] + pub fn terr(&mut self) -> TERR_W<8> { + TERR_W::new(self) + } + #[doc = "Bit 9 - Transfer Complete"] + #[inline(always)] + #[must_use] + pub fn tcmpl(&mut self) -> TCMPL_W<9> { + TCMPL_W::new(self) + } + #[doc = "Bit 10 - Channel Suspend"] + #[inline(always)] + #[must_use] + pub fn susp(&mut self) -> SUSP_W<10> { + SUSP_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Pending\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intpend](index.html) module"] +pub struct INTPEND_SPEC; +impl crate::RegisterSpec for INTPEND_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intpend::R](R) reader structure"] +impl crate::Readable for INTPEND_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intpend::W](W) writer structure"] +impl crate::Writable for INTPEND_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTPEND to value 0"] +impl crate::Resettable for INTPEND_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/dmac/intstatus.rs b/pac/atsaml22j/src/dmac/intstatus.rs new file mode 100644 index 000000000000..bcc1aab770c4 --- /dev/null +++ b/pac/atsaml22j/src/dmac/intstatus.rs @@ -0,0 +1,142 @@ +#[doc = "Register `INTSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `CHINT0` reader - Channel 0 Pending Interrupt"] +pub type CHINT0_R = crate::BitReader; +#[doc = "Field `CHINT1` reader - Channel 1 Pending Interrupt"] +pub type CHINT1_R = crate::BitReader; +#[doc = "Field `CHINT2` reader - Channel 2 Pending Interrupt"] +pub type CHINT2_R = crate::BitReader; +#[doc = "Field `CHINT3` reader - Channel 3 Pending Interrupt"] +pub type CHINT3_R = crate::BitReader; +#[doc = "Field `CHINT4` reader - Channel 4 Pending Interrupt"] +pub type CHINT4_R = crate::BitReader; +#[doc = "Field `CHINT5` reader - Channel 5 Pending Interrupt"] +pub type CHINT5_R = crate::BitReader; +#[doc = "Field `CHINT6` reader - Channel 6 Pending Interrupt"] +pub type CHINT6_R = crate::BitReader; +#[doc = "Field `CHINT7` reader - Channel 7 Pending Interrupt"] +pub type CHINT7_R = crate::BitReader; +#[doc = "Field `CHINT8` reader - Channel 8 Pending Interrupt"] +pub type CHINT8_R = crate::BitReader; +#[doc = "Field `CHINT9` reader - Channel 9 Pending Interrupt"] +pub type CHINT9_R = crate::BitReader; +#[doc = "Field `CHINT10` reader - Channel 10 Pending Interrupt"] +pub type CHINT10_R = crate::BitReader; +#[doc = "Field `CHINT11` reader - Channel 11 Pending Interrupt"] +pub type CHINT11_R = crate::BitReader; +#[doc = "Field `CHINT12` reader - Channel 12 Pending Interrupt"] +pub type CHINT12_R = crate::BitReader; +#[doc = "Field `CHINT13` reader - Channel 13 Pending Interrupt"] +pub type CHINT13_R = crate::BitReader; +#[doc = "Field `CHINT14` reader - Channel 14 Pending Interrupt"] +pub type CHINT14_R = crate::BitReader; +#[doc = "Field `CHINT15` reader - Channel 15 Pending Interrupt"] +pub type CHINT15_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Channel 0 Pending Interrupt"] + #[inline(always)] + pub fn chint0(&self) -> CHINT0_R { + CHINT0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Channel 1 Pending Interrupt"] + #[inline(always)] + pub fn chint1(&self) -> CHINT1_R { + CHINT1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Channel 2 Pending Interrupt"] + #[inline(always)] + pub fn chint2(&self) -> CHINT2_R { + CHINT2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Channel 3 Pending Interrupt"] + #[inline(always)] + pub fn chint3(&self) -> CHINT3_R { + CHINT3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Channel 4 Pending Interrupt"] + #[inline(always)] + pub fn chint4(&self) -> CHINT4_R { + CHINT4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Channel 5 Pending Interrupt"] + #[inline(always)] + pub fn chint5(&self) -> CHINT5_R { + CHINT5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Channel 6 Pending Interrupt"] + #[inline(always)] + pub fn chint6(&self) -> CHINT6_R { + CHINT6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Channel 7 Pending Interrupt"] + #[inline(always)] + pub fn chint7(&self) -> CHINT7_R { + CHINT7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Channel 8 Pending Interrupt"] + #[inline(always)] + pub fn chint8(&self) -> CHINT8_R { + CHINT8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Channel 9 Pending Interrupt"] + #[inline(always)] + pub fn chint9(&self) -> CHINT9_R { + CHINT9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Channel 10 Pending Interrupt"] + #[inline(always)] + pub fn chint10(&self) -> CHINT10_R { + CHINT10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Channel 11 Pending Interrupt"] + #[inline(always)] + pub fn chint11(&self) -> CHINT11_R { + CHINT11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Channel 12 Pending Interrupt"] + #[inline(always)] + pub fn chint12(&self) -> CHINT12_R { + CHINT12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Channel 13 Pending Interrupt"] + #[inline(always)] + pub fn chint13(&self) -> CHINT13_R { + CHINT13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Channel 14 Pending Interrupt"] + #[inline(always)] + pub fn chint14(&self) -> CHINT14_R { + CHINT14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Channel 15 Pending Interrupt"] + #[inline(always)] + pub fn chint15(&self) -> CHINT15_R { + CHINT15_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[doc = "Interrupt Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intstatus](index.html) module"] +pub struct INTSTATUS_SPEC; +impl crate::RegisterSpec for INTSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intstatus::R](R) reader structure"] +impl crate::Readable for INTSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets INTSTATUS to value 0"] +impl crate::Resettable for INTSTATUS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/dmac/pendch.rs b/pac/atsaml22j/src/dmac/pendch.rs new file mode 100644 index 000000000000..1e1a63911146 --- /dev/null +++ b/pac/atsaml22j/src/dmac/pendch.rs @@ -0,0 +1,142 @@ +#[doc = "Register `PENDCH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PENDCH0` reader - Pending Channel 0"] +pub type PENDCH0_R = crate::BitReader; +#[doc = "Field `PENDCH1` reader - Pending Channel 1"] +pub type PENDCH1_R = crate::BitReader; +#[doc = "Field `PENDCH2` reader - Pending Channel 2"] +pub type PENDCH2_R = crate::BitReader; +#[doc = "Field `PENDCH3` reader - Pending Channel 3"] +pub type PENDCH3_R = crate::BitReader; +#[doc = "Field `PENDCH4` reader - Pending Channel 4"] +pub type PENDCH4_R = crate::BitReader; +#[doc = "Field `PENDCH5` reader - Pending Channel 5"] +pub type PENDCH5_R = crate::BitReader; +#[doc = "Field `PENDCH6` reader - Pending Channel 6"] +pub type PENDCH6_R = crate::BitReader; +#[doc = "Field `PENDCH7` reader - Pending Channel 7"] +pub type PENDCH7_R = crate::BitReader; +#[doc = "Field `PENDCH8` reader - Pending Channel 8"] +pub type PENDCH8_R = crate::BitReader; +#[doc = "Field `PENDCH9` reader - Pending Channel 9"] +pub type PENDCH9_R = crate::BitReader; +#[doc = "Field `PENDCH10` reader - Pending Channel 10"] +pub type PENDCH10_R = crate::BitReader; +#[doc = "Field `PENDCH11` reader - Pending Channel 11"] +pub type PENDCH11_R = crate::BitReader; +#[doc = "Field `PENDCH12` reader - Pending Channel 12"] +pub type PENDCH12_R = crate::BitReader; +#[doc = "Field `PENDCH13` reader - Pending Channel 13"] +pub type PENDCH13_R = crate::BitReader; +#[doc = "Field `PENDCH14` reader - Pending Channel 14"] +pub type PENDCH14_R = crate::BitReader; +#[doc = "Field `PENDCH15` reader - Pending Channel 15"] +pub type PENDCH15_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Pending Channel 0"] + #[inline(always)] + pub fn pendch0(&self) -> PENDCH0_R { + PENDCH0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pending Channel 1"] + #[inline(always)] + pub fn pendch1(&self) -> PENDCH1_R { + PENDCH1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Pending Channel 2"] + #[inline(always)] + pub fn pendch2(&self) -> PENDCH2_R { + PENDCH2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Pending Channel 3"] + #[inline(always)] + pub fn pendch3(&self) -> PENDCH3_R { + PENDCH3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Pending Channel 4"] + #[inline(always)] + pub fn pendch4(&self) -> PENDCH4_R { + PENDCH4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Pending Channel 5"] + #[inline(always)] + pub fn pendch5(&self) -> PENDCH5_R { + PENDCH5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Pending Channel 6"] + #[inline(always)] + pub fn pendch6(&self) -> PENDCH6_R { + PENDCH6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Pending Channel 7"] + #[inline(always)] + pub fn pendch7(&self) -> PENDCH7_R { + PENDCH7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Pending Channel 8"] + #[inline(always)] + pub fn pendch8(&self) -> PENDCH8_R { + PENDCH8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Pending Channel 9"] + #[inline(always)] + pub fn pendch9(&self) -> PENDCH9_R { + PENDCH9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Pending Channel 10"] + #[inline(always)] + pub fn pendch10(&self) -> PENDCH10_R { + PENDCH10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Pending Channel 11"] + #[inline(always)] + pub fn pendch11(&self) -> PENDCH11_R { + PENDCH11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Pending Channel 12"] + #[inline(always)] + pub fn pendch12(&self) -> PENDCH12_R { + PENDCH12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Pending Channel 13"] + #[inline(always)] + pub fn pendch13(&self) -> PENDCH13_R { + PENDCH13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Pending Channel 14"] + #[inline(always)] + pub fn pendch14(&self) -> PENDCH14_R { + PENDCH14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Pending Channel 15"] + #[inline(always)] + pub fn pendch15(&self) -> PENDCH15_R { + PENDCH15_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[doc = "Pending Channels\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pendch](index.html) module"] +pub struct PENDCH_SPEC; +impl crate::RegisterSpec for PENDCH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pendch::R](R) reader structure"] +impl crate::Readable for PENDCH_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PENDCH to value 0"] +impl crate::Resettable for PENDCH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/dmac/prictrl0.rs b/pac/atsaml22j/src/dmac/prictrl0.rs new file mode 100644 index 000000000000..f56227a0b3c2 --- /dev/null +++ b/pac/atsaml22j/src/dmac/prictrl0.rs @@ -0,0 +1,185 @@ +#[doc = "Register `PRICTRL0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PRICTRL0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LVLPRI0` reader - Level 0 Channel Priority Number"] +pub type LVLPRI0_R = crate::FieldReader; +#[doc = "Field `LVLPRI0` writer - Level 0 Channel Priority Number"] +pub type LVLPRI0_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PRICTRL0_SPEC, u8, u8, 4, O>; +#[doc = "Field `RRLVLEN0` reader - Level 0 Round-Robin Scheduling Enable"] +pub type RRLVLEN0_R = crate::BitReader; +#[doc = "Field `RRLVLEN0` writer - Level 0 Round-Robin Scheduling Enable"] +pub type RRLVLEN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, PRICTRL0_SPEC, bool, O>; +#[doc = "Field `LVLPRI1` reader - Level 1 Channel Priority Number"] +pub type LVLPRI1_R = crate::FieldReader; +#[doc = "Field `LVLPRI1` writer - Level 1 Channel Priority Number"] +pub type LVLPRI1_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PRICTRL0_SPEC, u8, u8, 4, O>; +#[doc = "Field `RRLVLEN1` reader - Level 1 Round-Robin Scheduling Enable"] +pub type RRLVLEN1_R = crate::BitReader; +#[doc = "Field `RRLVLEN1` writer - Level 1 Round-Robin Scheduling Enable"] +pub type RRLVLEN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, PRICTRL0_SPEC, bool, O>; +#[doc = "Field `LVLPRI2` reader - Level 2 Channel Priority Number"] +pub type LVLPRI2_R = crate::FieldReader; +#[doc = "Field `LVLPRI2` writer - Level 2 Channel Priority Number"] +pub type LVLPRI2_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PRICTRL0_SPEC, u8, u8, 4, O>; +#[doc = "Field `RRLVLEN2` reader - Level 2 Round-Robin Scheduling Enable"] +pub type RRLVLEN2_R = crate::BitReader; +#[doc = "Field `RRLVLEN2` writer - Level 2 Round-Robin Scheduling Enable"] +pub type RRLVLEN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, PRICTRL0_SPEC, bool, O>; +#[doc = "Field `LVLPRI3` reader - Level 3 Channel Priority Number"] +pub type LVLPRI3_R = crate::FieldReader; +#[doc = "Field `LVLPRI3` writer - Level 3 Channel Priority Number"] +pub type LVLPRI3_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PRICTRL0_SPEC, u8, u8, 4, O>; +#[doc = "Field `RRLVLEN3` reader - Level 3 Round-Robin Scheduling Enable"] +pub type RRLVLEN3_R = crate::BitReader; +#[doc = "Field `RRLVLEN3` writer - Level 3 Round-Robin Scheduling Enable"] +pub type RRLVLEN3_W<'a, const O: u8> = crate::BitWriter<'a, u32, PRICTRL0_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:3 - Level 0 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri0(&self) -> LVLPRI0_R { + LVLPRI0_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 7 - Level 0 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen0(&self) -> RRLVLEN0_R { + RRLVLEN0_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:11 - Level 1 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri1(&self) -> LVLPRI1_R { + LVLPRI1_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 15 - Level 1 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen1(&self) -> RRLVLEN1_R { + RRLVLEN1_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:19 - Level 2 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri2(&self) -> LVLPRI2_R { + LVLPRI2_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bit 23 - Level 2 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen2(&self) -> RRLVLEN2_R { + RRLVLEN2_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bits 24:27 - Level 3 Channel Priority Number"] + #[inline(always)] + pub fn lvlpri3(&self) -> LVLPRI3_R { + LVLPRI3_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 31 - Level 3 Round-Robin Scheduling Enable"] + #[inline(always)] + pub fn rrlvlen3(&self) -> RRLVLEN3_R { + RRLVLEN3_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Level 0 Channel Priority Number"] + #[inline(always)] + #[must_use] + pub fn lvlpri0(&mut self) -> LVLPRI0_W<0> { + LVLPRI0_W::new(self) + } + #[doc = "Bit 7 - Level 0 Round-Robin Scheduling Enable"] + #[inline(always)] + #[must_use] + pub fn rrlvlen0(&mut self) -> RRLVLEN0_W<7> { + RRLVLEN0_W::new(self) + } + #[doc = "Bits 8:11 - Level 1 Channel Priority Number"] + #[inline(always)] + #[must_use] + pub fn lvlpri1(&mut self) -> LVLPRI1_W<8> { + LVLPRI1_W::new(self) + } + #[doc = "Bit 15 - Level 1 Round-Robin Scheduling Enable"] + #[inline(always)] + #[must_use] + pub fn rrlvlen1(&mut self) -> RRLVLEN1_W<15> { + RRLVLEN1_W::new(self) + } + #[doc = "Bits 16:19 - Level 2 Channel Priority Number"] + #[inline(always)] + #[must_use] + pub fn lvlpri2(&mut self) -> LVLPRI2_W<16> { + LVLPRI2_W::new(self) + } + #[doc = "Bit 23 - Level 2 Round-Robin Scheduling Enable"] + #[inline(always)] + #[must_use] + pub fn rrlvlen2(&mut self) -> RRLVLEN2_W<23> { + RRLVLEN2_W::new(self) + } + #[doc = "Bits 24:27 - Level 3 Channel Priority Number"] + #[inline(always)] + #[must_use] + pub fn lvlpri3(&mut self) -> LVLPRI3_W<24> { + LVLPRI3_W::new(self) + } + #[doc = "Bit 31 - Level 3 Round-Robin Scheduling Enable"] + #[inline(always)] + #[must_use] + pub fn rrlvlen3(&mut self) -> RRLVLEN3_W<31> { + RRLVLEN3_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Priority Control 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [prictrl0](index.html) module"] +pub struct PRICTRL0_SPEC; +impl crate::RegisterSpec for PRICTRL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [prictrl0::R](R) reader structure"] +impl crate::Readable for PRICTRL0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [prictrl0::W](W) writer structure"] +impl crate::Writable for PRICTRL0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PRICTRL0 to value 0"] +impl crate::Resettable for PRICTRL0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/dmac/qosctrl.rs b/pac/atsaml22j/src/dmac/qosctrl.rs new file mode 100644 index 000000000000..94792503f899 --- /dev/null +++ b/pac/atsaml22j/src/dmac/qosctrl.rs @@ -0,0 +1,335 @@ +#[doc = "Register `QOSCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `QOSCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WRBQOS` reader - Write-Back Quality of Service"] +pub type WRBQOS_R = crate::FieldReader; +#[doc = "Write-Back Quality of Service\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum WRBQOSSELECT_A { + #[doc = "0: Background (no sensitive operation)"] + DISABLE = 0, + #[doc = "1: Sensitive Bandwidth"] + LOW = 1, + #[doc = "2: Sensitive Latency"] + MEDIUM = 2, + #[doc = "3: Critical Latency"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WRBQOSSELECT_A) -> Self { + variant as _ + } +} +impl WRBQOS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WRBQOSSELECT_A { + match self.bits { + 0 => WRBQOSSELECT_A::DISABLE, + 1 => WRBQOSSELECT_A::LOW, + 2 => WRBQOSSELECT_A::MEDIUM, + 3 => WRBQOSSELECT_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == WRBQOSSELECT_A::DISABLE + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == WRBQOSSELECT_A::LOW + } + #[doc = "Checks if the value of the field is `MEDIUM`"] + #[inline(always)] + pub fn is_medium(&self) -> bool { + *self == WRBQOSSELECT_A::MEDIUM + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == WRBQOSSELECT_A::HIGH + } +} +#[doc = "Field `WRBQOS` writer - Write-Back Quality of Service"] +pub type WRBQOS_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u8, QOSCTRL_SPEC, u8, WRBQOSSELECT_A, 2, O>; +impl<'a, const O: u8> WRBQOS_W<'a, O> { + #[doc = "Background (no sensitive operation)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(WRBQOSSELECT_A::DISABLE) + } + #[doc = "Sensitive Bandwidth"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(WRBQOSSELECT_A::LOW) + } + #[doc = "Sensitive Latency"] + #[inline(always)] + pub fn medium(self) -> &'a mut W { + self.variant(WRBQOSSELECT_A::MEDIUM) + } + #[doc = "Critical Latency"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(WRBQOSSELECT_A::HIGH) + } +} +#[doc = "Field `FQOS` reader - Fetch Quality of Service"] +pub type FQOS_R = crate::FieldReader; +#[doc = "Fetch Quality of Service\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FQOSSELECT_A { + #[doc = "0: Background (no sensitive operation)"] + DISABLE = 0, + #[doc = "1: Sensitive Bandwidth"] + LOW = 1, + #[doc = "2: Sensitive Latency"] + MEDIUM = 2, + #[doc = "3: Critical Latency"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FQOSSELECT_A) -> Self { + variant as _ + } +} +impl FQOS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FQOSSELECT_A { + match self.bits { + 0 => FQOSSELECT_A::DISABLE, + 1 => FQOSSELECT_A::LOW, + 2 => FQOSSELECT_A::MEDIUM, + 3 => FQOSSELECT_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == FQOSSELECT_A::DISABLE + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == FQOSSELECT_A::LOW + } + #[doc = "Checks if the value of the field is `MEDIUM`"] + #[inline(always)] + pub fn is_medium(&self) -> bool { + *self == FQOSSELECT_A::MEDIUM + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == FQOSSELECT_A::HIGH + } +} +#[doc = "Field `FQOS` writer - Fetch Quality of Service"] +pub type FQOS_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u8, QOSCTRL_SPEC, u8, FQOSSELECT_A, 2, O>; +impl<'a, const O: u8> FQOS_W<'a, O> { + #[doc = "Background (no sensitive operation)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(FQOSSELECT_A::DISABLE) + } + #[doc = "Sensitive Bandwidth"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(FQOSSELECT_A::LOW) + } + #[doc = "Sensitive Latency"] + #[inline(always)] + pub fn medium(self) -> &'a mut W { + self.variant(FQOSSELECT_A::MEDIUM) + } + #[doc = "Critical Latency"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(FQOSSELECT_A::HIGH) + } +} +#[doc = "Field `DQOS` reader - Data Transfer Quality of Service"] +pub type DQOS_R = crate::FieldReader; +#[doc = "Data Transfer Quality of Service\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum DQOSSELECT_A { + #[doc = "0: Background (no sensitive operation)"] + DISABLE = 0, + #[doc = "1: Sensitive Bandwidth"] + LOW = 1, + #[doc = "2: Sensitive Latency"] + MEDIUM = 2, + #[doc = "3: Critical Latency"] + HIGH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DQOSSELECT_A) -> Self { + variant as _ + } +} +impl DQOS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DQOSSELECT_A { + match self.bits { + 0 => DQOSSELECT_A::DISABLE, + 1 => DQOSSELECT_A::LOW, + 2 => DQOSSELECT_A::MEDIUM, + 3 => DQOSSELECT_A::HIGH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == DQOSSELECT_A::DISABLE + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == DQOSSELECT_A::LOW + } + #[doc = "Checks if the value of the field is `MEDIUM`"] + #[inline(always)] + pub fn is_medium(&self) -> bool { + *self == DQOSSELECT_A::MEDIUM + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == DQOSSELECT_A::HIGH + } +} +#[doc = "Field `DQOS` writer - Data Transfer Quality of Service"] +pub type DQOS_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u8, QOSCTRL_SPEC, u8, DQOSSELECT_A, 2, O>; +impl<'a, const O: u8> DQOS_W<'a, O> { + #[doc = "Background (no sensitive operation)"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(DQOSSELECT_A::DISABLE) + } + #[doc = "Sensitive Bandwidth"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(DQOSSELECT_A::LOW) + } + #[doc = "Sensitive Latency"] + #[inline(always)] + pub fn medium(self) -> &'a mut W { + self.variant(DQOSSELECT_A::MEDIUM) + } + #[doc = "Critical Latency"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(DQOSSELECT_A::HIGH) + } +} +impl R { + #[doc = "Bits 0:1 - Write-Back Quality of Service"] + #[inline(always)] + pub fn wrbqos(&self) -> WRBQOS_R { + WRBQOS_R::new(self.bits & 3) + } + #[doc = "Bits 2:3 - Fetch Quality of Service"] + #[inline(always)] + pub fn fqos(&self) -> FQOS_R { + FQOS_R::new((self.bits >> 2) & 3) + } + #[doc = "Bits 4:5 - Data Transfer Quality of Service"] + #[inline(always)] + pub fn dqos(&self) -> DQOS_R { + DQOS_R::new((self.bits >> 4) & 3) + } +} +impl W { + #[doc = "Bits 0:1 - Write-Back Quality of Service"] + #[inline(always)] + #[must_use] + pub fn wrbqos(&mut self) -> WRBQOS_W<0> { + WRBQOS_W::new(self) + } + #[doc = "Bits 2:3 - Fetch Quality of Service"] + #[inline(always)] + #[must_use] + pub fn fqos(&mut self) -> FQOS_W<2> { + FQOS_W::new(self) + } + #[doc = "Bits 4:5 - Data Transfer Quality of Service"] + #[inline(always)] + #[must_use] + pub fn dqos(&mut self) -> DQOS_W<4> { + DQOS_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "QOS Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [qosctrl](index.html) module"] +pub struct QOSCTRL_SPEC; +impl crate::RegisterSpec for QOSCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [qosctrl::R](R) reader structure"] +impl crate::Readable for QOSCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [qosctrl::W](W) writer structure"] +impl crate::Writable for QOSCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets QOSCTRL to value 0x2a"] +impl crate::Resettable for QOSCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x2a; +} diff --git a/pac/atsaml22j/src/dmac/swtrigctrl.rs b/pac/atsaml22j/src/dmac/swtrigctrl.rs new file mode 100644 index 000000000000..92c8fe52c068 --- /dev/null +++ b/pac/atsaml22j/src/dmac/swtrigctrl.rs @@ -0,0 +1,305 @@ +#[doc = "Register `SWTRIGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SWTRIGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWTRIG0` reader - Channel 0 Software Trigger"] +pub type SWTRIG0_R = crate::BitReader; +#[doc = "Field `SWTRIG0` writer - Channel 0 Software Trigger"] +pub type SWTRIG0_W<'a, const O: u8> = crate::BitWriter<'a, u32, SWTRIGCTRL_SPEC, bool, O>; +#[doc = "Field `SWTRIG1` reader - Channel 1 Software Trigger"] +pub type SWTRIG1_R = crate::BitReader; +#[doc = "Field `SWTRIG1` writer - Channel 1 Software Trigger"] +pub type SWTRIG1_W<'a, const O: u8> = crate::BitWriter<'a, u32, SWTRIGCTRL_SPEC, bool, O>; +#[doc = "Field `SWTRIG2` reader - Channel 2 Software Trigger"] +pub type SWTRIG2_R = crate::BitReader; +#[doc = "Field `SWTRIG2` writer - Channel 2 Software Trigger"] +pub type SWTRIG2_W<'a, const O: u8> = crate::BitWriter<'a, u32, SWTRIGCTRL_SPEC, bool, O>; +#[doc = "Field `SWTRIG3` reader - Channel 3 Software Trigger"] +pub type SWTRIG3_R = crate::BitReader; +#[doc = "Field `SWTRIG3` writer - Channel 3 Software Trigger"] +pub type SWTRIG3_W<'a, const O: u8> = crate::BitWriter<'a, u32, SWTRIGCTRL_SPEC, bool, O>; +#[doc = "Field `SWTRIG4` reader - Channel 4 Software Trigger"] +pub type SWTRIG4_R = crate::BitReader; +#[doc = "Field `SWTRIG4` writer - Channel 4 Software Trigger"] +pub type SWTRIG4_W<'a, const O: u8> = crate::BitWriter<'a, u32, SWTRIGCTRL_SPEC, bool, O>; +#[doc = "Field `SWTRIG5` reader - Channel 5 Software Trigger"] +pub type SWTRIG5_R = crate::BitReader; +#[doc = "Field `SWTRIG5` writer - Channel 5 Software Trigger"] +pub type SWTRIG5_W<'a, const O: u8> = crate::BitWriter<'a, u32, SWTRIGCTRL_SPEC, bool, O>; +#[doc = "Field `SWTRIG6` reader - Channel 6 Software Trigger"] +pub type SWTRIG6_R = crate::BitReader; +#[doc = "Field `SWTRIG6` writer - Channel 6 Software Trigger"] +pub type SWTRIG6_W<'a, const O: u8> = crate::BitWriter<'a, u32, SWTRIGCTRL_SPEC, bool, O>; +#[doc = "Field `SWTRIG7` reader - Channel 7 Software Trigger"] +pub type SWTRIG7_R = crate::BitReader; +#[doc = "Field `SWTRIG7` writer - Channel 7 Software Trigger"] +pub type SWTRIG7_W<'a, const O: u8> = crate::BitWriter<'a, u32, SWTRIGCTRL_SPEC, bool, O>; +#[doc = "Field `SWTRIG8` reader - Channel 8 Software Trigger"] +pub type SWTRIG8_R = crate::BitReader; +#[doc = "Field `SWTRIG8` writer - Channel 8 Software Trigger"] +pub type SWTRIG8_W<'a, const O: u8> = crate::BitWriter<'a, u32, SWTRIGCTRL_SPEC, bool, O>; +#[doc = "Field `SWTRIG9` reader - Channel 9 Software Trigger"] +pub type SWTRIG9_R = crate::BitReader; +#[doc = "Field `SWTRIG9` writer - Channel 9 Software Trigger"] +pub type SWTRIG9_W<'a, const O: u8> = crate::BitWriter<'a, u32, SWTRIGCTRL_SPEC, bool, O>; +#[doc = "Field `SWTRIG10` reader - Channel 10 Software Trigger"] +pub type SWTRIG10_R = crate::BitReader; +#[doc = "Field `SWTRIG10` writer - Channel 10 Software Trigger"] +pub type SWTRIG10_W<'a, const O: u8> = crate::BitWriter<'a, u32, SWTRIGCTRL_SPEC, bool, O>; +#[doc = "Field `SWTRIG11` reader - Channel 11 Software Trigger"] +pub type SWTRIG11_R = crate::BitReader; +#[doc = "Field `SWTRIG11` writer - Channel 11 Software Trigger"] +pub type SWTRIG11_W<'a, const O: u8> = crate::BitWriter<'a, u32, SWTRIGCTRL_SPEC, bool, O>; +#[doc = "Field `SWTRIG12` reader - Channel 12 Software Trigger"] +pub type SWTRIG12_R = crate::BitReader; +#[doc = "Field `SWTRIG12` writer - Channel 12 Software Trigger"] +pub type SWTRIG12_W<'a, const O: u8> = crate::BitWriter<'a, u32, SWTRIGCTRL_SPEC, bool, O>; +#[doc = "Field `SWTRIG13` reader - Channel 13 Software Trigger"] +pub type SWTRIG13_R = crate::BitReader; +#[doc = "Field `SWTRIG13` writer - Channel 13 Software Trigger"] +pub type SWTRIG13_W<'a, const O: u8> = crate::BitWriter<'a, u32, SWTRIGCTRL_SPEC, bool, O>; +#[doc = "Field `SWTRIG14` reader - Channel 14 Software Trigger"] +pub type SWTRIG14_R = crate::BitReader; +#[doc = "Field `SWTRIG14` writer - Channel 14 Software Trigger"] +pub type SWTRIG14_W<'a, const O: u8> = crate::BitWriter<'a, u32, SWTRIGCTRL_SPEC, bool, O>; +#[doc = "Field `SWTRIG15` reader - Channel 15 Software Trigger"] +pub type SWTRIG15_R = crate::BitReader; +#[doc = "Field `SWTRIG15` writer - Channel 15 Software Trigger"] +pub type SWTRIG15_W<'a, const O: u8> = crate::BitWriter<'a, u32, SWTRIGCTRL_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Channel 0 Software Trigger"] + #[inline(always)] + pub fn swtrig0(&self) -> SWTRIG0_R { + SWTRIG0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Channel 1 Software Trigger"] + #[inline(always)] + pub fn swtrig1(&self) -> SWTRIG1_R { + SWTRIG1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Channel 2 Software Trigger"] + #[inline(always)] + pub fn swtrig2(&self) -> SWTRIG2_R { + SWTRIG2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Channel 3 Software Trigger"] + #[inline(always)] + pub fn swtrig3(&self) -> SWTRIG3_R { + SWTRIG3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Channel 4 Software Trigger"] + #[inline(always)] + pub fn swtrig4(&self) -> SWTRIG4_R { + SWTRIG4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Channel 5 Software Trigger"] + #[inline(always)] + pub fn swtrig5(&self) -> SWTRIG5_R { + SWTRIG5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Channel 6 Software Trigger"] + #[inline(always)] + pub fn swtrig6(&self) -> SWTRIG6_R { + SWTRIG6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Channel 7 Software Trigger"] + #[inline(always)] + pub fn swtrig7(&self) -> SWTRIG7_R { + SWTRIG7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Channel 8 Software Trigger"] + #[inline(always)] + pub fn swtrig8(&self) -> SWTRIG8_R { + SWTRIG8_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Channel 9 Software Trigger"] + #[inline(always)] + pub fn swtrig9(&self) -> SWTRIG9_R { + SWTRIG9_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Channel 10 Software Trigger"] + #[inline(always)] + pub fn swtrig10(&self) -> SWTRIG10_R { + SWTRIG10_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Channel 11 Software Trigger"] + #[inline(always)] + pub fn swtrig11(&self) -> SWTRIG11_R { + SWTRIG11_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Channel 12 Software Trigger"] + #[inline(always)] + pub fn swtrig12(&self) -> SWTRIG12_R { + SWTRIG12_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Channel 13 Software Trigger"] + #[inline(always)] + pub fn swtrig13(&self) -> SWTRIG13_R { + SWTRIG13_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Channel 14 Software Trigger"] + #[inline(always)] + pub fn swtrig14(&self) -> SWTRIG14_R { + SWTRIG14_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Channel 15 Software Trigger"] + #[inline(always)] + pub fn swtrig15(&self) -> SWTRIG15_R { + SWTRIG15_R::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Software Trigger"] + #[inline(always)] + #[must_use] + pub fn swtrig0(&mut self) -> SWTRIG0_W<0> { + SWTRIG0_W::new(self) + } + #[doc = "Bit 1 - Channel 1 Software Trigger"] + #[inline(always)] + #[must_use] + pub fn swtrig1(&mut self) -> SWTRIG1_W<1> { + SWTRIG1_W::new(self) + } + #[doc = "Bit 2 - Channel 2 Software Trigger"] + #[inline(always)] + #[must_use] + pub fn swtrig2(&mut self) -> SWTRIG2_W<2> { + SWTRIG2_W::new(self) + } + #[doc = "Bit 3 - Channel 3 Software Trigger"] + #[inline(always)] + #[must_use] + pub fn swtrig3(&mut self) -> SWTRIG3_W<3> { + SWTRIG3_W::new(self) + } + #[doc = "Bit 4 - Channel 4 Software Trigger"] + #[inline(always)] + #[must_use] + pub fn swtrig4(&mut self) -> SWTRIG4_W<4> { + SWTRIG4_W::new(self) + } + #[doc = "Bit 5 - Channel 5 Software Trigger"] + #[inline(always)] + #[must_use] + pub fn swtrig5(&mut self) -> SWTRIG5_W<5> { + SWTRIG5_W::new(self) + } + #[doc = "Bit 6 - Channel 6 Software Trigger"] + #[inline(always)] + #[must_use] + pub fn swtrig6(&mut self) -> SWTRIG6_W<6> { + SWTRIG6_W::new(self) + } + #[doc = "Bit 7 - Channel 7 Software Trigger"] + #[inline(always)] + #[must_use] + pub fn swtrig7(&mut self) -> SWTRIG7_W<7> { + SWTRIG7_W::new(self) + } + #[doc = "Bit 8 - Channel 8 Software Trigger"] + #[inline(always)] + #[must_use] + pub fn swtrig8(&mut self) -> SWTRIG8_W<8> { + SWTRIG8_W::new(self) + } + #[doc = "Bit 9 - Channel 9 Software Trigger"] + #[inline(always)] + #[must_use] + pub fn swtrig9(&mut self) -> SWTRIG9_W<9> { + SWTRIG9_W::new(self) + } + #[doc = "Bit 10 - Channel 10 Software Trigger"] + #[inline(always)] + #[must_use] + pub fn swtrig10(&mut self) -> SWTRIG10_W<10> { + SWTRIG10_W::new(self) + } + #[doc = "Bit 11 - Channel 11 Software Trigger"] + #[inline(always)] + #[must_use] + pub fn swtrig11(&mut self) -> SWTRIG11_W<11> { + SWTRIG11_W::new(self) + } + #[doc = "Bit 12 - Channel 12 Software Trigger"] + #[inline(always)] + #[must_use] + pub fn swtrig12(&mut self) -> SWTRIG12_W<12> { + SWTRIG12_W::new(self) + } + #[doc = "Bit 13 - Channel 13 Software Trigger"] + #[inline(always)] + #[must_use] + pub fn swtrig13(&mut self) -> SWTRIG13_W<13> { + SWTRIG13_W::new(self) + } + #[doc = "Bit 14 - Channel 14 Software Trigger"] + #[inline(always)] + #[must_use] + pub fn swtrig14(&mut self) -> SWTRIG14_W<14> { + SWTRIG14_W::new(self) + } + #[doc = "Bit 15 - Channel 15 Software Trigger"] + #[inline(always)] + #[must_use] + pub fn swtrig15(&mut self) -> SWTRIG15_W<15> { + SWTRIG15_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Software Trigger Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [swtrigctrl](index.html) module"] +pub struct SWTRIGCTRL_SPEC; +impl crate::RegisterSpec for SWTRIGCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [swtrigctrl::R](R) reader structure"] +impl crate::Readable for SWTRIGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [swtrigctrl::W](W) writer structure"] +impl crate::Writable for SWTRIGCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SWTRIGCTRL to value 0"] +impl crate::Resettable for SWTRIGCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/dmac/wrbaddr.rs b/pac/atsaml22j/src/dmac/wrbaddr.rs new file mode 100644 index 000000000000..273b098bfcff --- /dev/null +++ b/pac/atsaml22j/src/dmac/wrbaddr.rs @@ -0,0 +1,80 @@ +#[doc = "Register `WRBADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WRBADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WRBADDR` reader - Write-Back Memory Base Address"] +pub type WRBADDR_R = crate::FieldReader; +#[doc = "Field `WRBADDR` writer - Write-Back Memory Base Address"] +pub type WRBADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, WRBADDR_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - Write-Back Memory Base Address"] + #[inline(always)] + pub fn wrbaddr(&self) -> WRBADDR_R { + WRBADDR_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Write-Back Memory Base Address"] + #[inline(always)] + #[must_use] + pub fn wrbaddr(&mut self) -> WRBADDR_W<0> { + WRBADDR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Write-Back Memory Section Base Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wrbaddr](index.html) module"] +pub struct WRBADDR_SPEC; +impl crate::RegisterSpec for WRBADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wrbaddr::R](R) reader structure"] +impl crate::Readable for WRBADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wrbaddr::W](W) writer structure"] +impl crate::Writable for WRBADDR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets WRBADDR to value 0"] +impl crate::Resettable for WRBADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/dsu.rs b/pac/atsaml22j/src/dsu.rs new file mode 100644 index 000000000000..c45782df6ccb --- /dev/null +++ b/pac/atsaml22j/src/dsu.rs @@ -0,0 +1,158 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrl: CTRL, + #[doc = "0x01 - Status A"] + pub statusa: STATUSA, + #[doc = "0x02 - Status B"] + pub statusb: STATUSB, + _reserved3: [u8; 0x01], + #[doc = "0x04 - Address"] + pub addr: ADDR, + #[doc = "0x08 - Length"] + pub length: LENGTH, + #[doc = "0x0c - Data"] + pub data: DATA, + #[doc = "0x10..0x18 - Debug Communication Channel n"] + pub dcc: [DCC; 2], + #[doc = "0x18 - Device Identification"] + pub did: DID, + _reserved8: [u8; 0xd4], + #[doc = "0xf0..0xf8 - Device Configuration"] + pub dcfg: [DCFG; 2], + _reserved9: [u8; 0x0f08], + #[doc = "0x1000 - CoreSight ROM Table Entry 0"] + pub entry0: ENTRY0, + #[doc = "0x1004 - CoreSight ROM Table Entry 1"] + pub entry1: ENTRY1, + #[doc = "0x1008 - CoreSight ROM Table End"] + pub end: END, + _reserved12: [u8; 0x0fc0], + #[doc = "0x1fcc - CoreSight ROM Table Memory Type"] + pub memtype: MEMTYPE, + #[doc = "0x1fd0 - Peripheral Identification 4"] + pub pid4: PID4, + #[doc = "0x1fd4 - Peripheral Identification 5"] + pub pid5: PID5, + #[doc = "0x1fd8 - Peripheral Identification 6"] + pub pid6: PID6, + #[doc = "0x1fdc - Peripheral Identification 7"] + pub pid7: PID7, + #[doc = "0x1fe0 - Peripheral Identification 0"] + pub pid0: PID0, + #[doc = "0x1fe4 - Peripheral Identification 1"] + pub pid1: PID1, + #[doc = "0x1fe8 - Peripheral Identification 2"] + pub pid2: PID2, + #[doc = "0x1fec - Peripheral Identification 3"] + pub pid3: PID3, + #[doc = "0x1ff0 - Component Identification 0"] + pub cid0: CID0, + #[doc = "0x1ff4 - Component Identification 1"] + pub cid1: CID1, + #[doc = "0x1ff8 - Component Identification 2"] + pub cid2: CID2, + #[doc = "0x1ffc - Component Identification 3"] + pub cid3: CID3, +} +#[doc = "CTRL (w) register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "STATUSA (rw) register accessor: an alias for `Reg`"] +pub type STATUSA = crate::Reg; +#[doc = "Status A"] +pub mod statusa; +#[doc = "STATUSB (r) register accessor: an alias for `Reg`"] +pub type STATUSB = crate::Reg; +#[doc = "Status B"] +pub mod statusb; +#[doc = "ADDR (rw) register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "Address"] +pub mod addr; +#[doc = "LENGTH (rw) register accessor: an alias for `Reg`"] +pub type LENGTH = crate::Reg; +#[doc = "Length"] +pub mod length; +#[doc = "DATA (rw) register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "Data"] +pub mod data; +#[doc = "DCC (rw) register accessor: an alias for `Reg`"] +pub type DCC = crate::Reg; +#[doc = "Debug Communication Channel n"] +pub mod dcc; +#[doc = "DID (r) register accessor: an alias for `Reg`"] +pub type DID = crate::Reg; +#[doc = "Device Identification"] +pub mod did; +#[doc = "DCFG (rw) register accessor: an alias for `Reg`"] +pub type DCFG = crate::Reg; +#[doc = "Device Configuration"] +pub mod dcfg; +#[doc = "ENTRY0 (r) register accessor: an alias for `Reg`"] +pub type ENTRY0 = crate::Reg; +#[doc = "CoreSight ROM Table Entry 0"] +pub mod entry0; +#[doc = "ENTRY1 (r) register accessor: an alias for `Reg`"] +pub type ENTRY1 = crate::Reg; +#[doc = "CoreSight ROM Table Entry 1"] +pub mod entry1; +#[doc = "END (r) register accessor: an alias for `Reg`"] +pub type END = crate::Reg; +#[doc = "CoreSight ROM Table End"] +pub mod end; +#[doc = "MEMTYPE (r) register accessor: an alias for `Reg`"] +pub type MEMTYPE = crate::Reg; +#[doc = "CoreSight ROM Table Memory Type"] +pub mod memtype; +#[doc = "PID4 (r) register accessor: an alias for `Reg`"] +pub type PID4 = crate::Reg; +#[doc = "Peripheral Identification 4"] +pub mod pid4; +#[doc = "PID5 (r) register accessor: an alias for `Reg`"] +pub type PID5 = crate::Reg; +#[doc = "Peripheral Identification 5"] +pub mod pid5; +#[doc = "PID6 (r) register accessor: an alias for `Reg`"] +pub type PID6 = crate::Reg; +#[doc = "Peripheral Identification 6"] +pub mod pid6; +#[doc = "PID7 (r) register accessor: an alias for `Reg`"] +pub type PID7 = crate::Reg; +#[doc = "Peripheral Identification 7"] +pub mod pid7; +#[doc = "PID0 (r) register accessor: an alias for `Reg`"] +pub type PID0 = crate::Reg; +#[doc = "Peripheral Identification 0"] +pub mod pid0; +#[doc = "PID1 (r) register accessor: an alias for `Reg`"] +pub type PID1 = crate::Reg; +#[doc = "Peripheral Identification 1"] +pub mod pid1; +#[doc = "PID2 (r) register accessor: an alias for `Reg`"] +pub type PID2 = crate::Reg; +#[doc = "Peripheral Identification 2"] +pub mod pid2; +#[doc = "PID3 (r) register accessor: an alias for `Reg`"] +pub type PID3 = crate::Reg; +#[doc = "Peripheral Identification 3"] +pub mod pid3; +#[doc = "CID0 (r) register accessor: an alias for `Reg`"] +pub type CID0 = crate::Reg; +#[doc = "Component Identification 0"] +pub mod cid0; +#[doc = "CID1 (r) register accessor: an alias for `Reg`"] +pub type CID1 = crate::Reg; +#[doc = "Component Identification 1"] +pub mod cid1; +#[doc = "CID2 (r) register accessor: an alias for `Reg`"] +pub type CID2 = crate::Reg; +#[doc = "Component Identification 2"] +pub mod cid2; +#[doc = "CID3 (r) register accessor: an alias for `Reg`"] +pub type CID3 = crate::Reg; +#[doc = "Component Identification 3"] +pub mod cid3; diff --git a/pac/atsaml22j/src/dsu/addr.rs b/pac/atsaml22j/src/dsu/addr.rs new file mode 100644 index 000000000000..4a8728ec2f94 --- /dev/null +++ b/pac/atsaml22j/src/dsu/addr.rs @@ -0,0 +1,95 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `AMOD` reader - Access Mode"] +pub type AMOD_R = crate::FieldReader; +#[doc = "Field `AMOD` writer - Access Mode"] +pub type AMOD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ADDR_SPEC, u8, u8, 2, O>; +#[doc = "Field `ADDR` reader - Address"] +pub type ADDR_R = crate::FieldReader; +#[doc = "Field `ADDR` writer - Address"] +pub type ADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ADDR_SPEC, u32, u32, 30, O>; +impl R { + #[doc = "Bits 0:1 - Access Mode"] + #[inline(always)] + pub fn amod(&self) -> AMOD_R { + AMOD_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:31 - Address"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits >> 2) & 0x3fff_ffff) + } +} +impl W { + #[doc = "Bits 0:1 - Access Mode"] + #[inline(always)] + #[must_use] + pub fn amod(&mut self) -> AMOD_W<0> { + AMOD_W::new(self) + } + #[doc = "Bits 2:31 - Address"] + #[inline(always)] + #[must_use] + pub fn addr(&mut self) -> ADDR_W<2> { + ADDR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/dsu/cid0.rs b/pac/atsaml22j/src/dsu/cid0.rs new file mode 100644 index 000000000000..d6d06f8910ab --- /dev/null +++ b/pac/atsaml22j/src/dsu/cid0.rs @@ -0,0 +1,37 @@ +#[doc = "Register `CID0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PREAMBLEB0` reader - Preamble Byte 0"] +pub type PREAMBLEB0_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Preamble Byte 0"] + #[inline(always)] + pub fn preambleb0(&self) -> PREAMBLEB0_R { + PREAMBLEB0_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "Component Identification 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid0](index.html) module"] +pub struct CID0_SPEC; +impl crate::RegisterSpec for CID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid0::R](R) reader structure"] +impl crate::Readable for CID0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID0 to value 0x0d"] +impl crate::Resettable for CID0_SPEC { + const RESET_VALUE: Self::Ux = 0x0d; +} diff --git a/pac/atsaml22j/src/dsu/cid1.rs b/pac/atsaml22j/src/dsu/cid1.rs new file mode 100644 index 000000000000..eb1802e2f971 --- /dev/null +++ b/pac/atsaml22j/src/dsu/cid1.rs @@ -0,0 +1,44 @@ +#[doc = "Register `CID1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PREAMBLE` reader - Preamble"] +pub type PREAMBLE_R = crate::FieldReader; +#[doc = "Field `CCLASS` reader - Component Class"] +pub type CCLASS_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Preamble"] + #[inline(always)] + pub fn preamble(&self) -> PREAMBLE_R { + PREAMBLE_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Component Class"] + #[inline(always)] + pub fn cclass(&self) -> CCLASS_R { + CCLASS_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Component Identification 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid1](index.html) module"] +pub struct CID1_SPEC; +impl crate::RegisterSpec for CID1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid1::R](R) reader structure"] +impl crate::Readable for CID1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID1 to value 0x10"] +impl crate::Resettable for CID1_SPEC { + const RESET_VALUE: Self::Ux = 0x10; +} diff --git a/pac/atsaml22j/src/dsu/cid2.rs b/pac/atsaml22j/src/dsu/cid2.rs new file mode 100644 index 000000000000..a9fc6bdedc5b --- /dev/null +++ b/pac/atsaml22j/src/dsu/cid2.rs @@ -0,0 +1,37 @@ +#[doc = "Register `CID2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PREAMBLEB2` reader - Preamble Byte 2"] +pub type PREAMBLEB2_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Preamble Byte 2"] + #[inline(always)] + pub fn preambleb2(&self) -> PREAMBLEB2_R { + PREAMBLEB2_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "Component Identification 2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid2](index.html) module"] +pub struct CID2_SPEC; +impl crate::RegisterSpec for CID2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid2::R](R) reader structure"] +impl crate::Readable for CID2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID2 to value 0x05"] +impl crate::Resettable for CID2_SPEC { + const RESET_VALUE: Self::Ux = 0x05; +} diff --git a/pac/atsaml22j/src/dsu/cid3.rs b/pac/atsaml22j/src/dsu/cid3.rs new file mode 100644 index 000000000000..080dd4c63f39 --- /dev/null +++ b/pac/atsaml22j/src/dsu/cid3.rs @@ -0,0 +1,37 @@ +#[doc = "Register `CID3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PREAMBLEB3` reader - Preamble Byte 3"] +pub type PREAMBLEB3_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Preamble Byte 3"] + #[inline(always)] + pub fn preambleb3(&self) -> PREAMBLEB3_R { + PREAMBLEB3_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "Component Identification 3\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid3](index.html) module"] +pub struct CID3_SPEC; +impl crate::RegisterSpec for CID3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid3::R](R) reader structure"] +impl crate::Readable for CID3_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID3 to value 0xb1"] +impl crate::Resettable for CID3_SPEC { + const RESET_VALUE: Self::Ux = 0xb1; +} diff --git a/pac/atsaml22j/src/dsu/ctrl.rs b/pac/atsaml22j/src/dsu/ctrl.rs new file mode 100644 index 000000000000..93c417c2da60 --- /dev/null +++ b/pac/atsaml22j/src/dsu/ctrl.rs @@ -0,0 +1,92 @@ +#[doc = "Register `CTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub type SWRST_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRL_SPEC, bool, O>; +#[doc = "Field `CRC` writer - 32-bit Cyclic Redundancy Code"] +pub type CRC_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRL_SPEC, bool, O>; +#[doc = "Field `MBIST` writer - Memory built-in self-test"] +pub type MBIST_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRL_SPEC, bool, O>; +#[doc = "Field `CE` writer - Chip-Erase"] +pub type CE_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRL_SPEC, bool, O>; +#[doc = "Field `ARR` writer - Auxiliary Row Read"] +pub type ARR_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRL_SPEC, bool, O>; +#[doc = "Field `SMSA` writer - Start Memory Stream Access"] +pub type SMSA_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRL_SPEC, bool, O>; +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + #[must_use] + pub fn swrst(&mut self) -> SWRST_W<0> { + SWRST_W::new(self) + } + #[doc = "Bit 2 - 32-bit Cyclic Redundancy Code"] + #[inline(always)] + #[must_use] + pub fn crc(&mut self) -> CRC_W<2> { + CRC_W::new(self) + } + #[doc = "Bit 3 - Memory built-in self-test"] + #[inline(always)] + #[must_use] + pub fn mbist(&mut self) -> MBIST_W<3> { + MBIST_W::new(self) + } + #[doc = "Bit 4 - Chip-Erase"] + #[inline(always)] + #[must_use] + pub fn ce(&mut self) -> CE_W<4> { + CE_W::new(self) + } + #[doc = "Bit 6 - Auxiliary Row Read"] + #[inline(always)] + #[must_use] + pub fn arr(&mut self) -> ARR_W<6> { + ARR_W::new(self) + } + #[doc = "Bit 7 - Start Memory Stream Access"] + #[inline(always)] + #[must_use] + pub fn smsa(&mut self) -> SMSA_W<7> { + SMSA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRL to value 0"] +impl crate::Resettable for CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/dsu/data.rs b/pac/atsaml22j/src/dsu/data.rs new file mode 100644 index 000000000000..a3af669cc9a9 --- /dev/null +++ b/pac/atsaml22j/src/dsu/data.rs @@ -0,0 +1,80 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data"] +pub type DATA_R = crate::FieldReader; +#[doc = "Field `DATA` writer - Data"] +pub type DATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DATA_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - Data"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Data"] + #[inline(always)] + #[must_use] + pub fn data(&mut self) -> DATA_W<0> { + DATA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/dsu/dcc.rs b/pac/atsaml22j/src/dsu/dcc.rs new file mode 100644 index 000000000000..51d4bafd14f2 --- /dev/null +++ b/pac/atsaml22j/src/dsu/dcc.rs @@ -0,0 +1,80 @@ +#[doc = "Register `DCC%s` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DCC%s` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data"] +pub type DATA_R = crate::FieldReader; +#[doc = "Field `DATA` writer - Data"] +pub type DATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DCC_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - Data"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Data"] + #[inline(always)] + #[must_use] + pub fn data(&mut self) -> DATA_W<0> { + DATA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Communication Channel n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dcc](index.html) module"] +pub struct DCC_SPEC; +impl crate::RegisterSpec for DCC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dcc::R](R) reader structure"] +impl crate::Readable for DCC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dcc::W](W) writer structure"] +impl crate::Writable for DCC_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DCC%s to value 0"] +impl crate::Resettable for DCC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/dsu/dcfg.rs b/pac/atsaml22j/src/dsu/dcfg.rs new file mode 100644 index 000000000000..8ae1a079203f --- /dev/null +++ b/pac/atsaml22j/src/dsu/dcfg.rs @@ -0,0 +1,80 @@ +#[doc = "Register `DCFG%s` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DCFG%s` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DCFG` reader - Device Configuration"] +pub type DCFG_R = crate::FieldReader; +#[doc = "Field `DCFG` writer - Device Configuration"] +pub type DCFG_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DCFG_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - Device Configuration"] + #[inline(always)] + pub fn dcfg(&self) -> DCFG_R { + DCFG_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Device Configuration"] + #[inline(always)] + #[must_use] + pub fn dcfg(&mut self) -> DCFG_W<0> { + DCFG_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Device Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dcfg](index.html) module"] +pub struct DCFG_SPEC; +impl crate::RegisterSpec for DCFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dcfg::R](R) reader structure"] +impl crate::Readable for DCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dcfg::W](W) writer structure"] +impl crate::Writable for DCFG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DCFG%s to value 0"] +impl crate::Resettable for DCFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/dsu/did.rs b/pac/atsaml22j/src/dsu/did.rs new file mode 100644 index 000000000000..112c0a332a84 --- /dev/null +++ b/pac/atsaml22j/src/dsu/did.rs @@ -0,0 +1,196 @@ +#[doc = "Register `DID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `DEVSEL` reader - Device Select"] +pub type DEVSEL_R = crate::FieldReader; +#[doc = "Field `REVISION` reader - Revision Number"] +pub type REVISION_R = crate::FieldReader; +#[doc = "Field `DIE` reader - Die Number"] +pub type DIE_R = crate::FieldReader; +#[doc = "Field `SERIES` reader - Series"] +pub type SERIES_R = crate::FieldReader; +#[doc = "Series\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SERIESSELECT_A { + #[doc = "0: Cortex-M0+ processor, basic feature set"] + _0 = 0, + #[doc = "1: Cortex-M0+ processor, USB"] + _1 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SERIESSELECT_A) -> Self { + variant as _ + } +} +impl SERIES_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SERIESSELECT_A::_0), + 1 => Some(SERIESSELECT_A::_1), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_0`"] + #[inline(always)] + pub fn is_0(&self) -> bool { + *self == SERIESSELECT_A::_0 + } + #[doc = "Checks if the value of the field is `_1`"] + #[inline(always)] + pub fn is_1(&self) -> bool { + *self == SERIESSELECT_A::_1 + } +} +#[doc = "Field `FAMILY` reader - Family"] +pub type FAMILY_R = crate::FieldReader; +#[doc = "Family\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FAMILYSELECT_A { + #[doc = "0: General purpose microcontroller"] + _0 = 0, + #[doc = "1: PicoPower"] + _1 = 1, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FAMILYSELECT_A) -> Self { + variant as _ + } +} +impl FAMILY_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FAMILYSELECT_A::_0), + 1 => Some(FAMILYSELECT_A::_1), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_0`"] + #[inline(always)] + pub fn is_0(&self) -> bool { + *self == FAMILYSELECT_A::_0 + } + #[doc = "Checks if the value of the field is `_1`"] + #[inline(always)] + pub fn is_1(&self) -> bool { + *self == FAMILYSELECT_A::_1 + } +} +#[doc = "Field `PROCESSOR` reader - Processor"] +pub type PROCESSOR_R = crate::FieldReader; +#[doc = "Processor\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum PROCESSORSELECT_A { + #[doc = "0: Cortex-M0"] + _0 = 0, + #[doc = "1: Cortex-M0+"] + _1 = 1, + #[doc = "2: Cortex-M3"] + _2 = 2, + #[doc = "3: Cortex-M4"] + _3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PROCESSORSELECT_A) -> Self { + variant as _ + } +} +impl PROCESSOR_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PROCESSORSELECT_A::_0), + 1 => Some(PROCESSORSELECT_A::_1), + 2 => Some(PROCESSORSELECT_A::_2), + 3 => Some(PROCESSORSELECT_A::_3), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_0`"] + #[inline(always)] + pub fn is_0(&self) -> bool { + *self == PROCESSORSELECT_A::_0 + } + #[doc = "Checks if the value of the field is `_1`"] + #[inline(always)] + pub fn is_1(&self) -> bool { + *self == PROCESSORSELECT_A::_1 + } + #[doc = "Checks if the value of the field is `_2`"] + #[inline(always)] + pub fn is_2(&self) -> bool { + *self == PROCESSORSELECT_A::_2 + } + #[doc = "Checks if the value of the field is `_3`"] + #[inline(always)] + pub fn is_3(&self) -> bool { + *self == PROCESSORSELECT_A::_3 + } +} +impl R { + #[doc = "Bits 0:7 - Device Select"] + #[inline(always)] + pub fn devsel(&self) -> DEVSEL_R { + DEVSEL_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:11 - Revision Number"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bits 12:15 - Die Number"] + #[inline(always)] + pub fn die(&self) -> DIE_R { + DIE_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:21 - Series"] + #[inline(always)] + pub fn series(&self) -> SERIES_R { + SERIES_R::new(((self.bits >> 16) & 0x3f) as u8) + } + #[doc = "Bits 23:27 - Family"] + #[inline(always)] + pub fn family(&self) -> FAMILY_R { + FAMILY_R::new(((self.bits >> 23) & 0x1f) as u8) + } + #[doc = "Bits 28:31 - Processor"] + #[inline(always)] + pub fn processor(&self) -> PROCESSOR_R { + PROCESSOR_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +#[doc = "Device Identification\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [did](index.html) module"] +pub struct DID_SPEC; +impl crate::RegisterSpec for DID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [did::R](R) reader structure"] +impl crate::Readable for DID_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DID to value 0x1082_0105"] +impl crate::Resettable for DID_SPEC { + const RESET_VALUE: Self::Ux = 0x1082_0105; +} diff --git a/pac/atsaml22j/src/dsu/end.rs b/pac/atsaml22j/src/dsu/end.rs new file mode 100644 index 000000000000..32603c5ece33 --- /dev/null +++ b/pac/atsaml22j/src/dsu/end.rs @@ -0,0 +1,37 @@ +#[doc = "Register `END` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `END` reader - End Marker"] +pub type END_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - End Marker"] + #[inline(always)] + pub fn end(&self) -> END_R { + END_R::new(self.bits) + } +} +#[doc = "CoreSight ROM Table End\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [end](index.html) module"] +pub struct END_SPEC; +impl crate::RegisterSpec for END_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [end::R](R) reader structure"] +impl crate::Readable for END_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets END to value 0"] +impl crate::Resettable for END_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/dsu/entry0.rs b/pac/atsaml22j/src/dsu/entry0.rs new file mode 100644 index 000000000000..d67846b3e8de --- /dev/null +++ b/pac/atsaml22j/src/dsu/entry0.rs @@ -0,0 +1,51 @@ +#[doc = "Register `ENTRY0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `EPRES` reader - Entry Present"] +pub type EPRES_R = crate::BitReader; +#[doc = "Field `FMT` reader - Format"] +pub type FMT_R = crate::BitReader; +#[doc = "Field `ADDOFF` reader - Address Offset"] +pub type ADDOFF_R = crate::FieldReader; +impl R { + #[doc = "Bit 0 - Entry Present"] + #[inline(always)] + pub fn epres(&self) -> EPRES_R { + EPRES_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Format"] + #[inline(always)] + pub fn fmt(&self) -> FMT_R { + FMT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 12:31 - Address Offset"] + #[inline(always)] + pub fn addoff(&self) -> ADDOFF_R { + ADDOFF_R::new((self.bits >> 12) & 0x000f_ffff) + } +} +#[doc = "CoreSight ROM Table Entry 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [entry0](index.html) module"] +pub struct ENTRY0_SPEC; +impl crate::RegisterSpec for ENTRY0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [entry0::R](R) reader structure"] +impl crate::Readable for ENTRY0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets ENTRY0 to value 0x9f0f_c002"] +impl crate::Resettable for ENTRY0_SPEC { + const RESET_VALUE: Self::Ux = 0x9f0f_c002; +} diff --git a/pac/atsaml22j/src/dsu/entry1.rs b/pac/atsaml22j/src/dsu/entry1.rs new file mode 100644 index 000000000000..b972ca58e2c4 --- /dev/null +++ b/pac/atsaml22j/src/dsu/entry1.rs @@ -0,0 +1,28 @@ +#[doc = "Register `ENTRY1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "CoreSight ROM Table Entry 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [entry1](index.html) module"] +pub struct ENTRY1_SPEC; +impl crate::RegisterSpec for ENTRY1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [entry1::R](R) reader structure"] +impl crate::Readable for ENTRY1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets ENTRY1 to value 0x7002"] +impl crate::Resettable for ENTRY1_SPEC { + const RESET_VALUE: Self::Ux = 0x7002; +} diff --git a/pac/atsaml22j/src/dsu/length.rs b/pac/atsaml22j/src/dsu/length.rs new file mode 100644 index 000000000000..b63210fcbd87 --- /dev/null +++ b/pac/atsaml22j/src/dsu/length.rs @@ -0,0 +1,80 @@ +#[doc = "Register `LENGTH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LENGTH` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LENGTH` reader - Length"] +pub type LENGTH_R = crate::FieldReader; +#[doc = "Field `LENGTH` writer - Length"] +pub type LENGTH_W<'a, const O: u8> = crate::FieldWriter<'a, u32, LENGTH_SPEC, u32, u32, 30, O>; +impl R { + #[doc = "Bits 2:31 - Length"] + #[inline(always)] + pub fn length(&self) -> LENGTH_R { + LENGTH_R::new((self.bits >> 2) & 0x3fff_ffff) + } +} +impl W { + #[doc = "Bits 2:31 - Length"] + #[inline(always)] + #[must_use] + pub fn length(&mut self) -> LENGTH_W<2> { + LENGTH_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Length\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [length](index.html) module"] +pub struct LENGTH_SPEC; +impl crate::RegisterSpec for LENGTH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [length::R](R) reader structure"] +impl crate::Readable for LENGTH_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [length::W](W) writer structure"] +impl crate::Writable for LENGTH_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LENGTH to value 0"] +impl crate::Resettable for LENGTH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/dsu/memtype.rs b/pac/atsaml22j/src/dsu/memtype.rs new file mode 100644 index 000000000000..bca2245622d5 --- /dev/null +++ b/pac/atsaml22j/src/dsu/memtype.rs @@ -0,0 +1,37 @@ +#[doc = "Register `MEMTYPE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SMEMP` reader - System Memory Present"] +pub type SMEMP_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - System Memory Present"] + #[inline(always)] + pub fn smemp(&self) -> SMEMP_R { + SMEMP_R::new((self.bits & 1) != 0) + } +} +#[doc = "CoreSight ROM Table Memory Type\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [memtype](index.html) module"] +pub struct MEMTYPE_SPEC; +impl crate::RegisterSpec for MEMTYPE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [memtype::R](R) reader structure"] +impl crate::Readable for MEMTYPE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets MEMTYPE to value 0"] +impl crate::Resettable for MEMTYPE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/dsu/pid0.rs b/pac/atsaml22j/src/dsu/pid0.rs new file mode 100644 index 000000000000..0f1e42696ae6 --- /dev/null +++ b/pac/atsaml22j/src/dsu/pid0.rs @@ -0,0 +1,37 @@ +#[doc = "Register `PID0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PARTNBL` reader - Part Number Low"] +pub type PARTNBL_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Part Number Low"] + #[inline(always)] + pub fn partnbl(&self) -> PARTNBL_R { + PARTNBL_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "Peripheral Identification 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid0](index.html) module"] +pub struct PID0_SPEC; +impl crate::RegisterSpec for PID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid0::R](R) reader structure"] +impl crate::Readable for PID0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID0 to value 0xd0"] +impl crate::Resettable for PID0_SPEC { + const RESET_VALUE: Self::Ux = 0xd0; +} diff --git a/pac/atsaml22j/src/dsu/pid1.rs b/pac/atsaml22j/src/dsu/pid1.rs new file mode 100644 index 000000000000..142434362579 --- /dev/null +++ b/pac/atsaml22j/src/dsu/pid1.rs @@ -0,0 +1,44 @@ +#[doc = "Register `PID1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PARTNBH` reader - Part Number High"] +pub type PARTNBH_R = crate::FieldReader; +#[doc = "Field `JEPIDCL` reader - Low part of the JEP-106 Identity Code"] +pub type JEPIDCL_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - Part Number High"] + #[inline(always)] + pub fn partnbh(&self) -> PARTNBH_R { + PARTNBH_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Low part of the JEP-106 Identity Code"] + #[inline(always)] + pub fn jepidcl(&self) -> JEPIDCL_R { + JEPIDCL_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Peripheral Identification 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid1](index.html) module"] +pub struct PID1_SPEC; +impl crate::RegisterSpec for PID1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid1::R](R) reader structure"] +impl crate::Readable for PID1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID1 to value 0xfc"] +impl crate::Resettable for PID1_SPEC { + const RESET_VALUE: Self::Ux = 0xfc; +} diff --git a/pac/atsaml22j/src/dsu/pid2.rs b/pac/atsaml22j/src/dsu/pid2.rs new file mode 100644 index 000000000000..eccb3052b0e8 --- /dev/null +++ b/pac/atsaml22j/src/dsu/pid2.rs @@ -0,0 +1,51 @@ +#[doc = "Register `PID2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `JEPIDCH` reader - JEP-106 Identity Code High"] +pub type JEPIDCH_R = crate::FieldReader; +#[doc = "Field `JEPU` reader - JEP-106 Identity Code is used"] +pub type JEPU_R = crate::BitReader; +#[doc = "Field `REVISION` reader - Revision Number"] +pub type REVISION_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:2 - JEP-106 Identity Code High"] + #[inline(always)] + pub fn jepidch(&self) -> JEPIDCH_R { + JEPIDCH_R::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - JEP-106 Identity Code is used"] + #[inline(always)] + pub fn jepu(&self) -> JEPU_R { + JEPU_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:7 - Revision Number"] + #[inline(always)] + pub fn revision(&self) -> REVISION_R { + REVISION_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Peripheral Identification 2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid2](index.html) module"] +pub struct PID2_SPEC; +impl crate::RegisterSpec for PID2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid2::R](R) reader structure"] +impl crate::Readable for PID2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID2 to value 0x09"] +impl crate::Resettable for PID2_SPEC { + const RESET_VALUE: Self::Ux = 0x09; +} diff --git a/pac/atsaml22j/src/dsu/pid3.rs b/pac/atsaml22j/src/dsu/pid3.rs new file mode 100644 index 000000000000..a4e9cbaa6ee4 --- /dev/null +++ b/pac/atsaml22j/src/dsu/pid3.rs @@ -0,0 +1,44 @@ +#[doc = "Register `PID3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `CUSMOD` reader - ARM CUSMOD"] +pub type CUSMOD_R = crate::FieldReader; +#[doc = "Field `REVAND` reader - Revision Number"] +pub type REVAND_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - ARM CUSMOD"] + #[inline(always)] + pub fn cusmod(&self) -> CUSMOD_R { + CUSMOD_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - Revision Number"] + #[inline(always)] + pub fn revand(&self) -> REVAND_R { + REVAND_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Peripheral Identification 3\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid3](index.html) module"] +pub struct PID3_SPEC; +impl crate::RegisterSpec for PID3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid3::R](R) reader structure"] +impl crate::Readable for PID3_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID3 to value 0"] +impl crate::Resettable for PID3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/dsu/pid4.rs b/pac/atsaml22j/src/dsu/pid4.rs new file mode 100644 index 000000000000..8075709c7da9 --- /dev/null +++ b/pac/atsaml22j/src/dsu/pid4.rs @@ -0,0 +1,44 @@ +#[doc = "Register `PID4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `JEPCC` reader - JEP-106 Continuation Code"] +pub type JEPCC_R = crate::FieldReader; +#[doc = "Field `FKBC` reader - 4KB count"] +pub type FKBC_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:3 - JEP-106 Continuation Code"] + #[inline(always)] + pub fn jepcc(&self) -> JEPCC_R { + JEPCC_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:7 - 4KB count"] + #[inline(always)] + pub fn fkbc(&self) -> FKBC_R { + FKBC_R::new(((self.bits >> 4) & 0x0f) as u8) + } +} +#[doc = "Peripheral Identification 4\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid4](index.html) module"] +pub struct PID4_SPEC; +impl crate::RegisterSpec for PID4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid4::R](R) reader structure"] +impl crate::Readable for PID4_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID4 to value 0"] +impl crate::Resettable for PID4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/dsu/pid5.rs b/pac/atsaml22j/src/dsu/pid5.rs new file mode 100644 index 000000000000..51f0a3b6a532 --- /dev/null +++ b/pac/atsaml22j/src/dsu/pid5.rs @@ -0,0 +1,28 @@ +#[doc = "Register `PID5` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 5\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid5](index.html) module"] +pub struct PID5_SPEC; +impl crate::RegisterSpec for PID5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid5::R](R) reader structure"] +impl crate::Readable for PID5_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID5 to value 0"] +impl crate::Resettable for PID5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/dsu/pid6.rs b/pac/atsaml22j/src/dsu/pid6.rs new file mode 100644 index 000000000000..38aa7a8515f8 --- /dev/null +++ b/pac/atsaml22j/src/dsu/pid6.rs @@ -0,0 +1,28 @@ +#[doc = "Register `PID6` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 6\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid6](index.html) module"] +pub struct PID6_SPEC; +impl crate::RegisterSpec for PID6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid6::R](R) reader structure"] +impl crate::Readable for PID6_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID6 to value 0"] +impl crate::Resettable for PID6_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/dsu/pid7.rs b/pac/atsaml22j/src/dsu/pid7.rs new file mode 100644 index 000000000000..fc0161b33656 --- /dev/null +++ b/pac/atsaml22j/src/dsu/pid7.rs @@ -0,0 +1,28 @@ +#[doc = "Register `PID7` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 7\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid7](index.html) module"] +pub struct PID7_SPEC; +impl crate::RegisterSpec for PID7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid7::R](R) reader structure"] +impl crate::Readable for PID7_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID7 to value 0"] +impl crate::Resettable for PID7_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/dsu/statusa.rs b/pac/atsaml22j/src/dsu/statusa.rs new file mode 100644 index 000000000000..4b3c67fb1dc8 --- /dev/null +++ b/pac/atsaml22j/src/dsu/statusa.rs @@ -0,0 +1,140 @@ +#[doc = "Register `STATUSA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUSA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DONE` reader - Done"] +pub type DONE_R = crate::BitReader; +#[doc = "Field `DONE` writer - Done"] +pub type DONE_W<'a, const O: u8> = crate::BitWriter<'a, u8, STATUSA_SPEC, bool, O>; +#[doc = "Field `CRSTEXT` reader - CPU Reset Phase Extension"] +pub type CRSTEXT_R = crate::BitReader; +#[doc = "Field `CRSTEXT` writer - CPU Reset Phase Extension"] +pub type CRSTEXT_W<'a, const O: u8> = crate::BitWriter<'a, u8, STATUSA_SPEC, bool, O>; +#[doc = "Field `BERR` reader - Bus Error"] +pub type BERR_R = crate::BitReader; +#[doc = "Field `BERR` writer - Bus Error"] +pub type BERR_W<'a, const O: u8> = crate::BitWriter<'a, u8, STATUSA_SPEC, bool, O>; +#[doc = "Field `FAIL` reader - Failure"] +pub type FAIL_R = crate::BitReader; +#[doc = "Field `FAIL` writer - Failure"] +pub type FAIL_W<'a, const O: u8> = crate::BitWriter<'a, u8, STATUSA_SPEC, bool, O>; +#[doc = "Field `PERR` reader - Protection Error"] +pub type PERR_R = crate::BitReader; +#[doc = "Field `PERR` writer - Protection Error"] +pub type PERR_W<'a, const O: u8> = crate::BitWriter<'a, u8, STATUSA_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Done"] + #[inline(always)] + pub fn done(&self) -> DONE_R { + DONE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - CPU Reset Phase Extension"] + #[inline(always)] + pub fn crstext(&self) -> CRSTEXT_R { + CRSTEXT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Bus Error"] + #[inline(always)] + pub fn berr(&self) -> BERR_R { + BERR_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Failure"] + #[inline(always)] + pub fn fail(&self) -> FAIL_R { + FAIL_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Protection Error"] + #[inline(always)] + pub fn perr(&self) -> PERR_R { + PERR_R::new(((self.bits >> 4) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Done"] + #[inline(always)] + #[must_use] + pub fn done(&mut self) -> DONE_W<0> { + DONE_W::new(self) + } + #[doc = "Bit 1 - CPU Reset Phase Extension"] + #[inline(always)] + #[must_use] + pub fn crstext(&mut self) -> CRSTEXT_W<1> { + CRSTEXT_W::new(self) + } + #[doc = "Bit 2 - Bus Error"] + #[inline(always)] + #[must_use] + pub fn berr(&mut self) -> BERR_W<2> { + BERR_W::new(self) + } + #[doc = "Bit 3 - Failure"] + #[inline(always)] + #[must_use] + pub fn fail(&mut self) -> FAIL_W<3> { + FAIL_W::new(self) + } + #[doc = "Bit 4 - Protection Error"] + #[inline(always)] + #[must_use] + pub fn perr(&mut self) -> PERR_W<4> { + PERR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusa](index.html) module"] +pub struct STATUSA_SPEC; +impl crate::RegisterSpec for STATUSA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [statusa::R](R) reader structure"] +impl crate::Readable for STATUSA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [statusa::W](W) writer structure"] +impl crate::Writable for STATUSA_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets STATUSA to value 0"] +impl crate::Resettable for STATUSA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/dsu/statusb.rs b/pac/atsaml22j/src/dsu/statusb.rs new file mode 100644 index 000000000000..cead5bd7d521 --- /dev/null +++ b/pac/atsaml22j/src/dsu/statusb.rs @@ -0,0 +1,65 @@ +#[doc = "Register `STATUSB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PROT` reader - Protected"] +pub type PROT_R = crate::BitReader; +#[doc = "Field `DBGPRES` reader - Debugger Present"] +pub type DBGPRES_R = crate::BitReader; +#[doc = "Field `DCCD0` reader - Debug Communication Channel 0 Dirty"] +pub type DCCD0_R = crate::BitReader; +#[doc = "Field `DCCD1` reader - Debug Communication Channel 1 Dirty"] +pub type DCCD1_R = crate::BitReader; +#[doc = "Field `HPE` reader - Hot-Plugging Enable"] +pub type HPE_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Protected"] + #[inline(always)] + pub fn prot(&self) -> PROT_R { + PROT_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Debugger Present"] + #[inline(always)] + pub fn dbgpres(&self) -> DBGPRES_R { + DBGPRES_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Debug Communication Channel 0 Dirty"] + #[inline(always)] + pub fn dccd0(&self) -> DCCD0_R { + DCCD0_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Debug Communication Channel 1 Dirty"] + #[inline(always)] + pub fn dccd1(&self) -> DCCD1_R { + DCCD1_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Hot-Plugging Enable"] + #[inline(always)] + pub fn hpe(&self) -> HPE_R { + HPE_R::new(((self.bits >> 4) & 1) != 0) + } +} +#[doc = "Status B\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusb](index.html) module"] +pub struct STATUSB_SPEC; +impl crate::RegisterSpec for STATUSB_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [statusb::R](R) reader structure"] +impl crate::Readable for STATUSB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSB to value 0"] +impl crate::Resettable for STATUSB_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/eic.rs b/pac/atsaml22j/src/eic.rs new file mode 100644 index 000000000000..d7e020cd17aa --- /dev/null +++ b/pac/atsaml22j/src/eic.rs @@ -0,0 +1,64 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrla: CTRLA, + #[doc = "0x01 - NMI Control"] + pub nmictrl: NMICTRL, + #[doc = "0x02 - NMI Interrupt Flag"] + pub nmiflag: NMIFLAG, + #[doc = "0x04 - Syncbusy register"] + pub syncbusy: SYNCBUSY, + #[doc = "0x08 - Event Control"] + pub evctrl: EVCTRL, + #[doc = "0x0c - Interrupt Enable Clear"] + pub intenclr: INTENCLR, + #[doc = "0x10 - Interrupt Enable Set"] + pub intenset: INTENSET, + #[doc = "0x14 - Interrupt Flag Status and Clear"] + pub intflag: INTFLAG, + #[doc = "0x18 - EIC Asynchronous edge Detection Enable"] + pub asynch: ASYNCH, + #[doc = "0x1c..0x24 - Configuration n"] + pub config: [CONFIG; 2], +} +#[doc = "CTRLA (rw) register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control"] +pub mod ctrla; +#[doc = "NMICTRL (rw) register accessor: an alias for `Reg`"] +pub type NMICTRL = crate::Reg; +#[doc = "NMI Control"] +pub mod nmictrl; +#[doc = "NMIFLAG (rw) register accessor: an alias for `Reg`"] +pub type NMIFLAG = crate::Reg; +#[doc = "NMI Interrupt Flag"] +pub mod nmiflag; +#[doc = "SYNCBUSY (r) register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Syncbusy register"] +pub mod syncbusy; +#[doc = "EVCTRL (rw) register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR (rw) register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET (rw) register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG (rw) register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "ASYNCH (rw) register accessor: an alias for `Reg`"] +pub type ASYNCH = crate::Reg; +#[doc = "EIC Asynchronous edge Detection Enable"] +pub mod asynch; +#[doc = "CONFIG (rw) register accessor: an alias for `Reg`"] +pub type CONFIG = crate::Reg; +#[doc = "Configuration n"] +pub mod config; diff --git a/pac/atsaml22j/src/eic/asynch.rs b/pac/atsaml22j/src/eic/asynch.rs new file mode 100644 index 000000000000..4bfeed9fa0cd --- /dev/null +++ b/pac/atsaml22j/src/eic/asynch.rs @@ -0,0 +1,80 @@ +#[doc = "Register `ASYNCH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ASYNCH` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ASYNCH` reader - EIC Asynchronous edge Detection Enable"] +pub type ASYNCH_R = crate::FieldReader; +#[doc = "Field `ASYNCH` writer - EIC Asynchronous edge Detection Enable"] +pub type ASYNCH_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ASYNCH_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - EIC Asynchronous edge Detection Enable"] + #[inline(always)] + pub fn asynch(&self) -> ASYNCH_R { + ASYNCH_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - EIC Asynchronous edge Detection Enable"] + #[inline(always)] + #[must_use] + pub fn asynch(&mut self) -> ASYNCH_W<0> { + ASYNCH_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "EIC Asynchronous edge Detection Enable\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [asynch](index.html) module"] +pub struct ASYNCH_SPEC; +impl crate::RegisterSpec for ASYNCH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [asynch::R](R) reader structure"] +impl crate::Readable for ASYNCH_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [asynch::W](W) writer structure"] +impl crate::Writable for ASYNCH_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ASYNCH to value 0"] +impl crate::Resettable for ASYNCH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/eic/config.rs b/pac/atsaml22j/src/eic/config.rs new file mode 100644 index 000000000000..5c4a12a4a882 --- /dev/null +++ b/pac/atsaml22j/src/eic/config.rs @@ -0,0 +1,1113 @@ +#[doc = "Register `CONFIG%s` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CONFIG%s` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SENSE0` reader - Input Sense Configuration 0"] +pub type SENSE0_R = crate::FieldReader; +#[doc = "Input Sense Configuration 0\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SENSE0SELECT_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE0SELECT_A) -> Self { + variant as _ + } +} +impl SENSE0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE0SELECT_A::NONE), + 1 => Some(SENSE0SELECT_A::RISE), + 2 => Some(SENSE0SELECT_A::FALL), + 3 => Some(SENSE0SELECT_A::BOTH), + 4 => Some(SENSE0SELECT_A::HIGH), + 5 => Some(SENSE0SELECT_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == SENSE0SELECT_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + *self == SENSE0SELECT_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + *self == SENSE0SELECT_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + *self == SENSE0SELECT_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == SENSE0SELECT_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == SENSE0SELECT_A::LOW + } +} +#[doc = "Field `SENSE0` writer - Input Sense Configuration 0"] +pub type SENSE0_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, CONFIG_SPEC, u8, SENSE0SELECT_A, 3, O>; +impl<'a, const O: u8> SENSE0_W<'a, O> { + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE0SELECT_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE0SELECT_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE0SELECT_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE0SELECT_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE0SELECT_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE0SELECT_A::LOW) + } +} +#[doc = "Field `FILTEN0` reader - Filter Enable 0"] +pub type FILTEN0_R = crate::BitReader; +#[doc = "Field `FILTEN0` writer - Filter Enable 0"] +pub type FILTEN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONFIG_SPEC, bool, O>; +#[doc = "Field `SENSE1` reader - Input Sense Configuration 1"] +pub type SENSE1_R = crate::FieldReader; +#[doc = "Input Sense Configuration 1\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SENSE1SELECT_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE1SELECT_A) -> Self { + variant as _ + } +} +impl SENSE1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE1SELECT_A::NONE), + 1 => Some(SENSE1SELECT_A::RISE), + 2 => Some(SENSE1SELECT_A::FALL), + 3 => Some(SENSE1SELECT_A::BOTH), + 4 => Some(SENSE1SELECT_A::HIGH), + 5 => Some(SENSE1SELECT_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == SENSE1SELECT_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + *self == SENSE1SELECT_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + *self == SENSE1SELECT_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + *self == SENSE1SELECT_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == SENSE1SELECT_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == SENSE1SELECT_A::LOW + } +} +#[doc = "Field `SENSE1` writer - Input Sense Configuration 1"] +pub type SENSE1_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, CONFIG_SPEC, u8, SENSE1SELECT_A, 3, O>; +impl<'a, const O: u8> SENSE1_W<'a, O> { + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE1SELECT_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE1SELECT_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE1SELECT_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE1SELECT_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE1SELECT_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE1SELECT_A::LOW) + } +} +#[doc = "Field `FILTEN1` reader - Filter Enable 1"] +pub type FILTEN1_R = crate::BitReader; +#[doc = "Field `FILTEN1` writer - Filter Enable 1"] +pub type FILTEN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONFIG_SPEC, bool, O>; +#[doc = "Field `SENSE2` reader - Input Sense Configuration 2"] +pub type SENSE2_R = crate::FieldReader; +#[doc = "Input Sense Configuration 2\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SENSE2SELECT_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE2SELECT_A) -> Self { + variant as _ + } +} +impl SENSE2_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE2SELECT_A::NONE), + 1 => Some(SENSE2SELECT_A::RISE), + 2 => Some(SENSE2SELECT_A::FALL), + 3 => Some(SENSE2SELECT_A::BOTH), + 4 => Some(SENSE2SELECT_A::HIGH), + 5 => Some(SENSE2SELECT_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == SENSE2SELECT_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + *self == SENSE2SELECT_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + *self == SENSE2SELECT_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + *self == SENSE2SELECT_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == SENSE2SELECT_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == SENSE2SELECT_A::LOW + } +} +#[doc = "Field `SENSE2` writer - Input Sense Configuration 2"] +pub type SENSE2_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, CONFIG_SPEC, u8, SENSE2SELECT_A, 3, O>; +impl<'a, const O: u8> SENSE2_W<'a, O> { + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE2SELECT_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE2SELECT_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE2SELECT_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE2SELECT_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE2SELECT_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE2SELECT_A::LOW) + } +} +#[doc = "Field `FILTEN2` reader - Filter Enable 2"] +pub type FILTEN2_R = crate::BitReader; +#[doc = "Field `FILTEN2` writer - Filter Enable 2"] +pub type FILTEN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONFIG_SPEC, bool, O>; +#[doc = "Field `SENSE3` reader - Input Sense Configuration 3"] +pub type SENSE3_R = crate::FieldReader; +#[doc = "Input Sense Configuration 3\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SENSE3SELECT_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE3SELECT_A) -> Self { + variant as _ + } +} +impl SENSE3_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE3SELECT_A::NONE), + 1 => Some(SENSE3SELECT_A::RISE), + 2 => Some(SENSE3SELECT_A::FALL), + 3 => Some(SENSE3SELECT_A::BOTH), + 4 => Some(SENSE3SELECT_A::HIGH), + 5 => Some(SENSE3SELECT_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == SENSE3SELECT_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + *self == SENSE3SELECT_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + *self == SENSE3SELECT_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + *self == SENSE3SELECT_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == SENSE3SELECT_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == SENSE3SELECT_A::LOW + } +} +#[doc = "Field `SENSE3` writer - Input Sense Configuration 3"] +pub type SENSE3_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, CONFIG_SPEC, u8, SENSE3SELECT_A, 3, O>; +impl<'a, const O: u8> SENSE3_W<'a, O> { + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE3SELECT_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE3SELECT_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE3SELECT_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE3SELECT_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE3SELECT_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE3SELECT_A::LOW) + } +} +#[doc = "Field `FILTEN3` reader - Filter Enable 3"] +pub type FILTEN3_R = crate::BitReader; +#[doc = "Field `FILTEN3` writer - Filter Enable 3"] +pub type FILTEN3_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONFIG_SPEC, bool, O>; +#[doc = "Field `SENSE4` reader - Input Sense Configuration 4"] +pub type SENSE4_R = crate::FieldReader; +#[doc = "Input Sense Configuration 4\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SENSE4SELECT_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE4SELECT_A) -> Self { + variant as _ + } +} +impl SENSE4_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE4SELECT_A::NONE), + 1 => Some(SENSE4SELECT_A::RISE), + 2 => Some(SENSE4SELECT_A::FALL), + 3 => Some(SENSE4SELECT_A::BOTH), + 4 => Some(SENSE4SELECT_A::HIGH), + 5 => Some(SENSE4SELECT_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == SENSE4SELECT_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + *self == SENSE4SELECT_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + *self == SENSE4SELECT_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + *self == SENSE4SELECT_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == SENSE4SELECT_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == SENSE4SELECT_A::LOW + } +} +#[doc = "Field `SENSE4` writer - Input Sense Configuration 4"] +pub type SENSE4_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, CONFIG_SPEC, u8, SENSE4SELECT_A, 3, O>; +impl<'a, const O: u8> SENSE4_W<'a, O> { + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE4SELECT_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE4SELECT_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE4SELECT_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE4SELECT_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE4SELECT_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE4SELECT_A::LOW) + } +} +#[doc = "Field `FILTEN4` reader - Filter Enable 4"] +pub type FILTEN4_R = crate::BitReader; +#[doc = "Field `FILTEN4` writer - Filter Enable 4"] +pub type FILTEN4_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONFIG_SPEC, bool, O>; +#[doc = "Field `SENSE5` reader - Input Sense Configuration 5"] +pub type SENSE5_R = crate::FieldReader; +#[doc = "Input Sense Configuration 5\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SENSE5SELECT_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE5SELECT_A) -> Self { + variant as _ + } +} +impl SENSE5_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE5SELECT_A::NONE), + 1 => Some(SENSE5SELECT_A::RISE), + 2 => Some(SENSE5SELECT_A::FALL), + 3 => Some(SENSE5SELECT_A::BOTH), + 4 => Some(SENSE5SELECT_A::HIGH), + 5 => Some(SENSE5SELECT_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == SENSE5SELECT_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + *self == SENSE5SELECT_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + *self == SENSE5SELECT_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + *self == SENSE5SELECT_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == SENSE5SELECT_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == SENSE5SELECT_A::LOW + } +} +#[doc = "Field `SENSE5` writer - Input Sense Configuration 5"] +pub type SENSE5_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, CONFIG_SPEC, u8, SENSE5SELECT_A, 3, O>; +impl<'a, const O: u8> SENSE5_W<'a, O> { + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE5SELECT_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE5SELECT_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE5SELECT_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE5SELECT_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE5SELECT_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE5SELECT_A::LOW) + } +} +#[doc = "Field `FILTEN5` reader - Filter Enable 5"] +pub type FILTEN5_R = crate::BitReader; +#[doc = "Field `FILTEN5` writer - Filter Enable 5"] +pub type FILTEN5_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONFIG_SPEC, bool, O>; +#[doc = "Field `SENSE6` reader - Input Sense Configuration 6"] +pub type SENSE6_R = crate::FieldReader; +#[doc = "Input Sense Configuration 6\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SENSE6SELECT_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE6SELECT_A) -> Self { + variant as _ + } +} +impl SENSE6_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE6SELECT_A::NONE), + 1 => Some(SENSE6SELECT_A::RISE), + 2 => Some(SENSE6SELECT_A::FALL), + 3 => Some(SENSE6SELECT_A::BOTH), + 4 => Some(SENSE6SELECT_A::HIGH), + 5 => Some(SENSE6SELECT_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == SENSE6SELECT_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + *self == SENSE6SELECT_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + *self == SENSE6SELECT_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + *self == SENSE6SELECT_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == SENSE6SELECT_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == SENSE6SELECT_A::LOW + } +} +#[doc = "Field `SENSE6` writer - Input Sense Configuration 6"] +pub type SENSE6_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, CONFIG_SPEC, u8, SENSE6SELECT_A, 3, O>; +impl<'a, const O: u8> SENSE6_W<'a, O> { + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE6SELECT_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE6SELECT_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE6SELECT_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE6SELECT_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE6SELECT_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE6SELECT_A::LOW) + } +} +#[doc = "Field `FILTEN6` reader - Filter Enable 6"] +pub type FILTEN6_R = crate::BitReader; +#[doc = "Field `FILTEN6` writer - Filter Enable 6"] +pub type FILTEN6_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONFIG_SPEC, bool, O>; +#[doc = "Field `SENSE7` reader - Input Sense Configuration 7"] +pub type SENSE7_R = crate::FieldReader; +#[doc = "Input Sense Configuration 7\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SENSE7SELECT_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SENSE7SELECT_A) -> Self { + variant as _ + } +} +impl SENSE7_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SENSE7SELECT_A::NONE), + 1 => Some(SENSE7SELECT_A::RISE), + 2 => Some(SENSE7SELECT_A::FALL), + 3 => Some(SENSE7SELECT_A::BOTH), + 4 => Some(SENSE7SELECT_A::HIGH), + 5 => Some(SENSE7SELECT_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == SENSE7SELECT_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + *self == SENSE7SELECT_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + *self == SENSE7SELECT_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + *self == SENSE7SELECT_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == SENSE7SELECT_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == SENSE7SELECT_A::LOW + } +} +#[doc = "Field `SENSE7` writer - Input Sense Configuration 7"] +pub type SENSE7_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, CONFIG_SPEC, u8, SENSE7SELECT_A, 3, O>; +impl<'a, const O: u8> SENSE7_W<'a, O> { + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(SENSE7SELECT_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(SENSE7SELECT_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(SENSE7SELECT_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(SENSE7SELECT_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(SENSE7SELECT_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(SENSE7SELECT_A::LOW) + } +} +#[doc = "Field `FILTEN7` reader - Filter Enable 7"] +pub type FILTEN7_R = crate::BitReader; +#[doc = "Field `FILTEN7` writer - Filter Enable 7"] +pub type FILTEN7_W<'a, const O: u8> = crate::BitWriter<'a, u32, CONFIG_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:2 - Input Sense Configuration 0"] + #[inline(always)] + pub fn sense0(&self) -> SENSE0_R { + SENSE0_R::new((self.bits & 7) as u8) + } + #[doc = "Bit 3 - Filter Enable 0"] + #[inline(always)] + pub fn filten0(&self) -> FILTEN0_R { + FILTEN0_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:6 - Input Sense Configuration 1"] + #[inline(always)] + pub fn sense1(&self) -> SENSE1_R { + SENSE1_R::new(((self.bits >> 4) & 7) as u8) + } + #[doc = "Bit 7 - Filter Enable 1"] + #[inline(always)] + pub fn filten1(&self) -> FILTEN1_R { + FILTEN1_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:10 - Input Sense Configuration 2"] + #[inline(always)] + pub fn sense2(&self) -> SENSE2_R { + SENSE2_R::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 11 - Filter Enable 2"] + #[inline(always)] + pub fn filten2(&self) -> FILTEN2_R { + FILTEN2_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 12:14 - Input Sense Configuration 3"] + #[inline(always)] + pub fn sense3(&self) -> SENSE3_R { + SENSE3_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - Filter Enable 3"] + #[inline(always)] + pub fn filten3(&self) -> FILTEN3_R { + FILTEN3_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:18 - Input Sense Configuration 4"] + #[inline(always)] + pub fn sense4(&self) -> SENSE4_R { + SENSE4_R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bit 19 - Filter Enable 4"] + #[inline(always)] + pub fn filten4(&self) -> FILTEN4_R { + FILTEN4_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bits 20:22 - Input Sense Configuration 5"] + #[inline(always)] + pub fn sense5(&self) -> SENSE5_R { + SENSE5_R::new(((self.bits >> 20) & 7) as u8) + } + #[doc = "Bit 23 - Filter Enable 5"] + #[inline(always)] + pub fn filten5(&self) -> FILTEN5_R { + FILTEN5_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bits 24:26 - Input Sense Configuration 6"] + #[inline(always)] + pub fn sense6(&self) -> SENSE6_R { + SENSE6_R::new(((self.bits >> 24) & 7) as u8) + } + #[doc = "Bit 27 - Filter Enable 6"] + #[inline(always)] + pub fn filten6(&self) -> FILTEN6_R { + FILTEN6_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bits 28:30 - Input Sense Configuration 7"] + #[inline(always)] + pub fn sense7(&self) -> SENSE7_R { + SENSE7_R::new(((self.bits >> 28) & 7) as u8) + } + #[doc = "Bit 31 - Filter Enable 7"] + #[inline(always)] + pub fn filten7(&self) -> FILTEN7_R { + FILTEN7_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Input Sense Configuration 0"] + #[inline(always)] + #[must_use] + pub fn sense0(&mut self) -> SENSE0_W<0> { + SENSE0_W::new(self) + } + #[doc = "Bit 3 - Filter Enable 0"] + #[inline(always)] + #[must_use] + pub fn filten0(&mut self) -> FILTEN0_W<3> { + FILTEN0_W::new(self) + } + #[doc = "Bits 4:6 - Input Sense Configuration 1"] + #[inline(always)] + #[must_use] + pub fn sense1(&mut self) -> SENSE1_W<4> { + SENSE1_W::new(self) + } + #[doc = "Bit 7 - Filter Enable 1"] + #[inline(always)] + #[must_use] + pub fn filten1(&mut self) -> FILTEN1_W<7> { + FILTEN1_W::new(self) + } + #[doc = "Bits 8:10 - Input Sense Configuration 2"] + #[inline(always)] + #[must_use] + pub fn sense2(&mut self) -> SENSE2_W<8> { + SENSE2_W::new(self) + } + #[doc = "Bit 11 - Filter Enable 2"] + #[inline(always)] + #[must_use] + pub fn filten2(&mut self) -> FILTEN2_W<11> { + FILTEN2_W::new(self) + } + #[doc = "Bits 12:14 - Input Sense Configuration 3"] + #[inline(always)] + #[must_use] + pub fn sense3(&mut self) -> SENSE3_W<12> { + SENSE3_W::new(self) + } + #[doc = "Bit 15 - Filter Enable 3"] + #[inline(always)] + #[must_use] + pub fn filten3(&mut self) -> FILTEN3_W<15> { + FILTEN3_W::new(self) + } + #[doc = "Bits 16:18 - Input Sense Configuration 4"] + #[inline(always)] + #[must_use] + pub fn sense4(&mut self) -> SENSE4_W<16> { + SENSE4_W::new(self) + } + #[doc = "Bit 19 - Filter Enable 4"] + #[inline(always)] + #[must_use] + pub fn filten4(&mut self) -> FILTEN4_W<19> { + FILTEN4_W::new(self) + } + #[doc = "Bits 20:22 - Input Sense Configuration 5"] + #[inline(always)] + #[must_use] + pub fn sense5(&mut self) -> SENSE5_W<20> { + SENSE5_W::new(self) + } + #[doc = "Bit 23 - Filter Enable 5"] + #[inline(always)] + #[must_use] + pub fn filten5(&mut self) -> FILTEN5_W<23> { + FILTEN5_W::new(self) + } + #[doc = "Bits 24:26 - Input Sense Configuration 6"] + #[inline(always)] + #[must_use] + pub fn sense6(&mut self) -> SENSE6_W<24> { + SENSE6_W::new(self) + } + #[doc = "Bit 27 - Filter Enable 6"] + #[inline(always)] + #[must_use] + pub fn filten6(&mut self) -> FILTEN6_W<27> { + FILTEN6_W::new(self) + } + #[doc = "Bits 28:30 - Input Sense Configuration 7"] + #[inline(always)] + #[must_use] + pub fn sense7(&mut self) -> SENSE7_W<28> { + SENSE7_W::new(self) + } + #[doc = "Bit 31 - Filter Enable 7"] + #[inline(always)] + #[must_use] + pub fn filten7(&mut self) -> FILTEN7_W<31> { + FILTEN7_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Configuration n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [config](index.html) module"] +pub struct CONFIG_SPEC; +impl crate::RegisterSpec for CONFIG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [config::R](R) reader structure"] +impl crate::Readable for CONFIG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [config::W](W) writer structure"] +impl crate::Writable for CONFIG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CONFIG%s to value 0"] +impl crate::Resettable for CONFIG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/eic/ctrla.rs b/pac/atsaml22j/src/eic/ctrla.rs new file mode 100644 index 000000000000..9ac0288b1e63 --- /dev/null +++ b/pac/atsaml22j/src/eic/ctrla.rs @@ -0,0 +1,103 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub type SWRST_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLA_SPEC, bool, O>; +#[doc = "Field `ENABLE` reader - Enable"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - Enable"] +pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLA_SPEC, bool, O>; +#[doc = "Field `CKSEL` reader - Clock Selection"] +pub type CKSEL_R = crate::BitReader; +#[doc = "Field `CKSEL` writer - Clock Selection"] +pub type CKSEL_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLA_SPEC, bool, O>; +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 4 - Clock Selection"] + #[inline(always)] + pub fn cksel(&self) -> CKSEL_R { + CKSEL_R::new(((self.bits >> 4) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + #[must_use] + pub fn swrst(&mut self) -> SWRST_W<0> { + SWRST_W::new(self) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W<1> { + ENABLE_W::new(self) + } + #[doc = "Bit 4 - Clock Selection"] + #[inline(always)] + #[must_use] + pub fn cksel(&mut self) -> CKSEL_W<4> { + CKSEL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/eic/evctrl.rs b/pac/atsaml22j/src/eic/evctrl.rs new file mode 100644 index 000000000000..b51da36b873a --- /dev/null +++ b/pac/atsaml22j/src/eic/evctrl.rs @@ -0,0 +1,80 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EXTINTEO` reader - External Interrupt Event Output Enable"] +pub type EXTINTEO_R = crate::FieldReader; +#[doc = "Field `EXTINTEO` writer - External Interrupt Event Output Enable"] +pub type EXTINTEO_W<'a, const O: u8> = crate::FieldWriter<'a, u32, EVCTRL_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - External Interrupt Event Output Enable"] + #[inline(always)] + pub fn extinteo(&self) -> EXTINTEO_R { + EXTINTEO_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - External Interrupt Event Output Enable"] + #[inline(always)] + #[must_use] + pub fn extinteo(&mut self) -> EXTINTEO_W<0> { + EXTINTEO_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/eic/intenclr.rs b/pac/atsaml22j/src/eic/intenclr.rs new file mode 100644 index 000000000000..da6bf0c1fc0e --- /dev/null +++ b/pac/atsaml22j/src/eic/intenclr.rs @@ -0,0 +1,80 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EXTINT` reader - External Interrupt Disable"] +pub type EXTINT_R = crate::FieldReader; +#[doc = "Field `EXTINT` writer - External Interrupt Disable"] +pub type EXTINT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, INTENCLR_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - External Interrupt Disable"] + #[inline(always)] + pub fn extint(&self) -> EXTINT_R { + EXTINT_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - External Interrupt Disable"] + #[inline(always)] + #[must_use] + pub fn extint(&mut self) -> EXTINT_W<0> { + EXTINT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/eic/intenset.rs b/pac/atsaml22j/src/eic/intenset.rs new file mode 100644 index 000000000000..bb0b3ebe5663 --- /dev/null +++ b/pac/atsaml22j/src/eic/intenset.rs @@ -0,0 +1,80 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EXTINT` reader - External Interrupt Disable"] +pub type EXTINT_R = crate::FieldReader; +#[doc = "Field `EXTINT` writer - External Interrupt Disable"] +pub type EXTINT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, INTENSET_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - External Interrupt Disable"] + #[inline(always)] + pub fn extint(&self) -> EXTINT_R { + EXTINT_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - External Interrupt Disable"] + #[inline(always)] + #[must_use] + pub fn extint(&mut self) -> EXTINT_W<0> { + EXTINT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/eic/intflag.rs b/pac/atsaml22j/src/eic/intflag.rs new file mode 100644 index 000000000000..b65b59109c2c --- /dev/null +++ b/pac/atsaml22j/src/eic/intflag.rs @@ -0,0 +1,80 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EXTINT` reader - External Interrupt Flag"] +pub type EXTINT_R = crate::FieldReader; +#[doc = "Field `EXTINT` writer - External Interrupt Flag"] +pub type EXTINT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, INTFLAG_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - External Interrupt Flag"] + #[inline(always)] + pub fn extint(&self) -> EXTINT_R { + EXTINT_R::new((self.bits & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:15 - External Interrupt Flag"] + #[inline(always)] + #[must_use] + pub fn extint(&mut self) -> EXTINT_W<0> { + EXTINT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/eic/nmictrl.rs b/pac/atsaml22j/src/eic/nmictrl.rs new file mode 100644 index 000000000000..d2aa8f8a9e4f --- /dev/null +++ b/pac/atsaml22j/src/eic/nmictrl.rs @@ -0,0 +1,211 @@ +#[doc = "Register `NMICTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `NMICTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `NMISENSE` reader - NMI Input Sense Configuration"] +pub type NMISENSE_R = crate::FieldReader; +#[doc = "NMI Input Sense Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum NMISENSESELECT_A { + #[doc = "0: No detection"] + NONE = 0, + #[doc = "1: Rising edge detection"] + RISE = 1, + #[doc = "2: Falling edge detection"] + FALL = 2, + #[doc = "3: Both edges detection"] + BOTH = 3, + #[doc = "4: High level detection"] + HIGH = 4, + #[doc = "5: Low level detection"] + LOW = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: NMISENSESELECT_A) -> Self { + variant as _ + } +} +impl NMISENSE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(NMISENSESELECT_A::NONE), + 1 => Some(NMISENSESELECT_A::RISE), + 2 => Some(NMISENSESELECT_A::FALL), + 3 => Some(NMISENSESELECT_A::BOTH), + 4 => Some(NMISENSESELECT_A::HIGH), + 5 => Some(NMISENSESELECT_A::LOW), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == NMISENSESELECT_A::NONE + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + *self == NMISENSESELECT_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + *self == NMISENSESELECT_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + *self == NMISENSESELECT_A::BOTH + } + #[doc = "Checks if the value of the field is `HIGH`"] + #[inline(always)] + pub fn is_high(&self) -> bool { + *self == NMISENSESELECT_A::HIGH + } + #[doc = "Checks if the value of the field is `LOW`"] + #[inline(always)] + pub fn is_low(&self) -> bool { + *self == NMISENSESELECT_A::LOW + } +} +#[doc = "Field `NMISENSE` writer - NMI Input Sense Configuration"] +pub type NMISENSE_W<'a, const O: u8> = + crate::FieldWriter<'a, u8, NMICTRL_SPEC, u8, NMISENSESELECT_A, 3, O>; +impl<'a, const O: u8> NMISENSE_W<'a, O> { + #[doc = "No detection"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(NMISENSESELECT_A::NONE) + } + #[doc = "Rising edge detection"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(NMISENSESELECT_A::RISE) + } + #[doc = "Falling edge detection"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(NMISENSESELECT_A::FALL) + } + #[doc = "Both edges detection"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(NMISENSESELECT_A::BOTH) + } + #[doc = "High level detection"] + #[inline(always)] + pub fn high(self) -> &'a mut W { + self.variant(NMISENSESELECT_A::HIGH) + } + #[doc = "Low level detection"] + #[inline(always)] + pub fn low(self) -> &'a mut W { + self.variant(NMISENSESELECT_A::LOW) + } +} +#[doc = "Field `NMIFILTEN` reader - NMI Filter Enable"] +pub type NMIFILTEN_R = crate::BitReader; +#[doc = "Field `NMIFILTEN` writer - NMI Filter Enable"] +pub type NMIFILTEN_W<'a, const O: u8> = crate::BitWriter<'a, u8, NMICTRL_SPEC, bool, O>; +#[doc = "Field `NMIASYNCH` reader - NMI Asynchronous edge Detection Enable"] +pub type NMIASYNCH_R = crate::BitReader; +#[doc = "Field `NMIASYNCH` writer - NMI Asynchronous edge Detection Enable"] +pub type NMIASYNCH_W<'a, const O: u8> = crate::BitWriter<'a, u8, NMICTRL_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:2 - NMI Input Sense Configuration"] + #[inline(always)] + pub fn nmisense(&self) -> NMISENSE_R { + NMISENSE_R::new(self.bits & 7) + } + #[doc = "Bit 3 - NMI Filter Enable"] + #[inline(always)] + pub fn nmifilten(&self) -> NMIFILTEN_R { + NMIFILTEN_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NMI Asynchronous edge Detection Enable"] + #[inline(always)] + pub fn nmiasynch(&self) -> NMIASYNCH_R { + NMIASYNCH_R::new(((self.bits >> 4) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - NMI Input Sense Configuration"] + #[inline(always)] + #[must_use] + pub fn nmisense(&mut self) -> NMISENSE_W<0> { + NMISENSE_W::new(self) + } + #[doc = "Bit 3 - NMI Filter Enable"] + #[inline(always)] + #[must_use] + pub fn nmifilten(&mut self) -> NMIFILTEN_W<3> { + NMIFILTEN_W::new(self) + } + #[doc = "Bit 4 - NMI Asynchronous edge Detection Enable"] + #[inline(always)] + #[must_use] + pub fn nmiasynch(&mut self) -> NMIASYNCH_W<4> { + NMIASYNCH_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "NMI Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [nmictrl](index.html) module"] +pub struct NMICTRL_SPEC; +impl crate::RegisterSpec for NMICTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [nmictrl::R](R) reader structure"] +impl crate::Readable for NMICTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [nmictrl::W](W) writer structure"] +impl crate::Writable for NMICTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets NMICTRL to value 0"] +impl crate::Resettable for NMICTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/eic/nmiflag.rs b/pac/atsaml22j/src/eic/nmiflag.rs new file mode 100644 index 000000000000..58582847089d --- /dev/null +++ b/pac/atsaml22j/src/eic/nmiflag.rs @@ -0,0 +1,80 @@ +#[doc = "Register `NMIFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `NMIFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `NMI` reader - NMI Interrupt Flag"] +pub type NMI_R = crate::BitReader; +#[doc = "Field `NMI` writer - NMI Interrupt Flag"] +pub type NMI_W<'a, const O: u8> = crate::BitWriter<'a, u16, NMIFLAG_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - NMI Interrupt Flag"] + #[inline(always)] + pub fn nmi(&self) -> NMI_R { + NMI_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - NMI Interrupt Flag"] + #[inline(always)] + #[must_use] + pub fn nmi(&mut self) -> NMI_W<0> { + NMI_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "NMI Interrupt Flag\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [nmiflag](index.html) module"] +pub struct NMIFLAG_SPEC; +impl crate::RegisterSpec for NMIFLAG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [nmiflag::R](R) reader structure"] +impl crate::Readable for NMIFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [nmiflag::W](W) writer structure"] +impl crate::Writable for NMIFLAG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets NMIFLAG to value 0"] +impl crate::Resettable for NMIFLAG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/eic/syncbusy.rs b/pac/atsaml22j/src/eic/syncbusy.rs new file mode 100644 index 000000000000..0847c56888d7 --- /dev/null +++ b/pac/atsaml22j/src/eic/syncbusy.rs @@ -0,0 +1,44 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software reset synchronisation"] +pub type SWRST_R = crate::BitReader; +#[doc = "Field `ENABLE` reader - Enable synchronisation"] +pub type ENABLE_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Software reset synchronisation"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable synchronisation"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[doc = "Syncbusy register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/evsys.rs b/pac/atsaml22j/src/evsys.rs new file mode 100644 index 000000000000..beb3546f6007 --- /dev/null +++ b/pac/atsaml22j/src/evsys.rs @@ -0,0 +1,54 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrla: CTRLA, + _reserved1: [u8; 0x0b], + #[doc = "0x0c - Channel Status"] + pub chstatus: CHSTATUS, + #[doc = "0x10 - Interrupt Enable Clear"] + pub intenclr: INTENCLR, + #[doc = "0x14 - Interrupt Enable Set"] + pub intenset: INTENSET, + #[doc = "0x18 - Interrupt Flag Status and Clear"] + pub intflag: INTFLAG, + #[doc = "0x1c - Software Event"] + pub swevt: SWEVT, + #[doc = "0x20..0x40 - Channel n"] + pub channel: [CHANNEL; 8], + _reserved7: [u8; 0x40], + #[doc = "0x80..0xfc - User Multiplexer n"] + pub user: [USER; 31], +} +#[doc = "CTRLA (rw) register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control"] +pub mod ctrla; +#[doc = "CHSTATUS (r) register accessor: an alias for `Reg`"] +pub type CHSTATUS = crate::Reg; +#[doc = "Channel Status"] +pub mod chstatus; +#[doc = "INTENCLR (rw) register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET (rw) register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG (rw) register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "SWEVT (w) register accessor: an alias for `Reg`"] +pub type SWEVT = crate::Reg; +#[doc = "Software Event"] +pub mod swevt; +#[doc = "CHANNEL (rw) register accessor: an alias for `Reg`"] +pub type CHANNEL = crate::Reg; +#[doc = "Channel n"] +pub mod channel; +#[doc = "USER (rw) register accessor: an alias for `Reg`"] +pub type USER = crate::Reg; +#[doc = "User Multiplexer n"] +pub mod user; diff --git a/pac/atsaml22j/src/evsys/channel.rs b/pac/atsaml22j/src/evsys/channel.rs new file mode 100644 index 000000000000..f3e3f39bcee3 --- /dev/null +++ b/pac/atsaml22j/src/evsys/channel.rs @@ -0,0 +1,277 @@ +#[doc = "Register `CHANNEL%s` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CHANNEL%s` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVGEN` reader - Event Generator Selection"] +pub type EVGEN_R = crate::FieldReader; +#[doc = "Field `EVGEN` writer - Event Generator Selection"] +pub type EVGEN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CHANNEL_SPEC, u8, u8, 7, O>; +#[doc = "Field `PATH` reader - Path Selection"] +pub type PATH_R = crate::FieldReader; +#[doc = "Path Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum PATHSELECT_A { + #[doc = "0: Synchronous path"] + SYNCHRONOUS = 0, + #[doc = "1: Resynchronized path"] + RESYNCHRONIZED = 1, + #[doc = "2: Asynchronous path"] + ASYNCHRONOUS = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PATHSELECT_A) -> Self { + variant as _ + } +} +impl PATH_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PATHSELECT_A::SYNCHRONOUS), + 1 => Some(PATHSELECT_A::RESYNCHRONIZED), + 2 => Some(PATHSELECT_A::ASYNCHRONOUS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SYNCHRONOUS`"] + #[inline(always)] + pub fn is_synchronous(&self) -> bool { + *self == PATHSELECT_A::SYNCHRONOUS + } + #[doc = "Checks if the value of the field is `RESYNCHRONIZED`"] + #[inline(always)] + pub fn is_resynchronized(&self) -> bool { + *self == PATHSELECT_A::RESYNCHRONIZED + } + #[doc = "Checks if the value of the field is `ASYNCHRONOUS`"] + #[inline(always)] + pub fn is_asynchronous(&self) -> bool { + *self == PATHSELECT_A::ASYNCHRONOUS + } +} +#[doc = "Field `PATH` writer - Path Selection"] +pub type PATH_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, CHANNEL_SPEC, u8, PATHSELECT_A, 2, O>; +impl<'a, const O: u8> PATH_W<'a, O> { + #[doc = "Synchronous path"] + #[inline(always)] + pub fn synchronous(self) -> &'a mut W { + self.variant(PATHSELECT_A::SYNCHRONOUS) + } + #[doc = "Resynchronized path"] + #[inline(always)] + pub fn resynchronized(self) -> &'a mut W { + self.variant(PATHSELECT_A::RESYNCHRONIZED) + } + #[doc = "Asynchronous path"] + #[inline(always)] + pub fn asynchronous(self) -> &'a mut W { + self.variant(PATHSELECT_A::ASYNCHRONOUS) + } +} +#[doc = "Field `EDGSEL` reader - Edge Detection Selection"] +pub type EDGSEL_R = crate::FieldReader; +#[doc = "Edge Detection Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum EDGSELSELECT_A { + #[doc = "0: No event output when using the resynchronized or synchronous path"] + NO_EVT_OUTPUT = 0, + #[doc = "1: Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path"] + RISING_EDGE = 1, + #[doc = "2: Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path"] + FALLING_EDGE = 2, + #[doc = "3: Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path"] + BOTH_EDGES = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EDGSELSELECT_A) -> Self { + variant as _ + } +} +impl EDGSEL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EDGSELSELECT_A { + match self.bits { + 0 => EDGSELSELECT_A::NO_EVT_OUTPUT, + 1 => EDGSELSELECT_A::RISING_EDGE, + 2 => EDGSELSELECT_A::FALLING_EDGE, + 3 => EDGSELSELECT_A::BOTH_EDGES, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NO_EVT_OUTPUT`"] + #[inline(always)] + pub fn is_no_evt_output(&self) -> bool { + *self == EDGSELSELECT_A::NO_EVT_OUTPUT + } + #[doc = "Checks if the value of the field is `RISING_EDGE`"] + #[inline(always)] + pub fn is_rising_edge(&self) -> bool { + *self == EDGSELSELECT_A::RISING_EDGE + } + #[doc = "Checks if the value of the field is `FALLING_EDGE`"] + #[inline(always)] + pub fn is_falling_edge(&self) -> bool { + *self == EDGSELSELECT_A::FALLING_EDGE + } + #[doc = "Checks if the value of the field is `BOTH_EDGES`"] + #[inline(always)] + pub fn is_both_edges(&self) -> bool { + *self == EDGSELSELECT_A::BOTH_EDGES + } +} +#[doc = "Field `EDGSEL` writer - Edge Detection Selection"] +pub type EDGSEL_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, CHANNEL_SPEC, u8, EDGSELSELECT_A, 2, O>; +impl<'a, const O: u8> EDGSEL_W<'a, O> { + #[doc = "No event output when using the resynchronized or synchronous path"] + #[inline(always)] + pub fn no_evt_output(self) -> &'a mut W { + self.variant(EDGSELSELECT_A::NO_EVT_OUTPUT) + } + #[doc = "Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path"] + #[inline(always)] + pub fn rising_edge(self) -> &'a mut W { + self.variant(EDGSELSELECT_A::RISING_EDGE) + } + #[doc = "Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path"] + #[inline(always)] + pub fn falling_edge(self) -> &'a mut W { + self.variant(EDGSELSELECT_A::FALLING_EDGE) + } + #[doc = "Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path"] + #[inline(always)] + pub fn both_edges(self) -> &'a mut W { + self.variant(EDGSELSELECT_A::BOTH_EDGES) + } +} +#[doc = "Field `RUNSTDBY` reader - Run in standby"] +pub type RUNSTDBY_R = crate::BitReader; +#[doc = "Field `RUNSTDBY` writer - Run in standby"] +pub type RUNSTDBY_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHANNEL_SPEC, bool, O>; +#[doc = "Field `ONDEMAND` reader - Generic Clock On Demand"] +pub type ONDEMAND_R = crate::BitReader; +#[doc = "Field `ONDEMAND` writer - Generic Clock On Demand"] +pub type ONDEMAND_W<'a, const O: u8> = crate::BitWriter<'a, u32, CHANNEL_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:6 - Event Generator Selection"] + #[inline(always)] + pub fn evgen(&self) -> EVGEN_R { + EVGEN_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 8:9 - Path Selection"] + #[inline(always)] + pub fn path(&self) -> PATH_R { + PATH_R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:11 - Edge Detection Selection"] + #[inline(always)] + pub fn edgsel(&self) -> EDGSEL_R { + EDGSEL_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bit 14 - Run in standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Generic Clock On Demand"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - Event Generator Selection"] + #[inline(always)] + #[must_use] + pub fn evgen(&mut self) -> EVGEN_W<0> { + EVGEN_W::new(self) + } + #[doc = "Bits 8:9 - Path Selection"] + #[inline(always)] + #[must_use] + pub fn path(&mut self) -> PATH_W<8> { + PATH_W::new(self) + } + #[doc = "Bits 10:11 - Edge Detection Selection"] + #[inline(always)] + #[must_use] + pub fn edgsel(&mut self) -> EDGSEL_W<10> { + EDGSEL_W::new(self) + } + #[doc = "Bit 14 - Run in standby"] + #[inline(always)] + #[must_use] + pub fn runstdby(&mut self) -> RUNSTDBY_W<14> { + RUNSTDBY_W::new(self) + } + #[doc = "Bit 15 - Generic Clock On Demand"] + #[inline(always)] + #[must_use] + pub fn ondemand(&mut self) -> ONDEMAND_W<15> { + ONDEMAND_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Channel n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [channel](index.html) module"] +pub struct CHANNEL_SPEC; +impl crate::RegisterSpec for CHANNEL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [channel::R](R) reader structure"] +impl crate::Readable for CHANNEL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [channel::W](W) writer structure"] +impl crate::Writable for CHANNEL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CHANNEL%s to value 0x8000"] +impl crate::Resettable for CHANNEL_SPEC { + const RESET_VALUE: Self::Ux = 0x8000; +} diff --git a/pac/atsaml22j/src/evsys/chstatus.rs b/pac/atsaml22j/src/evsys/chstatus.rs new file mode 100644 index 000000000000..4434e4989f0e --- /dev/null +++ b/pac/atsaml22j/src/evsys/chstatus.rs @@ -0,0 +1,142 @@ +#[doc = "Register `CHSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `USRRDY0` reader - Channel 0 User Ready"] +pub type USRRDY0_R = crate::BitReader; +#[doc = "Field `USRRDY1` reader - Channel 1 User Ready"] +pub type USRRDY1_R = crate::BitReader; +#[doc = "Field `USRRDY2` reader - Channel 2 User Ready"] +pub type USRRDY2_R = crate::BitReader; +#[doc = "Field `USRRDY3` reader - Channel 3 User Ready"] +pub type USRRDY3_R = crate::BitReader; +#[doc = "Field `USRRDY4` reader - Channel 4 User Ready"] +pub type USRRDY4_R = crate::BitReader; +#[doc = "Field `USRRDY5` reader - Channel 5 User Ready"] +pub type USRRDY5_R = crate::BitReader; +#[doc = "Field `USRRDY6` reader - Channel 6 User Ready"] +pub type USRRDY6_R = crate::BitReader; +#[doc = "Field `USRRDY7` reader - Channel 7 User Ready"] +pub type USRRDY7_R = crate::BitReader; +#[doc = "Field `CHBUSY0` reader - Channel 0 Busy"] +pub type CHBUSY0_R = crate::BitReader; +#[doc = "Field `CHBUSY1` reader - Channel 1 Busy"] +pub type CHBUSY1_R = crate::BitReader; +#[doc = "Field `CHBUSY2` reader - Channel 2 Busy"] +pub type CHBUSY2_R = crate::BitReader; +#[doc = "Field `CHBUSY3` reader - Channel 3 Busy"] +pub type CHBUSY3_R = crate::BitReader; +#[doc = "Field `CHBUSY4` reader - Channel 4 Busy"] +pub type CHBUSY4_R = crate::BitReader; +#[doc = "Field `CHBUSY5` reader - Channel 5 Busy"] +pub type CHBUSY5_R = crate::BitReader; +#[doc = "Field `CHBUSY6` reader - Channel 6 Busy"] +pub type CHBUSY6_R = crate::BitReader; +#[doc = "Field `CHBUSY7` reader - Channel 7 Busy"] +pub type CHBUSY7_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Channel 0 User Ready"] + #[inline(always)] + pub fn usrrdy0(&self) -> USRRDY0_R { + USRRDY0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Channel 1 User Ready"] + #[inline(always)] + pub fn usrrdy1(&self) -> USRRDY1_R { + USRRDY1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Channel 2 User Ready"] + #[inline(always)] + pub fn usrrdy2(&self) -> USRRDY2_R { + USRRDY2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Channel 3 User Ready"] + #[inline(always)] + pub fn usrrdy3(&self) -> USRRDY3_R { + USRRDY3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Channel 4 User Ready"] + #[inline(always)] + pub fn usrrdy4(&self) -> USRRDY4_R { + USRRDY4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Channel 5 User Ready"] + #[inline(always)] + pub fn usrrdy5(&self) -> USRRDY5_R { + USRRDY5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Channel 6 User Ready"] + #[inline(always)] + pub fn usrrdy6(&self) -> USRRDY6_R { + USRRDY6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Channel 7 User Ready"] + #[inline(always)] + pub fn usrrdy7(&self) -> USRRDY7_R { + USRRDY7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 16 - Channel 0 Busy"] + #[inline(always)] + pub fn chbusy0(&self) -> CHBUSY0_R { + CHBUSY0_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Channel 1 Busy"] + #[inline(always)] + pub fn chbusy1(&self) -> CHBUSY1_R { + CHBUSY1_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Channel 2 Busy"] + #[inline(always)] + pub fn chbusy2(&self) -> CHBUSY2_R { + CHBUSY2_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Channel 3 Busy"] + #[inline(always)] + pub fn chbusy3(&self) -> CHBUSY3_R { + CHBUSY3_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Channel 4 Busy"] + #[inline(always)] + pub fn chbusy4(&self) -> CHBUSY4_R { + CHBUSY4_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Channel 5 Busy"] + #[inline(always)] + pub fn chbusy5(&self) -> CHBUSY5_R { + CHBUSY5_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Channel 6 Busy"] + #[inline(always)] + pub fn chbusy6(&self) -> CHBUSY6_R { + CHBUSY6_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Channel 7 Busy"] + #[inline(always)] + pub fn chbusy7(&self) -> CHBUSY7_R { + CHBUSY7_R::new(((self.bits >> 23) & 1) != 0) + } +} +#[doc = "Channel Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chstatus](index.html) module"] +pub struct CHSTATUS_SPEC; +impl crate::RegisterSpec for CHSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [chstatus::R](R) reader structure"] +impl crate::Readable for CHSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CHSTATUS to value 0"] +impl crate::Resettable for CHSTATUS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/evsys/ctrla.rs b/pac/atsaml22j/src/evsys/ctrla.rs new file mode 100644 index 000000000000..ec3c7f119f23 --- /dev/null +++ b/pac/atsaml22j/src/evsys/ctrla.rs @@ -0,0 +1,71 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub type SWRST_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLA_SPEC, bool, O>; +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + #[must_use] + pub fn swrst(&mut self) -> SWRST_W<0> { + SWRST_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/evsys/intenclr.rs b/pac/atsaml22j/src/evsys/intenclr.rs new file mode 100644 index 000000000000..8e67b8076763 --- /dev/null +++ b/pac/atsaml22j/src/evsys/intenclr.rs @@ -0,0 +1,305 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVR0` reader - Channel 0 Overrun Interrupt Enable"] +pub type OVR0_R = crate::BitReader; +#[doc = "Field `OVR0` writer - Channel 0 Overrun Interrupt Enable"] +pub type OVR0_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>; +#[doc = "Field `OVR1` reader - Channel 1 Overrun Interrupt Enable"] +pub type OVR1_R = crate::BitReader; +#[doc = "Field `OVR1` writer - Channel 1 Overrun Interrupt Enable"] +pub type OVR1_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>; +#[doc = "Field `OVR2` reader - Channel 2 Overrun Interrupt Enable"] +pub type OVR2_R = crate::BitReader; +#[doc = "Field `OVR2` writer - Channel 2 Overrun Interrupt Enable"] +pub type OVR2_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>; +#[doc = "Field `OVR3` reader - Channel 3 Overrun Interrupt Enable"] +pub type OVR3_R = crate::BitReader; +#[doc = "Field `OVR3` writer - Channel 3 Overrun Interrupt Enable"] +pub type OVR3_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>; +#[doc = "Field `OVR4` reader - Channel 4 Overrun Interrupt Enable"] +pub type OVR4_R = crate::BitReader; +#[doc = "Field `OVR4` writer - Channel 4 Overrun Interrupt Enable"] +pub type OVR4_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>; +#[doc = "Field `OVR5` reader - Channel 5 Overrun Interrupt Enable"] +pub type OVR5_R = crate::BitReader; +#[doc = "Field `OVR5` writer - Channel 5 Overrun Interrupt Enable"] +pub type OVR5_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>; +#[doc = "Field `OVR6` reader - Channel 6 Overrun Interrupt Enable"] +pub type OVR6_R = crate::BitReader; +#[doc = "Field `OVR6` writer - Channel 6 Overrun Interrupt Enable"] +pub type OVR6_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>; +#[doc = "Field `OVR7` reader - Channel 7 Overrun Interrupt Enable"] +pub type OVR7_R = crate::BitReader; +#[doc = "Field `OVR7` writer - Channel 7 Overrun Interrupt Enable"] +pub type OVR7_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>; +#[doc = "Field `EVD0` reader - Channel 0 Event Detection Interrupt Enable"] +pub type EVD0_R = crate::BitReader; +#[doc = "Field `EVD0` writer - Channel 0 Event Detection Interrupt Enable"] +pub type EVD0_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>; +#[doc = "Field `EVD1` reader - Channel 1 Event Detection Interrupt Enable"] +pub type EVD1_R = crate::BitReader; +#[doc = "Field `EVD1` writer - Channel 1 Event Detection Interrupt Enable"] +pub type EVD1_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>; +#[doc = "Field `EVD2` reader - Channel 2 Event Detection Interrupt Enable"] +pub type EVD2_R = crate::BitReader; +#[doc = "Field `EVD2` writer - Channel 2 Event Detection Interrupt Enable"] +pub type EVD2_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>; +#[doc = "Field `EVD3` reader - Channel 3 Event Detection Interrupt Enable"] +pub type EVD3_R = crate::BitReader; +#[doc = "Field `EVD3` writer - Channel 3 Event Detection Interrupt Enable"] +pub type EVD3_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>; +#[doc = "Field `EVD4` reader - Channel 4 Event Detection Interrupt Enable"] +pub type EVD4_R = crate::BitReader; +#[doc = "Field `EVD4` writer - Channel 4 Event Detection Interrupt Enable"] +pub type EVD4_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>; +#[doc = "Field `EVD5` reader - Channel 5 Event Detection Interrupt Enable"] +pub type EVD5_R = crate::BitReader; +#[doc = "Field `EVD5` writer - Channel 5 Event Detection Interrupt Enable"] +pub type EVD5_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>; +#[doc = "Field `EVD6` reader - Channel 6 Event Detection Interrupt Enable"] +pub type EVD6_R = crate::BitReader; +#[doc = "Field `EVD6` writer - Channel 6 Event Detection Interrupt Enable"] +pub type EVD6_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>; +#[doc = "Field `EVD7` reader - Channel 7 Event Detection Interrupt Enable"] +pub type EVD7_R = crate::BitReader; +#[doc = "Field `EVD7` writer - Channel 7 Event Detection Interrupt Enable"] +pub type EVD7_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Channel 0 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr0(&self) -> OVR0_R { + OVR0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Channel 1 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr1(&self) -> OVR1_R { + OVR1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Channel 2 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr2(&self) -> OVR2_R { + OVR2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Channel 3 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr3(&self) -> OVR3_R { + OVR3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Channel 4 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr4(&self) -> OVR4_R { + OVR4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Channel 5 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr5(&self) -> OVR5_R { + OVR5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Channel 6 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr6(&self) -> OVR6_R { + OVR6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Channel 7 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr7(&self) -> OVR7_R { + OVR7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 16 - Channel 0 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd0(&self) -> EVD0_R { + EVD0_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Channel 1 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd1(&self) -> EVD1_R { + EVD1_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Channel 2 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd2(&self) -> EVD2_R { + EVD2_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Channel 3 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd3(&self) -> EVD3_R { + EVD3_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Channel 4 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd4(&self) -> EVD4_R { + EVD4_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Channel 5 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd5(&self) -> EVD5_R { + EVD5_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Channel 6 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd6(&self) -> EVD6_R { + EVD6_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Channel 7 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd7(&self) -> EVD7_R { + EVD7_R::new(((self.bits >> 23) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Overrun Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn ovr0(&mut self) -> OVR0_W<0> { + OVR0_W::new(self) + } + #[doc = "Bit 1 - Channel 1 Overrun Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn ovr1(&mut self) -> OVR1_W<1> { + OVR1_W::new(self) + } + #[doc = "Bit 2 - Channel 2 Overrun Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn ovr2(&mut self) -> OVR2_W<2> { + OVR2_W::new(self) + } + #[doc = "Bit 3 - Channel 3 Overrun Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn ovr3(&mut self) -> OVR3_W<3> { + OVR3_W::new(self) + } + #[doc = "Bit 4 - Channel 4 Overrun Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn ovr4(&mut self) -> OVR4_W<4> { + OVR4_W::new(self) + } + #[doc = "Bit 5 - Channel 5 Overrun Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn ovr5(&mut self) -> OVR5_W<5> { + OVR5_W::new(self) + } + #[doc = "Bit 6 - Channel 6 Overrun Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn ovr6(&mut self) -> OVR6_W<6> { + OVR6_W::new(self) + } + #[doc = "Bit 7 - Channel 7 Overrun Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn ovr7(&mut self) -> OVR7_W<7> { + OVR7_W::new(self) + } + #[doc = "Bit 16 - Channel 0 Event Detection Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn evd0(&mut self) -> EVD0_W<16> { + EVD0_W::new(self) + } + #[doc = "Bit 17 - Channel 1 Event Detection Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn evd1(&mut self) -> EVD1_W<17> { + EVD1_W::new(self) + } + #[doc = "Bit 18 - Channel 2 Event Detection Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn evd2(&mut self) -> EVD2_W<18> { + EVD2_W::new(self) + } + #[doc = "Bit 19 - Channel 3 Event Detection Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn evd3(&mut self) -> EVD3_W<19> { + EVD3_W::new(self) + } + #[doc = "Bit 20 - Channel 4 Event Detection Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn evd4(&mut self) -> EVD4_W<20> { + EVD4_W::new(self) + } + #[doc = "Bit 21 - Channel 5 Event Detection Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn evd5(&mut self) -> EVD5_W<21> { + EVD5_W::new(self) + } + #[doc = "Bit 22 - Channel 6 Event Detection Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn evd6(&mut self) -> EVD6_W<22> { + EVD6_W::new(self) + } + #[doc = "Bit 23 - Channel 7 Event Detection Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn evd7(&mut self) -> EVD7_W<23> { + EVD7_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/evsys/intenset.rs b/pac/atsaml22j/src/evsys/intenset.rs new file mode 100644 index 000000000000..04db06a3f4c1 --- /dev/null +++ b/pac/atsaml22j/src/evsys/intenset.rs @@ -0,0 +1,305 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVR0` reader - Channel 0 Overrun Interrupt Enable"] +pub type OVR0_R = crate::BitReader; +#[doc = "Field `OVR0` writer - Channel 0 Overrun Interrupt Enable"] +pub type OVR0_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>; +#[doc = "Field `OVR1` reader - Channel 1 Overrun Interrupt Enable"] +pub type OVR1_R = crate::BitReader; +#[doc = "Field `OVR1` writer - Channel 1 Overrun Interrupt Enable"] +pub type OVR1_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>; +#[doc = "Field `OVR2` reader - Channel 2 Overrun Interrupt Enable"] +pub type OVR2_R = crate::BitReader; +#[doc = "Field `OVR2` writer - Channel 2 Overrun Interrupt Enable"] +pub type OVR2_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>; +#[doc = "Field `OVR3` reader - Channel 3 Overrun Interrupt Enable"] +pub type OVR3_R = crate::BitReader; +#[doc = "Field `OVR3` writer - Channel 3 Overrun Interrupt Enable"] +pub type OVR3_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>; +#[doc = "Field `OVR4` reader - Channel 4 Overrun Interrupt Enable"] +pub type OVR4_R = crate::BitReader; +#[doc = "Field `OVR4` writer - Channel 4 Overrun Interrupt Enable"] +pub type OVR4_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>; +#[doc = "Field `OVR5` reader - Channel 5 Overrun Interrupt Enable"] +pub type OVR5_R = crate::BitReader; +#[doc = "Field `OVR5` writer - Channel 5 Overrun Interrupt Enable"] +pub type OVR5_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>; +#[doc = "Field `OVR6` reader - Channel 6 Overrun Interrupt Enable"] +pub type OVR6_R = crate::BitReader; +#[doc = "Field `OVR6` writer - Channel 6 Overrun Interrupt Enable"] +pub type OVR6_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>; +#[doc = "Field `OVR7` reader - Channel 7 Overrun Interrupt Enable"] +pub type OVR7_R = crate::BitReader; +#[doc = "Field `OVR7` writer - Channel 7 Overrun Interrupt Enable"] +pub type OVR7_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>; +#[doc = "Field `EVD0` reader - Channel 0 Event Detection Interrupt Enable"] +pub type EVD0_R = crate::BitReader; +#[doc = "Field `EVD0` writer - Channel 0 Event Detection Interrupt Enable"] +pub type EVD0_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>; +#[doc = "Field `EVD1` reader - Channel 1 Event Detection Interrupt Enable"] +pub type EVD1_R = crate::BitReader; +#[doc = "Field `EVD1` writer - Channel 1 Event Detection Interrupt Enable"] +pub type EVD1_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>; +#[doc = "Field `EVD2` reader - Channel 2 Event Detection Interrupt Enable"] +pub type EVD2_R = crate::BitReader; +#[doc = "Field `EVD2` writer - Channel 2 Event Detection Interrupt Enable"] +pub type EVD2_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>; +#[doc = "Field `EVD3` reader - Channel 3 Event Detection Interrupt Enable"] +pub type EVD3_R = crate::BitReader; +#[doc = "Field `EVD3` writer - Channel 3 Event Detection Interrupt Enable"] +pub type EVD3_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>; +#[doc = "Field `EVD4` reader - Channel 4 Event Detection Interrupt Enable"] +pub type EVD4_R = crate::BitReader; +#[doc = "Field `EVD4` writer - Channel 4 Event Detection Interrupt Enable"] +pub type EVD4_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>; +#[doc = "Field `EVD5` reader - Channel 5 Event Detection Interrupt Enable"] +pub type EVD5_R = crate::BitReader; +#[doc = "Field `EVD5` writer - Channel 5 Event Detection Interrupt Enable"] +pub type EVD5_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>; +#[doc = "Field `EVD6` reader - Channel 6 Event Detection Interrupt Enable"] +pub type EVD6_R = crate::BitReader; +#[doc = "Field `EVD6` writer - Channel 6 Event Detection Interrupt Enable"] +pub type EVD6_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>; +#[doc = "Field `EVD7` reader - Channel 7 Event Detection Interrupt Enable"] +pub type EVD7_R = crate::BitReader; +#[doc = "Field `EVD7` writer - Channel 7 Event Detection Interrupt Enable"] +pub type EVD7_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Channel 0 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr0(&self) -> OVR0_R { + OVR0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Channel 1 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr1(&self) -> OVR1_R { + OVR1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Channel 2 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr2(&self) -> OVR2_R { + OVR2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Channel 3 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr3(&self) -> OVR3_R { + OVR3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Channel 4 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr4(&self) -> OVR4_R { + OVR4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Channel 5 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr5(&self) -> OVR5_R { + OVR5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Channel 6 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr6(&self) -> OVR6_R { + OVR6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Channel 7 Overrun Interrupt Enable"] + #[inline(always)] + pub fn ovr7(&self) -> OVR7_R { + OVR7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 16 - Channel 0 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd0(&self) -> EVD0_R { + EVD0_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Channel 1 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd1(&self) -> EVD1_R { + EVD1_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Channel 2 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd2(&self) -> EVD2_R { + EVD2_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Channel 3 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd3(&self) -> EVD3_R { + EVD3_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Channel 4 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd4(&self) -> EVD4_R { + EVD4_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Channel 5 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd5(&self) -> EVD5_R { + EVD5_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Channel 6 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd6(&self) -> EVD6_R { + EVD6_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Channel 7 Event Detection Interrupt Enable"] + #[inline(always)] + pub fn evd7(&self) -> EVD7_R { + EVD7_R::new(((self.bits >> 23) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Overrun Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn ovr0(&mut self) -> OVR0_W<0> { + OVR0_W::new(self) + } + #[doc = "Bit 1 - Channel 1 Overrun Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn ovr1(&mut self) -> OVR1_W<1> { + OVR1_W::new(self) + } + #[doc = "Bit 2 - Channel 2 Overrun Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn ovr2(&mut self) -> OVR2_W<2> { + OVR2_W::new(self) + } + #[doc = "Bit 3 - Channel 3 Overrun Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn ovr3(&mut self) -> OVR3_W<3> { + OVR3_W::new(self) + } + #[doc = "Bit 4 - Channel 4 Overrun Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn ovr4(&mut self) -> OVR4_W<4> { + OVR4_W::new(self) + } + #[doc = "Bit 5 - Channel 5 Overrun Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn ovr5(&mut self) -> OVR5_W<5> { + OVR5_W::new(self) + } + #[doc = "Bit 6 - Channel 6 Overrun Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn ovr6(&mut self) -> OVR6_W<6> { + OVR6_W::new(self) + } + #[doc = "Bit 7 - Channel 7 Overrun Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn ovr7(&mut self) -> OVR7_W<7> { + OVR7_W::new(self) + } + #[doc = "Bit 16 - Channel 0 Event Detection Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn evd0(&mut self) -> EVD0_W<16> { + EVD0_W::new(self) + } + #[doc = "Bit 17 - Channel 1 Event Detection Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn evd1(&mut self) -> EVD1_W<17> { + EVD1_W::new(self) + } + #[doc = "Bit 18 - Channel 2 Event Detection Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn evd2(&mut self) -> EVD2_W<18> { + EVD2_W::new(self) + } + #[doc = "Bit 19 - Channel 3 Event Detection Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn evd3(&mut self) -> EVD3_W<19> { + EVD3_W::new(self) + } + #[doc = "Bit 20 - Channel 4 Event Detection Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn evd4(&mut self) -> EVD4_W<20> { + EVD4_W::new(self) + } + #[doc = "Bit 21 - Channel 5 Event Detection Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn evd5(&mut self) -> EVD5_W<21> { + EVD5_W::new(self) + } + #[doc = "Bit 22 - Channel 6 Event Detection Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn evd6(&mut self) -> EVD6_W<22> { + EVD6_W::new(self) + } + #[doc = "Bit 23 - Channel 7 Event Detection Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn evd7(&mut self) -> EVD7_W<23> { + EVD7_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/evsys/intflag.rs b/pac/atsaml22j/src/evsys/intflag.rs new file mode 100644 index 000000000000..18a4400ac11a --- /dev/null +++ b/pac/atsaml22j/src/evsys/intflag.rs @@ -0,0 +1,305 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVR0` reader - Channel 0 Overrun"] +pub type OVR0_R = crate::BitReader; +#[doc = "Field `OVR0` writer - Channel 0 Overrun"] +pub type OVR0_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAG_SPEC, bool, O>; +#[doc = "Field `OVR1` reader - Channel 1 Overrun"] +pub type OVR1_R = crate::BitReader; +#[doc = "Field `OVR1` writer - Channel 1 Overrun"] +pub type OVR1_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAG_SPEC, bool, O>; +#[doc = "Field `OVR2` reader - Channel 2 Overrun"] +pub type OVR2_R = crate::BitReader; +#[doc = "Field `OVR2` writer - Channel 2 Overrun"] +pub type OVR2_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAG_SPEC, bool, O>; +#[doc = "Field `OVR3` reader - Channel 3 Overrun"] +pub type OVR3_R = crate::BitReader; +#[doc = "Field `OVR3` writer - Channel 3 Overrun"] +pub type OVR3_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAG_SPEC, bool, O>; +#[doc = "Field `OVR4` reader - Channel 4 Overrun"] +pub type OVR4_R = crate::BitReader; +#[doc = "Field `OVR4` writer - Channel 4 Overrun"] +pub type OVR4_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAG_SPEC, bool, O>; +#[doc = "Field `OVR5` reader - Channel 5 Overrun"] +pub type OVR5_R = crate::BitReader; +#[doc = "Field `OVR5` writer - Channel 5 Overrun"] +pub type OVR5_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAG_SPEC, bool, O>; +#[doc = "Field `OVR6` reader - Channel 6 Overrun"] +pub type OVR6_R = crate::BitReader; +#[doc = "Field `OVR6` writer - Channel 6 Overrun"] +pub type OVR6_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAG_SPEC, bool, O>; +#[doc = "Field `OVR7` reader - Channel 7 Overrun"] +pub type OVR7_R = crate::BitReader; +#[doc = "Field `OVR7` writer - Channel 7 Overrun"] +pub type OVR7_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAG_SPEC, bool, O>; +#[doc = "Field `EVD0` reader - Channel 0 Event Detection"] +pub type EVD0_R = crate::BitReader; +#[doc = "Field `EVD0` writer - Channel 0 Event Detection"] +pub type EVD0_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAG_SPEC, bool, O>; +#[doc = "Field `EVD1` reader - Channel 1 Event Detection"] +pub type EVD1_R = crate::BitReader; +#[doc = "Field `EVD1` writer - Channel 1 Event Detection"] +pub type EVD1_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAG_SPEC, bool, O>; +#[doc = "Field `EVD2` reader - Channel 2 Event Detection"] +pub type EVD2_R = crate::BitReader; +#[doc = "Field `EVD2` writer - Channel 2 Event Detection"] +pub type EVD2_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAG_SPEC, bool, O>; +#[doc = "Field `EVD3` reader - Channel 3 Event Detection"] +pub type EVD3_R = crate::BitReader; +#[doc = "Field `EVD3` writer - Channel 3 Event Detection"] +pub type EVD3_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAG_SPEC, bool, O>; +#[doc = "Field `EVD4` reader - Channel 4 Event Detection"] +pub type EVD4_R = crate::BitReader; +#[doc = "Field `EVD4` writer - Channel 4 Event Detection"] +pub type EVD4_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAG_SPEC, bool, O>; +#[doc = "Field `EVD5` reader - Channel 5 Event Detection"] +pub type EVD5_R = crate::BitReader; +#[doc = "Field `EVD5` writer - Channel 5 Event Detection"] +pub type EVD5_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAG_SPEC, bool, O>; +#[doc = "Field `EVD6` reader - Channel 6 Event Detection"] +pub type EVD6_R = crate::BitReader; +#[doc = "Field `EVD6` writer - Channel 6 Event Detection"] +pub type EVD6_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAG_SPEC, bool, O>; +#[doc = "Field `EVD7` reader - Channel 7 Event Detection"] +pub type EVD7_R = crate::BitReader; +#[doc = "Field `EVD7` writer - Channel 7 Event Detection"] +pub type EVD7_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAG_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Channel 0 Overrun"] + #[inline(always)] + pub fn ovr0(&self) -> OVR0_R { + OVR0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Channel 1 Overrun"] + #[inline(always)] + pub fn ovr1(&self) -> OVR1_R { + OVR1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Channel 2 Overrun"] + #[inline(always)] + pub fn ovr2(&self) -> OVR2_R { + OVR2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Channel 3 Overrun"] + #[inline(always)] + pub fn ovr3(&self) -> OVR3_R { + OVR3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Channel 4 Overrun"] + #[inline(always)] + pub fn ovr4(&self) -> OVR4_R { + OVR4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Channel 5 Overrun"] + #[inline(always)] + pub fn ovr5(&self) -> OVR5_R { + OVR5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Channel 6 Overrun"] + #[inline(always)] + pub fn ovr6(&self) -> OVR6_R { + OVR6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Channel 7 Overrun"] + #[inline(always)] + pub fn ovr7(&self) -> OVR7_R { + OVR7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 16 - Channel 0 Event Detection"] + #[inline(always)] + pub fn evd0(&self) -> EVD0_R { + EVD0_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Channel 1 Event Detection"] + #[inline(always)] + pub fn evd1(&self) -> EVD1_R { + EVD1_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Channel 2 Event Detection"] + #[inline(always)] + pub fn evd2(&self) -> EVD2_R { + EVD2_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Channel 3 Event Detection"] + #[inline(always)] + pub fn evd3(&self) -> EVD3_R { + EVD3_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Channel 4 Event Detection"] + #[inline(always)] + pub fn evd4(&self) -> EVD4_R { + EVD4_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Channel 5 Event Detection"] + #[inline(always)] + pub fn evd5(&self) -> EVD5_R { + EVD5_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Channel 6 Event Detection"] + #[inline(always)] + pub fn evd6(&self) -> EVD6_R { + EVD6_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Channel 7 Event Detection"] + #[inline(always)] + pub fn evd7(&self) -> EVD7_R { + EVD7_R::new(((self.bits >> 23) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Channel 0 Overrun"] + #[inline(always)] + #[must_use] + pub fn ovr0(&mut self) -> OVR0_W<0> { + OVR0_W::new(self) + } + #[doc = "Bit 1 - Channel 1 Overrun"] + #[inline(always)] + #[must_use] + pub fn ovr1(&mut self) -> OVR1_W<1> { + OVR1_W::new(self) + } + #[doc = "Bit 2 - Channel 2 Overrun"] + #[inline(always)] + #[must_use] + pub fn ovr2(&mut self) -> OVR2_W<2> { + OVR2_W::new(self) + } + #[doc = "Bit 3 - Channel 3 Overrun"] + #[inline(always)] + #[must_use] + pub fn ovr3(&mut self) -> OVR3_W<3> { + OVR3_W::new(self) + } + #[doc = "Bit 4 - Channel 4 Overrun"] + #[inline(always)] + #[must_use] + pub fn ovr4(&mut self) -> OVR4_W<4> { + OVR4_W::new(self) + } + #[doc = "Bit 5 - Channel 5 Overrun"] + #[inline(always)] + #[must_use] + pub fn ovr5(&mut self) -> OVR5_W<5> { + OVR5_W::new(self) + } + #[doc = "Bit 6 - Channel 6 Overrun"] + #[inline(always)] + #[must_use] + pub fn ovr6(&mut self) -> OVR6_W<6> { + OVR6_W::new(self) + } + #[doc = "Bit 7 - Channel 7 Overrun"] + #[inline(always)] + #[must_use] + pub fn ovr7(&mut self) -> OVR7_W<7> { + OVR7_W::new(self) + } + #[doc = "Bit 16 - Channel 0 Event Detection"] + #[inline(always)] + #[must_use] + pub fn evd0(&mut self) -> EVD0_W<16> { + EVD0_W::new(self) + } + #[doc = "Bit 17 - Channel 1 Event Detection"] + #[inline(always)] + #[must_use] + pub fn evd1(&mut self) -> EVD1_W<17> { + EVD1_W::new(self) + } + #[doc = "Bit 18 - Channel 2 Event Detection"] + #[inline(always)] + #[must_use] + pub fn evd2(&mut self) -> EVD2_W<18> { + EVD2_W::new(self) + } + #[doc = "Bit 19 - Channel 3 Event Detection"] + #[inline(always)] + #[must_use] + pub fn evd3(&mut self) -> EVD3_W<19> { + EVD3_W::new(self) + } + #[doc = "Bit 20 - Channel 4 Event Detection"] + #[inline(always)] + #[must_use] + pub fn evd4(&mut self) -> EVD4_W<20> { + EVD4_W::new(self) + } + #[doc = "Bit 21 - Channel 5 Event Detection"] + #[inline(always)] + #[must_use] + pub fn evd5(&mut self) -> EVD5_W<21> { + EVD5_W::new(self) + } + #[doc = "Bit 22 - Channel 6 Event Detection"] + #[inline(always)] + #[must_use] + pub fn evd6(&mut self) -> EVD6_W<22> { + EVD6_W::new(self) + } + #[doc = "Bit 23 - Channel 7 Event Detection"] + #[inline(always)] + #[must_use] + pub fn evd7(&mut self) -> EVD7_W<23> { + EVD7_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/evsys/swevt.rs b/pac/atsaml22j/src/evsys/swevt.rs new file mode 100644 index 000000000000..cee05b70e812 --- /dev/null +++ b/pac/atsaml22j/src/evsys/swevt.rs @@ -0,0 +1,108 @@ +#[doc = "Register `SWEVT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHANNEL0` writer - Channel 0 Software Selection"] +pub type CHANNEL0_W<'a, const O: u8> = crate::BitWriter<'a, u32, SWEVT_SPEC, bool, O>; +#[doc = "Field `CHANNEL1` writer - Channel 1 Software Selection"] +pub type CHANNEL1_W<'a, const O: u8> = crate::BitWriter<'a, u32, SWEVT_SPEC, bool, O>; +#[doc = "Field `CHANNEL2` writer - Channel 2 Software Selection"] +pub type CHANNEL2_W<'a, const O: u8> = crate::BitWriter<'a, u32, SWEVT_SPEC, bool, O>; +#[doc = "Field `CHANNEL3` writer - Channel 3 Software Selection"] +pub type CHANNEL3_W<'a, const O: u8> = crate::BitWriter<'a, u32, SWEVT_SPEC, bool, O>; +#[doc = "Field `CHANNEL4` writer - Channel 4 Software Selection"] +pub type CHANNEL4_W<'a, const O: u8> = crate::BitWriter<'a, u32, SWEVT_SPEC, bool, O>; +#[doc = "Field `CHANNEL5` writer - Channel 5 Software Selection"] +pub type CHANNEL5_W<'a, const O: u8> = crate::BitWriter<'a, u32, SWEVT_SPEC, bool, O>; +#[doc = "Field `CHANNEL6` writer - Channel 6 Software Selection"] +pub type CHANNEL6_W<'a, const O: u8> = crate::BitWriter<'a, u32, SWEVT_SPEC, bool, O>; +#[doc = "Field `CHANNEL7` writer - Channel 7 Software Selection"] +pub type CHANNEL7_W<'a, const O: u8> = crate::BitWriter<'a, u32, SWEVT_SPEC, bool, O>; +impl W { + #[doc = "Bit 0 - Channel 0 Software Selection"] + #[inline(always)] + #[must_use] + pub fn channel0(&mut self) -> CHANNEL0_W<0> { + CHANNEL0_W::new(self) + } + #[doc = "Bit 1 - Channel 1 Software Selection"] + #[inline(always)] + #[must_use] + pub fn channel1(&mut self) -> CHANNEL1_W<1> { + CHANNEL1_W::new(self) + } + #[doc = "Bit 2 - Channel 2 Software Selection"] + #[inline(always)] + #[must_use] + pub fn channel2(&mut self) -> CHANNEL2_W<2> { + CHANNEL2_W::new(self) + } + #[doc = "Bit 3 - Channel 3 Software Selection"] + #[inline(always)] + #[must_use] + pub fn channel3(&mut self) -> CHANNEL3_W<3> { + CHANNEL3_W::new(self) + } + #[doc = "Bit 4 - Channel 4 Software Selection"] + #[inline(always)] + #[must_use] + pub fn channel4(&mut self) -> CHANNEL4_W<4> { + CHANNEL4_W::new(self) + } + #[doc = "Bit 5 - Channel 5 Software Selection"] + #[inline(always)] + #[must_use] + pub fn channel5(&mut self) -> CHANNEL5_W<5> { + CHANNEL5_W::new(self) + } + #[doc = "Bit 6 - Channel 6 Software Selection"] + #[inline(always)] + #[must_use] + pub fn channel6(&mut self) -> CHANNEL6_W<6> { + CHANNEL6_W::new(self) + } + #[doc = "Bit 7 - Channel 7 Software Selection"] + #[inline(always)] + #[must_use] + pub fn channel7(&mut self) -> CHANNEL7_W<7> { + CHANNEL7_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Software Event\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [swevt](index.html) module"] +pub struct SWEVT_SPEC; +impl crate::RegisterSpec for SWEVT_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [swevt::W](W) writer structure"] +impl crate::Writable for SWEVT_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SWEVT to value 0"] +impl crate::Resettable for SWEVT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/evsys/user.rs b/pac/atsaml22j/src/evsys/user.rs new file mode 100644 index 000000000000..22b62bf3d20b --- /dev/null +++ b/pac/atsaml22j/src/evsys/user.rs @@ -0,0 +1,80 @@ +#[doc = "Register `USER%s` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `USER%s` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHANNEL` reader - Channel Event Selection"] +pub type CHANNEL_R = crate::FieldReader; +#[doc = "Field `CHANNEL` writer - Channel Event Selection"] +pub type CHANNEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, USER_SPEC, u8, u8, 4, O>; +impl R { + #[doc = "Bits 0:3 - Channel Event Selection"] + #[inline(always)] + pub fn channel(&self) -> CHANNEL_R { + CHANNEL_R::new((self.bits & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:3 - Channel Event Selection"] + #[inline(always)] + #[must_use] + pub fn channel(&mut self) -> CHANNEL_W<0> { + CHANNEL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "User Multiplexer n\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [user](index.html) module"] +pub struct USER_SPEC; +impl crate::RegisterSpec for USER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [user::R](R) reader structure"] +impl crate::Readable for USER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [user::W](W) writer structure"] +impl crate::Writable for USER_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets USER%s to value 0"] +impl crate::Resettable for USER_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/freqm.rs b/pac/atsaml22j/src/freqm.rs new file mode 100644 index 000000000000..00ad60f036e6 --- /dev/null +++ b/pac/atsaml22j/src/freqm.rs @@ -0,0 +1,59 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A Register"] + pub ctrla: CTRLA, + #[doc = "0x01 - Control B Register"] + pub ctrlb: CTRLB, + #[doc = "0x02 - Config A register"] + pub cfga: CFGA, + _reserved3: [u8; 0x04], + #[doc = "0x08 - Interrupt Enable Clear Register"] + pub intenclr: INTENCLR, + #[doc = "0x09 - Interrupt Enable Set Register"] + pub intenset: INTENSET, + #[doc = "0x0a - Interrupt Flag Register"] + pub intflag: INTFLAG, + #[doc = "0x0b - Status Register"] + pub status: STATUS, + #[doc = "0x0c - Synchronization Busy Register"] + pub syncbusy: SYNCBUSY, + #[doc = "0x10 - Count Value Register"] + pub value: VALUE, +} +#[doc = "CTRLA (rw) register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A Register"] +pub mod ctrla; +#[doc = "CTRLB (w) register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B Register"] +pub mod ctrlb; +#[doc = "CFGA (rw) register accessor: an alias for `Reg`"] +pub type CFGA = crate::Reg; +#[doc = "Config A register"] +pub mod cfga; +#[doc = "INTENCLR (rw) register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear Register"] +pub mod intenclr; +#[doc = "INTENSET (rw) register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set Register"] +pub mod intenset; +#[doc = "INTFLAG (rw) register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Register"] +pub mod intflag; +#[doc = "STATUS (rw) register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status Register"] +pub mod status; +#[doc = "SYNCBUSY (r) register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy Register"] +pub mod syncbusy; +#[doc = "VALUE (r) register accessor: an alias for `Reg`"] +pub type VALUE = crate::Reg; +#[doc = "Count Value Register"] +pub mod value; diff --git a/pac/atsaml22j/src/freqm/cfga.rs b/pac/atsaml22j/src/freqm/cfga.rs new file mode 100644 index 000000000000..e12943e835fb --- /dev/null +++ b/pac/atsaml22j/src/freqm/cfga.rs @@ -0,0 +1,80 @@ +#[doc = "Register `CFGA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CFGA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `REFNUM` reader - Number of Reference Clock Cycles"] +pub type REFNUM_R = crate::FieldReader; +#[doc = "Field `REFNUM` writer - Number of Reference Clock Cycles"] +pub type REFNUM_W<'a, const O: u8> = crate::FieldWriter<'a, u16, CFGA_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Number of Reference Clock Cycles"] + #[inline(always)] + pub fn refnum(&self) -> REFNUM_R { + REFNUM_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Number of Reference Clock Cycles"] + #[inline(always)] + #[must_use] + pub fn refnum(&mut self) -> REFNUM_W<0> { + REFNUM_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Config A register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfga](index.html) module"] +pub struct CFGA_SPEC; +impl crate::RegisterSpec for CFGA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [cfga::R](R) reader structure"] +impl crate::Readable for CFGA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cfga::W](W) writer structure"] +impl crate::Writable for CFGA_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CFGA to value 0"] +impl crate::Resettable for CFGA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/freqm/ctrla.rs b/pac/atsaml22j/src/freqm/ctrla.rs new file mode 100644 index 000000000000..b368c63f92b4 --- /dev/null +++ b/pac/atsaml22j/src/freqm/ctrla.rs @@ -0,0 +1,95 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub type SWRST_R = crate::BitReader; +#[doc = "Field `SWRST` writer - Software Reset"] +pub type SWRST_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLA_SPEC, bool, O>; +#[doc = "Field `ENABLE` reader - Enable"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - Enable"] +pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLA_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + #[must_use] + pub fn swrst(&mut self) -> SWRST_W<0> { + SWRST_W::new(self) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W<1> { + ENABLE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/freqm/ctrlb.rs b/pac/atsaml22j/src/freqm/ctrlb.rs new file mode 100644 index 000000000000..ca24815e2c66 --- /dev/null +++ b/pac/atsaml22j/src/freqm/ctrlb.rs @@ -0,0 +1,52 @@ +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `START` writer - Start Measurement"] +pub type START_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLB_SPEC, bool, O>; +impl W { + #[doc = "Bit 0 - Start Measurement"] + #[inline(always)] + #[must_use] + pub fn start(&mut self) -> START_W<0> { + START_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/freqm/intenclr.rs b/pac/atsaml22j/src/freqm/intenclr.rs new file mode 100644 index 000000000000..25b761047200 --- /dev/null +++ b/pac/atsaml22j/src/freqm/intenclr.rs @@ -0,0 +1,80 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DONE` reader - Measurement Done Interrupt Enable"] +pub type DONE_R = crate::BitReader; +#[doc = "Field `DONE` writer - Measurement Done Interrupt Enable"] +pub type DONE_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Measurement Done Interrupt Enable"] + #[inline(always)] + pub fn done(&self) -> DONE_R { + DONE_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Measurement Done Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn done(&mut self) -> DONE_W<0> { + DONE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/freqm/intenset.rs b/pac/atsaml22j/src/freqm/intenset.rs new file mode 100644 index 000000000000..4cde8baa0b1f --- /dev/null +++ b/pac/atsaml22j/src/freqm/intenset.rs @@ -0,0 +1,80 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DONE` reader - Measurement Done Interrupt Enable"] +pub type DONE_R = crate::BitReader; +#[doc = "Field `DONE` writer - Measurement Done Interrupt Enable"] +pub type DONE_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENSET_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Measurement Done Interrupt Enable"] + #[inline(always)] + pub fn done(&self) -> DONE_R { + DONE_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Measurement Done Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn done(&mut self) -> DONE_W<0> { + DONE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/freqm/intflag.rs b/pac/atsaml22j/src/freqm/intflag.rs new file mode 100644 index 000000000000..598d94a0c811 --- /dev/null +++ b/pac/atsaml22j/src/freqm/intflag.rs @@ -0,0 +1,80 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DONE` reader - Measurement Done"] +pub type DONE_R = crate::BitReader; +#[doc = "Field `DONE` writer - Measurement Done"] +pub type DONE_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTFLAG_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Measurement Done"] + #[inline(always)] + pub fn done(&self) -> DONE_R { + DONE_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Measurement Done"] + #[inline(always)] + #[must_use] + pub fn done(&mut self) -> DONE_W<0> { + DONE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/freqm/status.rs b/pac/atsaml22j/src/freqm/status.rs new file mode 100644 index 000000000000..9c5e7d63867a --- /dev/null +++ b/pac/atsaml22j/src/freqm/status.rs @@ -0,0 +1,87 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUSY` reader - FREQM Status"] +pub type BUSY_R = crate::BitReader; +#[doc = "Field `OVF` reader - Sticky Count Value Overflow"] +pub type OVF_R = crate::BitReader; +#[doc = "Field `OVF` writer - Sticky Count Value Overflow"] +pub type OVF_W<'a, const O: u8> = crate::BitWriter<'a, u8, STATUS_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - FREQM Status"] + #[inline(always)] + pub fn busy(&self) -> BUSY_R { + BUSY_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Sticky Count Value Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Sticky Count Value Overflow"] + #[inline(always)] + #[must_use] + pub fn ovf(&mut self) -> OVF_W<1> { + OVF_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/freqm/syncbusy.rs b/pac/atsaml22j/src/freqm/syncbusy.rs new file mode 100644 index 000000000000..dfdc791369c8 --- /dev/null +++ b/pac/atsaml22j/src/freqm/syncbusy.rs @@ -0,0 +1,44 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub type SWRST_R = crate::BitReader; +#[doc = "Field `ENABLE` reader - Enable"] +pub type ENABLE_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[doc = "Synchronization Busy Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/freqm/value.rs b/pac/atsaml22j/src/freqm/value.rs new file mode 100644 index 000000000000..cfcca09ab737 --- /dev/null +++ b/pac/atsaml22j/src/freqm/value.rs @@ -0,0 +1,37 @@ +#[doc = "Register `VALUE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `VALUE` reader - Measurement Value"] +pub type VALUE_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:23 - Measurement Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new(self.bits & 0x00ff_ffff) + } +} +#[doc = "Count Value Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [value](index.html) module"] +pub struct VALUE_SPEC; +impl crate::RegisterSpec for VALUE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [value::R](R) reader structure"] +impl crate::Readable for VALUE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets VALUE to value 0"] +impl crate::Resettable for VALUE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/gclk.rs b/pac/atsaml22j/src/gclk.rs new file mode 100644 index 000000000000..92355f244208 --- /dev/null +++ b/pac/atsaml22j/src/gclk.rs @@ -0,0 +1,31 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrla: CTRLA, + _reserved1: [u8; 0x03], + #[doc = "0x04 - Synchronization Busy"] + pub syncbusy: SYNCBUSY, + _reserved2: [u8; 0x18], + #[doc = "0x20..0x34 - Generic Clock Generator Control"] + pub genctrl: [GENCTRL; 5], + _reserved3: [u8; 0x4c], + #[doc = "0x80..0xf8 - Peripheral Clock Control"] + pub pchctrl: [PCHCTRL; 30], +} +#[doc = "CTRLA (rw) register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control"] +pub mod ctrla; +#[doc = "SYNCBUSY (r) register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; +#[doc = "GENCTRL (rw) register accessor: an alias for `Reg`"] +pub type GENCTRL = crate::Reg; +#[doc = "Generic Clock Generator Control"] +pub mod genctrl; +#[doc = "PCHCTRL (rw) register accessor: an alias for `Reg`"] +pub type PCHCTRL = crate::Reg; +#[doc = "Peripheral Clock Control"] +pub mod pchctrl; diff --git a/pac/atsaml22j/src/gclk/ctrla.rs b/pac/atsaml22j/src/gclk/ctrla.rs new file mode 100644 index 000000000000..f01973b7e1de --- /dev/null +++ b/pac/atsaml22j/src/gclk/ctrla.rs @@ -0,0 +1,80 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub type SWRST_R = crate::BitReader; +#[doc = "Field `SWRST` writer - Software Reset"] +pub type SWRST_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLA_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + #[must_use] + pub fn swrst(&mut self) -> SWRST_W<0> { + SWRST_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/gclk/genctrl.rs b/pac/atsaml22j/src/gclk/genctrl.rs new file mode 100644 index 000000000000..97dcd9b53b77 --- /dev/null +++ b/pac/atsaml22j/src/gclk/genctrl.rs @@ -0,0 +1,312 @@ +#[doc = "Register `GENCTRL%s` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GENCTRL%s` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SRC` reader - Source Select"] +pub type SRC_R = crate::FieldReader; +#[doc = "Source Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SRCSELECT_A { + #[doc = "0: XOSC oscillator output"] + XOSC = 0, + #[doc = "1: Generator input pad"] + GCLKIN = 1, + #[doc = "2: Generic clock generator 1 output"] + GCLKGEN1 = 2, + #[doc = "3: OSCULP32K oscillator output"] + OSCULP32K = 3, + #[doc = "4: XOSC32K oscillator output"] + XOSC32K = 4, + #[doc = "5: OSC16M oscillator output"] + OSC16M = 5, + #[doc = "6: DFLL48M output"] + DFLL48M = 6, + #[doc = "7: DPLL96M output"] + DPLL96M = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SRCSELECT_A) -> Self { + variant as _ + } +} +impl SRC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SRCSELECT_A { + match self.bits { + 0 => SRCSELECT_A::XOSC, + 1 => SRCSELECT_A::GCLKIN, + 2 => SRCSELECT_A::GCLKGEN1, + 3 => SRCSELECT_A::OSCULP32K, + 4 => SRCSELECT_A::XOSC32K, + 5 => SRCSELECT_A::OSC16M, + 6 => SRCSELECT_A::DFLL48M, + 7 => SRCSELECT_A::DPLL96M, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `XOSC`"] + #[inline(always)] + pub fn is_xosc(&self) -> bool { + *self == SRCSELECT_A::XOSC + } + #[doc = "Checks if the value of the field is `GCLKIN`"] + #[inline(always)] + pub fn is_gclkin(&self) -> bool { + *self == SRCSELECT_A::GCLKIN + } + #[doc = "Checks if the value of the field is `GCLKGEN1`"] + #[inline(always)] + pub fn is_gclkgen1(&self) -> bool { + *self == SRCSELECT_A::GCLKGEN1 + } + #[doc = "Checks if the value of the field is `OSCULP32K`"] + #[inline(always)] + pub fn is_osculp32k(&self) -> bool { + *self == SRCSELECT_A::OSCULP32K + } + #[doc = "Checks if the value of the field is `XOSC32K`"] + #[inline(always)] + pub fn is_xosc32k(&self) -> bool { + *self == SRCSELECT_A::XOSC32K + } + #[doc = "Checks if the value of the field is `OSC16M`"] + #[inline(always)] + pub fn is_osc16m(&self) -> bool { + *self == SRCSELECT_A::OSC16M + } + #[doc = "Checks if the value of the field is `DFLL48M`"] + #[inline(always)] + pub fn is_dfll48m(&self) -> bool { + *self == SRCSELECT_A::DFLL48M + } + #[doc = "Checks if the value of the field is `DPLL96M`"] + #[inline(always)] + pub fn is_dpll96m(&self) -> bool { + *self == SRCSELECT_A::DPLL96M + } +} +#[doc = "Field `SRC` writer - Source Select"] +pub type SRC_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, GENCTRL_SPEC, u8, SRCSELECT_A, 3, O>; +impl<'a, const O: u8> SRC_W<'a, O> { + #[doc = "XOSC oscillator output"] + #[inline(always)] + pub fn xosc(self) -> &'a mut W { + self.variant(SRCSELECT_A::XOSC) + } + #[doc = "Generator input pad"] + #[inline(always)] + pub fn gclkin(self) -> &'a mut W { + self.variant(SRCSELECT_A::GCLKIN) + } + #[doc = "Generic clock generator 1 output"] + #[inline(always)] + pub fn gclkgen1(self) -> &'a mut W { + self.variant(SRCSELECT_A::GCLKGEN1) + } + #[doc = "OSCULP32K oscillator output"] + #[inline(always)] + pub fn osculp32k(self) -> &'a mut W { + self.variant(SRCSELECT_A::OSCULP32K) + } + #[doc = "XOSC32K oscillator output"] + #[inline(always)] + pub fn xosc32k(self) -> &'a mut W { + self.variant(SRCSELECT_A::XOSC32K) + } + #[doc = "OSC16M oscillator output"] + #[inline(always)] + pub fn osc16m(self) -> &'a mut W { + self.variant(SRCSELECT_A::OSC16M) + } + #[doc = "DFLL48M output"] + #[inline(always)] + pub fn dfll48m(self) -> &'a mut W { + self.variant(SRCSELECT_A::DFLL48M) + } + #[doc = "DPLL96M output"] + #[inline(always)] + pub fn dpll96m(self) -> &'a mut W { + self.variant(SRCSELECT_A::DPLL96M) + } +} +#[doc = "Field `GENEN` reader - Generic Clock Generator Enable"] +pub type GENEN_R = crate::BitReader; +#[doc = "Field `GENEN` writer - Generic Clock Generator Enable"] +pub type GENEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, GENCTRL_SPEC, bool, O>; +#[doc = "Field `IDC` reader - Improve Duty Cycle"] +pub type IDC_R = crate::BitReader; +#[doc = "Field `IDC` writer - Improve Duty Cycle"] +pub type IDC_W<'a, const O: u8> = crate::BitWriter<'a, u32, GENCTRL_SPEC, bool, O>; +#[doc = "Field `OOV` reader - Output Off Value"] +pub type OOV_R = crate::BitReader; +#[doc = "Field `OOV` writer - Output Off Value"] +pub type OOV_W<'a, const O: u8> = crate::BitWriter<'a, u32, GENCTRL_SPEC, bool, O>; +#[doc = "Field `OE` reader - Output Enable"] +pub type OE_R = crate::BitReader; +#[doc = "Field `OE` writer - Output Enable"] +pub type OE_W<'a, const O: u8> = crate::BitWriter<'a, u32, GENCTRL_SPEC, bool, O>; +#[doc = "Field `DIVSEL` reader - Divide Selection"] +pub type DIVSEL_R = crate::BitReader; +#[doc = "Field `DIVSEL` writer - Divide Selection"] +pub type DIVSEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, GENCTRL_SPEC, bool, O>; +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub type RUNSTDBY_R = crate::BitReader; +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub type RUNSTDBY_W<'a, const O: u8> = crate::BitWriter<'a, u32, GENCTRL_SPEC, bool, O>; +#[doc = "Field `DIV` reader - Division Factor"] +pub type DIV_R = crate::FieldReader; +#[doc = "Field `DIV` writer - Division Factor"] +pub type DIV_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GENCTRL_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:2 - Source Select"] + #[inline(always)] + pub fn src(&self) -> SRC_R { + SRC_R::new((self.bits & 7) as u8) + } + #[doc = "Bit 8 - Generic Clock Generator Enable"] + #[inline(always)] + pub fn genen(&self) -> GENEN_R { + GENEN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Improve Duty Cycle"] + #[inline(always)] + pub fn idc(&self) -> IDC_R { + IDC_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Output Off Value"] + #[inline(always)] + pub fn oov(&self) -> OOV_R { + OOV_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Output Enable"] + #[inline(always)] + pub fn oe(&self) -> OE_R { + OE_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Divide Selection"] + #[inline(always)] + pub fn divsel(&self) -> DIVSEL_R { + DIVSEL_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bits 16:31 - Division Factor"] + #[inline(always)] + pub fn div(&self) -> DIV_R { + DIV_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:2 - Source Select"] + #[inline(always)] + #[must_use] + pub fn src(&mut self) -> SRC_W<0> { + SRC_W::new(self) + } + #[doc = "Bit 8 - Generic Clock Generator Enable"] + #[inline(always)] + #[must_use] + pub fn genen(&mut self) -> GENEN_W<8> { + GENEN_W::new(self) + } + #[doc = "Bit 9 - Improve Duty Cycle"] + #[inline(always)] + #[must_use] + pub fn idc(&mut self) -> IDC_W<9> { + IDC_W::new(self) + } + #[doc = "Bit 10 - Output Off Value"] + #[inline(always)] + #[must_use] + pub fn oov(&mut self) -> OOV_W<10> { + OOV_W::new(self) + } + #[doc = "Bit 11 - Output Enable"] + #[inline(always)] + #[must_use] + pub fn oe(&mut self) -> OE_W<11> { + OE_W::new(self) + } + #[doc = "Bit 12 - Divide Selection"] + #[inline(always)] + #[must_use] + pub fn divsel(&mut self) -> DIVSEL_W<12> { + DIVSEL_W::new(self) + } + #[doc = "Bit 13 - Run in Standby"] + #[inline(always)] + #[must_use] + pub fn runstdby(&mut self) -> RUNSTDBY_W<13> { + RUNSTDBY_W::new(self) + } + #[doc = "Bits 16:31 - Division Factor"] + #[inline(always)] + #[must_use] + pub fn div(&mut self) -> DIV_W<16> { + DIV_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Generic Clock Generator Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [genctrl](index.html) module"] +pub struct GENCTRL_SPEC; +impl crate::RegisterSpec for GENCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [genctrl::R](R) reader structure"] +impl crate::Readable for GENCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [genctrl::W](W) writer structure"] +impl crate::Writable for GENCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GENCTRL%s to value 0"] +impl crate::Resettable for GENCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/gclk/pchctrl.rs b/pac/atsaml22j/src/gclk/pchctrl.rs new file mode 100644 index 000000000000..0f80e7194d2f --- /dev/null +++ b/pac/atsaml22j/src/gclk/pchctrl.rs @@ -0,0 +1,197 @@ +#[doc = "Register `PCHCTRL%s` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PCHCTRL%s` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GEN` reader - Generic Clock Generator"] +pub type GEN_R = crate::FieldReader; +#[doc = "Generic Clock Generator\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum GENSELECT_A { + #[doc = "0: Generic clock generator 0"] + GCLK0 = 0, + #[doc = "1: Generic clock generator 1"] + GCLK1 = 1, + #[doc = "2: Generic clock generator 2"] + GCLK2 = 2, + #[doc = "3: Generic clock generator 3"] + GCLK3 = 3, + #[doc = "4: Generic clock generator 4"] + GCLK4 = 4, +} +impl From for u8 { + #[inline(always)] + fn from(variant: GENSELECT_A) -> Self { + variant as _ + } +} +impl GEN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(GENSELECT_A::GCLK0), + 1 => Some(GENSELECT_A::GCLK1), + 2 => Some(GENSELECT_A::GCLK2), + 3 => Some(GENSELECT_A::GCLK3), + 4 => Some(GENSELECT_A::GCLK4), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK0`"] + #[inline(always)] + pub fn is_gclk0(&self) -> bool { + *self == GENSELECT_A::GCLK0 + } + #[doc = "Checks if the value of the field is `GCLK1`"] + #[inline(always)] + pub fn is_gclk1(&self) -> bool { + *self == GENSELECT_A::GCLK1 + } + #[doc = "Checks if the value of the field is `GCLK2`"] + #[inline(always)] + pub fn is_gclk2(&self) -> bool { + *self == GENSELECT_A::GCLK2 + } + #[doc = "Checks if the value of the field is `GCLK3`"] + #[inline(always)] + pub fn is_gclk3(&self) -> bool { + *self == GENSELECT_A::GCLK3 + } + #[doc = "Checks if the value of the field is `GCLK4`"] + #[inline(always)] + pub fn is_gclk4(&self) -> bool { + *self == GENSELECT_A::GCLK4 + } +} +#[doc = "Field `GEN` writer - Generic Clock Generator"] +pub type GEN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PCHCTRL_SPEC, u8, GENSELECT_A, 3, O>; +impl<'a, const O: u8> GEN_W<'a, O> { + #[doc = "Generic clock generator 0"] + #[inline(always)] + pub fn gclk0(self) -> &'a mut W { + self.variant(GENSELECT_A::GCLK0) + } + #[doc = "Generic clock generator 1"] + #[inline(always)] + pub fn gclk1(self) -> &'a mut W { + self.variant(GENSELECT_A::GCLK1) + } + #[doc = "Generic clock generator 2"] + #[inline(always)] + pub fn gclk2(self) -> &'a mut W { + self.variant(GENSELECT_A::GCLK2) + } + #[doc = "Generic clock generator 3"] + #[inline(always)] + pub fn gclk3(self) -> &'a mut W { + self.variant(GENSELECT_A::GCLK3) + } + #[doc = "Generic clock generator 4"] + #[inline(always)] + pub fn gclk4(self) -> &'a mut W { + self.variant(GENSELECT_A::GCLK4) + } +} +#[doc = "Field `CHEN` reader - Channel Enable"] +pub type CHEN_R = crate::BitReader; +#[doc = "Field `CHEN` writer - Channel Enable"] +pub type CHEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCHCTRL_SPEC, bool, O>; +#[doc = "Field `WRTLOCK` reader - Write Lock"] +pub type WRTLOCK_R = crate::BitReader; +#[doc = "Field `WRTLOCK` writer - Write Lock"] +pub type WRTLOCK_W<'a, const O: u8> = crate::BitWriter<'a, u32, PCHCTRL_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:2 - Generic Clock Generator"] + #[inline(always)] + pub fn gen(&self) -> GEN_R { + GEN_R::new((self.bits & 7) as u8) + } + #[doc = "Bit 6 - Channel Enable"] + #[inline(always)] + pub fn chen(&self) -> CHEN_R { + CHEN_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&self) -> WRTLOCK_R { + WRTLOCK_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Generic Clock Generator"] + #[inline(always)] + #[must_use] + pub fn gen(&mut self) -> GEN_W<0> { + GEN_W::new(self) + } + #[doc = "Bit 6 - Channel Enable"] + #[inline(always)] + #[must_use] + pub fn chen(&mut self) -> CHEN_W<6> { + CHEN_W::new(self) + } + #[doc = "Bit 7 - Write Lock"] + #[inline(always)] + #[must_use] + pub fn wrtlock(&mut self) -> WRTLOCK_W<7> { + WRTLOCK_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Peripheral Clock Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pchctrl](index.html) module"] +pub struct PCHCTRL_SPEC; +impl crate::RegisterSpec for PCHCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pchctrl::R](R) reader structure"] +impl crate::Readable for PCHCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pchctrl::W](W) writer structure"] +impl crate::Writable for PCHCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PCHCTRL%s to value 0"] +impl crate::Resettable for PCHCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/gclk/syncbusy.rs b/pac/atsaml22j/src/gclk/syncbusy.rs new file mode 100644 index 000000000000..44dca7bdfd4f --- /dev/null +++ b/pac/atsaml22j/src/gclk/syncbusy.rs @@ -0,0 +1,207 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchroniation Busy bit"] +pub type SWRST_R = crate::BitReader; +#[doc = "Field `GENCTRL0` reader - Generic Clock Generator Control 0 Synchronization Busy bits"] +pub type GENCTRL0_R = crate::BitReader; +#[doc = "Generic Clock Generator Control 0 Synchronization Busy bits\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum GENCTRL0SELECT_A { + #[doc = "1: Generic clock generator 0"] + GCLK0 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: GENCTRL0SELECT_A) -> Self { + variant as u8 != 0 + } +} +impl GENCTRL0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + true => Some(GENCTRL0SELECT_A::GCLK0), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK0`"] + #[inline(always)] + pub fn is_gclk0(&self) -> bool { + *self == GENCTRL0SELECT_A::GCLK0 + } +} +#[doc = "Field `GENCTRL1` reader - Generic Clock Generator Control 1 Synchronization Busy bits"] +pub type GENCTRL1_R = crate::BitReader; +#[doc = "Generic Clock Generator Control 1 Synchronization Busy bits\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum GENCTRL1SELECT_A { + #[doc = "1: Generic clock generator 1"] + GCLK1 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: GENCTRL1SELECT_A) -> Self { + variant as u8 != 0 + } +} +impl GENCTRL1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + true => Some(GENCTRL1SELECT_A::GCLK1), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK1`"] + #[inline(always)] + pub fn is_gclk1(&self) -> bool { + *self == GENCTRL1SELECT_A::GCLK1 + } +} +#[doc = "Field `GENCTRL2` reader - Generic Clock Generator Control 2 Synchronization Busy bits"] +pub type GENCTRL2_R = crate::BitReader; +#[doc = "Generic Clock Generator Control 2 Synchronization Busy bits\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum GENCTRL2SELECT_A { + #[doc = "1: Generic clock generator 2"] + GCLK2 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: GENCTRL2SELECT_A) -> Self { + variant as u8 != 0 + } +} +impl GENCTRL2_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + true => Some(GENCTRL2SELECT_A::GCLK2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK2`"] + #[inline(always)] + pub fn is_gclk2(&self) -> bool { + *self == GENCTRL2SELECT_A::GCLK2 + } +} +#[doc = "Field `GENCTRL3` reader - Generic Clock Generator Control 3 Synchronization Busy bits"] +pub type GENCTRL3_R = crate::BitReader; +#[doc = "Generic Clock Generator Control 3 Synchronization Busy bits\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum GENCTRL3SELECT_A { + #[doc = "1: Generic clock generator 3"] + GCLK3 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: GENCTRL3SELECT_A) -> Self { + variant as u8 != 0 + } +} +impl GENCTRL3_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + true => Some(GENCTRL3SELECT_A::GCLK3), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK3`"] + #[inline(always)] + pub fn is_gclk3(&self) -> bool { + *self == GENCTRL3SELECT_A::GCLK3 + } +} +#[doc = "Field `GENCTRL4` reader - Generic Clock Generator Control 4 Synchronization Busy bits"] +pub type GENCTRL4_R = crate::BitReader; +#[doc = "Generic Clock Generator Control 4 Synchronization Busy bits\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum GENCTRL4SELECT_A { + #[doc = "1: Generic clock generator 4"] + GCLK4 = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: GENCTRL4SELECT_A) -> Self { + variant as u8 != 0 + } +} +impl GENCTRL4_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + true => Some(GENCTRL4SELECT_A::GCLK4), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK4`"] + #[inline(always)] + pub fn is_gclk4(&self) -> bool { + *self == GENCTRL4SELECT_A::GCLK4 + } +} +impl R { + #[doc = "Bit 0 - Software Reset Synchroniation Busy bit"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 2 - Generic Clock Generator Control 0 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl0(&self) -> GENCTRL0_R { + GENCTRL0_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Generic Clock Generator Control 1 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl1(&self) -> GENCTRL1_R { + GENCTRL1_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Generic Clock Generator Control 2 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl2(&self) -> GENCTRL2_R { + GENCTRL2_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Generic Clock Generator Control 3 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl3(&self) -> GENCTRL3_R { + GENCTRL3_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Generic Clock Generator Control 4 Synchronization Busy bits"] + #[inline(always)] + pub fn genctrl4(&self) -> GENCTRL4_R { + GENCTRL4_R::new(((self.bits >> 6) & 1) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/generic.rs b/pac/atsaml22j/src/generic.rs new file mode 100644 index 000000000000..da9c619743b7 --- /dev/null +++ b/pac/atsaml22j/src/generic.rs @@ -0,0 +1,634 @@ +use core::marker; +#[doc = " Raw register type (`u8`, `u16`, `u32`, ...)"] +pub trait RawReg: + Copy + + Default + + From + + core::ops::BitOr + + core::ops::BitAnd + + core::ops::BitOrAssign + + core::ops::BitAndAssign + + core::ops::Not + + core::ops::Shl +{ + #[doc = " Mask for bits of width `WI`"] + fn mask() -> Self; + #[doc = " Mask for bits of width 1"] + fn one() -> Self; +} +macro_rules! raw_reg { + ($ U : ty , $ size : literal , $ mask : ident) => { + impl RawReg for $U { + #[inline(always)] + fn mask() -> Self { + $mask::() + } + #[inline(always)] + fn one() -> Self { + 1 + } + } + const fn $mask() -> $U { + <$U>::MAX >> ($size - WI) + } + }; +} +raw_reg!(u8, 8, mask_u8); +raw_reg!(u16, 16, mask_u16); +raw_reg!(u32, 32, mask_u32); +raw_reg!(u64, 64, mask_u64); +#[doc = " Raw register type"] +pub trait RegisterSpec { + #[doc = " Raw register type (`u8`, `u16`, `u32`, ...)."] + type Ux: RawReg; +} +#[doc = " Trait implemented by readable registers to enable the `read` method."] +#[doc = ""] +#[doc = " Registers marked with `Writable` can be also be `modify`'ed."] +pub trait Readable: RegisterSpec { + #[doc = " Result from a call to `read` and argument to `modify`."] + type Reader: From> + core::ops::Deref>; +} +#[doc = " Trait implemented by writeable registers."] +#[doc = ""] +#[doc = " This enables the `write`, `write_with_zero` and `reset` methods."] +#[doc = ""] +#[doc = " Registers marked with `Readable` can be also be `modify`'ed."] +pub trait Writable: RegisterSpec { + #[doc = " Writer type argument to `write`, et al."] + type Writer: From> + core::ops::DerefMut>; + #[doc = " Specifies the register bits that are not changed if you pass `1` and are changed if you pass `0`"] + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux; + #[doc = " Specifies the register bits that are not changed if you pass `0` and are changed if you pass `1`"] + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux; +} +#[doc = " Reset value of the register."] +#[doc = ""] +#[doc = " This value is the initial value for the `write` method. It can also be directly written to the"] +#[doc = " register by using the `reset` method."] +pub trait Resettable: RegisterSpec { + #[doc = " Reset value of the register."] + const RESET_VALUE: Self::Ux; + #[doc = " Reset value of the register."] + #[inline(always)] + fn reset_value() -> Self::Ux { + Self::RESET_VALUE + } +} +#[doc = " This structure provides volatile access to registers."] +#[repr(transparent)] +pub struct Reg { + register: vcell::VolatileCell, + _marker: marker::PhantomData, +} +unsafe impl Send for Reg where REG::Ux: Send {} +impl Reg { + #[doc = " Returns the underlying memory address of register."] + #[doc = ""] + #[doc = " ```ignore"] + #[doc = " let reg_ptr = periph.reg.as_ptr();"] + #[doc = " ```"] + #[inline(always)] + pub fn as_ptr(&self) -> *mut REG::Ux { + self.register.as_ptr() + } +} +impl Reg { + #[doc = " Reads the contents of a `Readable` register."] + #[doc = ""] + #[doc = " You can read the raw contents of a register by using `bits`:"] + #[doc = " ```ignore"] + #[doc = " let bits = periph.reg.read().bits();"] + #[doc = " ```"] + #[doc = " or get the content of a particular field of a register:"] + #[doc = " ```ignore"] + #[doc = " let reader = periph.reg.read();"] + #[doc = " let bits = reader.field1().bits();"] + #[doc = " let flag = reader.field2().bit_is_set();"] + #[doc = " ```"] + #[inline(always)] + pub fn read(&self) -> REG::Reader { + REG::Reader::from(R { + bits: self.register.get(), + _reg: marker::PhantomData, + }) + } +} +impl Reg { + #[doc = " Writes the reset value to `Writable` register."] + #[doc = ""] + #[doc = " Resets the register to its initial state."] + #[inline(always)] + pub fn reset(&self) { + self.register.set(REG::RESET_VALUE) + } + #[doc = " Writes bits to a `Writable` register."] + #[doc = ""] + #[doc = " You can write raw bits into a register:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| unsafe { w.bits(rawbits) });"] + #[doc = " ```"] + #[doc = " or write only the fields you need:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| w"] + #[doc = " .field1().bits(newfield1bits)"] + #[doc = " .field2().set_bit()"] + #[doc = " .field3().variant(VARIANT)"] + #[doc = " );"] + #[doc = " ```"] + #[doc = " or an alternative way of saying the same:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.write(|w| {"] + #[doc = " w.field1().bits(newfield1bits);"] + #[doc = " w.field2().set_bit();"] + #[doc = " w.field3().variant(VARIANT)"] + #[doc = " });"] + #[doc = " ```"] + #[doc = " In the latter case, other fields will be set to their reset value."] + #[inline(always)] + pub fn write(&self, f: F) + where + F: FnOnce(&mut REG::Writer) -> &mut W, + { + self.register.set( + f(&mut REG::Writer::from(W { + bits: REG::RESET_VALUE & !REG::ONE_TO_MODIFY_FIELDS_BITMAP + | REG::ZERO_TO_MODIFY_FIELDS_BITMAP, + _reg: marker::PhantomData, + })) + .bits, + ); + } +} +impl Reg { + #[doc = " Writes 0 to a `Writable` register."] + #[doc = ""] + #[doc = " Similar to `write`, but unused bits will contain 0."] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " Unsafe to use with registers which don't allow to write 0."] + #[inline(always)] + pub unsafe fn write_with_zero(&self, f: F) + where + F: FnOnce(&mut REG::Writer) -> &mut W, + { + self.register.set( + f(&mut REG::Writer::from(W { + bits: REG::Ux::default(), + _reg: marker::PhantomData, + })) + .bits, + ); + } +} +impl Reg { + #[doc = " Modifies the contents of the register by reading and then writing it."] + #[doc = ""] + #[doc = " E.g. to do a read-modify-write sequence to change parts of a register:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|r, w| unsafe { w.bits("] + #[doc = " r.bits() | 3"] + #[doc = " ) });"] + #[doc = " ```"] + #[doc = " or"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|_, w| w"] + #[doc = " .field1().bits(newfield1bits)"] + #[doc = " .field2().set_bit()"] + #[doc = " .field3().variant(VARIANT)"] + #[doc = " );"] + #[doc = " ```"] + #[doc = " or an alternative way of saying the same:"] + #[doc = " ```ignore"] + #[doc = " periph.reg.modify(|_, w| {"] + #[doc = " w.field1().bits(newfield1bits);"] + #[doc = " w.field2().set_bit();"] + #[doc = " w.field3().variant(VARIANT)"] + #[doc = " });"] + #[doc = " ```"] + #[doc = " Other fields will have the value they had before the call to `modify`."] + #[inline(always)] + pub fn modify(&self, f: F) + where + for<'w> F: FnOnce(®::Reader, &'w mut REG::Writer) -> &'w mut W, + { + let bits = self.register.get(); + self.register.set( + f( + ®::Reader::from(R { + bits, + _reg: marker::PhantomData, + }), + &mut REG::Writer::from(W { + bits: bits & !REG::ONE_TO_MODIFY_FIELDS_BITMAP + | REG::ZERO_TO_MODIFY_FIELDS_BITMAP, + _reg: marker::PhantomData, + }), + ) + .bits, + ); + } +} +#[doc = " Register reader."] +#[doc = ""] +#[doc = " Result of the `read` methods of registers. Also used as a closure argument in the `modify`"] +#[doc = " method."] +pub struct R { + pub(crate) bits: REG::Ux, + _reg: marker::PhantomData, +} +impl R { + #[doc = " Reads raw bits from register."] + #[inline(always)] + pub fn bits(&self) -> REG::Ux { + self.bits + } +} +impl PartialEq for R +where + REG::Ux: PartialEq, + FI: Copy, + REG::Ux: From, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(®::Ux::from(*other)) + } +} +#[doc = " Register writer."] +#[doc = ""] +#[doc = " Used as an argument to the closures in the `write` and `modify` methods of the register."] +pub struct W { + #[doc = "Writable bits"] + pub(crate) bits: REG::Ux, + _reg: marker::PhantomData, +} +impl W { + #[doc = " Writes raw bits to the register."] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " Read datasheet or reference manual to find what values are allowed to pass."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: REG::Ux) -> &mut Self { + self.bits = bits; + self + } +} +#[doc(hidden)] +pub struct FieldReaderRaw { + pub(crate) bits: U, + _reg: marker::PhantomData, +} +impl FieldReaderRaw +where + U: Copy, +{ + #[doc = " Creates a new instance of the reader."] + #[allow(unused)] + #[inline(always)] + pub(crate) fn new(bits: U) -> Self { + Self { + bits, + _reg: marker::PhantomData, + } + } +} +#[doc(hidden)] +pub struct BitReaderRaw { + pub(crate) bits: bool, + _reg: marker::PhantomData, +} +impl BitReaderRaw { + #[doc = " Creates a new instance of the reader."] + #[allow(unused)] + #[inline(always)] + pub(crate) fn new(bits: bool) -> Self { + Self { + bits, + _reg: marker::PhantomData, + } + } +} +#[doc = " Field reader."] +#[doc = ""] +#[doc = " Result of the `read` methods of fields."] +pub type FieldReader = FieldReaderRaw; +#[doc = " Bit-wise field reader"] +pub type BitReader = BitReaderRaw; +impl FieldReader +where + U: Copy, +{ + #[doc = " Reads raw bits from field."] + #[inline(always)] + pub fn bits(&self) -> U { + self.bits + } +} +impl PartialEq for FieldReader +where + U: PartialEq, + FI: Copy, + U: From, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(&U::from(*other)) + } +} +impl PartialEq for BitReader +where + FI: Copy, + bool: From, +{ + #[inline(always)] + fn eq(&self, other: &FI) -> bool { + self.bits.eq(&bool::from(*other)) + } +} +impl BitReader { + #[doc = " Value of the field as raw bits."] + #[inline(always)] + pub fn bit(&self) -> bool { + self.bits + } + #[doc = " Returns `true` if the bit is clear (0)."] + #[inline(always)] + pub fn bit_is_clear(&self) -> bool { + !self.bit() + } + #[doc = " Returns `true` if the bit is set (1)."] + #[inline(always)] + pub fn bit_is_set(&self) -> bool { + self.bit() + } +} +#[doc(hidden)] +pub struct Safe; +#[doc(hidden)] +pub struct Unsafe; +#[doc(hidden)] +pub struct FieldWriterRaw<'a, U, REG, N, FI, Safety, const WI: u8, const O: u8> +where + REG: Writable + RegisterSpec, + N: From, +{ + pub(crate) w: &'a mut REG::Writer, + _field: marker::PhantomData<(N, FI, Safety)>, +} +impl<'a, U, REG, N, FI, Safety, const WI: u8, const O: u8> + FieldWriterRaw<'a, U, REG, N, FI, Safety, WI, O> +where + REG: Writable + RegisterSpec, + N: From, +{ + #[doc = " Creates a new instance of the writer"] + #[allow(unused)] + #[inline(always)] + pub(crate) fn new(w: &'a mut REG::Writer) -> Self { + Self { + w, + _field: marker::PhantomData, + } + } +} +#[doc(hidden)] +pub struct BitWriterRaw<'a, U, REG, FI, M, const O: u8> +where + REG: Writable + RegisterSpec, + bool: From, +{ + pub(crate) w: &'a mut REG::Writer, + _field: marker::PhantomData<(FI, M)>, +} +impl<'a, U, REG, FI, M, const O: u8> BitWriterRaw<'a, U, REG, FI, M, O> +where + REG: Writable + RegisterSpec, + bool: From, +{ + #[doc = " Creates a new instance of the writer"] + #[allow(unused)] + #[inline(always)] + pub(crate) fn new(w: &'a mut REG::Writer) -> Self { + Self { + w, + _field: marker::PhantomData, + } + } +} +#[doc = " Write field Proxy with unsafe `bits`"] +pub type FieldWriter<'a, U, REG, N, FI, const WI: u8, const O: u8> = + FieldWriterRaw<'a, U, REG, N, FI, Unsafe, WI, O>; +#[doc = " Write field Proxy with safe `bits`"] +pub type FieldWriterSafe<'a, U, REG, N, FI, const WI: u8, const O: u8> = + FieldWriterRaw<'a, U, REG, N, FI, Safe, WI, O>; +impl<'a, U, REG, N, FI, const WI: u8, const OF: u8> FieldWriter<'a, U, REG, N, FI, WI, OF> +where + REG: Writable + RegisterSpec, + N: From, +{ + #[doc = " Field width"] + pub const WIDTH: u8 = WI; +} +impl<'a, U, REG, N, FI, const WI: u8, const OF: u8> FieldWriterSafe<'a, U, REG, N, FI, WI, OF> +where + REG: Writable + RegisterSpec, + N: From, +{ + #[doc = " Field width"] + pub const WIDTH: u8 = WI; +} +macro_rules! bit_proxy { + ($ writer : ident , $ mwv : ident) => { + #[doc(hidden)] + pub struct $mwv; + #[doc = " Bit-wise write field proxy"] + pub type $writer<'a, U, REG, FI, const O: u8> = BitWriterRaw<'a, U, REG, FI, $mwv, O>; + impl<'a, U, REG, FI, const OF: u8> $writer<'a, U, REG, FI, OF> + where + REG: Writable + RegisterSpec, + bool: From, + { + #[doc = " Field width"] + pub const WIDTH: u8 = 1; + } + }; +} +macro_rules! impl_bit_proxy { + ($ writer : ident) => { + impl<'a, U, REG, FI, const OF: u8> $writer<'a, U, REG, FI, OF> + where + REG: Writable + RegisterSpec, + U: RawReg, + bool: From, + { + #[doc = " Writes bit to the field"] + #[inline(always)] + pub fn bit(self, value: bool) -> &'a mut REG::Writer { + self.w.bits &= !(U::one() << OF); + self.w.bits |= (U::from(value) & U::one()) << OF; + self.w + } + #[doc = " Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FI) -> &'a mut REG::Writer { + self.bit(bool::from(variant)) + } + } + }; +} +bit_proxy!(BitWriter, BitM); +bit_proxy!(BitWriter1S, Bit1S); +bit_proxy!(BitWriter0C, Bit0C); +bit_proxy!(BitWriter1C, Bit1C); +bit_proxy!(BitWriter0S, Bit0S); +bit_proxy!(BitWriter1T, Bit1T); +bit_proxy!(BitWriter0T, Bit0T); +impl<'a, U, REG, N, FI, const WI: u8, const OF: u8> FieldWriter<'a, U, REG, N, FI, WI, OF> +where + REG: Writable + RegisterSpec, + U: RawReg + From, + N: From, +{ + #[doc = " Writes raw bits to the field"] + #[doc = ""] + #[doc = " # Safety"] + #[doc = ""] + #[doc = " Passing incorrect value can cause undefined behaviour. See reference manual"] + #[inline(always)] + pub unsafe fn bits(self, value: N) -> &'a mut REG::Writer { + self.w.bits &= !(U::mask::() << OF); + self.w.bits |= (U::from(value) & U::mask::()) << OF; + self.w + } + #[doc = " Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FI) -> &'a mut REG::Writer { + unsafe { self.bits(N::from(variant)) } + } +} +impl<'a, U, REG, N, FI, const WI: u8, const OF: u8> FieldWriterSafe<'a, U, REG, N, FI, WI, OF> +where + REG: Writable + RegisterSpec, + U: RawReg + From, + N: From, +{ + #[doc = " Writes raw bits to the field"] + #[inline(always)] + pub fn bits(self, value: N) -> &'a mut REG::Writer { + self.w.bits &= !(U::mask::() << OF); + self.w.bits |= (U::from(value) & U::mask::()) << OF; + self.w + } + #[doc = " Writes `variant` to the field"] + #[inline(always)] + pub fn variant(self, variant: FI) -> &'a mut REG::Writer { + self.bits(N::from(variant)) + } +} +impl_bit_proxy!(BitWriter); +impl_bit_proxy!(BitWriter1S); +impl_bit_proxy!(BitWriter0C); +impl_bit_proxy!(BitWriter1C); +impl_bit_proxy!(BitWriter0S); +impl_bit_proxy!(BitWriter1T); +impl_bit_proxy!(BitWriter0T); +impl<'a, U, REG, FI, const OF: u8> BitWriter<'a, U, REG, FI, OF> +where + REG: Writable + RegisterSpec, + U: RawReg, + bool: From, +{ + #[doc = " Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut REG::Writer { + self.w.bits |= U::one() << OF; + self.w + } + #[doc = " Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut REG::Writer { + self.w.bits &= !(U::one() << OF); + self.w + } +} +impl<'a, U, REG, FI, const OF: u8> BitWriter1S<'a, U, REG, FI, OF> +where + REG: Writable + RegisterSpec, + U: RawReg, + bool: From, +{ + #[doc = " Sets the field bit"] + #[inline(always)] + pub fn set_bit(self) -> &'a mut REG::Writer { + self.w.bits |= U::one() << OF; + self.w + } +} +impl<'a, U, REG, FI, const OF: u8> BitWriter0C<'a, U, REG, FI, OF> +where + REG: Writable + RegisterSpec, + U: RawReg, + bool: From, +{ + #[doc = " Clears the field bit"] + #[inline(always)] + pub fn clear_bit(self) -> &'a mut REG::Writer { + self.w.bits &= !(U::one() << OF); + self.w + } +} +impl<'a, U, REG, FI, const OF: u8> BitWriter1C<'a, U, REG, FI, OF> +where + REG: Writable + RegisterSpec, + U: RawReg, + bool: From, +{ + #[doc = "Clears the field bit by passing one"] + #[inline(always)] + pub fn clear_bit_by_one(self) -> &'a mut REG::Writer { + self.w.bits |= U::one() << OF; + self.w + } +} +impl<'a, U, REG, FI, const OF: u8> BitWriter0S<'a, U, REG, FI, OF> +where + REG: Writable + RegisterSpec, + U: RawReg, + bool: From, +{ + #[doc = "Sets the field bit by passing zero"] + #[inline(always)] + pub fn set_bit_by_zero(self) -> &'a mut REG::Writer { + self.w.bits &= !(U::one() << OF); + self.w + } +} +impl<'a, U, REG, FI, const OF: u8> BitWriter1T<'a, U, REG, FI, OF> +where + REG: Writable + RegisterSpec, + U: RawReg, + bool: From, +{ + #[doc = "Toggle the field bit by passing one"] + #[inline(always)] + pub fn toggle_bit(self) -> &'a mut REG::Writer { + self.w.bits |= U::one() << OF; + self.w + } +} +impl<'a, U, REG, FI, const OF: u8> BitWriter0T<'a, U, REG, FI, OF> +where + REG: Writable + RegisterSpec, + U: RawReg, + bool: From, +{ + #[doc = "Toggle the field bit by passing zero"] + #[inline(always)] + pub fn toggle_bit(self) -> &'a mut REG::Writer { + self.w.bits &= !(U::one() << OF); + self.w + } +} diff --git a/pac/atsaml22j/src/lib.rs b/pac/atsaml22j/src/lib.rs new file mode 100644 index 000000000000..877175db4fef --- /dev/null +++ b/pac/atsaml22j/src/lib.rs @@ -0,0 +1,1338 @@ +#![doc = "Peripheral access API for ATSAML22J18A microcontrollers (generated using svd2rust v0.28.0 ( ))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next] +svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.28.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"] +#![deny(dead_code)] +#![deny(improper_ctypes)] +#![deny(missing_docs)] +#![deny(no_mangle_generic_items)] +#![deny(non_shorthand_field_patterns)] +#![deny(overflowing_literals)] +#![deny(path_statements)] +#![deny(patterns_in_fns_without_body)] +#![deny(private_in_public)] +#![deny(unconditional_recursion)] +#![deny(unused_allocation)] +#![deny(unused_comparisons)] +#![deny(unused_parens)] +#![deny(while_true)] +#![allow(non_camel_case_types)] +#![allow(non_snake_case)] +#![no_std] +use core::marker::PhantomData; +use core::ops::Deref; +#[doc = r"Number available in the NVIC for configuring priority"] +pub const NVIC_PRIO_BITS: u8 = 2; +#[cfg(feature = "rt")] +pub use self::Interrupt as interrupt; +pub use cortex_m::peripheral::Peripherals as CorePeripherals; +pub use cortex_m::peripheral::{CBP, CPUID, DCB, DWT, FPB, ITM, MPU, NVIC, SCB, SYST, TPIU}; +#[cfg(feature = "rt")] +pub use cortex_m_rt::interrupt; +#[allow(unused_imports)] +use generic::*; +#[doc = r"Common register and bit access and modify traits"] +pub mod generic; +#[cfg(feature = "rt")] +extern "C" { + fn SYSTEM(); + fn WDT(); + fn RTC(); + fn EIC(); + fn FREQM(); + fn USB(); + fn NVMCTRL(); + fn DMAC(); + fn EVSYS(); + fn SERCOM0(); + fn SERCOM1(); + fn SERCOM2(); + fn SERCOM3(); + fn TCC0(); + fn TC0(); + fn TC1(); + fn TC2(); + fn TC3(); + fn ADC(); + fn AC(); + fn SLCD(); + fn AES(); + fn TRNG(); +} +#[doc(hidden)] +pub union Vector { + _handler: unsafe extern "C" fn(), + _reserved: u32, +} +#[cfg(feature = "rt")] +#[doc(hidden)] +#[link_section = ".vector_table.interrupts"] +#[no_mangle] +pub static __INTERRUPTS: [Vector; 26] = [ + Vector { _handler: SYSTEM }, + Vector { _handler: WDT }, + Vector { _handler: RTC }, + Vector { _handler: EIC }, + Vector { _handler: FREQM }, + Vector { _handler: USB }, + Vector { _handler: NVMCTRL }, + Vector { _handler: DMAC }, + Vector { _handler: EVSYS }, + Vector { _handler: SERCOM0 }, + Vector { _handler: SERCOM1 }, + Vector { _handler: SERCOM2 }, + Vector { _handler: SERCOM3 }, + Vector { _reserved: 0 }, + Vector { _reserved: 0 }, + Vector { _handler: TCC0 }, + Vector { _handler: TC0 }, + Vector { _handler: TC1 }, + Vector { _handler: TC2 }, + Vector { _handler: TC3 }, + Vector { _handler: ADC }, + Vector { _handler: AC }, + Vector { _reserved: 0 }, + Vector { _handler: SLCD }, + Vector { _handler: AES }, + Vector { _handler: TRNG }, +]; +#[doc = r"Enumeration of all the interrupts."] +#[derive(Copy, Clone, Debug, PartialEq, Eq)] +#[repr(u16)] +pub enum Interrupt { + #[doc = "0 - SYSTEM"] + SYSTEM = 0, + #[doc = "1 - WDT"] + WDT = 1, + #[doc = "2 - RTC"] + RTC = 2, + #[doc = "3 - EIC"] + EIC = 3, + #[doc = "4 - FREQM"] + FREQM = 4, + #[doc = "5 - USB"] + USB = 5, + #[doc = "6 - NVMCTRL"] + NVMCTRL = 6, + #[doc = "7 - DMAC"] + DMAC = 7, + #[doc = "8 - EVSYS"] + EVSYS = 8, + #[doc = "9 - SERCOM0"] + SERCOM0 = 9, + #[doc = "10 - SERCOM1"] + SERCOM1 = 10, + #[doc = "11 - SERCOM2"] + SERCOM2 = 11, + #[doc = "12 - SERCOM3"] + SERCOM3 = 12, + #[doc = "15 - TCC0"] + TCC0 = 15, + #[doc = "16 - TC0"] + TC0 = 16, + #[doc = "17 - TC1"] + TC1 = 17, + #[doc = "18 - TC2"] + TC2 = 18, + #[doc = "19 - TC3"] + TC3 = 19, + #[doc = "20 - ADC"] + ADC = 20, + #[doc = "21 - AC"] + AC = 21, + #[doc = "23 - SLCD"] + SLCD = 23, + #[doc = "24 - AES"] + AES = 24, + #[doc = "25 - TRNG"] + TRNG = 25, +} +unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt { + #[inline(always)] + fn number(self) -> u16 { + self as u16 + } +} +#[doc = "Analog Comparators"] +pub struct AC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for AC {} +impl AC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const ac::RegisterBlock = 0x4200_3400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const ac::RegisterBlock { + Self::PTR + } +} +impl Deref for AC { + type Target = ac::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for AC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AC").finish() + } +} +#[doc = "Analog Comparators"] +pub mod ac; +#[doc = "Analog Digital Converter"] +pub struct ADC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for ADC {} +impl ADC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const adc::RegisterBlock = 0x4200_3000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const adc::RegisterBlock { + Self::PTR + } +} +impl Deref for ADC { + type Target = adc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for ADC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("ADC").finish() + } +} +#[doc = "Analog Digital Converter"] +pub mod adc; +#[doc = "Advanced Encryption Standard"] +pub struct AES { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for AES {} +impl AES { + #[doc = r"Pointer to the register block"] + pub const PTR: *const aes::RegisterBlock = 0x4200_4000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const aes::RegisterBlock { + Self::PTR + } +} +impl Deref for AES { + type Target = aes::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for AES { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("AES").finish() + } +} +#[doc = "Advanced Encryption Standard"] +pub mod aes; +#[doc = "Configurable Custom Logic"] +pub struct CCL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for CCL {} +impl CCL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const ccl::RegisterBlock = 0x4200_4800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const ccl::RegisterBlock { + Self::PTR + } +} +impl Deref for CCL { + type Target = ccl::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for CCL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("CCL").finish() + } +} +#[doc = "Configurable Custom Logic"] +pub mod ccl; +#[doc = "Direct Memory Access Controller"] +pub struct DMAC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for DMAC {} +impl DMAC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const dmac::RegisterBlock = 0x4100_8000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const dmac::RegisterBlock { + Self::PTR + } +} +impl Deref for DMAC { + type Target = dmac::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for DMAC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DMAC").finish() + } +} +#[doc = "Direct Memory Access Controller"] +pub mod dmac; +#[doc = "Device Service Unit"] +pub struct DSU { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for DSU {} +impl DSU { + #[doc = r"Pointer to the register block"] + pub const PTR: *const dsu::RegisterBlock = 0x4100_2000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const dsu::RegisterBlock { + Self::PTR + } +} +impl Deref for DSU { + type Target = dsu::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for DSU { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("DSU").finish() + } +} +#[doc = "Device Service Unit"] +pub mod dsu; +#[doc = "External Interrupt Controller"] +pub struct EIC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for EIC {} +impl EIC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const eic::RegisterBlock = 0x4000_2800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const eic::RegisterBlock { + Self::PTR + } +} +impl Deref for EIC { + type Target = eic::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for EIC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EIC").finish() + } +} +#[doc = "External Interrupt Controller"] +pub mod eic; +#[doc = "Event System Interface"] +pub struct EVSYS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for EVSYS {} +impl EVSYS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const evsys::RegisterBlock = 0x4200_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const evsys::RegisterBlock { + Self::PTR + } +} +impl Deref for EVSYS { + type Target = evsys::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for EVSYS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("EVSYS").finish() + } +} +#[doc = "Event System Interface"] +pub mod evsys; +#[doc = "Frequency Meter"] +pub struct FREQM { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for FREQM {} +impl FREQM { + #[doc = r"Pointer to the register block"] + pub const PTR: *const freqm::RegisterBlock = 0x4000_2c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const freqm::RegisterBlock { + Self::PTR + } +} +impl Deref for FREQM { + type Target = freqm::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for FREQM { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("FREQM").finish() + } +} +#[doc = "Frequency Meter"] +pub mod freqm; +#[doc = "Generic Clock Generator"] +pub struct GCLK { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for GCLK {} +impl GCLK { + #[doc = r"Pointer to the register block"] + pub const PTR: *const gclk::RegisterBlock = 0x4000_1c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const gclk::RegisterBlock { + Self::PTR + } +} +impl Deref for GCLK { + type Target = gclk::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for GCLK { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("GCLK").finish() + } +} +#[doc = "Generic Clock Generator"] +pub mod gclk; +#[doc = "Main Clock"] +pub struct MCLK { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for MCLK {} +impl MCLK { + #[doc = r"Pointer to the register block"] + pub const PTR: *const mclk::RegisterBlock = 0x4000_0800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const mclk::RegisterBlock { + Self::PTR + } +} +impl Deref for MCLK { + type Target = mclk::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for MCLK { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MCLK").finish() + } +} +#[doc = "Main Clock"] +pub mod mclk; +#[doc = "Cortex-M0+ Micro-Trace Buffer"] +pub struct MTB { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for MTB {} +impl MTB { + #[doc = r"Pointer to the register block"] + pub const PTR: *const mtb::RegisterBlock = 0x4100_a000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const mtb::RegisterBlock { + Self::PTR + } +} +impl Deref for MTB { + type Target = mtb::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for MTB { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("MTB").finish() + } +} +#[doc = "Cortex-M0+ Micro-Trace Buffer"] +pub mod mtb; +#[doc = "Non-Volatile Memory Controller"] +pub struct NVMCTRL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for NVMCTRL {} +impl NVMCTRL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const nvmctrl::RegisterBlock = 0x4100_4000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const nvmctrl::RegisterBlock { + Self::PTR + } +} +impl Deref for NVMCTRL { + type Target = nvmctrl::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for NVMCTRL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("NVMCTRL").finish() + } +} +#[doc = "Non-Volatile Memory Controller"] +pub mod nvmctrl; +#[doc = "Oscillators Control"] +pub struct OSCCTRL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for OSCCTRL {} +impl OSCCTRL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const oscctrl::RegisterBlock = 0x4000_1000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const oscctrl::RegisterBlock { + Self::PTR + } +} +impl Deref for OSCCTRL { + type Target = oscctrl::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for OSCCTRL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OSCCTRL").finish() + } +} +#[doc = "Oscillators Control"] +pub mod oscctrl; +#[doc = "32k Oscillators Control"] +pub struct OSC32KCTRL { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for OSC32KCTRL {} +impl OSC32KCTRL { + #[doc = r"Pointer to the register block"] + pub const PTR: *const osc32kctrl::RegisterBlock = 0x4000_1400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const osc32kctrl::RegisterBlock { + Self::PTR + } +} +impl Deref for OSC32KCTRL { + type Target = osc32kctrl::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for OSC32KCTRL { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("OSC32KCTRL").finish() + } +} +#[doc = "32k Oscillators Control"] +pub mod osc32kctrl; +#[doc = "Peripheral Access Controller"] +pub struct PAC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PAC {} +impl PAC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pac::RegisterBlock = 0x4000_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pac::RegisterBlock { + Self::PTR + } +} +impl Deref for PAC { + type Target = pac::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PAC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PAC").finish() + } +} +#[doc = "Peripheral Access Controller"] +pub mod pac; +#[doc = "Power Manager"] +pub struct PM { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PM {} +impl PM { + #[doc = r"Pointer to the register block"] + pub const PTR: *const pm::RegisterBlock = 0x4000_0400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const pm::RegisterBlock { + Self::PTR + } +} +impl Deref for PM { + type Target = pm::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PM { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PM").finish() + } +} +#[doc = "Power Manager"] +pub mod pm; +#[doc = "Port Module"] +pub struct PORT { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PORT {} +impl PORT { + #[doc = r"Pointer to the register block"] + pub const PTR: *const port::RegisterBlock = 0x4100_6000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const port::RegisterBlock { + Self::PTR + } +} +impl Deref for PORT { + type Target = port::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PORT { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PORT").finish() + } +} +#[doc = "Port Module"] +pub mod port; +#[doc = "Port Module (IOBUS)"] +pub struct PORT_IOBUS { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for PORT_IOBUS {} +impl PORT_IOBUS { + #[doc = r"Pointer to the register block"] + pub const PTR: *const port::RegisterBlock = 0x6000_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const port::RegisterBlock { + Self::PTR + } +} +impl Deref for PORT_IOBUS { + type Target = port::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for PORT_IOBUS { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("PORT_IOBUS").finish() + } +} +#[doc = "Port Module (IOBUS)"] +pub use self::port as port_iobus; +#[doc = "Reset Controller"] +pub struct RSTC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for RSTC {} +impl RSTC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const rstc::RegisterBlock = 0x4000_0c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const rstc::RegisterBlock { + Self::PTR + } +} +impl Deref for RSTC { + type Target = rstc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for RSTC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RSTC").finish() + } +} +#[doc = "Reset Controller"] +pub mod rstc; +#[doc = "Real-Time Counter"] +pub struct RTC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for RTC {} +impl RTC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const rtc::RegisterBlock = 0x4000_2400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const rtc::RegisterBlock { + Self::PTR + } +} +impl Deref for RTC { + type Target = rtc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for RTC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("RTC").finish() + } +} +#[doc = "Real-Time Counter"] +pub mod rtc; +#[doc = "Serial Communication Interface 0"] +pub struct SERCOM0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM0 {} +impl SERCOM0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_0400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM0 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM0").finish() + } +} +#[doc = "Serial Communication Interface 0"] +pub mod sercom0; +#[doc = "Serial Communication Interface 1"] +pub struct SERCOM1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM1 {} +impl SERCOM1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_0800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM1 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM1").finish() + } +} +#[doc = "Serial Communication Interface 1"] +pub use self::sercom0 as sercom1; +#[doc = "Serial Communication Interface 2"] +pub struct SERCOM2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM2 {} +impl SERCOM2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_0c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM2 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM2").finish() + } +} +#[doc = "Serial Communication Interface 2"] +pub use self::sercom0 as sercom2; +#[doc = "Serial Communication Interface 3"] +pub struct SERCOM3 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SERCOM3 {} +impl SERCOM3 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const sercom0::RegisterBlock = 0x4200_1000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const sercom0::RegisterBlock { + Self::PTR + } +} +impl Deref for SERCOM3 { + type Target = sercom0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SERCOM3 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SERCOM3").finish() + } +} +#[doc = "Serial Communication Interface 3"] +pub use self::sercom0 as sercom3; +#[doc = "Segment Liquid Crystal Display Controller"] +pub struct SLCD { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SLCD {} +impl SLCD { + #[doc = r"Pointer to the register block"] + pub const PTR: *const slcd::RegisterBlock = 0x4200_3c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const slcd::RegisterBlock { + Self::PTR + } +} +impl Deref for SLCD { + type Target = slcd::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SLCD { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SLCD").finish() + } +} +#[doc = "Segment Liquid Crystal Display Controller"] +pub mod slcd; +#[doc = "Supply Controller"] +pub struct SUPC { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for SUPC {} +impl SUPC { + #[doc = r"Pointer to the register block"] + pub const PTR: *const supc::RegisterBlock = 0x4000_1800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const supc::RegisterBlock { + Self::PTR + } +} +impl Deref for SUPC { + type Target = supc::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for SUPC { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("SUPC").finish() + } +} +#[doc = "Supply Controller"] +pub mod supc; +#[doc = "Basic Timer Counter 0"] +pub struct TC0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC0 {} +impl TC0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc0::RegisterBlock = 0x4200_2000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TC0 { + type Target = tc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC0").finish() + } +} +#[doc = "Basic Timer Counter 0"] +pub mod tc0; +#[doc = "Basic Timer Counter 1"] +pub struct TC1 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC1 {} +impl TC1 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc0::RegisterBlock = 0x4200_2400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TC1 { + type Target = tc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC1 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC1").finish() + } +} +#[doc = "Basic Timer Counter 1"] +pub use self::tc0 as tc1; +#[doc = "Basic Timer Counter 2"] +pub struct TC2 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC2 {} +impl TC2 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc0::RegisterBlock = 0x4200_2800 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TC2 { + type Target = tc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC2 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC2").finish() + } +} +#[doc = "Basic Timer Counter 2"] +pub use self::tc0 as tc2; +#[doc = "Basic Timer Counter 3"] +pub struct TC3 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TC3 {} +impl TC3 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tc0::RegisterBlock = 0x4200_2c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TC3 { + type Target = tc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TC3 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TC3").finish() + } +} +#[doc = "Basic Timer Counter 3"] +pub use self::tc0 as tc3; +#[doc = "Timer Counter Control"] +pub struct TCC0 { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TCC0 {} +impl TCC0 { + #[doc = r"Pointer to the register block"] + pub const PTR: *const tcc0::RegisterBlock = 0x4200_1c00 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const tcc0::RegisterBlock { + Self::PTR + } +} +impl Deref for TCC0 { + type Target = tcc0::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TCC0 { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TCC0").finish() + } +} +#[doc = "Timer Counter Control"] +pub mod tcc0; +#[doc = "True Random Generator"] +pub struct TRNG { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for TRNG {} +impl TRNG { + #[doc = r"Pointer to the register block"] + pub const PTR: *const trng::RegisterBlock = 0x4200_4400 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const trng::RegisterBlock { + Self::PTR + } +} +impl Deref for TRNG { + type Target = trng::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for TRNG { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("TRNG").finish() + } +} +#[doc = "True Random Generator"] +pub mod trng; +#[doc = "Universal Serial Bus"] +pub struct USB { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for USB {} +impl USB { + #[doc = r"Pointer to the register block"] + pub const PTR: *const usb::RegisterBlock = 0x4100_0000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const usb::RegisterBlock { + Self::PTR + } +} +impl Deref for USB { + type Target = usb::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for USB { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("USB").finish() + } +} +#[doc = "Universal Serial Bus"] +pub mod usb; +#[doc = "Watchdog Timer"] +pub struct WDT { + _marker: PhantomData<*const ()>, +} +unsafe impl Send for WDT {} +impl WDT { + #[doc = r"Pointer to the register block"] + pub const PTR: *const wdt::RegisterBlock = 0x4000_2000 as *const _; + #[doc = r"Return the pointer to the register block"] + #[inline(always)] + pub const fn ptr() -> *const wdt::RegisterBlock { + Self::PTR + } +} +impl Deref for WDT { + type Target = wdt::RegisterBlock; + #[inline(always)] + fn deref(&self) -> &Self::Target { + unsafe { &*Self::PTR } + } +} +impl core::fmt::Debug for WDT { + fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { + f.debug_struct("WDT").finish() + } +} +#[doc = "Watchdog Timer"] +pub mod wdt; +#[no_mangle] +static mut DEVICE_PERIPHERALS: bool = false; +#[doc = r" All the peripherals."] +#[allow(non_snake_case)] +pub struct Peripherals { + #[doc = "AC"] + pub AC: AC, + #[doc = "ADC"] + pub ADC: ADC, + #[doc = "AES"] + pub AES: AES, + #[doc = "CCL"] + pub CCL: CCL, + #[doc = "DMAC"] + pub DMAC: DMAC, + #[doc = "DSU"] + pub DSU: DSU, + #[doc = "EIC"] + pub EIC: EIC, + #[doc = "EVSYS"] + pub EVSYS: EVSYS, + #[doc = "FREQM"] + pub FREQM: FREQM, + #[doc = "GCLK"] + pub GCLK: GCLK, + #[doc = "MCLK"] + pub MCLK: MCLK, + #[doc = "MTB"] + pub MTB: MTB, + #[doc = "NVMCTRL"] + pub NVMCTRL: NVMCTRL, + #[doc = "OSCCTRL"] + pub OSCCTRL: OSCCTRL, + #[doc = "OSC32KCTRL"] + pub OSC32KCTRL: OSC32KCTRL, + #[doc = "PAC"] + pub PAC: PAC, + #[doc = "PM"] + pub PM: PM, + #[doc = "PORT"] + pub PORT: PORT, + #[doc = "PORT_IOBUS"] + pub PORT_IOBUS: PORT_IOBUS, + #[doc = "RSTC"] + pub RSTC: RSTC, + #[doc = "RTC"] + pub RTC: RTC, + #[doc = "SERCOM0"] + pub SERCOM0: SERCOM0, + #[doc = "SERCOM1"] + pub SERCOM1: SERCOM1, + #[doc = "SERCOM2"] + pub SERCOM2: SERCOM2, + #[doc = "SERCOM3"] + pub SERCOM3: SERCOM3, + #[doc = "SLCD"] + pub SLCD: SLCD, + #[doc = "SUPC"] + pub SUPC: SUPC, + #[doc = "TC0"] + pub TC0: TC0, + #[doc = "TC1"] + pub TC1: TC1, + #[doc = "TC2"] + pub TC2: TC2, + #[doc = "TC3"] + pub TC3: TC3, + #[doc = "TCC0"] + pub TCC0: TCC0, + #[doc = "TRNG"] + pub TRNG: TRNG, + #[doc = "USB"] + pub USB: USB, + #[doc = "WDT"] + pub WDT: WDT, +} +impl Peripherals { + #[doc = r" Returns all the peripherals *once*."] + #[cfg(feature = "critical-section")] + #[inline] + pub fn take() -> Option { + critical_section::with(|_| { + if unsafe { DEVICE_PERIPHERALS } { + return None; + } + Some(unsafe { Peripherals::steal() }) + }) + } + #[doc = r" Unchecked version of `Peripherals::take`."] + #[doc = r""] + #[doc = r" # Safety"] + #[doc = r""] + #[doc = r" Each of the returned peripherals must be used at most once."] + #[inline] + pub unsafe fn steal() -> Self { + DEVICE_PERIPHERALS = true; + Peripherals { + AC: AC { + _marker: PhantomData, + }, + ADC: ADC { + _marker: PhantomData, + }, + AES: AES { + _marker: PhantomData, + }, + CCL: CCL { + _marker: PhantomData, + }, + DMAC: DMAC { + _marker: PhantomData, + }, + DSU: DSU { + _marker: PhantomData, + }, + EIC: EIC { + _marker: PhantomData, + }, + EVSYS: EVSYS { + _marker: PhantomData, + }, + FREQM: FREQM { + _marker: PhantomData, + }, + GCLK: GCLK { + _marker: PhantomData, + }, + MCLK: MCLK { + _marker: PhantomData, + }, + MTB: MTB { + _marker: PhantomData, + }, + NVMCTRL: NVMCTRL { + _marker: PhantomData, + }, + OSCCTRL: OSCCTRL { + _marker: PhantomData, + }, + OSC32KCTRL: OSC32KCTRL { + _marker: PhantomData, + }, + PAC: PAC { + _marker: PhantomData, + }, + PM: PM { + _marker: PhantomData, + }, + PORT: PORT { + _marker: PhantomData, + }, + PORT_IOBUS: PORT_IOBUS { + _marker: PhantomData, + }, + RSTC: RSTC { + _marker: PhantomData, + }, + RTC: RTC { + _marker: PhantomData, + }, + SERCOM0: SERCOM0 { + _marker: PhantomData, + }, + SERCOM1: SERCOM1 { + _marker: PhantomData, + }, + SERCOM2: SERCOM2 { + _marker: PhantomData, + }, + SERCOM3: SERCOM3 { + _marker: PhantomData, + }, + SLCD: SLCD { + _marker: PhantomData, + }, + SUPC: SUPC { + _marker: PhantomData, + }, + TC0: TC0 { + _marker: PhantomData, + }, + TC1: TC1 { + _marker: PhantomData, + }, + TC2: TC2 { + _marker: PhantomData, + }, + TC3: TC3 { + _marker: PhantomData, + }, + TCC0: TCC0 { + _marker: PhantomData, + }, + TRNG: TRNG { + _marker: PhantomData, + }, + USB: USB { + _marker: PhantomData, + }, + WDT: WDT { + _marker: PhantomData, + }, + } + } +} diff --git a/pac/atsaml22j/src/mclk.rs b/pac/atsaml22j/src/mclk.rs new file mode 100644 index 000000000000..3772dd619904 --- /dev/null +++ b/pac/atsaml22j/src/mclk.rs @@ -0,0 +1,61 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved0: [u8; 0x01], + #[doc = "0x01 - Interrupt Enable Clear"] + pub intenclr: INTENCLR, + #[doc = "0x02 - Interrupt Enable Set"] + pub intenset: INTENSET, + #[doc = "0x03 - Interrupt Flag Status and Clear"] + pub intflag: INTFLAG, + #[doc = "0x04 - CPU Clock Division"] + pub cpudiv: CPUDIV, + _reserved4: [u8; 0x01], + #[doc = "0x06 - Backup Clock Division"] + pub bupdiv: BUPDIV, + _reserved5: [u8; 0x09], + #[doc = "0x10 - AHB Mask"] + pub ahbmask: AHBMASK, + #[doc = "0x14 - APBA Mask"] + pub apbamask: APBAMASK, + #[doc = "0x18 - APBB Mask"] + pub apbbmask: APBBMASK, + #[doc = "0x1c - APBC Mask"] + pub apbcmask: APBCMASK, +} +#[doc = "INTENCLR (rw) register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET (rw) register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG (rw) register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "CPUDIV (rw) register accessor: an alias for `Reg`"] +pub type CPUDIV = crate::Reg; +#[doc = "CPU Clock Division"] +pub mod cpudiv; +#[doc = "BUPDIV (rw) register accessor: an alias for `Reg`"] +pub type BUPDIV = crate::Reg; +#[doc = "Backup Clock Division"] +pub mod bupdiv; +#[doc = "AHBMASK (rw) register accessor: an alias for `Reg`"] +pub type AHBMASK = crate::Reg; +#[doc = "AHB Mask"] +pub mod ahbmask; +#[doc = "APBAMASK (rw) register accessor: an alias for `Reg`"] +pub type APBAMASK = crate::Reg; +#[doc = "APBA Mask"] +pub mod apbamask; +#[doc = "APBBMASK (rw) register accessor: an alias for `Reg`"] +pub type APBBMASK = crate::Reg; +#[doc = "APBB Mask"] +pub mod apbbmask; +#[doc = "APBCMASK (rw) register accessor: an alias for `Reg`"] +pub type APBCMASK = crate::Reg; +#[doc = "APBC Mask"] +pub mod apbcmask; diff --git a/pac/atsaml22j/src/mclk/ahbmask.rs b/pac/atsaml22j/src/mclk/ahbmask.rs new file mode 100644 index 000000000000..48a1f7c3f499 --- /dev/null +++ b/pac/atsaml22j/src/mclk/ahbmask.rs @@ -0,0 +1,215 @@ +#[doc = "Register `AHBMASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `AHBMASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `HPB0_` reader - HPB0 AHB Clock Mask"] +pub type HPB0__R = crate::BitReader; +#[doc = "Field `HPB0_` writer - HPB0 AHB Clock Mask"] +pub type HPB0__W<'a, const O: u8> = crate::BitWriter<'a, u32, AHBMASK_SPEC, bool, O>; +#[doc = "Field `HPB1_` reader - HPB1 AHB Clock Mask"] +pub type HPB1__R = crate::BitReader; +#[doc = "Field `HPB1_` writer - HPB1 AHB Clock Mask"] +pub type HPB1__W<'a, const O: u8> = crate::BitWriter<'a, u32, AHBMASK_SPEC, bool, O>; +#[doc = "Field `HPB2_` reader - HPB2 AHB Clock Mask"] +pub type HPB2__R = crate::BitReader; +#[doc = "Field `HPB2_` writer - HPB2 AHB Clock Mask"] +pub type HPB2__W<'a, const O: u8> = crate::BitWriter<'a, u32, AHBMASK_SPEC, bool, O>; +#[doc = "Field `DMAC_` reader - DMAC AHB Clock Mask"] +pub type DMAC__R = crate::BitReader; +#[doc = "Field `DMAC_` writer - DMAC AHB Clock Mask"] +pub type DMAC__W<'a, const O: u8> = crate::BitWriter<'a, u32, AHBMASK_SPEC, bool, O>; +#[doc = "Field `USB_` reader - USB AHB Clock Mask"] +pub type USB__R = crate::BitReader; +#[doc = "Field `USB_` writer - USB AHB Clock Mask"] +pub type USB__W<'a, const O: u8> = crate::BitWriter<'a, u32, AHBMASK_SPEC, bool, O>; +#[doc = "Field `DSU_` reader - DSU AHB Clock Mask"] +pub type DSU__R = crate::BitReader; +#[doc = "Field `DSU_` writer - DSU AHB Clock Mask"] +pub type DSU__W<'a, const O: u8> = crate::BitWriter<'a, u32, AHBMASK_SPEC, bool, O>; +#[doc = "Field `PAC_` reader - PAC AHB Clock Mask"] +pub type PAC__R = crate::BitReader; +#[doc = "Field `PAC_` writer - PAC AHB Clock Mask"] +pub type PAC__W<'a, const O: u8> = crate::BitWriter<'a, u32, AHBMASK_SPEC, bool, O>; +#[doc = "Field `NVMCTRL_` reader - NVMCTRL AHB Clock Mask"] +pub type NVMCTRL__R = crate::BitReader; +#[doc = "Field `NVMCTRL_` writer - NVMCTRL AHB Clock Mask"] +pub type NVMCTRL__W<'a, const O: u8> = crate::BitWriter<'a, u32, AHBMASK_SPEC, bool, O>; +#[doc = "Field `HSRAM_` reader - HSRAM AHB Clock Mask"] +pub type HSRAM__R = crate::BitReader; +#[doc = "Field `HSRAM_` writer - HSRAM AHB Clock Mask"] +pub type HSRAM__W<'a, const O: u8> = crate::BitWriter<'a, u32, AHBMASK_SPEC, bool, O>; +#[doc = "Field `NVMCTRL_PICACHU_` reader - NVMCTRL_PICACHU AHB Clock Mask"] +pub type NVMCTRL_PICACHU__R = crate::BitReader; +#[doc = "Field `NVMCTRL_PICACHU_` writer - NVMCTRL_PICACHU AHB Clock Mask"] +pub type NVMCTRL_PICACHU__W<'a, const O: u8> = crate::BitWriter<'a, u32, AHBMASK_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - HPB0 AHB Clock Mask"] + #[inline(always)] + pub fn hpb0_(&self) -> HPB0__R { + HPB0__R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - HPB1 AHB Clock Mask"] + #[inline(always)] + pub fn hpb1_(&self) -> HPB1__R { + HPB1__R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - HPB2 AHB Clock Mask"] + #[inline(always)] + pub fn hpb2_(&self) -> HPB2__R { + HPB2__R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - DMAC AHB Clock Mask"] + #[inline(always)] + pub fn dmac_(&self) -> DMAC__R { + DMAC__R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - USB AHB Clock Mask"] + #[inline(always)] + pub fn usb_(&self) -> USB__R { + USB__R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - DSU AHB Clock Mask"] + #[inline(always)] + pub fn dsu_(&self) -> DSU__R { + DSU__R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 7 - PAC AHB Clock Mask"] + #[inline(always)] + pub fn pac_(&self) -> PAC__R { + PAC__R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - NVMCTRL AHB Clock Mask"] + #[inline(always)] + pub fn nvmctrl_(&self) -> NVMCTRL__R { + NVMCTRL__R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - HSRAM AHB Clock Mask"] + #[inline(always)] + pub fn hsram_(&self) -> HSRAM__R { + HSRAM__R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - NVMCTRL_PICACHU AHB Clock Mask"] + #[inline(always)] + pub fn nvmctrl_picachu_(&self) -> NVMCTRL_PICACHU__R { + NVMCTRL_PICACHU__R::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - HPB0 AHB Clock Mask"] + #[inline(always)] + #[must_use] + pub fn hpb0_(&mut self) -> HPB0__W<0> { + HPB0__W::new(self) + } + #[doc = "Bit 1 - HPB1 AHB Clock Mask"] + #[inline(always)] + #[must_use] + pub fn hpb1_(&mut self) -> HPB1__W<1> { + HPB1__W::new(self) + } + #[doc = "Bit 2 - HPB2 AHB Clock Mask"] + #[inline(always)] + #[must_use] + pub fn hpb2_(&mut self) -> HPB2__W<2> { + HPB2__W::new(self) + } + #[doc = "Bit 3 - DMAC AHB Clock Mask"] + #[inline(always)] + #[must_use] + pub fn dmac_(&mut self) -> DMAC__W<3> { + DMAC__W::new(self) + } + #[doc = "Bit 4 - USB AHB Clock Mask"] + #[inline(always)] + #[must_use] + pub fn usb_(&mut self) -> USB__W<4> { + USB__W::new(self) + } + #[doc = "Bit 5 - DSU AHB Clock Mask"] + #[inline(always)] + #[must_use] + pub fn dsu_(&mut self) -> DSU__W<5> { + DSU__W::new(self) + } + #[doc = "Bit 7 - PAC AHB Clock Mask"] + #[inline(always)] + #[must_use] + pub fn pac_(&mut self) -> PAC__W<7> { + PAC__W::new(self) + } + #[doc = "Bit 8 - NVMCTRL AHB Clock Mask"] + #[inline(always)] + #[must_use] + pub fn nvmctrl_(&mut self) -> NVMCTRL__W<8> { + NVMCTRL__W::new(self) + } + #[doc = "Bit 9 - HSRAM AHB Clock Mask"] + #[inline(always)] + #[must_use] + pub fn hsram_(&mut self) -> HSRAM__W<9> { + HSRAM__W::new(self) + } + #[doc = "Bit 10 - NVMCTRL_PICACHU AHB Clock Mask"] + #[inline(always)] + #[must_use] + pub fn nvmctrl_picachu_(&mut self) -> NVMCTRL_PICACHU__W<10> { + NVMCTRL_PICACHU__W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "AHB Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ahbmask](index.html) module"] +pub struct AHBMASK_SPEC; +impl crate::RegisterSpec for AHBMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ahbmask::R](R) reader structure"] +impl crate::Readable for AHBMASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ahbmask::W](W) writer structure"] +impl crate::Writable for AHBMASK_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets AHBMASK to value 0x07ff"] +impl crate::Resettable for AHBMASK_SPEC { + const RESET_VALUE: Self::Ux = 0x07ff; +} diff --git a/pac/atsaml22j/src/mclk/apbamask.rs b/pac/atsaml22j/src/mclk/apbamask.rs new file mode 100644 index 000000000000..086373a199a3 --- /dev/null +++ b/pac/atsaml22j/src/mclk/apbamask.rs @@ -0,0 +1,245 @@ +#[doc = "Register `APBAMASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `APBAMASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PAC_` reader - PAC APB Clock Enable"] +pub type PAC__R = crate::BitReader; +#[doc = "Field `PAC_` writer - PAC APB Clock Enable"] +pub type PAC__W<'a, const O: u8> = crate::BitWriter<'a, u32, APBAMASK_SPEC, bool, O>; +#[doc = "Field `PM_` reader - PM APB Clock Enable"] +pub type PM__R = crate::BitReader; +#[doc = "Field `PM_` writer - PM APB Clock Enable"] +pub type PM__W<'a, const O: u8> = crate::BitWriter<'a, u32, APBAMASK_SPEC, bool, O>; +#[doc = "Field `MCLK_` reader - MCLK APB Clock Enable"] +pub type MCLK__R = crate::BitReader; +#[doc = "Field `MCLK_` writer - MCLK APB Clock Enable"] +pub type MCLK__W<'a, const O: u8> = crate::BitWriter<'a, u32, APBAMASK_SPEC, bool, O>; +#[doc = "Field `RSTC_` reader - RSTC APB Clock Enable"] +pub type RSTC__R = crate::BitReader; +#[doc = "Field `RSTC_` writer - RSTC APB Clock Enable"] +pub type RSTC__W<'a, const O: u8> = crate::BitWriter<'a, u32, APBAMASK_SPEC, bool, O>; +#[doc = "Field `OSCCTRL_` reader - OSCCTRL APB Clock Enable"] +pub type OSCCTRL__R = crate::BitReader; +#[doc = "Field `OSCCTRL_` writer - OSCCTRL APB Clock Enable"] +pub type OSCCTRL__W<'a, const O: u8> = crate::BitWriter<'a, u32, APBAMASK_SPEC, bool, O>; +#[doc = "Field `OSC32KCTRL_` reader - OSC32KCTRL APB Clock Enable"] +pub type OSC32KCTRL__R = crate::BitReader; +#[doc = "Field `OSC32KCTRL_` writer - OSC32KCTRL APB Clock Enable"] +pub type OSC32KCTRL__W<'a, const O: u8> = crate::BitWriter<'a, u32, APBAMASK_SPEC, bool, O>; +#[doc = "Field `SUPC_` reader - SUPC APB Clock Enable"] +pub type SUPC__R = crate::BitReader; +#[doc = "Field `SUPC_` writer - SUPC APB Clock Enable"] +pub type SUPC__W<'a, const O: u8> = crate::BitWriter<'a, u32, APBAMASK_SPEC, bool, O>; +#[doc = "Field `GCLK_` reader - GCLK APB Clock Enable"] +pub type GCLK__R = crate::BitReader; +#[doc = "Field `GCLK_` writer - GCLK APB Clock Enable"] +pub type GCLK__W<'a, const O: u8> = crate::BitWriter<'a, u32, APBAMASK_SPEC, bool, O>; +#[doc = "Field `WDT_` reader - WDT APB Clock Enable"] +pub type WDT__R = crate::BitReader; +#[doc = "Field `WDT_` writer - WDT APB Clock Enable"] +pub type WDT__W<'a, const O: u8> = crate::BitWriter<'a, u32, APBAMASK_SPEC, bool, O>; +#[doc = "Field `RTC_` reader - RTC APB Clock Enable"] +pub type RTC__R = crate::BitReader; +#[doc = "Field `RTC_` writer - RTC APB Clock Enable"] +pub type RTC__W<'a, const O: u8> = crate::BitWriter<'a, u32, APBAMASK_SPEC, bool, O>; +#[doc = "Field `EIC_` reader - EIC APB Clock Enable"] +pub type EIC__R = crate::BitReader; +#[doc = "Field `EIC_` writer - EIC APB Clock Enable"] +pub type EIC__W<'a, const O: u8> = crate::BitWriter<'a, u32, APBAMASK_SPEC, bool, O>; +#[doc = "Field `FREQM_` reader - FREQM APB Clock Enable"] +pub type FREQM__R = crate::BitReader; +#[doc = "Field `FREQM_` writer - FREQM APB Clock Enable"] +pub type FREQM__W<'a, const O: u8> = crate::BitWriter<'a, u32, APBAMASK_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - PAC APB Clock Enable"] + #[inline(always)] + pub fn pac_(&self) -> PAC__R { + PAC__R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - PM APB Clock Enable"] + #[inline(always)] + pub fn pm_(&self) -> PM__R { + PM__R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - MCLK APB Clock Enable"] + #[inline(always)] + pub fn mclk_(&self) -> MCLK__R { + MCLK__R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - RSTC APB Clock Enable"] + #[inline(always)] + pub fn rstc_(&self) -> RSTC__R { + RSTC__R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - OSCCTRL APB Clock Enable"] + #[inline(always)] + pub fn oscctrl_(&self) -> OSCCTRL__R { + OSCCTRL__R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - OSC32KCTRL APB Clock Enable"] + #[inline(always)] + pub fn osc32kctrl_(&self) -> OSC32KCTRL__R { + OSC32KCTRL__R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - SUPC APB Clock Enable"] + #[inline(always)] + pub fn supc_(&self) -> SUPC__R { + SUPC__R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - GCLK APB Clock Enable"] + #[inline(always)] + pub fn gclk_(&self) -> GCLK__R { + GCLK__R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - WDT APB Clock Enable"] + #[inline(always)] + pub fn wdt_(&self) -> WDT__R { + WDT__R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - RTC APB Clock Enable"] + #[inline(always)] + pub fn rtc_(&self) -> RTC__R { + RTC__R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - EIC APB Clock Enable"] + #[inline(always)] + pub fn eic_(&self) -> EIC__R { + EIC__R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - FREQM APB Clock Enable"] + #[inline(always)] + pub fn freqm_(&self) -> FREQM__R { + FREQM__R::new(((self.bits >> 11) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - PAC APB Clock Enable"] + #[inline(always)] + #[must_use] + pub fn pac_(&mut self) -> PAC__W<0> { + PAC__W::new(self) + } + #[doc = "Bit 1 - PM APB Clock Enable"] + #[inline(always)] + #[must_use] + pub fn pm_(&mut self) -> PM__W<1> { + PM__W::new(self) + } + #[doc = "Bit 2 - MCLK APB Clock Enable"] + #[inline(always)] + #[must_use] + pub fn mclk_(&mut self) -> MCLK__W<2> { + MCLK__W::new(self) + } + #[doc = "Bit 3 - RSTC APB Clock Enable"] + #[inline(always)] + #[must_use] + pub fn rstc_(&mut self) -> RSTC__W<3> { + RSTC__W::new(self) + } + #[doc = "Bit 4 - OSCCTRL APB Clock Enable"] + #[inline(always)] + #[must_use] + pub fn oscctrl_(&mut self) -> OSCCTRL__W<4> { + OSCCTRL__W::new(self) + } + #[doc = "Bit 5 - OSC32KCTRL APB Clock Enable"] + #[inline(always)] + #[must_use] + pub fn osc32kctrl_(&mut self) -> OSC32KCTRL__W<5> { + OSC32KCTRL__W::new(self) + } + #[doc = "Bit 6 - SUPC APB Clock Enable"] + #[inline(always)] + #[must_use] + pub fn supc_(&mut self) -> SUPC__W<6> { + SUPC__W::new(self) + } + #[doc = "Bit 7 - GCLK APB Clock Enable"] + #[inline(always)] + #[must_use] + pub fn gclk_(&mut self) -> GCLK__W<7> { + GCLK__W::new(self) + } + #[doc = "Bit 8 - WDT APB Clock Enable"] + #[inline(always)] + #[must_use] + pub fn wdt_(&mut self) -> WDT__W<8> { + WDT__W::new(self) + } + #[doc = "Bit 9 - RTC APB Clock Enable"] + #[inline(always)] + #[must_use] + pub fn rtc_(&mut self) -> RTC__W<9> { + RTC__W::new(self) + } + #[doc = "Bit 10 - EIC APB Clock Enable"] + #[inline(always)] + #[must_use] + pub fn eic_(&mut self) -> EIC__W<10> { + EIC__W::new(self) + } + #[doc = "Bit 11 - FREQM APB Clock Enable"] + #[inline(always)] + #[must_use] + pub fn freqm_(&mut self) -> FREQM__W<11> { + FREQM__W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "APBA Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apbamask](index.html) module"] +pub struct APBAMASK_SPEC; +impl crate::RegisterSpec for APBAMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [apbamask::R](R) reader structure"] +impl crate::Readable for APBAMASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [apbamask::W](W) writer structure"] +impl crate::Writable for APBAMASK_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets APBAMASK to value 0x1fff"] +impl crate::Resettable for APBAMASK_SPEC { + const RESET_VALUE: Self::Ux = 0x1fff; +} diff --git a/pac/atsaml22j/src/mclk/apbbmask.rs b/pac/atsaml22j/src/mclk/apbbmask.rs new file mode 100644 index 000000000000..4f4c47d95b1c --- /dev/null +++ b/pac/atsaml22j/src/mclk/apbbmask.rs @@ -0,0 +1,125 @@ +#[doc = "Register `APBBMASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `APBBMASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `USB_` reader - USB APB Clock Enable"] +pub type USB__R = crate::BitReader; +#[doc = "Field `USB_` writer - USB APB Clock Enable"] +pub type USB__W<'a, const O: u8> = crate::BitWriter<'a, u32, APBBMASK_SPEC, bool, O>; +#[doc = "Field `DSU_` reader - DSU APB Clock Enable"] +pub type DSU__R = crate::BitReader; +#[doc = "Field `DSU_` writer - DSU APB Clock Enable"] +pub type DSU__W<'a, const O: u8> = crate::BitWriter<'a, u32, APBBMASK_SPEC, bool, O>; +#[doc = "Field `NVMCTRL_` reader - NVMCTRL APB Clock Enable"] +pub type NVMCTRL__R = crate::BitReader; +#[doc = "Field `NVMCTRL_` writer - NVMCTRL APB Clock Enable"] +pub type NVMCTRL__W<'a, const O: u8> = crate::BitWriter<'a, u32, APBBMASK_SPEC, bool, O>; +#[doc = "Field `PORT_` reader - PORT APB Clock Enable"] +pub type PORT__R = crate::BitReader; +#[doc = "Field `PORT_` writer - PORT APB Clock Enable"] +pub type PORT__W<'a, const O: u8> = crate::BitWriter<'a, u32, APBBMASK_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - USB APB Clock Enable"] + #[inline(always)] + pub fn usb_(&self) -> USB__R { + USB__R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - DSU APB Clock Enable"] + #[inline(always)] + pub fn dsu_(&self) -> DSU__R { + DSU__R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NVMCTRL APB Clock Enable"] + #[inline(always)] + pub fn nvmctrl_(&self) -> NVMCTRL__R { + NVMCTRL__R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - PORT APB Clock Enable"] + #[inline(always)] + pub fn port_(&self) -> PORT__R { + PORT__R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - USB APB Clock Enable"] + #[inline(always)] + #[must_use] + pub fn usb_(&mut self) -> USB__W<0> { + USB__W::new(self) + } + #[doc = "Bit 1 - DSU APB Clock Enable"] + #[inline(always)] + #[must_use] + pub fn dsu_(&mut self) -> DSU__W<1> { + DSU__W::new(self) + } + #[doc = "Bit 2 - NVMCTRL APB Clock Enable"] + #[inline(always)] + #[must_use] + pub fn nvmctrl_(&mut self) -> NVMCTRL__W<2> { + NVMCTRL__W::new(self) + } + #[doc = "Bit 3 - PORT APB Clock Enable"] + #[inline(always)] + #[must_use] + pub fn port_(&mut self) -> PORT__W<3> { + PORT__W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "APBB Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apbbmask](index.html) module"] +pub struct APBBMASK_SPEC; +impl crate::RegisterSpec for APBBMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [apbbmask::R](R) reader structure"] +impl crate::Readable for APBBMASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [apbbmask::W](W) writer structure"] +impl crate::Writable for APBBMASK_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets APBBMASK to value 0x4f"] +impl crate::Resettable for APBBMASK_SPEC { + const RESET_VALUE: Self::Ux = 0x4f; +} diff --git a/pac/atsaml22j/src/mclk/apbcmask.rs b/pac/atsaml22j/src/mclk/apbcmask.rs new file mode 100644 index 000000000000..a3c4ae1388a7 --- /dev/null +++ b/pac/atsaml22j/src/mclk/apbcmask.rs @@ -0,0 +1,320 @@ +#[doc = "Register `APBCMASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `APBCMASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVSYS_` reader - EVSYS APB Clock Enable"] +pub type EVSYS__R = crate::BitReader; +#[doc = "Field `EVSYS_` writer - EVSYS APB Clock Enable"] +pub type EVSYS__W<'a, const O: u8> = crate::BitWriter<'a, u32, APBCMASK_SPEC, bool, O>; +#[doc = "Field `SERCOM0_` reader - SERCOM0 APB Clock Enable"] +pub type SERCOM0__R = crate::BitReader; +#[doc = "Field `SERCOM0_` writer - SERCOM0 APB Clock Enable"] +pub type SERCOM0__W<'a, const O: u8> = crate::BitWriter<'a, u32, APBCMASK_SPEC, bool, O>; +#[doc = "Field `SERCOM1_` reader - SERCOM1 APB Clock Enable"] +pub type SERCOM1__R = crate::BitReader; +#[doc = "Field `SERCOM1_` writer - SERCOM1 APB Clock Enable"] +pub type SERCOM1__W<'a, const O: u8> = crate::BitWriter<'a, u32, APBCMASK_SPEC, bool, O>; +#[doc = "Field `SERCOM2_` reader - SERCOM2 APB Clock Enable"] +pub type SERCOM2__R = crate::BitReader; +#[doc = "Field `SERCOM2_` writer - SERCOM2 APB Clock Enable"] +pub type SERCOM2__W<'a, const O: u8> = crate::BitWriter<'a, u32, APBCMASK_SPEC, bool, O>; +#[doc = "Field `SERCOM3_` reader - SERCOM3 APB Clock Enable"] +pub type SERCOM3__R = crate::BitReader; +#[doc = "Field `SERCOM3_` writer - SERCOM3 APB Clock Enable"] +pub type SERCOM3__W<'a, const O: u8> = crate::BitWriter<'a, u32, APBCMASK_SPEC, bool, O>; +#[doc = "Field `TCC0_` reader - TCC0 APB Clock Enable"] +pub type TCC0__R = crate::BitReader; +#[doc = "Field `TCC0_` writer - TCC0 APB Clock Enable"] +pub type TCC0__W<'a, const O: u8> = crate::BitWriter<'a, u32, APBCMASK_SPEC, bool, O>; +#[doc = "Field `TC0_` reader - TC0 APB Clock Enable"] +pub type TC0__R = crate::BitReader; +#[doc = "Field `TC0_` writer - TC0 APB Clock Enable"] +pub type TC0__W<'a, const O: u8> = crate::BitWriter<'a, u32, APBCMASK_SPEC, bool, O>; +#[doc = "Field `TC1_` reader - TC1 APB Clock Enable"] +pub type TC1__R = crate::BitReader; +#[doc = "Field `TC1_` writer - TC1 APB Clock Enable"] +pub type TC1__W<'a, const O: u8> = crate::BitWriter<'a, u32, APBCMASK_SPEC, bool, O>; +#[doc = "Field `TC2_` reader - TC2 APB Clock Enable"] +pub type TC2__R = crate::BitReader; +#[doc = "Field `TC2_` writer - TC2 APB Clock Enable"] +pub type TC2__W<'a, const O: u8> = crate::BitWriter<'a, u32, APBCMASK_SPEC, bool, O>; +#[doc = "Field `TC3_` reader - TC3 APB Clock Enable"] +pub type TC3__R = crate::BitReader; +#[doc = "Field `TC3_` writer - TC3 APB Clock Enable"] +pub type TC3__W<'a, const O: u8> = crate::BitWriter<'a, u32, APBCMASK_SPEC, bool, O>; +#[doc = "Field `ADC_` reader - ADC APB Clock Enable"] +pub type ADC__R = crate::BitReader; +#[doc = "Field `ADC_` writer - ADC APB Clock Enable"] +pub type ADC__W<'a, const O: u8> = crate::BitWriter<'a, u32, APBCMASK_SPEC, bool, O>; +#[doc = "Field `AC_` reader - AC APB Clock Enable"] +pub type AC__R = crate::BitReader; +#[doc = "Field `AC_` writer - AC APB Clock Enable"] +pub type AC__W<'a, const O: u8> = crate::BitWriter<'a, u32, APBCMASK_SPEC, bool, O>; +#[doc = "Field `PTC_` reader - PTC APB Clock Enable"] +pub type PTC__R = crate::BitReader; +#[doc = "Field `PTC_` writer - PTC APB Clock Enable"] +pub type PTC__W<'a, const O: u8> = crate::BitWriter<'a, u32, APBCMASK_SPEC, bool, O>; +#[doc = "Field `SLCD_` reader - SLCD APB Clock Enable"] +pub type SLCD__R = crate::BitReader; +#[doc = "Field `SLCD_` writer - SLCD APB Clock Enable"] +pub type SLCD__W<'a, const O: u8> = crate::BitWriter<'a, u32, APBCMASK_SPEC, bool, O>; +#[doc = "Field `AES_` reader - AES APB Clock Enable"] +pub type AES__R = crate::BitReader; +#[doc = "Field `AES_` writer - AES APB Clock Enable"] +pub type AES__W<'a, const O: u8> = crate::BitWriter<'a, u32, APBCMASK_SPEC, bool, O>; +#[doc = "Field `TRNG_` reader - TRNG APB Clock Enable"] +pub type TRNG__R = crate::BitReader; +#[doc = "Field `TRNG_` writer - TRNG APB Clock Enable"] +pub type TRNG__W<'a, const O: u8> = crate::BitWriter<'a, u32, APBCMASK_SPEC, bool, O>; +#[doc = "Field `CCL_` reader - CCL APB Clock Enable"] +pub type CCL__R = crate::BitReader; +#[doc = "Field `CCL_` writer - CCL APB Clock Enable"] +pub type CCL__W<'a, const O: u8> = crate::BitWriter<'a, u32, APBCMASK_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - EVSYS APB Clock Enable"] + #[inline(always)] + pub fn evsys_(&self) -> EVSYS__R { + EVSYS__R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - SERCOM0 APB Clock Enable"] + #[inline(always)] + pub fn sercom0_(&self) -> SERCOM0__R { + SERCOM0__R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - SERCOM1 APB Clock Enable"] + #[inline(always)] + pub fn sercom1_(&self) -> SERCOM1__R { + SERCOM1__R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - SERCOM2 APB Clock Enable"] + #[inline(always)] + pub fn sercom2_(&self) -> SERCOM2__R { + SERCOM2__R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - SERCOM3 APB Clock Enable"] + #[inline(always)] + pub fn sercom3_(&self) -> SERCOM3__R { + SERCOM3__R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 7 - TCC0 APB Clock Enable"] + #[inline(always)] + pub fn tcc0_(&self) -> TCC0__R { + TCC0__R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - TC0 APB Clock Enable"] + #[inline(always)] + pub fn tc0_(&self) -> TC0__R { + TC0__R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - TC1 APB Clock Enable"] + #[inline(always)] + pub fn tc1_(&self) -> TC1__R { + TC1__R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - TC2 APB Clock Enable"] + #[inline(always)] + pub fn tc2_(&self) -> TC2__R { + TC2__R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - TC3 APB Clock Enable"] + #[inline(always)] + pub fn tc3_(&self) -> TC3__R { + TC3__R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - ADC APB Clock Enable"] + #[inline(always)] + pub fn adc_(&self) -> ADC__R { + ADC__R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - AC APB Clock Enable"] + #[inline(always)] + pub fn ac_(&self) -> AC__R { + AC__R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - PTC APB Clock Enable"] + #[inline(always)] + pub fn ptc_(&self) -> PTC__R { + PTC__R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - SLCD APB Clock Enable"] + #[inline(always)] + pub fn slcd_(&self) -> SLCD__R { + SLCD__R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - AES APB Clock Enable"] + #[inline(always)] + pub fn aes_(&self) -> AES__R { + AES__R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - TRNG APB Clock Enable"] + #[inline(always)] + pub fn trng_(&self) -> TRNG__R { + TRNG__R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - CCL APB Clock Enable"] + #[inline(always)] + pub fn ccl_(&self) -> CCL__R { + CCL__R::new(((self.bits >> 18) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - EVSYS APB Clock Enable"] + #[inline(always)] + #[must_use] + pub fn evsys_(&mut self) -> EVSYS__W<0> { + EVSYS__W::new(self) + } + #[doc = "Bit 1 - SERCOM0 APB Clock Enable"] + #[inline(always)] + #[must_use] + pub fn sercom0_(&mut self) -> SERCOM0__W<1> { + SERCOM0__W::new(self) + } + #[doc = "Bit 2 - SERCOM1 APB Clock Enable"] + #[inline(always)] + #[must_use] + pub fn sercom1_(&mut self) -> SERCOM1__W<2> { + SERCOM1__W::new(self) + } + #[doc = "Bit 3 - SERCOM2 APB Clock Enable"] + #[inline(always)] + #[must_use] + pub fn sercom2_(&mut self) -> SERCOM2__W<3> { + SERCOM2__W::new(self) + } + #[doc = "Bit 4 - SERCOM3 APB Clock Enable"] + #[inline(always)] + #[must_use] + pub fn sercom3_(&mut self) -> SERCOM3__W<4> { + SERCOM3__W::new(self) + } + #[doc = "Bit 7 - TCC0 APB Clock Enable"] + #[inline(always)] + #[must_use] + pub fn tcc0_(&mut self) -> TCC0__W<7> { + TCC0__W::new(self) + } + #[doc = "Bit 8 - TC0 APB Clock Enable"] + #[inline(always)] + #[must_use] + pub fn tc0_(&mut self) -> TC0__W<8> { + TC0__W::new(self) + } + #[doc = "Bit 9 - TC1 APB Clock Enable"] + #[inline(always)] + #[must_use] + pub fn tc1_(&mut self) -> TC1__W<9> { + TC1__W::new(self) + } + #[doc = "Bit 10 - TC2 APB Clock Enable"] + #[inline(always)] + #[must_use] + pub fn tc2_(&mut self) -> TC2__W<10> { + TC2__W::new(self) + } + #[doc = "Bit 11 - TC3 APB Clock Enable"] + #[inline(always)] + #[must_use] + pub fn tc3_(&mut self) -> TC3__W<11> { + TC3__W::new(self) + } + #[doc = "Bit 12 - ADC APB Clock Enable"] + #[inline(always)] + #[must_use] + pub fn adc_(&mut self) -> ADC__W<12> { + ADC__W::new(self) + } + #[doc = "Bit 13 - AC APB Clock Enable"] + #[inline(always)] + #[must_use] + pub fn ac_(&mut self) -> AC__W<13> { + AC__W::new(self) + } + #[doc = "Bit 14 - PTC APB Clock Enable"] + #[inline(always)] + #[must_use] + pub fn ptc_(&mut self) -> PTC__W<14> { + PTC__W::new(self) + } + #[doc = "Bit 15 - SLCD APB Clock Enable"] + #[inline(always)] + #[must_use] + pub fn slcd_(&mut self) -> SLCD__W<15> { + SLCD__W::new(self) + } + #[doc = "Bit 16 - AES APB Clock Enable"] + #[inline(always)] + #[must_use] + pub fn aes_(&mut self) -> AES__W<16> { + AES__W::new(self) + } + #[doc = "Bit 17 - TRNG APB Clock Enable"] + #[inline(always)] + #[must_use] + pub fn trng_(&mut self) -> TRNG__W<17> { + TRNG__W::new(self) + } + #[doc = "Bit 18 - CCL APB Clock Enable"] + #[inline(always)] + #[must_use] + pub fn ccl_(&mut self) -> CCL__W<18> { + CCL__W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "APBC Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [apbcmask](index.html) module"] +pub struct APBCMASK_SPEC; +impl crate::RegisterSpec for APBCMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [apbcmask::R](R) reader structure"] +impl crate::Readable for APBCMASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [apbcmask::W](W) writer structure"] +impl crate::Writable for APBCMASK_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets APBCMASK to value 0x0007_ffff"] +impl crate::Resettable for APBCMASK_SPEC { + const RESET_VALUE: Self::Ux = 0x0007_ffff; +} diff --git a/pac/atsaml22j/src/mclk/bupdiv.rs b/pac/atsaml22j/src/mclk/bupdiv.rs new file mode 100644 index 000000000000..b947847981a2 --- /dev/null +++ b/pac/atsaml22j/src/mclk/bupdiv.rs @@ -0,0 +1,207 @@ +#[doc = "Register `BUPDIV` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BUPDIV` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUPDIV` reader - Backup Clock Division Factor"] +pub type BUPDIV_R = crate::FieldReader; +#[doc = "Backup Clock Division Factor\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum BUPDIVSELECT_A { + #[doc = "1: Divide by 1"] + DIV1 = 1, + #[doc = "2: Divide by 2"] + DIV2 = 2, + #[doc = "4: Divide by 4"] + DIV4 = 4, + #[doc = "8: Divide by 8"] + DIV8 = 8, + #[doc = "16: Divide by 16"] + DIV16 = 16, + #[doc = "32: Divide by 32"] + DIV32 = 32, + #[doc = "64: Divide by 64"] + DIV64 = 64, + #[doc = "128: Divide by 128"] + DIV128 = 128, +} +impl From for u8 { + #[inline(always)] + fn from(variant: BUPDIVSELECT_A) -> Self { + variant as _ + } +} +impl BUPDIV_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 1 => Some(BUPDIVSELECT_A::DIV1), + 2 => Some(BUPDIVSELECT_A::DIV2), + 4 => Some(BUPDIVSELECT_A::DIV4), + 8 => Some(BUPDIVSELECT_A::DIV8), + 16 => Some(BUPDIVSELECT_A::DIV16), + 32 => Some(BUPDIVSELECT_A::DIV32), + 64 => Some(BUPDIVSELECT_A::DIV64), + 128 => Some(BUPDIVSELECT_A::DIV128), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + *self == BUPDIVSELECT_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + *self == BUPDIVSELECT_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + *self == BUPDIVSELECT_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + *self == BUPDIVSELECT_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + *self == BUPDIVSELECT_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + *self == BUPDIVSELECT_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + *self == BUPDIVSELECT_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + *self == BUPDIVSELECT_A::DIV128 + } +} +#[doc = "Field `BUPDIV` writer - Backup Clock Division Factor"] +pub type BUPDIV_W<'a, const O: u8> = + crate::FieldWriter<'a, u8, BUPDIV_SPEC, u8, BUPDIVSELECT_A, 8, O>; +impl<'a, const O: u8> BUPDIV_W<'a, O> { + #[doc = "Divide by 1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(BUPDIVSELECT_A::DIV1) + } + #[doc = "Divide by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(BUPDIVSELECT_A::DIV2) + } + #[doc = "Divide by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(BUPDIVSELECT_A::DIV4) + } + #[doc = "Divide by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(BUPDIVSELECT_A::DIV8) + } + #[doc = "Divide by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(BUPDIVSELECT_A::DIV16) + } + #[doc = "Divide by 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(BUPDIVSELECT_A::DIV32) + } + #[doc = "Divide by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(BUPDIVSELECT_A::DIV64) + } + #[doc = "Divide by 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(BUPDIVSELECT_A::DIV128) + } +} +impl R { + #[doc = "Bits 0:7 - Backup Clock Division Factor"] + #[inline(always)] + pub fn bupdiv(&self) -> BUPDIV_R { + BUPDIV_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:7 - Backup Clock Division Factor"] + #[inline(always)] + #[must_use] + pub fn bupdiv(&mut self) -> BUPDIV_W<0> { + BUPDIV_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Backup Clock Division\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bupdiv](index.html) module"] +pub struct BUPDIV_SPEC; +impl crate::RegisterSpec for BUPDIV_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [bupdiv::R](R) reader structure"] +impl crate::Readable for BUPDIV_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [bupdiv::W](W) writer structure"] +impl crate::Writable for BUPDIV_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BUPDIV to value 0x01"] +impl crate::Resettable for BUPDIV_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/pac/atsaml22j/src/mclk/cpudiv.rs b/pac/atsaml22j/src/mclk/cpudiv.rs new file mode 100644 index 000000000000..0f499a1001a4 --- /dev/null +++ b/pac/atsaml22j/src/mclk/cpudiv.rs @@ -0,0 +1,207 @@ +#[doc = "Register `CPUDIV` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CPUDIV` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CPUDIV` reader - CPU Clock Division Factor"] +pub type CPUDIV_R = crate::FieldReader; +#[doc = "CPU Clock Division Factor\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum CPUDIVSELECT_A { + #[doc = "1: Divide by 1"] + DIV1 = 1, + #[doc = "2: Divide by 2"] + DIV2 = 2, + #[doc = "4: Divide by 4"] + DIV4 = 4, + #[doc = "8: Divide by 8"] + DIV8 = 8, + #[doc = "16: Divide by 16"] + DIV16 = 16, + #[doc = "32: Divide by 32"] + DIV32 = 32, + #[doc = "64: Divide by 64"] + DIV64 = 64, + #[doc = "128: Divide by 128"] + DIV128 = 128, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CPUDIVSELECT_A) -> Self { + variant as _ + } +} +impl CPUDIV_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 1 => Some(CPUDIVSELECT_A::DIV1), + 2 => Some(CPUDIVSELECT_A::DIV2), + 4 => Some(CPUDIVSELECT_A::DIV4), + 8 => Some(CPUDIVSELECT_A::DIV8), + 16 => Some(CPUDIVSELECT_A::DIV16), + 32 => Some(CPUDIVSELECT_A::DIV32), + 64 => Some(CPUDIVSELECT_A::DIV64), + 128 => Some(CPUDIVSELECT_A::DIV128), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + *self == CPUDIVSELECT_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + *self == CPUDIVSELECT_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + *self == CPUDIVSELECT_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + *self == CPUDIVSELECT_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + *self == CPUDIVSELECT_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + *self == CPUDIVSELECT_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + *self == CPUDIVSELECT_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + *self == CPUDIVSELECT_A::DIV128 + } +} +#[doc = "Field `CPUDIV` writer - CPU Clock Division Factor"] +pub type CPUDIV_W<'a, const O: u8> = + crate::FieldWriter<'a, u8, CPUDIV_SPEC, u8, CPUDIVSELECT_A, 8, O>; +impl<'a, const O: u8> CPUDIV_W<'a, O> { + #[doc = "Divide by 1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(CPUDIVSELECT_A::DIV1) + } + #[doc = "Divide by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(CPUDIVSELECT_A::DIV2) + } + #[doc = "Divide by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(CPUDIVSELECT_A::DIV4) + } + #[doc = "Divide by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(CPUDIVSELECT_A::DIV8) + } + #[doc = "Divide by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(CPUDIVSELECT_A::DIV16) + } + #[doc = "Divide by 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(CPUDIVSELECT_A::DIV32) + } + #[doc = "Divide by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(CPUDIVSELECT_A::DIV64) + } + #[doc = "Divide by 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(CPUDIVSELECT_A::DIV128) + } +} +impl R { + #[doc = "Bits 0:7 - CPU Clock Division Factor"] + #[inline(always)] + pub fn cpudiv(&self) -> CPUDIV_R { + CPUDIV_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:7 - CPU Clock Division Factor"] + #[inline(always)] + #[must_use] + pub fn cpudiv(&mut self) -> CPUDIV_W<0> { + CPUDIV_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "CPU Clock Division\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cpudiv](index.html) module"] +pub struct CPUDIV_SPEC; +impl crate::RegisterSpec for CPUDIV_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [cpudiv::R](R) reader structure"] +impl crate::Readable for CPUDIV_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cpudiv::W](W) writer structure"] +impl crate::Writable for CPUDIV_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CPUDIV to value 0x01"] +impl crate::Resettable for CPUDIV_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/pac/atsaml22j/src/mclk/intenclr.rs b/pac/atsaml22j/src/mclk/intenclr.rs new file mode 100644 index 000000000000..a3e73e055f72 --- /dev/null +++ b/pac/atsaml22j/src/mclk/intenclr.rs @@ -0,0 +1,80 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CKRDY` reader - Clock Ready Interrupt Enable"] +pub type CKRDY_R = crate::BitReader; +#[doc = "Field `CKRDY` writer - Clock Ready Interrupt Enable"] +pub type CKRDY_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Clock Ready Interrupt Enable"] + #[inline(always)] + pub fn ckrdy(&self) -> CKRDY_R { + CKRDY_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Ready Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn ckrdy(&mut self) -> CKRDY_W<0> { + CKRDY_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/mclk/intenset.rs b/pac/atsaml22j/src/mclk/intenset.rs new file mode 100644 index 000000000000..c397777e356c --- /dev/null +++ b/pac/atsaml22j/src/mclk/intenset.rs @@ -0,0 +1,80 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CKRDY` reader - Clock Ready Interrupt Enable"] +pub type CKRDY_R = crate::BitReader; +#[doc = "Field `CKRDY` writer - Clock Ready Interrupt Enable"] +pub type CKRDY_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENSET_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Clock Ready Interrupt Enable"] + #[inline(always)] + pub fn ckrdy(&self) -> CKRDY_R { + CKRDY_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Ready Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn ckrdy(&mut self) -> CKRDY_W<0> { + CKRDY_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/mclk/intflag.rs b/pac/atsaml22j/src/mclk/intflag.rs new file mode 100644 index 000000000000..8f53a58c2fe4 --- /dev/null +++ b/pac/atsaml22j/src/mclk/intflag.rs @@ -0,0 +1,80 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CKRDY` reader - Clock Ready"] +pub type CKRDY_R = crate::BitReader; +#[doc = "Field `CKRDY` writer - Clock Ready"] +pub type CKRDY_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTFLAG_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Clock Ready"] + #[inline(always)] + pub fn ckrdy(&self) -> CKRDY_R { + CKRDY_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Ready"] + #[inline(always)] + #[must_use] + pub fn ckrdy(&mut self) -> CKRDY_W<0> { + CKRDY_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTFLAG to value 0x01"] +impl crate::Resettable for INTFLAG_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/pac/atsaml22j/src/mtb.rs b/pac/atsaml22j/src/mtb.rs new file mode 100644 index 000000000000..20ad48d545ec --- /dev/null +++ b/pac/atsaml22j/src/mtb.rs @@ -0,0 +1,158 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - MTB Position"] + pub position: POSITION, + #[doc = "0x04 - MTB Master"] + pub master: MASTER, + #[doc = "0x08 - MTB Flow"] + pub flow: FLOW, + #[doc = "0x0c - MTB Base"] + pub base: BASE, + _reserved4: [u8; 0x0ef0], + #[doc = "0xf00 - MTB Integration Mode Control"] + pub itctrl: ITCTRL, + _reserved5: [u8; 0x9c], + #[doc = "0xfa0 - MTB Claim Set"] + pub claimset: CLAIMSET, + #[doc = "0xfa4 - MTB Claim Clear"] + pub claimclr: CLAIMCLR, + _reserved7: [u8; 0x08], + #[doc = "0xfb0 - MTB Lock Access"] + pub lockaccess: LOCKACCESS, + #[doc = "0xfb4 - MTB Lock Status"] + pub lockstatus: LOCKSTATUS, + #[doc = "0xfb8 - MTB Authentication Status"] + pub authstatus: AUTHSTATUS, + #[doc = "0xfbc - MTB Device Architecture"] + pub devarch: DEVARCH, + _reserved11: [u8; 0x08], + #[doc = "0xfc8 - MTB Device Configuration"] + pub devid: DEVID, + #[doc = "0xfcc - MTB Device Type"] + pub devtype: DEVTYPE, + #[doc = "0xfd0 - Peripheral Identification 4"] + pub pid4: PID4, + #[doc = "0xfd4 - Peripheral Identification 5"] + pub pid5: PID5, + #[doc = "0xfd8 - Peripheral Identification 6"] + pub pid6: PID6, + #[doc = "0xfdc - Peripheral Identification 7"] + pub pid7: PID7, + #[doc = "0xfe0 - Peripheral Identification 0"] + pub pid0: PID0, + #[doc = "0xfe4 - Peripheral Identification 1"] + pub pid1: PID1, + #[doc = "0xfe8 - Peripheral Identification 2"] + pub pid2: PID2, + #[doc = "0xfec - Peripheral Identification 3"] + pub pid3: PID3, + #[doc = "0xff0 - Component Identification 0"] + pub cid0: CID0, + #[doc = "0xff4 - Component Identification 1"] + pub cid1: CID1, + #[doc = "0xff8 - Component Identification 2"] + pub cid2: CID2, + #[doc = "0xffc - Component Identification 3"] + pub cid3: CID3, +} +#[doc = "POSITION (rw) register accessor: an alias for `Reg`"] +pub type POSITION = crate::Reg; +#[doc = "MTB Position"] +pub mod position; +#[doc = "MASTER (rw) register accessor: an alias for `Reg`"] +pub type MASTER = crate::Reg; +#[doc = "MTB Master"] +pub mod master; +#[doc = "FLOW (rw) register accessor: an alias for `Reg`"] +pub type FLOW = crate::Reg; +#[doc = "MTB Flow"] +pub mod flow; +#[doc = "BASE (r) register accessor: an alias for `Reg`"] +pub type BASE = crate::Reg; +#[doc = "MTB Base"] +pub mod base; +#[doc = "ITCTRL (rw) register accessor: an alias for `Reg`"] +pub type ITCTRL = crate::Reg; +#[doc = "MTB Integration Mode Control"] +pub mod itctrl; +#[doc = "CLAIMSET (rw) register accessor: an alias for `Reg`"] +pub type CLAIMSET = crate::Reg; +#[doc = "MTB Claim Set"] +pub mod claimset; +#[doc = "CLAIMCLR (rw) register accessor: an alias for `Reg`"] +pub type CLAIMCLR = crate::Reg; +#[doc = "MTB Claim Clear"] +pub mod claimclr; +#[doc = "LOCKACCESS (rw) register accessor: an alias for `Reg`"] +pub type LOCKACCESS = crate::Reg; +#[doc = "MTB Lock Access"] +pub mod lockaccess; +#[doc = "LOCKSTATUS (r) register accessor: an alias for `Reg`"] +pub type LOCKSTATUS = crate::Reg; +#[doc = "MTB Lock Status"] +pub mod lockstatus; +#[doc = "AUTHSTATUS (r) register accessor: an alias for `Reg`"] +pub type AUTHSTATUS = crate::Reg; +#[doc = "MTB Authentication Status"] +pub mod authstatus; +#[doc = "DEVARCH (r) register accessor: an alias for `Reg`"] +pub type DEVARCH = crate::Reg; +#[doc = "MTB Device Architecture"] +pub mod devarch; +#[doc = "DEVID (r) register accessor: an alias for `Reg`"] +pub type DEVID = crate::Reg; +#[doc = "MTB Device Configuration"] +pub mod devid; +#[doc = "DEVTYPE (r) register accessor: an alias for `Reg`"] +pub type DEVTYPE = crate::Reg; +#[doc = "MTB Device Type"] +pub mod devtype; +#[doc = "PID4 (r) register accessor: an alias for `Reg`"] +pub type PID4 = crate::Reg; +#[doc = "Peripheral Identification 4"] +pub mod pid4; +#[doc = "PID5 (r) register accessor: an alias for `Reg`"] +pub type PID5 = crate::Reg; +#[doc = "Peripheral Identification 5"] +pub mod pid5; +#[doc = "PID6 (r) register accessor: an alias for `Reg`"] +pub type PID6 = crate::Reg; +#[doc = "Peripheral Identification 6"] +pub mod pid6; +#[doc = "PID7 (r) register accessor: an alias for `Reg`"] +pub type PID7 = crate::Reg; +#[doc = "Peripheral Identification 7"] +pub mod pid7; +#[doc = "PID0 (r) register accessor: an alias for `Reg`"] +pub type PID0 = crate::Reg; +#[doc = "Peripheral Identification 0"] +pub mod pid0; +#[doc = "PID1 (r) register accessor: an alias for `Reg`"] +pub type PID1 = crate::Reg; +#[doc = "Peripheral Identification 1"] +pub mod pid1; +#[doc = "PID2 (r) register accessor: an alias for `Reg`"] +pub type PID2 = crate::Reg; +#[doc = "Peripheral Identification 2"] +pub mod pid2; +#[doc = "PID3 (r) register accessor: an alias for `Reg`"] +pub type PID3 = crate::Reg; +#[doc = "Peripheral Identification 3"] +pub mod pid3; +#[doc = "CID0 (r) register accessor: an alias for `Reg`"] +pub type CID0 = crate::Reg; +#[doc = "Component Identification 0"] +pub mod cid0; +#[doc = "CID1 (r) register accessor: an alias for `Reg`"] +pub type CID1 = crate::Reg; +#[doc = "Component Identification 1"] +pub mod cid1; +#[doc = "CID2 (r) register accessor: an alias for `Reg`"] +pub type CID2 = crate::Reg; +#[doc = "Component Identification 2"] +pub mod cid2; +#[doc = "CID3 (r) register accessor: an alias for `Reg`"] +pub type CID3 = crate::Reg; +#[doc = "Component Identification 3"] +pub mod cid3; diff --git a/pac/atsaml22j/src/mtb/authstatus.rs b/pac/atsaml22j/src/mtb/authstatus.rs new file mode 100644 index 000000000000..e9bdeb7b7ee6 --- /dev/null +++ b/pac/atsaml22j/src/mtb/authstatus.rs @@ -0,0 +1,28 @@ +#[doc = "Register `AUTHSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Authentication Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [authstatus](index.html) module"] +pub struct AUTHSTATUS_SPEC; +impl crate::RegisterSpec for AUTHSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [authstatus::R](R) reader structure"] +impl crate::Readable for AUTHSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets AUTHSTATUS to value 0"] +impl crate::Resettable for AUTHSTATUS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/mtb/base.rs b/pac/atsaml22j/src/mtb/base.rs new file mode 100644 index 000000000000..c42577ed91c6 --- /dev/null +++ b/pac/atsaml22j/src/mtb/base.rs @@ -0,0 +1,28 @@ +#[doc = "Register `BASE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Base\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [base](index.html) module"] +pub struct BASE_SPEC; +impl crate::RegisterSpec for BASE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [base::R](R) reader structure"] +impl crate::Readable for BASE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets BASE to value 0"] +impl crate::Resettable for BASE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/mtb/cid0.rs b/pac/atsaml22j/src/mtb/cid0.rs new file mode 100644 index 000000000000..03c20d41b155 --- /dev/null +++ b/pac/atsaml22j/src/mtb/cid0.rs @@ -0,0 +1,28 @@ +#[doc = "Register `CID0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Component Identification 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid0](index.html) module"] +pub struct CID0_SPEC; +impl crate::RegisterSpec for CID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid0::R](R) reader structure"] +impl crate::Readable for CID0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID0 to value 0"] +impl crate::Resettable for CID0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/mtb/cid1.rs b/pac/atsaml22j/src/mtb/cid1.rs new file mode 100644 index 000000000000..a41b055374dd --- /dev/null +++ b/pac/atsaml22j/src/mtb/cid1.rs @@ -0,0 +1,28 @@ +#[doc = "Register `CID1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Component Identification 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid1](index.html) module"] +pub struct CID1_SPEC; +impl crate::RegisterSpec for CID1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid1::R](R) reader structure"] +impl crate::Readable for CID1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID1 to value 0"] +impl crate::Resettable for CID1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/mtb/cid2.rs b/pac/atsaml22j/src/mtb/cid2.rs new file mode 100644 index 000000000000..437affa93bca --- /dev/null +++ b/pac/atsaml22j/src/mtb/cid2.rs @@ -0,0 +1,28 @@ +#[doc = "Register `CID2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Component Identification 2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid2](index.html) module"] +pub struct CID2_SPEC; +impl crate::RegisterSpec for CID2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid2::R](R) reader structure"] +impl crate::Readable for CID2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID2 to value 0"] +impl crate::Resettable for CID2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/mtb/cid3.rs b/pac/atsaml22j/src/mtb/cid3.rs new file mode 100644 index 000000000000..873cde02b91b --- /dev/null +++ b/pac/atsaml22j/src/mtb/cid3.rs @@ -0,0 +1,28 @@ +#[doc = "Register `CID3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Component Identification 3\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cid3](index.html) module"] +pub struct CID3_SPEC; +impl crate::RegisterSpec for CID3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cid3::R](R) reader structure"] +impl crate::Readable for CID3_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets CID3 to value 0"] +impl crate::Resettable for CID3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/mtb/claimclr.rs b/pac/atsaml22j/src/mtb/claimclr.rs new file mode 100644 index 000000000000..339db37787df --- /dev/null +++ b/pac/atsaml22j/src/mtb/claimclr.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CLAIMCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLAIMCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Claim Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [claimclr](index.html) module"] +pub struct CLAIMCLR_SPEC; +impl crate::RegisterSpec for CLAIMCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [claimclr::R](R) reader structure"] +impl crate::Readable for CLAIMCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [claimclr::W](W) writer structure"] +impl crate::Writable for CLAIMCLR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CLAIMCLR to value 0"] +impl crate::Resettable for CLAIMCLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/mtb/claimset.rs b/pac/atsaml22j/src/mtb/claimset.rs new file mode 100644 index 000000000000..b0dca357f260 --- /dev/null +++ b/pac/atsaml22j/src/mtb/claimset.rs @@ -0,0 +1,63 @@ +#[doc = "Register `CLAIMSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLAIMSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Claim Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [claimset](index.html) module"] +pub struct CLAIMSET_SPEC; +impl crate::RegisterSpec for CLAIMSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [claimset::R](R) reader structure"] +impl crate::Readable for CLAIMSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [claimset::W](W) writer structure"] +impl crate::Writable for CLAIMSET_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CLAIMSET to value 0"] +impl crate::Resettable for CLAIMSET_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/mtb/devarch.rs b/pac/atsaml22j/src/mtb/devarch.rs new file mode 100644 index 000000000000..2b6828cfc3ed --- /dev/null +++ b/pac/atsaml22j/src/mtb/devarch.rs @@ -0,0 +1,28 @@ +#[doc = "Register `DEVARCH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Device Architecture\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devarch](index.html) module"] +pub struct DEVARCH_SPEC; +impl crate::RegisterSpec for DEVARCH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [devarch::R](R) reader structure"] +impl crate::Readable for DEVARCH_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DEVARCH to value 0"] +impl crate::Resettable for DEVARCH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/mtb/devid.rs b/pac/atsaml22j/src/mtb/devid.rs new file mode 100644 index 000000000000..3aa1aca52f01 --- /dev/null +++ b/pac/atsaml22j/src/mtb/devid.rs @@ -0,0 +1,28 @@ +#[doc = "Register `DEVID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Device Configuration\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devid](index.html) module"] +pub struct DEVID_SPEC; +impl crate::RegisterSpec for DEVID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [devid::R](R) reader structure"] +impl crate::Readable for DEVID_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DEVID to value 0"] +impl crate::Resettable for DEVID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/mtb/devtype.rs b/pac/atsaml22j/src/mtb/devtype.rs new file mode 100644 index 000000000000..5f08a5316fe9 --- /dev/null +++ b/pac/atsaml22j/src/mtb/devtype.rs @@ -0,0 +1,28 @@ +#[doc = "Register `DEVTYPE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Device Type\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devtype](index.html) module"] +pub struct DEVTYPE_SPEC; +impl crate::RegisterSpec for DEVTYPE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [devtype::R](R) reader structure"] +impl crate::Readable for DEVTYPE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DEVTYPE to value 0"] +impl crate::Resettable for DEVTYPE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/mtb/flow.rs b/pac/atsaml22j/src/mtb/flow.rs new file mode 100644 index 000000000000..5a05e2be915e --- /dev/null +++ b/pac/atsaml22j/src/mtb/flow.rs @@ -0,0 +1,110 @@ +#[doc = "Register `FLOW` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FLOW` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `AUTOSTOP` reader - Auto Stop Tracing"] +pub type AUTOSTOP_R = crate::BitReader; +#[doc = "Field `AUTOSTOP` writer - Auto Stop Tracing"] +pub type AUTOSTOP_W<'a, const O: u8> = crate::BitWriter<'a, u32, FLOW_SPEC, bool, O>; +#[doc = "Field `AUTOHALT` reader - Auto Halt Request"] +pub type AUTOHALT_R = crate::BitReader; +#[doc = "Field `AUTOHALT` writer - Auto Halt Request"] +pub type AUTOHALT_W<'a, const O: u8> = crate::BitWriter<'a, u32, FLOW_SPEC, bool, O>; +#[doc = "Field `WATERMARK` reader - Watermark value"] +pub type WATERMARK_R = crate::FieldReader; +#[doc = "Field `WATERMARK` writer - Watermark value"] +pub type WATERMARK_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FLOW_SPEC, u32, u32, 29, O>; +impl R { + #[doc = "Bit 0 - Auto Stop Tracing"] + #[inline(always)] + pub fn autostop(&self) -> AUTOSTOP_R { + AUTOSTOP_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Auto Halt Request"] + #[inline(always)] + pub fn autohalt(&self) -> AUTOHALT_R { + AUTOHALT_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 3:31 - Watermark value"] + #[inline(always)] + pub fn watermark(&self) -> WATERMARK_R { + WATERMARK_R::new((self.bits >> 3) & 0x1fff_ffff) + } +} +impl W { + #[doc = "Bit 0 - Auto Stop Tracing"] + #[inline(always)] + #[must_use] + pub fn autostop(&mut self) -> AUTOSTOP_W<0> { + AUTOSTOP_W::new(self) + } + #[doc = "Bit 1 - Auto Halt Request"] + #[inline(always)] + #[must_use] + pub fn autohalt(&mut self) -> AUTOHALT_W<1> { + AUTOHALT_W::new(self) + } + #[doc = "Bits 3:31 - Watermark value"] + #[inline(always)] + #[must_use] + pub fn watermark(&mut self) -> WATERMARK_W<3> { + WATERMARK_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Flow\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [flow](index.html) module"] +pub struct FLOW_SPEC; +impl crate::RegisterSpec for FLOW_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [flow::R](R) reader structure"] +impl crate::Readable for FLOW_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [flow::W](W) writer structure"] +impl crate::Writable for FLOW_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FLOW to value 0"] +impl crate::Resettable for FLOW_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/mtb/itctrl.rs b/pac/atsaml22j/src/mtb/itctrl.rs new file mode 100644 index 000000000000..66d161c30e33 --- /dev/null +++ b/pac/atsaml22j/src/mtb/itctrl.rs @@ -0,0 +1,63 @@ +#[doc = "Register `ITCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ITCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Integration Mode Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [itctrl](index.html) module"] +pub struct ITCTRL_SPEC; +impl crate::RegisterSpec for ITCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [itctrl::R](R) reader structure"] +impl crate::Readable for ITCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [itctrl::W](W) writer structure"] +impl crate::Writable for ITCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ITCTRL to value 0"] +impl crate::Resettable for ITCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/mtb/lockaccess.rs b/pac/atsaml22j/src/mtb/lockaccess.rs new file mode 100644 index 000000000000..d6a0c6d56aba --- /dev/null +++ b/pac/atsaml22j/src/mtb/lockaccess.rs @@ -0,0 +1,63 @@ +#[doc = "Register `LOCKACCESS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LOCKACCESS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Lock Access\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lockaccess](index.html) module"] +pub struct LOCKACCESS_SPEC; +impl crate::RegisterSpec for LOCKACCESS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [lockaccess::R](R) reader structure"] +impl crate::Readable for LOCKACCESS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [lockaccess::W](W) writer structure"] +impl crate::Writable for LOCKACCESS_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LOCKACCESS to value 0"] +impl crate::Resettable for LOCKACCESS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/mtb/lockstatus.rs b/pac/atsaml22j/src/mtb/lockstatus.rs new file mode 100644 index 000000000000..e7d9c2fbf9ad --- /dev/null +++ b/pac/atsaml22j/src/mtb/lockstatus.rs @@ -0,0 +1,28 @@ +#[doc = "Register `LOCKSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "MTB Lock Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lockstatus](index.html) module"] +pub struct LOCKSTATUS_SPEC; +impl crate::RegisterSpec for LOCKSTATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [lockstatus::R](R) reader structure"] +impl crate::Readable for LOCKSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets LOCKSTATUS to value 0"] +impl crate::Resettable for LOCKSTATUS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/mtb/master.rs b/pac/atsaml22j/src/mtb/master.rs new file mode 100644 index 000000000000..8876b1707e3e --- /dev/null +++ b/pac/atsaml22j/src/mtb/master.rs @@ -0,0 +1,170 @@ +#[doc = "Register `MASTER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MASTER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MASK` reader - Maximum Value of the Trace Buffer in SRAM"] +pub type MASK_R = crate::FieldReader; +#[doc = "Field `MASK` writer - Maximum Value of the Trace Buffer in SRAM"] +pub type MASK_W<'a, const O: u8> = crate::FieldWriter<'a, u32, MASTER_SPEC, u8, u8, 5, O>; +#[doc = "Field `TSTARTEN` reader - Trace Start Input Enable"] +pub type TSTARTEN_R = crate::BitReader; +#[doc = "Field `TSTARTEN` writer - Trace Start Input Enable"] +pub type TSTARTEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, MASTER_SPEC, bool, O>; +#[doc = "Field `TSTOPEN` reader - Trace Stop Input Enable"] +pub type TSTOPEN_R = crate::BitReader; +#[doc = "Field `TSTOPEN` writer - Trace Stop Input Enable"] +pub type TSTOPEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, MASTER_SPEC, bool, O>; +#[doc = "Field `SFRWPRIV` reader - Special Function Register Write Privilege"] +pub type SFRWPRIV_R = crate::BitReader; +#[doc = "Field `SFRWPRIV` writer - Special Function Register Write Privilege"] +pub type SFRWPRIV_W<'a, const O: u8> = crate::BitWriter<'a, u32, MASTER_SPEC, bool, O>; +#[doc = "Field `RAMPRIV` reader - SRAM Privilege"] +pub type RAMPRIV_R = crate::BitReader; +#[doc = "Field `RAMPRIV` writer - SRAM Privilege"] +pub type RAMPRIV_W<'a, const O: u8> = crate::BitWriter<'a, u32, MASTER_SPEC, bool, O>; +#[doc = "Field `HALTREQ` reader - Halt Request"] +pub type HALTREQ_R = crate::BitReader; +#[doc = "Field `HALTREQ` writer - Halt Request"] +pub type HALTREQ_W<'a, const O: u8> = crate::BitWriter<'a, u32, MASTER_SPEC, bool, O>; +#[doc = "Field `EN` reader - Main Trace Enable"] +pub type EN_R = crate::BitReader; +#[doc = "Field `EN` writer - Main Trace Enable"] +pub type EN_W<'a, const O: u8> = crate::BitWriter<'a, u32, MASTER_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:4 - Maximum Value of the Trace Buffer in SRAM"] + #[inline(always)] + pub fn mask(&self) -> MASK_R { + MASK_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bit 5 - Trace Start Input Enable"] + #[inline(always)] + pub fn tstarten(&self) -> TSTARTEN_R { + TSTARTEN_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Trace Stop Input Enable"] + #[inline(always)] + pub fn tstopen(&self) -> TSTOPEN_R { + TSTOPEN_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Special Function Register Write Privilege"] + #[inline(always)] + pub fn sfrwpriv(&self) -> SFRWPRIV_R { + SFRWPRIV_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - SRAM Privilege"] + #[inline(always)] + pub fn rampriv(&self) -> RAMPRIV_R { + RAMPRIV_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Halt Request"] + #[inline(always)] + pub fn haltreq(&self) -> HALTREQ_R { + HALTREQ_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 31 - Main Trace Enable"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Maximum Value of the Trace Buffer in SRAM"] + #[inline(always)] + #[must_use] + pub fn mask(&mut self) -> MASK_W<0> { + MASK_W::new(self) + } + #[doc = "Bit 5 - Trace Start Input Enable"] + #[inline(always)] + #[must_use] + pub fn tstarten(&mut self) -> TSTARTEN_W<5> { + TSTARTEN_W::new(self) + } + #[doc = "Bit 6 - Trace Stop Input Enable"] + #[inline(always)] + #[must_use] + pub fn tstopen(&mut self) -> TSTOPEN_W<6> { + TSTOPEN_W::new(self) + } + #[doc = "Bit 7 - Special Function Register Write Privilege"] + #[inline(always)] + #[must_use] + pub fn sfrwpriv(&mut self) -> SFRWPRIV_W<7> { + SFRWPRIV_W::new(self) + } + #[doc = "Bit 8 - SRAM Privilege"] + #[inline(always)] + #[must_use] + pub fn rampriv(&mut self) -> RAMPRIV_W<8> { + RAMPRIV_W::new(self) + } + #[doc = "Bit 9 - Halt Request"] + #[inline(always)] + #[must_use] + pub fn haltreq(&mut self) -> HALTREQ_W<9> { + HALTREQ_W::new(self) + } + #[doc = "Bit 31 - Main Trace Enable"] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W<31> { + EN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Master\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [master](index.html) module"] +pub struct MASTER_SPEC; +impl crate::RegisterSpec for MASTER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [master::R](R) reader structure"] +impl crate::Readable for MASTER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [master::W](W) writer structure"] +impl crate::Writable for MASTER_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets MASTER to value 0"] +impl crate::Resettable for MASTER_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/mtb/pid0.rs b/pac/atsaml22j/src/mtb/pid0.rs new file mode 100644 index 000000000000..44e3b6a9b6bc --- /dev/null +++ b/pac/atsaml22j/src/mtb/pid0.rs @@ -0,0 +1,28 @@ +#[doc = "Register `PID0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 0\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid0](index.html) module"] +pub struct PID0_SPEC; +impl crate::RegisterSpec for PID0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid0::R](R) reader structure"] +impl crate::Readable for PID0_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID0 to value 0"] +impl crate::Resettable for PID0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/mtb/pid1.rs b/pac/atsaml22j/src/mtb/pid1.rs new file mode 100644 index 000000000000..3de009ce7dcf --- /dev/null +++ b/pac/atsaml22j/src/mtb/pid1.rs @@ -0,0 +1,28 @@ +#[doc = "Register `PID1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 1\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid1](index.html) module"] +pub struct PID1_SPEC; +impl crate::RegisterSpec for PID1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid1::R](R) reader structure"] +impl crate::Readable for PID1_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID1 to value 0"] +impl crate::Resettable for PID1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/mtb/pid2.rs b/pac/atsaml22j/src/mtb/pid2.rs new file mode 100644 index 000000000000..801b24f4bbf4 --- /dev/null +++ b/pac/atsaml22j/src/mtb/pid2.rs @@ -0,0 +1,28 @@ +#[doc = "Register `PID2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 2\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid2](index.html) module"] +pub struct PID2_SPEC; +impl crate::RegisterSpec for PID2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid2::R](R) reader structure"] +impl crate::Readable for PID2_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID2 to value 0"] +impl crate::Resettable for PID2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/mtb/pid3.rs b/pac/atsaml22j/src/mtb/pid3.rs new file mode 100644 index 000000000000..b7bb525d6a6c --- /dev/null +++ b/pac/atsaml22j/src/mtb/pid3.rs @@ -0,0 +1,28 @@ +#[doc = "Register `PID3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 3\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid3](index.html) module"] +pub struct PID3_SPEC; +impl crate::RegisterSpec for PID3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid3::R](R) reader structure"] +impl crate::Readable for PID3_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID3 to value 0"] +impl crate::Resettable for PID3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/mtb/pid4.rs b/pac/atsaml22j/src/mtb/pid4.rs new file mode 100644 index 000000000000..316f5acdac85 --- /dev/null +++ b/pac/atsaml22j/src/mtb/pid4.rs @@ -0,0 +1,28 @@ +#[doc = "Register `PID4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 4\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid4](index.html) module"] +pub struct PID4_SPEC; +impl crate::RegisterSpec for PID4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid4::R](R) reader structure"] +impl crate::Readable for PID4_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID4 to value 0"] +impl crate::Resettable for PID4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/mtb/pid5.rs b/pac/atsaml22j/src/mtb/pid5.rs new file mode 100644 index 000000000000..51f0a3b6a532 --- /dev/null +++ b/pac/atsaml22j/src/mtb/pid5.rs @@ -0,0 +1,28 @@ +#[doc = "Register `PID5` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 5\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid5](index.html) module"] +pub struct PID5_SPEC; +impl crate::RegisterSpec for PID5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid5::R](R) reader structure"] +impl crate::Readable for PID5_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID5 to value 0"] +impl crate::Resettable for PID5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/mtb/pid6.rs b/pac/atsaml22j/src/mtb/pid6.rs new file mode 100644 index 000000000000..38aa7a8515f8 --- /dev/null +++ b/pac/atsaml22j/src/mtb/pid6.rs @@ -0,0 +1,28 @@ +#[doc = "Register `PID6` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 6\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid6](index.html) module"] +pub struct PID6_SPEC; +impl crate::RegisterSpec for PID6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid6::R](R) reader structure"] +impl crate::Readable for PID6_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID6 to value 0"] +impl crate::Resettable for PID6_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/mtb/pid7.rs b/pac/atsaml22j/src/mtb/pid7.rs new file mode 100644 index 000000000000..fc0161b33656 --- /dev/null +++ b/pac/atsaml22j/src/mtb/pid7.rs @@ -0,0 +1,28 @@ +#[doc = "Register `PID7` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Peripheral Identification 7\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pid7](index.html) module"] +pub struct PID7_SPEC; +impl crate::RegisterSpec for PID7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [pid7::R](R) reader structure"] +impl crate::Readable for PID7_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets PID7 to value 0"] +impl crate::Resettable for PID7_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/mtb/position.rs b/pac/atsaml22j/src/mtb/position.rs new file mode 100644 index 000000000000..412fd955b6b3 --- /dev/null +++ b/pac/atsaml22j/src/mtb/position.rs @@ -0,0 +1,95 @@ +#[doc = "Register `POSITION` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `POSITION` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WRAP` reader - Pointer Value Wraps"] +pub type WRAP_R = crate::BitReader; +#[doc = "Field `WRAP` writer - Pointer Value Wraps"] +pub type WRAP_W<'a, const O: u8> = crate::BitWriter<'a, u32, POSITION_SPEC, bool, O>; +#[doc = "Field `POINTER` reader - Trace Packet Location Pointer"] +pub type POINTER_R = crate::FieldReader; +#[doc = "Field `POINTER` writer - Trace Packet Location Pointer"] +pub type POINTER_W<'a, const O: u8> = crate::FieldWriter<'a, u32, POSITION_SPEC, u32, u32, 29, O>; +impl R { + #[doc = "Bit 2 - Pointer Value Wraps"] + #[inline(always)] + pub fn wrap(&self) -> WRAP_R { + WRAP_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 3:31 - Trace Packet Location Pointer"] + #[inline(always)] + pub fn pointer(&self) -> POINTER_R { + POINTER_R::new((self.bits >> 3) & 0x1fff_ffff) + } +} +impl W { + #[doc = "Bit 2 - Pointer Value Wraps"] + #[inline(always)] + #[must_use] + pub fn wrap(&mut self) -> WRAP_W<2> { + WRAP_W::new(self) + } + #[doc = "Bits 3:31 - Trace Packet Location Pointer"] + #[inline(always)] + #[must_use] + pub fn pointer(&mut self) -> POINTER_W<3> { + POINTER_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MTB Position\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [position](index.html) module"] +pub struct POSITION_SPEC; +impl crate::RegisterSpec for POSITION_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [position::R](R) reader structure"] +impl crate::Readable for POSITION_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [position::W](W) writer structure"] +impl crate::Writable for POSITION_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets POSITION to value 0"] +impl crate::Resettable for POSITION_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/nvmctrl.rs b/pac/atsaml22j/src/nvmctrl.rs new file mode 100644 index 000000000000..140e56fc59df --- /dev/null +++ b/pac/atsaml22j/src/nvmctrl.rs @@ -0,0 +1,63 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: CTRLA, + _reserved1: [u8; 0x02], + #[doc = "0x04 - Control B"] + pub ctrlb: CTRLB, + #[doc = "0x08 - NVM Parameter"] + pub param: PARAM, + #[doc = "0x0c - Interrupt Enable Clear"] + pub intenclr: INTENCLR, + _reserved4: [u8; 0x03], + #[doc = "0x10 - Interrupt Enable Set"] + pub intenset: INTENSET, + _reserved5: [u8; 0x03], + #[doc = "0x14 - Interrupt Flag Status and Clear"] + pub intflag: INTFLAG, + _reserved6: [u8; 0x03], + #[doc = "0x18 - Status"] + pub status: STATUS, + _reserved7: [u8; 0x02], + #[doc = "0x1c - Address"] + pub addr: ADDR, + #[doc = "0x20 - Lock Section"] + pub lock: LOCK, +} +#[doc = "CTRLA (rw) register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLB (rw) register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B"] +pub mod ctrlb; +#[doc = "PARAM (rw) register accessor: an alias for `Reg`"] +pub type PARAM = crate::Reg; +#[doc = "NVM Parameter"] +pub mod param; +#[doc = "INTENCLR (rw) register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET (rw) register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG (rw) register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS (rw) register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "ADDR (rw) register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "Address"] +pub mod addr; +#[doc = "LOCK (rw) register accessor: an alias for `Reg`"] +pub type LOCK = crate::Reg; +#[doc = "Lock Section"] +pub mod lock; diff --git a/pac/atsaml22j/src/nvmctrl/addr.rs b/pac/atsaml22j/src/nvmctrl/addr.rs new file mode 100644 index 000000000000..42ee48f3ad6b --- /dev/null +++ b/pac/atsaml22j/src/nvmctrl/addr.rs @@ -0,0 +1,80 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - NVM Address"] +pub type ADDR_R = crate::FieldReader; +#[doc = "Field `ADDR` writer - NVM Address"] +pub type ADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ADDR_SPEC, u32, u32, 22, O>; +impl R { + #[doc = "Bits 0:21 - NVM Address"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new(self.bits & 0x003f_ffff) + } +} +impl W { + #[doc = "Bits 0:21 - NVM Address"] + #[inline(always)] + #[must_use] + pub fn addr(&mut self) -> ADDR_W<0> { + ADDR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/nvmctrl/ctrla.rs b/pac/atsaml22j/src/nvmctrl/ctrla.rs new file mode 100644 index 000000000000..bac02923fe57 --- /dev/null +++ b/pac/atsaml22j/src/nvmctrl/ctrla.rs @@ -0,0 +1,348 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CMD` reader - Command"] +pub type CMD_R = crate::FieldReader; +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum CMDSELECT_A { + #[doc = "2: Erase Row - Erases the row addressed by the ADDR register."] + ER = 2, + #[doc = "4: Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register."] + WP = 4, + #[doc = "5: Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row."] + EAR = 5, + #[doc = "6: Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row."] + WAP = 6, + #[doc = "10: Security Flow Command"] + SF = 10, + #[doc = "15: Write lockbits"] + WL = 15, + #[doc = "26: RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register."] + RWWEEER = 26, + #[doc = "28: RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register."] + RWWEEWP = 28, + #[doc = "64: Lock Region - Locks the region containing the address location in the ADDR register."] + LR = 64, + #[doc = "65: Unlock Region - Unlocks the region containing the address location in the ADDR register."] + UR = 65, + #[doc = "66: Sets the power reduction mode."] + SPRM = 66, + #[doc = "67: Clears the power reduction mode."] + CPRM = 67, + #[doc = "68: Page Buffer Clear - Clears the page buffer."] + PBC = 68, + #[doc = "69: Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row."] + SSB = 69, + #[doc = "70: Invalidate all cache lines."] + INVALL = 70, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMDSELECT_A) -> Self { + variant as _ + } +} +impl CMD_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 2 => Some(CMDSELECT_A::ER), + 4 => Some(CMDSELECT_A::WP), + 5 => Some(CMDSELECT_A::EAR), + 6 => Some(CMDSELECT_A::WAP), + 10 => Some(CMDSELECT_A::SF), + 15 => Some(CMDSELECT_A::WL), + 26 => Some(CMDSELECT_A::RWWEEER), + 28 => Some(CMDSELECT_A::RWWEEWP), + 64 => Some(CMDSELECT_A::LR), + 65 => Some(CMDSELECT_A::UR), + 66 => Some(CMDSELECT_A::SPRM), + 67 => Some(CMDSELECT_A::CPRM), + 68 => Some(CMDSELECT_A::PBC), + 69 => Some(CMDSELECT_A::SSB), + 70 => Some(CMDSELECT_A::INVALL), + _ => None, + } + } + #[doc = "Checks if the value of the field is `ER`"] + #[inline(always)] + pub fn is_er(&self) -> bool { + *self == CMDSELECT_A::ER + } + #[doc = "Checks if the value of the field is `WP`"] + #[inline(always)] + pub fn is_wp(&self) -> bool { + *self == CMDSELECT_A::WP + } + #[doc = "Checks if the value of the field is `EAR`"] + #[inline(always)] + pub fn is_ear(&self) -> bool { + *self == CMDSELECT_A::EAR + } + #[doc = "Checks if the value of the field is `WAP`"] + #[inline(always)] + pub fn is_wap(&self) -> bool { + *self == CMDSELECT_A::WAP + } + #[doc = "Checks if the value of the field is `SF`"] + #[inline(always)] + pub fn is_sf(&self) -> bool { + *self == CMDSELECT_A::SF + } + #[doc = "Checks if the value of the field is `WL`"] + #[inline(always)] + pub fn is_wl(&self) -> bool { + *self == CMDSELECT_A::WL + } + #[doc = "Checks if the value of the field is `RWWEEER`"] + #[inline(always)] + pub fn is_rwweeer(&self) -> bool { + *self == CMDSELECT_A::RWWEEER + } + #[doc = "Checks if the value of the field is `RWWEEWP`"] + #[inline(always)] + pub fn is_rwweewp(&self) -> bool { + *self == CMDSELECT_A::RWWEEWP + } + #[doc = "Checks if the value of the field is `LR`"] + #[inline(always)] + pub fn is_lr(&self) -> bool { + *self == CMDSELECT_A::LR + } + #[doc = "Checks if the value of the field is `UR`"] + #[inline(always)] + pub fn is_ur(&self) -> bool { + *self == CMDSELECT_A::UR + } + #[doc = "Checks if the value of the field is `SPRM`"] + #[inline(always)] + pub fn is_sprm(&self) -> bool { + *self == CMDSELECT_A::SPRM + } + #[doc = "Checks if the value of the field is `CPRM`"] + #[inline(always)] + pub fn is_cprm(&self) -> bool { + *self == CMDSELECT_A::CPRM + } + #[doc = "Checks if the value of the field is `PBC`"] + #[inline(always)] + pub fn is_pbc(&self) -> bool { + *self == CMDSELECT_A::PBC + } + #[doc = "Checks if the value of the field is `SSB`"] + #[inline(always)] + pub fn is_ssb(&self) -> bool { + *self == CMDSELECT_A::SSB + } + #[doc = "Checks if the value of the field is `INVALL`"] + #[inline(always)] + pub fn is_invall(&self) -> bool { + *self == CMDSELECT_A::INVALL + } +} +#[doc = "Field `CMD` writer - Command"] +pub type CMD_W<'a, const O: u8> = crate::FieldWriter<'a, u16, CTRLA_SPEC, u8, CMDSELECT_A, 7, O>; +impl<'a, const O: u8> CMD_W<'a, O> { + #[doc = "Erase Row - Erases the row addressed by the ADDR register."] + #[inline(always)] + pub fn er(self) -> &'a mut W { + self.variant(CMDSELECT_A::ER) + } + #[doc = "Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register."] + #[inline(always)] + pub fn wp(self) -> &'a mut W { + self.variant(CMDSELECT_A::WP) + } + #[doc = "Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row."] + #[inline(always)] + pub fn ear(self) -> &'a mut W { + self.variant(CMDSELECT_A::EAR) + } + #[doc = "Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row."] + #[inline(always)] + pub fn wap(self) -> &'a mut W { + self.variant(CMDSELECT_A::WAP) + } + #[doc = "Security Flow Command"] + #[inline(always)] + pub fn sf(self) -> &'a mut W { + self.variant(CMDSELECT_A::SF) + } + #[doc = "Write lockbits"] + #[inline(always)] + pub fn wl(self) -> &'a mut W { + self.variant(CMDSELECT_A::WL) + } + #[doc = "RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register."] + #[inline(always)] + pub fn rwweeer(self) -> &'a mut W { + self.variant(CMDSELECT_A::RWWEEER) + } + #[doc = "RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register."] + #[inline(always)] + pub fn rwweewp(self) -> &'a mut W { + self.variant(CMDSELECT_A::RWWEEWP) + } + #[doc = "Lock Region - Locks the region containing the address location in the ADDR register."] + #[inline(always)] + pub fn lr(self) -> &'a mut W { + self.variant(CMDSELECT_A::LR) + } + #[doc = "Unlock Region - Unlocks the region containing the address location in the ADDR register."] + #[inline(always)] + pub fn ur(self) -> &'a mut W { + self.variant(CMDSELECT_A::UR) + } + #[doc = "Sets the power reduction mode."] + #[inline(always)] + pub fn sprm(self) -> &'a mut W { + self.variant(CMDSELECT_A::SPRM) + } + #[doc = "Clears the power reduction mode."] + #[inline(always)] + pub fn cprm(self) -> &'a mut W { + self.variant(CMDSELECT_A::CPRM) + } + #[doc = "Page Buffer Clear - Clears the page buffer."] + #[inline(always)] + pub fn pbc(self) -> &'a mut W { + self.variant(CMDSELECT_A::PBC) + } + #[doc = "Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row."] + #[inline(always)] + pub fn ssb(self) -> &'a mut W { + self.variant(CMDSELECT_A::SSB) + } + #[doc = "Invalidate all cache lines."] + #[inline(always)] + pub fn invall(self) -> &'a mut W { + self.variant(CMDSELECT_A::INVALL) + } +} +#[doc = "Field `CMDEX` reader - Command Execution"] +pub type CMDEX_R = crate::FieldReader; +#[doc = "Command Execution\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum CMDEXSELECT_A { + #[doc = "165: Execution Key"] + KEY = 165, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMDEXSELECT_A) -> Self { + variant as _ + } +} +impl CMDEX_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 165 => Some(CMDEXSELECT_A::KEY), + _ => None, + } + } + #[doc = "Checks if the value of the field is `KEY`"] + #[inline(always)] + pub fn is_key(&self) -> bool { + *self == CMDEXSELECT_A::KEY + } +} +#[doc = "Field `CMDEX` writer - Command Execution"] +pub type CMDEX_W<'a, const O: u8> = + crate::FieldWriter<'a, u16, CTRLA_SPEC, u8, CMDEXSELECT_A, 8, O>; +impl<'a, const O: u8> CMDEX_W<'a, O> { + #[doc = "Execution Key"] + #[inline(always)] + pub fn key(self) -> &'a mut W { + self.variant(CMDEXSELECT_A::KEY) + } +} +impl R { + #[doc = "Bits 0:6 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new((self.bits & 0x7f) as u8) + } + #[doc = "Bits 8:15 - Command Execution"] + #[inline(always)] + pub fn cmdex(&self) -> CMDEX_R { + CMDEX_R::new(((self.bits >> 8) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:6 - Command"] + #[inline(always)] + #[must_use] + pub fn cmd(&mut self) -> CMD_W<0> { + CMD_W::new(self) + } + #[doc = "Bits 8:15 - Command Execution"] + #[inline(always)] + #[must_use] + pub fn cmdex(&mut self) -> CMDEX_W<8> { + CMDEX_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/nvmctrl/ctrlb.rs b/pac/atsaml22j/src/nvmctrl/ctrlb.rs new file mode 100644 index 000000000000..ce80b78912ec --- /dev/null +++ b/pac/atsaml22j/src/nvmctrl/ctrlb.rs @@ -0,0 +1,340 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RWS` reader - NVM Read Wait States"] +pub type RWS_R = crate::FieldReader; +#[doc = "NVM Read Wait States\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum RWSSELECT_A { + #[doc = "0: Single Auto Wait State"] + SINGLE = 0, + #[doc = "1: Half Auto Wait State"] + HALF = 1, + #[doc = "2: Dual Auto Wait State"] + DUAL = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RWSSELECT_A) -> Self { + variant as _ + } +} +impl RWS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(RWSSELECT_A::SINGLE), + 1 => Some(RWSSELECT_A::HALF), + 2 => Some(RWSSELECT_A::DUAL), + _ => None, + } + } + #[doc = "Checks if the value of the field is `SINGLE`"] + #[inline(always)] + pub fn is_single(&self) -> bool { + *self == RWSSELECT_A::SINGLE + } + #[doc = "Checks if the value of the field is `HALF`"] + #[inline(always)] + pub fn is_half(&self) -> bool { + *self == RWSSELECT_A::HALF + } + #[doc = "Checks if the value of the field is `DUAL`"] + #[inline(always)] + pub fn is_dual(&self) -> bool { + *self == RWSSELECT_A::DUAL + } +} +#[doc = "Field `RWS` writer - NVM Read Wait States"] +pub type RWS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRLB_SPEC, u8, RWSSELECT_A, 4, O>; +impl<'a, const O: u8> RWS_W<'a, O> { + #[doc = "Single Auto Wait State"] + #[inline(always)] + pub fn single(self) -> &'a mut W { + self.variant(RWSSELECT_A::SINGLE) + } + #[doc = "Half Auto Wait State"] + #[inline(always)] + pub fn half(self) -> &'a mut W { + self.variant(RWSSELECT_A::HALF) + } + #[doc = "Dual Auto Wait State"] + #[inline(always)] + pub fn dual(self) -> &'a mut W { + self.variant(RWSSELECT_A::DUAL) + } +} +#[doc = "Field `MANW` reader - Manual Write"] +pub type MANW_R = crate::BitReader; +#[doc = "Field `MANW` writer - Manual Write"] +pub type MANW_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLB_SPEC, bool, O>; +#[doc = "Field `SLEEPPRM` reader - Power Reduction Mode during Sleep"] +pub type SLEEPPRM_R = crate::FieldReader; +#[doc = "Power Reduction Mode during Sleep\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SLEEPPRMSELECT_A { + #[doc = "0: NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access."] + WAKEONACCESS = 0, + #[doc = "1: NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep."] + WAKEUPINSTANT = 1, + #[doc = "3: Auto power reduction disabled."] + DISABLED = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SLEEPPRMSELECT_A) -> Self { + variant as _ + } +} +impl SLEEPPRM_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SLEEPPRMSELECT_A::WAKEONACCESS), + 1 => Some(SLEEPPRMSELECT_A::WAKEUPINSTANT), + 3 => Some(SLEEPPRMSELECT_A::DISABLED), + _ => None, + } + } + #[doc = "Checks if the value of the field is `WAKEONACCESS`"] + #[inline(always)] + pub fn is_wakeonaccess(&self) -> bool { + *self == SLEEPPRMSELECT_A::WAKEONACCESS + } + #[doc = "Checks if the value of the field is `WAKEUPINSTANT`"] + #[inline(always)] + pub fn is_wakeupinstant(&self) -> bool { + *self == SLEEPPRMSELECT_A::WAKEUPINSTANT + } + #[doc = "Checks if the value of the field is `DISABLED`"] + #[inline(always)] + pub fn is_disabled(&self) -> bool { + *self == SLEEPPRMSELECT_A::DISABLED + } +} +#[doc = "Field `SLEEPPRM` writer - Power Reduction Mode during Sleep"] +pub type SLEEPPRM_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, CTRLB_SPEC, u8, SLEEPPRMSELECT_A, 2, O>; +impl<'a, const O: u8> SLEEPPRM_W<'a, O> { + #[doc = "NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access."] + #[inline(always)] + pub fn wakeonaccess(self) -> &'a mut W { + self.variant(SLEEPPRMSELECT_A::WAKEONACCESS) + } + #[doc = "NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep."] + #[inline(always)] + pub fn wakeupinstant(self) -> &'a mut W { + self.variant(SLEEPPRMSELECT_A::WAKEUPINSTANT) + } + #[doc = "Auto power reduction disabled."] + #[inline(always)] + pub fn disabled(self) -> &'a mut W { + self.variant(SLEEPPRMSELECT_A::DISABLED) + } +} +#[doc = "Field `FWUP` reader - fast wake-up"] +pub type FWUP_R = crate::BitReader; +#[doc = "Field `FWUP` writer - fast wake-up"] +pub type FWUP_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLB_SPEC, bool, O>; +#[doc = "Field `READMODE` reader - NVMCTRL Read Mode"] +pub type READMODE_R = crate::FieldReader; +#[doc = "NVMCTRL Read Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum READMODESELECT_A { + #[doc = "0: The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance."] + NO_MISS_PENALTY = 0, + #[doc = "1: Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time."] + LOW_POWER = 1, + #[doc = "2: The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings."] + DETERMINISTIC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: READMODESELECT_A) -> Self { + variant as _ + } +} +impl READMODE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(READMODESELECT_A::NO_MISS_PENALTY), + 1 => Some(READMODESELECT_A::LOW_POWER), + 2 => Some(READMODESELECT_A::DETERMINISTIC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NO_MISS_PENALTY`"] + #[inline(always)] + pub fn is_no_miss_penalty(&self) -> bool { + *self == READMODESELECT_A::NO_MISS_PENALTY + } + #[doc = "Checks if the value of the field is `LOW_POWER`"] + #[inline(always)] + pub fn is_low_power(&self) -> bool { + *self == READMODESELECT_A::LOW_POWER + } + #[doc = "Checks if the value of the field is `DETERMINISTIC`"] + #[inline(always)] + pub fn is_deterministic(&self) -> bool { + *self == READMODESELECT_A::DETERMINISTIC + } +} +#[doc = "Field `READMODE` writer - NVMCTRL Read Mode"] +pub type READMODE_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, CTRLB_SPEC, u8, READMODESELECT_A, 2, O>; +impl<'a, const O: u8> READMODE_W<'a, O> { + #[doc = "The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance."] + #[inline(always)] + pub fn no_miss_penalty(self) -> &'a mut W { + self.variant(READMODESELECT_A::NO_MISS_PENALTY) + } + #[doc = "Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time."] + #[inline(always)] + pub fn low_power(self) -> &'a mut W { + self.variant(READMODESELECT_A::LOW_POWER) + } + #[doc = "The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings."] + #[inline(always)] + pub fn deterministic(self) -> &'a mut W { + self.variant(READMODESELECT_A::DETERMINISTIC) + } +} +#[doc = "Field `CACHEDIS` reader - Cache Disable"] +pub type CACHEDIS_R = crate::BitReader; +#[doc = "Field `CACHEDIS` writer - Cache Disable"] +pub type CACHEDIS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLB_SPEC, bool, O>; +impl R { + #[doc = "Bits 1:4 - NVM Read Wait States"] + #[inline(always)] + pub fn rws(&self) -> RWS_R { + RWS_R::new(((self.bits >> 1) & 0x0f) as u8) + } + #[doc = "Bit 7 - Manual Write"] + #[inline(always)] + pub fn manw(&self) -> MANW_R { + MANW_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:9 - Power Reduction Mode during Sleep"] + #[inline(always)] + pub fn sleepprm(&self) -> SLEEPPRM_R { + SLEEPPRM_R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bit 11 - fast wake-up"] + #[inline(always)] + pub fn fwup(&self) -> FWUP_R { + FWUP_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 16:17 - NVMCTRL Read Mode"] + #[inline(always)] + pub fn readmode(&self) -> READMODE_R { + READMODE_R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bit 18 - Cache Disable"] + #[inline(always)] + pub fn cachedis(&self) -> CACHEDIS_R { + CACHEDIS_R::new(((self.bits >> 18) & 1) != 0) + } +} +impl W { + #[doc = "Bits 1:4 - NVM Read Wait States"] + #[inline(always)] + #[must_use] + pub fn rws(&mut self) -> RWS_W<1> { + RWS_W::new(self) + } + #[doc = "Bit 7 - Manual Write"] + #[inline(always)] + #[must_use] + pub fn manw(&mut self) -> MANW_W<7> { + MANW_W::new(self) + } + #[doc = "Bits 8:9 - Power Reduction Mode during Sleep"] + #[inline(always)] + #[must_use] + pub fn sleepprm(&mut self) -> SLEEPPRM_W<8> { + SLEEPPRM_W::new(self) + } + #[doc = "Bit 11 - fast wake-up"] + #[inline(always)] + #[must_use] + pub fn fwup(&mut self) -> FWUP_W<11> { + FWUP_W::new(self) + } + #[doc = "Bits 16:17 - NVMCTRL Read Mode"] + #[inline(always)] + #[must_use] + pub fn readmode(&mut self) -> READMODE_W<16> { + READMODE_W::new(self) + } + #[doc = "Bit 18 - Cache Disable"] + #[inline(always)] + #[must_use] + pub fn cachedis(&mut self) -> CACHEDIS_W<18> { + CACHEDIS_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRLB to value 0x80"] +impl crate::Resettable for CTRLB_SPEC { + const RESET_VALUE: Self::Ux = 0x80; +} diff --git a/pac/atsaml22j/src/nvmctrl/intenclr.rs b/pac/atsaml22j/src/nvmctrl/intenclr.rs new file mode 100644 index 000000000000..5d682eba3d83 --- /dev/null +++ b/pac/atsaml22j/src/nvmctrl/intenclr.rs @@ -0,0 +1,95 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `READY` reader - NVM Ready Interrupt Enable"] +pub type READY_R = crate::BitReader; +#[doc = "Field `READY` writer - NVM Ready Interrupt Enable"] +pub type READY_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>; +#[doc = "Field `ERROR` reader - Error Interrupt Enable"] +pub type ERROR_R = crate::BitReader; +#[doc = "Field `ERROR` writer - Error Interrupt Enable"] +pub type ERROR_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - NVM Ready Interrupt Enable"] + #[inline(always)] + pub fn ready(&self) -> READY_R { + READY_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - NVM Ready Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn ready(&mut self) -> READY_W<0> { + READY_W::new(self) + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn error(&mut self) -> ERROR_W<1> { + ERROR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/nvmctrl/intenset.rs b/pac/atsaml22j/src/nvmctrl/intenset.rs new file mode 100644 index 000000000000..62e9fef274ba --- /dev/null +++ b/pac/atsaml22j/src/nvmctrl/intenset.rs @@ -0,0 +1,95 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `READY` reader - NVM Ready Interrupt Enable"] +pub type READY_R = crate::BitReader; +#[doc = "Field `READY` writer - NVM Ready Interrupt Enable"] +pub type READY_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENSET_SPEC, bool, O>; +#[doc = "Field `ERROR` reader - Error Interrupt Enable"] +pub type ERROR_R = crate::BitReader; +#[doc = "Field `ERROR` writer - Error Interrupt Enable"] +pub type ERROR_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENSET_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - NVM Ready Interrupt Enable"] + #[inline(always)] + pub fn ready(&self) -> READY_R { + READY_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - NVM Ready Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn ready(&mut self) -> READY_W<0> { + READY_W::new(self) + } + #[doc = "Bit 1 - Error Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn error(&mut self) -> ERROR_W<1> { + ERROR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/nvmctrl/intflag.rs b/pac/atsaml22j/src/nvmctrl/intflag.rs new file mode 100644 index 000000000000..cf5d9c93a012 --- /dev/null +++ b/pac/atsaml22j/src/nvmctrl/intflag.rs @@ -0,0 +1,95 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `READY` reader - NVM Ready"] +pub type READY_R = crate::BitReader; +#[doc = "Field `READY` writer - NVM Ready"] +pub type READY_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTFLAG_SPEC, bool, O>; +#[doc = "Field `ERROR` reader - Error"] +pub type ERROR_R = crate::BitReader; +#[doc = "Field `ERROR` writer - Error"] +pub type ERROR_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTFLAG_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - NVM Ready"] + #[inline(always)] + pub fn ready(&self) -> READY_R { + READY_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Error"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - NVM Ready"] + #[inline(always)] + #[must_use] + pub fn ready(&mut self) -> READY_W<0> { + READY_W::new(self) + } + #[doc = "Bit 1 - Error"] + #[inline(always)] + #[must_use] + pub fn error(&mut self) -> ERROR_W<1> { + ERROR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/nvmctrl/lock.rs b/pac/atsaml22j/src/nvmctrl/lock.rs new file mode 100644 index 000000000000..a07ac2800d06 --- /dev/null +++ b/pac/atsaml22j/src/nvmctrl/lock.rs @@ -0,0 +1,72 @@ +#[doc = "Register `LOCK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LOCK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LOCK` reader - Region Lock Bits"] +pub type LOCK_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Region Lock Bits"] + #[inline(always)] + pub fn lock(&self) -> LOCK_R { + LOCK_R::new(self.bits) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Lock Section\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lock](index.html) module"] +pub struct LOCK_SPEC; +impl crate::RegisterSpec for LOCK_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [lock::R](R) reader structure"] +impl crate::Readable for LOCK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [lock::W](W) writer structure"] +impl crate::Writable for LOCK_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LOCK to value 0"] +impl crate::Resettable for LOCK_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/nvmctrl/param.rs b/pac/atsaml22j/src/nvmctrl/param.rs new file mode 100644 index 000000000000..6e0734814f5c --- /dev/null +++ b/pac/atsaml22j/src/nvmctrl/param.rs @@ -0,0 +1,170 @@ +#[doc = "Register `PARAM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PARAM` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `NVMP` reader - NVM Pages"] +pub type NVMP_R = crate::FieldReader; +#[doc = "Field `PSZ` reader - Page Size"] +pub type PSZ_R = crate::FieldReader; +#[doc = "Page Size\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum PSZSELECT_A { + #[doc = "0: 8 bytes"] + _8 = 0, + #[doc = "1: 16 bytes"] + _16 = 1, + #[doc = "2: 32 bytes"] + _32 = 2, + #[doc = "3: 64 bytes"] + _64 = 3, + #[doc = "4: 128 bytes"] + _128 = 4, + #[doc = "5: 256 bytes"] + _256 = 5, + #[doc = "6: 512 bytes"] + _512 = 6, + #[doc = "7: 1024 bytes"] + _1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PSZSELECT_A) -> Self { + variant as _ + } +} +impl PSZ_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PSZSELECT_A { + match self.bits { + 0 => PSZSELECT_A::_8, + 1 => PSZSELECT_A::_16, + 2 => PSZSELECT_A::_32, + 3 => PSZSELECT_A::_64, + 4 => PSZSELECT_A::_128, + 5 => PSZSELECT_A::_256, + 6 => PSZSELECT_A::_512, + 7 => PSZSELECT_A::_1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `_8`"] + #[inline(always)] + pub fn is_8(&self) -> bool { + *self == PSZSELECT_A::_8 + } + #[doc = "Checks if the value of the field is `_16`"] + #[inline(always)] + pub fn is_16(&self) -> bool { + *self == PSZSELECT_A::_16 + } + #[doc = "Checks if the value of the field is `_32`"] + #[inline(always)] + pub fn is_32(&self) -> bool { + *self == PSZSELECT_A::_32 + } + #[doc = "Checks if the value of the field is `_64`"] + #[inline(always)] + pub fn is_64(&self) -> bool { + *self == PSZSELECT_A::_64 + } + #[doc = "Checks if the value of the field is `_128`"] + #[inline(always)] + pub fn is_128(&self) -> bool { + *self == PSZSELECT_A::_128 + } + #[doc = "Checks if the value of the field is `_256`"] + #[inline(always)] + pub fn is_256(&self) -> bool { + *self == PSZSELECT_A::_256 + } + #[doc = "Checks if the value of the field is `_512`"] + #[inline(always)] + pub fn is_512(&self) -> bool { + *self == PSZSELECT_A::_512 + } + #[doc = "Checks if the value of the field is `_1024`"] + #[inline(always)] + pub fn is_1024(&self) -> bool { + *self == PSZSELECT_A::_1024 + } +} +#[doc = "Field `RWWEEP` reader - RWW EEPROM Pages"] +pub type RWWEEP_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - NVM Pages"] + #[inline(always)] + pub fn nvmp(&self) -> NVMP_R { + NVMP_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:18 - Page Size"] + #[inline(always)] + pub fn psz(&self) -> PSZ_R { + PSZ_R::new(((self.bits >> 16) & 7) as u8) + } + #[doc = "Bits 20:31 - RWW EEPROM Pages"] + #[inline(always)] + pub fn rwweep(&self) -> RWWEEP_R { + RWWEEP_R::new(((self.bits >> 20) & 0x0fff) as u16) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "NVM Parameter\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [param](index.html) module"] +pub struct PARAM_SPEC; +impl crate::RegisterSpec for PARAM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [param::R](R) reader structure"] +impl crate::Readable for PARAM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [param::W](W) writer structure"] +impl crate::Writable for PARAM_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PARAM to value 0"] +impl crate::Resettable for PARAM_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/nvmctrl/status.rs b/pac/atsaml22j/src/nvmctrl/status.rs new file mode 100644 index 000000000000..d3b0ba8c53b6 --- /dev/null +++ b/pac/atsaml22j/src/nvmctrl/status.rs @@ -0,0 +1,139 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PRM` reader - Power Reduction Mode"] +pub type PRM_R = crate::BitReader; +#[doc = "Field `LOAD` reader - NVM Page Buffer Active Loading"] +pub type LOAD_R = crate::BitReader; +#[doc = "Field `LOAD` writer - NVM Page Buffer Active Loading"] +pub type LOAD_W<'a, const O: u8> = crate::BitWriter<'a, u16, STATUS_SPEC, bool, O>; +#[doc = "Field `PROGE` reader - Programming Error Status"] +pub type PROGE_R = crate::BitReader; +#[doc = "Field `PROGE` writer - Programming Error Status"] +pub type PROGE_W<'a, const O: u8> = crate::BitWriter<'a, u16, STATUS_SPEC, bool, O>; +#[doc = "Field `LOCKE` reader - Lock Error Status"] +pub type LOCKE_R = crate::BitReader; +#[doc = "Field `LOCKE` writer - Lock Error Status"] +pub type LOCKE_W<'a, const O: u8> = crate::BitWriter<'a, u16, STATUS_SPEC, bool, O>; +#[doc = "Field `NVME` reader - NVM Error"] +pub type NVME_R = crate::BitReader; +#[doc = "Field `NVME` writer - NVM Error"] +pub type NVME_W<'a, const O: u8> = crate::BitWriter<'a, u16, STATUS_SPEC, bool, O>; +#[doc = "Field `SB` reader - Security Bit Status"] +pub type SB_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Power Reduction Mode"] + #[inline(always)] + pub fn prm(&self) -> PRM_R { + PRM_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - NVM Page Buffer Active Loading"] + #[inline(always)] + pub fn load(&self) -> LOAD_R { + LOAD_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Programming Error Status"] + #[inline(always)] + pub fn proge(&self) -> PROGE_R { + PROGE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Lock Error Status"] + #[inline(always)] + pub fn locke(&self) -> LOCKE_R { + LOCKE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - NVM Error"] + #[inline(always)] + pub fn nvme(&self) -> NVME_R { + NVME_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 8 - Security Bit Status"] + #[inline(always)] + pub fn sb(&self) -> SB_R { + SB_R::new(((self.bits >> 8) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - NVM Page Buffer Active Loading"] + #[inline(always)] + #[must_use] + pub fn load(&mut self) -> LOAD_W<1> { + LOAD_W::new(self) + } + #[doc = "Bit 2 - Programming Error Status"] + #[inline(always)] + #[must_use] + pub fn proge(&mut self) -> PROGE_W<2> { + PROGE_W::new(self) + } + #[doc = "Bit 3 - Lock Error Status"] + #[inline(always)] + #[must_use] + pub fn locke(&mut self) -> LOCKE_W<3> { + LOCKE_W::new(self) + } + #[doc = "Bit 4 - NVM Error"] + #[inline(always)] + #[must_use] + pub fn nvme(&mut self) -> NVME_W<4> { + NVME_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/osc32kctrl.rs b/pac/atsaml22j/src/osc32kctrl.rs new file mode 100644 index 000000000000..bc9717ada096 --- /dev/null +++ b/pac/atsaml22j/src/osc32kctrl.rs @@ -0,0 +1,66 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Interrupt Enable Clear"] + pub intenclr: INTENCLR, + #[doc = "0x04 - Interrupt Enable Set"] + pub intenset: INTENSET, + #[doc = "0x08 - Interrupt Flag Status and Clear"] + pub intflag: INTFLAG, + #[doc = "0x0c - Power and Clocks Status"] + pub status: STATUS, + #[doc = "0x10 - RTC Clock Selection"] + pub rtcctrl: RTCCTRL, + #[doc = "0x11 - SLCD Clock Selection"] + pub slcdctrl: SLCDCTRL, + _reserved6: [u8; 0x02], + #[doc = "0x14 - 32kHz External Crystal Oscillator (XOSC32K) Control"] + pub xosc32k: XOSC32K, + #[doc = "0x16 - Clock Failure Detector Control"] + pub cfdctrl: CFDCTRL, + #[doc = "0x17 - Event Control"] + pub evctrl: EVCTRL, + _reserved9: [u8; 0x04], + #[doc = "0x1c - 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control"] + pub osculp32k: OSCULP32K, +} +#[doc = "INTENCLR (rw) register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET (rw) register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG (rw) register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS (r) register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Power and Clocks Status"] +pub mod status; +#[doc = "RTCCTRL (rw) register accessor: an alias for `Reg`"] +pub type RTCCTRL = crate::Reg; +#[doc = "RTC Clock Selection"] +pub mod rtcctrl; +#[doc = "SLCDCTRL (rw) register accessor: an alias for `Reg`"] +pub type SLCDCTRL = crate::Reg; +#[doc = "SLCD Clock Selection"] +pub mod slcdctrl; +#[doc = "XOSC32K (rw) register accessor: an alias for `Reg`"] +pub type XOSC32K = crate::Reg; +#[doc = "32kHz External Crystal Oscillator (XOSC32K) Control"] +pub mod xosc32k; +#[doc = "CFDCTRL (rw) register accessor: an alias for `Reg`"] +pub type CFDCTRL = crate::Reg; +#[doc = "Clock Failure Detector Control"] +pub mod cfdctrl; +#[doc = "EVCTRL (rw) register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "OSCULP32K (rw) register accessor: an alias for `Reg`"] +pub type OSCULP32K = crate::Reg; +#[doc = "32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control"] +pub mod osculp32k; diff --git a/pac/atsaml22j/src/osc32kctrl/cfdctrl.rs b/pac/atsaml22j/src/osc32kctrl/cfdctrl.rs new file mode 100644 index 000000000000..10612d374b09 --- /dev/null +++ b/pac/atsaml22j/src/osc32kctrl/cfdctrl.rs @@ -0,0 +1,110 @@ +#[doc = "Register `CFDCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CFDCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CFDEN` reader - Clock Failure Detector Enable"] +pub type CFDEN_R = crate::BitReader; +#[doc = "Field `CFDEN` writer - Clock Failure Detector Enable"] +pub type CFDEN_W<'a, const O: u8> = crate::BitWriter<'a, u8, CFDCTRL_SPEC, bool, O>; +#[doc = "Field `SWBACK` reader - Clock Switch Back"] +pub type SWBACK_R = crate::BitReader; +#[doc = "Field `SWBACK` writer - Clock Switch Back"] +pub type SWBACK_W<'a, const O: u8> = crate::BitWriter<'a, u8, CFDCTRL_SPEC, bool, O>; +#[doc = "Field `CFDPRESC` reader - Clock Failure Detector Prescaler"] +pub type CFDPRESC_R = crate::BitReader; +#[doc = "Field `CFDPRESC` writer - Clock Failure Detector Prescaler"] +pub type CFDPRESC_W<'a, const O: u8> = crate::BitWriter<'a, u8, CFDCTRL_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Clock Failure Detector Enable"] + #[inline(always)] + pub fn cfden(&self) -> CFDEN_R { + CFDEN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Clock Switch Back"] + #[inline(always)] + pub fn swback(&self) -> SWBACK_R { + SWBACK_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Clock Failure Detector Prescaler"] + #[inline(always)] + pub fn cfdpresc(&self) -> CFDPRESC_R { + CFDPRESC_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Failure Detector Enable"] + #[inline(always)] + #[must_use] + pub fn cfden(&mut self) -> CFDEN_W<0> { + CFDEN_W::new(self) + } + #[doc = "Bit 1 - Clock Switch Back"] + #[inline(always)] + #[must_use] + pub fn swback(&mut self) -> SWBACK_W<1> { + SWBACK_W::new(self) + } + #[doc = "Bit 2 - Clock Failure Detector Prescaler"] + #[inline(always)] + #[must_use] + pub fn cfdpresc(&mut self) -> CFDPRESC_W<2> { + CFDPRESC_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clock Failure Detector Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfdctrl](index.html) module"] +pub struct CFDCTRL_SPEC; +impl crate::RegisterSpec for CFDCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [cfdctrl::R](R) reader structure"] +impl crate::Readable for CFDCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cfdctrl::W](W) writer structure"] +impl crate::Writable for CFDCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CFDCTRL to value 0"] +impl crate::Resettable for CFDCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/osc32kctrl/evctrl.rs b/pac/atsaml22j/src/osc32kctrl/evctrl.rs new file mode 100644 index 000000000000..0c8a687b8880 --- /dev/null +++ b/pac/atsaml22j/src/osc32kctrl/evctrl.rs @@ -0,0 +1,80 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CFDEO` reader - Clock Failure Detector Event Output Enable"] +pub type CFDEO_R = crate::BitReader; +#[doc = "Field `CFDEO` writer - Clock Failure Detector Event Output Enable"] +pub type CFDEO_W<'a, const O: u8> = crate::BitWriter<'a, u8, EVCTRL_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Clock Failure Detector Event Output Enable"] + #[inline(always)] + pub fn cfdeo(&self) -> CFDEO_R { + CFDEO_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Failure Detector Event Output Enable"] + #[inline(always)] + #[must_use] + pub fn cfdeo(&mut self) -> CFDEO_W<0> { + CFDEO_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/osc32kctrl/intenclr.rs b/pac/atsaml22j/src/osc32kctrl/intenclr.rs new file mode 100644 index 000000000000..68ad55d3105e --- /dev/null +++ b/pac/atsaml22j/src/osc32kctrl/intenclr.rs @@ -0,0 +1,95 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSC32KRDY` reader - XOSC32K Ready Interrupt Enable"] +pub type XOSC32KRDY_R = crate::BitReader; +#[doc = "Field `XOSC32KRDY` writer - XOSC32K Ready Interrupt Enable"] +pub type XOSC32KRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>; +#[doc = "Field `CLKFAIL` reader - XOSC32K Clock Failure Detector Interrupt Enable"] +pub type CLKFAIL_R = crate::BitReader; +#[doc = "Field `CLKFAIL` writer - XOSC32K Clock Failure Detector Interrupt Enable"] +pub type CLKFAIL_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - XOSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn xosc32krdy(&self) -> XOSC32KRDY_R { + XOSC32KRDY_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn clkfail(&self) -> CLKFAIL_R { + CLKFAIL_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC32K Ready Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn xosc32krdy(&mut self) -> XOSC32KRDY_W<0> { + XOSC32KRDY_W::new(self) + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn clkfail(&mut self) -> CLKFAIL_W<2> { + CLKFAIL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/osc32kctrl/intenset.rs b/pac/atsaml22j/src/osc32kctrl/intenset.rs new file mode 100644 index 000000000000..384fce08ebb1 --- /dev/null +++ b/pac/atsaml22j/src/osc32kctrl/intenset.rs @@ -0,0 +1,95 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSC32KRDY` reader - XOSC32K Ready Interrupt Enable"] +pub type XOSC32KRDY_R = crate::BitReader; +#[doc = "Field `XOSC32KRDY` writer - XOSC32K Ready Interrupt Enable"] +pub type XOSC32KRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>; +#[doc = "Field `CLKFAIL` reader - XOSC32K Clock Failure Detector Interrupt Enable"] +pub type CLKFAIL_R = crate::BitReader; +#[doc = "Field `CLKFAIL` writer - XOSC32K Clock Failure Detector Interrupt Enable"] +pub type CLKFAIL_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - XOSC32K Ready Interrupt Enable"] + #[inline(always)] + pub fn xosc32krdy(&self) -> XOSC32KRDY_R { + XOSC32KRDY_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn clkfail(&self) -> CLKFAIL_R { + CLKFAIL_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC32K Ready Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn xosc32krdy(&mut self) -> XOSC32KRDY_W<0> { + XOSC32KRDY_W::new(self) + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn clkfail(&mut self) -> CLKFAIL_W<2> { + CLKFAIL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/osc32kctrl/intflag.rs b/pac/atsaml22j/src/osc32kctrl/intflag.rs new file mode 100644 index 000000000000..a8d43f2f8098 --- /dev/null +++ b/pac/atsaml22j/src/osc32kctrl/intflag.rs @@ -0,0 +1,95 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSC32KRDY` reader - XOSC32K Ready"] +pub type XOSC32KRDY_R = crate::BitReader; +#[doc = "Field `XOSC32KRDY` writer - XOSC32K Ready"] +pub type XOSC32KRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAG_SPEC, bool, O>; +#[doc = "Field `CLKFAIL` reader - XOSC32K Clock Failure Detector"] +pub type CLKFAIL_R = crate::BitReader; +#[doc = "Field `CLKFAIL` writer - XOSC32K Clock Failure Detector"] +pub type CLKFAIL_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAG_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - XOSC32K Ready"] + #[inline(always)] + pub fn xosc32krdy(&self) -> XOSC32KRDY_R { + XOSC32KRDY_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector"] + #[inline(always)] + pub fn clkfail(&self) -> CLKFAIL_R { + CLKFAIL_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC32K Ready"] + #[inline(always)] + #[must_use] + pub fn xosc32krdy(&mut self) -> XOSC32KRDY_W<0> { + XOSC32KRDY_W::new(self) + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector"] + #[inline(always)] + #[must_use] + pub fn clkfail(&mut self) -> CLKFAIL_W<2> { + CLKFAIL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/osc32kctrl/osculp32k.rs b/pac/atsaml22j/src/osc32kctrl/osculp32k.rs new file mode 100644 index 000000000000..e7d35b3a11ac --- /dev/null +++ b/pac/atsaml22j/src/osc32kctrl/osculp32k.rs @@ -0,0 +1,125 @@ +#[doc = "Register `OSCULP32K` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OSCULP32K` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EN32K` reader - Enable Out 32k"] +pub type EN32K_R = crate::BitReader; +#[doc = "Field `EN32K` writer - Enable Out 32k"] +pub type EN32K_W<'a, const O: u8> = crate::BitWriter<'a, u32, OSCULP32K_SPEC, bool, O>; +#[doc = "Field `EN1K` reader - Enable Out 1k"] +pub type EN1K_R = crate::BitReader; +#[doc = "Field `EN1K` writer - Enable Out 1k"] +pub type EN1K_W<'a, const O: u8> = crate::BitWriter<'a, u32, OSCULP32K_SPEC, bool, O>; +#[doc = "Field `CALIB` reader - Oscillator Calibration"] +pub type CALIB_R = crate::FieldReader; +#[doc = "Field `CALIB` writer - Oscillator Calibration"] +pub type CALIB_W<'a, const O: u8> = crate::FieldWriter<'a, u32, OSCULP32K_SPEC, u8, u8, 5, O>; +#[doc = "Field `WRTLOCK` reader - Write Lock"] +pub type WRTLOCK_R = crate::BitReader; +#[doc = "Field `WRTLOCK` writer - Write Lock"] +pub type WRTLOCK_W<'a, const O: u8> = crate::BitWriter<'a, u32, OSCULP32K_SPEC, bool, O>; +impl R { + #[doc = "Bit 1 - Enable Out 32k"] + #[inline(always)] + pub fn en32k(&self) -> EN32K_R { + EN32K_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Enable Out 1k"] + #[inline(always)] + pub fn en1k(&self) -> EN1K_R { + EN1K_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 8:12 - Oscillator Calibration"] + #[inline(always)] + pub fn calib(&self) -> CALIB_R { + CALIB_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bit 15 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&self) -> WRTLOCK_R { + WRTLOCK_R::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Enable Out 32k"] + #[inline(always)] + #[must_use] + pub fn en32k(&mut self) -> EN32K_W<1> { + EN32K_W::new(self) + } + #[doc = "Bit 2 - Enable Out 1k"] + #[inline(always)] + #[must_use] + pub fn en1k(&mut self) -> EN1K_W<2> { + EN1K_W::new(self) + } + #[doc = "Bits 8:12 - Oscillator Calibration"] + #[inline(always)] + #[must_use] + pub fn calib(&mut self) -> CALIB_W<8> { + CALIB_W::new(self) + } + #[doc = "Bit 15 - Write Lock"] + #[inline(always)] + #[must_use] + pub fn wrtlock(&mut self) -> WRTLOCK_W<15> { + WRTLOCK_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osculp32k](index.html) module"] +pub struct OSCULP32K_SPEC; +impl crate::RegisterSpec for OSCULP32K_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [osculp32k::R](R) reader structure"] +impl crate::Readable for OSCULP32K_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [osculp32k::W](W) writer structure"] +impl crate::Writable for OSCULP32K_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OSCULP32K to value 0"] +impl crate::Resettable for OSCULP32K_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/osc32kctrl/rtcctrl.rs b/pac/atsaml22j/src/osc32kctrl/rtcctrl.rs new file mode 100644 index 000000000000..41a894ba3b04 --- /dev/null +++ b/pac/atsaml22j/src/osc32kctrl/rtcctrl.rs @@ -0,0 +1,155 @@ +#[doc = "Register `RTCCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RTCCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RTCSEL` reader - RTC Clock Selection"] +pub type RTCSEL_R = crate::FieldReader; +#[doc = "RTC Clock Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum RTCSELSELECT_A { + #[doc = "0: 1.024kHz from 32kHz internal ULP oscillator"] + ULP1K = 0, + #[doc = "1: 32.768kHz from 32kHz internal ULP oscillator"] + ULP32K = 1, + #[doc = "4: 1.024kHz from 32.768kHz external oscillator"] + XOSC1K = 4, + #[doc = "5: 32.768kHz from 32.768kHz external crystal oscillator"] + XOSC32K = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RTCSELSELECT_A) -> Self { + variant as _ + } +} +impl RTCSEL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(RTCSELSELECT_A::ULP1K), + 1 => Some(RTCSELSELECT_A::ULP32K), + 4 => Some(RTCSELSELECT_A::XOSC1K), + 5 => Some(RTCSELSELECT_A::XOSC32K), + _ => None, + } + } + #[doc = "Checks if the value of the field is `ULP1K`"] + #[inline(always)] + pub fn is_ulp1k(&self) -> bool { + *self == RTCSELSELECT_A::ULP1K + } + #[doc = "Checks if the value of the field is `ULP32K`"] + #[inline(always)] + pub fn is_ulp32k(&self) -> bool { + *self == RTCSELSELECT_A::ULP32K + } + #[doc = "Checks if the value of the field is `XOSC1K`"] + #[inline(always)] + pub fn is_xosc1k(&self) -> bool { + *self == RTCSELSELECT_A::XOSC1K + } + #[doc = "Checks if the value of the field is `XOSC32K`"] + #[inline(always)] + pub fn is_xosc32k(&self) -> bool { + *self == RTCSELSELECT_A::XOSC32K + } +} +#[doc = "Field `RTCSEL` writer - RTC Clock Selection"] +pub type RTCSEL_W<'a, const O: u8> = + crate::FieldWriter<'a, u8, RTCCTRL_SPEC, u8, RTCSELSELECT_A, 3, O>; +impl<'a, const O: u8> RTCSEL_W<'a, O> { + #[doc = "1.024kHz from 32kHz internal ULP oscillator"] + #[inline(always)] + pub fn ulp1k(self) -> &'a mut W { + self.variant(RTCSELSELECT_A::ULP1K) + } + #[doc = "32.768kHz from 32kHz internal ULP oscillator"] + #[inline(always)] + pub fn ulp32k(self) -> &'a mut W { + self.variant(RTCSELSELECT_A::ULP32K) + } + #[doc = "1.024kHz from 32.768kHz external oscillator"] + #[inline(always)] + pub fn xosc1k(self) -> &'a mut W { + self.variant(RTCSELSELECT_A::XOSC1K) + } + #[doc = "32.768kHz from 32.768kHz external crystal oscillator"] + #[inline(always)] + pub fn xosc32k(self) -> &'a mut W { + self.variant(RTCSELSELECT_A::XOSC32K) + } +} +impl R { + #[doc = "Bits 0:2 - RTC Clock Selection"] + #[inline(always)] + pub fn rtcsel(&self) -> RTCSEL_R { + RTCSEL_R::new(self.bits & 7) + } +} +impl W { + #[doc = "Bits 0:2 - RTC Clock Selection"] + #[inline(always)] + #[must_use] + pub fn rtcsel(&mut self) -> RTCSEL_W<0> { + RTCSEL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "RTC Clock Selection\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rtcctrl](index.html) module"] +pub struct RTCCTRL_SPEC; +impl crate::RegisterSpec for RTCCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [rtcctrl::R](R) reader structure"] +impl crate::Readable for RTCCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rtcctrl::W](W) writer structure"] +impl crate::Writable for RTCCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RTCCTRL to value 0"] +impl crate::Resettable for RTCCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/osc32kctrl/slcdctrl.rs b/pac/atsaml22j/src/osc32kctrl/slcdctrl.rs new file mode 100644 index 000000000000..c5b7a5a49a18 --- /dev/null +++ b/pac/atsaml22j/src/osc32kctrl/slcdctrl.rs @@ -0,0 +1,80 @@ +#[doc = "Register `SLCDCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SLCDCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SLCDSEL` reader - SLCD Clock Selection"] +pub type SLCDSEL_R = crate::BitReader; +#[doc = "Field `SLCDSEL` writer - SLCD Clock Selection"] +pub type SLCDSEL_W<'a, const O: u8> = crate::BitWriter<'a, u8, SLCDCTRL_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - SLCD Clock Selection"] + #[inline(always)] + pub fn slcdsel(&self) -> SLCDSEL_R { + SLCDSEL_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - SLCD Clock Selection"] + #[inline(always)] + #[must_use] + pub fn slcdsel(&mut self) -> SLCDSEL_W<0> { + SLCDSEL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SLCD Clock Selection\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [slcdctrl](index.html) module"] +pub struct SLCDCTRL_SPEC; +impl crate::RegisterSpec for SLCDCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [slcdctrl::R](R) reader structure"] +impl crate::Readable for SLCDCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [slcdctrl::W](W) writer structure"] +impl crate::Writable for SLCDCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SLCDCTRL to value 0"] +impl crate::Resettable for SLCDCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/osc32kctrl/status.rs b/pac/atsaml22j/src/osc32kctrl/status.rs new file mode 100644 index 000000000000..73d2cd61be12 --- /dev/null +++ b/pac/atsaml22j/src/osc32kctrl/status.rs @@ -0,0 +1,51 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `XOSC32KRDY` reader - XOSC32K Ready"] +pub type XOSC32KRDY_R = crate::BitReader; +#[doc = "Field `CLKFAIL` reader - XOSC32K Clock Failure Detector"] +pub type CLKFAIL_R = crate::BitReader; +#[doc = "Field `CLKSW` reader - XOSC32K Clock switch"] +pub type CLKSW_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - XOSC32K Ready"] + #[inline(always)] + pub fn xosc32krdy(&self) -> XOSC32KRDY_R { + XOSC32KRDY_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 2 - XOSC32K Clock Failure Detector"] + #[inline(always)] + pub fn clkfail(&self) -> CLKFAIL_R { + CLKFAIL_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - XOSC32K Clock switch"] + #[inline(always)] + pub fn clksw(&self) -> CLKSW_R { + CLKSW_R::new(((self.bits >> 3) & 1) != 0) + } +} +#[doc = "Power and Clocks Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/osc32kctrl/xosc32k.rs b/pac/atsaml22j/src/osc32kctrl/xosc32k.rs new file mode 100644 index 000000000000..5775658eea22 --- /dev/null +++ b/pac/atsaml22j/src/osc32kctrl/xosc32k.rs @@ -0,0 +1,185 @@ +#[doc = "Register `XOSC32K` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `XOSC32K` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Oscillator Enable"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - Oscillator Enable"] +pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u16, XOSC32K_SPEC, bool, O>; +#[doc = "Field `XTALEN` reader - Crystal Oscillator Enable"] +pub type XTALEN_R = crate::BitReader; +#[doc = "Field `XTALEN` writer - Crystal Oscillator Enable"] +pub type XTALEN_W<'a, const O: u8> = crate::BitWriter<'a, u16, XOSC32K_SPEC, bool, O>; +#[doc = "Field `EN32K` reader - 32kHz Output Enable"] +pub type EN32K_R = crate::BitReader; +#[doc = "Field `EN32K` writer - 32kHz Output Enable"] +pub type EN32K_W<'a, const O: u8> = crate::BitWriter<'a, u16, XOSC32K_SPEC, bool, O>; +#[doc = "Field `EN1K` reader - 1kHz Output Enable"] +pub type EN1K_R = crate::BitReader; +#[doc = "Field `EN1K` writer - 1kHz Output Enable"] +pub type EN1K_W<'a, const O: u8> = crate::BitWriter<'a, u16, XOSC32K_SPEC, bool, O>; +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub type RUNSTDBY_R = crate::BitReader; +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub type RUNSTDBY_W<'a, const O: u8> = crate::BitWriter<'a, u16, XOSC32K_SPEC, bool, O>; +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub type ONDEMAND_R = crate::BitReader; +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub type ONDEMAND_W<'a, const O: u8> = crate::BitWriter<'a, u16, XOSC32K_SPEC, bool, O>; +#[doc = "Field `STARTUP` reader - Oscillator Start-Up Time"] +pub type STARTUP_R = crate::FieldReader; +#[doc = "Field `STARTUP` writer - Oscillator Start-Up Time"] +pub type STARTUP_W<'a, const O: u8> = crate::FieldWriter<'a, u16, XOSC32K_SPEC, u8, u8, 3, O>; +#[doc = "Field `WRTLOCK` reader - Write Lock"] +pub type WRTLOCK_R = crate::BitReader; +#[doc = "Field `WRTLOCK` writer - Write Lock"] +pub type WRTLOCK_W<'a, const O: u8> = crate::BitWriter<'a, u16, XOSC32K_SPEC, bool, O>; +impl R { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Crystal Oscillator Enable"] + #[inline(always)] + pub fn xtalen(&self) -> XTALEN_R { + XTALEN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - 32kHz Output Enable"] + #[inline(always)] + pub fn en32k(&self) -> EN32K_R { + EN32K_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - 1kHz Output Enable"] + #[inline(always)] + pub fn en1k(&self) -> EN1K_R { + EN1K_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:10 - Oscillator Start-Up Time"] + #[inline(always)] + pub fn startup(&self) -> STARTUP_R { + STARTUP_R::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 12 - Write Lock"] + #[inline(always)] + pub fn wrtlock(&self) -> WRTLOCK_R { + WRTLOCK_R::new(((self.bits >> 12) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W<1> { + ENABLE_W::new(self) + } + #[doc = "Bit 2 - Crystal Oscillator Enable"] + #[inline(always)] + #[must_use] + pub fn xtalen(&mut self) -> XTALEN_W<2> { + XTALEN_W::new(self) + } + #[doc = "Bit 3 - 32kHz Output Enable"] + #[inline(always)] + #[must_use] + pub fn en32k(&mut self) -> EN32K_W<3> { + EN32K_W::new(self) + } + #[doc = "Bit 4 - 1kHz Output Enable"] + #[inline(always)] + #[must_use] + pub fn en1k(&mut self) -> EN1K_W<4> { + EN1K_W::new(self) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + #[must_use] + pub fn runstdby(&mut self) -> RUNSTDBY_W<6> { + RUNSTDBY_W::new(self) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + #[must_use] + pub fn ondemand(&mut self) -> ONDEMAND_W<7> { + ONDEMAND_W::new(self) + } + #[doc = "Bits 8:10 - Oscillator Start-Up Time"] + #[inline(always)] + #[must_use] + pub fn startup(&mut self) -> STARTUP_W<8> { + STARTUP_W::new(self) + } + #[doc = "Bit 12 - Write Lock"] + #[inline(always)] + #[must_use] + pub fn wrtlock(&mut self) -> WRTLOCK_W<12> { + WRTLOCK_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "32kHz External Crystal Oscillator (XOSC32K) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xosc32k](index.html) module"] +pub struct XOSC32K_SPEC; +impl crate::RegisterSpec for XOSC32K_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [xosc32k::R](R) reader structure"] +impl crate::Readable for XOSC32K_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [xosc32k::W](W) writer structure"] +impl crate::Writable for XOSC32K_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets XOSC32K to value 0x80"] +impl crate::Resettable for XOSC32K_SPEC { + const RESET_VALUE: Self::Ux = 0x80; +} diff --git a/pac/atsaml22j/src/oscctrl.rs b/pac/atsaml22j/src/oscctrl.rs new file mode 100644 index 000000000000..45eaadbd237f --- /dev/null +++ b/pac/atsaml22j/src/oscctrl.rs @@ -0,0 +1,118 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Interrupt Enable Clear"] + pub intenclr: INTENCLR, + #[doc = "0x04 - Interrupt Enable Set"] + pub intenset: INTENSET, + #[doc = "0x08 - Interrupt Flag Status and Clear"] + pub intflag: INTFLAG, + #[doc = "0x0c - Power and Clocks Status"] + pub status: STATUS, + #[doc = "0x10 - External Multipurpose Crystal Oscillator (XOSC) Control"] + pub xoscctrl: XOSCCTRL, + #[doc = "0x12 - Cloc Failure Detector Prescaler"] + pub cfdpresc: CFDPRESC, + #[doc = "0x13 - Event Control"] + pub evctrl: EVCTRL, + #[doc = "0x14 - 16MHz Internal Oscillator (OSC16M) Control"] + pub osc16mctrl: OSC16MCTRL, + _reserved8: [u8; 0x03], + #[doc = "0x18 - DFLL48M Control"] + pub dfllctrl: DFLLCTRL, + _reserved9: [u8; 0x02], + #[doc = "0x1c - DFLL48M Value"] + pub dfllval: DFLLVAL, + #[doc = "0x20 - DFLL48M Multiplier"] + pub dfllmul: DFLLMUL, + #[doc = "0x24 - DFLL48M Synchronization"] + pub dfllsync: DFLLSYNC, + _reserved12: [u8; 0x03], + #[doc = "0x28 - DPLL Control"] + pub dpllctrla: DPLLCTRLA, + _reserved13: [u8; 0x03], + #[doc = "0x2c - DPLL Ratio Control"] + pub dpllratio: DPLLRATIO, + #[doc = "0x30 - Digital Core Configuration"] + pub dpllctrlb: DPLLCTRLB, + #[doc = "0x34 - DPLL Prescaler"] + pub dpllpresc: DPLLPRESC, + _reserved16: [u8; 0x03], + #[doc = "0x38 - DPLL Synchronization Busy"] + pub dpllsyncbusy: DPLLSYNCBUSY, + _reserved17: [u8; 0x03], + #[doc = "0x3c - DPLL Status"] + pub dpllstatus: DPLLSTATUS, +} +#[doc = "INTENCLR (rw) register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET (rw) register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG (rw) register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS (r) register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Power and Clocks Status"] +pub mod status; +#[doc = "XOSCCTRL (rw) register accessor: an alias for `Reg`"] +pub type XOSCCTRL = crate::Reg; +#[doc = "External Multipurpose Crystal Oscillator (XOSC) Control"] +pub mod xoscctrl; +#[doc = "CFDPRESC (rw) register accessor: an alias for `Reg`"] +pub type CFDPRESC = crate::Reg; +#[doc = "Cloc Failure Detector Prescaler"] +pub mod cfdpresc; +#[doc = "EVCTRL (rw) register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "OSC16MCTRL (rw) register accessor: an alias for `Reg`"] +pub type OSC16MCTRL = crate::Reg; +#[doc = "16MHz Internal Oscillator (OSC16M) Control"] +pub mod osc16mctrl; +#[doc = "DFLLCTRL (rw) register accessor: an alias for `Reg`"] +pub type DFLLCTRL = crate::Reg; +#[doc = "DFLL48M Control"] +pub mod dfllctrl; +#[doc = "DFLLVAL (rw) register accessor: an alias for `Reg`"] +pub type DFLLVAL = crate::Reg; +#[doc = "DFLL48M Value"] +pub mod dfllval; +#[doc = "DFLLMUL (rw) register accessor: an alias for `Reg`"] +pub type DFLLMUL = crate::Reg; +#[doc = "DFLL48M Multiplier"] +pub mod dfllmul; +#[doc = "DFLLSYNC (rw) register accessor: an alias for `Reg`"] +pub type DFLLSYNC = crate::Reg; +#[doc = "DFLL48M Synchronization"] +pub mod dfllsync; +#[doc = "DPLLCTRLA (rw) register accessor: an alias for `Reg`"] +pub type DPLLCTRLA = crate::Reg; +#[doc = "DPLL Control"] +pub mod dpllctrla; +#[doc = "DPLLRATIO (rw) register accessor: an alias for `Reg`"] +pub type DPLLRATIO = crate::Reg; +#[doc = "DPLL Ratio Control"] +pub mod dpllratio; +#[doc = "DPLLCTRLB (rw) register accessor: an alias for `Reg`"] +pub type DPLLCTRLB = crate::Reg; +#[doc = "Digital Core Configuration"] +pub mod dpllctrlb; +#[doc = "DPLLPRESC (rw) register accessor: an alias for `Reg`"] +pub type DPLLPRESC = crate::Reg; +#[doc = "DPLL Prescaler"] +pub mod dpllpresc; +#[doc = "DPLLSYNCBUSY (r) register accessor: an alias for `Reg`"] +pub type DPLLSYNCBUSY = crate::Reg; +#[doc = "DPLL Synchronization Busy"] +pub mod dpllsyncbusy; +#[doc = "DPLLSTATUS (r) register accessor: an alias for `Reg`"] +pub type DPLLSTATUS = crate::Reg; +#[doc = "DPLL Status"] +pub mod dpllstatus; diff --git a/pac/atsaml22j/src/oscctrl/cfdpresc.rs b/pac/atsaml22j/src/oscctrl/cfdpresc.rs new file mode 100644 index 000000000000..ac09eff908c9 --- /dev/null +++ b/pac/atsaml22j/src/oscctrl/cfdpresc.rs @@ -0,0 +1,80 @@ +#[doc = "Register `CFDPRESC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CFDPRESC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CFDPRESC` reader - Clock Failure Detector Prescaler"] +pub type CFDPRESC_R = crate::FieldReader; +#[doc = "Field `CFDPRESC` writer - Clock Failure Detector Prescaler"] +pub type CFDPRESC_W<'a, const O: u8> = crate::FieldWriter<'a, u8, CFDPRESC_SPEC, u8, u8, 3, O>; +impl R { + #[doc = "Bits 0:2 - Clock Failure Detector Prescaler"] + #[inline(always)] + pub fn cfdpresc(&self) -> CFDPRESC_R { + CFDPRESC_R::new(self.bits & 7) + } +} +impl W { + #[doc = "Bits 0:2 - Clock Failure Detector Prescaler"] + #[inline(always)] + #[must_use] + pub fn cfdpresc(&mut self) -> CFDPRESC_W<0> { + CFDPRESC_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Cloc Failure Detector Prescaler\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cfdpresc](index.html) module"] +pub struct CFDPRESC_SPEC; +impl crate::RegisterSpec for CFDPRESC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [cfdpresc::R](R) reader structure"] +impl crate::Readable for CFDPRESC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cfdpresc::W](W) writer structure"] +impl crate::Writable for CFDPRESC_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CFDPRESC to value 0"] +impl crate::Resettable for CFDPRESC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/oscctrl/dfllctrl.rs b/pac/atsaml22j/src/oscctrl/dfllctrl.rs new file mode 100644 index 000000000000..b760430f42bf --- /dev/null +++ b/pac/atsaml22j/src/oscctrl/dfllctrl.rs @@ -0,0 +1,230 @@ +#[doc = "Register `DFLLCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DFLLCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - DFLL Enable"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - DFLL Enable"] +pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u16, DFLLCTRL_SPEC, bool, O>; +#[doc = "Field `MODE` reader - Operating Mode Selection"] +pub type MODE_R = crate::BitReader; +#[doc = "Field `MODE` writer - Operating Mode Selection"] +pub type MODE_W<'a, const O: u8> = crate::BitWriter<'a, u16, DFLLCTRL_SPEC, bool, O>; +#[doc = "Field `STABLE` reader - Stable DFLL Frequency"] +pub type STABLE_R = crate::BitReader; +#[doc = "Field `STABLE` writer - Stable DFLL Frequency"] +pub type STABLE_W<'a, const O: u8> = crate::BitWriter<'a, u16, DFLLCTRL_SPEC, bool, O>; +#[doc = "Field `LLAW` reader - Lose Lock After Wake"] +pub type LLAW_R = crate::BitReader; +#[doc = "Field `LLAW` writer - Lose Lock After Wake"] +pub type LLAW_W<'a, const O: u8> = crate::BitWriter<'a, u16, DFLLCTRL_SPEC, bool, O>; +#[doc = "Field `USBCRM` reader - USB Clock Recovery Mode"] +pub type USBCRM_R = crate::BitReader; +#[doc = "Field `USBCRM` writer - USB Clock Recovery Mode"] +pub type USBCRM_W<'a, const O: u8> = crate::BitWriter<'a, u16, DFLLCTRL_SPEC, bool, O>; +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub type RUNSTDBY_R = crate::BitReader; +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub type RUNSTDBY_W<'a, const O: u8> = crate::BitWriter<'a, u16, DFLLCTRL_SPEC, bool, O>; +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub type ONDEMAND_R = crate::BitReader; +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub type ONDEMAND_W<'a, const O: u8> = crate::BitWriter<'a, u16, DFLLCTRL_SPEC, bool, O>; +#[doc = "Field `CCDIS` reader - Chill Cycle Disable"] +pub type CCDIS_R = crate::BitReader; +#[doc = "Field `CCDIS` writer - Chill Cycle Disable"] +pub type CCDIS_W<'a, const O: u8> = crate::BitWriter<'a, u16, DFLLCTRL_SPEC, bool, O>; +#[doc = "Field `QLDIS` reader - Quick Lock Disable"] +pub type QLDIS_R = crate::BitReader; +#[doc = "Field `QLDIS` writer - Quick Lock Disable"] +pub type QLDIS_W<'a, const O: u8> = crate::BitWriter<'a, u16, DFLLCTRL_SPEC, bool, O>; +#[doc = "Field `BPLCKC` reader - Bypass Coarse Lock"] +pub type BPLCKC_R = crate::BitReader; +#[doc = "Field `BPLCKC` writer - Bypass Coarse Lock"] +pub type BPLCKC_W<'a, const O: u8> = crate::BitWriter<'a, u16, DFLLCTRL_SPEC, bool, O>; +#[doc = "Field `WAITLOCK` reader - Wait Lock"] +pub type WAITLOCK_R = crate::BitReader; +#[doc = "Field `WAITLOCK` writer - Wait Lock"] +pub type WAITLOCK_W<'a, const O: u8> = crate::BitWriter<'a, u16, DFLLCTRL_SPEC, bool, O>; +impl R { + #[doc = "Bit 1 - DFLL Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Operating Mode Selection"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Stable DFLL Frequency"] + #[inline(always)] + pub fn stable(&self) -> STABLE_R { + STABLE_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Lose Lock After Wake"] + #[inline(always)] + pub fn llaw(&self) -> LLAW_R { + LLAW_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - USB Clock Recovery Mode"] + #[inline(always)] + pub fn usbcrm(&self) -> USBCRM_R { + USBCRM_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Chill Cycle Disable"] + #[inline(always)] + pub fn ccdis(&self) -> CCDIS_R { + CCDIS_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Quick Lock Disable"] + #[inline(always)] + pub fn qldis(&self) -> QLDIS_R { + QLDIS_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Bypass Coarse Lock"] + #[inline(always)] + pub fn bplckc(&self) -> BPLCKC_R { + BPLCKC_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Wait Lock"] + #[inline(always)] + pub fn waitlock(&self) -> WAITLOCK_R { + WAITLOCK_R::new(((self.bits >> 11) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - DFLL Enable"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W<1> { + ENABLE_W::new(self) + } + #[doc = "Bit 2 - Operating Mode Selection"] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> MODE_W<2> { + MODE_W::new(self) + } + #[doc = "Bit 3 - Stable DFLL Frequency"] + #[inline(always)] + #[must_use] + pub fn stable(&mut self) -> STABLE_W<3> { + STABLE_W::new(self) + } + #[doc = "Bit 4 - Lose Lock After Wake"] + #[inline(always)] + #[must_use] + pub fn llaw(&mut self) -> LLAW_W<4> { + LLAW_W::new(self) + } + #[doc = "Bit 5 - USB Clock Recovery Mode"] + #[inline(always)] + #[must_use] + pub fn usbcrm(&mut self) -> USBCRM_W<5> { + USBCRM_W::new(self) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + #[must_use] + pub fn runstdby(&mut self) -> RUNSTDBY_W<6> { + RUNSTDBY_W::new(self) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + #[must_use] + pub fn ondemand(&mut self) -> ONDEMAND_W<7> { + ONDEMAND_W::new(self) + } + #[doc = "Bit 8 - Chill Cycle Disable"] + #[inline(always)] + #[must_use] + pub fn ccdis(&mut self) -> CCDIS_W<8> { + CCDIS_W::new(self) + } + #[doc = "Bit 9 - Quick Lock Disable"] + #[inline(always)] + #[must_use] + pub fn qldis(&mut self) -> QLDIS_W<9> { + QLDIS_W::new(self) + } + #[doc = "Bit 10 - Bypass Coarse Lock"] + #[inline(always)] + #[must_use] + pub fn bplckc(&mut self) -> BPLCKC_W<10> { + BPLCKC_W::new(self) + } + #[doc = "Bit 11 - Wait Lock"] + #[inline(always)] + #[must_use] + pub fn waitlock(&mut self) -> WAITLOCK_W<11> { + WAITLOCK_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DFLL48M Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dfllctrl](index.html) module"] +pub struct DFLLCTRL_SPEC; +impl crate::RegisterSpec for DFLLCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [dfllctrl::R](R) reader structure"] +impl crate::Readable for DFLLCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dfllctrl::W](W) writer structure"] +impl crate::Writable for DFLLCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DFLLCTRL to value 0x80"] +impl crate::Resettable for DFLLCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x80; +} diff --git a/pac/atsaml22j/src/oscctrl/dfllmul.rs b/pac/atsaml22j/src/oscctrl/dfllmul.rs new file mode 100644 index 000000000000..995ce12c337a --- /dev/null +++ b/pac/atsaml22j/src/oscctrl/dfllmul.rs @@ -0,0 +1,110 @@ +#[doc = "Register `DFLLMUL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DFLLMUL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MUL` reader - DFLL Multiply Factor"] +pub type MUL_R = crate::FieldReader; +#[doc = "Field `MUL` writer - DFLL Multiply Factor"] +pub type MUL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DFLLMUL_SPEC, u16, u16, 16, O>; +#[doc = "Field `FSTEP` reader - Fine Maximum Step"] +pub type FSTEP_R = crate::FieldReader; +#[doc = "Field `FSTEP` writer - Fine Maximum Step"] +pub type FSTEP_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DFLLMUL_SPEC, u16, u16, 10, O>; +#[doc = "Field `CSTEP` reader - Coarse Maximum Step"] +pub type CSTEP_R = crate::FieldReader; +#[doc = "Field `CSTEP` writer - Coarse Maximum Step"] +pub type CSTEP_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DFLLMUL_SPEC, u8, u8, 6, O>; +impl R { + #[doc = "Bits 0:15 - DFLL Multiply Factor"] + #[inline(always)] + pub fn mul(&self) -> MUL_R { + MUL_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:25 - Fine Maximum Step"] + #[inline(always)] + pub fn fstep(&self) -> FSTEP_R { + FSTEP_R::new(((self.bits >> 16) & 0x03ff) as u16) + } + #[doc = "Bits 26:31 - Coarse Maximum Step"] + #[inline(always)] + pub fn cstep(&self) -> CSTEP_R { + CSTEP_R::new(((self.bits >> 26) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:15 - DFLL Multiply Factor"] + #[inline(always)] + #[must_use] + pub fn mul(&mut self) -> MUL_W<0> { + MUL_W::new(self) + } + #[doc = "Bits 16:25 - Fine Maximum Step"] + #[inline(always)] + #[must_use] + pub fn fstep(&mut self) -> FSTEP_W<16> { + FSTEP_W::new(self) + } + #[doc = "Bits 26:31 - Coarse Maximum Step"] + #[inline(always)] + #[must_use] + pub fn cstep(&mut self) -> CSTEP_W<26> { + CSTEP_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DFLL48M Multiplier\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dfllmul](index.html) module"] +pub struct DFLLMUL_SPEC; +impl crate::RegisterSpec for DFLLMUL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dfllmul::R](R) reader structure"] +impl crate::Readable for DFLLMUL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dfllmul::W](W) writer structure"] +impl crate::Writable for DFLLMUL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DFLLMUL to value 0"] +impl crate::Resettable for DFLLMUL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/oscctrl/dfllsync.rs b/pac/atsaml22j/src/oscctrl/dfllsync.rs new file mode 100644 index 000000000000..66a5555913b2 --- /dev/null +++ b/pac/atsaml22j/src/oscctrl/dfllsync.rs @@ -0,0 +1,71 @@ +#[doc = "Register `DFLLSYNC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DFLLSYNC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `READREQ` writer - Read Request"] +pub type READREQ_W<'a, const O: u8> = crate::BitWriter<'a, u8, DFLLSYNC_SPEC, bool, O>; +impl W { + #[doc = "Bit 7 - Read Request"] + #[inline(always)] + #[must_use] + pub fn readreq(&mut self) -> READREQ_W<7> { + READREQ_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DFLL48M Synchronization\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dfllsync](index.html) module"] +pub struct DFLLSYNC_SPEC; +impl crate::RegisterSpec for DFLLSYNC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dfllsync::R](R) reader structure"] +impl crate::Readable for DFLLSYNC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dfllsync::W](W) writer structure"] +impl crate::Writable for DFLLSYNC_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DFLLSYNC to value 0"] +impl crate::Resettable for DFLLSYNC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/oscctrl/dfllval.rs b/pac/atsaml22j/src/oscctrl/dfllval.rs new file mode 100644 index 000000000000..bd71ff128726 --- /dev/null +++ b/pac/atsaml22j/src/oscctrl/dfllval.rs @@ -0,0 +1,102 @@ +#[doc = "Register `DFLLVAL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DFLLVAL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FINE` reader - Fine Value"] +pub type FINE_R = crate::FieldReader; +#[doc = "Field `FINE` writer - Fine Value"] +pub type FINE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DFLLVAL_SPEC, u16, u16, 10, O>; +#[doc = "Field `COARSE` reader - Coarse Value"] +pub type COARSE_R = crate::FieldReader; +#[doc = "Field `COARSE` writer - Coarse Value"] +pub type COARSE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DFLLVAL_SPEC, u8, u8, 6, O>; +#[doc = "Field `DIFF` reader - Multiplication Ratio Difference"] +pub type DIFF_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:9 - Fine Value"] + #[inline(always)] + pub fn fine(&self) -> FINE_R { + FINE_R::new((self.bits & 0x03ff) as u16) + } + #[doc = "Bits 10:15 - Coarse Value"] + #[inline(always)] + pub fn coarse(&self) -> COARSE_R { + COARSE_R::new(((self.bits >> 10) & 0x3f) as u8) + } + #[doc = "Bits 16:31 - Multiplication Ratio Difference"] + #[inline(always)] + pub fn diff(&self) -> DIFF_R { + DIFF_R::new(((self.bits >> 16) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bits 0:9 - Fine Value"] + #[inline(always)] + #[must_use] + pub fn fine(&mut self) -> FINE_W<0> { + FINE_W::new(self) + } + #[doc = "Bits 10:15 - Coarse Value"] + #[inline(always)] + #[must_use] + pub fn coarse(&mut self) -> COARSE_W<10> { + COARSE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DFLL48M Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dfllval](index.html) module"] +pub struct DFLLVAL_SPEC; +impl crate::RegisterSpec for DFLLVAL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dfllval::R](R) reader structure"] +impl crate::Readable for DFLLVAL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dfllval::W](W) writer structure"] +impl crate::Writable for DFLLVAL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DFLLVAL to value 0"] +impl crate::Resettable for DFLLVAL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/oscctrl/dpllctrla.rs b/pac/atsaml22j/src/oscctrl/dpllctrla.rs new file mode 100644 index 000000000000..b420703da9ff --- /dev/null +++ b/pac/atsaml22j/src/oscctrl/dpllctrla.rs @@ -0,0 +1,110 @@ +#[doc = "Register `DPLLCTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DPLLCTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - Enable"] +pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u8, DPLLCTRLA_SPEC, bool, O>; +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub type RUNSTDBY_R = crate::BitReader; +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub type RUNSTDBY_W<'a, const O: u8> = crate::BitWriter<'a, u8, DPLLCTRLA_SPEC, bool, O>; +#[doc = "Field `ONDEMAND` reader - On Demand"] +pub type ONDEMAND_R = crate::BitReader; +#[doc = "Field `ONDEMAND` writer - On Demand"] +pub type ONDEMAND_W<'a, const O: u8> = crate::BitWriter<'a, u8, DPLLCTRLA_SPEC, bool, O>; +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - On Demand"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W<1> { + ENABLE_W::new(self) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + #[must_use] + pub fn runstdby(&mut self) -> RUNSTDBY_W<6> { + RUNSTDBY_W::new(self) + } + #[doc = "Bit 7 - On Demand"] + #[inline(always)] + #[must_use] + pub fn ondemand(&mut self) -> ONDEMAND_W<7> { + ONDEMAND_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DPLL Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllctrla](index.html) module"] +pub struct DPLLCTRLA_SPEC; +impl crate::RegisterSpec for DPLLCTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dpllctrla::R](R) reader structure"] +impl crate::Readable for DPLLCTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dpllctrla::W](W) writer structure"] +impl crate::Writable for DPLLCTRLA_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DPLLCTRLA to value 0x80"] +impl crate::Resettable for DPLLCTRLA_SPEC { + const RESET_VALUE: Self::Ux = 0x80; +} diff --git a/pac/atsaml22j/src/oscctrl/dpllctrlb.rs b/pac/atsaml22j/src/oscctrl/dpllctrlb.rs new file mode 100644 index 000000000000..1a223345280c --- /dev/null +++ b/pac/atsaml22j/src/oscctrl/dpllctrlb.rs @@ -0,0 +1,170 @@ +#[doc = "Register `DPLLCTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DPLLCTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FILTER` reader - Proportional Integral Filter Selection"] +pub type FILTER_R = crate::FieldReader; +#[doc = "Field `FILTER` writer - Proportional Integral Filter Selection"] +pub type FILTER_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DPLLCTRLB_SPEC, u8, u8, 2, O>; +#[doc = "Field `LPEN` reader - Low-Power Enable"] +pub type LPEN_R = crate::BitReader; +#[doc = "Field `LPEN` writer - Low-Power Enable"] +pub type LPEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, DPLLCTRLB_SPEC, bool, O>; +#[doc = "Field `WUF` reader - Wake Up Fast"] +pub type WUF_R = crate::BitReader; +#[doc = "Field `WUF` writer - Wake Up Fast"] +pub type WUF_W<'a, const O: u8> = crate::BitWriter<'a, u32, DPLLCTRLB_SPEC, bool, O>; +#[doc = "Field `REFCLK` reader - Reference Clock Selection"] +pub type REFCLK_R = crate::FieldReader; +#[doc = "Field `REFCLK` writer - Reference Clock Selection"] +pub type REFCLK_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DPLLCTRLB_SPEC, u8, u8, 2, O>; +#[doc = "Field `LTIME` reader - Lock Time"] +pub type LTIME_R = crate::FieldReader; +#[doc = "Field `LTIME` writer - Lock Time"] +pub type LTIME_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DPLLCTRLB_SPEC, u8, u8, 3, O>; +#[doc = "Field `LBYPASS` reader - Lock Bypass"] +pub type LBYPASS_R = crate::BitReader; +#[doc = "Field `LBYPASS` writer - Lock Bypass"] +pub type LBYPASS_W<'a, const O: u8> = crate::BitWriter<'a, u32, DPLLCTRLB_SPEC, bool, O>; +#[doc = "Field `DIV` reader - Clock Divider"] +pub type DIV_R = crate::FieldReader; +#[doc = "Field `DIV` writer - Clock Divider"] +pub type DIV_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DPLLCTRLB_SPEC, u16, u16, 11, O>; +impl R { + #[doc = "Bits 0:1 - Proportional Integral Filter Selection"] + #[inline(always)] + pub fn filter(&self) -> FILTER_R { + FILTER_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - Low-Power Enable"] + #[inline(always)] + pub fn lpen(&self) -> LPEN_R { + LPEN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Wake Up Fast"] + #[inline(always)] + pub fn wuf(&self) -> WUF_R { + WUF_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:5 - Reference Clock Selection"] + #[inline(always)] + pub fn refclk(&self) -> REFCLK_R { + REFCLK_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 8:10 - Lock Time"] + #[inline(always)] + pub fn ltime(&self) -> LTIME_R { + LTIME_R::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 12 - Lock Bypass"] + #[inline(always)] + pub fn lbypass(&self) -> LBYPASS_R { + LBYPASS_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bits 16:26 - Clock Divider"] + #[inline(always)] + pub fn div(&self) -> DIV_R { + DIV_R::new(((self.bits >> 16) & 0x07ff) as u16) + } +} +impl W { + #[doc = "Bits 0:1 - Proportional Integral Filter Selection"] + #[inline(always)] + #[must_use] + pub fn filter(&mut self) -> FILTER_W<0> { + FILTER_W::new(self) + } + #[doc = "Bit 2 - Low-Power Enable"] + #[inline(always)] + #[must_use] + pub fn lpen(&mut self) -> LPEN_W<2> { + LPEN_W::new(self) + } + #[doc = "Bit 3 - Wake Up Fast"] + #[inline(always)] + #[must_use] + pub fn wuf(&mut self) -> WUF_W<3> { + WUF_W::new(self) + } + #[doc = "Bits 4:5 - Reference Clock Selection"] + #[inline(always)] + #[must_use] + pub fn refclk(&mut self) -> REFCLK_W<4> { + REFCLK_W::new(self) + } + #[doc = "Bits 8:10 - Lock Time"] + #[inline(always)] + #[must_use] + pub fn ltime(&mut self) -> LTIME_W<8> { + LTIME_W::new(self) + } + #[doc = "Bit 12 - Lock Bypass"] + #[inline(always)] + #[must_use] + pub fn lbypass(&mut self) -> LBYPASS_W<12> { + LBYPASS_W::new(self) + } + #[doc = "Bits 16:26 - Clock Divider"] + #[inline(always)] + #[must_use] + pub fn div(&mut self) -> DIV_W<16> { + DIV_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Digital Core Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllctrlb](index.html) module"] +pub struct DPLLCTRLB_SPEC; +impl crate::RegisterSpec for DPLLCTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dpllctrlb::R](R) reader structure"] +impl crate::Readable for DPLLCTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dpllctrlb::W](W) writer structure"] +impl crate::Writable for DPLLCTRLB_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DPLLCTRLB to value 0"] +impl crate::Resettable for DPLLCTRLB_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/oscctrl/dpllpresc.rs b/pac/atsaml22j/src/oscctrl/dpllpresc.rs new file mode 100644 index 000000000000..d77373d7f6ac --- /dev/null +++ b/pac/atsaml22j/src/oscctrl/dpllpresc.rs @@ -0,0 +1,142 @@ +#[doc = "Register `DPLLPRESC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DPLLPRESC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PRESC` reader - Output Clock Prescaler"] +pub type PRESC_R = crate::FieldReader; +#[doc = "Output Clock Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum PRESCSELECT_A { + #[doc = "0: DPLL output is divided by 1"] + DIV1 = 0, + #[doc = "1: DPLL output is divided by 2"] + DIV2 = 1, + #[doc = "2: DPLL output is divided by 4"] + DIV4 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCSELECT_A) -> Self { + variant as _ + } +} +impl PRESC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCSELECT_A::DIV1), + 1 => Some(PRESCSELECT_A::DIV2), + 2 => Some(PRESCSELECT_A::DIV4), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + *self == PRESCSELECT_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + *self == PRESCSELECT_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + *self == PRESCSELECT_A::DIV4 + } +} +#[doc = "Field `PRESC` writer - Output Clock Prescaler"] +pub type PRESC_W<'a, const O: u8> = + crate::FieldWriter<'a, u8, DPLLPRESC_SPEC, u8, PRESCSELECT_A, 2, O>; +impl<'a, const O: u8> PRESC_W<'a, O> { + #[doc = "DPLL output is divided by 1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCSELECT_A::DIV1) + } + #[doc = "DPLL output is divided by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCSELECT_A::DIV2) + } + #[doc = "DPLL output is divided by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCSELECT_A::DIV4) + } +} +impl R { + #[doc = "Bits 0:1 - Output Clock Prescaler"] + #[inline(always)] + pub fn presc(&self) -> PRESC_R { + PRESC_R::new(self.bits & 3) + } +} +impl W { + #[doc = "Bits 0:1 - Output Clock Prescaler"] + #[inline(always)] + #[must_use] + pub fn presc(&mut self) -> PRESC_W<0> { + PRESC_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DPLL Prescaler\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllpresc](index.html) module"] +pub struct DPLLPRESC_SPEC; +impl crate::RegisterSpec for DPLLPRESC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dpllpresc::R](R) reader structure"] +impl crate::Readable for DPLLPRESC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dpllpresc::W](W) writer structure"] +impl crate::Writable for DPLLPRESC_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DPLLPRESC to value 0"] +impl crate::Resettable for DPLLPRESC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/oscctrl/dpllratio.rs b/pac/atsaml22j/src/oscctrl/dpllratio.rs new file mode 100644 index 000000000000..a0e48ad3ff9a --- /dev/null +++ b/pac/atsaml22j/src/oscctrl/dpllratio.rs @@ -0,0 +1,95 @@ +#[doc = "Register `DPLLRATIO` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DPLLRATIO` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LDR` reader - Loop Divider Ratio"] +pub type LDR_R = crate::FieldReader; +#[doc = "Field `LDR` writer - Loop Divider Ratio"] +pub type LDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DPLLRATIO_SPEC, u16, u16, 12, O>; +#[doc = "Field `LDRFRAC` reader - Loop Divider Ratio Fractional Part"] +pub type LDRFRAC_R = crate::FieldReader; +#[doc = "Field `LDRFRAC` writer - Loop Divider Ratio Fractional Part"] +pub type LDRFRAC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DPLLRATIO_SPEC, u8, u8, 4, O>; +impl R { + #[doc = "Bits 0:11 - Loop Divider Ratio"] + #[inline(always)] + pub fn ldr(&self) -> LDR_R { + LDR_R::new((self.bits & 0x0fff) as u16) + } + #[doc = "Bits 16:19 - Loop Divider Ratio Fractional Part"] + #[inline(always)] + pub fn ldrfrac(&self) -> LDRFRAC_R { + LDRFRAC_R::new(((self.bits >> 16) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:11 - Loop Divider Ratio"] + #[inline(always)] + #[must_use] + pub fn ldr(&mut self) -> LDR_W<0> { + LDR_W::new(self) + } + #[doc = "Bits 16:19 - Loop Divider Ratio Fractional Part"] + #[inline(always)] + #[must_use] + pub fn ldrfrac(&mut self) -> LDRFRAC_W<16> { + LDRFRAC_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DPLL Ratio Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllratio](index.html) module"] +pub struct DPLLRATIO_SPEC; +impl crate::RegisterSpec for DPLLRATIO_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dpllratio::R](R) reader structure"] +impl crate::Readable for DPLLRATIO_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dpllratio::W](W) writer structure"] +impl crate::Writable for DPLLRATIO_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DPLLRATIO to value 0"] +impl crate::Resettable for DPLLRATIO_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/oscctrl/dpllstatus.rs b/pac/atsaml22j/src/oscctrl/dpllstatus.rs new file mode 100644 index 000000000000..dc03d7e063a7 --- /dev/null +++ b/pac/atsaml22j/src/oscctrl/dpllstatus.rs @@ -0,0 +1,44 @@ +#[doc = "Register `DPLLSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `LOCK` reader - DPLL Lock Status"] +pub type LOCK_R = crate::BitReader; +#[doc = "Field `CLKRDY` reader - DPLL Clock Ready"] +pub type CLKRDY_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - DPLL Lock Status"] + #[inline(always)] + pub fn lock(&self) -> LOCK_R { + LOCK_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - DPLL Clock Ready"] + #[inline(always)] + pub fn clkrdy(&self) -> CLKRDY_R { + CLKRDY_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[doc = "DPLL Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllstatus](index.html) module"] +pub struct DPLLSTATUS_SPEC; +impl crate::RegisterSpec for DPLLSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dpllstatus::R](R) reader structure"] +impl crate::Readable for DPLLSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DPLLSTATUS to value 0"] +impl crate::Resettable for DPLLSTATUS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/oscctrl/dpllsyncbusy.rs b/pac/atsaml22j/src/oscctrl/dpllsyncbusy.rs new file mode 100644 index 000000000000..edb0af9c642f --- /dev/null +++ b/pac/atsaml22j/src/oscctrl/dpllsyncbusy.rs @@ -0,0 +1,51 @@ +#[doc = "Register `DPLLSYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `ENABLE` reader - DPLL Enable Synchronization Status"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `DPLLRATIO` reader - DPLL Ratio Synchronization Status"] +pub type DPLLRATIO_R = crate::BitReader; +#[doc = "Field `DPLLPRESC` reader - DPLL Prescaler Synchronization Status"] +pub type DPLLPRESC_R = crate::BitReader; +impl R { + #[doc = "Bit 1 - DPLL Enable Synchronization Status"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - DPLL Ratio Synchronization Status"] + #[inline(always)] + pub fn dpllratio(&self) -> DPLLRATIO_R { + DPLLRATIO_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - DPLL Prescaler Synchronization Status"] + #[inline(always)] + pub fn dpllpresc(&self) -> DPLLPRESC_R { + DPLLPRESC_R::new(((self.bits >> 3) & 1) != 0) + } +} +#[doc = "DPLL Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dpllsyncbusy](index.html) module"] +pub struct DPLLSYNCBUSY_SPEC; +impl crate::RegisterSpec for DPLLSYNCBUSY_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dpllsyncbusy::R](R) reader structure"] +impl crate::Readable for DPLLSYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DPLLSYNCBUSY to value 0"] +impl crate::Resettable for DPLLSYNCBUSY_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/oscctrl/evctrl.rs b/pac/atsaml22j/src/oscctrl/evctrl.rs new file mode 100644 index 000000000000..0c8a687b8880 --- /dev/null +++ b/pac/atsaml22j/src/oscctrl/evctrl.rs @@ -0,0 +1,80 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CFDEO` reader - Clock Failure Detector Event Output Enable"] +pub type CFDEO_R = crate::BitReader; +#[doc = "Field `CFDEO` writer - Clock Failure Detector Event Output Enable"] +pub type CFDEO_W<'a, const O: u8> = crate::BitWriter<'a, u8, EVCTRL_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Clock Failure Detector Event Output Enable"] + #[inline(always)] + pub fn cfdeo(&self) -> CFDEO_R { + CFDEO_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Clock Failure Detector Event Output Enable"] + #[inline(always)] + #[must_use] + pub fn cfdeo(&mut self) -> CFDEO_W<0> { + CFDEO_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/oscctrl/intenclr.rs b/pac/atsaml22j/src/oscctrl/intenclr.rs new file mode 100644 index 000000000000..3071380b601e --- /dev/null +++ b/pac/atsaml22j/src/oscctrl/intenclr.rs @@ -0,0 +1,245 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSCRDY` reader - XOSC Ready Interrupt Enable"] +pub type XOSCRDY_R = crate::BitReader; +#[doc = "Field `XOSCRDY` writer - XOSC Ready Interrupt Enable"] +pub type XOSCRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>; +#[doc = "Field `XOSCFAIL` reader - XOSC Clock Failure Detector Interrupt Enable"] +pub type XOSCFAIL_R = crate::BitReader; +#[doc = "Field `XOSCFAIL` writer - XOSC Clock Failure Detector Interrupt Enable"] +pub type XOSCFAIL_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>; +#[doc = "Field `OSC16MRDY` reader - OSC16M Ready Interrupt Enable"] +pub type OSC16MRDY_R = crate::BitReader; +#[doc = "Field `OSC16MRDY` writer - OSC16M Ready Interrupt Enable"] +pub type OSC16MRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>; +#[doc = "Field `DFLLRDY` reader - DFLL Ready Interrupt Enable"] +pub type DFLLRDY_R = crate::BitReader; +#[doc = "Field `DFLLRDY` writer - DFLL Ready Interrupt Enable"] +pub type DFLLRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>; +#[doc = "Field `DFLLOOB` reader - DFLL Out Of Bounds Interrupt Enable"] +pub type DFLLOOB_R = crate::BitReader; +#[doc = "Field `DFLLOOB` writer - DFLL Out Of Bounds Interrupt Enable"] +pub type DFLLOOB_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>; +#[doc = "Field `DFLLLCKF` reader - DFLL Lock Fine Interrupt Enable"] +pub type DFLLLCKF_R = crate::BitReader; +#[doc = "Field `DFLLLCKF` writer - DFLL Lock Fine Interrupt Enable"] +pub type DFLLLCKF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>; +#[doc = "Field `DFLLLCKC` reader - DFLL Lock Coarse Interrupt Enable"] +pub type DFLLLCKC_R = crate::BitReader; +#[doc = "Field `DFLLLCKC` writer - DFLL Lock Coarse Interrupt Enable"] +pub type DFLLLCKC_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>; +#[doc = "Field `DFLLRCS` reader - DFLL Reference Clock Stopped Interrupt Enable"] +pub type DFLLRCS_R = crate::BitReader; +#[doc = "Field `DFLLRCS` writer - DFLL Reference Clock Stopped Interrupt Enable"] +pub type DFLLRCS_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>; +#[doc = "Field `DPLLLCKR` reader - DPLL Lock Rise Interrupt Enable"] +pub type DPLLLCKR_R = crate::BitReader; +#[doc = "Field `DPLLLCKR` writer - DPLL Lock Rise Interrupt Enable"] +pub type DPLLLCKR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>; +#[doc = "Field `DPLLLCKF` reader - DPLL Lock Fall Interrupt Enable"] +pub type DPLLLCKF_R = crate::BitReader; +#[doc = "Field `DPLLLCKF` writer - DPLL Lock Fall Interrupt Enable"] +pub type DPLLLCKF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>; +#[doc = "Field `DPLLLTO` reader - DPLL Time Out Interrupt Enable"] +pub type DPLLLTO_R = crate::BitReader; +#[doc = "Field `DPLLLTO` writer - DPLL Time Out Interrupt Enable"] +pub type DPLLLTO_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>; +#[doc = "Field `DPLLLDRTO` reader - DPLL Ratio Ready Interrupt Enable"] +pub type DPLLLDRTO_R = crate::BitReader; +#[doc = "Field `DPLLLDRTO` writer - DPLL Ratio Ready Interrupt Enable"] +pub type DPLLLDRTO_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - XOSC Ready Interrupt Enable"] + #[inline(always)] + pub fn xoscrdy(&self) -> XOSCRDY_R { + XOSCRDY_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - XOSC Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn xoscfail(&self) -> XOSCFAIL_R { + XOSCFAIL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 4 - OSC16M Ready Interrupt Enable"] + #[inline(always)] + pub fn osc16mrdy(&self) -> OSC16MRDY_R { + OSC16MRDY_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 8 - DFLL Ready Interrupt Enable"] + #[inline(always)] + pub fn dfllrdy(&self) -> DFLLRDY_R { + DFLLRDY_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - DFLL Out Of Bounds Interrupt Enable"] + #[inline(always)] + pub fn dflloob(&self) -> DFLLOOB_R { + DFLLOOB_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - DFLL Lock Fine Interrupt Enable"] + #[inline(always)] + pub fn dflllckf(&self) -> DFLLLCKF_R { + DFLLLCKF_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - DFLL Lock Coarse Interrupt Enable"] + #[inline(always)] + pub fn dflllckc(&self) -> DFLLLCKC_R { + DFLLLCKC_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - DFLL Reference Clock Stopped Interrupt Enable"] + #[inline(always)] + pub fn dfllrcs(&self) -> DFLLRCS_R { + DFLLRCS_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 16 - DPLL Lock Rise Interrupt Enable"] + #[inline(always)] + pub fn dplllckr(&self) -> DPLLLCKR_R { + DPLLLCKR_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - DPLL Lock Fall Interrupt Enable"] + #[inline(always)] + pub fn dplllckf(&self) -> DPLLLCKF_R { + DPLLLCKF_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - DPLL Time Out Interrupt Enable"] + #[inline(always)] + pub fn dplllto(&self) -> DPLLLTO_R { + DPLLLTO_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - DPLL Ratio Ready Interrupt Enable"] + #[inline(always)] + pub fn dpllldrto(&self) -> DPLLLDRTO_R { + DPLLLDRTO_R::new(((self.bits >> 19) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC Ready Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn xoscrdy(&mut self) -> XOSCRDY_W<0> { + XOSCRDY_W::new(self) + } + #[doc = "Bit 1 - XOSC Clock Failure Detector Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn xoscfail(&mut self) -> XOSCFAIL_W<1> { + XOSCFAIL_W::new(self) + } + #[doc = "Bit 4 - OSC16M Ready Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn osc16mrdy(&mut self) -> OSC16MRDY_W<4> { + OSC16MRDY_W::new(self) + } + #[doc = "Bit 8 - DFLL Ready Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn dfllrdy(&mut self) -> DFLLRDY_W<8> { + DFLLRDY_W::new(self) + } + #[doc = "Bit 9 - DFLL Out Of Bounds Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn dflloob(&mut self) -> DFLLOOB_W<9> { + DFLLOOB_W::new(self) + } + #[doc = "Bit 10 - DFLL Lock Fine Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn dflllckf(&mut self) -> DFLLLCKF_W<10> { + DFLLLCKF_W::new(self) + } + #[doc = "Bit 11 - DFLL Lock Coarse Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn dflllckc(&mut self) -> DFLLLCKC_W<11> { + DFLLLCKC_W::new(self) + } + #[doc = "Bit 12 - DFLL Reference Clock Stopped Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn dfllrcs(&mut self) -> DFLLRCS_W<12> { + DFLLRCS_W::new(self) + } + #[doc = "Bit 16 - DPLL Lock Rise Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn dplllckr(&mut self) -> DPLLLCKR_W<16> { + DPLLLCKR_W::new(self) + } + #[doc = "Bit 17 - DPLL Lock Fall Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn dplllckf(&mut self) -> DPLLLCKF_W<17> { + DPLLLCKF_W::new(self) + } + #[doc = "Bit 18 - DPLL Time Out Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn dplllto(&mut self) -> DPLLLTO_W<18> { + DPLLLTO_W::new(self) + } + #[doc = "Bit 19 - DPLL Ratio Ready Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn dpllldrto(&mut self) -> DPLLLDRTO_W<19> { + DPLLLDRTO_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/oscctrl/intenset.rs b/pac/atsaml22j/src/oscctrl/intenset.rs new file mode 100644 index 000000000000..bec614fea253 --- /dev/null +++ b/pac/atsaml22j/src/oscctrl/intenset.rs @@ -0,0 +1,245 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSCRDY` reader - XOSC Ready Interrupt Enable"] +pub type XOSCRDY_R = crate::BitReader; +#[doc = "Field `XOSCRDY` writer - XOSC Ready Interrupt Enable"] +pub type XOSCRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>; +#[doc = "Field `XOSCFAIL` reader - XOSC Clock Failure Detector Interrupt Enable"] +pub type XOSCFAIL_R = crate::BitReader; +#[doc = "Field `XOSCFAIL` writer - XOSC Clock Failure Detector Interrupt Enable"] +pub type XOSCFAIL_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>; +#[doc = "Field `OSC16MRDY` reader - OSC16M Ready Interrupt Enable"] +pub type OSC16MRDY_R = crate::BitReader; +#[doc = "Field `OSC16MRDY` writer - OSC16M Ready Interrupt Enable"] +pub type OSC16MRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>; +#[doc = "Field `DFLLRDY` reader - DFLL Ready Interrupt Enable"] +pub type DFLLRDY_R = crate::BitReader; +#[doc = "Field `DFLLRDY` writer - DFLL Ready Interrupt Enable"] +pub type DFLLRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>; +#[doc = "Field `DFLLOOB` reader - DFLL Out Of Bounds Interrupt Enable"] +pub type DFLLOOB_R = crate::BitReader; +#[doc = "Field `DFLLOOB` writer - DFLL Out Of Bounds Interrupt Enable"] +pub type DFLLOOB_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>; +#[doc = "Field `DFLLLCKF` reader - DFLL Lock Fine Interrupt Enable"] +pub type DFLLLCKF_R = crate::BitReader; +#[doc = "Field `DFLLLCKF` writer - DFLL Lock Fine Interrupt Enable"] +pub type DFLLLCKF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>; +#[doc = "Field `DFLLLCKC` reader - DFLL Lock Coarse Interrupt Enable"] +pub type DFLLLCKC_R = crate::BitReader; +#[doc = "Field `DFLLLCKC` writer - DFLL Lock Coarse Interrupt Enable"] +pub type DFLLLCKC_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>; +#[doc = "Field `DFLLRCS` reader - DFLL Reference Clock Stopped Interrupt Enable"] +pub type DFLLRCS_R = crate::BitReader; +#[doc = "Field `DFLLRCS` writer - DFLL Reference Clock Stopped Interrupt Enable"] +pub type DFLLRCS_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>; +#[doc = "Field `DPLLLCKR` reader - DPLL Lock Rise Interrupt Enable"] +pub type DPLLLCKR_R = crate::BitReader; +#[doc = "Field `DPLLLCKR` writer - DPLL Lock Rise Interrupt Enable"] +pub type DPLLLCKR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>; +#[doc = "Field `DPLLLCKF` reader - DPLL Lock Fall Interrupt Enable"] +pub type DPLLLCKF_R = crate::BitReader; +#[doc = "Field `DPLLLCKF` writer - DPLL Lock Fall Interrupt Enable"] +pub type DPLLLCKF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>; +#[doc = "Field `DPLLLTO` reader - DPLL Time Out Interrupt Enable"] +pub type DPLLLTO_R = crate::BitReader; +#[doc = "Field `DPLLLTO` writer - DPLL Time Out Interrupt Enable"] +pub type DPLLLTO_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>; +#[doc = "Field `DPLLLDRTO` reader - DPLL Ratio Ready Interrupt Enable"] +pub type DPLLLDRTO_R = crate::BitReader; +#[doc = "Field `DPLLLDRTO` writer - DPLL Ratio Ready Interrupt Enable"] +pub type DPLLLDRTO_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - XOSC Ready Interrupt Enable"] + #[inline(always)] + pub fn xoscrdy(&self) -> XOSCRDY_R { + XOSCRDY_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - XOSC Clock Failure Detector Interrupt Enable"] + #[inline(always)] + pub fn xoscfail(&self) -> XOSCFAIL_R { + XOSCFAIL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 4 - OSC16M Ready Interrupt Enable"] + #[inline(always)] + pub fn osc16mrdy(&self) -> OSC16MRDY_R { + OSC16MRDY_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 8 - DFLL Ready Interrupt Enable"] + #[inline(always)] + pub fn dfllrdy(&self) -> DFLLRDY_R { + DFLLRDY_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - DFLL Out Of Bounds Interrupt Enable"] + #[inline(always)] + pub fn dflloob(&self) -> DFLLOOB_R { + DFLLOOB_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - DFLL Lock Fine Interrupt Enable"] + #[inline(always)] + pub fn dflllckf(&self) -> DFLLLCKF_R { + DFLLLCKF_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - DFLL Lock Coarse Interrupt Enable"] + #[inline(always)] + pub fn dflllckc(&self) -> DFLLLCKC_R { + DFLLLCKC_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - DFLL Reference Clock Stopped Interrupt Enable"] + #[inline(always)] + pub fn dfllrcs(&self) -> DFLLRCS_R { + DFLLRCS_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 16 - DPLL Lock Rise Interrupt Enable"] + #[inline(always)] + pub fn dplllckr(&self) -> DPLLLCKR_R { + DPLLLCKR_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - DPLL Lock Fall Interrupt Enable"] + #[inline(always)] + pub fn dplllckf(&self) -> DPLLLCKF_R { + DPLLLCKF_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - DPLL Time Out Interrupt Enable"] + #[inline(always)] + pub fn dplllto(&self) -> DPLLLTO_R { + DPLLLTO_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - DPLL Ratio Ready Interrupt Enable"] + #[inline(always)] + pub fn dpllldrto(&self) -> DPLLLDRTO_R { + DPLLLDRTO_R::new(((self.bits >> 19) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC Ready Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn xoscrdy(&mut self) -> XOSCRDY_W<0> { + XOSCRDY_W::new(self) + } + #[doc = "Bit 1 - XOSC Clock Failure Detector Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn xoscfail(&mut self) -> XOSCFAIL_W<1> { + XOSCFAIL_W::new(self) + } + #[doc = "Bit 4 - OSC16M Ready Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn osc16mrdy(&mut self) -> OSC16MRDY_W<4> { + OSC16MRDY_W::new(self) + } + #[doc = "Bit 8 - DFLL Ready Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn dfllrdy(&mut self) -> DFLLRDY_W<8> { + DFLLRDY_W::new(self) + } + #[doc = "Bit 9 - DFLL Out Of Bounds Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn dflloob(&mut self) -> DFLLOOB_W<9> { + DFLLOOB_W::new(self) + } + #[doc = "Bit 10 - DFLL Lock Fine Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn dflllckf(&mut self) -> DFLLLCKF_W<10> { + DFLLLCKF_W::new(self) + } + #[doc = "Bit 11 - DFLL Lock Coarse Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn dflllckc(&mut self) -> DFLLLCKC_W<11> { + DFLLLCKC_W::new(self) + } + #[doc = "Bit 12 - DFLL Reference Clock Stopped Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn dfllrcs(&mut self) -> DFLLRCS_W<12> { + DFLLRCS_W::new(self) + } + #[doc = "Bit 16 - DPLL Lock Rise Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn dplllckr(&mut self) -> DPLLLCKR_W<16> { + DPLLLCKR_W::new(self) + } + #[doc = "Bit 17 - DPLL Lock Fall Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn dplllckf(&mut self) -> DPLLLCKF_W<17> { + DPLLLCKF_W::new(self) + } + #[doc = "Bit 18 - DPLL Time Out Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn dplllto(&mut self) -> DPLLLTO_W<18> { + DPLLLTO_W::new(self) + } + #[doc = "Bit 19 - DPLL Ratio Ready Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn dpllldrto(&mut self) -> DPLLLDRTO_W<19> { + DPLLLDRTO_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/oscctrl/intflag.rs b/pac/atsaml22j/src/oscctrl/intflag.rs new file mode 100644 index 000000000000..5fd6c49ba00b --- /dev/null +++ b/pac/atsaml22j/src/oscctrl/intflag.rs @@ -0,0 +1,245 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `XOSCRDY` reader - XOSC Ready"] +pub type XOSCRDY_R = crate::BitReader; +#[doc = "Field `XOSCRDY` writer - XOSC Ready"] +pub type XOSCRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAG_SPEC, bool, O>; +#[doc = "Field `XOSCFAIL` reader - XOSC Clock Failure Detector"] +pub type XOSCFAIL_R = crate::BitReader; +#[doc = "Field `XOSCFAIL` writer - XOSC Clock Failure Detector"] +pub type XOSCFAIL_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAG_SPEC, bool, O>; +#[doc = "Field `OSC16MRDY` reader - OSC16M Ready"] +pub type OSC16MRDY_R = crate::BitReader; +#[doc = "Field `OSC16MRDY` writer - OSC16M Ready"] +pub type OSC16MRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAG_SPEC, bool, O>; +#[doc = "Field `DFLLRDY` reader - DFLL Ready"] +pub type DFLLRDY_R = crate::BitReader; +#[doc = "Field `DFLLRDY` writer - DFLL Ready"] +pub type DFLLRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAG_SPEC, bool, O>; +#[doc = "Field `DFLLOOB` reader - DFLL Out Of Bounds"] +pub type DFLLOOB_R = crate::BitReader; +#[doc = "Field `DFLLOOB` writer - DFLL Out Of Bounds"] +pub type DFLLOOB_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAG_SPEC, bool, O>; +#[doc = "Field `DFLLLCKF` reader - DFLL Lock Fine"] +pub type DFLLLCKF_R = crate::BitReader; +#[doc = "Field `DFLLLCKF` writer - DFLL Lock Fine"] +pub type DFLLLCKF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAG_SPEC, bool, O>; +#[doc = "Field `DFLLLCKC` reader - DFLL Lock Coarse"] +pub type DFLLLCKC_R = crate::BitReader; +#[doc = "Field `DFLLLCKC` writer - DFLL Lock Coarse"] +pub type DFLLLCKC_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAG_SPEC, bool, O>; +#[doc = "Field `DFLLRCS` reader - DFLL Reference Clock Stopped"] +pub type DFLLRCS_R = crate::BitReader; +#[doc = "Field `DFLLRCS` writer - DFLL Reference Clock Stopped"] +pub type DFLLRCS_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAG_SPEC, bool, O>; +#[doc = "Field `DPLLLCKR` reader - DPLL Lock Rise"] +pub type DPLLLCKR_R = crate::BitReader; +#[doc = "Field `DPLLLCKR` writer - DPLL Lock Rise"] +pub type DPLLLCKR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAG_SPEC, bool, O>; +#[doc = "Field `DPLLLCKF` reader - DPLL Lock Fall"] +pub type DPLLLCKF_R = crate::BitReader; +#[doc = "Field `DPLLLCKF` writer - DPLL Lock Fall"] +pub type DPLLLCKF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAG_SPEC, bool, O>; +#[doc = "Field `DPLLLTO` reader - DPLL Timeout"] +pub type DPLLLTO_R = crate::BitReader; +#[doc = "Field `DPLLLTO` writer - DPLL Timeout"] +pub type DPLLLTO_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAG_SPEC, bool, O>; +#[doc = "Field `DPLLLDRTO` reader - DPLL Ratio Ready"] +pub type DPLLLDRTO_R = crate::BitReader; +#[doc = "Field `DPLLLDRTO` writer - DPLL Ratio Ready"] +pub type DPLLLDRTO_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAG_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - XOSC Ready"] + #[inline(always)] + pub fn xoscrdy(&self) -> XOSCRDY_R { + XOSCRDY_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - XOSC Clock Failure Detector"] + #[inline(always)] + pub fn xoscfail(&self) -> XOSCFAIL_R { + XOSCFAIL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 4 - OSC16M Ready"] + #[inline(always)] + pub fn osc16mrdy(&self) -> OSC16MRDY_R { + OSC16MRDY_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 8 - DFLL Ready"] + #[inline(always)] + pub fn dfllrdy(&self) -> DFLLRDY_R { + DFLLRDY_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - DFLL Out Of Bounds"] + #[inline(always)] + pub fn dflloob(&self) -> DFLLOOB_R { + DFLLOOB_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - DFLL Lock Fine"] + #[inline(always)] + pub fn dflllckf(&self) -> DFLLLCKF_R { + DFLLLCKF_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - DFLL Lock Coarse"] + #[inline(always)] + pub fn dflllckc(&self) -> DFLLLCKC_R { + DFLLLCKC_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - DFLL Reference Clock Stopped"] + #[inline(always)] + pub fn dfllrcs(&self) -> DFLLRCS_R { + DFLLRCS_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 16 - DPLL Lock Rise"] + #[inline(always)] + pub fn dplllckr(&self) -> DPLLLCKR_R { + DPLLLCKR_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - DPLL Lock Fall"] + #[inline(always)] + pub fn dplllckf(&self) -> DPLLLCKF_R { + DPLLLCKF_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - DPLL Timeout"] + #[inline(always)] + pub fn dplllto(&self) -> DPLLLTO_R { + DPLLLTO_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - DPLL Ratio Ready"] + #[inline(always)] + pub fn dpllldrto(&self) -> DPLLLDRTO_R { + DPLLLDRTO_R::new(((self.bits >> 19) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - XOSC Ready"] + #[inline(always)] + #[must_use] + pub fn xoscrdy(&mut self) -> XOSCRDY_W<0> { + XOSCRDY_W::new(self) + } + #[doc = "Bit 1 - XOSC Clock Failure Detector"] + #[inline(always)] + #[must_use] + pub fn xoscfail(&mut self) -> XOSCFAIL_W<1> { + XOSCFAIL_W::new(self) + } + #[doc = "Bit 4 - OSC16M Ready"] + #[inline(always)] + #[must_use] + pub fn osc16mrdy(&mut self) -> OSC16MRDY_W<4> { + OSC16MRDY_W::new(self) + } + #[doc = "Bit 8 - DFLL Ready"] + #[inline(always)] + #[must_use] + pub fn dfllrdy(&mut self) -> DFLLRDY_W<8> { + DFLLRDY_W::new(self) + } + #[doc = "Bit 9 - DFLL Out Of Bounds"] + #[inline(always)] + #[must_use] + pub fn dflloob(&mut self) -> DFLLOOB_W<9> { + DFLLOOB_W::new(self) + } + #[doc = "Bit 10 - DFLL Lock Fine"] + #[inline(always)] + #[must_use] + pub fn dflllckf(&mut self) -> DFLLLCKF_W<10> { + DFLLLCKF_W::new(self) + } + #[doc = "Bit 11 - DFLL Lock Coarse"] + #[inline(always)] + #[must_use] + pub fn dflllckc(&mut self) -> DFLLLCKC_W<11> { + DFLLLCKC_W::new(self) + } + #[doc = "Bit 12 - DFLL Reference Clock Stopped"] + #[inline(always)] + #[must_use] + pub fn dfllrcs(&mut self) -> DFLLRCS_W<12> { + DFLLRCS_W::new(self) + } + #[doc = "Bit 16 - DPLL Lock Rise"] + #[inline(always)] + #[must_use] + pub fn dplllckr(&mut self) -> DPLLLCKR_W<16> { + DPLLLCKR_W::new(self) + } + #[doc = "Bit 17 - DPLL Lock Fall"] + #[inline(always)] + #[must_use] + pub fn dplllckf(&mut self) -> DPLLLCKF_W<17> { + DPLLLCKF_W::new(self) + } + #[doc = "Bit 18 - DPLL Timeout"] + #[inline(always)] + #[must_use] + pub fn dplllto(&mut self) -> DPLLLTO_W<18> { + DPLLLTO_W::new(self) + } + #[doc = "Bit 19 - DPLL Ratio Ready"] + #[inline(always)] + #[must_use] + pub fn dpllldrto(&mut self) -> DPLLLDRTO_W<19> { + DPLLLDRTO_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/oscctrl/osc16mctrl.rs b/pac/atsaml22j/src/oscctrl/osc16mctrl.rs new file mode 100644 index 000000000000..d2f5cdc62814 --- /dev/null +++ b/pac/atsaml22j/src/oscctrl/osc16mctrl.rs @@ -0,0 +1,200 @@ +#[doc = "Register `OSC16MCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OSC16MCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Oscillator Enable"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - Oscillator Enable"] +pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u8, OSC16MCTRL_SPEC, bool, O>; +#[doc = "Field `FSEL` reader - Oscillator Frequency Select"] +pub type FSEL_R = crate::FieldReader; +#[doc = "Oscillator Frequency Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSELSELECT_A { + #[doc = "0: 4MHz"] + _4 = 0, + #[doc = "1: 8MHz"] + _8 = 1, + #[doc = "2: 12MHz"] + _12 = 2, + #[doc = "3: 16MHz"] + _16 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSELSELECT_A) -> Self { + variant as _ + } +} +impl FSEL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> FSELSELECT_A { + match self.bits { + 0 => FSELSELECT_A::_4, + 1 => FSELSELECT_A::_8, + 2 => FSELSELECT_A::_12, + 3 => FSELSELECT_A::_16, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `_4`"] + #[inline(always)] + pub fn is_4(&self) -> bool { + *self == FSELSELECT_A::_4 + } + #[doc = "Checks if the value of the field is `_8`"] + #[inline(always)] + pub fn is_8(&self) -> bool { + *self == FSELSELECT_A::_8 + } + #[doc = "Checks if the value of the field is `_12`"] + #[inline(always)] + pub fn is_12(&self) -> bool { + *self == FSELSELECT_A::_12 + } + #[doc = "Checks if the value of the field is `_16`"] + #[inline(always)] + pub fn is_16(&self) -> bool { + *self == FSELSELECT_A::_16 + } +} +#[doc = "Field `FSEL` writer - Oscillator Frequency Select"] +pub type FSEL_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u8, OSC16MCTRL_SPEC, u8, FSELSELECT_A, 2, O>; +impl<'a, const O: u8> FSEL_W<'a, O> { + #[doc = "4MHz"] + #[inline(always)] + pub fn _4(self) -> &'a mut W { + self.variant(FSELSELECT_A::_4) + } + #[doc = "8MHz"] + #[inline(always)] + pub fn _8(self) -> &'a mut W { + self.variant(FSELSELECT_A::_8) + } + #[doc = "12MHz"] + #[inline(always)] + pub fn _12(self) -> &'a mut W { + self.variant(FSELSELECT_A::_12) + } + #[doc = "16MHz"] + #[inline(always)] + pub fn _16(self) -> &'a mut W { + self.variant(FSELSELECT_A::_16) + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub type RUNSTDBY_R = crate::BitReader; +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub type RUNSTDBY_W<'a, const O: u8> = crate::BitWriter<'a, u8, OSC16MCTRL_SPEC, bool, O>; +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub type ONDEMAND_R = crate::BitReader; +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub type ONDEMAND_W<'a, const O: u8> = crate::BitWriter<'a, u8, OSC16MCTRL_SPEC, bool, O>; +impl R { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:3 - Oscillator Frequency Select"] + #[inline(always)] + pub fn fsel(&self) -> FSEL_R { + FSEL_R::new((self.bits >> 2) & 3) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W<1> { + ENABLE_W::new(self) + } + #[doc = "Bits 2:3 - Oscillator Frequency Select"] + #[inline(always)] + #[must_use] + pub fn fsel(&mut self) -> FSEL_W<2> { + FSEL_W::new(self) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + #[must_use] + pub fn runstdby(&mut self) -> RUNSTDBY_W<6> { + RUNSTDBY_W::new(self) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + #[must_use] + pub fn ondemand(&mut self) -> ONDEMAND_W<7> { + ONDEMAND_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "16MHz Internal Oscillator (OSC16M) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [osc16mctrl](index.html) module"] +pub struct OSC16MCTRL_SPEC; +impl crate::RegisterSpec for OSC16MCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [osc16mctrl::R](R) reader structure"] +impl crate::Readable for OSC16MCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [osc16mctrl::W](W) writer structure"] +impl crate::Writable for OSC16MCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OSC16MCTRL to value 0x82"] +impl crate::Resettable for OSC16MCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x82; +} diff --git a/pac/atsaml22j/src/oscctrl/status.rs b/pac/atsaml22j/src/oscctrl/status.rs new file mode 100644 index 000000000000..50c51204dd05 --- /dev/null +++ b/pac/atsaml22j/src/oscctrl/status.rs @@ -0,0 +1,121 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `XOSCRDY` reader - XOSC Ready"] +pub type XOSCRDY_R = crate::BitReader; +#[doc = "Field `XOSCFAIL` reader - XOSC Clock Failure Detector"] +pub type XOSCFAIL_R = crate::BitReader; +#[doc = "Field `XOSCCKSW` reader - XOSC Clock Switch"] +pub type XOSCCKSW_R = crate::BitReader; +#[doc = "Field `OSC16MRDY` reader - OSC16M Ready"] +pub type OSC16MRDY_R = crate::BitReader; +#[doc = "Field `DFLLRDY` reader - DFLL Ready"] +pub type DFLLRDY_R = crate::BitReader; +#[doc = "Field `DFLLOOB` reader - DFLL Out Of Bounds"] +pub type DFLLOOB_R = crate::BitReader; +#[doc = "Field `DFLLLCKF` reader - DFLL Lock Fine"] +pub type DFLLLCKF_R = crate::BitReader; +#[doc = "Field `DFLLLCKC` reader - DFLL Lock Coarse"] +pub type DFLLLCKC_R = crate::BitReader; +#[doc = "Field `DFLLRCS` reader - DFLL Reference Clock Stopped"] +pub type DFLLRCS_R = crate::BitReader; +#[doc = "Field `DPLLLCKR` reader - DPLL Lock Rise"] +pub type DPLLLCKR_R = crate::BitReader; +#[doc = "Field `DPLLLCKF` reader - DPLL Lock Fall"] +pub type DPLLLCKF_R = crate::BitReader; +#[doc = "Field `DPLLTO` reader - DPLL Timeout"] +pub type DPLLTO_R = crate::BitReader; +#[doc = "Field `DPLLLDRTO` reader - DPLL Ratio Ready"] +pub type DPLLLDRTO_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - XOSC Ready"] + #[inline(always)] + pub fn xoscrdy(&self) -> XOSCRDY_R { + XOSCRDY_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - XOSC Clock Failure Detector"] + #[inline(always)] + pub fn xoscfail(&self) -> XOSCFAIL_R { + XOSCFAIL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - XOSC Clock Switch"] + #[inline(always)] + pub fn xosccksw(&self) -> XOSCCKSW_R { + XOSCCKSW_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - OSC16M Ready"] + #[inline(always)] + pub fn osc16mrdy(&self) -> OSC16MRDY_R { + OSC16MRDY_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 8 - DFLL Ready"] + #[inline(always)] + pub fn dfllrdy(&self) -> DFLLRDY_R { + DFLLRDY_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - DFLL Out Of Bounds"] + #[inline(always)] + pub fn dflloob(&self) -> DFLLOOB_R { + DFLLOOB_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - DFLL Lock Fine"] + #[inline(always)] + pub fn dflllckf(&self) -> DFLLLCKF_R { + DFLLLCKF_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - DFLL Lock Coarse"] + #[inline(always)] + pub fn dflllckc(&self) -> DFLLLCKC_R { + DFLLLCKC_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - DFLL Reference Clock Stopped"] + #[inline(always)] + pub fn dfllrcs(&self) -> DFLLRCS_R { + DFLLRCS_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 16 - DPLL Lock Rise"] + #[inline(always)] + pub fn dplllckr(&self) -> DPLLLCKR_R { + DPLLLCKR_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - DPLL Lock Fall"] + #[inline(always)] + pub fn dplllckf(&self) -> DPLLLCKF_R { + DPLLLCKF_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - DPLL Timeout"] + #[inline(always)] + pub fn dpllto(&self) -> DPLLTO_R { + DPLLTO_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - DPLL Ratio Ready"] + #[inline(always)] + pub fn dpllldrto(&self) -> DPLLLDRTO_R { + DPLLLDRTO_R::new(((self.bits >> 19) & 1) != 0) + } +} +#[doc = "Power and Clocks Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/oscctrl/xoscctrl.rs b/pac/atsaml22j/src/oscctrl/xoscctrl.rs new file mode 100644 index 000000000000..10e31e4e3abd --- /dev/null +++ b/pac/atsaml22j/src/oscctrl/xoscctrl.rs @@ -0,0 +1,200 @@ +#[doc = "Register `XOSCCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `XOSCCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Oscillator Enable"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - Oscillator Enable"] +pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u16, XOSCCTRL_SPEC, bool, O>; +#[doc = "Field `XTALEN` reader - Crystal Oscillator Enable"] +pub type XTALEN_R = crate::BitReader; +#[doc = "Field `XTALEN` writer - Crystal Oscillator Enable"] +pub type XTALEN_W<'a, const O: u8> = crate::BitWriter<'a, u16, XOSCCTRL_SPEC, bool, O>; +#[doc = "Field `CFDEN` reader - Xosc Clock Failure Detecteor Enable"] +pub type CFDEN_R = crate::BitReader; +#[doc = "Field `CFDEN` writer - Xosc Clock Failure Detecteor Enable"] +pub type CFDEN_W<'a, const O: u8> = crate::BitWriter<'a, u16, XOSCCTRL_SPEC, bool, O>; +#[doc = "Field `SWBEN` reader - Xosc Clock Switch Enable"] +pub type SWBEN_R = crate::BitReader; +#[doc = "Field `SWBEN` writer - Xosc Clock Switch Enable"] +pub type SWBEN_W<'a, const O: u8> = crate::BitWriter<'a, u16, XOSCCTRL_SPEC, bool, O>; +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub type RUNSTDBY_R = crate::BitReader; +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub type RUNSTDBY_W<'a, const O: u8> = crate::BitWriter<'a, u16, XOSCCTRL_SPEC, bool, O>; +#[doc = "Field `ONDEMAND` reader - On Demand Control"] +pub type ONDEMAND_R = crate::BitReader; +#[doc = "Field `ONDEMAND` writer - On Demand Control"] +pub type ONDEMAND_W<'a, const O: u8> = crate::BitWriter<'a, u16, XOSCCTRL_SPEC, bool, O>; +#[doc = "Field `GAIN` reader - Oscillator Gain"] +pub type GAIN_R = crate::FieldReader; +#[doc = "Field `GAIN` writer - Oscillator Gain"] +pub type GAIN_W<'a, const O: u8> = crate::FieldWriter<'a, u16, XOSCCTRL_SPEC, u8, u8, 3, O>; +#[doc = "Field `AMPGC` reader - Automatic Amplitude Gain Control"] +pub type AMPGC_R = crate::BitReader; +#[doc = "Field `AMPGC` writer - Automatic Amplitude Gain Control"] +pub type AMPGC_W<'a, const O: u8> = crate::BitWriter<'a, u16, XOSCCTRL_SPEC, bool, O>; +#[doc = "Field `STARTUP` reader - Start-Up Time"] +pub type STARTUP_R = crate::FieldReader; +#[doc = "Field `STARTUP` writer - Start-Up Time"] +pub type STARTUP_W<'a, const O: u8> = crate::FieldWriter<'a, u16, XOSCCTRL_SPEC, u8, u8, 4, O>; +impl R { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Crystal Oscillator Enable"] + #[inline(always)] + pub fn xtalen(&self) -> XTALEN_R { + XTALEN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Xosc Clock Failure Detecteor Enable"] + #[inline(always)] + pub fn cfden(&self) -> CFDEN_R { + CFDEN_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Xosc Clock Switch Enable"] + #[inline(always)] + pub fn swben(&self) -> SWBEN_R { + SWBEN_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:10 - Oscillator Gain"] + #[inline(always)] + pub fn gain(&self) -> GAIN_R { + GAIN_R::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 11 - Automatic Amplitude Gain Control"] + #[inline(always)] + pub fn ampgc(&self) -> AMPGC_R { + AMPGC_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 12:15 - Start-Up Time"] + #[inline(always)] + pub fn startup(&self) -> STARTUP_R { + STARTUP_R::new(((self.bits >> 12) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 1 - Oscillator Enable"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W<1> { + ENABLE_W::new(self) + } + #[doc = "Bit 2 - Crystal Oscillator Enable"] + #[inline(always)] + #[must_use] + pub fn xtalen(&mut self) -> XTALEN_W<2> { + XTALEN_W::new(self) + } + #[doc = "Bit 3 - Xosc Clock Failure Detecteor Enable"] + #[inline(always)] + #[must_use] + pub fn cfden(&mut self) -> CFDEN_W<3> { + CFDEN_W::new(self) + } + #[doc = "Bit 4 - Xosc Clock Switch Enable"] + #[inline(always)] + #[must_use] + pub fn swben(&mut self) -> SWBEN_W<4> { + SWBEN_W::new(self) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + #[must_use] + pub fn runstdby(&mut self) -> RUNSTDBY_W<6> { + RUNSTDBY_W::new(self) + } + #[doc = "Bit 7 - On Demand Control"] + #[inline(always)] + #[must_use] + pub fn ondemand(&mut self) -> ONDEMAND_W<7> { + ONDEMAND_W::new(self) + } + #[doc = "Bits 8:10 - Oscillator Gain"] + #[inline(always)] + #[must_use] + pub fn gain(&mut self) -> GAIN_W<8> { + GAIN_W::new(self) + } + #[doc = "Bit 11 - Automatic Amplitude Gain Control"] + #[inline(always)] + #[must_use] + pub fn ampgc(&mut self) -> AMPGC_W<11> { + AMPGC_W::new(self) + } + #[doc = "Bits 12:15 - Start-Up Time"] + #[inline(always)] + #[must_use] + pub fn startup(&mut self) -> STARTUP_W<12> { + STARTUP_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "External Multipurpose Crystal Oscillator (XOSC) Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [xoscctrl](index.html) module"] +pub struct XOSCCTRL_SPEC; +impl crate::RegisterSpec for XOSCCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [xoscctrl::R](R) reader structure"] +impl crate::Readable for XOSCCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [xoscctrl::W](W) writer structure"] +impl crate::Writable for XOSCCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets XOSCCTRL to value 0x80"] +impl crate::Resettable for XOSCCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x80; +} diff --git a/pac/atsaml22j/src/pac.rs b/pac/atsaml22j/src/pac.rs new file mode 100644 index 000000000000..f9304cf9a19c --- /dev/null +++ b/pac/atsaml22j/src/pac.rs @@ -0,0 +1,73 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Write control"] + pub wrctrl: WRCTRL, + #[doc = "0x04 - Event control"] + pub evctrl: EVCTRL, + _reserved2: [u8; 0x03], + #[doc = "0x08 - Interrupt enable clear"] + pub intenclr: INTENCLR, + #[doc = "0x09 - Interrupt enable set"] + pub intenset: INTENSET, + _reserved4: [u8; 0x06], + #[doc = "0x10 - Bridge interrupt flag status"] + pub intflagahb: INTFLAGAHB, + #[doc = "0x14 - Peripheral interrupt flag status - Bridge A"] + pub intflaga: INTFLAGA, + #[doc = "0x18 - Peripheral interrupt flag status - Bridge B"] + pub intflagb: INTFLAGB, + #[doc = "0x1c - Peripheral interrupt flag status - Bridge C"] + pub intflagc: INTFLAGC, + _reserved8: [u8; 0x14], + #[doc = "0x34 - Peripheral write protection status - Bridge A"] + pub statusa: STATUSA, + #[doc = "0x38 - Peripheral write protection status - Bridge B"] + pub statusb: STATUSB, + #[doc = "0x3c - Peripheral write protection status - Bridge C"] + pub statusc: STATUSC, +} +#[doc = "WRCTRL (rw) register accessor: an alias for `Reg`"] +pub type WRCTRL = crate::Reg; +#[doc = "Write control"] +pub mod wrctrl; +#[doc = "EVCTRL (rw) register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event control"] +pub mod evctrl; +#[doc = "INTENCLR (rw) register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt enable clear"] +pub mod intenclr; +#[doc = "INTENSET (rw) register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt enable set"] +pub mod intenset; +#[doc = "INTFLAGAHB (rw) register accessor: an alias for `Reg`"] +pub type INTFLAGAHB = crate::Reg; +#[doc = "Bridge interrupt flag status"] +pub mod intflagahb; +#[doc = "INTFLAGA (rw) register accessor: an alias for `Reg`"] +pub type INTFLAGA = crate::Reg; +#[doc = "Peripheral interrupt flag status - Bridge A"] +pub mod intflaga; +#[doc = "INTFLAGB (rw) register accessor: an alias for `Reg`"] +pub type INTFLAGB = crate::Reg; +#[doc = "Peripheral interrupt flag status - Bridge B"] +pub mod intflagb; +#[doc = "INTFLAGC (rw) register accessor: an alias for `Reg`"] +pub type INTFLAGC = crate::Reg; +#[doc = "Peripheral interrupt flag status - Bridge C"] +pub mod intflagc; +#[doc = "STATUSA (r) register accessor: an alias for `Reg`"] +pub type STATUSA = crate::Reg; +#[doc = "Peripheral write protection status - Bridge A"] +pub mod statusa; +#[doc = "STATUSB (r) register accessor: an alias for `Reg`"] +pub type STATUSB = crate::Reg; +#[doc = "Peripheral write protection status - Bridge B"] +pub mod statusb; +#[doc = "STATUSC (r) register accessor: an alias for `Reg`"] +pub type STATUSC = crate::Reg; +#[doc = "Peripheral write protection status - Bridge C"] +pub mod statusc; diff --git a/pac/atsaml22j/src/pac/evctrl.rs b/pac/atsaml22j/src/pac/evctrl.rs new file mode 100644 index 000000000000..af1954be248c --- /dev/null +++ b/pac/atsaml22j/src/pac/evctrl.rs @@ -0,0 +1,80 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ERREO` reader - Peripheral acess error event output"] +pub type ERREO_R = crate::BitReader; +#[doc = "Field `ERREO` writer - Peripheral acess error event output"] +pub type ERREO_W<'a, const O: u8> = crate::BitWriter<'a, u8, EVCTRL_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Peripheral acess error event output"] + #[inline(always)] + pub fn erreo(&self) -> ERREO_R { + ERREO_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Peripheral acess error event output"] + #[inline(always)] + #[must_use] + pub fn erreo(&mut self) -> ERREO_W<0> { + ERREO_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/pac/intenclr.rs b/pac/atsaml22j/src/pac/intenclr.rs new file mode 100644 index 000000000000..53deb143e7e1 --- /dev/null +++ b/pac/atsaml22j/src/pac/intenclr.rs @@ -0,0 +1,80 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ERR` reader - Peripheral access error interrupt disable"] +pub type ERR_R = crate::BitReader; +#[doc = "Field `ERR` writer - Peripheral access error interrupt disable"] +pub type ERR_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Peripheral access error interrupt disable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Peripheral access error interrupt disable"] + #[inline(always)] + #[must_use] + pub fn err(&mut self) -> ERR_W<0> { + ERR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt enable clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/pac/intenset.rs b/pac/atsaml22j/src/pac/intenset.rs new file mode 100644 index 000000000000..e8b8d077a78d --- /dev/null +++ b/pac/atsaml22j/src/pac/intenset.rs @@ -0,0 +1,80 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ERR` reader - Peripheral access error interrupt enable"] +pub type ERR_R = crate::BitReader; +#[doc = "Field `ERR` writer - Peripheral access error interrupt enable"] +pub type ERR_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENSET_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Peripheral access error interrupt enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Peripheral access error interrupt enable"] + #[inline(always)] + #[must_use] + pub fn err(&mut self) -> ERR_W<0> { + ERR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt enable set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/pac/intflaga.rs b/pac/atsaml22j/src/pac/intflaga.rs new file mode 100644 index 000000000000..b40aca8726e5 --- /dev/null +++ b/pac/atsaml22j/src/pac/intflaga.rs @@ -0,0 +1,245 @@ +#[doc = "Register `INTFLAGA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAGA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PAC_` reader - PAC"] +pub type PAC__R = crate::BitReader; +#[doc = "Field `PAC_` writer - PAC"] +pub type PAC__W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAGA_SPEC, bool, O>; +#[doc = "Field `PM_` reader - PM"] +pub type PM__R = crate::BitReader; +#[doc = "Field `PM_` writer - PM"] +pub type PM__W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAGA_SPEC, bool, O>; +#[doc = "Field `MCLK_` reader - MCLK"] +pub type MCLK__R = crate::BitReader; +#[doc = "Field `MCLK_` writer - MCLK"] +pub type MCLK__W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAGA_SPEC, bool, O>; +#[doc = "Field `RSTC_` reader - RSTC"] +pub type RSTC__R = crate::BitReader; +#[doc = "Field `RSTC_` writer - RSTC"] +pub type RSTC__W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAGA_SPEC, bool, O>; +#[doc = "Field `OSCCTRL_` reader - OSCCTRL"] +pub type OSCCTRL__R = crate::BitReader; +#[doc = "Field `OSCCTRL_` writer - OSCCTRL"] +pub type OSCCTRL__W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAGA_SPEC, bool, O>; +#[doc = "Field `OSC32KCTRL_` reader - OSC32KCTRL"] +pub type OSC32KCTRL__R = crate::BitReader; +#[doc = "Field `OSC32KCTRL_` writer - OSC32KCTRL"] +pub type OSC32KCTRL__W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAGA_SPEC, bool, O>; +#[doc = "Field `SUPC_` reader - SUPC"] +pub type SUPC__R = crate::BitReader; +#[doc = "Field `SUPC_` writer - SUPC"] +pub type SUPC__W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAGA_SPEC, bool, O>; +#[doc = "Field `GCLK_` reader - GCLK"] +pub type GCLK__R = crate::BitReader; +#[doc = "Field `GCLK_` writer - GCLK"] +pub type GCLK__W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAGA_SPEC, bool, O>; +#[doc = "Field `WDT_` reader - WDT"] +pub type WDT__R = crate::BitReader; +#[doc = "Field `WDT_` writer - WDT"] +pub type WDT__W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAGA_SPEC, bool, O>; +#[doc = "Field `RTC_` reader - RTC"] +pub type RTC__R = crate::BitReader; +#[doc = "Field `RTC_` writer - RTC"] +pub type RTC__W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAGA_SPEC, bool, O>; +#[doc = "Field `EIC_` reader - EIC"] +pub type EIC__R = crate::BitReader; +#[doc = "Field `EIC_` writer - EIC"] +pub type EIC__W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAGA_SPEC, bool, O>; +#[doc = "Field `FREQM_` reader - FREQM"] +pub type FREQM__R = crate::BitReader; +#[doc = "Field `FREQM_` writer - FREQM"] +pub type FREQM__W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAGA_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - PAC"] + #[inline(always)] + pub fn pac_(&self) -> PAC__R { + PAC__R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - PM"] + #[inline(always)] + pub fn pm_(&self) -> PM__R { + PM__R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - MCLK"] + #[inline(always)] + pub fn mclk_(&self) -> MCLK__R { + MCLK__R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - RSTC"] + #[inline(always)] + pub fn rstc_(&self) -> RSTC__R { + RSTC__R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - OSCCTRL"] + #[inline(always)] + pub fn oscctrl_(&self) -> OSCCTRL__R { + OSCCTRL__R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - OSC32KCTRL"] + #[inline(always)] + pub fn osc32kctrl_(&self) -> OSC32KCTRL__R { + OSC32KCTRL__R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - SUPC"] + #[inline(always)] + pub fn supc_(&self) -> SUPC__R { + SUPC__R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - GCLK"] + #[inline(always)] + pub fn gclk_(&self) -> GCLK__R { + GCLK__R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - WDT"] + #[inline(always)] + pub fn wdt_(&self) -> WDT__R { + WDT__R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - RTC"] + #[inline(always)] + pub fn rtc_(&self) -> RTC__R { + RTC__R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - EIC"] + #[inline(always)] + pub fn eic_(&self) -> EIC__R { + EIC__R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - FREQM"] + #[inline(always)] + pub fn freqm_(&self) -> FREQM__R { + FREQM__R::new(((self.bits >> 11) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - PAC"] + #[inline(always)] + #[must_use] + pub fn pac_(&mut self) -> PAC__W<0> { + PAC__W::new(self) + } + #[doc = "Bit 1 - PM"] + #[inline(always)] + #[must_use] + pub fn pm_(&mut self) -> PM__W<1> { + PM__W::new(self) + } + #[doc = "Bit 2 - MCLK"] + #[inline(always)] + #[must_use] + pub fn mclk_(&mut self) -> MCLK__W<2> { + MCLK__W::new(self) + } + #[doc = "Bit 3 - RSTC"] + #[inline(always)] + #[must_use] + pub fn rstc_(&mut self) -> RSTC__W<3> { + RSTC__W::new(self) + } + #[doc = "Bit 4 - OSCCTRL"] + #[inline(always)] + #[must_use] + pub fn oscctrl_(&mut self) -> OSCCTRL__W<4> { + OSCCTRL__W::new(self) + } + #[doc = "Bit 5 - OSC32KCTRL"] + #[inline(always)] + #[must_use] + pub fn osc32kctrl_(&mut self) -> OSC32KCTRL__W<5> { + OSC32KCTRL__W::new(self) + } + #[doc = "Bit 6 - SUPC"] + #[inline(always)] + #[must_use] + pub fn supc_(&mut self) -> SUPC__W<6> { + SUPC__W::new(self) + } + #[doc = "Bit 7 - GCLK"] + #[inline(always)] + #[must_use] + pub fn gclk_(&mut self) -> GCLK__W<7> { + GCLK__W::new(self) + } + #[doc = "Bit 8 - WDT"] + #[inline(always)] + #[must_use] + pub fn wdt_(&mut self) -> WDT__W<8> { + WDT__W::new(self) + } + #[doc = "Bit 9 - RTC"] + #[inline(always)] + #[must_use] + pub fn rtc_(&mut self) -> RTC__W<9> { + RTC__W::new(self) + } + #[doc = "Bit 10 - EIC"] + #[inline(always)] + #[must_use] + pub fn eic_(&mut self) -> EIC__W<10> { + EIC__W::new(self) + } + #[doc = "Bit 11 - FREQM"] + #[inline(always)] + #[must_use] + pub fn freqm_(&mut self) -> FREQM__W<11> { + FREQM__W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Peripheral interrupt flag status - Bridge A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflaga](index.html) module"] +pub struct INTFLAGA_SPEC; +impl crate::RegisterSpec for INTFLAGA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflaga::R](R) reader structure"] +impl crate::Readable for INTFLAGA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflaga::W](W) writer structure"] +impl crate::Writable for INTFLAGA_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTFLAGA to value 0"] +impl crate::Resettable for INTFLAGA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/pac/intflagahb.rs b/pac/atsaml22j/src/pac/intflagahb.rs new file mode 100644 index 000000000000..b0f93e15a80a --- /dev/null +++ b/pac/atsaml22j/src/pac/intflagahb.rs @@ -0,0 +1,170 @@ +#[doc = "Register `INTFLAGAHB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAGAHB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FLASH_` reader - FLASH"] +pub type FLASH__R = crate::BitReader; +#[doc = "Field `FLASH_` writer - FLASH"] +pub type FLASH__W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAGAHB_SPEC, bool, O>; +#[doc = "Field `HSRAMCM0P_` reader - HSRAMCM0P"] +pub type HSRAMCM0P__R = crate::BitReader; +#[doc = "Field `HSRAMCM0P_` writer - HSRAMCM0P"] +pub type HSRAMCM0P__W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAGAHB_SPEC, bool, O>; +#[doc = "Field `HSRAMDSU_` reader - HSRAMDSU"] +pub type HSRAMDSU__R = crate::BitReader; +#[doc = "Field `HSRAMDSU_` writer - HSRAMDSU"] +pub type HSRAMDSU__W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAGAHB_SPEC, bool, O>; +#[doc = "Field `HPB1_` reader - HPB1"] +pub type HPB1__R = crate::BitReader; +#[doc = "Field `HPB1_` writer - HPB1"] +pub type HPB1__W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAGAHB_SPEC, bool, O>; +#[doc = "Field `HPB0_` reader - HPB0"] +pub type HPB0__R = crate::BitReader; +#[doc = "Field `HPB0_` writer - HPB0"] +pub type HPB0__W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAGAHB_SPEC, bool, O>; +#[doc = "Field `HPB2_` reader - HPB2"] +pub type HPB2__R = crate::BitReader; +#[doc = "Field `HPB2_` writer - HPB2"] +pub type HPB2__W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAGAHB_SPEC, bool, O>; +#[doc = "Field `HSRAMDMAC_` reader - HSRAMDMAC"] +pub type HSRAMDMAC__R = crate::BitReader; +#[doc = "Field `HSRAMDMAC_` writer - HSRAMDMAC"] +pub type HSRAMDMAC__W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAGAHB_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - FLASH"] + #[inline(always)] + pub fn flash_(&self) -> FLASH__R { + FLASH__R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - HSRAMCM0P"] + #[inline(always)] + pub fn hsramcm0p_(&self) -> HSRAMCM0P__R { + HSRAMCM0P__R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - HSRAMDSU"] + #[inline(always)] + pub fn hsramdsu_(&self) -> HSRAMDSU__R { + HSRAMDSU__R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - HPB1"] + #[inline(always)] + pub fn hpb1_(&self) -> HPB1__R { + HPB1__R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - HPB0"] + #[inline(always)] + pub fn hpb0_(&self) -> HPB0__R { + HPB0__R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - HPB2"] + #[inline(always)] + pub fn hpb2_(&self) -> HPB2__R { + HPB2__R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - HSRAMDMAC"] + #[inline(always)] + pub fn hsramdmac_(&self) -> HSRAMDMAC__R { + HSRAMDMAC__R::new(((self.bits >> 6) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - FLASH"] + #[inline(always)] + #[must_use] + pub fn flash_(&mut self) -> FLASH__W<0> { + FLASH__W::new(self) + } + #[doc = "Bit 1 - HSRAMCM0P"] + #[inline(always)] + #[must_use] + pub fn hsramcm0p_(&mut self) -> HSRAMCM0P__W<1> { + HSRAMCM0P__W::new(self) + } + #[doc = "Bit 2 - HSRAMDSU"] + #[inline(always)] + #[must_use] + pub fn hsramdsu_(&mut self) -> HSRAMDSU__W<2> { + HSRAMDSU__W::new(self) + } + #[doc = "Bit 3 - HPB1"] + #[inline(always)] + #[must_use] + pub fn hpb1_(&mut self) -> HPB1__W<3> { + HPB1__W::new(self) + } + #[doc = "Bit 4 - HPB0"] + #[inline(always)] + #[must_use] + pub fn hpb0_(&mut self) -> HPB0__W<4> { + HPB0__W::new(self) + } + #[doc = "Bit 5 - HPB2"] + #[inline(always)] + #[must_use] + pub fn hpb2_(&mut self) -> HPB2__W<5> { + HPB2__W::new(self) + } + #[doc = "Bit 6 - HSRAMDMAC"] + #[inline(always)] + #[must_use] + pub fn hsramdmac_(&mut self) -> HSRAMDMAC__W<6> { + HSRAMDMAC__W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Bridge interrupt flag status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflagahb](index.html) module"] +pub struct INTFLAGAHB_SPEC; +impl crate::RegisterSpec for INTFLAGAHB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflagahb::R](R) reader structure"] +impl crate::Readable for INTFLAGAHB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflagahb::W](W) writer structure"] +impl crate::Writable for INTFLAGAHB_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTFLAGAHB to value 0"] +impl crate::Resettable for INTFLAGAHB_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/pac/intflagb.rs b/pac/atsaml22j/src/pac/intflagb.rs new file mode 100644 index 000000000000..f7340d060cb3 --- /dev/null +++ b/pac/atsaml22j/src/pac/intflagb.rs @@ -0,0 +1,155 @@ +#[doc = "Register `INTFLAGB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAGB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `USB_` reader - USB"] +pub type USB__R = crate::BitReader; +#[doc = "Field `USB_` writer - USB"] +pub type USB__W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAGB_SPEC, bool, O>; +#[doc = "Field `DSU_` reader - DSU"] +pub type DSU__R = crate::BitReader; +#[doc = "Field `DSU_` writer - DSU"] +pub type DSU__W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAGB_SPEC, bool, O>; +#[doc = "Field `NVMCTRL_` reader - NVMCTRL"] +pub type NVMCTRL__R = crate::BitReader; +#[doc = "Field `NVMCTRL_` writer - NVMCTRL"] +pub type NVMCTRL__W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAGB_SPEC, bool, O>; +#[doc = "Field `PORT_` reader - PORT"] +pub type PORT__R = crate::BitReader; +#[doc = "Field `PORT_` writer - PORT"] +pub type PORT__W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAGB_SPEC, bool, O>; +#[doc = "Field `DMAC_` reader - DMAC"] +pub type DMAC__R = crate::BitReader; +#[doc = "Field `DMAC_` writer - DMAC"] +pub type DMAC__W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAGB_SPEC, bool, O>; +#[doc = "Field `MTB_` reader - MTB"] +pub type MTB__R = crate::BitReader; +#[doc = "Field `MTB_` writer - MTB"] +pub type MTB__W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAGB_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - USB"] + #[inline(always)] + pub fn usb_(&self) -> USB__R { + USB__R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - DSU"] + #[inline(always)] + pub fn dsu_(&self) -> DSU__R { + DSU__R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NVMCTRL"] + #[inline(always)] + pub fn nvmctrl_(&self) -> NVMCTRL__R { + NVMCTRL__R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - PORT"] + #[inline(always)] + pub fn port_(&self) -> PORT__R { + PORT__R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - DMAC"] + #[inline(always)] + pub fn dmac_(&self) -> DMAC__R { + DMAC__R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - MTB"] + #[inline(always)] + pub fn mtb_(&self) -> MTB__R { + MTB__R::new(((self.bits >> 5) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - USB"] + #[inline(always)] + #[must_use] + pub fn usb_(&mut self) -> USB__W<0> { + USB__W::new(self) + } + #[doc = "Bit 1 - DSU"] + #[inline(always)] + #[must_use] + pub fn dsu_(&mut self) -> DSU__W<1> { + DSU__W::new(self) + } + #[doc = "Bit 2 - NVMCTRL"] + #[inline(always)] + #[must_use] + pub fn nvmctrl_(&mut self) -> NVMCTRL__W<2> { + NVMCTRL__W::new(self) + } + #[doc = "Bit 3 - PORT"] + #[inline(always)] + #[must_use] + pub fn port_(&mut self) -> PORT__W<3> { + PORT__W::new(self) + } + #[doc = "Bit 4 - DMAC"] + #[inline(always)] + #[must_use] + pub fn dmac_(&mut self) -> DMAC__W<4> { + DMAC__W::new(self) + } + #[doc = "Bit 5 - MTB"] + #[inline(always)] + #[must_use] + pub fn mtb_(&mut self) -> MTB__W<5> { + MTB__W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Peripheral interrupt flag status - Bridge B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflagb](index.html) module"] +pub struct INTFLAGB_SPEC; +impl crate::RegisterSpec for INTFLAGB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflagb::R](R) reader structure"] +impl crate::Readable for INTFLAGB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflagb::W](W) writer structure"] +impl crate::Writable for INTFLAGB_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTFLAGB to value 0"] +impl crate::Resettable for INTFLAGB_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/pac/intflagc.rs b/pac/atsaml22j/src/pac/intflagc.rs new file mode 100644 index 000000000000..a3fb501b149e --- /dev/null +++ b/pac/atsaml22j/src/pac/intflagc.rs @@ -0,0 +1,320 @@ +#[doc = "Register `INTFLAGC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAGC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVSYS_` reader - EVSYS"] +pub type EVSYS__R = crate::BitReader; +#[doc = "Field `EVSYS_` writer - EVSYS"] +pub type EVSYS__W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAGC_SPEC, bool, O>; +#[doc = "Field `SERCOM0_` reader - SERCOM0"] +pub type SERCOM0__R = crate::BitReader; +#[doc = "Field `SERCOM0_` writer - SERCOM0"] +pub type SERCOM0__W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAGC_SPEC, bool, O>; +#[doc = "Field `SERCOM1_` reader - SERCOM1"] +pub type SERCOM1__R = crate::BitReader; +#[doc = "Field `SERCOM1_` writer - SERCOM1"] +pub type SERCOM1__W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAGC_SPEC, bool, O>; +#[doc = "Field `SERCOM2_` reader - SERCOM2"] +pub type SERCOM2__R = crate::BitReader; +#[doc = "Field `SERCOM2_` writer - SERCOM2"] +pub type SERCOM2__W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAGC_SPEC, bool, O>; +#[doc = "Field `SERCOM3_` reader - SERCOM3"] +pub type SERCOM3__R = crate::BitReader; +#[doc = "Field `SERCOM3_` writer - SERCOM3"] +pub type SERCOM3__W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAGC_SPEC, bool, O>; +#[doc = "Field `TCC0_` reader - TCC0"] +pub type TCC0__R = crate::BitReader; +#[doc = "Field `TCC0_` writer - TCC0"] +pub type TCC0__W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAGC_SPEC, bool, O>; +#[doc = "Field `TC0_` reader - TC0"] +pub type TC0__R = crate::BitReader; +#[doc = "Field `TC0_` writer - TC0"] +pub type TC0__W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAGC_SPEC, bool, O>; +#[doc = "Field `TC1_` reader - TC1"] +pub type TC1__R = crate::BitReader; +#[doc = "Field `TC1_` writer - TC1"] +pub type TC1__W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAGC_SPEC, bool, O>; +#[doc = "Field `TC2_` reader - TC2"] +pub type TC2__R = crate::BitReader; +#[doc = "Field `TC2_` writer - TC2"] +pub type TC2__W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAGC_SPEC, bool, O>; +#[doc = "Field `TC3_` reader - TC3"] +pub type TC3__R = crate::BitReader; +#[doc = "Field `TC3_` writer - TC3"] +pub type TC3__W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAGC_SPEC, bool, O>; +#[doc = "Field `ADC_` reader - ADC"] +pub type ADC__R = crate::BitReader; +#[doc = "Field `ADC_` writer - ADC"] +pub type ADC__W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAGC_SPEC, bool, O>; +#[doc = "Field `AC_` reader - AC"] +pub type AC__R = crate::BitReader; +#[doc = "Field `AC_` writer - AC"] +pub type AC__W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAGC_SPEC, bool, O>; +#[doc = "Field `PTC_` reader - PTC"] +pub type PTC__R = crate::BitReader; +#[doc = "Field `PTC_` writer - PTC"] +pub type PTC__W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAGC_SPEC, bool, O>; +#[doc = "Field `SLCD_` reader - SLCD"] +pub type SLCD__R = crate::BitReader; +#[doc = "Field `SLCD_` writer - SLCD"] +pub type SLCD__W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAGC_SPEC, bool, O>; +#[doc = "Field `AES_` reader - AES"] +pub type AES__R = crate::BitReader; +#[doc = "Field `AES_` writer - AES"] +pub type AES__W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAGC_SPEC, bool, O>; +#[doc = "Field `TRNG_` reader - TRNG"] +pub type TRNG__R = crate::BitReader; +#[doc = "Field `TRNG_` writer - TRNG"] +pub type TRNG__W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAGC_SPEC, bool, O>; +#[doc = "Field `CCL_` reader - CCL"] +pub type CCL__R = crate::BitReader; +#[doc = "Field `CCL_` writer - CCL"] +pub type CCL__W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAGC_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - EVSYS"] + #[inline(always)] + pub fn evsys_(&self) -> EVSYS__R { + EVSYS__R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - SERCOM0"] + #[inline(always)] + pub fn sercom0_(&self) -> SERCOM0__R { + SERCOM0__R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - SERCOM1"] + #[inline(always)] + pub fn sercom1_(&self) -> SERCOM1__R { + SERCOM1__R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - SERCOM2"] + #[inline(always)] + pub fn sercom2_(&self) -> SERCOM2__R { + SERCOM2__R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - SERCOM3"] + #[inline(always)] + pub fn sercom3_(&self) -> SERCOM3__R { + SERCOM3__R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 7 - TCC0"] + #[inline(always)] + pub fn tcc0_(&self) -> TCC0__R { + TCC0__R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - TC0"] + #[inline(always)] + pub fn tc0_(&self) -> TC0__R { + TC0__R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - TC1"] + #[inline(always)] + pub fn tc1_(&self) -> TC1__R { + TC1__R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - TC2"] + #[inline(always)] + pub fn tc2_(&self) -> TC2__R { + TC2__R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - TC3"] + #[inline(always)] + pub fn tc3_(&self) -> TC3__R { + TC3__R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - ADC"] + #[inline(always)] + pub fn adc_(&self) -> ADC__R { + ADC__R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - AC"] + #[inline(always)] + pub fn ac_(&self) -> AC__R { + AC__R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - PTC"] + #[inline(always)] + pub fn ptc_(&self) -> PTC__R { + PTC__R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - SLCD"] + #[inline(always)] + pub fn slcd_(&self) -> SLCD__R { + SLCD__R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - AES"] + #[inline(always)] + pub fn aes_(&self) -> AES__R { + AES__R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - TRNG"] + #[inline(always)] + pub fn trng_(&self) -> TRNG__R { + TRNG__R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - CCL"] + #[inline(always)] + pub fn ccl_(&self) -> CCL__R { + CCL__R::new(((self.bits >> 18) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - EVSYS"] + #[inline(always)] + #[must_use] + pub fn evsys_(&mut self) -> EVSYS__W<0> { + EVSYS__W::new(self) + } + #[doc = "Bit 1 - SERCOM0"] + #[inline(always)] + #[must_use] + pub fn sercom0_(&mut self) -> SERCOM0__W<1> { + SERCOM0__W::new(self) + } + #[doc = "Bit 2 - SERCOM1"] + #[inline(always)] + #[must_use] + pub fn sercom1_(&mut self) -> SERCOM1__W<2> { + SERCOM1__W::new(self) + } + #[doc = "Bit 3 - SERCOM2"] + #[inline(always)] + #[must_use] + pub fn sercom2_(&mut self) -> SERCOM2__W<3> { + SERCOM2__W::new(self) + } + #[doc = "Bit 4 - SERCOM3"] + #[inline(always)] + #[must_use] + pub fn sercom3_(&mut self) -> SERCOM3__W<4> { + SERCOM3__W::new(self) + } + #[doc = "Bit 7 - TCC0"] + #[inline(always)] + #[must_use] + pub fn tcc0_(&mut self) -> TCC0__W<7> { + TCC0__W::new(self) + } + #[doc = "Bit 8 - TC0"] + #[inline(always)] + #[must_use] + pub fn tc0_(&mut self) -> TC0__W<8> { + TC0__W::new(self) + } + #[doc = "Bit 9 - TC1"] + #[inline(always)] + #[must_use] + pub fn tc1_(&mut self) -> TC1__W<9> { + TC1__W::new(self) + } + #[doc = "Bit 10 - TC2"] + #[inline(always)] + #[must_use] + pub fn tc2_(&mut self) -> TC2__W<10> { + TC2__W::new(self) + } + #[doc = "Bit 11 - TC3"] + #[inline(always)] + #[must_use] + pub fn tc3_(&mut self) -> TC3__W<11> { + TC3__W::new(self) + } + #[doc = "Bit 12 - ADC"] + #[inline(always)] + #[must_use] + pub fn adc_(&mut self) -> ADC__W<12> { + ADC__W::new(self) + } + #[doc = "Bit 13 - AC"] + #[inline(always)] + #[must_use] + pub fn ac_(&mut self) -> AC__W<13> { + AC__W::new(self) + } + #[doc = "Bit 14 - PTC"] + #[inline(always)] + #[must_use] + pub fn ptc_(&mut self) -> PTC__W<14> { + PTC__W::new(self) + } + #[doc = "Bit 15 - SLCD"] + #[inline(always)] + #[must_use] + pub fn slcd_(&mut self) -> SLCD__W<15> { + SLCD__W::new(self) + } + #[doc = "Bit 16 - AES"] + #[inline(always)] + #[must_use] + pub fn aes_(&mut self) -> AES__W<16> { + AES__W::new(self) + } + #[doc = "Bit 17 - TRNG"] + #[inline(always)] + #[must_use] + pub fn trng_(&mut self) -> TRNG__W<17> { + TRNG__W::new(self) + } + #[doc = "Bit 18 - CCL"] + #[inline(always)] + #[must_use] + pub fn ccl_(&mut self) -> CCL__W<18> { + CCL__W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Peripheral interrupt flag status - Bridge C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflagc](index.html) module"] +pub struct INTFLAGC_SPEC; +impl crate::RegisterSpec for INTFLAGC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflagc::R](R) reader structure"] +impl crate::Readable for INTFLAGC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflagc::W](W) writer structure"] +impl crate::Writable for INTFLAGC_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTFLAGC to value 0"] +impl crate::Resettable for INTFLAGC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/pac/statusa.rs b/pac/atsaml22j/src/pac/statusa.rs new file mode 100644 index 000000000000..a019b989b4db --- /dev/null +++ b/pac/atsaml22j/src/pac/statusa.rs @@ -0,0 +1,114 @@ +#[doc = "Register `STATUSA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `PAC_` reader - PAC APB Protect Enable"] +pub type PAC__R = crate::BitReader; +#[doc = "Field `PM_` reader - PM APB Protect Enable"] +pub type PM__R = crate::BitReader; +#[doc = "Field `MCLK_` reader - MCLK APB Protect Enable"] +pub type MCLK__R = crate::BitReader; +#[doc = "Field `RSTC_` reader - RSTC APB Protect Enable"] +pub type RSTC__R = crate::BitReader; +#[doc = "Field `OSCCTRL_` reader - OSCCTRL APB Protect Enable"] +pub type OSCCTRL__R = crate::BitReader; +#[doc = "Field `OSC32KCTRL_` reader - OSC32KCTRL APB Protect Enable"] +pub type OSC32KCTRL__R = crate::BitReader; +#[doc = "Field `SUPC_` reader - SUPC APB Protect Enable"] +pub type SUPC__R = crate::BitReader; +#[doc = "Field `GCLK_` reader - GCLK APB Protect Enable"] +pub type GCLK__R = crate::BitReader; +#[doc = "Field `WDT_` reader - WDT APB Protect Enable"] +pub type WDT__R = crate::BitReader; +#[doc = "Field `RTC_` reader - RTC APB Protect Enable"] +pub type RTC__R = crate::BitReader; +#[doc = "Field `EIC_` reader - EIC APB Protect Enable"] +pub type EIC__R = crate::BitReader; +#[doc = "Field `FREQM_` reader - FREQM APB Protect Enable"] +pub type FREQM__R = crate::BitReader; +impl R { + #[doc = "Bit 0 - PAC APB Protect Enable"] + #[inline(always)] + pub fn pac_(&self) -> PAC__R { + PAC__R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - PM APB Protect Enable"] + #[inline(always)] + pub fn pm_(&self) -> PM__R { + PM__R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - MCLK APB Protect Enable"] + #[inline(always)] + pub fn mclk_(&self) -> MCLK__R { + MCLK__R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - RSTC APB Protect Enable"] + #[inline(always)] + pub fn rstc_(&self) -> RSTC__R { + RSTC__R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - OSCCTRL APB Protect Enable"] + #[inline(always)] + pub fn oscctrl_(&self) -> OSCCTRL__R { + OSCCTRL__R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - OSC32KCTRL APB Protect Enable"] + #[inline(always)] + pub fn osc32kctrl_(&self) -> OSC32KCTRL__R { + OSC32KCTRL__R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - SUPC APB Protect Enable"] + #[inline(always)] + pub fn supc_(&self) -> SUPC__R { + SUPC__R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - GCLK APB Protect Enable"] + #[inline(always)] + pub fn gclk_(&self) -> GCLK__R { + GCLK__R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - WDT APB Protect Enable"] + #[inline(always)] + pub fn wdt_(&self) -> WDT__R { + WDT__R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - RTC APB Protect Enable"] + #[inline(always)] + pub fn rtc_(&self) -> RTC__R { + RTC__R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - EIC APB Protect Enable"] + #[inline(always)] + pub fn eic_(&self) -> EIC__R { + EIC__R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - FREQM APB Protect Enable"] + #[inline(always)] + pub fn freqm_(&self) -> FREQM__R { + FREQM__R::new(((self.bits >> 11) & 1) != 0) + } +} +#[doc = "Peripheral write protection status - Bridge A\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusa](index.html) module"] +pub struct STATUSA_SPEC; +impl crate::RegisterSpec for STATUSA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [statusa::R](R) reader structure"] +impl crate::Readable for STATUSA_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSA to value 0"] +impl crate::Resettable for STATUSA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/pac/statusb.rs b/pac/atsaml22j/src/pac/statusb.rs new file mode 100644 index 000000000000..f6aede450310 --- /dev/null +++ b/pac/atsaml22j/src/pac/statusb.rs @@ -0,0 +1,72 @@ +#[doc = "Register `STATUSB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `USB_` reader - USB APB Protect Enable"] +pub type USB__R = crate::BitReader; +#[doc = "Field `DSU_` reader - DSU APB Protect Enable"] +pub type DSU__R = crate::BitReader; +#[doc = "Field `NVMCTRL_` reader - NVMCTRL APB Protect Enable"] +pub type NVMCTRL__R = crate::BitReader; +#[doc = "Field `PORT_` reader - PORT APB Protect Enable"] +pub type PORT__R = crate::BitReader; +#[doc = "Field `DMAC_` reader - DMAC APB Protect Enable"] +pub type DMAC__R = crate::BitReader; +#[doc = "Field `MTB_` reader - MTB APB Protect Enable"] +pub type MTB__R = crate::BitReader; +impl R { + #[doc = "Bit 0 - USB APB Protect Enable"] + #[inline(always)] + pub fn usb_(&self) -> USB__R { + USB__R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - DSU APB Protect Enable"] + #[inline(always)] + pub fn dsu_(&self) -> DSU__R { + DSU__R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - NVMCTRL APB Protect Enable"] + #[inline(always)] + pub fn nvmctrl_(&self) -> NVMCTRL__R { + NVMCTRL__R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - PORT APB Protect Enable"] + #[inline(always)] + pub fn port_(&self) -> PORT__R { + PORT__R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - DMAC APB Protect Enable"] + #[inline(always)] + pub fn dmac_(&self) -> DMAC__R { + DMAC__R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - MTB APB Protect Enable"] + #[inline(always)] + pub fn mtb_(&self) -> MTB__R { + MTB__R::new(((self.bits >> 5) & 1) != 0) + } +} +#[doc = "Peripheral write protection status - Bridge B\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusb](index.html) module"] +pub struct STATUSB_SPEC; +impl crate::RegisterSpec for STATUSB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [statusb::R](R) reader structure"] +impl crate::Readable for STATUSB_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSB to value 0x02"] +impl crate::Resettable for STATUSB_SPEC { + const RESET_VALUE: Self::Ux = 0x02; +} diff --git a/pac/atsaml22j/src/pac/statusc.rs b/pac/atsaml22j/src/pac/statusc.rs new file mode 100644 index 000000000000..25b916e38087 --- /dev/null +++ b/pac/atsaml22j/src/pac/statusc.rs @@ -0,0 +1,149 @@ +#[doc = "Register `STATUSC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `EVSYS_` reader - EVSYS APB Protect Enable"] +pub type EVSYS__R = crate::BitReader; +#[doc = "Field `SERCOM0_` reader - SERCOM0 APB Protect Enable"] +pub type SERCOM0__R = crate::BitReader; +#[doc = "Field `SERCOM1_` reader - SERCOM1 APB Protect Enable"] +pub type SERCOM1__R = crate::BitReader; +#[doc = "Field `SERCOM2_` reader - SERCOM2 APB Protect Enable"] +pub type SERCOM2__R = crate::BitReader; +#[doc = "Field `SERCOM3_` reader - SERCOM3 APB Protect Enable"] +pub type SERCOM3__R = crate::BitReader; +#[doc = "Field `TCC0_` reader - TCC0 APB Protect Enable"] +pub type TCC0__R = crate::BitReader; +#[doc = "Field `TC0_` reader - TC0 APB Protect Enable"] +pub type TC0__R = crate::BitReader; +#[doc = "Field `TC1_` reader - TC1 APB Protect Enable"] +pub type TC1__R = crate::BitReader; +#[doc = "Field `TC2_` reader - TC2 APB Protect Enable"] +pub type TC2__R = crate::BitReader; +#[doc = "Field `TC3_` reader - TC3 APB Protect Enable"] +pub type TC3__R = crate::BitReader; +#[doc = "Field `ADC_` reader - ADC APB Protect Enable"] +pub type ADC__R = crate::BitReader; +#[doc = "Field `AC_` reader - AC APB Protect Enable"] +pub type AC__R = crate::BitReader; +#[doc = "Field `PTC_` reader - PTC APB Protect Enable"] +pub type PTC__R = crate::BitReader; +#[doc = "Field `SLCD_` reader - SLCD APB Protect Enable"] +pub type SLCD__R = crate::BitReader; +#[doc = "Field `AES_` reader - AES APB Protect Enable"] +pub type AES__R = crate::BitReader; +#[doc = "Field `TRNG_` reader - TRNG APB Protect Enable"] +pub type TRNG__R = crate::BitReader; +#[doc = "Field `CCL_` reader - CCL APB Protect Enable"] +pub type CCL__R = crate::BitReader; +impl R { + #[doc = "Bit 0 - EVSYS APB Protect Enable"] + #[inline(always)] + pub fn evsys_(&self) -> EVSYS__R { + EVSYS__R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - SERCOM0 APB Protect Enable"] + #[inline(always)] + pub fn sercom0_(&self) -> SERCOM0__R { + SERCOM0__R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - SERCOM1 APB Protect Enable"] + #[inline(always)] + pub fn sercom1_(&self) -> SERCOM1__R { + SERCOM1__R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - SERCOM2 APB Protect Enable"] + #[inline(always)] + pub fn sercom2_(&self) -> SERCOM2__R { + SERCOM2__R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - SERCOM3 APB Protect Enable"] + #[inline(always)] + pub fn sercom3_(&self) -> SERCOM3__R { + SERCOM3__R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 7 - TCC0 APB Protect Enable"] + #[inline(always)] + pub fn tcc0_(&self) -> TCC0__R { + TCC0__R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - TC0 APB Protect Enable"] + #[inline(always)] + pub fn tc0_(&self) -> TC0__R { + TC0__R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - TC1 APB Protect Enable"] + #[inline(always)] + pub fn tc1_(&self) -> TC1__R { + TC1__R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - TC2 APB Protect Enable"] + #[inline(always)] + pub fn tc2_(&self) -> TC2__R { + TC2__R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - TC3 APB Protect Enable"] + #[inline(always)] + pub fn tc3_(&self) -> TC3__R { + TC3__R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - ADC APB Protect Enable"] + #[inline(always)] + pub fn adc_(&self) -> ADC__R { + ADC__R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - AC APB Protect Enable"] + #[inline(always)] + pub fn ac_(&self) -> AC__R { + AC__R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - PTC APB Protect Enable"] + #[inline(always)] + pub fn ptc_(&self) -> PTC__R { + PTC__R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - SLCD APB Protect Enable"] + #[inline(always)] + pub fn slcd_(&self) -> SLCD__R { + SLCD__R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - AES APB Protect Enable"] + #[inline(always)] + pub fn aes_(&self) -> AES__R { + AES__R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - TRNG APB Protect Enable"] + #[inline(always)] + pub fn trng_(&self) -> TRNG__R { + TRNG__R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - CCL APB Protect Enable"] + #[inline(always)] + pub fn ccl_(&self) -> CCL__R { + CCL__R::new(((self.bits >> 18) & 1) != 0) + } +} +#[doc = "Peripheral write protection status - Bridge C\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [statusc](index.html) module"] +pub struct STATUSC_SPEC; +impl crate::RegisterSpec for STATUSC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [statusc::R](R) reader structure"] +impl crate::Readable for STATUSC_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUSC to value 0x0008_0000"] +impl crate::Resettable for STATUSC_SPEC { + const RESET_VALUE: Self::Ux = 0x0008_0000; +} diff --git a/pac/atsaml22j/src/pac/wrctrl.rs b/pac/atsaml22j/src/pac/wrctrl.rs new file mode 100644 index 000000000000..0380b1f226a4 --- /dev/null +++ b/pac/atsaml22j/src/pac/wrctrl.rs @@ -0,0 +1,169 @@ +#[doc = "Register `WRCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WRCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PERID` reader - Peripheral identifier"] +pub type PERID_R = crate::FieldReader; +#[doc = "Field `PERID` writer - Peripheral identifier"] +pub type PERID_W<'a, const O: u8> = crate::FieldWriter<'a, u32, WRCTRL_SPEC, u16, u16, 16, O>; +#[doc = "Field `KEY` reader - Peripheral access control key"] +pub type KEY_R = crate::FieldReader; +#[doc = "Peripheral access control key\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum KEYSELECT_A { + #[doc = "0: No action"] + OFF = 0, + #[doc = "1: Clear protection"] + CLR = 1, + #[doc = "2: Set protection"] + SET = 2, + #[doc = "3: Set and lock protection"] + SETLCK = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: KEYSELECT_A) -> Self { + variant as _ + } +} +impl KEY_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(KEYSELECT_A::OFF), + 1 => Some(KEYSELECT_A::CLR), + 2 => Some(KEYSELECT_A::SET), + 3 => Some(KEYSELECT_A::SETLCK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == KEYSELECT_A::OFF + } + #[doc = "Checks if the value of the field is `CLR`"] + #[inline(always)] + pub fn is_clr(&self) -> bool { + *self == KEYSELECT_A::CLR + } + #[doc = "Checks if the value of the field is `SET`"] + #[inline(always)] + pub fn is_set(&self) -> bool { + *self == KEYSELECT_A::SET + } + #[doc = "Checks if the value of the field is `SETLCK`"] + #[inline(always)] + pub fn is_setlck(&self) -> bool { + *self == KEYSELECT_A::SETLCK + } +} +#[doc = "Field `KEY` writer - Peripheral access control key"] +pub type KEY_W<'a, const O: u8> = crate::FieldWriter<'a, u32, WRCTRL_SPEC, u8, KEYSELECT_A, 8, O>; +impl<'a, const O: u8> KEY_W<'a, O> { + #[doc = "No action"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(KEYSELECT_A::OFF) + } + #[doc = "Clear protection"] + #[inline(always)] + pub fn clr(self) -> &'a mut W { + self.variant(KEYSELECT_A::CLR) + } + #[doc = "Set protection"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(KEYSELECT_A::SET) + } + #[doc = "Set and lock protection"] + #[inline(always)] + pub fn setlck(self) -> &'a mut W { + self.variant(KEYSELECT_A::SETLCK) + } +} +impl R { + #[doc = "Bits 0:15 - Peripheral identifier"] + #[inline(always)] + pub fn perid(&self) -> PERID_R { + PERID_R::new((self.bits & 0xffff) as u16) + } + #[doc = "Bits 16:23 - Peripheral access control key"] + #[inline(always)] + pub fn key(&self) -> KEY_R { + KEY_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:15 - Peripheral identifier"] + #[inline(always)] + #[must_use] + pub fn perid(&mut self) -> PERID_W<0> { + PERID_W::new(self) + } + #[doc = "Bits 16:23 - Peripheral access control key"] + #[inline(always)] + #[must_use] + pub fn key(&mut self) -> KEY_W<16> { + KEY_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Write control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wrctrl](index.html) module"] +pub struct WRCTRL_SPEC; +impl crate::RegisterSpec for WRCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wrctrl::R](R) reader structure"] +impl crate::Readable for WRCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wrctrl::W](W) writer structure"] +impl crate::Writable for WRCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets WRCTRL to value 0"] +impl crate::Resettable for WRCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/pm.rs b/pac/atsaml22j/src/pm.rs new file mode 100644 index 000000000000..ff54cf924afd --- /dev/null +++ b/pac/atsaml22j/src/pm.rs @@ -0,0 +1,48 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: CTRLA, + #[doc = "0x01 - Sleep Configuration"] + pub sleepcfg: SLEEPCFG, + #[doc = "0x02 - Performance Level Configuration"] + pub plcfg: PLCFG, + _reserved3: [u8; 0x01], + #[doc = "0x04 - Interrupt Enable Clear"] + pub intenclr: INTENCLR, + #[doc = "0x05 - Interrupt Enable Set"] + pub intenset: INTENSET, + #[doc = "0x06 - Interrupt Flag Status and Clear"] + pub intflag: INTFLAG, + _reserved6: [u8; 0x01], + #[doc = "0x08 - Standby Configuration"] + pub stdbycfg: STDBYCFG, +} +#[doc = "CTRLA (rw) register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "SLEEPCFG (rw) register accessor: an alias for `Reg`"] +pub type SLEEPCFG = crate::Reg; +#[doc = "Sleep Configuration"] +pub mod sleepcfg; +#[doc = "PLCFG (rw) register accessor: an alias for `Reg`"] +pub type PLCFG = crate::Reg; +#[doc = "Performance Level Configuration"] +pub mod plcfg; +#[doc = "INTENCLR (rw) register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET (rw) register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG (rw) register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STDBYCFG (rw) register accessor: an alias for `Reg`"] +pub type STDBYCFG = crate::Reg; +#[doc = "Standby Configuration"] +pub mod stdbycfg; diff --git a/pac/atsaml22j/src/pm/ctrla.rs b/pac/atsaml22j/src/pm/ctrla.rs new file mode 100644 index 000000000000..64ce922ca7dc --- /dev/null +++ b/pac/atsaml22j/src/pm/ctrla.rs @@ -0,0 +1,80 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `IORET` reader - I/O Retention"] +pub type IORET_R = crate::BitReader; +#[doc = "Field `IORET` writer - I/O Retention"] +pub type IORET_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLA_SPEC, bool, O>; +impl R { + #[doc = "Bit 2 - I/O Retention"] + #[inline(always)] + pub fn ioret(&self) -> IORET_R { + IORET_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 2 - I/O Retention"] + #[inline(always)] + #[must_use] + pub fn ioret(&mut self) -> IORET_W<2> { + IORET_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/pm/intenclr.rs b/pac/atsaml22j/src/pm/intenclr.rs new file mode 100644 index 000000000000..d154ab258b95 --- /dev/null +++ b/pac/atsaml22j/src/pm/intenclr.rs @@ -0,0 +1,71 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PLRDY` writer - Performance Level Interrupt Enable"] +pub type PLRDY_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>; +impl W { + #[doc = "Bit 0 - Performance Level Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn plrdy(&mut self) -> PLRDY_W<0> { + PLRDY_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/pm/intenset.rs b/pac/atsaml22j/src/pm/intenset.rs new file mode 100644 index 000000000000..714dde83cab2 --- /dev/null +++ b/pac/atsaml22j/src/pm/intenset.rs @@ -0,0 +1,80 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PLRDY` reader - Performance Level Ready interrupt Enable"] +pub type PLRDY_R = crate::BitReader; +#[doc = "Field `PLRDY` writer - Performance Level Ready interrupt Enable"] +pub type PLRDY_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENSET_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Performance Level Ready interrupt Enable"] + #[inline(always)] + pub fn plrdy(&self) -> PLRDY_R { + PLRDY_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Performance Level Ready interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn plrdy(&mut self) -> PLRDY_W<0> { + PLRDY_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/pm/intflag.rs b/pac/atsaml22j/src/pm/intflag.rs new file mode 100644 index 000000000000..aed5286023db --- /dev/null +++ b/pac/atsaml22j/src/pm/intflag.rs @@ -0,0 +1,80 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PLRDY` reader - Performance Level Ready"] +pub type PLRDY_R = crate::BitReader; +#[doc = "Field `PLRDY` writer - Performance Level Ready"] +pub type PLRDY_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTFLAG_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Performance Level Ready"] + #[inline(always)] + pub fn plrdy(&self) -> PLRDY_R { + PLRDY_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Performance Level Ready"] + #[inline(always)] + #[must_use] + pub fn plrdy(&mut self) -> PLRDY_W<0> { + PLRDY_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/pm/plcfg.rs b/pac/atsaml22j/src/pm/plcfg.rs new file mode 100644 index 000000000000..08b882339ae0 --- /dev/null +++ b/pac/atsaml22j/src/pm/plcfg.rs @@ -0,0 +1,156 @@ +#[doc = "Register `PLCFG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PLCFG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PLSEL` reader - Performance Level Select"] +pub type PLSEL_R = crate::FieldReader; +#[doc = "Performance Level Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum PLSELSELECT_A { + #[doc = "0: Performance Level 0"] + PL0 = 0, + #[doc = "1: Performance Level 1"] + PL1 = 1, + #[doc = "2: Performance Level 2"] + PL2 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PLSELSELECT_A) -> Self { + variant as _ + } +} +impl PLSEL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PLSELSELECT_A::PL0), + 1 => Some(PLSELSELECT_A::PL1), + 2 => Some(PLSELSELECT_A::PL2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `PL0`"] + #[inline(always)] + pub fn is_pl0(&self) -> bool { + *self == PLSELSELECT_A::PL0 + } + #[doc = "Checks if the value of the field is `PL1`"] + #[inline(always)] + pub fn is_pl1(&self) -> bool { + *self == PLSELSELECT_A::PL1 + } + #[doc = "Checks if the value of the field is `PL2`"] + #[inline(always)] + pub fn is_pl2(&self) -> bool { + *self == PLSELSELECT_A::PL2 + } +} +#[doc = "Field `PLSEL` writer - Performance Level Select"] +pub type PLSEL_W<'a, const O: u8> = crate::FieldWriter<'a, u8, PLCFG_SPEC, u8, PLSELSELECT_A, 2, O>; +impl<'a, const O: u8> PLSEL_W<'a, O> { + #[doc = "Performance Level 0"] + #[inline(always)] + pub fn pl0(self) -> &'a mut W { + self.variant(PLSELSELECT_A::PL0) + } + #[doc = "Performance Level 1"] + #[inline(always)] + pub fn pl1(self) -> &'a mut W { + self.variant(PLSELSELECT_A::PL1) + } + #[doc = "Performance Level 2"] + #[inline(always)] + pub fn pl2(self) -> &'a mut W { + self.variant(PLSELSELECT_A::PL2) + } +} +#[doc = "Field `PLDIS` reader - Performance Level Disable"] +pub type PLDIS_R = crate::BitReader; +#[doc = "Field `PLDIS` writer - Performance Level Disable"] +pub type PLDIS_W<'a, const O: u8> = crate::BitWriter<'a, u8, PLCFG_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:1 - Performance Level Select"] + #[inline(always)] + pub fn plsel(&self) -> PLSEL_R { + PLSEL_R::new(self.bits & 3) + } + #[doc = "Bit 7 - Performance Level Disable"] + #[inline(always)] + pub fn pldis(&self) -> PLDIS_R { + PLDIS_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:1 - Performance Level Select"] + #[inline(always)] + #[must_use] + pub fn plsel(&mut self) -> PLSEL_W<0> { + PLSEL_W::new(self) + } + #[doc = "Bit 7 - Performance Level Disable"] + #[inline(always)] + #[must_use] + pub fn pldis(&mut self) -> PLDIS_W<7> { + PLDIS_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Performance Level Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [plcfg](index.html) module"] +pub struct PLCFG_SPEC; +impl crate::RegisterSpec for PLCFG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [plcfg::R](R) reader structure"] +impl crate::Readable for PLCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [plcfg::W](W) writer structure"] +impl crate::Writable for PLCFG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PLCFG to value 0"] +impl crate::Resettable for PLCFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/pm/sleepcfg.rs b/pac/atsaml22j/src/pm/sleepcfg.rs new file mode 100644 index 000000000000..fd47cec1d3ac --- /dev/null +++ b/pac/atsaml22j/src/pm/sleepcfg.rs @@ -0,0 +1,181 @@ +#[doc = "Register `SLEEPCFG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SLEEPCFG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SLEEPMODE` reader - Sleep Mode"] +pub type SLEEPMODE_R = crate::FieldReader; +#[doc = "Sleep Mode\n\nValue on reset: 2"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SLEEPMODESELECT_A { + #[doc = "0: CPU clock is OFF"] + IDLE0 = 0, + #[doc = "1: AHB clock is OFF"] + IDLE1 = 1, + #[doc = "2: APB clock are OFF"] + IDLE2 = 2, + #[doc = "4: All Clocks are OFF"] + STANDBY = 4, + #[doc = "5: Only Backup domain is powered ON"] + BACKUP = 5, + #[doc = "6: All power domains are powered OFF"] + OFF = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SLEEPMODESELECT_A) -> Self { + variant as _ + } +} +impl SLEEPMODE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SLEEPMODESELECT_A::IDLE0), + 1 => Some(SLEEPMODESELECT_A::IDLE1), + 2 => Some(SLEEPMODESELECT_A::IDLE2), + 4 => Some(SLEEPMODESELECT_A::STANDBY), + 5 => Some(SLEEPMODESELECT_A::BACKUP), + 6 => Some(SLEEPMODESELECT_A::OFF), + _ => None, + } + } + #[doc = "Checks if the value of the field is `IDLE0`"] + #[inline(always)] + pub fn is_idle0(&self) -> bool { + *self == SLEEPMODESELECT_A::IDLE0 + } + #[doc = "Checks if the value of the field is `IDLE1`"] + #[inline(always)] + pub fn is_idle1(&self) -> bool { + *self == SLEEPMODESELECT_A::IDLE1 + } + #[doc = "Checks if the value of the field is `IDLE2`"] + #[inline(always)] + pub fn is_idle2(&self) -> bool { + *self == SLEEPMODESELECT_A::IDLE2 + } + #[doc = "Checks if the value of the field is `STANDBY`"] + #[inline(always)] + pub fn is_standby(&self) -> bool { + *self == SLEEPMODESELECT_A::STANDBY + } + #[doc = "Checks if the value of the field is `BACKUP`"] + #[inline(always)] + pub fn is_backup(&self) -> bool { + *self == SLEEPMODESELECT_A::BACKUP + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == SLEEPMODESELECT_A::OFF + } +} +#[doc = "Field `SLEEPMODE` writer - Sleep Mode"] +pub type SLEEPMODE_W<'a, const O: u8> = + crate::FieldWriter<'a, u8, SLEEPCFG_SPEC, u8, SLEEPMODESELECT_A, 3, O>; +impl<'a, const O: u8> SLEEPMODE_W<'a, O> { + #[doc = "CPU clock is OFF"] + #[inline(always)] + pub fn idle0(self) -> &'a mut W { + self.variant(SLEEPMODESELECT_A::IDLE0) + } + #[doc = "AHB clock is OFF"] + #[inline(always)] + pub fn idle1(self) -> &'a mut W { + self.variant(SLEEPMODESELECT_A::IDLE1) + } + #[doc = "APB clock are OFF"] + #[inline(always)] + pub fn idle2(self) -> &'a mut W { + self.variant(SLEEPMODESELECT_A::IDLE2) + } + #[doc = "All Clocks are OFF"] + #[inline(always)] + pub fn standby(self) -> &'a mut W { + self.variant(SLEEPMODESELECT_A::STANDBY) + } + #[doc = "Only Backup domain is powered ON"] + #[inline(always)] + pub fn backup(self) -> &'a mut W { + self.variant(SLEEPMODESELECT_A::BACKUP) + } + #[doc = "All power domains are powered OFF"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(SLEEPMODESELECT_A::OFF) + } +} +impl R { + #[doc = "Bits 0:2 - Sleep Mode"] + #[inline(always)] + pub fn sleepmode(&self) -> SLEEPMODE_R { + SLEEPMODE_R::new(self.bits & 7) + } +} +impl W { + #[doc = "Bits 0:2 - Sleep Mode"] + #[inline(always)] + #[must_use] + pub fn sleepmode(&mut self) -> SLEEPMODE_W<0> { + SLEEPMODE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Sleep Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sleepcfg](index.html) module"] +pub struct SLEEPCFG_SPEC; +impl crate::RegisterSpec for SLEEPCFG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [sleepcfg::R](R) reader structure"] +impl crate::Readable for SLEEPCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sleepcfg::W](W) writer structure"] +impl crate::Writable for SLEEPCFG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SLEEPCFG to value 0x02"] +impl crate::Resettable for SLEEPCFG_SPEC { + const RESET_VALUE: Self::Ux = 0x02; +} diff --git a/pac/atsaml22j/src/pm/stdbycfg.rs b/pac/atsaml22j/src/pm/stdbycfg.rs new file mode 100644 index 000000000000..f31808fcd5df --- /dev/null +++ b/pac/atsaml22j/src/pm/stdbycfg.rs @@ -0,0 +1,157 @@ +#[doc = "Register `STDBYCFG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STDBYCFG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VREGSMOD` reader - Voltage Regulator Standby mode"] +pub type VREGSMOD_R = crate::FieldReader; +#[doc = "Voltage Regulator Standby mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum VREGSMODSELECT_A { + #[doc = "0: Automatic mode"] + AUTO = 0, + #[doc = "1: Performance oriented"] + PERFORMANCE = 1, + #[doc = "2: Low Power oriented"] + LP = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: VREGSMODSELECT_A) -> Self { + variant as _ + } +} +impl VREGSMOD_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(VREGSMODSELECT_A::AUTO), + 1 => Some(VREGSMODSELECT_A::PERFORMANCE), + 2 => Some(VREGSMODSELECT_A::LP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `AUTO`"] + #[inline(always)] + pub fn is_auto(&self) -> bool { + *self == VREGSMODSELECT_A::AUTO + } + #[doc = "Checks if the value of the field is `PERFORMANCE`"] + #[inline(always)] + pub fn is_performance(&self) -> bool { + *self == VREGSMODSELECT_A::PERFORMANCE + } + #[doc = "Checks if the value of the field is `LP`"] + #[inline(always)] + pub fn is_lp(&self) -> bool { + *self == VREGSMODSELECT_A::LP + } +} +#[doc = "Field `VREGSMOD` writer - Voltage Regulator Standby mode"] +pub type VREGSMOD_W<'a, const O: u8> = + crate::FieldWriter<'a, u16, STDBYCFG_SPEC, u8, VREGSMODSELECT_A, 2, O>; +impl<'a, const O: u8> VREGSMOD_W<'a, O> { + #[doc = "Automatic mode"] + #[inline(always)] + pub fn auto(self) -> &'a mut W { + self.variant(VREGSMODSELECT_A::AUTO) + } + #[doc = "Performance oriented"] + #[inline(always)] + pub fn performance(self) -> &'a mut W { + self.variant(VREGSMODSELECT_A::PERFORMANCE) + } + #[doc = "Low Power oriented"] + #[inline(always)] + pub fn lp(self) -> &'a mut W { + self.variant(VREGSMODSELECT_A::LP) + } +} +#[doc = "Field `BBIASHS` reader - Back Bias for HMCRAMCHS"] +pub type BBIASHS_R = crate::FieldReader; +#[doc = "Field `BBIASHS` writer - Back Bias for HMCRAMCHS"] +pub type BBIASHS_W<'a, const O: u8> = crate::FieldWriter<'a, u16, STDBYCFG_SPEC, u8, u8, 2, O>; +impl R { + #[doc = "Bits 6:7 - Voltage Regulator Standby mode"] + #[inline(always)] + pub fn vregsmod(&self) -> VREGSMOD_R { + VREGSMOD_R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 10:11 - Back Bias for HMCRAMCHS"] + #[inline(always)] + pub fn bbiashs(&self) -> BBIASHS_R { + BBIASHS_R::new(((self.bits >> 10) & 3) as u8) + } +} +impl W { + #[doc = "Bits 6:7 - Voltage Regulator Standby mode"] + #[inline(always)] + #[must_use] + pub fn vregsmod(&mut self) -> VREGSMOD_W<6> { + VREGSMOD_W::new(self) + } + #[doc = "Bits 10:11 - Back Bias for HMCRAMCHS"] + #[inline(always)] + #[must_use] + pub fn bbiashs(&mut self) -> BBIASHS_W<10> { + BBIASHS_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Standby Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [stdbycfg](index.html) module"] +pub struct STDBYCFG_SPEC; +impl crate::RegisterSpec for STDBYCFG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [stdbycfg::R](R) reader structure"] +impl crate::Readable for STDBYCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [stdbycfg::W](W) writer structure"] +impl crate::Writable for STDBYCFG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets STDBYCFG to value 0x0400"] +impl crate::Resettable for STDBYCFG_SPEC { + const RESET_VALUE: Self::Ux = 0x0400; +} diff --git a/pac/atsaml22j/src/port.rs b/pac/atsaml22j/src/port.rs new file mode 100644 index 000000000000..7cac50b8cc41 --- /dev/null +++ b/pac/atsaml22j/src/port.rs @@ -0,0 +1,121 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Data Direction"] + pub dir0: DIR, + #[doc = "0x04 - Data Direction Clear"] + pub dirclr0: DIRCLR, + #[doc = "0x08 - Data Direction Set"] + pub dirset0: DIRSET, + #[doc = "0x0c - Data Direction Toggle"] + pub dirtgl0: DIRTGL, + #[doc = "0x10 - Data Output Value"] + pub out0: OUT, + #[doc = "0x14 - Data Output Value Clear"] + pub outclr0: OUTCLR, + #[doc = "0x18 - Data Output Value Set"] + pub outset0: OUTSET, + #[doc = "0x1c - Data Output Value Toggle"] + pub outtgl0: OUTTGL, + #[doc = "0x20 - Data Input Value"] + pub in0: IN, + #[doc = "0x24 - Control"] + pub ctrl0: CTRL, + #[doc = "0x28 - Write Configuration"] + pub wrconfig0: WRCONFIG, + #[doc = "0x2c - Event Input Control"] + pub evctrl0: EVCTRL, + #[doc = "0x30..0x40 - Peripheral Multiplexing n - Group 0"] + pub pmux0_: [PMUX0_; 16], + #[doc = "0x40..0x60 - Pin Configuration n - Group 0"] + pub pincfg0_: [PINCFG0_; 32], + _reserved14: [u8; 0x20], + #[doc = "0x80 - Data Direction"] + pub dir1: DIR, + #[doc = "0x84 - Data Direction Clear"] + pub dirclr1: DIRCLR, + #[doc = "0x88 - Data Direction Set"] + pub dirset1: DIRSET, + #[doc = "0x8c - Data Direction Toggle"] + pub dirtgl1: DIRTGL, + #[doc = "0x90 - Data Output Value"] + pub out1: OUT, + #[doc = "0x94 - Data Output Value Clear"] + pub outclr1: OUTCLR, + #[doc = "0x98 - Data Output Value Set"] + pub outset1: OUTSET, + #[doc = "0x9c - Data Output Value Toggle"] + pub outtgl1: OUTTGL, + #[doc = "0xa0 - Data Input Value"] + pub in1: IN, + #[doc = "0xa4 - Control"] + pub ctrl1: CTRL, + #[doc = "0xa8 - Write Configuration"] + pub wrconfig1: WRCONFIG, + #[doc = "0xac - Event Input Control"] + pub evctrl1: EVCTRL, + #[doc = "0xb0..0xc0 - Peripheral Multiplexing n - Group 1"] + pub pmux1_0: [PMUX1_0; 16], + #[doc = "0xc0..0xe0 - Pin Configuration n - Group 1"] + pub pincfg1_0: [PINCFG1_0; 32], +} +#[doc = "DIR (rw) register accessor: an alias for `Reg`"] +pub type DIR = crate::Reg; +#[doc = "Data Direction"] +pub mod dir; +#[doc = "DIRCLR (rw) register accessor: an alias for `Reg`"] +pub type DIRCLR = crate::Reg; +#[doc = "Data Direction Clear"] +pub mod dirclr; +#[doc = "DIRSET (rw) register accessor: an alias for `Reg`"] +pub type DIRSET = crate::Reg; +#[doc = "Data Direction Set"] +pub mod dirset; +#[doc = "DIRTGL (rw) register accessor: an alias for `Reg`"] +pub type DIRTGL = crate::Reg; +#[doc = "Data Direction Toggle"] +pub mod dirtgl; +#[doc = "OUT (rw) register accessor: an alias for `Reg`"] +pub type OUT = crate::Reg; +#[doc = "Data Output Value"] +pub mod out; +#[doc = "OUTCLR (rw) register accessor: an alias for `Reg`"] +pub type OUTCLR = crate::Reg; +#[doc = "Data Output Value Clear"] +pub mod outclr; +#[doc = "OUTSET (rw) register accessor: an alias for `Reg`"] +pub type OUTSET = crate::Reg; +#[doc = "Data Output Value Set"] +pub mod outset; +#[doc = "OUTTGL (rw) register accessor: an alias for `Reg`"] +pub type OUTTGL = crate::Reg; +#[doc = "Data Output Value Toggle"] +pub mod outtgl; +#[doc = "IN (r) register accessor: an alias for `Reg`"] +pub type IN = crate::Reg; +#[doc = "Data Input Value"] +pub mod in_; +#[doc = "CTRL (rw) register accessor: an alias for `Reg`"] +pub type CTRL = crate::Reg; +#[doc = "Control"] +pub mod ctrl; +#[doc = "WRCONFIG (w) register accessor: an alias for `Reg`"] +pub type WRCONFIG = crate::Reg; +#[doc = "Write Configuration"] +pub mod wrconfig; +#[doc = "EVCTRL (rw) register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Input Control"] +pub mod evctrl; +#[doc = "PMUX0_ (rw) register accessor: an alias for `Reg`"] +pub type PMUX0_ = crate::Reg; +#[doc = "Peripheral Multiplexing n - Group 0"] +pub mod pmux0_; +pub use pmux0_ as pmux1_; +pub use PMUX0_ as PMUX1_; +#[doc = "PINCFG0_ (rw) register accessor: an alias for `Reg`"] +pub type PINCFG0_ = crate::Reg; +#[doc = "Pin Configuration n - Group 0"] +pub mod pincfg0_; +pub use pincfg0_ as pincfg1_; +pub use PINCFG0_ as PINCFG1_; diff --git a/pac/atsaml22j/src/port/ctrl.rs b/pac/atsaml22j/src/port/ctrl.rs new file mode 100644 index 000000000000..a483bf13206f --- /dev/null +++ b/pac/atsaml22j/src/port/ctrl.rs @@ -0,0 +1,71 @@ +#[doc = "Register `CTRL%s` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRL%s` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SAMPLING` writer - Input Sampling Mode"] +pub type SAMPLING_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRL_SPEC, u32, u32, 32, O>; +impl W { + #[doc = "Bits 0:31 - Input Sampling Mode"] + #[inline(always)] + #[must_use] + pub fn sampling(&mut self) -> SAMPLING_W<0> { + SAMPLING_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl](index.html) module"] +pub struct CTRL_SPEC; +impl crate::RegisterSpec for CTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrl::R](R) reader structure"] +impl crate::Readable for CTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrl::W](W) writer structure"] +impl crate::Writable for CTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRL%s to value 0"] +impl crate::Resettable for CTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/port/dir.rs b/pac/atsaml22j/src/port/dir.rs new file mode 100644 index 000000000000..4c4cbdd78b85 --- /dev/null +++ b/pac/atsaml22j/src/port/dir.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DIR%s` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIR%s` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Direction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dir](index.html) module"] +pub struct DIR_SPEC; +impl crate::RegisterSpec for DIR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dir::R](R) reader structure"] +impl crate::Readable for DIR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dir::W](W) writer structure"] +impl crate::Writable for DIR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DIR%s to value 0"] +impl crate::Resettable for DIR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/port/dirclr.rs b/pac/atsaml22j/src/port/dirclr.rs new file mode 100644 index 000000000000..66b815533239 --- /dev/null +++ b/pac/atsaml22j/src/port/dirclr.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DIRCLR%s` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIRCLR%s` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Direction Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dirclr](index.html) module"] +pub struct DIRCLR_SPEC; +impl crate::RegisterSpec for DIRCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dirclr::R](R) reader structure"] +impl crate::Readable for DIRCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dirclr::W](W) writer structure"] +impl crate::Writable for DIRCLR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DIRCLR%s to value 0"] +impl crate::Resettable for DIRCLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/port/dirset.rs b/pac/atsaml22j/src/port/dirset.rs new file mode 100644 index 000000000000..46521d6dab4a --- /dev/null +++ b/pac/atsaml22j/src/port/dirset.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DIRSET%s` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIRSET%s` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Direction Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dirset](index.html) module"] +pub struct DIRSET_SPEC; +impl crate::RegisterSpec for DIRSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dirset::R](R) reader structure"] +impl crate::Readable for DIRSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dirset::W](W) writer structure"] +impl crate::Writable for DIRSET_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DIRSET%s to value 0"] +impl crate::Resettable for DIRSET_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/port/dirtgl.rs b/pac/atsaml22j/src/port/dirtgl.rs new file mode 100644 index 000000000000..337ea6d10d4e --- /dev/null +++ b/pac/atsaml22j/src/port/dirtgl.rs @@ -0,0 +1,63 @@ +#[doc = "Register `DIRTGL%s` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DIRTGL%s` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Direction Toggle\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dirtgl](index.html) module"] +pub struct DIRTGL_SPEC; +impl crate::RegisterSpec for DIRTGL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [dirtgl::R](R) reader structure"] +impl crate::Readable for DIRTGL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dirtgl::W](W) writer structure"] +impl crate::Writable for DIRTGL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DIRTGL%s to value 0"] +impl crate::Resettable for DIRTGL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/port/evctrl.rs b/pac/atsaml22j/src/port/evctrl.rs new file mode 100644 index 000000000000..1b6dcd2a86cc --- /dev/null +++ b/pac/atsaml22j/src/port/evctrl.rs @@ -0,0 +1,245 @@ +#[doc = "Register `EVCTRL%s` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL%s` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PID0` reader - Port Event Pin Identifier 0"] +pub type PID0_R = crate::FieldReader; +#[doc = "Field `PID0` writer - Port Event Pin Identifier 0"] +pub type PID0_W<'a, const O: u8> = crate::FieldWriter<'a, u32, EVCTRL_SPEC, u8, u8, 5, O>; +#[doc = "Field `EVACT0` reader - Port Event Action 0"] +pub type EVACT0_R = crate::FieldReader; +#[doc = "Field `EVACT0` writer - Port Event Action 0"] +pub type EVACT0_W<'a, const O: u8> = crate::FieldWriter<'a, u32, EVCTRL_SPEC, u8, u8, 2, O>; +#[doc = "Field `PORTEI0` reader - Port Event Enable Input 0"] +pub type PORTEI0_R = crate::BitReader; +#[doc = "Field `PORTEI0` writer - Port Event Enable Input 0"] +pub type PORTEI0_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVCTRL_SPEC, bool, O>; +#[doc = "Field `PID1` reader - Port Event Pin Identifier 1"] +pub type PID1_R = crate::FieldReader; +#[doc = "Field `PID1` writer - Port Event Pin Identifier 1"] +pub type PID1_W<'a, const O: u8> = crate::FieldWriter<'a, u32, EVCTRL_SPEC, u8, u8, 5, O>; +#[doc = "Field `EVACT1` reader - Port Event Action 1"] +pub type EVACT1_R = crate::FieldReader; +#[doc = "Field `EVACT1` writer - Port Event Action 1"] +pub type EVACT1_W<'a, const O: u8> = crate::FieldWriter<'a, u32, EVCTRL_SPEC, u8, u8, 2, O>; +#[doc = "Field `PORTEI1` reader - Port Event Enable Input 1"] +pub type PORTEI1_R = crate::BitReader; +#[doc = "Field `PORTEI1` writer - Port Event Enable Input 1"] +pub type PORTEI1_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVCTRL_SPEC, bool, O>; +#[doc = "Field `PID2` reader - Port Event Pin Identifier 2"] +pub type PID2_R = crate::FieldReader; +#[doc = "Field `PID2` writer - Port Event Pin Identifier 2"] +pub type PID2_W<'a, const O: u8> = crate::FieldWriter<'a, u32, EVCTRL_SPEC, u8, u8, 5, O>; +#[doc = "Field `EVACT2` reader - Port Event Action 2"] +pub type EVACT2_R = crate::FieldReader; +#[doc = "Field `EVACT2` writer - Port Event Action 2"] +pub type EVACT2_W<'a, const O: u8> = crate::FieldWriter<'a, u32, EVCTRL_SPEC, u8, u8, 2, O>; +#[doc = "Field `PORTEI2` reader - Port Event Enable Input 2"] +pub type PORTEI2_R = crate::BitReader; +#[doc = "Field `PORTEI2` writer - Port Event Enable Input 2"] +pub type PORTEI2_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVCTRL_SPEC, bool, O>; +#[doc = "Field `PID3` reader - Port Event Pin Identifier 3"] +pub type PID3_R = crate::FieldReader; +#[doc = "Field `PID3` writer - Port Event Pin Identifier 3"] +pub type PID3_W<'a, const O: u8> = crate::FieldWriter<'a, u32, EVCTRL_SPEC, u8, u8, 5, O>; +#[doc = "Field `EVACT3` reader - Port Event Action 3"] +pub type EVACT3_R = crate::FieldReader; +#[doc = "Field `EVACT3` writer - Port Event Action 3"] +pub type EVACT3_W<'a, const O: u8> = crate::FieldWriter<'a, u32, EVCTRL_SPEC, u8, u8, 2, O>; +#[doc = "Field `PORTEI3` reader - Port Event Enable Input 3"] +pub type PORTEI3_R = crate::BitReader; +#[doc = "Field `PORTEI3` writer - Port Event Enable Input 3"] +pub type PORTEI3_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVCTRL_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:4 - Port Event Pin Identifier 0"] + #[inline(always)] + pub fn pid0(&self) -> PID0_R { + PID0_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:6 - Port Event Action 0"] + #[inline(always)] + pub fn evact0(&self) -> EVACT0_R { + EVACT0_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - Port Event Enable Input 0"] + #[inline(always)] + pub fn portei0(&self) -> PORTEI0_R { + PORTEI0_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:12 - Port Event Pin Identifier 1"] + #[inline(always)] + pub fn pid1(&self) -> PID1_R { + PID1_R::new(((self.bits >> 8) & 0x1f) as u8) + } + #[doc = "Bits 13:14 - Port Event Action 1"] + #[inline(always)] + pub fn evact1(&self) -> EVACT1_R { + EVACT1_R::new(((self.bits >> 13) & 3) as u8) + } + #[doc = "Bit 15 - Port Event Enable Input 1"] + #[inline(always)] + pub fn portei1(&self) -> PORTEI1_R { + PORTEI1_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:20 - Port Event Pin Identifier 2"] + #[inline(always)] + pub fn pid2(&self) -> PID2_R { + PID2_R::new(((self.bits >> 16) & 0x1f) as u8) + } + #[doc = "Bits 21:22 - Port Event Action 2"] + #[inline(always)] + pub fn evact2(&self) -> EVACT2_R { + EVACT2_R::new(((self.bits >> 21) & 3) as u8) + } + #[doc = "Bit 23 - Port Event Enable Input 2"] + #[inline(always)] + pub fn portei2(&self) -> PORTEI2_R { + PORTEI2_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bits 24:28 - Port Event Pin Identifier 3"] + #[inline(always)] + pub fn pid3(&self) -> PID3_R { + PID3_R::new(((self.bits >> 24) & 0x1f) as u8) + } + #[doc = "Bits 29:30 - Port Event Action 3"] + #[inline(always)] + pub fn evact3(&self) -> EVACT3_R { + EVACT3_R::new(((self.bits >> 29) & 3) as u8) + } + #[doc = "Bit 31 - Port Event Enable Input 3"] + #[inline(always)] + pub fn portei3(&self) -> PORTEI3_R { + PORTEI3_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Port Event Pin Identifier 0"] + #[inline(always)] + #[must_use] + pub fn pid0(&mut self) -> PID0_W<0> { + PID0_W::new(self) + } + #[doc = "Bits 5:6 - Port Event Action 0"] + #[inline(always)] + #[must_use] + pub fn evact0(&mut self) -> EVACT0_W<5> { + EVACT0_W::new(self) + } + #[doc = "Bit 7 - Port Event Enable Input 0"] + #[inline(always)] + #[must_use] + pub fn portei0(&mut self) -> PORTEI0_W<7> { + PORTEI0_W::new(self) + } + #[doc = "Bits 8:12 - Port Event Pin Identifier 1"] + #[inline(always)] + #[must_use] + pub fn pid1(&mut self) -> PID1_W<8> { + PID1_W::new(self) + } + #[doc = "Bits 13:14 - Port Event Action 1"] + #[inline(always)] + #[must_use] + pub fn evact1(&mut self) -> EVACT1_W<13> { + EVACT1_W::new(self) + } + #[doc = "Bit 15 - Port Event Enable Input 1"] + #[inline(always)] + #[must_use] + pub fn portei1(&mut self) -> PORTEI1_W<15> { + PORTEI1_W::new(self) + } + #[doc = "Bits 16:20 - Port Event Pin Identifier 2"] + #[inline(always)] + #[must_use] + pub fn pid2(&mut self) -> PID2_W<16> { + PID2_W::new(self) + } + #[doc = "Bits 21:22 - Port Event Action 2"] + #[inline(always)] + #[must_use] + pub fn evact2(&mut self) -> EVACT2_W<21> { + EVACT2_W::new(self) + } + #[doc = "Bit 23 - Port Event Enable Input 2"] + #[inline(always)] + #[must_use] + pub fn portei2(&mut self) -> PORTEI2_W<23> { + PORTEI2_W::new(self) + } + #[doc = "Bits 24:28 - Port Event Pin Identifier 3"] + #[inline(always)] + #[must_use] + pub fn pid3(&mut self) -> PID3_W<24> { + PID3_W::new(self) + } + #[doc = "Bits 29:30 - Port Event Action 3"] + #[inline(always)] + #[must_use] + pub fn evact3(&mut self) -> EVACT3_W<29> { + EVACT3_W::new(self) + } + #[doc = "Bit 31 - Port Event Enable Input 3"] + #[inline(always)] + #[must_use] + pub fn portei3(&mut self) -> PORTEI3_W<31> { + PORTEI3_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Input Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EVCTRL%s to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/port/in_.rs b/pac/atsaml22j/src/port/in_.rs new file mode 100644 index 000000000000..e8ce1ac053ca --- /dev/null +++ b/pac/atsaml22j/src/port/in_.rs @@ -0,0 +1,28 @@ +#[doc = "Register `IN%s` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Data Input Value\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [in_](index.html) module"] +pub struct IN_SPEC; +impl crate::RegisterSpec for IN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [in_::R](R) reader structure"] +impl crate::Readable for IN_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets IN%s to value 0"] +impl crate::Resettable for IN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/port/out.rs b/pac/atsaml22j/src/port/out.rs new file mode 100644 index 000000000000..11fdf1422d8f --- /dev/null +++ b/pac/atsaml22j/src/port/out.rs @@ -0,0 +1,63 @@ +#[doc = "Register `OUT%s` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OUT%s` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Output Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [out](index.html) module"] +pub struct OUT_SPEC; +impl crate::RegisterSpec for OUT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [out::R](R) reader structure"] +impl crate::Readable for OUT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [out::W](W) writer structure"] +impl crate::Writable for OUT_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUT%s to value 0"] +impl crate::Resettable for OUT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/port/outclr.rs b/pac/atsaml22j/src/port/outclr.rs new file mode 100644 index 000000000000..074e90a6ab66 --- /dev/null +++ b/pac/atsaml22j/src/port/outclr.rs @@ -0,0 +1,63 @@ +#[doc = "Register `OUTCLR%s` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OUTCLR%s` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Output Value Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [outclr](index.html) module"] +pub struct OUTCLR_SPEC; +impl crate::RegisterSpec for OUTCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [outclr::R](R) reader structure"] +impl crate::Readable for OUTCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [outclr::W](W) writer structure"] +impl crate::Writable for OUTCLR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUTCLR%s to value 0"] +impl crate::Resettable for OUTCLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/port/outset.rs b/pac/atsaml22j/src/port/outset.rs new file mode 100644 index 000000000000..5cea0285d144 --- /dev/null +++ b/pac/atsaml22j/src/port/outset.rs @@ -0,0 +1,63 @@ +#[doc = "Register `OUTSET%s` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OUTSET%s` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Output Value Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [outset](index.html) module"] +pub struct OUTSET_SPEC; +impl crate::RegisterSpec for OUTSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [outset::R](R) reader structure"] +impl crate::Readable for OUTSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [outset::W](W) writer structure"] +impl crate::Writable for OUTSET_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUTSET%s to value 0"] +impl crate::Resettable for OUTSET_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/port/outtgl.rs b/pac/atsaml22j/src/port/outtgl.rs new file mode 100644 index 000000000000..c5ac0ef2f079 --- /dev/null +++ b/pac/atsaml22j/src/port/outtgl.rs @@ -0,0 +1,63 @@ +#[doc = "Register `OUTTGL%s` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `OUTTGL%s` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +impl W { + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Data Output Value Toggle\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [outtgl](index.html) module"] +pub struct OUTTGL_SPEC; +impl crate::RegisterSpec for OUTTGL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [outtgl::R](R) reader structure"] +impl crate::Readable for OUTTGL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [outtgl::W](W) writer structure"] +impl crate::Writable for OUTTGL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets OUTTGL%s to value 0"] +impl crate::Resettable for OUTTGL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/port/pincfg0_.rs b/pac/atsaml22j/src/port/pincfg0_.rs new file mode 100644 index 000000000000..909d344ae16d --- /dev/null +++ b/pac/atsaml22j/src/port/pincfg0_.rs @@ -0,0 +1,118 @@ +#[doc = "Register `PINCFG0_%s` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PINCFG0_%s` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PMUXEN` reader - Select Peripheral Multiplexer"] +pub type PMUXEN_R = crate::BitReader; +#[doc = "Field `PMUXEN` writer - Select Peripheral Multiplexer"] +pub type PMUXEN_W<'a, const O: u8> = crate::BitWriter<'a, u8, PINCFG0__SPEC, bool, O>; +#[doc = "Field `INEN` reader - Input Enable"] +pub type INEN_R = crate::BitReader; +#[doc = "Field `INEN` writer - Input Enable"] +pub type INEN_W<'a, const O: u8> = crate::BitWriter<'a, u8, PINCFG0__SPEC, bool, O>; +#[doc = "Field `PULLEN` reader - Pull Enable"] +pub type PULLEN_R = crate::BitReader; +#[doc = "Field `PULLEN` writer - Pull Enable"] +pub type PULLEN_W<'a, const O: u8> = crate::BitWriter<'a, u8, PINCFG0__SPEC, bool, O>; +#[doc = "Field `DRVSTR` writer - Output Driver Strength Selection"] +pub type DRVSTR_W<'a, const O: u8> = crate::BitWriter<'a, u8, PINCFG0__SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Select Peripheral Multiplexer"] + #[inline(always)] + pub fn pmuxen(&self) -> PMUXEN_R { + PMUXEN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Input Enable"] + #[inline(always)] + pub fn inen(&self) -> INEN_R { + INEN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Pull Enable"] + #[inline(always)] + pub fn pullen(&self) -> PULLEN_R { + PULLEN_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Select Peripheral Multiplexer"] + #[inline(always)] + #[must_use] + pub fn pmuxen(&mut self) -> PMUXEN_W<0> { + PMUXEN_W::new(self) + } + #[doc = "Bit 1 - Input Enable"] + #[inline(always)] + #[must_use] + pub fn inen(&mut self) -> INEN_W<1> { + INEN_W::new(self) + } + #[doc = "Bit 2 - Pull Enable"] + #[inline(always)] + #[must_use] + pub fn pullen(&mut self) -> PULLEN_W<2> { + PULLEN_W::new(self) + } + #[doc = "Bit 6 - Output Driver Strength Selection"] + #[inline(always)] + #[must_use] + pub fn drvstr(&mut self) -> DRVSTR_W<6> { + DRVSTR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pin Configuration n - Group 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pincfg0_](index.html) module"] +pub struct PINCFG0__SPEC; +impl crate::RegisterSpec for PINCFG0__SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [pincfg0_::R](R) reader structure"] +impl crate::Readable for PINCFG0__SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pincfg0_::W](W) writer structure"] +impl crate::Writable for PINCFG0__SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PINCFG0_%s to value 0"] +impl crate::Resettable for PINCFG0__SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/port/pmux0_.rs b/pac/atsaml22j/src/port/pmux0_.rs new file mode 100644 index 000000000000..c6b9bd374436 --- /dev/null +++ b/pac/atsaml22j/src/port/pmux0_.rs @@ -0,0 +1,95 @@ +#[doc = "Register `PMUX0_%s` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PMUX0_%s` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PMUXE` reader - Peripheral Multiplexing for Even-Numbered Pin"] +pub type PMUXE_R = crate::FieldReader; +#[doc = "Field `PMUXE` writer - Peripheral Multiplexing for Even-Numbered Pin"] +pub type PMUXE_W<'a, const O: u8> = crate::FieldWriter<'a, u8, PMUX0__SPEC, u8, u8, 4, O>; +#[doc = "Field `PMUXO` reader - Peripheral Multiplexing for Odd-Numbered Pin"] +pub type PMUXO_R = crate::FieldReader; +#[doc = "Field `PMUXO` writer - Peripheral Multiplexing for Odd-Numbered Pin"] +pub type PMUXO_W<'a, const O: u8> = crate::FieldWriter<'a, u8, PMUX0__SPEC, u8, u8, 4, O>; +impl R { + #[doc = "Bits 0:3 - Peripheral Multiplexing for Even-Numbered Pin"] + #[inline(always)] + pub fn pmuxe(&self) -> PMUXE_R { + PMUXE_R::new(self.bits & 0x0f) + } + #[doc = "Bits 4:7 - Peripheral Multiplexing for Odd-Numbered Pin"] + #[inline(always)] + pub fn pmuxo(&self) -> PMUXO_R { + PMUXO_R::new((self.bits >> 4) & 0x0f) + } +} +impl W { + #[doc = "Bits 0:3 - Peripheral Multiplexing for Even-Numbered Pin"] + #[inline(always)] + #[must_use] + pub fn pmuxe(&mut self) -> PMUXE_W<0> { + PMUXE_W::new(self) + } + #[doc = "Bits 4:7 - Peripheral Multiplexing for Odd-Numbered Pin"] + #[inline(always)] + #[must_use] + pub fn pmuxo(&mut self) -> PMUXO_W<4> { + PMUXO_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Peripheral Multiplexing n - Group 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pmux0_](index.html) module"] +pub struct PMUX0__SPEC; +impl crate::RegisterSpec for PMUX0__SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [pmux0_::R](R) reader structure"] +impl crate::Readable for PMUX0__SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pmux0_::W](W) writer structure"] +impl crate::Writable for PMUX0__SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PMUX0_%s to value 0"] +impl crate::Resettable for PMUX0__SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/port/wrconfig.rs b/pac/atsaml22j/src/port/wrconfig.rs new file mode 100644 index 000000000000..d6b81743f7d6 --- /dev/null +++ b/pac/atsaml22j/src/port/wrconfig.rs @@ -0,0 +1,116 @@ +#[doc = "Register `WRCONFIG%s` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PINMASK` writer - Pin Mask for Multiple Pin Configuration"] +pub type PINMASK_W<'a, const O: u8> = crate::FieldWriter<'a, u32, WRCONFIG_SPEC, u16, u16, 16, O>; +#[doc = "Field `PMUXEN` writer - Select Peripheral Multiplexer"] +pub type PMUXEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, WRCONFIG_SPEC, bool, O>; +#[doc = "Field `INEN` writer - Input Enable"] +pub type INEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, WRCONFIG_SPEC, bool, O>; +#[doc = "Field `PULLEN` writer - Pull Enable"] +pub type PULLEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, WRCONFIG_SPEC, bool, O>; +#[doc = "Field `DRVSTR` writer - Output Driver Strength Selection"] +pub type DRVSTR_W<'a, const O: u8> = crate::BitWriter<'a, u32, WRCONFIG_SPEC, bool, O>; +#[doc = "Field `PMUX` writer - Peripheral Multiplexing Template"] +pub type PMUX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, WRCONFIG_SPEC, u8, u8, 4, O>; +#[doc = "Field `WRPMUX` writer - Write PMUX Registers"] +pub type WRPMUX_W<'a, const O: u8> = crate::BitWriter<'a, u32, WRCONFIG_SPEC, bool, O>; +#[doc = "Field `WRPINCFG` writer - Write PINCFG Registers"] +pub type WRPINCFG_W<'a, const O: u8> = crate::BitWriter<'a, u32, WRCONFIG_SPEC, bool, O>; +#[doc = "Field `HWSEL` writer - Half-Word Select"] +pub type HWSEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, WRCONFIG_SPEC, bool, O>; +impl W { + #[doc = "Bits 0:15 - Pin Mask for Multiple Pin Configuration"] + #[inline(always)] + #[must_use] + pub fn pinmask(&mut self) -> PINMASK_W<0> { + PINMASK_W::new(self) + } + #[doc = "Bit 16 - Select Peripheral Multiplexer"] + #[inline(always)] + #[must_use] + pub fn pmuxen(&mut self) -> PMUXEN_W<16> { + PMUXEN_W::new(self) + } + #[doc = "Bit 17 - Input Enable"] + #[inline(always)] + #[must_use] + pub fn inen(&mut self) -> INEN_W<17> { + INEN_W::new(self) + } + #[doc = "Bit 18 - Pull Enable"] + #[inline(always)] + #[must_use] + pub fn pullen(&mut self) -> PULLEN_W<18> { + PULLEN_W::new(self) + } + #[doc = "Bit 22 - Output Driver Strength Selection"] + #[inline(always)] + #[must_use] + pub fn drvstr(&mut self) -> DRVSTR_W<22> { + DRVSTR_W::new(self) + } + #[doc = "Bits 24:27 - Peripheral Multiplexing Template"] + #[inline(always)] + #[must_use] + pub fn pmux(&mut self) -> PMUX_W<24> { + PMUX_W::new(self) + } + #[doc = "Bit 28 - Write PMUX Registers"] + #[inline(always)] + #[must_use] + pub fn wrpmux(&mut self) -> WRPMUX_W<28> { + WRPMUX_W::new(self) + } + #[doc = "Bit 30 - Write PINCFG Registers"] + #[inline(always)] + #[must_use] + pub fn wrpincfg(&mut self) -> WRPINCFG_W<30> { + WRPINCFG_W::new(self) + } + #[doc = "Bit 31 - Half-Word Select"] + #[inline(always)] + #[must_use] + pub fn hwsel(&mut self) -> HWSEL_W<31> { + HWSEL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Write Configuration\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wrconfig](index.html) module"] +pub struct WRCONFIG_SPEC; +impl crate::RegisterSpec for WRCONFIG_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [wrconfig::W](W) writer structure"] +impl crate::Writable for WRCONFIG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets WRCONFIG%s to value 0"] +impl crate::Resettable for WRCONFIG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/rstc.rs b/pac/atsaml22j/src/rstc.rs new file mode 100644 index 000000000000..c5a01f750ed2 --- /dev/null +++ b/pac/atsaml22j/src/rstc.rs @@ -0,0 +1,17 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Reset Cause"] + pub rcause: RCAUSE, + _reserved1: [u8; 0x01], + #[doc = "0x02 - Backup Exit Source"] + pub bkupexit: BKUPEXIT, +} +#[doc = "RCAUSE (r) register accessor: an alias for `Reg`"] +pub type RCAUSE = crate::Reg; +#[doc = "Reset Cause"] +pub mod rcause; +#[doc = "BKUPEXIT (r) register accessor: an alias for `Reg`"] +pub type BKUPEXIT = crate::Reg; +#[doc = "Backup Exit Source"] +pub mod bkupexit; diff --git a/pac/atsaml22j/src/rstc/bkupexit.rs b/pac/atsaml22j/src/rstc/bkupexit.rs new file mode 100644 index 000000000000..e53a29bf85fb --- /dev/null +++ b/pac/atsaml22j/src/rstc/bkupexit.rs @@ -0,0 +1,44 @@ +#[doc = "Register `BKUPEXIT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `RTC` reader - Real Timer Counter Interrupt"] +pub type RTC_R = crate::BitReader; +#[doc = "Field `BBPS` reader - Battery Backup Power Switch"] +pub type BBPS_R = crate::BitReader; +impl R { + #[doc = "Bit 1 - Real Timer Counter Interrupt"] + #[inline(always)] + pub fn rtc(&self) -> RTC_R { + RTC_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Battery Backup Power Switch"] + #[inline(always)] + pub fn bbps(&self) -> BBPS_R { + BBPS_R::new(((self.bits >> 2) & 1) != 0) + } +} +#[doc = "Backup Exit Source\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bkupexit](index.html) module"] +pub struct BKUPEXIT_SPEC; +impl crate::RegisterSpec for BKUPEXIT_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [bkupexit::R](R) reader structure"] +impl crate::Readable for BKUPEXIT_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets BKUPEXIT to value 0"] +impl crate::Resettable for BKUPEXIT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/rstc/rcause.rs b/pac/atsaml22j/src/rstc/rcause.rs new file mode 100644 index 000000000000..eb896332a340 --- /dev/null +++ b/pac/atsaml22j/src/rstc/rcause.rs @@ -0,0 +1,79 @@ +#[doc = "Register `RCAUSE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `POR` reader - Power On Reset"] +pub type POR_R = crate::BitReader; +#[doc = "Field `BODCORE` reader - Brown Out CORE Detector Reset"] +pub type BODCORE_R = crate::BitReader; +#[doc = "Field `BODVDD` reader - Brown Out VDD Detector Reset"] +pub type BODVDD_R = crate::BitReader; +#[doc = "Field `EXT` reader - External Reset"] +pub type EXT_R = crate::BitReader; +#[doc = "Field `WDT` reader - Watchdog Reset"] +pub type WDT_R = crate::BitReader; +#[doc = "Field `SYST` reader - System Reset Request"] +pub type SYST_R = crate::BitReader; +#[doc = "Field `BACKUP` reader - Backup Reset"] +pub type BACKUP_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Power On Reset"] + #[inline(always)] + pub fn por(&self) -> POR_R { + POR_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Brown Out CORE Detector Reset"] + #[inline(always)] + pub fn bodcore(&self) -> BODCORE_R { + BODCORE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Brown Out VDD Detector Reset"] + #[inline(always)] + pub fn bodvdd(&self) -> BODVDD_R { + BODVDD_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - External Reset"] + #[inline(always)] + pub fn ext(&self) -> EXT_R { + EXT_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Watchdog Reset"] + #[inline(always)] + pub fn wdt(&self) -> WDT_R { + WDT_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - System Reset Request"] + #[inline(always)] + pub fn syst(&self) -> SYST_R { + SYST_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Backup Reset"] + #[inline(always)] + pub fn backup(&self) -> BACKUP_R { + BACKUP_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[doc = "Reset Cause\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rcause](index.html) module"] +pub struct RCAUSE_SPEC; +impl crate::RegisterSpec for RCAUSE_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [rcause::R](R) reader structure"] +impl crate::Readable for RCAUSE_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RCAUSE to value 0"] +impl crate::Resettable for RCAUSE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/rtc.rs b/pac/atsaml22j/src/rtc.rs new file mode 100644 index 000000000000..14f9360d82d6 --- /dev/null +++ b/pac/atsaml22j/src/rtc.rs @@ -0,0 +1,37 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved_0_mode0: [u8; 0xa0], +} +impl RegisterBlock { + #[doc = "0x00..0xa0 - Clock/Calendar with Alarm"] + #[inline(always)] + pub const fn mode2(&self) -> &MODE2 { + unsafe { &*(self as *const Self).cast::().add(0usize).cast() } + } + #[doc = "0x00..0xa0 - 16-bit Counter with Two 16-bit Compares"] + #[inline(always)] + pub const fn mode1(&self) -> &MODE1 { + unsafe { &*(self as *const Self).cast::().add(0usize).cast() } + } + #[doc = "0x00..0xa0 - 32-bit Counter with Single 32-bit Compare"] + #[inline(always)] + pub const fn mode0(&self) -> &MODE0 { + unsafe { &*(self as *const Self).cast::().add(0usize).cast() } + } +} +#[doc = "32-bit Counter with Single 32-bit Compare"] +pub use self::mode0::MODE0; +#[doc = r"Cluster"] +#[doc = "32-bit Counter with Single 32-bit Compare"] +pub mod mode0; +#[doc = "16-bit Counter with Two 16-bit Compares"] +pub use self::mode1::MODE1; +#[doc = r"Cluster"] +#[doc = "16-bit Counter with Two 16-bit Compares"] +pub mod mode1; +#[doc = "Clock/Calendar with Alarm"] +pub use self::mode2::MODE2; +#[doc = r"Cluster"] +#[doc = "Clock/Calendar with Alarm"] +pub mod mode2; diff --git a/pac/atsaml22j/src/rtc/mode0.rs b/pac/atsaml22j/src/rtc/mode0.rs new file mode 100644 index 000000000000..09e981d80349 --- /dev/null +++ b/pac/atsaml22j/src/rtc/mode0.rs @@ -0,0 +1,106 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct MODE0 { + #[doc = "0x00 - MODE0 Control A"] + pub ctrla: CTRLA, + #[doc = "0x02 - MODE0 Control B"] + pub ctrlb: CTRLB, + #[doc = "0x04 - MODE0 Event Control"] + pub evctrl: EVCTRL, + #[doc = "0x08 - MODE0 Interrupt Enable Clear"] + pub intenclr: INTENCLR, + #[doc = "0x0a - MODE0 Interrupt Enable Set"] + pub intenset: INTENSET, + #[doc = "0x0c - MODE0 Interrupt Flag Status and Clear"] + pub intflag: INTFLAG, + #[doc = "0x0e - Debug Control"] + pub dbgctrl: DBGCTRL, + _reserved7: [u8; 0x01], + #[doc = "0x10 - MODE0 Synchronization Busy Status"] + pub syncbusy: SYNCBUSY, + #[doc = "0x14 - Frequency Correction"] + pub freqcorr: FREQCORR, + _reserved9: [u8; 0x03], + #[doc = "0x18 - MODE0 Counter Value"] + pub count: COUNT, + _reserved10: [u8; 0x04], + #[doc = "0x20 - MODE0 Compare n Value"] + pub comp: [COMP; 1], + _reserved11: [u8; 0x1c], + #[doc = "0x40..0x48 - General Purpose"] + pub gp: [GP; 2], + _reserved12: [u8; 0x18], + #[doc = "0x60 - Tamper Control"] + pub tampctrl: TAMPCTRL, + #[doc = "0x64 - MODE0 Timestamp"] + pub timestamp: TIMESTAMP, + #[doc = "0x68 - Tamper ID"] + pub tampid: TAMPID, + _reserved15: [u8; 0x14], + #[doc = "0x80..0xa0 - Backup"] + pub bkup: [BKUP; 8], +} +#[doc = "CTRLA (rw) register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "MODE0 Control A"] +pub mod ctrla; +#[doc = "CTRLB (rw) register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "MODE0 Control B"] +pub mod ctrlb; +#[doc = "EVCTRL (rw) register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "MODE0 Event Control"] +pub mod evctrl; +#[doc = "INTENCLR (rw) register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "MODE0 Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET (rw) register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "MODE0 Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG (rw) register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "MODE0 Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "DBGCTRL (rw) register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY (r) register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "MODE0 Synchronization Busy Status"] +pub mod syncbusy; +#[doc = "FREQCORR (rw) register accessor: an alias for `Reg`"] +pub type FREQCORR = crate::Reg; +#[doc = "Frequency Correction"] +pub mod freqcorr; +#[doc = "COUNT (rw) register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "MODE0 Counter Value"] +pub mod count; +#[doc = "COMP (rw) register accessor: an alias for `Reg`"] +pub type COMP = crate::Reg; +#[doc = "MODE0 Compare n Value"] +pub mod comp; +#[doc = "GP (rw) register accessor: an alias for `Reg`"] +pub type GP = crate::Reg; +#[doc = "General Purpose"] +pub mod gp; +#[doc = "TAMPCTRL (rw) register accessor: an alias for `Reg`"] +pub type TAMPCTRL = crate::Reg; +#[doc = "Tamper Control"] +pub mod tampctrl; +#[doc = "TIMESTAMP (r) register accessor: an alias for `Reg`"] +pub type TIMESTAMP = crate::Reg; +#[doc = "MODE0 Timestamp"] +pub mod timestamp; +#[doc = "TAMPID (rw) register accessor: an alias for `Reg`"] +pub type TAMPID = crate::Reg; +#[doc = "Tamper ID"] +pub mod tampid; +#[doc = "BKUP (rw) register accessor: an alias for `Reg`"] +pub type BKUP = crate::Reg; +#[doc = "Backup"] +pub mod bkup; diff --git a/pac/atsaml22j/src/rtc/mode0/bkup.rs b/pac/atsaml22j/src/rtc/mode0/bkup.rs new file mode 100644 index 000000000000..0d0a909e0bec --- /dev/null +++ b/pac/atsaml22j/src/rtc/mode0/bkup.rs @@ -0,0 +1,80 @@ +#[doc = "Register `BKUP%s` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BKUP%s` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BKUP` reader - Backup"] +pub type BKUP_R = crate::FieldReader; +#[doc = "Field `BKUP` writer - Backup"] +pub type BKUP_W<'a, const O: u8> = crate::FieldWriter<'a, u32, BKUP_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - Backup"] + #[inline(always)] + pub fn bkup(&self) -> BKUP_R { + BKUP_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Backup"] + #[inline(always)] + #[must_use] + pub fn bkup(&mut self) -> BKUP_W<0> { + BKUP_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Backup\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bkup](index.html) module"] +pub struct BKUP_SPEC; +impl crate::RegisterSpec for BKUP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [bkup::R](R) reader structure"] +impl crate::Readable for BKUP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [bkup::W](W) writer structure"] +impl crate::Writable for BKUP_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BKUP%s to value 0"] +impl crate::Resettable for BKUP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/rtc/mode0/comp.rs b/pac/atsaml22j/src/rtc/mode0/comp.rs new file mode 100644 index 000000000000..96ca0f025e37 --- /dev/null +++ b/pac/atsaml22j/src/rtc/mode0/comp.rs @@ -0,0 +1,80 @@ +#[doc = "Register `COMP%s` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COMP%s` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP` reader - Compare Value"] +pub type COMP_R = crate::FieldReader; +#[doc = "Field `COMP` writer - Compare Value"] +pub type COMP_W<'a, const O: u8> = crate::FieldWriter<'a, u32, COMP_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - Compare Value"] + #[inline(always)] + pub fn comp(&self) -> COMP_R { + COMP_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Compare Value"] + #[inline(always)] + #[must_use] + pub fn comp(&mut self) -> COMP_W<0> { + COMP_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Compare n Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [comp](index.html) module"] +pub struct COMP_SPEC; +impl crate::RegisterSpec for COMP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [comp::R](R) reader structure"] +impl crate::Readable for COMP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [comp::W](W) writer structure"] +impl crate::Writable for COMP_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMP%s to value 0"] +impl crate::Resettable for COMP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/rtc/mode0/count.rs b/pac/atsaml22j/src/rtc/mode0/count.rs new file mode 100644 index 000000000000..80fbeb91d670 --- /dev/null +++ b/pac/atsaml22j/src/rtc/mode0/count.rs @@ -0,0 +1,80 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub type COUNT_R = crate::FieldReader; +#[doc = "Field `COUNT` writer - Counter Value"] +pub type COUNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, COUNT_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Counter Value"] + #[inline(always)] + #[must_use] + pub fn count(&mut self) -> COUNT_W<0> { + COUNT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Counter Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/rtc/mode0/ctrla.rs b/pac/atsaml22j/src/rtc/mode0/ctrla.rs new file mode 100644 index 000000000000..90b875edb68b --- /dev/null +++ b/pac/atsaml22j/src/rtc/mode0/ctrla.rs @@ -0,0 +1,418 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub type SWRST_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRLA_SPEC, bool, O>; +#[doc = "Field `ENABLE` reader - Enable"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - Enable"] +pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRLA_SPEC, bool, O>; +#[doc = "Field `MODE` reader - Operating Mode"] +pub type MODE_R = crate::FieldReader; +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum MODESELECT_A { + #[doc = "0: Mode 0: 32-bit Counter"] + COUNT32 = 0, + #[doc = "1: Mode 1: 16-bit Counter"] + COUNT16 = 1, + #[doc = "2: Mode 2: Clock/Calendar"] + CLOCK = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODESELECT_A) -> Self { + variant as _ + } +} +impl MODE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODESELECT_A::COUNT32), + 1 => Some(MODESELECT_A::COUNT16), + 2 => Some(MODESELECT_A::CLOCK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + *self == MODESELECT_A::COUNT32 + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + *self == MODESELECT_A::COUNT16 + } + #[doc = "Checks if the value of the field is `CLOCK`"] + #[inline(always)] + pub fn is_clock(&self) -> bool { + *self == MODESELECT_A::CLOCK + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub type MODE_W<'a, const O: u8> = crate::FieldWriter<'a, u16, CTRLA_SPEC, u8, MODESELECT_A, 2, O>; +impl<'a, const O: u8> MODE_W<'a, O> { + #[doc = "Mode 0: 32-bit Counter"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODESELECT_A::COUNT32) + } + #[doc = "Mode 1: 16-bit Counter"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODESELECT_A::COUNT16) + } + #[doc = "Mode 2: Clock/Calendar"] + #[inline(always)] + pub fn clock(self) -> &'a mut W { + self.variant(MODESELECT_A::CLOCK) + } +} +#[doc = "Field `MATCHCLR` reader - Clear on Match"] +pub type MATCHCLR_R = crate::BitReader; +#[doc = "Field `MATCHCLR` writer - Clear on Match"] +pub type MATCHCLR_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRLA_SPEC, bool, O>; +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub type PRESCALER_R = crate::FieldReader; +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum PRESCALERSELECT_A { + #[doc = "0: CLK_RTC_CNT = GCLK_RTC/1"] + OFF = 0, + #[doc = "1: CLK_RTC_CNT = GCLK_RTC/1"] + DIV1 = 1, + #[doc = "2: CLK_RTC_CNT = GCLK_RTC/2"] + DIV2 = 2, + #[doc = "3: CLK_RTC_CNT = GCLK_RTC/4"] + DIV4 = 3, + #[doc = "4: CLK_RTC_CNT = GCLK_RTC/8"] + DIV8 = 4, + #[doc = "5: CLK_RTC_CNT = GCLK_RTC/16"] + DIV16 = 5, + #[doc = "6: CLK_RTC_CNT = GCLK_RTC/32"] + DIV32 = 6, + #[doc = "7: CLK_RTC_CNT = GCLK_RTC/64"] + DIV64 = 7, + #[doc = "8: CLK_RTC_CNT = GCLK_RTC/128"] + DIV128 = 8, + #[doc = "9: CLK_RTC_CNT = GCLK_RTC/256"] + DIV256 = 9, + #[doc = "10: CLK_RTC_CNT = GCLK_RTC/512"] + DIV512 = 10, + #[doc = "11: CLK_RTC_CNT = GCLK_RTC/1024"] + DIV1024 = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALERSELECT_A) -> Self { + variant as _ + } +} +impl PRESCALER_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCALERSELECT_A::OFF), + 1 => Some(PRESCALERSELECT_A::DIV1), + 2 => Some(PRESCALERSELECT_A::DIV2), + 3 => Some(PRESCALERSELECT_A::DIV4), + 4 => Some(PRESCALERSELECT_A::DIV8), + 5 => Some(PRESCALERSELECT_A::DIV16), + 6 => Some(PRESCALERSELECT_A::DIV32), + 7 => Some(PRESCALERSELECT_A::DIV64), + 8 => Some(PRESCALERSELECT_A::DIV128), + 9 => Some(PRESCALERSELECT_A::DIV256), + 10 => Some(PRESCALERSELECT_A::DIV512), + 11 => Some(PRESCALERSELECT_A::DIV1024), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == PRESCALERSELECT_A::OFF + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + *self == PRESCALERSELECT_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + *self == PRESCALERSELECT_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + *self == PRESCALERSELECT_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + *self == PRESCALERSELECT_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + *self == PRESCALERSELECT_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + *self == PRESCALERSELECT_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + *self == PRESCALERSELECT_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + *self == PRESCALERSELECT_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + *self == PRESCALERSELECT_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV512`"] + #[inline(always)] + pub fn is_div512(&self) -> bool { + *self == PRESCALERSELECT_A::DIV512 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + *self == PRESCALERSELECT_A::DIV1024 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub type PRESCALER_W<'a, const O: u8> = + crate::FieldWriter<'a, u16, CTRLA_SPEC, u8, PRESCALERSELECT_A, 4, O>; +impl<'a, const O: u8> PRESCALER_W<'a, O> { + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::OFF) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV1) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV2) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV4) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV8) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV16) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV32) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV64) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV128) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV256) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/512"] + #[inline(always)] + pub fn div512(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV512) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV1024) + } +} +#[doc = "Field `BKTRST` reader - BKUP Registers Reset On Tamper Enable"] +pub type BKTRST_R = crate::BitReader; +#[doc = "Field `BKTRST` writer - BKUP Registers Reset On Tamper Enable"] +pub type BKTRST_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRLA_SPEC, bool, O>; +#[doc = "Field `GPTRST` reader - GP Registers Reset On Tamper Enable"] +pub type GPTRST_R = crate::BitReader; +#[doc = "Field `GPTRST` writer - GP Registers Reset On Tamper Enable"] +pub type GPTRST_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRLA_SPEC, bool, O>; +#[doc = "Field `COUNTSYNC` reader - Count Read Synchronization Enable"] +pub type COUNTSYNC_R = crate::BitReader; +#[doc = "Field `COUNTSYNC` writer - Count Read Synchronization Enable"] +pub type COUNTSYNC_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRLA_SPEC, bool, O>; +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bit 7 - Clear on Match"] + #[inline(always)] + pub fn matchclr(&self) -> MATCHCLR_R { + MATCHCLR_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 13 - BKUP Registers Reset On Tamper Enable"] + #[inline(always)] + pub fn bktrst(&self) -> BKTRST_R { + BKTRST_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - GP Registers Reset On Tamper Enable"] + #[inline(always)] + pub fn gptrst(&self) -> GPTRST_R { + GPTRST_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Count Read Synchronization Enable"] + #[inline(always)] + pub fn countsync(&self) -> COUNTSYNC_R { + COUNTSYNC_R::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + #[must_use] + pub fn swrst(&mut self) -> SWRST_W<0> { + SWRST_W::new(self) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W<1> { + ENABLE_W::new(self) + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> MODE_W<2> { + MODE_W::new(self) + } + #[doc = "Bit 7 - Clear on Match"] + #[inline(always)] + #[must_use] + pub fn matchclr(&mut self) -> MATCHCLR_W<7> { + MATCHCLR_W::new(self) + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + #[must_use] + pub fn prescaler(&mut self) -> PRESCALER_W<8> { + PRESCALER_W::new(self) + } + #[doc = "Bit 13 - BKUP Registers Reset On Tamper Enable"] + #[inline(always)] + #[must_use] + pub fn bktrst(&mut self) -> BKTRST_W<13> { + BKTRST_W::new(self) + } + #[doc = "Bit 14 - GP Registers Reset On Tamper Enable"] + #[inline(always)] + #[must_use] + pub fn gptrst(&mut self) -> GPTRST_W<14> { + GPTRST_W::new(self) + } + #[doc = "Bit 15 - Count Read Synchronization Enable"] + #[inline(always)] + #[must_use] + pub fn countsync(&mut self) -> COUNTSYNC_W<15> { + COUNTSYNC_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/rtc/mode0/ctrlb.rs b/pac/atsaml22j/src/rtc/mode0/ctrlb.rs new file mode 100644 index 000000000000..454524e5a9e9 --- /dev/null +++ b/pac/atsaml22j/src/rtc/mode0/ctrlb.rs @@ -0,0 +1,424 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GP0EN` reader - General Purpose 0 Enable"] +pub type GP0EN_R = crate::BitReader; +#[doc = "Field `GP0EN` writer - General Purpose 0 Enable"] +pub type GP0EN_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRLB_SPEC, bool, O>; +#[doc = "Field `DEBMAJ` reader - Debouncer Majority Enable"] +pub type DEBMAJ_R = crate::BitReader; +#[doc = "Field `DEBMAJ` writer - Debouncer Majority Enable"] +pub type DEBMAJ_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRLB_SPEC, bool, O>; +#[doc = "Field `DEBASYNC` reader - Debouncer Asynchronous Enable"] +pub type DEBASYNC_R = crate::BitReader; +#[doc = "Field `DEBASYNC` writer - Debouncer Asynchronous Enable"] +pub type DEBASYNC_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRLB_SPEC, bool, O>; +#[doc = "Field `RTCOUT` reader - RTC Output Enable"] +pub type RTCOUT_R = crate::BitReader; +#[doc = "Field `RTCOUT` writer - RTC Output Enable"] +pub type RTCOUT_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRLB_SPEC, bool, O>; +#[doc = "Field `DMAEN` reader - DMA Enable"] +pub type DMAEN_R = crate::BitReader; +#[doc = "Field `DMAEN` writer - DMA Enable"] +pub type DMAEN_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRLB_SPEC, bool, O>; +#[doc = "Field `DEBF` reader - Debounce Freqnuency"] +pub type DEBF_R = crate::FieldReader; +#[doc = "Debounce Freqnuency\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum DEBFSELECT_A { + #[doc = "0: CLK_RTC_DEB = CLK_RTC/2"] + DIV2 = 0, + #[doc = "1: CLK_RTC_DEB = CLK_RTC/4"] + DIV4 = 1, + #[doc = "2: CLK_RTC_DEB = CLK_RTC/8"] + DIV8 = 2, + #[doc = "3: CLK_RTC_DEB = CLK_RTC/16"] + DIV16 = 3, + #[doc = "4: CLK_RTC_DEB = CLK_RTC/32"] + DIV32 = 4, + #[doc = "5: CLK_RTC_DEB = CLK_RTC/64"] + DIV64 = 5, + #[doc = "6: CLK_RTC_DEB = CLK_RTC/128"] + DIV128 = 6, + #[doc = "7: CLK_RTC_DEB = CLK_RTC/256"] + DIV256 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DEBFSELECT_A) -> Self { + variant as _ + } +} +impl DEBF_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DEBFSELECT_A { + match self.bits { + 0 => DEBFSELECT_A::DIV2, + 1 => DEBFSELECT_A::DIV4, + 2 => DEBFSELECT_A::DIV8, + 3 => DEBFSELECT_A::DIV16, + 4 => DEBFSELECT_A::DIV32, + 5 => DEBFSELECT_A::DIV64, + 6 => DEBFSELECT_A::DIV128, + 7 => DEBFSELECT_A::DIV256, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + *self == DEBFSELECT_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + *self == DEBFSELECT_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + *self == DEBFSELECT_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + *self == DEBFSELECT_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + *self == DEBFSELECT_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + *self == DEBFSELECT_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + *self == DEBFSELECT_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + *self == DEBFSELECT_A::DIV256 + } +} +#[doc = "Field `DEBF` writer - Debounce Freqnuency"] +pub type DEBF_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u16, CTRLB_SPEC, u8, DEBFSELECT_A, 3, O>; +impl<'a, const O: u8> DEBF_W<'a, O> { + #[doc = "CLK_RTC_DEB = CLK_RTC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(DEBFSELECT_A::DIV2) + } + #[doc = "CLK_RTC_DEB = CLK_RTC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(DEBFSELECT_A::DIV4) + } + #[doc = "CLK_RTC_DEB = CLK_RTC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(DEBFSELECT_A::DIV8) + } + #[doc = "CLK_RTC_DEB = CLK_RTC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(DEBFSELECT_A::DIV16) + } + #[doc = "CLK_RTC_DEB = CLK_RTC/32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(DEBFSELECT_A::DIV32) + } + #[doc = "CLK_RTC_DEB = CLK_RTC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(DEBFSELECT_A::DIV64) + } + #[doc = "CLK_RTC_DEB = CLK_RTC/128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(DEBFSELECT_A::DIV128) + } + #[doc = "CLK_RTC_DEB = CLK_RTC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(DEBFSELECT_A::DIV256) + } +} +#[doc = "Field `ACTF` reader - Active Layer Freqnuency"] +pub type ACTF_R = crate::FieldReader; +#[doc = "Active Layer Freqnuency\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum ACTFSELECT_A { + #[doc = "0: CLK_RTC_OUT = CLK_RTC/2"] + DIV2 = 0, + #[doc = "1: CLK_RTC_OUT = CLK_RTC/4"] + DIV4 = 1, + #[doc = "2: CLK_RTC_OUT = CLK_RTC/8"] + DIV8 = 2, + #[doc = "3: CLK_RTC_OUT = CLK_RTC/16"] + DIV16 = 3, + #[doc = "4: CLK_RTC_OUT = CLK_RTC/32"] + DIV32 = 4, + #[doc = "5: CLK_RTC_OUT = CLK_RTC/64"] + DIV64 = 5, + #[doc = "6: CLK_RTC_OUT = CLK_RTC/128"] + DIV128 = 6, + #[doc = "7: CLK_RTC_OUT = CLK_RTC/256"] + DIV256 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ACTFSELECT_A) -> Self { + variant as _ + } +} +impl ACTF_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ACTFSELECT_A { + match self.bits { + 0 => ACTFSELECT_A::DIV2, + 1 => ACTFSELECT_A::DIV4, + 2 => ACTFSELECT_A::DIV8, + 3 => ACTFSELECT_A::DIV16, + 4 => ACTFSELECT_A::DIV32, + 5 => ACTFSELECT_A::DIV64, + 6 => ACTFSELECT_A::DIV128, + 7 => ACTFSELECT_A::DIV256, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + *self == ACTFSELECT_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + *self == ACTFSELECT_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + *self == ACTFSELECT_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + *self == ACTFSELECT_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + *self == ACTFSELECT_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + *self == ACTFSELECT_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + *self == ACTFSELECT_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + *self == ACTFSELECT_A::DIV256 + } +} +#[doc = "Field `ACTF` writer - Active Layer Freqnuency"] +pub type ACTF_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u16, CTRLB_SPEC, u8, ACTFSELECT_A, 3, O>; +impl<'a, const O: u8> ACTF_W<'a, O> { + #[doc = "CLK_RTC_OUT = CLK_RTC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(ACTFSELECT_A::DIV2) + } + #[doc = "CLK_RTC_OUT = CLK_RTC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(ACTFSELECT_A::DIV4) + } + #[doc = "CLK_RTC_OUT = CLK_RTC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(ACTFSELECT_A::DIV8) + } + #[doc = "CLK_RTC_OUT = CLK_RTC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(ACTFSELECT_A::DIV16) + } + #[doc = "CLK_RTC_OUT = CLK_RTC/32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(ACTFSELECT_A::DIV32) + } + #[doc = "CLK_RTC_OUT = CLK_RTC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(ACTFSELECT_A::DIV64) + } + #[doc = "CLK_RTC_OUT = CLK_RTC/128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(ACTFSELECT_A::DIV128) + } + #[doc = "CLK_RTC_OUT = CLK_RTC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(ACTFSELECT_A::DIV256) + } +} +impl R { + #[doc = "Bit 0 - General Purpose 0 Enable"] + #[inline(always)] + pub fn gp0en(&self) -> GP0EN_R { + GP0EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 4 - Debouncer Majority Enable"] + #[inline(always)] + pub fn debmaj(&self) -> DEBMAJ_R { + DEBMAJ_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Debouncer Asynchronous Enable"] + #[inline(always)] + pub fn debasync(&self) -> DEBASYNC_R { + DEBASYNC_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - RTC Output Enable"] + #[inline(always)] + pub fn rtcout(&self) -> RTCOUT_R { + RTCOUT_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - DMA Enable"] + #[inline(always)] + pub fn dmaen(&self) -> DMAEN_R { + DMAEN_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:10 - Debounce Freqnuency"] + #[inline(always)] + pub fn debf(&self) -> DEBF_R { + DEBF_R::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bits 12:14 - Active Layer Freqnuency"] + #[inline(always)] + pub fn actf(&self) -> ACTF_R { + ACTF_R::new(((self.bits >> 12) & 7) as u8) + } +} +impl W { + #[doc = "Bit 0 - General Purpose 0 Enable"] + #[inline(always)] + #[must_use] + pub fn gp0en(&mut self) -> GP0EN_W<0> { + GP0EN_W::new(self) + } + #[doc = "Bit 4 - Debouncer Majority Enable"] + #[inline(always)] + #[must_use] + pub fn debmaj(&mut self) -> DEBMAJ_W<4> { + DEBMAJ_W::new(self) + } + #[doc = "Bit 5 - Debouncer Asynchronous Enable"] + #[inline(always)] + #[must_use] + pub fn debasync(&mut self) -> DEBASYNC_W<5> { + DEBASYNC_W::new(self) + } + #[doc = "Bit 6 - RTC Output Enable"] + #[inline(always)] + #[must_use] + pub fn rtcout(&mut self) -> RTCOUT_W<6> { + RTCOUT_W::new(self) + } + #[doc = "Bit 7 - DMA Enable"] + #[inline(always)] + #[must_use] + pub fn dmaen(&mut self) -> DMAEN_W<7> { + DMAEN_W::new(self) + } + #[doc = "Bits 8:10 - Debounce Freqnuency"] + #[inline(always)] + #[must_use] + pub fn debf(&mut self) -> DEBF_W<8> { + DEBF_W::new(self) + } + #[doc = "Bits 12:14 - Active Layer Freqnuency"] + #[inline(always)] + #[must_use] + pub fn actf(&mut self) -> ACTF_W<12> { + ACTF_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/rtc/mode0/dbgctrl.rs b/pac/atsaml22j/src/rtc/mode0/dbgctrl.rs new file mode 100644 index 000000000000..271f8aa633ac --- /dev/null +++ b/pac/atsaml22j/src/rtc/mode0/dbgctrl.rs @@ -0,0 +1,80 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub type DBGRUN_R = crate::BitReader; +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub type DBGRUN_W<'a, const O: u8> = crate::BitWriter<'a, u8, DBGCTRL_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + #[must_use] + pub fn dbgrun(&mut self) -> DBGRUN_W<0> { + DBGRUN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/rtc/mode0/evctrl.rs b/pac/atsaml22j/src/rtc/mode0/evctrl.rs new file mode 100644 index 000000000000..85f43ba34c23 --- /dev/null +++ b/pac/atsaml22j/src/rtc/mode0/evctrl.rs @@ -0,0 +1,245 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PEREO0` reader - Periodic Interval 0 Event Output Enable"] +pub type PEREO0_R = crate::BitReader; +#[doc = "Field `PEREO0` writer - Periodic Interval 0 Event Output Enable"] +pub type PEREO0_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVCTRL_SPEC, bool, O>; +#[doc = "Field `PEREO1` reader - Periodic Interval 1 Event Output Enable"] +pub type PEREO1_R = crate::BitReader; +#[doc = "Field `PEREO1` writer - Periodic Interval 1 Event Output Enable"] +pub type PEREO1_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVCTRL_SPEC, bool, O>; +#[doc = "Field `PEREO2` reader - Periodic Interval 2 Event Output Enable"] +pub type PEREO2_R = crate::BitReader; +#[doc = "Field `PEREO2` writer - Periodic Interval 2 Event Output Enable"] +pub type PEREO2_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVCTRL_SPEC, bool, O>; +#[doc = "Field `PEREO3` reader - Periodic Interval 3 Event Output Enable"] +pub type PEREO3_R = crate::BitReader; +#[doc = "Field `PEREO3` writer - Periodic Interval 3 Event Output Enable"] +pub type PEREO3_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVCTRL_SPEC, bool, O>; +#[doc = "Field `PEREO4` reader - Periodic Interval 4 Event Output Enable"] +pub type PEREO4_R = crate::BitReader; +#[doc = "Field `PEREO4` writer - Periodic Interval 4 Event Output Enable"] +pub type PEREO4_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVCTRL_SPEC, bool, O>; +#[doc = "Field `PEREO5` reader - Periodic Interval 5 Event Output Enable"] +pub type PEREO5_R = crate::BitReader; +#[doc = "Field `PEREO5` writer - Periodic Interval 5 Event Output Enable"] +pub type PEREO5_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVCTRL_SPEC, bool, O>; +#[doc = "Field `PEREO6` reader - Periodic Interval 6 Event Output Enable"] +pub type PEREO6_R = crate::BitReader; +#[doc = "Field `PEREO6` writer - Periodic Interval 6 Event Output Enable"] +pub type PEREO6_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVCTRL_SPEC, bool, O>; +#[doc = "Field `PEREO7` reader - Periodic Interval 7 Event Output Enable"] +pub type PEREO7_R = crate::BitReader; +#[doc = "Field `PEREO7` writer - Periodic Interval 7 Event Output Enable"] +pub type PEREO7_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVCTRL_SPEC, bool, O>; +#[doc = "Field `CMPEO0` reader - Compare 0 Event Output Enable"] +pub type CMPEO0_R = crate::BitReader; +#[doc = "Field `CMPEO0` writer - Compare 0 Event Output Enable"] +pub type CMPEO0_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVCTRL_SPEC, bool, O>; +#[doc = "Field `TAMPEREO` reader - Tamper Event Output Enable"] +pub type TAMPEREO_R = crate::BitReader; +#[doc = "Field `TAMPEREO` writer - Tamper Event Output Enable"] +pub type TAMPEREO_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVCTRL_SPEC, bool, O>; +#[doc = "Field `OVFEO` reader - Overflow Event Output Enable"] +pub type OVFEO_R = crate::BitReader; +#[doc = "Field `OVFEO` writer - Overflow Event Output Enable"] +pub type OVFEO_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVCTRL_SPEC, bool, O>; +#[doc = "Field `TAMPEVEI` reader - Tamper Event Input Enable"] +pub type TAMPEVEI_R = crate::BitReader; +#[doc = "Field `TAMPEVEI` writer - Tamper Event Input Enable"] +pub type TAMPEVEI_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVCTRL_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&self) -> PEREO0_R { + PEREO0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&self) -> PEREO1_R { + PEREO1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&self) -> PEREO2_R { + PEREO2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&self) -> PEREO3_R { + PEREO3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&self) -> PEREO4_R { + PEREO4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&self) -> PEREO5_R { + PEREO5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&self) -> PEREO6_R { + PEREO6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&self) -> PEREO7_R { + PEREO7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Compare 0 Event Output Enable"] + #[inline(always)] + pub fn cmpeo0(&self) -> CMPEO0_R { + CMPEO0_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 14 - Tamper Event Output Enable"] + #[inline(always)] + pub fn tampereo(&self) -> TAMPEREO_R { + TAMPEREO_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Tamper Event Input Enable"] + #[inline(always)] + pub fn tampevei(&self) -> TAMPEVEI_R { + TAMPEVEI_R::new(((self.bits >> 16) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + #[must_use] + pub fn pereo0(&mut self) -> PEREO0_W<0> { + PEREO0_W::new(self) + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + #[must_use] + pub fn pereo1(&mut self) -> PEREO1_W<1> { + PEREO1_W::new(self) + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + #[must_use] + pub fn pereo2(&mut self) -> PEREO2_W<2> { + PEREO2_W::new(self) + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + #[must_use] + pub fn pereo3(&mut self) -> PEREO3_W<3> { + PEREO3_W::new(self) + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + #[must_use] + pub fn pereo4(&mut self) -> PEREO4_W<4> { + PEREO4_W::new(self) + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + #[must_use] + pub fn pereo5(&mut self) -> PEREO5_W<5> { + PEREO5_W::new(self) + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + #[must_use] + pub fn pereo6(&mut self) -> PEREO6_W<6> { + PEREO6_W::new(self) + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + #[must_use] + pub fn pereo7(&mut self) -> PEREO7_W<7> { + PEREO7_W::new(self) + } + #[doc = "Bit 8 - Compare 0 Event Output Enable"] + #[inline(always)] + #[must_use] + pub fn cmpeo0(&mut self) -> CMPEO0_W<8> { + CMPEO0_W::new(self) + } + #[doc = "Bit 14 - Tamper Event Output Enable"] + #[inline(always)] + #[must_use] + pub fn tampereo(&mut self) -> TAMPEREO_W<14> { + TAMPEREO_W::new(self) + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + #[must_use] + pub fn ovfeo(&mut self) -> OVFEO_W<15> { + OVFEO_W::new(self) + } + #[doc = "Bit 16 - Tamper Event Input Enable"] + #[inline(always)] + #[must_use] + pub fn tampevei(&mut self) -> TAMPEVEI_W<16> { + TAMPEVEI_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/rtc/mode0/freqcorr.rs b/pac/atsaml22j/src/rtc/mode0/freqcorr.rs new file mode 100644 index 000000000000..0a0b886b28f6 --- /dev/null +++ b/pac/atsaml22j/src/rtc/mode0/freqcorr.rs @@ -0,0 +1,95 @@ +#[doc = "Register `FREQCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FREQCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VALUE` reader - Correction Value"] +pub type VALUE_R = crate::FieldReader; +#[doc = "Field `VALUE` writer - Correction Value"] +pub type VALUE_W<'a, const O: u8> = crate::FieldWriter<'a, u8, FREQCORR_SPEC, u8, u8, 7, O>; +#[doc = "Field `SIGN` reader - Correction Sign"] +pub type SIGN_R = crate::BitReader; +#[doc = "Field `SIGN` writer - Correction Sign"] +pub type SIGN_W<'a, const O: u8> = crate::BitWriter<'a, u8, FREQCORR_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new(self.bits & 0x7f) + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&self) -> SIGN_R { + SIGN_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + #[must_use] + pub fn value(&mut self) -> VALUE_W<0> { + VALUE_W::new(self) + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + #[must_use] + pub fn sign(&mut self) -> SIGN_W<7> { + SIGN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Frequency Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [freqcorr](index.html) module"] +pub struct FREQCORR_SPEC; +impl crate::RegisterSpec for FREQCORR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [freqcorr::R](R) reader structure"] +impl crate::Readable for FREQCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [freqcorr::W](W) writer structure"] +impl crate::Writable for FREQCORR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FREQCORR to value 0"] +impl crate::Resettable for FREQCORR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/rtc/mode0/gp.rs b/pac/atsaml22j/src/rtc/mode0/gp.rs new file mode 100644 index 000000000000..c674475e018c --- /dev/null +++ b/pac/atsaml22j/src/rtc/mode0/gp.rs @@ -0,0 +1,80 @@ +#[doc = "Register `GP%s` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GP%s` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GP` reader - General Purpose"] +pub type GP_R = crate::FieldReader; +#[doc = "Field `GP` writer - General Purpose"] +pub type GP_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GP_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - General Purpose"] + #[inline(always)] + pub fn gp(&self) -> GP_R { + GP_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - General Purpose"] + #[inline(always)] + #[must_use] + pub fn gp(&mut self) -> GP_W<0> { + GP_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "General Purpose\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gp](index.html) module"] +pub struct GP_SPEC; +impl crate::RegisterSpec for GP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gp::R](R) reader structure"] +impl crate::Readable for GP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gp::W](W) writer structure"] +impl crate::Writable for GP_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GP%s to value 0"] +impl crate::Resettable for GP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/rtc/mode0/intenclr.rs b/pac/atsaml22j/src/rtc/mode0/intenclr.rs new file mode 100644 index 000000000000..d47e25e317f8 --- /dev/null +++ b/pac/atsaml22j/src/rtc/mode0/intenclr.rs @@ -0,0 +1,174 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` writer - Periodic Interval 0 Interrupt Enable"] +pub type PER0_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENCLR_SPEC, bool, O>; +#[doc = "Field `PER1` writer - Periodic Interval 1 Interrupt Enable"] +pub type PER1_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENCLR_SPEC, bool, O>; +#[doc = "Field `PER2` writer - Periodic Interval 2 Interrupt Enable"] +pub type PER2_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENCLR_SPEC, bool, O>; +#[doc = "Field `PER3` writer - Periodic Interval 3 Interrupt Enable"] +pub type PER3_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENCLR_SPEC, bool, O>; +#[doc = "Field `PER4` writer - Periodic Interval 4 Interrupt Enable"] +pub type PER4_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENCLR_SPEC, bool, O>; +#[doc = "Field `PER5` writer - Periodic Interval 5 Interrupt Enable"] +pub type PER5_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENCLR_SPEC, bool, O>; +#[doc = "Field `PER6` writer - Periodic Interval 6 Interrupt Enable"] +pub type PER6_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENCLR_SPEC, bool, O>; +#[doc = "Field `PER7` writer - Periodic Interval 7 Interrupt Enable"] +pub type PER7_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENCLR_SPEC, bool, O>; +#[doc = "Field `CMP0` reader - Compare 0 Interrupt Enable"] +pub type CMP0_R = crate::BitReader; +#[doc = "Field `CMP0` writer - Compare 0 Interrupt Enable"] +pub type CMP0_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENCLR_SPEC, bool, O>; +#[doc = "Field `TAMPER` reader - Tamper Enable"] +pub type TAMPER_R = crate::BitReader; +#[doc = "Field `TAMPER` writer - Tamper Enable"] +pub type TAMPER_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENCLR_SPEC, bool, O>; +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub type OVF_R = crate::BitReader; +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub type OVF_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENCLR_SPEC, bool, O>; +impl R { + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 14 - Tamper Enable"] + #[inline(always)] + pub fn tamper(&self) -> TAMPER_R { + TAMPER_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn per0(&mut self) -> PER0_W<0> { + PER0_W::new(self) + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn per1(&mut self) -> PER1_W<1> { + PER1_W::new(self) + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn per2(&mut self) -> PER2_W<2> { + PER2_W::new(self) + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn per3(&mut self) -> PER3_W<3> { + PER3_W::new(self) + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn per4(&mut self) -> PER4_W<4> { + PER4_W::new(self) + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn per5(&mut self) -> PER5_W<5> { + PER5_W::new(self) + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn per6(&mut self) -> PER6_W<6> { + PER6_W::new(self) + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn per7(&mut self) -> PER7_W<7> { + PER7_W::new(self) + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn cmp0(&mut self) -> CMP0_W<8> { + CMP0_W::new(self) + } + #[doc = "Bit 14 - Tamper Enable"] + #[inline(always)] + #[must_use] + pub fn tamper(&mut self) -> TAMPER_W<14> { + TAMPER_W::new(self) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn ovf(&mut self) -> OVF_W<15> { + OVF_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/rtc/mode0/intenset.rs b/pac/atsaml22j/src/rtc/mode0/intenset.rs new file mode 100644 index 000000000000..ffa81d796984 --- /dev/null +++ b/pac/atsaml22j/src/rtc/mode0/intenset.rs @@ -0,0 +1,230 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0 Interrupt Enable"] +pub type PER0_R = crate::BitReader; +#[doc = "Field `PER0` writer - Periodic Interval 0 Interrupt Enable"] +pub type PER0_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENSET_SPEC, bool, O>; +#[doc = "Field `PER1` reader - Periodic Interval 1 Interrupt Enable"] +pub type PER1_R = crate::BitReader; +#[doc = "Field `PER1` writer - Periodic Interval 1 Interrupt Enable"] +pub type PER1_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENSET_SPEC, bool, O>; +#[doc = "Field `PER2` reader - Periodic Interval 2 Interrupt Enable"] +pub type PER2_R = crate::BitReader; +#[doc = "Field `PER2` writer - Periodic Interval 2 Interrupt Enable"] +pub type PER2_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENSET_SPEC, bool, O>; +#[doc = "Field `PER3` reader - Periodic Interval 3 Interrupt Enable"] +pub type PER3_R = crate::BitReader; +#[doc = "Field `PER3` writer - Periodic Interval 3 Interrupt Enable"] +pub type PER3_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENSET_SPEC, bool, O>; +#[doc = "Field `PER4` reader - Periodic Interval 4 Interrupt Enable"] +pub type PER4_R = crate::BitReader; +#[doc = "Field `PER4` writer - Periodic Interval 4 Interrupt Enable"] +pub type PER4_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENSET_SPEC, bool, O>; +#[doc = "Field `PER5` reader - Periodic Interval 5 Interrupt Enable"] +pub type PER5_R = crate::BitReader; +#[doc = "Field `PER5` writer - Periodic Interval 5 Interrupt Enable"] +pub type PER5_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENSET_SPEC, bool, O>; +#[doc = "Field `PER6` reader - Periodic Interval 6 Interrupt Enable"] +pub type PER6_R = crate::BitReader; +#[doc = "Field `PER6` writer - Periodic Interval 6 Interrupt Enable"] +pub type PER6_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENSET_SPEC, bool, O>; +#[doc = "Field `PER7` reader - Periodic Interval 7 Interrupt Enable"] +pub type PER7_R = crate::BitReader; +#[doc = "Field `PER7` writer - Periodic Interval 7 Interrupt Enable"] +pub type PER7_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENSET_SPEC, bool, O>; +#[doc = "Field `CMP0` reader - Compare 0 Interrupt Enable"] +pub type CMP0_R = crate::BitReader; +#[doc = "Field `CMP0` writer - Compare 0 Interrupt Enable"] +pub type CMP0_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENSET_SPEC, bool, O>; +#[doc = "Field `TAMPER` reader - Tamper Enable"] +pub type TAMPER_R = crate::BitReader; +#[doc = "Field `TAMPER` writer - Tamper Enable"] +pub type TAMPER_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENSET_SPEC, bool, O>; +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub type OVF_R = crate::BitReader; +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub type OVF_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENSET_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 14 - Tamper Enable"] + #[inline(always)] + pub fn tamper(&self) -> TAMPER_R { + TAMPER_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn per0(&mut self) -> PER0_W<0> { + PER0_W::new(self) + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn per1(&mut self) -> PER1_W<1> { + PER1_W::new(self) + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn per2(&mut self) -> PER2_W<2> { + PER2_W::new(self) + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn per3(&mut self) -> PER3_W<3> { + PER3_W::new(self) + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn per4(&mut self) -> PER4_W<4> { + PER4_W::new(self) + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn per5(&mut self) -> PER5_W<5> { + PER5_W::new(self) + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn per6(&mut self) -> PER6_W<6> { + PER6_W::new(self) + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn per7(&mut self) -> PER7_W<7> { + PER7_W::new(self) + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn cmp0(&mut self) -> CMP0_W<8> { + CMP0_W::new(self) + } + #[doc = "Bit 14 - Tamper Enable"] + #[inline(always)] + #[must_use] + pub fn tamper(&mut self) -> TAMPER_W<14> { + TAMPER_W::new(self) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn ovf(&mut self) -> OVF_W<15> { + OVF_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/rtc/mode0/intflag.rs b/pac/atsaml22j/src/rtc/mode0/intflag.rs new file mode 100644 index 000000000000..7b21b4aff95e --- /dev/null +++ b/pac/atsaml22j/src/rtc/mode0/intflag.rs @@ -0,0 +1,230 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0"] +pub type PER0_R = crate::BitReader; +#[doc = "Field `PER0` writer - Periodic Interval 0"] +pub type PER0_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTFLAG_SPEC, bool, O>; +#[doc = "Field `PER1` reader - Periodic Interval 1"] +pub type PER1_R = crate::BitReader; +#[doc = "Field `PER1` writer - Periodic Interval 1"] +pub type PER1_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTFLAG_SPEC, bool, O>; +#[doc = "Field `PER2` reader - Periodic Interval 2"] +pub type PER2_R = crate::BitReader; +#[doc = "Field `PER2` writer - Periodic Interval 2"] +pub type PER2_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTFLAG_SPEC, bool, O>; +#[doc = "Field `PER3` reader - Periodic Interval 3"] +pub type PER3_R = crate::BitReader; +#[doc = "Field `PER3` writer - Periodic Interval 3"] +pub type PER3_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTFLAG_SPEC, bool, O>; +#[doc = "Field `PER4` reader - Periodic Interval 4"] +pub type PER4_R = crate::BitReader; +#[doc = "Field `PER4` writer - Periodic Interval 4"] +pub type PER4_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTFLAG_SPEC, bool, O>; +#[doc = "Field `PER5` reader - Periodic Interval 5"] +pub type PER5_R = crate::BitReader; +#[doc = "Field `PER5` writer - Periodic Interval 5"] +pub type PER5_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTFLAG_SPEC, bool, O>; +#[doc = "Field `PER6` reader - Periodic Interval 6"] +pub type PER6_R = crate::BitReader; +#[doc = "Field `PER6` writer - Periodic Interval 6"] +pub type PER6_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTFLAG_SPEC, bool, O>; +#[doc = "Field `PER7` reader - Periodic Interval 7"] +pub type PER7_R = crate::BitReader; +#[doc = "Field `PER7` writer - Periodic Interval 7"] +pub type PER7_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTFLAG_SPEC, bool, O>; +#[doc = "Field `CMP0` reader - Compare 0"] +pub type CMP0_R = crate::BitReader; +#[doc = "Field `CMP0` writer - Compare 0"] +pub type CMP0_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTFLAG_SPEC, bool, O>; +#[doc = "Field `TAMPER` reader - Tamper"] +pub type TAMPER_R = crate::BitReader; +#[doc = "Field `TAMPER` writer - Tamper"] +pub type TAMPER_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTFLAG_SPEC, bool, O>; +#[doc = "Field `OVF` reader - Overflow"] +pub type OVF_R = crate::BitReader; +#[doc = "Field `OVF` writer - Overflow"] +pub type OVF_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTFLAG_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Periodic Interval 0"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Compare 0"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 14 - Tamper"] + #[inline(always)] + pub fn tamper(&self) -> TAMPER_R { + TAMPER_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0"] + #[inline(always)] + #[must_use] + pub fn per0(&mut self) -> PER0_W<0> { + PER0_W::new(self) + } + #[doc = "Bit 1 - Periodic Interval 1"] + #[inline(always)] + #[must_use] + pub fn per1(&mut self) -> PER1_W<1> { + PER1_W::new(self) + } + #[doc = "Bit 2 - Periodic Interval 2"] + #[inline(always)] + #[must_use] + pub fn per2(&mut self) -> PER2_W<2> { + PER2_W::new(self) + } + #[doc = "Bit 3 - Periodic Interval 3"] + #[inline(always)] + #[must_use] + pub fn per3(&mut self) -> PER3_W<3> { + PER3_W::new(self) + } + #[doc = "Bit 4 - Periodic Interval 4"] + #[inline(always)] + #[must_use] + pub fn per4(&mut self) -> PER4_W<4> { + PER4_W::new(self) + } + #[doc = "Bit 5 - Periodic Interval 5"] + #[inline(always)] + #[must_use] + pub fn per5(&mut self) -> PER5_W<5> { + PER5_W::new(self) + } + #[doc = "Bit 6 - Periodic Interval 6"] + #[inline(always)] + #[must_use] + pub fn per6(&mut self) -> PER6_W<6> { + PER6_W::new(self) + } + #[doc = "Bit 7 - Periodic Interval 7"] + #[inline(always)] + #[must_use] + pub fn per7(&mut self) -> PER7_W<7> { + PER7_W::new(self) + } + #[doc = "Bit 8 - Compare 0"] + #[inline(always)] + #[must_use] + pub fn cmp0(&mut self) -> CMP0_W<8> { + CMP0_W::new(self) + } + #[doc = "Bit 14 - Tamper"] + #[inline(always)] + #[must_use] + pub fn tamper(&mut self) -> TAMPER_W<14> { + TAMPER_W::new(self) + } + #[doc = "Bit 15 - Overflow"] + #[inline(always)] + #[must_use] + pub fn ovf(&mut self) -> OVF_W<15> { + OVF_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE0 Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/rtc/mode0/syncbusy.rs b/pac/atsaml22j/src/rtc/mode0/syncbusy.rs new file mode 100644 index 000000000000..ba1cdeb398a7 --- /dev/null +++ b/pac/atsaml22j/src/rtc/mode0/syncbusy.rs @@ -0,0 +1,86 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Busy"] +pub type SWRST_R = crate::BitReader; +#[doc = "Field `ENABLE` reader - Enable Bit Busy"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `FREQCORR` reader - FREQCORR Register Busy"] +pub type FREQCORR_R = crate::BitReader; +#[doc = "Field `COUNT` reader - COUNT Register Busy"] +pub type COUNT_R = crate::BitReader; +#[doc = "Field `COMP0` reader - COMP 0 Register Busy"] +pub type COMP0_R = crate::BitReader; +#[doc = "Field `COUNTSYNC` reader - Count Synchronization Enable Bit Busy"] +pub type COUNTSYNC_R = crate::BitReader; +#[doc = "Field `GP0` reader - General Purpose 0 Register Busy"] +pub type GP0_R = crate::BitReader; +#[doc = "Field `GP1` reader - General Purpose 1 Register Busy"] +pub type GP1_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Software Reset Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable Bit Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - FREQCORR Register Busy"] + #[inline(always)] + pub fn freqcorr(&self) -> FREQCORR_R { + FREQCORR_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - COUNT Register Busy"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - COMP 0 Register Busy"] + #[inline(always)] + pub fn comp0(&self) -> COMP0_R { + COMP0_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 15 - Count Synchronization Enable Bit Busy"] + #[inline(always)] + pub fn countsync(&self) -> COUNTSYNC_R { + COUNTSYNC_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - General Purpose 0 Register Busy"] + #[inline(always)] + pub fn gp0(&self) -> GP0_R { + GP0_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - General Purpose 1 Register Busy"] + #[inline(always)] + pub fn gp1(&self) -> GP1_R { + GP1_R::new(((self.bits >> 17) & 1) != 0) + } +} +#[doc = "MODE0 Synchronization Busy Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/rtc/mode0/tampctrl.rs b/pac/atsaml22j/src/rtc/mode0/tampctrl.rs new file mode 100644 index 000000000000..8765e653ee07 --- /dev/null +++ b/pac/atsaml22j/src/rtc/mode0/tampctrl.rs @@ -0,0 +1,665 @@ +#[doc = "Register `TAMPCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TAMPCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `IN0ACT` reader - Tamper Input 0 Action"] +pub type IN0ACT_R = crate::FieldReader; +#[doc = "Tamper Input 0 Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum IN0ACTSELECT_A { + #[doc = "0: Off (Disabled)"] + OFF = 0, + #[doc = "1: Wake without timestamp"] + WAKE = 1, + #[doc = "2: Capture timestamp"] + CAPTURE = 2, + #[doc = "3: Compare IN0 to OUT"] + ACTL = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: IN0ACTSELECT_A) -> Self { + variant as _ + } +} +impl IN0ACT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> IN0ACTSELECT_A { + match self.bits { + 0 => IN0ACTSELECT_A::OFF, + 1 => IN0ACTSELECT_A::WAKE, + 2 => IN0ACTSELECT_A::CAPTURE, + 3 => IN0ACTSELECT_A::ACTL, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == IN0ACTSELECT_A::OFF + } + #[doc = "Checks if the value of the field is `WAKE`"] + #[inline(always)] + pub fn is_wake(&self) -> bool { + *self == IN0ACTSELECT_A::WAKE + } + #[doc = "Checks if the value of the field is `CAPTURE`"] + #[inline(always)] + pub fn is_capture(&self) -> bool { + *self == IN0ACTSELECT_A::CAPTURE + } + #[doc = "Checks if the value of the field is `ACTL`"] + #[inline(always)] + pub fn is_actl(&self) -> bool { + *self == IN0ACTSELECT_A::ACTL + } +} +#[doc = "Field `IN0ACT` writer - Tamper Input 0 Action"] +pub type IN0ACT_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, TAMPCTRL_SPEC, u8, IN0ACTSELECT_A, 2, O>; +impl<'a, const O: u8> IN0ACT_W<'a, O> { + #[doc = "Off (Disabled)"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(IN0ACTSELECT_A::OFF) + } + #[doc = "Wake without timestamp"] + #[inline(always)] + pub fn wake(self) -> &'a mut W { + self.variant(IN0ACTSELECT_A::WAKE) + } + #[doc = "Capture timestamp"] + #[inline(always)] + pub fn capture(self) -> &'a mut W { + self.variant(IN0ACTSELECT_A::CAPTURE) + } + #[doc = "Compare IN0 to OUT"] + #[inline(always)] + pub fn actl(self) -> &'a mut W { + self.variant(IN0ACTSELECT_A::ACTL) + } +} +#[doc = "Field `IN1ACT` reader - Tamper Input 1 Action"] +pub type IN1ACT_R = crate::FieldReader; +#[doc = "Tamper Input 1 Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum IN1ACTSELECT_A { + #[doc = "0: Off (Disabled)"] + OFF = 0, + #[doc = "1: Wake without timestamp"] + WAKE = 1, + #[doc = "2: Capture timestamp"] + CAPTURE = 2, + #[doc = "3: Compare IN1 to OUT"] + ACTL = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: IN1ACTSELECT_A) -> Self { + variant as _ + } +} +impl IN1ACT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> IN1ACTSELECT_A { + match self.bits { + 0 => IN1ACTSELECT_A::OFF, + 1 => IN1ACTSELECT_A::WAKE, + 2 => IN1ACTSELECT_A::CAPTURE, + 3 => IN1ACTSELECT_A::ACTL, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == IN1ACTSELECT_A::OFF + } + #[doc = "Checks if the value of the field is `WAKE`"] + #[inline(always)] + pub fn is_wake(&self) -> bool { + *self == IN1ACTSELECT_A::WAKE + } + #[doc = "Checks if the value of the field is `CAPTURE`"] + #[inline(always)] + pub fn is_capture(&self) -> bool { + *self == IN1ACTSELECT_A::CAPTURE + } + #[doc = "Checks if the value of the field is `ACTL`"] + #[inline(always)] + pub fn is_actl(&self) -> bool { + *self == IN1ACTSELECT_A::ACTL + } +} +#[doc = "Field `IN1ACT` writer - Tamper Input 1 Action"] +pub type IN1ACT_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, TAMPCTRL_SPEC, u8, IN1ACTSELECT_A, 2, O>; +impl<'a, const O: u8> IN1ACT_W<'a, O> { + #[doc = "Off (Disabled)"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(IN1ACTSELECT_A::OFF) + } + #[doc = "Wake without timestamp"] + #[inline(always)] + pub fn wake(self) -> &'a mut W { + self.variant(IN1ACTSELECT_A::WAKE) + } + #[doc = "Capture timestamp"] + #[inline(always)] + pub fn capture(self) -> &'a mut W { + self.variant(IN1ACTSELECT_A::CAPTURE) + } + #[doc = "Compare IN1 to OUT"] + #[inline(always)] + pub fn actl(self) -> &'a mut W { + self.variant(IN1ACTSELECT_A::ACTL) + } +} +#[doc = "Field `IN2ACT` reader - Tamper Input 2 Action"] +pub type IN2ACT_R = crate::FieldReader; +#[doc = "Tamper Input 2 Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum IN2ACTSELECT_A { + #[doc = "0: Off (Disabled)"] + OFF = 0, + #[doc = "1: Wake without timestamp"] + WAKE = 1, + #[doc = "2: Capture timestamp"] + CAPTURE = 2, + #[doc = "3: Compare IN2 to OUT"] + ACTL = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: IN2ACTSELECT_A) -> Self { + variant as _ + } +} +impl IN2ACT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> IN2ACTSELECT_A { + match self.bits { + 0 => IN2ACTSELECT_A::OFF, + 1 => IN2ACTSELECT_A::WAKE, + 2 => IN2ACTSELECT_A::CAPTURE, + 3 => IN2ACTSELECT_A::ACTL, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == IN2ACTSELECT_A::OFF + } + #[doc = "Checks if the value of the field is `WAKE`"] + #[inline(always)] + pub fn is_wake(&self) -> bool { + *self == IN2ACTSELECT_A::WAKE + } + #[doc = "Checks if the value of the field is `CAPTURE`"] + #[inline(always)] + pub fn is_capture(&self) -> bool { + *self == IN2ACTSELECT_A::CAPTURE + } + #[doc = "Checks if the value of the field is `ACTL`"] + #[inline(always)] + pub fn is_actl(&self) -> bool { + *self == IN2ACTSELECT_A::ACTL + } +} +#[doc = "Field `IN2ACT` writer - Tamper Input 2 Action"] +pub type IN2ACT_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, TAMPCTRL_SPEC, u8, IN2ACTSELECT_A, 2, O>; +impl<'a, const O: u8> IN2ACT_W<'a, O> { + #[doc = "Off (Disabled)"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(IN2ACTSELECT_A::OFF) + } + #[doc = "Wake without timestamp"] + #[inline(always)] + pub fn wake(self) -> &'a mut W { + self.variant(IN2ACTSELECT_A::WAKE) + } + #[doc = "Capture timestamp"] + #[inline(always)] + pub fn capture(self) -> &'a mut W { + self.variant(IN2ACTSELECT_A::CAPTURE) + } + #[doc = "Compare IN2 to OUT"] + #[inline(always)] + pub fn actl(self) -> &'a mut W { + self.variant(IN2ACTSELECT_A::ACTL) + } +} +#[doc = "Field `IN3ACT` reader - Tamper Input 3 Action"] +pub type IN3ACT_R = crate::FieldReader; +#[doc = "Tamper Input 3 Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum IN3ACTSELECT_A { + #[doc = "0: Off (Disabled)"] + OFF = 0, + #[doc = "1: Wake without timestamp"] + WAKE = 1, + #[doc = "2: Capture timestamp"] + CAPTURE = 2, + #[doc = "3: Compare IN3 to OUT"] + ACTL = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: IN3ACTSELECT_A) -> Self { + variant as _ + } +} +impl IN3ACT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> IN3ACTSELECT_A { + match self.bits { + 0 => IN3ACTSELECT_A::OFF, + 1 => IN3ACTSELECT_A::WAKE, + 2 => IN3ACTSELECT_A::CAPTURE, + 3 => IN3ACTSELECT_A::ACTL, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == IN3ACTSELECT_A::OFF + } + #[doc = "Checks if the value of the field is `WAKE`"] + #[inline(always)] + pub fn is_wake(&self) -> bool { + *self == IN3ACTSELECT_A::WAKE + } + #[doc = "Checks if the value of the field is `CAPTURE`"] + #[inline(always)] + pub fn is_capture(&self) -> bool { + *self == IN3ACTSELECT_A::CAPTURE + } + #[doc = "Checks if the value of the field is `ACTL`"] + #[inline(always)] + pub fn is_actl(&self) -> bool { + *self == IN3ACTSELECT_A::ACTL + } +} +#[doc = "Field `IN3ACT` writer - Tamper Input 3 Action"] +pub type IN3ACT_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, TAMPCTRL_SPEC, u8, IN3ACTSELECT_A, 2, O>; +impl<'a, const O: u8> IN3ACT_W<'a, O> { + #[doc = "Off (Disabled)"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(IN3ACTSELECT_A::OFF) + } + #[doc = "Wake without timestamp"] + #[inline(always)] + pub fn wake(self) -> &'a mut W { + self.variant(IN3ACTSELECT_A::WAKE) + } + #[doc = "Capture timestamp"] + #[inline(always)] + pub fn capture(self) -> &'a mut W { + self.variant(IN3ACTSELECT_A::CAPTURE) + } + #[doc = "Compare IN3 to OUT"] + #[inline(always)] + pub fn actl(self) -> &'a mut W { + self.variant(IN3ACTSELECT_A::ACTL) + } +} +#[doc = "Field `IN4ACT` reader - Tamper Input 4 Action"] +pub type IN4ACT_R = crate::FieldReader; +#[doc = "Tamper Input 4 Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum IN4ACTSELECT_A { + #[doc = "0: Off (Disabled)"] + OFF = 0, + #[doc = "1: Wake without timestamp"] + WAKE = 1, + #[doc = "2: Capture timestamp"] + CAPTURE = 2, + #[doc = "3: Compare IN4 to OUT"] + ACTL = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: IN4ACTSELECT_A) -> Self { + variant as _ + } +} +impl IN4ACT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> IN4ACTSELECT_A { + match self.bits { + 0 => IN4ACTSELECT_A::OFF, + 1 => IN4ACTSELECT_A::WAKE, + 2 => IN4ACTSELECT_A::CAPTURE, + 3 => IN4ACTSELECT_A::ACTL, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == IN4ACTSELECT_A::OFF + } + #[doc = "Checks if the value of the field is `WAKE`"] + #[inline(always)] + pub fn is_wake(&self) -> bool { + *self == IN4ACTSELECT_A::WAKE + } + #[doc = "Checks if the value of the field is `CAPTURE`"] + #[inline(always)] + pub fn is_capture(&self) -> bool { + *self == IN4ACTSELECT_A::CAPTURE + } + #[doc = "Checks if the value of the field is `ACTL`"] + #[inline(always)] + pub fn is_actl(&self) -> bool { + *self == IN4ACTSELECT_A::ACTL + } +} +#[doc = "Field `IN4ACT` writer - Tamper Input 4 Action"] +pub type IN4ACT_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, TAMPCTRL_SPEC, u8, IN4ACTSELECT_A, 2, O>; +impl<'a, const O: u8> IN4ACT_W<'a, O> { + #[doc = "Off (Disabled)"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(IN4ACTSELECT_A::OFF) + } + #[doc = "Wake without timestamp"] + #[inline(always)] + pub fn wake(self) -> &'a mut W { + self.variant(IN4ACTSELECT_A::WAKE) + } + #[doc = "Capture timestamp"] + #[inline(always)] + pub fn capture(self) -> &'a mut W { + self.variant(IN4ACTSELECT_A::CAPTURE) + } + #[doc = "Compare IN4 to OUT"] + #[inline(always)] + pub fn actl(self) -> &'a mut W { + self.variant(IN4ACTSELECT_A::ACTL) + } +} +#[doc = "Field `TAMLVL0` reader - Tamper Level Select 0"] +pub type TAMLVL0_R = crate::BitReader; +#[doc = "Field `TAMLVL0` writer - Tamper Level Select 0"] +pub type TAMLVL0_W<'a, const O: u8> = crate::BitWriter<'a, u32, TAMPCTRL_SPEC, bool, O>; +#[doc = "Field `TAMLVL1` reader - Tamper Level Select 1"] +pub type TAMLVL1_R = crate::BitReader; +#[doc = "Field `TAMLVL1` writer - Tamper Level Select 1"] +pub type TAMLVL1_W<'a, const O: u8> = crate::BitWriter<'a, u32, TAMPCTRL_SPEC, bool, O>; +#[doc = "Field `TAMLVL2` reader - Tamper Level Select 2"] +pub type TAMLVL2_R = crate::BitReader; +#[doc = "Field `TAMLVL2` writer - Tamper Level Select 2"] +pub type TAMLVL2_W<'a, const O: u8> = crate::BitWriter<'a, u32, TAMPCTRL_SPEC, bool, O>; +#[doc = "Field `TAMLVL3` reader - Tamper Level Select 3"] +pub type TAMLVL3_R = crate::BitReader; +#[doc = "Field `TAMLVL3` writer - Tamper Level Select 3"] +pub type TAMLVL3_W<'a, const O: u8> = crate::BitWriter<'a, u32, TAMPCTRL_SPEC, bool, O>; +#[doc = "Field `TAMLVL4` reader - Tamper Level Select 4"] +pub type TAMLVL4_R = crate::BitReader; +#[doc = "Field `TAMLVL4` writer - Tamper Level Select 4"] +pub type TAMLVL4_W<'a, const O: u8> = crate::BitWriter<'a, u32, TAMPCTRL_SPEC, bool, O>; +#[doc = "Field `DEBNC0` reader - Debouncer Enable 0"] +pub type DEBNC0_R = crate::BitReader; +#[doc = "Field `DEBNC0` writer - Debouncer Enable 0"] +pub type DEBNC0_W<'a, const O: u8> = crate::BitWriter<'a, u32, TAMPCTRL_SPEC, bool, O>; +#[doc = "Field `DEBNC1` reader - Debouncer Enable 1"] +pub type DEBNC1_R = crate::BitReader; +#[doc = "Field `DEBNC1` writer - Debouncer Enable 1"] +pub type DEBNC1_W<'a, const O: u8> = crate::BitWriter<'a, u32, TAMPCTRL_SPEC, bool, O>; +#[doc = "Field `DEBNC2` reader - Debouncer Enable 2"] +pub type DEBNC2_R = crate::BitReader; +#[doc = "Field `DEBNC2` writer - Debouncer Enable 2"] +pub type DEBNC2_W<'a, const O: u8> = crate::BitWriter<'a, u32, TAMPCTRL_SPEC, bool, O>; +#[doc = "Field `DEBNC3` reader - Debouncer Enable 3"] +pub type DEBNC3_R = crate::BitReader; +#[doc = "Field `DEBNC3` writer - Debouncer Enable 3"] +pub type DEBNC3_W<'a, const O: u8> = crate::BitWriter<'a, u32, TAMPCTRL_SPEC, bool, O>; +#[doc = "Field `DEBNC4` reader - Debouncer Enable 4"] +pub type DEBNC4_R = crate::BitReader; +#[doc = "Field `DEBNC4` writer - Debouncer Enable 4"] +pub type DEBNC4_W<'a, const O: u8> = crate::BitWriter<'a, u32, TAMPCTRL_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:1 - Tamper Input 0 Action"] + #[inline(always)] + pub fn in0act(&self) -> IN0ACT_R { + IN0ACT_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Tamper Input 1 Action"] + #[inline(always)] + pub fn in1act(&self) -> IN1ACT_R { + IN1ACT_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Tamper Input 2 Action"] + #[inline(always)] + pub fn in2act(&self) -> IN2ACT_R { + IN2ACT_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - Tamper Input 3 Action"] + #[inline(always)] + pub fn in3act(&self) -> IN3ACT_R { + IN3ACT_R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - Tamper Input 4 Action"] + #[inline(always)] + pub fn in4act(&self) -> IN4ACT_R { + IN4ACT_R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bit 16 - Tamper Level Select 0"] + #[inline(always)] + pub fn tamlvl0(&self) -> TAMLVL0_R { + TAMLVL0_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Tamper Level Select 1"] + #[inline(always)] + pub fn tamlvl1(&self) -> TAMLVL1_R { + TAMLVL1_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Tamper Level Select 2"] + #[inline(always)] + pub fn tamlvl2(&self) -> TAMLVL2_R { + TAMLVL2_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Tamper Level Select 3"] + #[inline(always)] + pub fn tamlvl3(&self) -> TAMLVL3_R { + TAMLVL3_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Tamper Level Select 4"] + #[inline(always)] + pub fn tamlvl4(&self) -> TAMLVL4_R { + TAMLVL4_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 24 - Debouncer Enable 0"] + #[inline(always)] + pub fn debnc0(&self) -> DEBNC0_R { + DEBNC0_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Debouncer Enable 1"] + #[inline(always)] + pub fn debnc1(&self) -> DEBNC1_R { + DEBNC1_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Debouncer Enable 2"] + #[inline(always)] + pub fn debnc2(&self) -> DEBNC2_R { + DEBNC2_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Debouncer Enable 3"] + #[inline(always)] + pub fn debnc3(&self) -> DEBNC3_R { + DEBNC3_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Debouncer Enable 4"] + #[inline(always)] + pub fn debnc4(&self) -> DEBNC4_R { + DEBNC4_R::new(((self.bits >> 28) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:1 - Tamper Input 0 Action"] + #[inline(always)] + #[must_use] + pub fn in0act(&mut self) -> IN0ACT_W<0> { + IN0ACT_W::new(self) + } + #[doc = "Bits 2:3 - Tamper Input 1 Action"] + #[inline(always)] + #[must_use] + pub fn in1act(&mut self) -> IN1ACT_W<2> { + IN1ACT_W::new(self) + } + #[doc = "Bits 4:5 - Tamper Input 2 Action"] + #[inline(always)] + #[must_use] + pub fn in2act(&mut self) -> IN2ACT_W<4> { + IN2ACT_W::new(self) + } + #[doc = "Bits 6:7 - Tamper Input 3 Action"] + #[inline(always)] + #[must_use] + pub fn in3act(&mut self) -> IN3ACT_W<6> { + IN3ACT_W::new(self) + } + #[doc = "Bits 8:9 - Tamper Input 4 Action"] + #[inline(always)] + #[must_use] + pub fn in4act(&mut self) -> IN4ACT_W<8> { + IN4ACT_W::new(self) + } + #[doc = "Bit 16 - Tamper Level Select 0"] + #[inline(always)] + #[must_use] + pub fn tamlvl0(&mut self) -> TAMLVL0_W<16> { + TAMLVL0_W::new(self) + } + #[doc = "Bit 17 - Tamper Level Select 1"] + #[inline(always)] + #[must_use] + pub fn tamlvl1(&mut self) -> TAMLVL1_W<17> { + TAMLVL1_W::new(self) + } + #[doc = "Bit 18 - Tamper Level Select 2"] + #[inline(always)] + #[must_use] + pub fn tamlvl2(&mut self) -> TAMLVL2_W<18> { + TAMLVL2_W::new(self) + } + #[doc = "Bit 19 - Tamper Level Select 3"] + #[inline(always)] + #[must_use] + pub fn tamlvl3(&mut self) -> TAMLVL3_W<19> { + TAMLVL3_W::new(self) + } + #[doc = "Bit 20 - Tamper Level Select 4"] + #[inline(always)] + #[must_use] + pub fn tamlvl4(&mut self) -> TAMLVL4_W<20> { + TAMLVL4_W::new(self) + } + #[doc = "Bit 24 - Debouncer Enable 0"] + #[inline(always)] + #[must_use] + pub fn debnc0(&mut self) -> DEBNC0_W<24> { + DEBNC0_W::new(self) + } + #[doc = "Bit 25 - Debouncer Enable 1"] + #[inline(always)] + #[must_use] + pub fn debnc1(&mut self) -> DEBNC1_W<25> { + DEBNC1_W::new(self) + } + #[doc = "Bit 26 - Debouncer Enable 2"] + #[inline(always)] + #[must_use] + pub fn debnc2(&mut self) -> DEBNC2_W<26> { + DEBNC2_W::new(self) + } + #[doc = "Bit 27 - Debouncer Enable 3"] + #[inline(always)] + #[must_use] + pub fn debnc3(&mut self) -> DEBNC3_W<27> { + DEBNC3_W::new(self) + } + #[doc = "Bit 28 - Debouncer Enable 4"] + #[inline(always)] + #[must_use] + pub fn debnc4(&mut self) -> DEBNC4_W<28> { + DEBNC4_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Tamper Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tampctrl](index.html) module"] +pub struct TAMPCTRL_SPEC; +impl crate::RegisterSpec for TAMPCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tampctrl::R](R) reader structure"] +impl crate::Readable for TAMPCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [tampctrl::W](W) writer structure"] +impl crate::Writable for TAMPCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TAMPCTRL to value 0"] +impl crate::Resettable for TAMPCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/rtc/mode0/tampid.rs b/pac/atsaml22j/src/rtc/mode0/tampid.rs new file mode 100644 index 000000000000..3677f47b1990 --- /dev/null +++ b/pac/atsaml22j/src/rtc/mode0/tampid.rs @@ -0,0 +1,155 @@ +#[doc = "Register `TAMPID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TAMPID` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TAMPID0` reader - Tamper Input 0 Detected"] +pub type TAMPID0_R = crate::BitReader; +#[doc = "Field `TAMPID0` writer - Tamper Input 0 Detected"] +pub type TAMPID0_W<'a, const O: u8> = crate::BitWriter<'a, u32, TAMPID_SPEC, bool, O>; +#[doc = "Field `TAMPID1` reader - Tamper Input 1 Detected"] +pub type TAMPID1_R = crate::BitReader; +#[doc = "Field `TAMPID1` writer - Tamper Input 1 Detected"] +pub type TAMPID1_W<'a, const O: u8> = crate::BitWriter<'a, u32, TAMPID_SPEC, bool, O>; +#[doc = "Field `TAMPID2` reader - Tamper Input 2 Detected"] +pub type TAMPID2_R = crate::BitReader; +#[doc = "Field `TAMPID2` writer - Tamper Input 2 Detected"] +pub type TAMPID2_W<'a, const O: u8> = crate::BitWriter<'a, u32, TAMPID_SPEC, bool, O>; +#[doc = "Field `TAMPID3` reader - Tamper Input 3 Detected"] +pub type TAMPID3_R = crate::BitReader; +#[doc = "Field `TAMPID3` writer - Tamper Input 3 Detected"] +pub type TAMPID3_W<'a, const O: u8> = crate::BitWriter<'a, u32, TAMPID_SPEC, bool, O>; +#[doc = "Field `TAMPID4` reader - Tamper Input 4 Detected"] +pub type TAMPID4_R = crate::BitReader; +#[doc = "Field `TAMPID4` writer - Tamper Input 4 Detected"] +pub type TAMPID4_W<'a, const O: u8> = crate::BitWriter<'a, u32, TAMPID_SPEC, bool, O>; +#[doc = "Field `TAMPEVT` reader - Tamper Event Detected"] +pub type TAMPEVT_R = crate::BitReader; +#[doc = "Field `TAMPEVT` writer - Tamper Event Detected"] +pub type TAMPEVT_W<'a, const O: u8> = crate::BitWriter<'a, u32, TAMPID_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Tamper Input 0 Detected"] + #[inline(always)] + pub fn tampid0(&self) -> TAMPID0_R { + TAMPID0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Tamper Input 1 Detected"] + #[inline(always)] + pub fn tampid1(&self) -> TAMPID1_R { + TAMPID1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Tamper Input 2 Detected"] + #[inline(always)] + pub fn tampid2(&self) -> TAMPID2_R { + TAMPID2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Tamper Input 3 Detected"] + #[inline(always)] + pub fn tampid3(&self) -> TAMPID3_R { + TAMPID3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Tamper Input 4 Detected"] + #[inline(always)] + pub fn tampid4(&self) -> TAMPID4_R { + TAMPID4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 31 - Tamper Event Detected"] + #[inline(always)] + pub fn tampevt(&self) -> TAMPEVT_R { + TAMPEVT_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Tamper Input 0 Detected"] + #[inline(always)] + #[must_use] + pub fn tampid0(&mut self) -> TAMPID0_W<0> { + TAMPID0_W::new(self) + } + #[doc = "Bit 1 - Tamper Input 1 Detected"] + #[inline(always)] + #[must_use] + pub fn tampid1(&mut self) -> TAMPID1_W<1> { + TAMPID1_W::new(self) + } + #[doc = "Bit 2 - Tamper Input 2 Detected"] + #[inline(always)] + #[must_use] + pub fn tampid2(&mut self) -> TAMPID2_W<2> { + TAMPID2_W::new(self) + } + #[doc = "Bit 3 - Tamper Input 3 Detected"] + #[inline(always)] + #[must_use] + pub fn tampid3(&mut self) -> TAMPID3_W<3> { + TAMPID3_W::new(self) + } + #[doc = "Bit 4 - Tamper Input 4 Detected"] + #[inline(always)] + #[must_use] + pub fn tampid4(&mut self) -> TAMPID4_W<4> { + TAMPID4_W::new(self) + } + #[doc = "Bit 31 - Tamper Event Detected"] + #[inline(always)] + #[must_use] + pub fn tampevt(&mut self) -> TAMPEVT_W<31> { + TAMPEVT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Tamper ID\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tampid](index.html) module"] +pub struct TAMPID_SPEC; +impl crate::RegisterSpec for TAMPID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tampid::R](R) reader structure"] +impl crate::Readable for TAMPID_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [tampid::W](W) writer structure"] +impl crate::Writable for TAMPID_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TAMPID to value 0"] +impl crate::Resettable for TAMPID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/rtc/mode0/timestamp.rs b/pac/atsaml22j/src/rtc/mode0/timestamp.rs new file mode 100644 index 000000000000..6008ad6d792b --- /dev/null +++ b/pac/atsaml22j/src/rtc/mode0/timestamp.rs @@ -0,0 +1,37 @@ +#[doc = "Register `TIMESTAMP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COUNT` reader - Count Timestamp Value"] +pub type COUNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Count Timestamp Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits) + } +} +#[doc = "MODE0 Timestamp\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [timestamp](index.html) module"] +pub struct TIMESTAMP_SPEC; +impl crate::RegisterSpec for TIMESTAMP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [timestamp::R](R) reader structure"] +impl crate::Readable for TIMESTAMP_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets TIMESTAMP to value 0"] +impl crate::Resettable for TIMESTAMP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/rtc/mode1.rs b/pac/atsaml22j/src/rtc/mode1.rs new file mode 100644 index 000000000000..9b0d9984276e --- /dev/null +++ b/pac/atsaml22j/src/rtc/mode1.rs @@ -0,0 +1,113 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct MODE1 { + #[doc = "0x00 - MODE1 Control A"] + pub ctrla: CTRLA, + #[doc = "0x02 - MODE1 Control B"] + pub ctrlb: CTRLB, + #[doc = "0x04 - MODE1 Event Control"] + pub evctrl: EVCTRL, + #[doc = "0x08 - MODE1 Interrupt Enable Clear"] + pub intenclr: INTENCLR, + #[doc = "0x0a - MODE1 Interrupt Enable Set"] + pub intenset: INTENSET, + #[doc = "0x0c - MODE1 Interrupt Flag Status and Clear"] + pub intflag: INTFLAG, + #[doc = "0x0e - Debug Control"] + pub dbgctrl: DBGCTRL, + _reserved7: [u8; 0x01], + #[doc = "0x10 - MODE1 Synchronization Busy Status"] + pub syncbusy: SYNCBUSY, + #[doc = "0x14 - Frequency Correction"] + pub freqcorr: FREQCORR, + _reserved9: [u8; 0x03], + #[doc = "0x18 - MODE1 Counter Value"] + pub count: COUNT, + _reserved10: [u8; 0x02], + #[doc = "0x1c - MODE1 Counter Period"] + pub per: PER, + _reserved11: [u8; 0x02], + #[doc = "0x20 - MODE1 Compare n Value"] + pub comp: [COMP; 2], + _reserved12: [u8; 0x1c], + #[doc = "0x40..0x48 - General Purpose"] + pub gp: [GP; 2], + _reserved13: [u8; 0x18], + #[doc = "0x60 - Tamper Control"] + pub tampctrl: TAMPCTRL, + #[doc = "0x64 - MODE1 Timestamp"] + pub timestamp: TIMESTAMP, + #[doc = "0x68 - Tamper ID"] + pub tampid: TAMPID, + _reserved16: [u8; 0x14], + #[doc = "0x80..0xa0 - Backup"] + pub bkup: [BKUP; 8], +} +#[doc = "CTRLA (rw) register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "MODE1 Control A"] +pub mod ctrla; +#[doc = "CTRLB (rw) register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "MODE1 Control B"] +pub mod ctrlb; +#[doc = "EVCTRL (rw) register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "MODE1 Event Control"] +pub mod evctrl; +#[doc = "INTENCLR (rw) register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "MODE1 Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET (rw) register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "MODE1 Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG (rw) register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "MODE1 Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "DBGCTRL (rw) register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY (r) register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "MODE1 Synchronization Busy Status"] +pub mod syncbusy; +#[doc = "FREQCORR (rw) register accessor: an alias for `Reg`"] +pub type FREQCORR = crate::Reg; +#[doc = "Frequency Correction"] +pub mod freqcorr; +#[doc = "COUNT (rw) register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "MODE1 Counter Value"] +pub mod count; +#[doc = "PER (rw) register accessor: an alias for `Reg`"] +pub type PER = crate::Reg; +#[doc = "MODE1 Counter Period"] +pub mod per; +#[doc = "COMP (rw) register accessor: an alias for `Reg`"] +pub type COMP = crate::Reg; +#[doc = "MODE1 Compare n Value"] +pub mod comp; +#[doc = "GP (rw) register accessor: an alias for `Reg`"] +pub type GP = crate::Reg; +#[doc = "General Purpose"] +pub mod gp; +#[doc = "TAMPCTRL (rw) register accessor: an alias for `Reg`"] +pub type TAMPCTRL = crate::Reg; +#[doc = "Tamper Control"] +pub mod tampctrl; +#[doc = "TIMESTAMP (r) register accessor: an alias for `Reg`"] +pub type TIMESTAMP = crate::Reg; +#[doc = "MODE1 Timestamp"] +pub mod timestamp; +#[doc = "TAMPID (rw) register accessor: an alias for `Reg`"] +pub type TAMPID = crate::Reg; +#[doc = "Tamper ID"] +pub mod tampid; +#[doc = "BKUP (rw) register accessor: an alias for `Reg`"] +pub type BKUP = crate::Reg; +#[doc = "Backup"] +pub mod bkup; diff --git a/pac/atsaml22j/src/rtc/mode1/bkup.rs b/pac/atsaml22j/src/rtc/mode1/bkup.rs new file mode 100644 index 000000000000..0d0a909e0bec --- /dev/null +++ b/pac/atsaml22j/src/rtc/mode1/bkup.rs @@ -0,0 +1,80 @@ +#[doc = "Register `BKUP%s` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BKUP%s` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BKUP` reader - Backup"] +pub type BKUP_R = crate::FieldReader; +#[doc = "Field `BKUP` writer - Backup"] +pub type BKUP_W<'a, const O: u8> = crate::FieldWriter<'a, u32, BKUP_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - Backup"] + #[inline(always)] + pub fn bkup(&self) -> BKUP_R { + BKUP_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Backup"] + #[inline(always)] + #[must_use] + pub fn bkup(&mut self) -> BKUP_W<0> { + BKUP_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Backup\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bkup](index.html) module"] +pub struct BKUP_SPEC; +impl crate::RegisterSpec for BKUP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [bkup::R](R) reader structure"] +impl crate::Readable for BKUP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [bkup::W](W) writer structure"] +impl crate::Writable for BKUP_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BKUP%s to value 0"] +impl crate::Resettable for BKUP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/rtc/mode1/comp.rs b/pac/atsaml22j/src/rtc/mode1/comp.rs new file mode 100644 index 000000000000..d73905d6dec2 --- /dev/null +++ b/pac/atsaml22j/src/rtc/mode1/comp.rs @@ -0,0 +1,80 @@ +#[doc = "Register `COMP%s` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COMP%s` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COMP` reader - Compare Value"] +pub type COMP_R = crate::FieldReader; +#[doc = "Field `COMP` writer - Compare Value"] +pub type COMP_W<'a, const O: u8> = crate::FieldWriter<'a, u16, COMP_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - Compare Value"] + #[inline(always)] + pub fn comp(&self) -> COMP_R { + COMP_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - Compare Value"] + #[inline(always)] + #[must_use] + pub fn comp(&mut self) -> COMP_W<0> { + COMP_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Compare n Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [comp](index.html) module"] +pub struct COMP_SPEC; +impl crate::RegisterSpec for COMP_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [comp::R](R) reader structure"] +impl crate::Readable for COMP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [comp::W](W) writer structure"] +impl crate::Writable for COMP_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COMP%s to value 0"] +impl crate::Resettable for COMP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/rtc/mode1/count.rs b/pac/atsaml22j/src/rtc/mode1/count.rs new file mode 100644 index 000000000000..c34a01de1419 --- /dev/null +++ b/pac/atsaml22j/src/rtc/mode1/count.rs @@ -0,0 +1,80 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub type COUNT_R = crate::FieldReader; +#[doc = "Field `COUNT` writer - Counter Value"] +pub type COUNT_W<'a, const O: u8> = crate::FieldWriter<'a, u16, COUNT_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - Counter Value"] + #[inline(always)] + #[must_use] + pub fn count(&mut self) -> COUNT_W<0> { + COUNT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Counter Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/rtc/mode1/ctrla.rs b/pac/atsaml22j/src/rtc/mode1/ctrla.rs new file mode 100644 index 000000000000..eb08de3c0efa --- /dev/null +++ b/pac/atsaml22j/src/rtc/mode1/ctrla.rs @@ -0,0 +1,403 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub type SWRST_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRLA_SPEC, bool, O>; +#[doc = "Field `ENABLE` reader - Enable"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - Enable"] +pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRLA_SPEC, bool, O>; +#[doc = "Field `MODE` reader - Operating Mode"] +pub type MODE_R = crate::FieldReader; +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum MODESELECT_A { + #[doc = "0: Mode 0: 32-bit Counter"] + COUNT32 = 0, + #[doc = "1: Mode 1: 16-bit Counter"] + COUNT16 = 1, + #[doc = "2: Mode 2: Clock/Calendar"] + CLOCK = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODESELECT_A) -> Self { + variant as _ + } +} +impl MODE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODESELECT_A::COUNT32), + 1 => Some(MODESELECT_A::COUNT16), + 2 => Some(MODESELECT_A::CLOCK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + *self == MODESELECT_A::COUNT32 + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + *self == MODESELECT_A::COUNT16 + } + #[doc = "Checks if the value of the field is `CLOCK`"] + #[inline(always)] + pub fn is_clock(&self) -> bool { + *self == MODESELECT_A::CLOCK + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub type MODE_W<'a, const O: u8> = crate::FieldWriter<'a, u16, CTRLA_SPEC, u8, MODESELECT_A, 2, O>; +impl<'a, const O: u8> MODE_W<'a, O> { + #[doc = "Mode 0: 32-bit Counter"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODESELECT_A::COUNT32) + } + #[doc = "Mode 1: 16-bit Counter"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODESELECT_A::COUNT16) + } + #[doc = "Mode 2: Clock/Calendar"] + #[inline(always)] + pub fn clock(self) -> &'a mut W { + self.variant(MODESELECT_A::CLOCK) + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub type PRESCALER_R = crate::FieldReader; +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum PRESCALERSELECT_A { + #[doc = "0: CLK_RTC_CNT = GCLK_RTC/1"] + OFF = 0, + #[doc = "1: CLK_RTC_CNT = GCLK_RTC/1"] + DIV1 = 1, + #[doc = "2: CLK_RTC_CNT = GCLK_RTC/2"] + DIV2 = 2, + #[doc = "3: CLK_RTC_CNT = GCLK_RTC/4"] + DIV4 = 3, + #[doc = "4: CLK_RTC_CNT = GCLK_RTC/8"] + DIV8 = 4, + #[doc = "5: CLK_RTC_CNT = GCLK_RTC/16"] + DIV16 = 5, + #[doc = "6: CLK_RTC_CNT = GCLK_RTC/32"] + DIV32 = 6, + #[doc = "7: CLK_RTC_CNT = GCLK_RTC/64"] + DIV64 = 7, + #[doc = "8: CLK_RTC_CNT = GCLK_RTC/128"] + DIV128 = 8, + #[doc = "9: CLK_RTC_CNT = GCLK_RTC/256"] + DIV256 = 9, + #[doc = "10: CLK_RTC_CNT = GCLK_RTC/512"] + DIV512 = 10, + #[doc = "11: CLK_RTC_CNT = GCLK_RTC/1024"] + DIV1024 = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALERSELECT_A) -> Self { + variant as _ + } +} +impl PRESCALER_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCALERSELECT_A::OFF), + 1 => Some(PRESCALERSELECT_A::DIV1), + 2 => Some(PRESCALERSELECT_A::DIV2), + 3 => Some(PRESCALERSELECT_A::DIV4), + 4 => Some(PRESCALERSELECT_A::DIV8), + 5 => Some(PRESCALERSELECT_A::DIV16), + 6 => Some(PRESCALERSELECT_A::DIV32), + 7 => Some(PRESCALERSELECT_A::DIV64), + 8 => Some(PRESCALERSELECT_A::DIV128), + 9 => Some(PRESCALERSELECT_A::DIV256), + 10 => Some(PRESCALERSELECT_A::DIV512), + 11 => Some(PRESCALERSELECT_A::DIV1024), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == PRESCALERSELECT_A::OFF + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + *self == PRESCALERSELECT_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + *self == PRESCALERSELECT_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + *self == PRESCALERSELECT_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + *self == PRESCALERSELECT_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + *self == PRESCALERSELECT_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + *self == PRESCALERSELECT_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + *self == PRESCALERSELECT_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + *self == PRESCALERSELECT_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + *self == PRESCALERSELECT_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV512`"] + #[inline(always)] + pub fn is_div512(&self) -> bool { + *self == PRESCALERSELECT_A::DIV512 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + *self == PRESCALERSELECT_A::DIV1024 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub type PRESCALER_W<'a, const O: u8> = + crate::FieldWriter<'a, u16, CTRLA_SPEC, u8, PRESCALERSELECT_A, 4, O>; +impl<'a, const O: u8> PRESCALER_W<'a, O> { + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::OFF) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV1) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV2) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV4) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV8) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV16) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV32) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV64) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV128) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV256) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/512"] + #[inline(always)] + pub fn div512(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV512) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV1024) + } +} +#[doc = "Field `BKTRST` reader - BKUP Registers Reset On Tamper Enable"] +pub type BKTRST_R = crate::BitReader; +#[doc = "Field `BKTRST` writer - BKUP Registers Reset On Tamper Enable"] +pub type BKTRST_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRLA_SPEC, bool, O>; +#[doc = "Field `GPTRST` reader - GP Registers Reset On Tamper Enable"] +pub type GPTRST_R = crate::BitReader; +#[doc = "Field `GPTRST` writer - GP Registers Reset On Tamper Enable"] +pub type GPTRST_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRLA_SPEC, bool, O>; +#[doc = "Field `COUNTSYNC` reader - Count Read Synchronization Enable"] +pub type COUNTSYNC_R = crate::BitReader; +#[doc = "Field `COUNTSYNC` writer - Count Read Synchronization Enable"] +pub type COUNTSYNC_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRLA_SPEC, bool, O>; +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 13 - BKUP Registers Reset On Tamper Enable"] + #[inline(always)] + pub fn bktrst(&self) -> BKTRST_R { + BKTRST_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - GP Registers Reset On Tamper Enable"] + #[inline(always)] + pub fn gptrst(&self) -> GPTRST_R { + GPTRST_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Count Read Synchronization Enable"] + #[inline(always)] + pub fn countsync(&self) -> COUNTSYNC_R { + COUNTSYNC_R::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + #[must_use] + pub fn swrst(&mut self) -> SWRST_W<0> { + SWRST_W::new(self) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W<1> { + ENABLE_W::new(self) + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> MODE_W<2> { + MODE_W::new(self) + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + #[must_use] + pub fn prescaler(&mut self) -> PRESCALER_W<8> { + PRESCALER_W::new(self) + } + #[doc = "Bit 13 - BKUP Registers Reset On Tamper Enable"] + #[inline(always)] + #[must_use] + pub fn bktrst(&mut self) -> BKTRST_W<13> { + BKTRST_W::new(self) + } + #[doc = "Bit 14 - GP Registers Reset On Tamper Enable"] + #[inline(always)] + #[must_use] + pub fn gptrst(&mut self) -> GPTRST_W<14> { + GPTRST_W::new(self) + } + #[doc = "Bit 15 - Count Read Synchronization Enable"] + #[inline(always)] + #[must_use] + pub fn countsync(&mut self) -> COUNTSYNC_W<15> { + COUNTSYNC_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/rtc/mode1/ctrlb.rs b/pac/atsaml22j/src/rtc/mode1/ctrlb.rs new file mode 100644 index 000000000000..0768536857d8 --- /dev/null +++ b/pac/atsaml22j/src/rtc/mode1/ctrlb.rs @@ -0,0 +1,424 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GP0EN` reader - General Purpose 0 Enable"] +pub type GP0EN_R = crate::BitReader; +#[doc = "Field `GP0EN` writer - General Purpose 0 Enable"] +pub type GP0EN_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRLB_SPEC, bool, O>; +#[doc = "Field `DEBMAJ` reader - Debouncer Majority Enable"] +pub type DEBMAJ_R = crate::BitReader; +#[doc = "Field `DEBMAJ` writer - Debouncer Majority Enable"] +pub type DEBMAJ_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRLB_SPEC, bool, O>; +#[doc = "Field `DEBASYNC` reader - Debouncer Asynchronous Enable"] +pub type DEBASYNC_R = crate::BitReader; +#[doc = "Field `DEBASYNC` writer - Debouncer Asynchronous Enable"] +pub type DEBASYNC_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRLB_SPEC, bool, O>; +#[doc = "Field `RTCOUT` reader - RTC Output Enable"] +pub type RTCOUT_R = crate::BitReader; +#[doc = "Field `RTCOUT` writer - RTC Output Enable"] +pub type RTCOUT_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRLB_SPEC, bool, O>; +#[doc = "Field `DMAEN` reader - DMA Enable"] +pub type DMAEN_R = crate::BitReader; +#[doc = "Field `DMAEN` writer - DMA Enable"] +pub type DMAEN_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRLB_SPEC, bool, O>; +#[doc = "Field `DEBF` reader - Debounce Freqnuency"] +pub type DEBF_R = crate::FieldReader; +#[doc = "Debounce Freqnuency\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum DEBFSELECT_A { + #[doc = "0: CLK_RTC_DEB = CLK_RTC/2"] + DIV2 = 0, + #[doc = "1: CLK_RTC_DEB = CLK_RTC/4"] + DIV4 = 1, + #[doc = "2: CLK_RTC_DEB = CLK_RTC/8"] + DIV8 = 2, + #[doc = "3: CLK_RTC_DEB = CLK_RTC/16"] + DIV16 = 3, + #[doc = "4: CLK_RTC_DEB = CLK_RTC/32"] + DIV32 = 4, + #[doc = "5: CLK_RTC_DEB = CLK_RTC/64"] + DIV64 = 5, + #[doc = "6: CLK_RTC_DEB = CLK_RTC/128"] + DIV128 = 6, + #[doc = "7: CLK_RTC_DEB = CLK_RTC/256"] + DIV256 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DEBFSELECT_A) -> Self { + variant as _ + } +} +impl DEBF_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DEBFSELECT_A { + match self.bits { + 0 => DEBFSELECT_A::DIV2, + 1 => DEBFSELECT_A::DIV4, + 2 => DEBFSELECT_A::DIV8, + 3 => DEBFSELECT_A::DIV16, + 4 => DEBFSELECT_A::DIV32, + 5 => DEBFSELECT_A::DIV64, + 6 => DEBFSELECT_A::DIV128, + 7 => DEBFSELECT_A::DIV256, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + *self == DEBFSELECT_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + *self == DEBFSELECT_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + *self == DEBFSELECT_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + *self == DEBFSELECT_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + *self == DEBFSELECT_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + *self == DEBFSELECT_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + *self == DEBFSELECT_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + *self == DEBFSELECT_A::DIV256 + } +} +#[doc = "Field `DEBF` writer - Debounce Freqnuency"] +pub type DEBF_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u16, CTRLB_SPEC, u8, DEBFSELECT_A, 3, O>; +impl<'a, const O: u8> DEBF_W<'a, O> { + #[doc = "CLK_RTC_DEB = CLK_RTC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(DEBFSELECT_A::DIV2) + } + #[doc = "CLK_RTC_DEB = CLK_RTC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(DEBFSELECT_A::DIV4) + } + #[doc = "CLK_RTC_DEB = CLK_RTC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(DEBFSELECT_A::DIV8) + } + #[doc = "CLK_RTC_DEB = CLK_RTC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(DEBFSELECT_A::DIV16) + } + #[doc = "CLK_RTC_DEB = CLK_RTC/32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(DEBFSELECT_A::DIV32) + } + #[doc = "CLK_RTC_DEB = CLK_RTC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(DEBFSELECT_A::DIV64) + } + #[doc = "CLK_RTC_DEB = CLK_RTC/128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(DEBFSELECT_A::DIV128) + } + #[doc = "CLK_RTC_DEB = CLK_RTC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(DEBFSELECT_A::DIV256) + } +} +#[doc = "Field `ACTF` reader - Active Layer Freqnuency"] +pub type ACTF_R = crate::FieldReader; +#[doc = "Active Layer Freqnuency\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum ACTFSELECT_A { + #[doc = "0: CLK_RTC_OUT = CLK_RTC/2"] + DIV2 = 0, + #[doc = "1: CLK_RTC_OUT = CLK_RTC/4"] + DIV4 = 1, + #[doc = "2: CLK_RTC_OUT = CLK_RTC/8"] + DIV8 = 2, + #[doc = "3: CLK_RTC_OUT = CLK_RTC/16"] + DIV16 = 3, + #[doc = "4: CLK_RTC_OUT = CLK_RTC/32"] + DIV32 = 4, + #[doc = "5: CLK_RTC_OUT = CLK_RTC/64"] + DIV64 = 5, + #[doc = "6: CLK_RTC_OUT = CLK_RTC/128"] + DIV128 = 6, + #[doc = "7: CLK_RTC_OUT = CLK_RTC/256"] + DIV256 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ACTFSELECT_A) -> Self { + variant as _ + } +} +impl ACTF_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ACTFSELECT_A { + match self.bits { + 0 => ACTFSELECT_A::DIV2, + 1 => ACTFSELECT_A::DIV4, + 2 => ACTFSELECT_A::DIV8, + 3 => ACTFSELECT_A::DIV16, + 4 => ACTFSELECT_A::DIV32, + 5 => ACTFSELECT_A::DIV64, + 6 => ACTFSELECT_A::DIV128, + 7 => ACTFSELECT_A::DIV256, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + *self == ACTFSELECT_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + *self == ACTFSELECT_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + *self == ACTFSELECT_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + *self == ACTFSELECT_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + *self == ACTFSELECT_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + *self == ACTFSELECT_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + *self == ACTFSELECT_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + *self == ACTFSELECT_A::DIV256 + } +} +#[doc = "Field `ACTF` writer - Active Layer Freqnuency"] +pub type ACTF_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u16, CTRLB_SPEC, u8, ACTFSELECT_A, 3, O>; +impl<'a, const O: u8> ACTF_W<'a, O> { + #[doc = "CLK_RTC_OUT = CLK_RTC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(ACTFSELECT_A::DIV2) + } + #[doc = "CLK_RTC_OUT = CLK_RTC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(ACTFSELECT_A::DIV4) + } + #[doc = "CLK_RTC_OUT = CLK_RTC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(ACTFSELECT_A::DIV8) + } + #[doc = "CLK_RTC_OUT = CLK_RTC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(ACTFSELECT_A::DIV16) + } + #[doc = "CLK_RTC_OUT = CLK_RTC/32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(ACTFSELECT_A::DIV32) + } + #[doc = "CLK_RTC_OUT = CLK_RTC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(ACTFSELECT_A::DIV64) + } + #[doc = "CLK_RTC_OUT = CLK_RTC/128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(ACTFSELECT_A::DIV128) + } + #[doc = "CLK_RTC_OUT = CLK_RTC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(ACTFSELECT_A::DIV256) + } +} +impl R { + #[doc = "Bit 0 - General Purpose 0 Enable"] + #[inline(always)] + pub fn gp0en(&self) -> GP0EN_R { + GP0EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 4 - Debouncer Majority Enable"] + #[inline(always)] + pub fn debmaj(&self) -> DEBMAJ_R { + DEBMAJ_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Debouncer Asynchronous Enable"] + #[inline(always)] + pub fn debasync(&self) -> DEBASYNC_R { + DEBASYNC_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - RTC Output Enable"] + #[inline(always)] + pub fn rtcout(&self) -> RTCOUT_R { + RTCOUT_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - DMA Enable"] + #[inline(always)] + pub fn dmaen(&self) -> DMAEN_R { + DMAEN_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:10 - Debounce Freqnuency"] + #[inline(always)] + pub fn debf(&self) -> DEBF_R { + DEBF_R::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bits 12:14 - Active Layer Freqnuency"] + #[inline(always)] + pub fn actf(&self) -> ACTF_R { + ACTF_R::new(((self.bits >> 12) & 7) as u8) + } +} +impl W { + #[doc = "Bit 0 - General Purpose 0 Enable"] + #[inline(always)] + #[must_use] + pub fn gp0en(&mut self) -> GP0EN_W<0> { + GP0EN_W::new(self) + } + #[doc = "Bit 4 - Debouncer Majority Enable"] + #[inline(always)] + #[must_use] + pub fn debmaj(&mut self) -> DEBMAJ_W<4> { + DEBMAJ_W::new(self) + } + #[doc = "Bit 5 - Debouncer Asynchronous Enable"] + #[inline(always)] + #[must_use] + pub fn debasync(&mut self) -> DEBASYNC_W<5> { + DEBASYNC_W::new(self) + } + #[doc = "Bit 6 - RTC Output Enable"] + #[inline(always)] + #[must_use] + pub fn rtcout(&mut self) -> RTCOUT_W<6> { + RTCOUT_W::new(self) + } + #[doc = "Bit 7 - DMA Enable"] + #[inline(always)] + #[must_use] + pub fn dmaen(&mut self) -> DMAEN_W<7> { + DMAEN_W::new(self) + } + #[doc = "Bits 8:10 - Debounce Freqnuency"] + #[inline(always)] + #[must_use] + pub fn debf(&mut self) -> DEBF_W<8> { + DEBF_W::new(self) + } + #[doc = "Bits 12:14 - Active Layer Freqnuency"] + #[inline(always)] + #[must_use] + pub fn actf(&mut self) -> ACTF_W<12> { + ACTF_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/rtc/mode1/dbgctrl.rs b/pac/atsaml22j/src/rtc/mode1/dbgctrl.rs new file mode 100644 index 000000000000..271f8aa633ac --- /dev/null +++ b/pac/atsaml22j/src/rtc/mode1/dbgctrl.rs @@ -0,0 +1,80 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub type DBGRUN_R = crate::BitReader; +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub type DBGRUN_W<'a, const O: u8> = crate::BitWriter<'a, u8, DBGCTRL_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + #[must_use] + pub fn dbgrun(&mut self) -> DBGRUN_W<0> { + DBGRUN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/rtc/mode1/evctrl.rs b/pac/atsaml22j/src/rtc/mode1/evctrl.rs new file mode 100644 index 000000000000..4fa0ade8c9e7 --- /dev/null +++ b/pac/atsaml22j/src/rtc/mode1/evctrl.rs @@ -0,0 +1,260 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PEREO0` reader - Periodic Interval 0 Event Output Enable"] +pub type PEREO0_R = crate::BitReader; +#[doc = "Field `PEREO0` writer - Periodic Interval 0 Event Output Enable"] +pub type PEREO0_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVCTRL_SPEC, bool, O>; +#[doc = "Field `PEREO1` reader - Periodic Interval 1 Event Output Enable"] +pub type PEREO1_R = crate::BitReader; +#[doc = "Field `PEREO1` writer - Periodic Interval 1 Event Output Enable"] +pub type PEREO1_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVCTRL_SPEC, bool, O>; +#[doc = "Field `PEREO2` reader - Periodic Interval 2 Event Output Enable"] +pub type PEREO2_R = crate::BitReader; +#[doc = "Field `PEREO2` writer - Periodic Interval 2 Event Output Enable"] +pub type PEREO2_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVCTRL_SPEC, bool, O>; +#[doc = "Field `PEREO3` reader - Periodic Interval 3 Event Output Enable"] +pub type PEREO3_R = crate::BitReader; +#[doc = "Field `PEREO3` writer - Periodic Interval 3 Event Output Enable"] +pub type PEREO3_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVCTRL_SPEC, bool, O>; +#[doc = "Field `PEREO4` reader - Periodic Interval 4 Event Output Enable"] +pub type PEREO4_R = crate::BitReader; +#[doc = "Field `PEREO4` writer - Periodic Interval 4 Event Output Enable"] +pub type PEREO4_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVCTRL_SPEC, bool, O>; +#[doc = "Field `PEREO5` reader - Periodic Interval 5 Event Output Enable"] +pub type PEREO5_R = crate::BitReader; +#[doc = "Field `PEREO5` writer - Periodic Interval 5 Event Output Enable"] +pub type PEREO5_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVCTRL_SPEC, bool, O>; +#[doc = "Field `PEREO6` reader - Periodic Interval 6 Event Output Enable"] +pub type PEREO6_R = crate::BitReader; +#[doc = "Field `PEREO6` writer - Periodic Interval 6 Event Output Enable"] +pub type PEREO6_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVCTRL_SPEC, bool, O>; +#[doc = "Field `PEREO7` reader - Periodic Interval 7 Event Output Enable"] +pub type PEREO7_R = crate::BitReader; +#[doc = "Field `PEREO7` writer - Periodic Interval 7 Event Output Enable"] +pub type PEREO7_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVCTRL_SPEC, bool, O>; +#[doc = "Field `CMPEO0` reader - Compare 0 Event Output Enable"] +pub type CMPEO0_R = crate::BitReader; +#[doc = "Field `CMPEO0` writer - Compare 0 Event Output Enable"] +pub type CMPEO0_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVCTRL_SPEC, bool, O>; +#[doc = "Field `CMPEO1` reader - Compare 1 Event Output Enable"] +pub type CMPEO1_R = crate::BitReader; +#[doc = "Field `CMPEO1` writer - Compare 1 Event Output Enable"] +pub type CMPEO1_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVCTRL_SPEC, bool, O>; +#[doc = "Field `TAMPEREO` reader - Tamper Event Output Enable"] +pub type TAMPEREO_R = crate::BitReader; +#[doc = "Field `TAMPEREO` writer - Tamper Event Output Enable"] +pub type TAMPEREO_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVCTRL_SPEC, bool, O>; +#[doc = "Field `OVFEO` reader - Overflow Event Output Enable"] +pub type OVFEO_R = crate::BitReader; +#[doc = "Field `OVFEO` writer - Overflow Event Output Enable"] +pub type OVFEO_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVCTRL_SPEC, bool, O>; +#[doc = "Field `TAMPEVEI` reader - Tamper Event Input Enable"] +pub type TAMPEVEI_R = crate::BitReader; +#[doc = "Field `TAMPEVEI` writer - Tamper Event Input Enable"] +pub type TAMPEVEI_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVCTRL_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&self) -> PEREO0_R { + PEREO0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&self) -> PEREO1_R { + PEREO1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&self) -> PEREO2_R { + PEREO2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&self) -> PEREO3_R { + PEREO3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&self) -> PEREO4_R { + PEREO4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&self) -> PEREO5_R { + PEREO5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&self) -> PEREO6_R { + PEREO6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&self) -> PEREO7_R { + PEREO7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Compare 0 Event Output Enable"] + #[inline(always)] + pub fn cmpeo0(&self) -> CMPEO0_R { + CMPEO0_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Compare 1 Event Output Enable"] + #[inline(always)] + pub fn cmpeo1(&self) -> CMPEO1_R { + CMPEO1_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 14 - Tamper Event Output Enable"] + #[inline(always)] + pub fn tampereo(&self) -> TAMPEREO_R { + TAMPEREO_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Tamper Event Input Enable"] + #[inline(always)] + pub fn tampevei(&self) -> TAMPEVEI_R { + TAMPEVEI_R::new(((self.bits >> 16) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + #[must_use] + pub fn pereo0(&mut self) -> PEREO0_W<0> { + PEREO0_W::new(self) + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + #[must_use] + pub fn pereo1(&mut self) -> PEREO1_W<1> { + PEREO1_W::new(self) + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + #[must_use] + pub fn pereo2(&mut self) -> PEREO2_W<2> { + PEREO2_W::new(self) + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + #[must_use] + pub fn pereo3(&mut self) -> PEREO3_W<3> { + PEREO3_W::new(self) + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + #[must_use] + pub fn pereo4(&mut self) -> PEREO4_W<4> { + PEREO4_W::new(self) + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + #[must_use] + pub fn pereo5(&mut self) -> PEREO5_W<5> { + PEREO5_W::new(self) + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + #[must_use] + pub fn pereo6(&mut self) -> PEREO6_W<6> { + PEREO6_W::new(self) + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + #[must_use] + pub fn pereo7(&mut self) -> PEREO7_W<7> { + PEREO7_W::new(self) + } + #[doc = "Bit 8 - Compare 0 Event Output Enable"] + #[inline(always)] + #[must_use] + pub fn cmpeo0(&mut self) -> CMPEO0_W<8> { + CMPEO0_W::new(self) + } + #[doc = "Bit 9 - Compare 1 Event Output Enable"] + #[inline(always)] + #[must_use] + pub fn cmpeo1(&mut self) -> CMPEO1_W<9> { + CMPEO1_W::new(self) + } + #[doc = "Bit 14 - Tamper Event Output Enable"] + #[inline(always)] + #[must_use] + pub fn tampereo(&mut self) -> TAMPEREO_W<14> { + TAMPEREO_W::new(self) + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + #[must_use] + pub fn ovfeo(&mut self) -> OVFEO_W<15> { + OVFEO_W::new(self) + } + #[doc = "Bit 16 - Tamper Event Input Enable"] + #[inline(always)] + #[must_use] + pub fn tampevei(&mut self) -> TAMPEVEI_W<16> { + TAMPEVEI_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/rtc/mode1/freqcorr.rs b/pac/atsaml22j/src/rtc/mode1/freqcorr.rs new file mode 100644 index 000000000000..0a0b886b28f6 --- /dev/null +++ b/pac/atsaml22j/src/rtc/mode1/freqcorr.rs @@ -0,0 +1,95 @@ +#[doc = "Register `FREQCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FREQCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VALUE` reader - Correction Value"] +pub type VALUE_R = crate::FieldReader; +#[doc = "Field `VALUE` writer - Correction Value"] +pub type VALUE_W<'a, const O: u8> = crate::FieldWriter<'a, u8, FREQCORR_SPEC, u8, u8, 7, O>; +#[doc = "Field `SIGN` reader - Correction Sign"] +pub type SIGN_R = crate::BitReader; +#[doc = "Field `SIGN` writer - Correction Sign"] +pub type SIGN_W<'a, const O: u8> = crate::BitWriter<'a, u8, FREQCORR_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new(self.bits & 0x7f) + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&self) -> SIGN_R { + SIGN_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + #[must_use] + pub fn value(&mut self) -> VALUE_W<0> { + VALUE_W::new(self) + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + #[must_use] + pub fn sign(&mut self) -> SIGN_W<7> { + SIGN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Frequency Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [freqcorr](index.html) module"] +pub struct FREQCORR_SPEC; +impl crate::RegisterSpec for FREQCORR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [freqcorr::R](R) reader structure"] +impl crate::Readable for FREQCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [freqcorr::W](W) writer structure"] +impl crate::Writable for FREQCORR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FREQCORR to value 0"] +impl crate::Resettable for FREQCORR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/rtc/mode1/gp.rs b/pac/atsaml22j/src/rtc/mode1/gp.rs new file mode 100644 index 000000000000..c674475e018c --- /dev/null +++ b/pac/atsaml22j/src/rtc/mode1/gp.rs @@ -0,0 +1,80 @@ +#[doc = "Register `GP%s` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GP%s` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GP` reader - General Purpose"] +pub type GP_R = crate::FieldReader; +#[doc = "Field `GP` writer - General Purpose"] +pub type GP_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GP_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - General Purpose"] + #[inline(always)] + pub fn gp(&self) -> GP_R { + GP_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - General Purpose"] + #[inline(always)] + #[must_use] + pub fn gp(&mut self) -> GP_W<0> { + GP_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "General Purpose\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gp](index.html) module"] +pub struct GP_SPEC; +impl crate::RegisterSpec for GP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gp::R](R) reader structure"] +impl crate::Readable for GP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gp::W](W) writer structure"] +impl crate::Writable for GP_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GP%s to value 0"] +impl crate::Resettable for GP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/rtc/mode1/intenclr.rs b/pac/atsaml22j/src/rtc/mode1/intenclr.rs new file mode 100644 index 000000000000..19fcae8c5f5d --- /dev/null +++ b/pac/atsaml22j/src/rtc/mode1/intenclr.rs @@ -0,0 +1,245 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0 Interrupt Enable"] +pub type PER0_R = crate::BitReader; +#[doc = "Field `PER0` writer - Periodic Interval 0 Interrupt Enable"] +pub type PER0_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENCLR_SPEC, bool, O>; +#[doc = "Field `PER1` reader - Periodic Interval 1 Interrupt Enable"] +pub type PER1_R = crate::BitReader; +#[doc = "Field `PER1` writer - Periodic Interval 1 Interrupt Enable"] +pub type PER1_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENCLR_SPEC, bool, O>; +#[doc = "Field `PER2` reader - Periodic Interval 2 Interrupt Enable"] +pub type PER2_R = crate::BitReader; +#[doc = "Field `PER2` writer - Periodic Interval 2 Interrupt Enable"] +pub type PER2_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENCLR_SPEC, bool, O>; +#[doc = "Field `PER3` reader - Periodic Interval 3 Interrupt Enable"] +pub type PER3_R = crate::BitReader; +#[doc = "Field `PER3` writer - Periodic Interval 3 Interrupt Enable"] +pub type PER3_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENCLR_SPEC, bool, O>; +#[doc = "Field `PER4` reader - Periodic Interval 4 Interrupt Enable"] +pub type PER4_R = crate::BitReader; +#[doc = "Field `PER4` writer - Periodic Interval 4 Interrupt Enable"] +pub type PER4_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENCLR_SPEC, bool, O>; +#[doc = "Field `PER5` reader - Periodic Interval 5 Interrupt Enable"] +pub type PER5_R = crate::BitReader; +#[doc = "Field `PER5` writer - Periodic Interval 5 Interrupt Enable"] +pub type PER5_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENCLR_SPEC, bool, O>; +#[doc = "Field `PER6` reader - Periodic Interval 6 Interrupt Enable"] +pub type PER6_R = crate::BitReader; +#[doc = "Field `PER6` writer - Periodic Interval 6 Interrupt Enable"] +pub type PER6_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENCLR_SPEC, bool, O>; +#[doc = "Field `PER7` reader - Periodic Interval 7 Interrupt Enable"] +pub type PER7_R = crate::BitReader; +#[doc = "Field `PER7` writer - Periodic Interval 7 Interrupt Enable"] +pub type PER7_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENCLR_SPEC, bool, O>; +#[doc = "Field `CMP0` reader - Compare 0 Interrupt Enable"] +pub type CMP0_R = crate::BitReader; +#[doc = "Field `CMP0` writer - Compare 0 Interrupt Enable"] +pub type CMP0_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENCLR_SPEC, bool, O>; +#[doc = "Field `CMP1` reader - Compare 1 Interrupt Enable"] +pub type CMP1_R = crate::BitReader; +#[doc = "Field `CMP1` writer - Compare 1 Interrupt Enable"] +pub type CMP1_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENCLR_SPEC, bool, O>; +#[doc = "Field `TAMPER` reader - Tamper Enable"] +pub type TAMPER_R = crate::BitReader; +#[doc = "Field `TAMPER` writer - Tamper Enable"] +pub type TAMPER_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENCLR_SPEC, bool, O>; +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub type OVF_R = crate::BitReader; +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub type OVF_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENCLR_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Compare 1 Interrupt Enable"] + #[inline(always)] + pub fn cmp1(&self) -> CMP1_R { + CMP1_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 14 - Tamper Enable"] + #[inline(always)] + pub fn tamper(&self) -> TAMPER_R { + TAMPER_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn per0(&mut self) -> PER0_W<0> { + PER0_W::new(self) + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn per1(&mut self) -> PER1_W<1> { + PER1_W::new(self) + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn per2(&mut self) -> PER2_W<2> { + PER2_W::new(self) + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn per3(&mut self) -> PER3_W<3> { + PER3_W::new(self) + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn per4(&mut self) -> PER4_W<4> { + PER4_W::new(self) + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn per5(&mut self) -> PER5_W<5> { + PER5_W::new(self) + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn per6(&mut self) -> PER6_W<6> { + PER6_W::new(self) + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn per7(&mut self) -> PER7_W<7> { + PER7_W::new(self) + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn cmp0(&mut self) -> CMP0_W<8> { + CMP0_W::new(self) + } + #[doc = "Bit 9 - Compare 1 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn cmp1(&mut self) -> CMP1_W<9> { + CMP1_W::new(self) + } + #[doc = "Bit 14 - Tamper Enable"] + #[inline(always)] + #[must_use] + pub fn tamper(&mut self) -> TAMPER_W<14> { + TAMPER_W::new(self) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn ovf(&mut self) -> OVF_W<15> { + OVF_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/rtc/mode1/intenset.rs b/pac/atsaml22j/src/rtc/mode1/intenset.rs new file mode 100644 index 000000000000..67cce1925e25 --- /dev/null +++ b/pac/atsaml22j/src/rtc/mode1/intenset.rs @@ -0,0 +1,245 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0 Interrupt Enable"] +pub type PER0_R = crate::BitReader; +#[doc = "Field `PER0` writer - Periodic Interval 0 Interrupt Enable"] +pub type PER0_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENSET_SPEC, bool, O>; +#[doc = "Field `PER1` reader - Periodic Interval 1 Interrupt Enable"] +pub type PER1_R = crate::BitReader; +#[doc = "Field `PER1` writer - Periodic Interval 1 Interrupt Enable"] +pub type PER1_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENSET_SPEC, bool, O>; +#[doc = "Field `PER2` reader - Periodic Interval 2 Interrupt Enable"] +pub type PER2_R = crate::BitReader; +#[doc = "Field `PER2` writer - Periodic Interval 2 Interrupt Enable"] +pub type PER2_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENSET_SPEC, bool, O>; +#[doc = "Field `PER3` reader - Periodic Interval 3 Interrupt Enable"] +pub type PER3_R = crate::BitReader; +#[doc = "Field `PER3` writer - Periodic Interval 3 Interrupt Enable"] +pub type PER3_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENSET_SPEC, bool, O>; +#[doc = "Field `PER4` reader - Periodic Interval 4 Interrupt Enable"] +pub type PER4_R = crate::BitReader; +#[doc = "Field `PER4` writer - Periodic Interval 4 Interrupt Enable"] +pub type PER4_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENSET_SPEC, bool, O>; +#[doc = "Field `PER5` reader - Periodic Interval 5 Interrupt Enable"] +pub type PER5_R = crate::BitReader; +#[doc = "Field `PER5` writer - Periodic Interval 5 Interrupt Enable"] +pub type PER5_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENSET_SPEC, bool, O>; +#[doc = "Field `PER6` reader - Periodic Interval 6 Interrupt Enable"] +pub type PER6_R = crate::BitReader; +#[doc = "Field `PER6` writer - Periodic Interval 6 Interrupt Enable"] +pub type PER6_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENSET_SPEC, bool, O>; +#[doc = "Field `PER7` reader - Periodic Interval 7 Interrupt Enable"] +pub type PER7_R = crate::BitReader; +#[doc = "Field `PER7` writer - Periodic Interval 7 Interrupt Enable"] +pub type PER7_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENSET_SPEC, bool, O>; +#[doc = "Field `CMP0` reader - Compare 0 Interrupt Enable"] +pub type CMP0_R = crate::BitReader; +#[doc = "Field `CMP0` writer - Compare 0 Interrupt Enable"] +pub type CMP0_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENSET_SPEC, bool, O>; +#[doc = "Field `CMP1` reader - Compare 1 Interrupt Enable"] +pub type CMP1_R = crate::BitReader; +#[doc = "Field `CMP1` writer - Compare 1 Interrupt Enable"] +pub type CMP1_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENSET_SPEC, bool, O>; +#[doc = "Field `TAMPER` reader - Tamper Enable"] +pub type TAMPER_R = crate::BitReader; +#[doc = "Field `TAMPER` writer - Tamper Enable"] +pub type TAMPER_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENSET_SPEC, bool, O>; +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub type OVF_R = crate::BitReader; +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub type OVF_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENSET_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Compare 1 Interrupt Enable"] + #[inline(always)] + pub fn cmp1(&self) -> CMP1_R { + CMP1_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 14 - Tamper Enable"] + #[inline(always)] + pub fn tamper(&self) -> TAMPER_R { + TAMPER_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn per0(&mut self) -> PER0_W<0> { + PER0_W::new(self) + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn per1(&mut self) -> PER1_W<1> { + PER1_W::new(self) + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn per2(&mut self) -> PER2_W<2> { + PER2_W::new(self) + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn per3(&mut self) -> PER3_W<3> { + PER3_W::new(self) + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn per4(&mut self) -> PER4_W<4> { + PER4_W::new(self) + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn per5(&mut self) -> PER5_W<5> { + PER5_W::new(self) + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn per6(&mut self) -> PER6_W<6> { + PER6_W::new(self) + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn per7(&mut self) -> PER7_W<7> { + PER7_W::new(self) + } + #[doc = "Bit 8 - Compare 0 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn cmp0(&mut self) -> CMP0_W<8> { + CMP0_W::new(self) + } + #[doc = "Bit 9 - Compare 1 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn cmp1(&mut self) -> CMP1_W<9> { + CMP1_W::new(self) + } + #[doc = "Bit 14 - Tamper Enable"] + #[inline(always)] + #[must_use] + pub fn tamper(&mut self) -> TAMPER_W<14> { + TAMPER_W::new(self) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn ovf(&mut self) -> OVF_W<15> { + OVF_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/rtc/mode1/intflag.rs b/pac/atsaml22j/src/rtc/mode1/intflag.rs new file mode 100644 index 000000000000..29da28e205ca --- /dev/null +++ b/pac/atsaml22j/src/rtc/mode1/intflag.rs @@ -0,0 +1,245 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0"] +pub type PER0_R = crate::BitReader; +#[doc = "Field `PER0` writer - Periodic Interval 0"] +pub type PER0_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTFLAG_SPEC, bool, O>; +#[doc = "Field `PER1` reader - Periodic Interval 1"] +pub type PER1_R = crate::BitReader; +#[doc = "Field `PER1` writer - Periodic Interval 1"] +pub type PER1_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTFLAG_SPEC, bool, O>; +#[doc = "Field `PER2` reader - Periodic Interval 2"] +pub type PER2_R = crate::BitReader; +#[doc = "Field `PER2` writer - Periodic Interval 2"] +pub type PER2_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTFLAG_SPEC, bool, O>; +#[doc = "Field `PER3` reader - Periodic Interval 3"] +pub type PER3_R = crate::BitReader; +#[doc = "Field `PER3` writer - Periodic Interval 3"] +pub type PER3_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTFLAG_SPEC, bool, O>; +#[doc = "Field `PER4` reader - Periodic Interval 4"] +pub type PER4_R = crate::BitReader; +#[doc = "Field `PER4` writer - Periodic Interval 4"] +pub type PER4_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTFLAG_SPEC, bool, O>; +#[doc = "Field `PER5` reader - Periodic Interval 5"] +pub type PER5_R = crate::BitReader; +#[doc = "Field `PER5` writer - Periodic Interval 5"] +pub type PER5_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTFLAG_SPEC, bool, O>; +#[doc = "Field `PER6` reader - Periodic Interval 6"] +pub type PER6_R = crate::BitReader; +#[doc = "Field `PER6` writer - Periodic Interval 6"] +pub type PER6_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTFLAG_SPEC, bool, O>; +#[doc = "Field `PER7` reader - Periodic Interval 7"] +pub type PER7_R = crate::BitReader; +#[doc = "Field `PER7` writer - Periodic Interval 7"] +pub type PER7_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTFLAG_SPEC, bool, O>; +#[doc = "Field `CMP0` reader - Compare 0"] +pub type CMP0_R = crate::BitReader; +#[doc = "Field `CMP0` writer - Compare 0"] +pub type CMP0_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTFLAG_SPEC, bool, O>; +#[doc = "Field `CMP1` reader - Compare 1"] +pub type CMP1_R = crate::BitReader; +#[doc = "Field `CMP1` writer - Compare 1"] +pub type CMP1_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTFLAG_SPEC, bool, O>; +#[doc = "Field `TAMPER` reader - Tamper"] +pub type TAMPER_R = crate::BitReader; +#[doc = "Field `TAMPER` writer - Tamper"] +pub type TAMPER_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTFLAG_SPEC, bool, O>; +#[doc = "Field `OVF` reader - Overflow"] +pub type OVF_R = crate::BitReader; +#[doc = "Field `OVF` writer - Overflow"] +pub type OVF_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTFLAG_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Periodic Interval 0"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Compare 0"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Compare 1"] + #[inline(always)] + pub fn cmp1(&self) -> CMP1_R { + CMP1_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 14 - Tamper"] + #[inline(always)] + pub fn tamper(&self) -> TAMPER_R { + TAMPER_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0"] + #[inline(always)] + #[must_use] + pub fn per0(&mut self) -> PER0_W<0> { + PER0_W::new(self) + } + #[doc = "Bit 1 - Periodic Interval 1"] + #[inline(always)] + #[must_use] + pub fn per1(&mut self) -> PER1_W<1> { + PER1_W::new(self) + } + #[doc = "Bit 2 - Periodic Interval 2"] + #[inline(always)] + #[must_use] + pub fn per2(&mut self) -> PER2_W<2> { + PER2_W::new(self) + } + #[doc = "Bit 3 - Periodic Interval 3"] + #[inline(always)] + #[must_use] + pub fn per3(&mut self) -> PER3_W<3> { + PER3_W::new(self) + } + #[doc = "Bit 4 - Periodic Interval 4"] + #[inline(always)] + #[must_use] + pub fn per4(&mut self) -> PER4_W<4> { + PER4_W::new(self) + } + #[doc = "Bit 5 - Periodic Interval 5"] + #[inline(always)] + #[must_use] + pub fn per5(&mut self) -> PER5_W<5> { + PER5_W::new(self) + } + #[doc = "Bit 6 - Periodic Interval 6"] + #[inline(always)] + #[must_use] + pub fn per6(&mut self) -> PER6_W<6> { + PER6_W::new(self) + } + #[doc = "Bit 7 - Periodic Interval 7"] + #[inline(always)] + #[must_use] + pub fn per7(&mut self) -> PER7_W<7> { + PER7_W::new(self) + } + #[doc = "Bit 8 - Compare 0"] + #[inline(always)] + #[must_use] + pub fn cmp0(&mut self) -> CMP0_W<8> { + CMP0_W::new(self) + } + #[doc = "Bit 9 - Compare 1"] + #[inline(always)] + #[must_use] + pub fn cmp1(&mut self) -> CMP1_W<9> { + CMP1_W::new(self) + } + #[doc = "Bit 14 - Tamper"] + #[inline(always)] + #[must_use] + pub fn tamper(&mut self) -> TAMPER_W<14> { + TAMPER_W::new(self) + } + #[doc = "Bit 15 - Overflow"] + #[inline(always)] + #[must_use] + pub fn ovf(&mut self) -> OVF_W<15> { + OVF_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/rtc/mode1/per.rs b/pac/atsaml22j/src/rtc/mode1/per.rs new file mode 100644 index 000000000000..a1bcb0f7d0ac --- /dev/null +++ b/pac/atsaml22j/src/rtc/mode1/per.rs @@ -0,0 +1,80 @@ +#[doc = "Register `PER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER` reader - Counter Period"] +pub type PER_R = crate::FieldReader; +#[doc = "Field `PER` writer - Counter Period"] +pub type PER_W<'a, const O: u8> = crate::FieldWriter<'a, u16, PER_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - Counter Period"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - Counter Period"] + #[inline(always)] + #[must_use] + pub fn per(&mut self) -> PER_W<0> { + PER_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE1 Counter Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per](index.html) module"] +pub struct PER_SPEC; +impl crate::RegisterSpec for PER_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [per::R](R) reader structure"] +impl crate::Readable for PER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per::W](W) writer structure"] +impl crate::Writable for PER_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PER to value 0"] +impl crate::Resettable for PER_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/rtc/mode1/syncbusy.rs b/pac/atsaml22j/src/rtc/mode1/syncbusy.rs new file mode 100644 index 000000000000..6d8a55491800 --- /dev/null +++ b/pac/atsaml22j/src/rtc/mode1/syncbusy.rs @@ -0,0 +1,100 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Bit Busy"] +pub type SWRST_R = crate::BitReader; +#[doc = "Field `ENABLE` reader - Enable Bit Busy"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `FREQCORR` reader - FREQCORR Register Busy"] +pub type FREQCORR_R = crate::BitReader; +#[doc = "Field `COUNT` reader - COUNT Register Busy"] +pub type COUNT_R = crate::BitReader; +#[doc = "Field `PER` reader - PER Register Busy"] +pub type PER_R = crate::BitReader; +#[doc = "Field `COMP0` reader - COMP 0 Register Busy"] +pub type COMP0_R = crate::BitReader; +#[doc = "Field `COMP1` reader - COMP 1 Register Busy"] +pub type COMP1_R = crate::BitReader; +#[doc = "Field `COUNTSYNC` reader - Count Synchronization Enable Bit Busy"] +pub type COUNTSYNC_R = crate::BitReader; +#[doc = "Field `GP0` reader - General Purpose 0 Register Busy"] +pub type GP0_R = crate::BitReader; +#[doc = "Field `GP1` reader - General Purpose 1 Register Busy"] +pub type GP1_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Software Reset Bit Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable Bit Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - FREQCORR Register Busy"] + #[inline(always)] + pub fn freqcorr(&self) -> FREQCORR_R { + FREQCORR_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - COUNT Register Busy"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - PER Register Busy"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - COMP 0 Register Busy"] + #[inline(always)] + pub fn comp0(&self) -> COMP0_R { + COMP0_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - COMP 1 Register Busy"] + #[inline(always)] + pub fn comp1(&self) -> COMP1_R { + COMP1_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 15 - Count Synchronization Enable Bit Busy"] + #[inline(always)] + pub fn countsync(&self) -> COUNTSYNC_R { + COUNTSYNC_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - General Purpose 0 Register Busy"] + #[inline(always)] + pub fn gp0(&self) -> GP0_R { + GP0_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - General Purpose 1 Register Busy"] + #[inline(always)] + pub fn gp1(&self) -> GP1_R { + GP1_R::new(((self.bits >> 17) & 1) != 0) + } +} +#[doc = "MODE1 Synchronization Busy Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/rtc/mode1/tampctrl.rs b/pac/atsaml22j/src/rtc/mode1/tampctrl.rs new file mode 100644 index 000000000000..8765e653ee07 --- /dev/null +++ b/pac/atsaml22j/src/rtc/mode1/tampctrl.rs @@ -0,0 +1,665 @@ +#[doc = "Register `TAMPCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TAMPCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `IN0ACT` reader - Tamper Input 0 Action"] +pub type IN0ACT_R = crate::FieldReader; +#[doc = "Tamper Input 0 Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum IN0ACTSELECT_A { + #[doc = "0: Off (Disabled)"] + OFF = 0, + #[doc = "1: Wake without timestamp"] + WAKE = 1, + #[doc = "2: Capture timestamp"] + CAPTURE = 2, + #[doc = "3: Compare IN0 to OUT"] + ACTL = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: IN0ACTSELECT_A) -> Self { + variant as _ + } +} +impl IN0ACT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> IN0ACTSELECT_A { + match self.bits { + 0 => IN0ACTSELECT_A::OFF, + 1 => IN0ACTSELECT_A::WAKE, + 2 => IN0ACTSELECT_A::CAPTURE, + 3 => IN0ACTSELECT_A::ACTL, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == IN0ACTSELECT_A::OFF + } + #[doc = "Checks if the value of the field is `WAKE`"] + #[inline(always)] + pub fn is_wake(&self) -> bool { + *self == IN0ACTSELECT_A::WAKE + } + #[doc = "Checks if the value of the field is `CAPTURE`"] + #[inline(always)] + pub fn is_capture(&self) -> bool { + *self == IN0ACTSELECT_A::CAPTURE + } + #[doc = "Checks if the value of the field is `ACTL`"] + #[inline(always)] + pub fn is_actl(&self) -> bool { + *self == IN0ACTSELECT_A::ACTL + } +} +#[doc = "Field `IN0ACT` writer - Tamper Input 0 Action"] +pub type IN0ACT_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, TAMPCTRL_SPEC, u8, IN0ACTSELECT_A, 2, O>; +impl<'a, const O: u8> IN0ACT_W<'a, O> { + #[doc = "Off (Disabled)"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(IN0ACTSELECT_A::OFF) + } + #[doc = "Wake without timestamp"] + #[inline(always)] + pub fn wake(self) -> &'a mut W { + self.variant(IN0ACTSELECT_A::WAKE) + } + #[doc = "Capture timestamp"] + #[inline(always)] + pub fn capture(self) -> &'a mut W { + self.variant(IN0ACTSELECT_A::CAPTURE) + } + #[doc = "Compare IN0 to OUT"] + #[inline(always)] + pub fn actl(self) -> &'a mut W { + self.variant(IN0ACTSELECT_A::ACTL) + } +} +#[doc = "Field `IN1ACT` reader - Tamper Input 1 Action"] +pub type IN1ACT_R = crate::FieldReader; +#[doc = "Tamper Input 1 Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum IN1ACTSELECT_A { + #[doc = "0: Off (Disabled)"] + OFF = 0, + #[doc = "1: Wake without timestamp"] + WAKE = 1, + #[doc = "2: Capture timestamp"] + CAPTURE = 2, + #[doc = "3: Compare IN1 to OUT"] + ACTL = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: IN1ACTSELECT_A) -> Self { + variant as _ + } +} +impl IN1ACT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> IN1ACTSELECT_A { + match self.bits { + 0 => IN1ACTSELECT_A::OFF, + 1 => IN1ACTSELECT_A::WAKE, + 2 => IN1ACTSELECT_A::CAPTURE, + 3 => IN1ACTSELECT_A::ACTL, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == IN1ACTSELECT_A::OFF + } + #[doc = "Checks if the value of the field is `WAKE`"] + #[inline(always)] + pub fn is_wake(&self) -> bool { + *self == IN1ACTSELECT_A::WAKE + } + #[doc = "Checks if the value of the field is `CAPTURE`"] + #[inline(always)] + pub fn is_capture(&self) -> bool { + *self == IN1ACTSELECT_A::CAPTURE + } + #[doc = "Checks if the value of the field is `ACTL`"] + #[inline(always)] + pub fn is_actl(&self) -> bool { + *self == IN1ACTSELECT_A::ACTL + } +} +#[doc = "Field `IN1ACT` writer - Tamper Input 1 Action"] +pub type IN1ACT_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, TAMPCTRL_SPEC, u8, IN1ACTSELECT_A, 2, O>; +impl<'a, const O: u8> IN1ACT_W<'a, O> { + #[doc = "Off (Disabled)"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(IN1ACTSELECT_A::OFF) + } + #[doc = "Wake without timestamp"] + #[inline(always)] + pub fn wake(self) -> &'a mut W { + self.variant(IN1ACTSELECT_A::WAKE) + } + #[doc = "Capture timestamp"] + #[inline(always)] + pub fn capture(self) -> &'a mut W { + self.variant(IN1ACTSELECT_A::CAPTURE) + } + #[doc = "Compare IN1 to OUT"] + #[inline(always)] + pub fn actl(self) -> &'a mut W { + self.variant(IN1ACTSELECT_A::ACTL) + } +} +#[doc = "Field `IN2ACT` reader - Tamper Input 2 Action"] +pub type IN2ACT_R = crate::FieldReader; +#[doc = "Tamper Input 2 Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum IN2ACTSELECT_A { + #[doc = "0: Off (Disabled)"] + OFF = 0, + #[doc = "1: Wake without timestamp"] + WAKE = 1, + #[doc = "2: Capture timestamp"] + CAPTURE = 2, + #[doc = "3: Compare IN2 to OUT"] + ACTL = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: IN2ACTSELECT_A) -> Self { + variant as _ + } +} +impl IN2ACT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> IN2ACTSELECT_A { + match self.bits { + 0 => IN2ACTSELECT_A::OFF, + 1 => IN2ACTSELECT_A::WAKE, + 2 => IN2ACTSELECT_A::CAPTURE, + 3 => IN2ACTSELECT_A::ACTL, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == IN2ACTSELECT_A::OFF + } + #[doc = "Checks if the value of the field is `WAKE`"] + #[inline(always)] + pub fn is_wake(&self) -> bool { + *self == IN2ACTSELECT_A::WAKE + } + #[doc = "Checks if the value of the field is `CAPTURE`"] + #[inline(always)] + pub fn is_capture(&self) -> bool { + *self == IN2ACTSELECT_A::CAPTURE + } + #[doc = "Checks if the value of the field is `ACTL`"] + #[inline(always)] + pub fn is_actl(&self) -> bool { + *self == IN2ACTSELECT_A::ACTL + } +} +#[doc = "Field `IN2ACT` writer - Tamper Input 2 Action"] +pub type IN2ACT_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, TAMPCTRL_SPEC, u8, IN2ACTSELECT_A, 2, O>; +impl<'a, const O: u8> IN2ACT_W<'a, O> { + #[doc = "Off (Disabled)"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(IN2ACTSELECT_A::OFF) + } + #[doc = "Wake without timestamp"] + #[inline(always)] + pub fn wake(self) -> &'a mut W { + self.variant(IN2ACTSELECT_A::WAKE) + } + #[doc = "Capture timestamp"] + #[inline(always)] + pub fn capture(self) -> &'a mut W { + self.variant(IN2ACTSELECT_A::CAPTURE) + } + #[doc = "Compare IN2 to OUT"] + #[inline(always)] + pub fn actl(self) -> &'a mut W { + self.variant(IN2ACTSELECT_A::ACTL) + } +} +#[doc = "Field `IN3ACT` reader - Tamper Input 3 Action"] +pub type IN3ACT_R = crate::FieldReader; +#[doc = "Tamper Input 3 Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum IN3ACTSELECT_A { + #[doc = "0: Off (Disabled)"] + OFF = 0, + #[doc = "1: Wake without timestamp"] + WAKE = 1, + #[doc = "2: Capture timestamp"] + CAPTURE = 2, + #[doc = "3: Compare IN3 to OUT"] + ACTL = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: IN3ACTSELECT_A) -> Self { + variant as _ + } +} +impl IN3ACT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> IN3ACTSELECT_A { + match self.bits { + 0 => IN3ACTSELECT_A::OFF, + 1 => IN3ACTSELECT_A::WAKE, + 2 => IN3ACTSELECT_A::CAPTURE, + 3 => IN3ACTSELECT_A::ACTL, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == IN3ACTSELECT_A::OFF + } + #[doc = "Checks if the value of the field is `WAKE`"] + #[inline(always)] + pub fn is_wake(&self) -> bool { + *self == IN3ACTSELECT_A::WAKE + } + #[doc = "Checks if the value of the field is `CAPTURE`"] + #[inline(always)] + pub fn is_capture(&self) -> bool { + *self == IN3ACTSELECT_A::CAPTURE + } + #[doc = "Checks if the value of the field is `ACTL`"] + #[inline(always)] + pub fn is_actl(&self) -> bool { + *self == IN3ACTSELECT_A::ACTL + } +} +#[doc = "Field `IN3ACT` writer - Tamper Input 3 Action"] +pub type IN3ACT_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, TAMPCTRL_SPEC, u8, IN3ACTSELECT_A, 2, O>; +impl<'a, const O: u8> IN3ACT_W<'a, O> { + #[doc = "Off (Disabled)"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(IN3ACTSELECT_A::OFF) + } + #[doc = "Wake without timestamp"] + #[inline(always)] + pub fn wake(self) -> &'a mut W { + self.variant(IN3ACTSELECT_A::WAKE) + } + #[doc = "Capture timestamp"] + #[inline(always)] + pub fn capture(self) -> &'a mut W { + self.variant(IN3ACTSELECT_A::CAPTURE) + } + #[doc = "Compare IN3 to OUT"] + #[inline(always)] + pub fn actl(self) -> &'a mut W { + self.variant(IN3ACTSELECT_A::ACTL) + } +} +#[doc = "Field `IN4ACT` reader - Tamper Input 4 Action"] +pub type IN4ACT_R = crate::FieldReader; +#[doc = "Tamper Input 4 Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum IN4ACTSELECT_A { + #[doc = "0: Off (Disabled)"] + OFF = 0, + #[doc = "1: Wake without timestamp"] + WAKE = 1, + #[doc = "2: Capture timestamp"] + CAPTURE = 2, + #[doc = "3: Compare IN4 to OUT"] + ACTL = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: IN4ACTSELECT_A) -> Self { + variant as _ + } +} +impl IN4ACT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> IN4ACTSELECT_A { + match self.bits { + 0 => IN4ACTSELECT_A::OFF, + 1 => IN4ACTSELECT_A::WAKE, + 2 => IN4ACTSELECT_A::CAPTURE, + 3 => IN4ACTSELECT_A::ACTL, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == IN4ACTSELECT_A::OFF + } + #[doc = "Checks if the value of the field is `WAKE`"] + #[inline(always)] + pub fn is_wake(&self) -> bool { + *self == IN4ACTSELECT_A::WAKE + } + #[doc = "Checks if the value of the field is `CAPTURE`"] + #[inline(always)] + pub fn is_capture(&self) -> bool { + *self == IN4ACTSELECT_A::CAPTURE + } + #[doc = "Checks if the value of the field is `ACTL`"] + #[inline(always)] + pub fn is_actl(&self) -> bool { + *self == IN4ACTSELECT_A::ACTL + } +} +#[doc = "Field `IN4ACT` writer - Tamper Input 4 Action"] +pub type IN4ACT_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, TAMPCTRL_SPEC, u8, IN4ACTSELECT_A, 2, O>; +impl<'a, const O: u8> IN4ACT_W<'a, O> { + #[doc = "Off (Disabled)"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(IN4ACTSELECT_A::OFF) + } + #[doc = "Wake without timestamp"] + #[inline(always)] + pub fn wake(self) -> &'a mut W { + self.variant(IN4ACTSELECT_A::WAKE) + } + #[doc = "Capture timestamp"] + #[inline(always)] + pub fn capture(self) -> &'a mut W { + self.variant(IN4ACTSELECT_A::CAPTURE) + } + #[doc = "Compare IN4 to OUT"] + #[inline(always)] + pub fn actl(self) -> &'a mut W { + self.variant(IN4ACTSELECT_A::ACTL) + } +} +#[doc = "Field `TAMLVL0` reader - Tamper Level Select 0"] +pub type TAMLVL0_R = crate::BitReader; +#[doc = "Field `TAMLVL0` writer - Tamper Level Select 0"] +pub type TAMLVL0_W<'a, const O: u8> = crate::BitWriter<'a, u32, TAMPCTRL_SPEC, bool, O>; +#[doc = "Field `TAMLVL1` reader - Tamper Level Select 1"] +pub type TAMLVL1_R = crate::BitReader; +#[doc = "Field `TAMLVL1` writer - Tamper Level Select 1"] +pub type TAMLVL1_W<'a, const O: u8> = crate::BitWriter<'a, u32, TAMPCTRL_SPEC, bool, O>; +#[doc = "Field `TAMLVL2` reader - Tamper Level Select 2"] +pub type TAMLVL2_R = crate::BitReader; +#[doc = "Field `TAMLVL2` writer - Tamper Level Select 2"] +pub type TAMLVL2_W<'a, const O: u8> = crate::BitWriter<'a, u32, TAMPCTRL_SPEC, bool, O>; +#[doc = "Field `TAMLVL3` reader - Tamper Level Select 3"] +pub type TAMLVL3_R = crate::BitReader; +#[doc = "Field `TAMLVL3` writer - Tamper Level Select 3"] +pub type TAMLVL3_W<'a, const O: u8> = crate::BitWriter<'a, u32, TAMPCTRL_SPEC, bool, O>; +#[doc = "Field `TAMLVL4` reader - Tamper Level Select 4"] +pub type TAMLVL4_R = crate::BitReader; +#[doc = "Field `TAMLVL4` writer - Tamper Level Select 4"] +pub type TAMLVL4_W<'a, const O: u8> = crate::BitWriter<'a, u32, TAMPCTRL_SPEC, bool, O>; +#[doc = "Field `DEBNC0` reader - Debouncer Enable 0"] +pub type DEBNC0_R = crate::BitReader; +#[doc = "Field `DEBNC0` writer - Debouncer Enable 0"] +pub type DEBNC0_W<'a, const O: u8> = crate::BitWriter<'a, u32, TAMPCTRL_SPEC, bool, O>; +#[doc = "Field `DEBNC1` reader - Debouncer Enable 1"] +pub type DEBNC1_R = crate::BitReader; +#[doc = "Field `DEBNC1` writer - Debouncer Enable 1"] +pub type DEBNC1_W<'a, const O: u8> = crate::BitWriter<'a, u32, TAMPCTRL_SPEC, bool, O>; +#[doc = "Field `DEBNC2` reader - Debouncer Enable 2"] +pub type DEBNC2_R = crate::BitReader; +#[doc = "Field `DEBNC2` writer - Debouncer Enable 2"] +pub type DEBNC2_W<'a, const O: u8> = crate::BitWriter<'a, u32, TAMPCTRL_SPEC, bool, O>; +#[doc = "Field `DEBNC3` reader - Debouncer Enable 3"] +pub type DEBNC3_R = crate::BitReader; +#[doc = "Field `DEBNC3` writer - Debouncer Enable 3"] +pub type DEBNC3_W<'a, const O: u8> = crate::BitWriter<'a, u32, TAMPCTRL_SPEC, bool, O>; +#[doc = "Field `DEBNC4` reader - Debouncer Enable 4"] +pub type DEBNC4_R = crate::BitReader; +#[doc = "Field `DEBNC4` writer - Debouncer Enable 4"] +pub type DEBNC4_W<'a, const O: u8> = crate::BitWriter<'a, u32, TAMPCTRL_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:1 - Tamper Input 0 Action"] + #[inline(always)] + pub fn in0act(&self) -> IN0ACT_R { + IN0ACT_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Tamper Input 1 Action"] + #[inline(always)] + pub fn in1act(&self) -> IN1ACT_R { + IN1ACT_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Tamper Input 2 Action"] + #[inline(always)] + pub fn in2act(&self) -> IN2ACT_R { + IN2ACT_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - Tamper Input 3 Action"] + #[inline(always)] + pub fn in3act(&self) -> IN3ACT_R { + IN3ACT_R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - Tamper Input 4 Action"] + #[inline(always)] + pub fn in4act(&self) -> IN4ACT_R { + IN4ACT_R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bit 16 - Tamper Level Select 0"] + #[inline(always)] + pub fn tamlvl0(&self) -> TAMLVL0_R { + TAMLVL0_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Tamper Level Select 1"] + #[inline(always)] + pub fn tamlvl1(&self) -> TAMLVL1_R { + TAMLVL1_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Tamper Level Select 2"] + #[inline(always)] + pub fn tamlvl2(&self) -> TAMLVL2_R { + TAMLVL2_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Tamper Level Select 3"] + #[inline(always)] + pub fn tamlvl3(&self) -> TAMLVL3_R { + TAMLVL3_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Tamper Level Select 4"] + #[inline(always)] + pub fn tamlvl4(&self) -> TAMLVL4_R { + TAMLVL4_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 24 - Debouncer Enable 0"] + #[inline(always)] + pub fn debnc0(&self) -> DEBNC0_R { + DEBNC0_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Debouncer Enable 1"] + #[inline(always)] + pub fn debnc1(&self) -> DEBNC1_R { + DEBNC1_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Debouncer Enable 2"] + #[inline(always)] + pub fn debnc2(&self) -> DEBNC2_R { + DEBNC2_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Debouncer Enable 3"] + #[inline(always)] + pub fn debnc3(&self) -> DEBNC3_R { + DEBNC3_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Debouncer Enable 4"] + #[inline(always)] + pub fn debnc4(&self) -> DEBNC4_R { + DEBNC4_R::new(((self.bits >> 28) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:1 - Tamper Input 0 Action"] + #[inline(always)] + #[must_use] + pub fn in0act(&mut self) -> IN0ACT_W<0> { + IN0ACT_W::new(self) + } + #[doc = "Bits 2:3 - Tamper Input 1 Action"] + #[inline(always)] + #[must_use] + pub fn in1act(&mut self) -> IN1ACT_W<2> { + IN1ACT_W::new(self) + } + #[doc = "Bits 4:5 - Tamper Input 2 Action"] + #[inline(always)] + #[must_use] + pub fn in2act(&mut self) -> IN2ACT_W<4> { + IN2ACT_W::new(self) + } + #[doc = "Bits 6:7 - Tamper Input 3 Action"] + #[inline(always)] + #[must_use] + pub fn in3act(&mut self) -> IN3ACT_W<6> { + IN3ACT_W::new(self) + } + #[doc = "Bits 8:9 - Tamper Input 4 Action"] + #[inline(always)] + #[must_use] + pub fn in4act(&mut self) -> IN4ACT_W<8> { + IN4ACT_W::new(self) + } + #[doc = "Bit 16 - Tamper Level Select 0"] + #[inline(always)] + #[must_use] + pub fn tamlvl0(&mut self) -> TAMLVL0_W<16> { + TAMLVL0_W::new(self) + } + #[doc = "Bit 17 - Tamper Level Select 1"] + #[inline(always)] + #[must_use] + pub fn tamlvl1(&mut self) -> TAMLVL1_W<17> { + TAMLVL1_W::new(self) + } + #[doc = "Bit 18 - Tamper Level Select 2"] + #[inline(always)] + #[must_use] + pub fn tamlvl2(&mut self) -> TAMLVL2_W<18> { + TAMLVL2_W::new(self) + } + #[doc = "Bit 19 - Tamper Level Select 3"] + #[inline(always)] + #[must_use] + pub fn tamlvl3(&mut self) -> TAMLVL3_W<19> { + TAMLVL3_W::new(self) + } + #[doc = "Bit 20 - Tamper Level Select 4"] + #[inline(always)] + #[must_use] + pub fn tamlvl4(&mut self) -> TAMLVL4_W<20> { + TAMLVL4_W::new(self) + } + #[doc = "Bit 24 - Debouncer Enable 0"] + #[inline(always)] + #[must_use] + pub fn debnc0(&mut self) -> DEBNC0_W<24> { + DEBNC0_W::new(self) + } + #[doc = "Bit 25 - Debouncer Enable 1"] + #[inline(always)] + #[must_use] + pub fn debnc1(&mut self) -> DEBNC1_W<25> { + DEBNC1_W::new(self) + } + #[doc = "Bit 26 - Debouncer Enable 2"] + #[inline(always)] + #[must_use] + pub fn debnc2(&mut self) -> DEBNC2_W<26> { + DEBNC2_W::new(self) + } + #[doc = "Bit 27 - Debouncer Enable 3"] + #[inline(always)] + #[must_use] + pub fn debnc3(&mut self) -> DEBNC3_W<27> { + DEBNC3_W::new(self) + } + #[doc = "Bit 28 - Debouncer Enable 4"] + #[inline(always)] + #[must_use] + pub fn debnc4(&mut self) -> DEBNC4_W<28> { + DEBNC4_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Tamper Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tampctrl](index.html) module"] +pub struct TAMPCTRL_SPEC; +impl crate::RegisterSpec for TAMPCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tampctrl::R](R) reader structure"] +impl crate::Readable for TAMPCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [tampctrl::W](W) writer structure"] +impl crate::Writable for TAMPCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TAMPCTRL to value 0"] +impl crate::Resettable for TAMPCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/rtc/mode1/tampid.rs b/pac/atsaml22j/src/rtc/mode1/tampid.rs new file mode 100644 index 000000000000..3677f47b1990 --- /dev/null +++ b/pac/atsaml22j/src/rtc/mode1/tampid.rs @@ -0,0 +1,155 @@ +#[doc = "Register `TAMPID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TAMPID` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TAMPID0` reader - Tamper Input 0 Detected"] +pub type TAMPID0_R = crate::BitReader; +#[doc = "Field `TAMPID0` writer - Tamper Input 0 Detected"] +pub type TAMPID0_W<'a, const O: u8> = crate::BitWriter<'a, u32, TAMPID_SPEC, bool, O>; +#[doc = "Field `TAMPID1` reader - Tamper Input 1 Detected"] +pub type TAMPID1_R = crate::BitReader; +#[doc = "Field `TAMPID1` writer - Tamper Input 1 Detected"] +pub type TAMPID1_W<'a, const O: u8> = crate::BitWriter<'a, u32, TAMPID_SPEC, bool, O>; +#[doc = "Field `TAMPID2` reader - Tamper Input 2 Detected"] +pub type TAMPID2_R = crate::BitReader; +#[doc = "Field `TAMPID2` writer - Tamper Input 2 Detected"] +pub type TAMPID2_W<'a, const O: u8> = crate::BitWriter<'a, u32, TAMPID_SPEC, bool, O>; +#[doc = "Field `TAMPID3` reader - Tamper Input 3 Detected"] +pub type TAMPID3_R = crate::BitReader; +#[doc = "Field `TAMPID3` writer - Tamper Input 3 Detected"] +pub type TAMPID3_W<'a, const O: u8> = crate::BitWriter<'a, u32, TAMPID_SPEC, bool, O>; +#[doc = "Field `TAMPID4` reader - Tamper Input 4 Detected"] +pub type TAMPID4_R = crate::BitReader; +#[doc = "Field `TAMPID4` writer - Tamper Input 4 Detected"] +pub type TAMPID4_W<'a, const O: u8> = crate::BitWriter<'a, u32, TAMPID_SPEC, bool, O>; +#[doc = "Field `TAMPEVT` reader - Tamper Event Detected"] +pub type TAMPEVT_R = crate::BitReader; +#[doc = "Field `TAMPEVT` writer - Tamper Event Detected"] +pub type TAMPEVT_W<'a, const O: u8> = crate::BitWriter<'a, u32, TAMPID_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Tamper Input 0 Detected"] + #[inline(always)] + pub fn tampid0(&self) -> TAMPID0_R { + TAMPID0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Tamper Input 1 Detected"] + #[inline(always)] + pub fn tampid1(&self) -> TAMPID1_R { + TAMPID1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Tamper Input 2 Detected"] + #[inline(always)] + pub fn tampid2(&self) -> TAMPID2_R { + TAMPID2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Tamper Input 3 Detected"] + #[inline(always)] + pub fn tampid3(&self) -> TAMPID3_R { + TAMPID3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Tamper Input 4 Detected"] + #[inline(always)] + pub fn tampid4(&self) -> TAMPID4_R { + TAMPID4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 31 - Tamper Event Detected"] + #[inline(always)] + pub fn tampevt(&self) -> TAMPEVT_R { + TAMPEVT_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Tamper Input 0 Detected"] + #[inline(always)] + #[must_use] + pub fn tampid0(&mut self) -> TAMPID0_W<0> { + TAMPID0_W::new(self) + } + #[doc = "Bit 1 - Tamper Input 1 Detected"] + #[inline(always)] + #[must_use] + pub fn tampid1(&mut self) -> TAMPID1_W<1> { + TAMPID1_W::new(self) + } + #[doc = "Bit 2 - Tamper Input 2 Detected"] + #[inline(always)] + #[must_use] + pub fn tampid2(&mut self) -> TAMPID2_W<2> { + TAMPID2_W::new(self) + } + #[doc = "Bit 3 - Tamper Input 3 Detected"] + #[inline(always)] + #[must_use] + pub fn tampid3(&mut self) -> TAMPID3_W<3> { + TAMPID3_W::new(self) + } + #[doc = "Bit 4 - Tamper Input 4 Detected"] + #[inline(always)] + #[must_use] + pub fn tampid4(&mut self) -> TAMPID4_W<4> { + TAMPID4_W::new(self) + } + #[doc = "Bit 31 - Tamper Event Detected"] + #[inline(always)] + #[must_use] + pub fn tampevt(&mut self) -> TAMPEVT_W<31> { + TAMPEVT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Tamper ID\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tampid](index.html) module"] +pub struct TAMPID_SPEC; +impl crate::RegisterSpec for TAMPID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tampid::R](R) reader structure"] +impl crate::Readable for TAMPID_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [tampid::W](W) writer structure"] +impl crate::Writable for TAMPID_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TAMPID to value 0"] +impl crate::Resettable for TAMPID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/rtc/mode1/timestamp.rs b/pac/atsaml22j/src/rtc/mode1/timestamp.rs new file mode 100644 index 000000000000..531f7d0c6ca6 --- /dev/null +++ b/pac/atsaml22j/src/rtc/mode1/timestamp.rs @@ -0,0 +1,37 @@ +#[doc = "Register `TIMESTAMP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `COUNT` reader - Count Timestamp Value"] +pub type COUNT_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:15 - Count Timestamp Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits & 0xffff) as u16) + } +} +#[doc = "MODE1 Timestamp\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [timestamp](index.html) module"] +pub struct TIMESTAMP_SPEC; +impl crate::RegisterSpec for TIMESTAMP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [timestamp::R](R) reader structure"] +impl crate::Readable for TIMESTAMP_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets TIMESTAMP to value 0"] +impl crate::Resettable for TIMESTAMP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/rtc/mode2.rs b/pac/atsaml22j/src/rtc/mode2.rs new file mode 100644 index 000000000000..4c9dcf1382d4 --- /dev/null +++ b/pac/atsaml22j/src/rtc/mode2.rs @@ -0,0 +1,112 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct MODE2 { + #[doc = "0x00 - MODE2 Control A"] + pub ctrla: CTRLA, + #[doc = "0x02 - MODE2 Control B"] + pub ctrlb: CTRLB, + #[doc = "0x04 - MODE2 Event Control"] + pub evctrl: EVCTRL, + #[doc = "0x08 - MODE2 Interrupt Enable Clear"] + pub intenclr: INTENCLR, + #[doc = "0x0a - MODE2 Interrupt Enable Set"] + pub intenset: INTENSET, + #[doc = "0x0c - MODE2 Interrupt Flag Status and Clear"] + pub intflag: INTFLAG, + #[doc = "0x0e - Debug Control"] + pub dbgctrl: DBGCTRL, + _reserved7: [u8; 0x01], + #[doc = "0x10 - MODE2 Synchronization Busy Status"] + pub syncbusy: SYNCBUSY, + #[doc = "0x14 - Frequency Correction"] + pub freqcorr: FREQCORR, + _reserved9: [u8; 0x03], + #[doc = "0x18 - MODE2 Clock Value"] + pub clock: CLOCK, + _reserved10: [u8; 0x04], + #[doc = "0x20 - MODE2 Alarm n Value"] + pub alarm: [ALARM; 1], + #[doc = "0x24 - MODE2 Alarm n Mask"] + pub mask: [MASK; 1], + _reserved12: [u8; 0x1b], + #[doc = "0x40..0x48 - General Purpose"] + pub gp: [GP; 2], + _reserved13: [u8; 0x18], + #[doc = "0x60 - Tamper Control"] + pub tampctrl: TAMPCTRL, + #[doc = "0x64 - MODE2 Timestamp"] + pub timestamp: TIMESTAMP, + #[doc = "0x68 - Tamper ID"] + pub tampid: TAMPID, + _reserved16: [u8; 0x14], + #[doc = "0x80..0xa0 - Backup"] + pub bkup: [BKUP; 8], +} +#[doc = "CTRLA (rw) register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "MODE2 Control A"] +pub mod ctrla; +#[doc = "CTRLB (rw) register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "MODE2 Control B"] +pub mod ctrlb; +#[doc = "EVCTRL (rw) register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "MODE2 Event Control"] +pub mod evctrl; +#[doc = "INTENCLR (rw) register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "MODE2 Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET (rw) register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "MODE2 Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG (rw) register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "MODE2 Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "DBGCTRL (rw) register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY (r) register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "MODE2 Synchronization Busy Status"] +pub mod syncbusy; +#[doc = "FREQCORR (rw) register accessor: an alias for `Reg`"] +pub type FREQCORR = crate::Reg; +#[doc = "Frequency Correction"] +pub mod freqcorr; +#[doc = "CLOCK (rw) register accessor: an alias for `Reg`"] +pub type CLOCK = crate::Reg; +#[doc = "MODE2 Clock Value"] +pub mod clock; +#[doc = "ALARM (rw) register accessor: an alias for `Reg`"] +pub type ALARM = crate::Reg; +#[doc = "MODE2 Alarm n Value"] +pub mod alarm; +#[doc = "MASK (rw) register accessor: an alias for `Reg`"] +pub type MASK = crate::Reg; +#[doc = "MODE2 Alarm n Mask"] +pub mod mask; +#[doc = "GP (rw) register accessor: an alias for `Reg`"] +pub type GP = crate::Reg; +#[doc = "General Purpose"] +pub mod gp; +#[doc = "TAMPCTRL (rw) register accessor: an alias for `Reg`"] +pub type TAMPCTRL = crate::Reg; +#[doc = "Tamper Control"] +pub mod tampctrl; +#[doc = "TIMESTAMP (r) register accessor: an alias for `Reg`"] +pub type TIMESTAMP = crate::Reg; +#[doc = "MODE2 Timestamp"] +pub mod timestamp; +#[doc = "TAMPID (rw) register accessor: an alias for `Reg`"] +pub type TAMPID = crate::Reg; +#[doc = "Tamper ID"] +pub mod tampid; +#[doc = "BKUP (rw) register accessor: an alias for `Reg`"] +pub type BKUP = crate::Reg; +#[doc = "Backup"] +pub mod bkup; diff --git a/pac/atsaml22j/src/rtc/mode2/alarm.rs b/pac/atsaml22j/src/rtc/mode2/alarm.rs new file mode 100644 index 000000000000..d0af1bf502e6 --- /dev/null +++ b/pac/atsaml22j/src/rtc/mode2/alarm.rs @@ -0,0 +1,203 @@ +#[doc = "Register `ALARM%s` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ALARM%s` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SECOND` reader - Second"] +pub type SECOND_R = crate::FieldReader; +#[doc = "Field `SECOND` writer - Second"] +pub type SECOND_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ALARM_SPEC, u8, u8, 6, O>; +#[doc = "Field `MINUTE` reader - Minute"] +pub type MINUTE_R = crate::FieldReader; +#[doc = "Field `MINUTE` writer - Minute"] +pub type MINUTE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ALARM_SPEC, u8, u8, 6, O>; +#[doc = "Field `HOUR` reader - Hour"] +pub type HOUR_R = crate::FieldReader; +#[doc = "Hour\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum HOURSELECT_A { + #[doc = "0: Morning hour"] + AM = 0, + #[doc = "16: Afternoon hour"] + PM = 16, +} +impl From for u8 { + #[inline(always)] + fn from(variant: HOURSELECT_A) -> Self { + variant as _ + } +} +impl HOUR_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(HOURSELECT_A::AM), + 16 => Some(HOURSELECT_A::PM), + _ => None, + } + } + #[doc = "Checks if the value of the field is `AM`"] + #[inline(always)] + pub fn is_am(&self) -> bool { + *self == HOURSELECT_A::AM + } + #[doc = "Checks if the value of the field is `PM`"] + #[inline(always)] + pub fn is_pm(&self) -> bool { + *self == HOURSELECT_A::PM + } +} +#[doc = "Field `HOUR` writer - Hour"] +pub type HOUR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ALARM_SPEC, u8, HOURSELECT_A, 5, O>; +impl<'a, const O: u8> HOUR_W<'a, O> { + #[doc = "Morning hour"] + #[inline(always)] + pub fn am(self) -> &'a mut W { + self.variant(HOURSELECT_A::AM) + } + #[doc = "Afternoon hour"] + #[inline(always)] + pub fn pm(self) -> &'a mut W { + self.variant(HOURSELECT_A::PM) + } +} +#[doc = "Field `DAY` reader - Day"] +pub type DAY_R = crate::FieldReader; +#[doc = "Field `DAY` writer - Day"] +pub type DAY_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ALARM_SPEC, u8, u8, 5, O>; +#[doc = "Field `MONTH` reader - Month"] +pub type MONTH_R = crate::FieldReader; +#[doc = "Field `MONTH` writer - Month"] +pub type MONTH_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ALARM_SPEC, u8, u8, 4, O>; +#[doc = "Field `YEAR` reader - Year"] +pub type YEAR_R = crate::FieldReader; +#[doc = "Field `YEAR` writer - Year"] +pub type YEAR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ALARM_SPEC, u8, u8, 6, O>; +impl R { + #[doc = "Bits 0:5 - Second"] + #[inline(always)] + pub fn second(&self) -> SECOND_R { + SECOND_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:11 - Minute"] + #[inline(always)] + pub fn minute(&self) -> MINUTE_R { + MINUTE_R::new(((self.bits >> 6) & 0x3f) as u8) + } + #[doc = "Bits 12:16 - Hour"] + #[inline(always)] + pub fn hour(&self) -> HOUR_R { + HOUR_R::new(((self.bits >> 12) & 0x1f) as u8) + } + #[doc = "Bits 17:21 - Day"] + #[inline(always)] + pub fn day(&self) -> DAY_R { + DAY_R::new(((self.bits >> 17) & 0x1f) as u8) + } + #[doc = "Bits 22:25 - Month"] + #[inline(always)] + pub fn month(&self) -> MONTH_R { + MONTH_R::new(((self.bits >> 22) & 0x0f) as u8) + } + #[doc = "Bits 26:31 - Year"] + #[inline(always)] + pub fn year(&self) -> YEAR_R { + YEAR_R::new(((self.bits >> 26) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Second"] + #[inline(always)] + #[must_use] + pub fn second(&mut self) -> SECOND_W<0> { + SECOND_W::new(self) + } + #[doc = "Bits 6:11 - Minute"] + #[inline(always)] + #[must_use] + pub fn minute(&mut self) -> MINUTE_W<6> { + MINUTE_W::new(self) + } + #[doc = "Bits 12:16 - Hour"] + #[inline(always)] + #[must_use] + pub fn hour(&mut self) -> HOUR_W<12> { + HOUR_W::new(self) + } + #[doc = "Bits 17:21 - Day"] + #[inline(always)] + #[must_use] + pub fn day(&mut self) -> DAY_W<17> { + DAY_W::new(self) + } + #[doc = "Bits 22:25 - Month"] + #[inline(always)] + #[must_use] + pub fn month(&mut self) -> MONTH_W<22> { + MONTH_W::new(self) + } + #[doc = "Bits 26:31 - Year"] + #[inline(always)] + #[must_use] + pub fn year(&mut self) -> YEAR_W<26> { + YEAR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Alarm n Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [alarm](index.html) module"] +pub struct ALARM_SPEC; +impl crate::RegisterSpec for ALARM_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [alarm::R](R) reader structure"] +impl crate::Readable for ALARM_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [alarm::W](W) writer structure"] +impl crate::Writable for ALARM_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ALARM%s to value 0"] +impl crate::Resettable for ALARM_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/rtc/mode2/bkup.rs b/pac/atsaml22j/src/rtc/mode2/bkup.rs new file mode 100644 index 000000000000..0d0a909e0bec --- /dev/null +++ b/pac/atsaml22j/src/rtc/mode2/bkup.rs @@ -0,0 +1,80 @@ +#[doc = "Register `BKUP%s` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BKUP%s` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BKUP` reader - Backup"] +pub type BKUP_R = crate::FieldReader; +#[doc = "Field `BKUP` writer - Backup"] +pub type BKUP_W<'a, const O: u8> = crate::FieldWriter<'a, u32, BKUP_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - Backup"] + #[inline(always)] + pub fn bkup(&self) -> BKUP_R { + BKUP_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Backup"] + #[inline(always)] + #[must_use] + pub fn bkup(&mut self) -> BKUP_W<0> { + BKUP_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Backup\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bkup](index.html) module"] +pub struct BKUP_SPEC; +impl crate::RegisterSpec for BKUP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [bkup::R](R) reader structure"] +impl crate::Readable for BKUP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [bkup::W](W) writer structure"] +impl crate::Writable for BKUP_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BKUP%s to value 0"] +impl crate::Resettable for BKUP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/rtc/mode2/clock.rs b/pac/atsaml22j/src/rtc/mode2/clock.rs new file mode 100644 index 000000000000..1f832f91e7f0 --- /dev/null +++ b/pac/atsaml22j/src/rtc/mode2/clock.rs @@ -0,0 +1,203 @@ +#[doc = "Register `CLOCK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CLOCK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SECOND` reader - Second"] +pub type SECOND_R = crate::FieldReader; +#[doc = "Field `SECOND` writer - Second"] +pub type SECOND_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLOCK_SPEC, u8, u8, 6, O>; +#[doc = "Field `MINUTE` reader - Minute"] +pub type MINUTE_R = crate::FieldReader; +#[doc = "Field `MINUTE` writer - Minute"] +pub type MINUTE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLOCK_SPEC, u8, u8, 6, O>; +#[doc = "Field `HOUR` reader - Hour"] +pub type HOUR_R = crate::FieldReader; +#[doc = "Hour\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum HOURSELECT_A { + #[doc = "0: AM when CLKREP in 12-hour"] + AM = 0, + #[doc = "16: PM when CLKREP in 12-hour"] + PM = 16, +} +impl From for u8 { + #[inline(always)] + fn from(variant: HOURSELECT_A) -> Self { + variant as _ + } +} +impl HOUR_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(HOURSELECT_A::AM), + 16 => Some(HOURSELECT_A::PM), + _ => None, + } + } + #[doc = "Checks if the value of the field is `AM`"] + #[inline(always)] + pub fn is_am(&self) -> bool { + *self == HOURSELECT_A::AM + } + #[doc = "Checks if the value of the field is `PM`"] + #[inline(always)] + pub fn is_pm(&self) -> bool { + *self == HOURSELECT_A::PM + } +} +#[doc = "Field `HOUR` writer - Hour"] +pub type HOUR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLOCK_SPEC, u8, HOURSELECT_A, 5, O>; +impl<'a, const O: u8> HOUR_W<'a, O> { + #[doc = "AM when CLKREP in 12-hour"] + #[inline(always)] + pub fn am(self) -> &'a mut W { + self.variant(HOURSELECT_A::AM) + } + #[doc = "PM when CLKREP in 12-hour"] + #[inline(always)] + pub fn pm(self) -> &'a mut W { + self.variant(HOURSELECT_A::PM) + } +} +#[doc = "Field `DAY` reader - Day"] +pub type DAY_R = crate::FieldReader; +#[doc = "Field `DAY` writer - Day"] +pub type DAY_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLOCK_SPEC, u8, u8, 5, O>; +#[doc = "Field `MONTH` reader - Month"] +pub type MONTH_R = crate::FieldReader; +#[doc = "Field `MONTH` writer - Month"] +pub type MONTH_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLOCK_SPEC, u8, u8, 4, O>; +#[doc = "Field `YEAR` reader - Year"] +pub type YEAR_R = crate::FieldReader; +#[doc = "Field `YEAR` writer - Year"] +pub type YEAR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CLOCK_SPEC, u8, u8, 6, O>; +impl R { + #[doc = "Bits 0:5 - Second"] + #[inline(always)] + pub fn second(&self) -> SECOND_R { + SECOND_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:11 - Minute"] + #[inline(always)] + pub fn minute(&self) -> MINUTE_R { + MINUTE_R::new(((self.bits >> 6) & 0x3f) as u8) + } + #[doc = "Bits 12:16 - Hour"] + #[inline(always)] + pub fn hour(&self) -> HOUR_R { + HOUR_R::new(((self.bits >> 12) & 0x1f) as u8) + } + #[doc = "Bits 17:21 - Day"] + #[inline(always)] + pub fn day(&self) -> DAY_R { + DAY_R::new(((self.bits >> 17) & 0x1f) as u8) + } + #[doc = "Bits 22:25 - Month"] + #[inline(always)] + pub fn month(&self) -> MONTH_R { + MONTH_R::new(((self.bits >> 22) & 0x0f) as u8) + } + #[doc = "Bits 26:31 - Year"] + #[inline(always)] + pub fn year(&self) -> YEAR_R { + YEAR_R::new(((self.bits >> 26) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - Second"] + #[inline(always)] + #[must_use] + pub fn second(&mut self) -> SECOND_W<0> { + SECOND_W::new(self) + } + #[doc = "Bits 6:11 - Minute"] + #[inline(always)] + #[must_use] + pub fn minute(&mut self) -> MINUTE_W<6> { + MINUTE_W::new(self) + } + #[doc = "Bits 12:16 - Hour"] + #[inline(always)] + #[must_use] + pub fn hour(&mut self) -> HOUR_W<12> { + HOUR_W::new(self) + } + #[doc = "Bits 17:21 - Day"] + #[inline(always)] + #[must_use] + pub fn day(&mut self) -> DAY_W<17> { + DAY_W::new(self) + } + #[doc = "Bits 22:25 - Month"] + #[inline(always)] + #[must_use] + pub fn month(&mut self) -> MONTH_W<22> { + MONTH_W::new(self) + } + #[doc = "Bits 26:31 - Year"] + #[inline(always)] + #[must_use] + pub fn year(&mut self) -> YEAR_W<26> { + YEAR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Clock Value\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clock](index.html) module"] +pub struct CLOCK_SPEC; +impl crate::RegisterSpec for CLOCK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [clock::R](R) reader structure"] +impl crate::Readable for CLOCK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [clock::W](W) writer structure"] +impl crate::Writable for CLOCK_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CLOCK to value 0"] +impl crate::Resettable for CLOCK_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/rtc/mode2/ctrla.rs b/pac/atsaml22j/src/rtc/mode2/ctrla.rs new file mode 100644 index 000000000000..610b748fe965 --- /dev/null +++ b/pac/atsaml22j/src/rtc/mode2/ctrla.rs @@ -0,0 +1,433 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub type SWRST_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRLA_SPEC, bool, O>; +#[doc = "Field `ENABLE` reader - Enable"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - Enable"] +pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRLA_SPEC, bool, O>; +#[doc = "Field `MODE` reader - Operating Mode"] +pub type MODE_R = crate::FieldReader; +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum MODESELECT_A { + #[doc = "0: Mode 0: 32-bit Counter"] + COUNT32 = 0, + #[doc = "1: Mode 1: 16-bit Counter"] + COUNT16 = 1, + #[doc = "2: Mode 2: Clock/Calendar"] + CLOCK = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODESELECT_A) -> Self { + variant as _ + } +} +impl MODE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODESELECT_A::COUNT32), + 1 => Some(MODESELECT_A::COUNT16), + 2 => Some(MODESELECT_A::CLOCK), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + *self == MODESELECT_A::COUNT32 + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + *self == MODESELECT_A::COUNT16 + } + #[doc = "Checks if the value of the field is `CLOCK`"] + #[inline(always)] + pub fn is_clock(&self) -> bool { + *self == MODESELECT_A::CLOCK + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub type MODE_W<'a, const O: u8> = crate::FieldWriter<'a, u16, CTRLA_SPEC, u8, MODESELECT_A, 2, O>; +impl<'a, const O: u8> MODE_W<'a, O> { + #[doc = "Mode 0: 32-bit Counter"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODESELECT_A::COUNT32) + } + #[doc = "Mode 1: 16-bit Counter"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODESELECT_A::COUNT16) + } + #[doc = "Mode 2: Clock/Calendar"] + #[inline(always)] + pub fn clock(self) -> &'a mut W { + self.variant(MODESELECT_A::CLOCK) + } +} +#[doc = "Field `CLKREP` reader - Clock Representation"] +pub type CLKREP_R = crate::BitReader; +#[doc = "Field `CLKREP` writer - Clock Representation"] +pub type CLKREP_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRLA_SPEC, bool, O>; +#[doc = "Field `MATCHCLR` reader - Clear on Match"] +pub type MATCHCLR_R = crate::BitReader; +#[doc = "Field `MATCHCLR` writer - Clear on Match"] +pub type MATCHCLR_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRLA_SPEC, bool, O>; +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub type PRESCALER_R = crate::FieldReader; +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum PRESCALERSELECT_A { + #[doc = "0: CLK_RTC_CNT = GCLK_RTC/1"] + OFF = 0, + #[doc = "1: CLK_RTC_CNT = GCLK_RTC/1"] + DIV1 = 1, + #[doc = "2: CLK_RTC_CNT = GCLK_RTC/2"] + DIV2 = 2, + #[doc = "3: CLK_RTC_CNT = GCLK_RTC/4"] + DIV4 = 3, + #[doc = "4: CLK_RTC_CNT = GCLK_RTC/8"] + DIV8 = 4, + #[doc = "5: CLK_RTC_CNT = GCLK_RTC/16"] + DIV16 = 5, + #[doc = "6: CLK_RTC_CNT = GCLK_RTC/32"] + DIV32 = 6, + #[doc = "7: CLK_RTC_CNT = GCLK_RTC/64"] + DIV64 = 7, + #[doc = "8: CLK_RTC_CNT = GCLK_RTC/128"] + DIV128 = 8, + #[doc = "9: CLK_RTC_CNT = GCLK_RTC/256"] + DIV256 = 9, + #[doc = "10: CLK_RTC_CNT = GCLK_RTC/512"] + DIV512 = 10, + #[doc = "11: CLK_RTC_CNT = GCLK_RTC/1024"] + DIV1024 = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALERSELECT_A) -> Self { + variant as _ + } +} +impl PRESCALER_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCALERSELECT_A::OFF), + 1 => Some(PRESCALERSELECT_A::DIV1), + 2 => Some(PRESCALERSELECT_A::DIV2), + 3 => Some(PRESCALERSELECT_A::DIV4), + 4 => Some(PRESCALERSELECT_A::DIV8), + 5 => Some(PRESCALERSELECT_A::DIV16), + 6 => Some(PRESCALERSELECT_A::DIV32), + 7 => Some(PRESCALERSELECT_A::DIV64), + 8 => Some(PRESCALERSELECT_A::DIV128), + 9 => Some(PRESCALERSELECT_A::DIV256), + 10 => Some(PRESCALERSELECT_A::DIV512), + 11 => Some(PRESCALERSELECT_A::DIV1024), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == PRESCALERSELECT_A::OFF + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + *self == PRESCALERSELECT_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + *self == PRESCALERSELECT_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + *self == PRESCALERSELECT_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + *self == PRESCALERSELECT_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + *self == PRESCALERSELECT_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + *self == PRESCALERSELECT_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + *self == PRESCALERSELECT_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + *self == PRESCALERSELECT_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + *self == PRESCALERSELECT_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV512`"] + #[inline(always)] + pub fn is_div512(&self) -> bool { + *self == PRESCALERSELECT_A::DIV512 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + *self == PRESCALERSELECT_A::DIV1024 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub type PRESCALER_W<'a, const O: u8> = + crate::FieldWriter<'a, u16, CTRLA_SPEC, u8, PRESCALERSELECT_A, 4, O>; +impl<'a, const O: u8> PRESCALER_W<'a, O> { + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::OFF) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV1) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV2) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV4) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV8) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV16) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV32) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV64) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV128) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV256) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/512"] + #[inline(always)] + pub fn div512(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV512) + } + #[doc = "CLK_RTC_CNT = GCLK_RTC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV1024) + } +} +#[doc = "Field `BKTRST` reader - BKUP Registers Reset On Tamper Enable"] +pub type BKTRST_R = crate::BitReader; +#[doc = "Field `BKTRST` writer - BKUP Registers Reset On Tamper Enable"] +pub type BKTRST_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRLA_SPEC, bool, O>; +#[doc = "Field `GPTRST` reader - GP Registers Reset On Tamper Enable"] +pub type GPTRST_R = crate::BitReader; +#[doc = "Field `GPTRST` writer - GP Registers Reset On Tamper Enable"] +pub type GPTRST_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRLA_SPEC, bool, O>; +#[doc = "Field `CLOCKSYNC` reader - Clock Read Synchronization Enable"] +pub type CLOCKSYNC_R = crate::BitReader; +#[doc = "Field `CLOCKSYNC` writer - Clock Read Synchronization Enable"] +pub type CLOCKSYNC_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRLA_SPEC, bool, O>; +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bit 6 - Clock Representation"] + #[inline(always)] + pub fn clkrep(&self) -> CLKREP_R { + CLKREP_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Clear on Match"] + #[inline(always)] + pub fn matchclr(&self) -> MATCHCLR_R { + MATCHCLR_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 13 - BKUP Registers Reset On Tamper Enable"] + #[inline(always)] + pub fn bktrst(&self) -> BKTRST_R { + BKTRST_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - GP Registers Reset On Tamper Enable"] + #[inline(always)] + pub fn gptrst(&self) -> GPTRST_R { + GPTRST_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Clock Read Synchronization Enable"] + #[inline(always)] + pub fn clocksync(&self) -> CLOCKSYNC_R { + CLOCKSYNC_R::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + #[must_use] + pub fn swrst(&mut self) -> SWRST_W<0> { + SWRST_W::new(self) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W<1> { + ENABLE_W::new(self) + } + #[doc = "Bits 2:3 - Operating Mode"] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> MODE_W<2> { + MODE_W::new(self) + } + #[doc = "Bit 6 - Clock Representation"] + #[inline(always)] + #[must_use] + pub fn clkrep(&mut self) -> CLKREP_W<6> { + CLKREP_W::new(self) + } + #[doc = "Bit 7 - Clear on Match"] + #[inline(always)] + #[must_use] + pub fn matchclr(&mut self) -> MATCHCLR_W<7> { + MATCHCLR_W::new(self) + } + #[doc = "Bits 8:11 - Prescaler"] + #[inline(always)] + #[must_use] + pub fn prescaler(&mut self) -> PRESCALER_W<8> { + PRESCALER_W::new(self) + } + #[doc = "Bit 13 - BKUP Registers Reset On Tamper Enable"] + #[inline(always)] + #[must_use] + pub fn bktrst(&mut self) -> BKTRST_W<13> { + BKTRST_W::new(self) + } + #[doc = "Bit 14 - GP Registers Reset On Tamper Enable"] + #[inline(always)] + #[must_use] + pub fn gptrst(&mut self) -> GPTRST_W<14> { + GPTRST_W::new(self) + } + #[doc = "Bit 15 - Clock Read Synchronization Enable"] + #[inline(always)] + #[must_use] + pub fn clocksync(&mut self) -> CLOCKSYNC_W<15> { + CLOCKSYNC_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/rtc/mode2/ctrlb.rs b/pac/atsaml22j/src/rtc/mode2/ctrlb.rs new file mode 100644 index 000000000000..936e988c6425 --- /dev/null +++ b/pac/atsaml22j/src/rtc/mode2/ctrlb.rs @@ -0,0 +1,424 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GP0EN` reader - General Purpose 0 Enable"] +pub type GP0EN_R = crate::BitReader; +#[doc = "Field `GP0EN` writer - General Purpose 0 Enable"] +pub type GP0EN_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRLB_SPEC, bool, O>; +#[doc = "Field `DEBMAJ` reader - Debouncer Majority Enable"] +pub type DEBMAJ_R = crate::BitReader; +#[doc = "Field `DEBMAJ` writer - Debouncer Majority Enable"] +pub type DEBMAJ_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRLB_SPEC, bool, O>; +#[doc = "Field `DEBASYNC` reader - Debouncer Asynchronous Enable"] +pub type DEBASYNC_R = crate::BitReader; +#[doc = "Field `DEBASYNC` writer - Debouncer Asynchronous Enable"] +pub type DEBASYNC_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRLB_SPEC, bool, O>; +#[doc = "Field `RTCOUT` reader - RTC Output Enable"] +pub type RTCOUT_R = crate::BitReader; +#[doc = "Field `RTCOUT` writer - RTC Output Enable"] +pub type RTCOUT_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRLB_SPEC, bool, O>; +#[doc = "Field `DMAEN` reader - DMA Enable"] +pub type DMAEN_R = crate::BitReader; +#[doc = "Field `DMAEN` writer - DMA Enable"] +pub type DMAEN_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRLB_SPEC, bool, O>; +#[doc = "Field `DEBF` reader - Debounce Freqnuency"] +pub type DEBF_R = crate::FieldReader; +#[doc = "Debounce Freqnuency\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum DEBFSELECT_A { + #[doc = "0: CLK_RTC_DEB = CLK_RTC/2"] + DIV2 = 0, + #[doc = "1: CLK_RTC_DEB = CLK_RTC/4"] + DIV4 = 1, + #[doc = "2: CLK_RTC_DEB = CLK_RTC/8"] + DIV8 = 2, + #[doc = "3: CLK_RTC_DEB = CLK_RTC/16"] + DIV16 = 3, + #[doc = "4: CLK_RTC_DEB = CLK_RTC/32"] + DIV32 = 4, + #[doc = "5: CLK_RTC_DEB = CLK_RTC/64"] + DIV64 = 5, + #[doc = "6: CLK_RTC_DEB = CLK_RTC/128"] + DIV128 = 6, + #[doc = "7: CLK_RTC_DEB = CLK_RTC/256"] + DIV256 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DEBFSELECT_A) -> Self { + variant as _ + } +} +impl DEBF_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DEBFSELECT_A { + match self.bits { + 0 => DEBFSELECT_A::DIV2, + 1 => DEBFSELECT_A::DIV4, + 2 => DEBFSELECT_A::DIV8, + 3 => DEBFSELECT_A::DIV16, + 4 => DEBFSELECT_A::DIV32, + 5 => DEBFSELECT_A::DIV64, + 6 => DEBFSELECT_A::DIV128, + 7 => DEBFSELECT_A::DIV256, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + *self == DEBFSELECT_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + *self == DEBFSELECT_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + *self == DEBFSELECT_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + *self == DEBFSELECT_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + *self == DEBFSELECT_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + *self == DEBFSELECT_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + *self == DEBFSELECT_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + *self == DEBFSELECT_A::DIV256 + } +} +#[doc = "Field `DEBF` writer - Debounce Freqnuency"] +pub type DEBF_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u16, CTRLB_SPEC, u8, DEBFSELECT_A, 3, O>; +impl<'a, const O: u8> DEBF_W<'a, O> { + #[doc = "CLK_RTC_DEB = CLK_RTC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(DEBFSELECT_A::DIV2) + } + #[doc = "CLK_RTC_DEB = CLK_RTC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(DEBFSELECT_A::DIV4) + } + #[doc = "CLK_RTC_DEB = CLK_RTC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(DEBFSELECT_A::DIV8) + } + #[doc = "CLK_RTC_DEB = CLK_RTC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(DEBFSELECT_A::DIV16) + } + #[doc = "CLK_RTC_DEB = CLK_RTC/32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(DEBFSELECT_A::DIV32) + } + #[doc = "CLK_RTC_DEB = CLK_RTC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(DEBFSELECT_A::DIV64) + } + #[doc = "CLK_RTC_DEB = CLK_RTC/128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(DEBFSELECT_A::DIV128) + } + #[doc = "CLK_RTC_DEB = CLK_RTC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(DEBFSELECT_A::DIV256) + } +} +#[doc = "Field `ACTF` reader - Active Layer Freqnuency"] +pub type ACTF_R = crate::FieldReader; +#[doc = "Active Layer Freqnuency\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum ACTFSELECT_A { + #[doc = "0: CLK_RTC_OUT = CLK_RTC/2"] + DIV2 = 0, + #[doc = "1: CLK_RTC_OUT = CLK_RTC/4"] + DIV4 = 1, + #[doc = "2: CLK_RTC_OUT = CLK_RTC/8"] + DIV8 = 2, + #[doc = "3: CLK_RTC_OUT = CLK_RTC/16"] + DIV16 = 3, + #[doc = "4: CLK_RTC_OUT = CLK_RTC/32"] + DIV32 = 4, + #[doc = "5: CLK_RTC_OUT = CLK_RTC/64"] + DIV64 = 5, + #[doc = "6: CLK_RTC_OUT = CLK_RTC/128"] + DIV128 = 6, + #[doc = "7: CLK_RTC_OUT = CLK_RTC/256"] + DIV256 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ACTFSELECT_A) -> Self { + variant as _ + } +} +impl ACTF_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ACTFSELECT_A { + match self.bits { + 0 => ACTFSELECT_A::DIV2, + 1 => ACTFSELECT_A::DIV4, + 2 => ACTFSELECT_A::DIV8, + 3 => ACTFSELECT_A::DIV16, + 4 => ACTFSELECT_A::DIV32, + 5 => ACTFSELECT_A::DIV64, + 6 => ACTFSELECT_A::DIV128, + 7 => ACTFSELECT_A::DIV256, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + *self == ACTFSELECT_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + *self == ACTFSELECT_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + *self == ACTFSELECT_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + *self == ACTFSELECT_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + *self == ACTFSELECT_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + *self == ACTFSELECT_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + *self == ACTFSELECT_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + *self == ACTFSELECT_A::DIV256 + } +} +#[doc = "Field `ACTF` writer - Active Layer Freqnuency"] +pub type ACTF_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u16, CTRLB_SPEC, u8, ACTFSELECT_A, 3, O>; +impl<'a, const O: u8> ACTF_W<'a, O> { + #[doc = "CLK_RTC_OUT = CLK_RTC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(ACTFSELECT_A::DIV2) + } + #[doc = "CLK_RTC_OUT = CLK_RTC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(ACTFSELECT_A::DIV4) + } + #[doc = "CLK_RTC_OUT = CLK_RTC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(ACTFSELECT_A::DIV8) + } + #[doc = "CLK_RTC_OUT = CLK_RTC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(ACTFSELECT_A::DIV16) + } + #[doc = "CLK_RTC_OUT = CLK_RTC/32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(ACTFSELECT_A::DIV32) + } + #[doc = "CLK_RTC_OUT = CLK_RTC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(ACTFSELECT_A::DIV64) + } + #[doc = "CLK_RTC_OUT = CLK_RTC/128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(ACTFSELECT_A::DIV128) + } + #[doc = "CLK_RTC_OUT = CLK_RTC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(ACTFSELECT_A::DIV256) + } +} +impl R { + #[doc = "Bit 0 - General Purpose 0 Enable"] + #[inline(always)] + pub fn gp0en(&self) -> GP0EN_R { + GP0EN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 4 - Debouncer Majority Enable"] + #[inline(always)] + pub fn debmaj(&self) -> DEBMAJ_R { + DEBMAJ_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Debouncer Asynchronous Enable"] + #[inline(always)] + pub fn debasync(&self) -> DEBASYNC_R { + DEBASYNC_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - RTC Output Enable"] + #[inline(always)] + pub fn rtcout(&self) -> RTCOUT_R { + RTCOUT_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - DMA Enable"] + #[inline(always)] + pub fn dmaen(&self) -> DMAEN_R { + DMAEN_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:10 - Debounce Freqnuency"] + #[inline(always)] + pub fn debf(&self) -> DEBF_R { + DEBF_R::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bits 12:14 - Active Layer Freqnuency"] + #[inline(always)] + pub fn actf(&self) -> ACTF_R { + ACTF_R::new(((self.bits >> 12) & 7) as u8) + } +} +impl W { + #[doc = "Bit 0 - General Purpose 0 Enable"] + #[inline(always)] + #[must_use] + pub fn gp0en(&mut self) -> GP0EN_W<0> { + GP0EN_W::new(self) + } + #[doc = "Bit 4 - Debouncer Majority Enable"] + #[inline(always)] + #[must_use] + pub fn debmaj(&mut self) -> DEBMAJ_W<4> { + DEBMAJ_W::new(self) + } + #[doc = "Bit 5 - Debouncer Asynchronous Enable"] + #[inline(always)] + #[must_use] + pub fn debasync(&mut self) -> DEBASYNC_W<5> { + DEBASYNC_W::new(self) + } + #[doc = "Bit 6 - RTC Output Enable"] + #[inline(always)] + #[must_use] + pub fn rtcout(&mut self) -> RTCOUT_W<6> { + RTCOUT_W::new(self) + } + #[doc = "Bit 7 - DMA Enable"] + #[inline(always)] + #[must_use] + pub fn dmaen(&mut self) -> DMAEN_W<7> { + DMAEN_W::new(self) + } + #[doc = "Bits 8:10 - Debounce Freqnuency"] + #[inline(always)] + #[must_use] + pub fn debf(&mut self) -> DEBF_W<8> { + DEBF_W::new(self) + } + #[doc = "Bits 12:14 - Active Layer Freqnuency"] + #[inline(always)] + #[must_use] + pub fn actf(&mut self) -> ACTF_W<12> { + ACTF_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/rtc/mode2/dbgctrl.rs b/pac/atsaml22j/src/rtc/mode2/dbgctrl.rs new file mode 100644 index 000000000000..271f8aa633ac --- /dev/null +++ b/pac/atsaml22j/src/rtc/mode2/dbgctrl.rs @@ -0,0 +1,80 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub type DBGRUN_R = crate::BitReader; +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub type DBGRUN_W<'a, const O: u8> = crate::BitWriter<'a, u8, DBGCTRL_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + #[must_use] + pub fn dbgrun(&mut self) -> DBGRUN_W<0> { + DBGRUN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/rtc/mode2/evctrl.rs b/pac/atsaml22j/src/rtc/mode2/evctrl.rs new file mode 100644 index 000000000000..df1e0c9eccb6 --- /dev/null +++ b/pac/atsaml22j/src/rtc/mode2/evctrl.rs @@ -0,0 +1,245 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PEREO0` reader - Periodic Interval 0 Event Output Enable"] +pub type PEREO0_R = crate::BitReader; +#[doc = "Field `PEREO0` writer - Periodic Interval 0 Event Output Enable"] +pub type PEREO0_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVCTRL_SPEC, bool, O>; +#[doc = "Field `PEREO1` reader - Periodic Interval 1 Event Output Enable"] +pub type PEREO1_R = crate::BitReader; +#[doc = "Field `PEREO1` writer - Periodic Interval 1 Event Output Enable"] +pub type PEREO1_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVCTRL_SPEC, bool, O>; +#[doc = "Field `PEREO2` reader - Periodic Interval 2 Event Output Enable"] +pub type PEREO2_R = crate::BitReader; +#[doc = "Field `PEREO2` writer - Periodic Interval 2 Event Output Enable"] +pub type PEREO2_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVCTRL_SPEC, bool, O>; +#[doc = "Field `PEREO3` reader - Periodic Interval 3 Event Output Enable"] +pub type PEREO3_R = crate::BitReader; +#[doc = "Field `PEREO3` writer - Periodic Interval 3 Event Output Enable"] +pub type PEREO3_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVCTRL_SPEC, bool, O>; +#[doc = "Field `PEREO4` reader - Periodic Interval 4 Event Output Enable"] +pub type PEREO4_R = crate::BitReader; +#[doc = "Field `PEREO4` writer - Periodic Interval 4 Event Output Enable"] +pub type PEREO4_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVCTRL_SPEC, bool, O>; +#[doc = "Field `PEREO5` reader - Periodic Interval 5 Event Output Enable"] +pub type PEREO5_R = crate::BitReader; +#[doc = "Field `PEREO5` writer - Periodic Interval 5 Event Output Enable"] +pub type PEREO5_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVCTRL_SPEC, bool, O>; +#[doc = "Field `PEREO6` reader - Periodic Interval 6 Event Output Enable"] +pub type PEREO6_R = crate::BitReader; +#[doc = "Field `PEREO6` writer - Periodic Interval 6 Event Output Enable"] +pub type PEREO6_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVCTRL_SPEC, bool, O>; +#[doc = "Field `PEREO7` reader - Periodic Interval 7 Event Output Enable"] +pub type PEREO7_R = crate::BitReader; +#[doc = "Field `PEREO7` writer - Periodic Interval 7 Event Output Enable"] +pub type PEREO7_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVCTRL_SPEC, bool, O>; +#[doc = "Field `ALARMEO0` reader - Alarm 0 Event Output Enable"] +pub type ALARMEO0_R = crate::BitReader; +#[doc = "Field `ALARMEO0` writer - Alarm 0 Event Output Enable"] +pub type ALARMEO0_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVCTRL_SPEC, bool, O>; +#[doc = "Field `TAMPEREO` reader - Tamper Event Output Enable"] +pub type TAMPEREO_R = crate::BitReader; +#[doc = "Field `TAMPEREO` writer - Tamper Event Output Enable"] +pub type TAMPEREO_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVCTRL_SPEC, bool, O>; +#[doc = "Field `OVFEO` reader - Overflow Event Output Enable"] +pub type OVFEO_R = crate::BitReader; +#[doc = "Field `OVFEO` writer - Overflow Event Output Enable"] +pub type OVFEO_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVCTRL_SPEC, bool, O>; +#[doc = "Field `TAMPEVEI` reader - Tamper Event Input Enable"] +pub type TAMPEVEI_R = crate::BitReader; +#[doc = "Field `TAMPEVEI` writer - Tamper Event Input Enable"] +pub type TAMPEVEI_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVCTRL_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + pub fn pereo0(&self) -> PEREO0_R { + PEREO0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + pub fn pereo1(&self) -> PEREO1_R { + PEREO1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + pub fn pereo2(&self) -> PEREO2_R { + PEREO2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + pub fn pereo3(&self) -> PEREO3_R { + PEREO3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + pub fn pereo4(&self) -> PEREO4_R { + PEREO4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + pub fn pereo5(&self) -> PEREO5_R { + PEREO5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + pub fn pereo6(&self) -> PEREO6_R { + PEREO6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + pub fn pereo7(&self) -> PEREO7_R { + PEREO7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Alarm 0 Event Output Enable"] + #[inline(always)] + pub fn alarmeo0(&self) -> ALARMEO0_R { + ALARMEO0_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 14 - Tamper Event Output Enable"] + #[inline(always)] + pub fn tampereo(&self) -> TAMPEREO_R { + TAMPEREO_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Tamper Event Input Enable"] + #[inline(always)] + pub fn tampevei(&self) -> TAMPEVEI_R { + TAMPEVEI_R::new(((self.bits >> 16) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Event Output Enable"] + #[inline(always)] + #[must_use] + pub fn pereo0(&mut self) -> PEREO0_W<0> { + PEREO0_W::new(self) + } + #[doc = "Bit 1 - Periodic Interval 1 Event Output Enable"] + #[inline(always)] + #[must_use] + pub fn pereo1(&mut self) -> PEREO1_W<1> { + PEREO1_W::new(self) + } + #[doc = "Bit 2 - Periodic Interval 2 Event Output Enable"] + #[inline(always)] + #[must_use] + pub fn pereo2(&mut self) -> PEREO2_W<2> { + PEREO2_W::new(self) + } + #[doc = "Bit 3 - Periodic Interval 3 Event Output Enable"] + #[inline(always)] + #[must_use] + pub fn pereo3(&mut self) -> PEREO3_W<3> { + PEREO3_W::new(self) + } + #[doc = "Bit 4 - Periodic Interval 4 Event Output Enable"] + #[inline(always)] + #[must_use] + pub fn pereo4(&mut self) -> PEREO4_W<4> { + PEREO4_W::new(self) + } + #[doc = "Bit 5 - Periodic Interval 5 Event Output Enable"] + #[inline(always)] + #[must_use] + pub fn pereo5(&mut self) -> PEREO5_W<5> { + PEREO5_W::new(self) + } + #[doc = "Bit 6 - Periodic Interval 6 Event Output Enable"] + #[inline(always)] + #[must_use] + pub fn pereo6(&mut self) -> PEREO6_W<6> { + PEREO6_W::new(self) + } + #[doc = "Bit 7 - Periodic Interval 7 Event Output Enable"] + #[inline(always)] + #[must_use] + pub fn pereo7(&mut self) -> PEREO7_W<7> { + PEREO7_W::new(self) + } + #[doc = "Bit 8 - Alarm 0 Event Output Enable"] + #[inline(always)] + #[must_use] + pub fn alarmeo0(&mut self) -> ALARMEO0_W<8> { + ALARMEO0_W::new(self) + } + #[doc = "Bit 14 - Tamper Event Output Enable"] + #[inline(always)] + #[must_use] + pub fn tampereo(&mut self) -> TAMPEREO_W<14> { + TAMPEREO_W::new(self) + } + #[doc = "Bit 15 - Overflow Event Output Enable"] + #[inline(always)] + #[must_use] + pub fn ovfeo(&mut self) -> OVFEO_W<15> { + OVFEO_W::new(self) + } + #[doc = "Bit 16 - Tamper Event Input Enable"] + #[inline(always)] + #[must_use] + pub fn tampevei(&mut self) -> TAMPEVEI_W<16> { + TAMPEVEI_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/rtc/mode2/freqcorr.rs b/pac/atsaml22j/src/rtc/mode2/freqcorr.rs new file mode 100644 index 000000000000..0a0b886b28f6 --- /dev/null +++ b/pac/atsaml22j/src/rtc/mode2/freqcorr.rs @@ -0,0 +1,95 @@ +#[doc = "Register `FREQCORR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FREQCORR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `VALUE` reader - Correction Value"] +pub type VALUE_R = crate::FieldReader; +#[doc = "Field `VALUE` writer - Correction Value"] +pub type VALUE_W<'a, const O: u8> = crate::FieldWriter<'a, u8, FREQCORR_SPEC, u8, u8, 7, O>; +#[doc = "Field `SIGN` reader - Correction Sign"] +pub type SIGN_R = crate::BitReader; +#[doc = "Field `SIGN` writer - Correction Sign"] +pub type SIGN_W<'a, const O: u8> = crate::BitWriter<'a, u8, FREQCORR_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + pub fn value(&self) -> VALUE_R { + VALUE_R::new(self.bits & 0x7f) + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + pub fn sign(&self) -> SIGN_R { + SIGN_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - Correction Value"] + #[inline(always)] + #[must_use] + pub fn value(&mut self) -> VALUE_W<0> { + VALUE_W::new(self) + } + #[doc = "Bit 7 - Correction Sign"] + #[inline(always)] + #[must_use] + pub fn sign(&mut self) -> SIGN_W<7> { + SIGN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Frequency Correction\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [freqcorr](index.html) module"] +pub struct FREQCORR_SPEC; +impl crate::RegisterSpec for FREQCORR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [freqcorr::R](R) reader structure"] +impl crate::Readable for FREQCORR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [freqcorr::W](W) writer structure"] +impl crate::Writable for FREQCORR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FREQCORR to value 0"] +impl crate::Resettable for FREQCORR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/rtc/mode2/gp.rs b/pac/atsaml22j/src/rtc/mode2/gp.rs new file mode 100644 index 000000000000..c674475e018c --- /dev/null +++ b/pac/atsaml22j/src/rtc/mode2/gp.rs @@ -0,0 +1,80 @@ +#[doc = "Register `GP%s` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `GP%s` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GP` reader - General Purpose"] +pub type GP_R = crate::FieldReader; +#[doc = "Field `GP` writer - General Purpose"] +pub type GP_W<'a, const O: u8> = crate::FieldWriter<'a, u32, GP_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - General Purpose"] + #[inline(always)] + pub fn gp(&self) -> GP_R { + GP_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - General Purpose"] + #[inline(always)] + #[must_use] + pub fn gp(&mut self) -> GP_W<0> { + GP_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "General Purpose\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [gp](index.html) module"] +pub struct GP_SPEC; +impl crate::RegisterSpec for GP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [gp::R](R) reader structure"] +impl crate::Readable for GP_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [gp::W](W) writer structure"] +impl crate::Writable for GP_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets GP%s to value 0"] +impl crate::Resettable for GP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/rtc/mode2/intenclr.rs b/pac/atsaml22j/src/rtc/mode2/intenclr.rs new file mode 100644 index 000000000000..54c1aef3ee75 --- /dev/null +++ b/pac/atsaml22j/src/rtc/mode2/intenclr.rs @@ -0,0 +1,230 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0 Interrupt Enable"] +pub type PER0_R = crate::BitReader; +#[doc = "Field `PER0` writer - Periodic Interval 0 Interrupt Enable"] +pub type PER0_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENCLR_SPEC, bool, O>; +#[doc = "Field `PER1` reader - Periodic Interval 1 Interrupt Enable"] +pub type PER1_R = crate::BitReader; +#[doc = "Field `PER1` writer - Periodic Interval 1 Interrupt Enable"] +pub type PER1_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENCLR_SPEC, bool, O>; +#[doc = "Field `PER2` reader - Periodic Interval 2 Interrupt Enable"] +pub type PER2_R = crate::BitReader; +#[doc = "Field `PER2` writer - Periodic Interval 2 Interrupt Enable"] +pub type PER2_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENCLR_SPEC, bool, O>; +#[doc = "Field `PER3` reader - Periodic Interval 3 Interrupt Enable"] +pub type PER3_R = crate::BitReader; +#[doc = "Field `PER3` writer - Periodic Interval 3 Interrupt Enable"] +pub type PER3_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENCLR_SPEC, bool, O>; +#[doc = "Field `PER4` reader - Periodic Interval 4 Interrupt Enable"] +pub type PER4_R = crate::BitReader; +#[doc = "Field `PER4` writer - Periodic Interval 4 Interrupt Enable"] +pub type PER4_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENCLR_SPEC, bool, O>; +#[doc = "Field `PER5` reader - Periodic Interval 5 Interrupt Enable"] +pub type PER5_R = crate::BitReader; +#[doc = "Field `PER5` writer - Periodic Interval 5 Interrupt Enable"] +pub type PER5_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENCLR_SPEC, bool, O>; +#[doc = "Field `PER6` reader - Periodic Interval 6 Interrupt Enable"] +pub type PER6_R = crate::BitReader; +#[doc = "Field `PER6` writer - Periodic Interval 6 Interrupt Enable"] +pub type PER6_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENCLR_SPEC, bool, O>; +#[doc = "Field `PER7` reader - Periodic Interval 7 Interrupt Enable"] +pub type PER7_R = crate::BitReader; +#[doc = "Field `PER7` writer - Periodic Interval 7 Interrupt Enable"] +pub type PER7_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENCLR_SPEC, bool, O>; +#[doc = "Field `ALARM0` reader - Alarm 0 Interrupt Enable"] +pub type ALARM0_R = crate::BitReader; +#[doc = "Field `ALARM0` writer - Alarm 0 Interrupt Enable"] +pub type ALARM0_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENCLR_SPEC, bool, O>; +#[doc = "Field `TAMPER` reader - Tamper Enable"] +pub type TAMPER_R = crate::BitReader; +#[doc = "Field `TAMPER` writer - Tamper Enable"] +pub type TAMPER_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENCLR_SPEC, bool, O>; +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub type OVF_R = crate::BitReader; +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub type OVF_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENCLR_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Alarm 0 Interrupt Enable"] + #[inline(always)] + pub fn alarm0(&self) -> ALARM0_R { + ALARM0_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 14 - Tamper Enable"] + #[inline(always)] + pub fn tamper(&self) -> TAMPER_R { + TAMPER_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn per0(&mut self) -> PER0_W<0> { + PER0_W::new(self) + } + #[doc = "Bit 1 - Periodic Interval 1 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn per1(&mut self) -> PER1_W<1> { + PER1_W::new(self) + } + #[doc = "Bit 2 - Periodic Interval 2 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn per2(&mut self) -> PER2_W<2> { + PER2_W::new(self) + } + #[doc = "Bit 3 - Periodic Interval 3 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn per3(&mut self) -> PER3_W<3> { + PER3_W::new(self) + } + #[doc = "Bit 4 - Periodic Interval 4 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn per4(&mut self) -> PER4_W<4> { + PER4_W::new(self) + } + #[doc = "Bit 5 - Periodic Interval 5 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn per5(&mut self) -> PER5_W<5> { + PER5_W::new(self) + } + #[doc = "Bit 6 - Periodic Interval 6 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn per6(&mut self) -> PER6_W<6> { + PER6_W::new(self) + } + #[doc = "Bit 7 - Periodic Interval 7 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn per7(&mut self) -> PER7_W<7> { + PER7_W::new(self) + } + #[doc = "Bit 8 - Alarm 0 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn alarm0(&mut self) -> ALARM0_W<8> { + ALARM0_W::new(self) + } + #[doc = "Bit 14 - Tamper Enable"] + #[inline(always)] + #[must_use] + pub fn tamper(&mut self) -> TAMPER_W<14> { + TAMPER_W::new(self) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn ovf(&mut self) -> OVF_W<15> { + OVF_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/rtc/mode2/intenset.rs b/pac/atsaml22j/src/rtc/mode2/intenset.rs new file mode 100644 index 000000000000..b94de33b3e06 --- /dev/null +++ b/pac/atsaml22j/src/rtc/mode2/intenset.rs @@ -0,0 +1,230 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0 Enable"] +pub type PER0_R = crate::BitReader; +#[doc = "Field `PER0` writer - Periodic Interval 0 Enable"] +pub type PER0_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENSET_SPEC, bool, O>; +#[doc = "Field `PER1` reader - Periodic Interval 1 Enable"] +pub type PER1_R = crate::BitReader; +#[doc = "Field `PER1` writer - Periodic Interval 1 Enable"] +pub type PER1_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENSET_SPEC, bool, O>; +#[doc = "Field `PER2` reader - Periodic Interval 2 Enable"] +pub type PER2_R = crate::BitReader; +#[doc = "Field `PER2` writer - Periodic Interval 2 Enable"] +pub type PER2_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENSET_SPEC, bool, O>; +#[doc = "Field `PER3` reader - Periodic Interval 3 Enable"] +pub type PER3_R = crate::BitReader; +#[doc = "Field `PER3` writer - Periodic Interval 3 Enable"] +pub type PER3_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENSET_SPEC, bool, O>; +#[doc = "Field `PER4` reader - Periodic Interval 4 Enable"] +pub type PER4_R = crate::BitReader; +#[doc = "Field `PER4` writer - Periodic Interval 4 Enable"] +pub type PER4_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENSET_SPEC, bool, O>; +#[doc = "Field `PER5` reader - Periodic Interval 5 Enable"] +pub type PER5_R = crate::BitReader; +#[doc = "Field `PER5` writer - Periodic Interval 5 Enable"] +pub type PER5_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENSET_SPEC, bool, O>; +#[doc = "Field `PER6` reader - Periodic Interval 6 Enable"] +pub type PER6_R = crate::BitReader; +#[doc = "Field `PER6` writer - Periodic Interval 6 Enable"] +pub type PER6_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENSET_SPEC, bool, O>; +#[doc = "Field `PER7` reader - Periodic Interval 7 Enable"] +pub type PER7_R = crate::BitReader; +#[doc = "Field `PER7` writer - Periodic Interval 7 Enable"] +pub type PER7_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENSET_SPEC, bool, O>; +#[doc = "Field `ALARM0` reader - Alarm 0 Interrupt Enable"] +pub type ALARM0_R = crate::BitReader; +#[doc = "Field `ALARM0` writer - Alarm 0 Interrupt Enable"] +pub type ALARM0_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENSET_SPEC, bool, O>; +#[doc = "Field `TAMPER` reader - Tamper Enable"] +pub type TAMPER_R = crate::BitReader; +#[doc = "Field `TAMPER` writer - Tamper Enable"] +pub type TAMPER_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENSET_SPEC, bool, O>; +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub type OVF_R = crate::BitReader; +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub type OVF_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENSET_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Periodic Interval 0 Enable"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1 Enable"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2 Enable"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3 Enable"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4 Enable"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5 Enable"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6 Enable"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7 Enable"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Alarm 0 Interrupt Enable"] + #[inline(always)] + pub fn alarm0(&self) -> ALARM0_R { + ALARM0_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 14 - Tamper Enable"] + #[inline(always)] + pub fn tamper(&self) -> TAMPER_R { + TAMPER_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0 Enable"] + #[inline(always)] + #[must_use] + pub fn per0(&mut self) -> PER0_W<0> { + PER0_W::new(self) + } + #[doc = "Bit 1 - Periodic Interval 1 Enable"] + #[inline(always)] + #[must_use] + pub fn per1(&mut self) -> PER1_W<1> { + PER1_W::new(self) + } + #[doc = "Bit 2 - Periodic Interval 2 Enable"] + #[inline(always)] + #[must_use] + pub fn per2(&mut self) -> PER2_W<2> { + PER2_W::new(self) + } + #[doc = "Bit 3 - Periodic Interval 3 Enable"] + #[inline(always)] + #[must_use] + pub fn per3(&mut self) -> PER3_W<3> { + PER3_W::new(self) + } + #[doc = "Bit 4 - Periodic Interval 4 Enable"] + #[inline(always)] + #[must_use] + pub fn per4(&mut self) -> PER4_W<4> { + PER4_W::new(self) + } + #[doc = "Bit 5 - Periodic Interval 5 Enable"] + #[inline(always)] + #[must_use] + pub fn per5(&mut self) -> PER5_W<5> { + PER5_W::new(self) + } + #[doc = "Bit 6 - Periodic Interval 6 Enable"] + #[inline(always)] + #[must_use] + pub fn per6(&mut self) -> PER6_W<6> { + PER6_W::new(self) + } + #[doc = "Bit 7 - Periodic Interval 7 Enable"] + #[inline(always)] + #[must_use] + pub fn per7(&mut self) -> PER7_W<7> { + PER7_W::new(self) + } + #[doc = "Bit 8 - Alarm 0 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn alarm0(&mut self) -> ALARM0_W<8> { + ALARM0_W::new(self) + } + #[doc = "Bit 14 - Tamper Enable"] + #[inline(always)] + #[must_use] + pub fn tamper(&mut self) -> TAMPER_W<14> { + TAMPER_W::new(self) + } + #[doc = "Bit 15 - Overflow Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn ovf(&mut self) -> OVF_W<15> { + OVF_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/rtc/mode2/intflag.rs b/pac/atsaml22j/src/rtc/mode2/intflag.rs new file mode 100644 index 000000000000..da851e9b6a22 --- /dev/null +++ b/pac/atsaml22j/src/rtc/mode2/intflag.rs @@ -0,0 +1,230 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER0` reader - Periodic Interval 0"] +pub type PER0_R = crate::BitReader; +#[doc = "Field `PER0` writer - Periodic Interval 0"] +pub type PER0_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTFLAG_SPEC, bool, O>; +#[doc = "Field `PER1` reader - Periodic Interval 1"] +pub type PER1_R = crate::BitReader; +#[doc = "Field `PER1` writer - Periodic Interval 1"] +pub type PER1_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTFLAG_SPEC, bool, O>; +#[doc = "Field `PER2` reader - Periodic Interval 2"] +pub type PER2_R = crate::BitReader; +#[doc = "Field `PER2` writer - Periodic Interval 2"] +pub type PER2_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTFLAG_SPEC, bool, O>; +#[doc = "Field `PER3` reader - Periodic Interval 3"] +pub type PER3_R = crate::BitReader; +#[doc = "Field `PER3` writer - Periodic Interval 3"] +pub type PER3_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTFLAG_SPEC, bool, O>; +#[doc = "Field `PER4` reader - Periodic Interval 4"] +pub type PER4_R = crate::BitReader; +#[doc = "Field `PER4` writer - Periodic Interval 4"] +pub type PER4_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTFLAG_SPEC, bool, O>; +#[doc = "Field `PER5` reader - Periodic Interval 5"] +pub type PER5_R = crate::BitReader; +#[doc = "Field `PER5` writer - Periodic Interval 5"] +pub type PER5_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTFLAG_SPEC, bool, O>; +#[doc = "Field `PER6` reader - Periodic Interval 6"] +pub type PER6_R = crate::BitReader; +#[doc = "Field `PER6` writer - Periodic Interval 6"] +pub type PER6_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTFLAG_SPEC, bool, O>; +#[doc = "Field `PER7` reader - Periodic Interval 7"] +pub type PER7_R = crate::BitReader; +#[doc = "Field `PER7` writer - Periodic Interval 7"] +pub type PER7_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTFLAG_SPEC, bool, O>; +#[doc = "Field `ALARM0` reader - Alarm 0"] +pub type ALARM0_R = crate::BitReader; +#[doc = "Field `ALARM0` writer - Alarm 0"] +pub type ALARM0_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTFLAG_SPEC, bool, O>; +#[doc = "Field `TAMPER` reader - Tamper"] +pub type TAMPER_R = crate::BitReader; +#[doc = "Field `TAMPER` writer - Tamper"] +pub type TAMPER_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTFLAG_SPEC, bool, O>; +#[doc = "Field `OVF` reader - Overflow"] +pub type OVF_R = crate::BitReader; +#[doc = "Field `OVF` writer - Overflow"] +pub type OVF_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTFLAG_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Periodic Interval 0"] + #[inline(always)] + pub fn per0(&self) -> PER0_R { + PER0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Periodic Interval 1"] + #[inline(always)] + pub fn per1(&self) -> PER1_R { + PER1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Periodic Interval 2"] + #[inline(always)] + pub fn per2(&self) -> PER2_R { + PER2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Periodic Interval 3"] + #[inline(always)] + pub fn per3(&self) -> PER3_R { + PER3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Periodic Interval 4"] + #[inline(always)] + pub fn per4(&self) -> PER4_R { + PER4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Periodic Interval 5"] + #[inline(always)] + pub fn per5(&self) -> PER5_R { + PER5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Periodic Interval 6"] + #[inline(always)] + pub fn per6(&self) -> PER6_R { + PER6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Periodic Interval 7"] + #[inline(always)] + pub fn per7(&self) -> PER7_R { + PER7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Alarm 0"] + #[inline(always)] + pub fn alarm0(&self) -> ALARM0_R { + ALARM0_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 14 - Tamper"] + #[inline(always)] + pub fn tamper(&self) -> TAMPER_R { + TAMPER_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Periodic Interval 0"] + #[inline(always)] + #[must_use] + pub fn per0(&mut self) -> PER0_W<0> { + PER0_W::new(self) + } + #[doc = "Bit 1 - Periodic Interval 1"] + #[inline(always)] + #[must_use] + pub fn per1(&mut self) -> PER1_W<1> { + PER1_W::new(self) + } + #[doc = "Bit 2 - Periodic Interval 2"] + #[inline(always)] + #[must_use] + pub fn per2(&mut self) -> PER2_W<2> { + PER2_W::new(self) + } + #[doc = "Bit 3 - Periodic Interval 3"] + #[inline(always)] + #[must_use] + pub fn per3(&mut self) -> PER3_W<3> { + PER3_W::new(self) + } + #[doc = "Bit 4 - Periodic Interval 4"] + #[inline(always)] + #[must_use] + pub fn per4(&mut self) -> PER4_W<4> { + PER4_W::new(self) + } + #[doc = "Bit 5 - Periodic Interval 5"] + #[inline(always)] + #[must_use] + pub fn per5(&mut self) -> PER5_W<5> { + PER5_W::new(self) + } + #[doc = "Bit 6 - Periodic Interval 6"] + #[inline(always)] + #[must_use] + pub fn per6(&mut self) -> PER6_W<6> { + PER6_W::new(self) + } + #[doc = "Bit 7 - Periodic Interval 7"] + #[inline(always)] + #[must_use] + pub fn per7(&mut self) -> PER7_W<7> { + PER7_W::new(self) + } + #[doc = "Bit 8 - Alarm 0"] + #[inline(always)] + #[must_use] + pub fn alarm0(&mut self) -> ALARM0_W<8> { + ALARM0_W::new(self) + } + #[doc = "Bit 14 - Tamper"] + #[inline(always)] + #[must_use] + pub fn tamper(&mut self) -> TAMPER_W<14> { + TAMPER_W::new(self) + } + #[doc = "Bit 15 - Overflow"] + #[inline(always)] + #[must_use] + pub fn ovf(&mut self) -> OVF_W<15> { + OVF_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/rtc/mode2/mask.rs b/pac/atsaml22j/src/rtc/mode2/mask.rs new file mode 100644 index 000000000000..1ac1c5067cf3 --- /dev/null +++ b/pac/atsaml22j/src/rtc/mode2/mask.rs @@ -0,0 +1,193 @@ +#[doc = "Register `MASK%s` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `MASK%s` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SEL` reader - Alarm Mask Selection"] +pub type SEL_R = crate::FieldReader; +#[doc = "Alarm Mask Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SELSELECT_A { + #[doc = "0: Alarm Disabled"] + OFF = 0, + #[doc = "1: Match seconds only"] + SS = 1, + #[doc = "2: Match seconds and minutes only"] + MMSS = 2, + #[doc = "3: Match seconds, minutes, and hours only"] + HHMMSS = 3, + #[doc = "4: Match seconds, minutes, hours, and days only"] + DDHHMMSS = 4, + #[doc = "5: Match seconds, minutes, hours, days, and months only"] + MMDDHHMMSS = 5, + #[doc = "6: Match seconds, minutes, hours, days, months, and years"] + YYMMDDHHMMSS = 6, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SELSELECT_A) -> Self { + variant as _ + } +} +impl SEL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SELSELECT_A::OFF), + 1 => Some(SELSELECT_A::SS), + 2 => Some(SELSELECT_A::MMSS), + 3 => Some(SELSELECT_A::HHMMSS), + 4 => Some(SELSELECT_A::DDHHMMSS), + 5 => Some(SELSELECT_A::MMDDHHMMSS), + 6 => Some(SELSELECT_A::YYMMDDHHMMSS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == SELSELECT_A::OFF + } + #[doc = "Checks if the value of the field is `SS`"] + #[inline(always)] + pub fn is_ss(&self) -> bool { + *self == SELSELECT_A::SS + } + #[doc = "Checks if the value of the field is `MMSS`"] + #[inline(always)] + pub fn is_mmss(&self) -> bool { + *self == SELSELECT_A::MMSS + } + #[doc = "Checks if the value of the field is `HHMMSS`"] + #[inline(always)] + pub fn is_hhmmss(&self) -> bool { + *self == SELSELECT_A::HHMMSS + } + #[doc = "Checks if the value of the field is `DDHHMMSS`"] + #[inline(always)] + pub fn is_ddhhmmss(&self) -> bool { + *self == SELSELECT_A::DDHHMMSS + } + #[doc = "Checks if the value of the field is `MMDDHHMMSS`"] + #[inline(always)] + pub fn is_mmddhhmmss(&self) -> bool { + *self == SELSELECT_A::MMDDHHMMSS + } + #[doc = "Checks if the value of the field is `YYMMDDHHMMSS`"] + #[inline(always)] + pub fn is_yymmddhhmmss(&self) -> bool { + *self == SELSELECT_A::YYMMDDHHMMSS + } +} +#[doc = "Field `SEL` writer - Alarm Mask Selection"] +pub type SEL_W<'a, const O: u8> = crate::FieldWriter<'a, u8, MASK_SPEC, u8, SELSELECT_A, 3, O>; +impl<'a, const O: u8> SEL_W<'a, O> { + #[doc = "Alarm Disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(SELSELECT_A::OFF) + } + #[doc = "Match seconds only"] + #[inline(always)] + pub fn ss(self) -> &'a mut W { + self.variant(SELSELECT_A::SS) + } + #[doc = "Match seconds and minutes only"] + #[inline(always)] + pub fn mmss(self) -> &'a mut W { + self.variant(SELSELECT_A::MMSS) + } + #[doc = "Match seconds, minutes, and hours only"] + #[inline(always)] + pub fn hhmmss(self) -> &'a mut W { + self.variant(SELSELECT_A::HHMMSS) + } + #[doc = "Match seconds, minutes, hours, and days only"] + #[inline(always)] + pub fn ddhhmmss(self) -> &'a mut W { + self.variant(SELSELECT_A::DDHHMMSS) + } + #[doc = "Match seconds, minutes, hours, days, and months only"] + #[inline(always)] + pub fn mmddhhmmss(self) -> &'a mut W { + self.variant(SELSELECT_A::MMDDHHMMSS) + } + #[doc = "Match seconds, minutes, hours, days, months, and years"] + #[inline(always)] + pub fn yymmddhhmmss(self) -> &'a mut W { + self.variant(SELSELECT_A::YYMMDDHHMMSS) + } +} +impl R { + #[doc = "Bits 0:2 - Alarm Mask Selection"] + #[inline(always)] + pub fn sel(&self) -> SEL_R { + SEL_R::new(self.bits & 7) + } +} +impl W { + #[doc = "Bits 0:2 - Alarm Mask Selection"] + #[inline(always)] + #[must_use] + pub fn sel(&mut self) -> SEL_W<0> { + SEL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "MODE2 Alarm n Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mask](index.html) module"] +pub struct MASK_SPEC; +impl crate::RegisterSpec for MASK_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [mask::R](R) reader structure"] +impl crate::Readable for MASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [mask::W](W) writer structure"] +impl crate::Writable for MASK_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets MASK%s to value 0"] +impl crate::Resettable for MASK_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/rtc/mode2/syncbusy.rs b/pac/atsaml22j/src/rtc/mode2/syncbusy.rs new file mode 100644 index 000000000000..a5633c82a8c6 --- /dev/null +++ b/pac/atsaml22j/src/rtc/mode2/syncbusy.rs @@ -0,0 +1,93 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Bit Busy"] +pub type SWRST_R = crate::BitReader; +#[doc = "Field `ENABLE` reader - Enable Bit Busy"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `FREQCORR` reader - FREQCORR Register Busy"] +pub type FREQCORR_R = crate::BitReader; +#[doc = "Field `CLOCK` reader - CLOCK Register Busy"] +pub type CLOCK_R = crate::BitReader; +#[doc = "Field `ALARM0` reader - ALARM 0 Register Busy"] +pub type ALARM0_R = crate::BitReader; +#[doc = "Field `MASK0` reader - MASK 0 Register Busy"] +pub type MASK0_R = crate::BitReader; +#[doc = "Field `CLOCKSYNC` reader - Clock Synchronization Enable Bit Busy"] +pub type CLOCKSYNC_R = crate::BitReader; +#[doc = "Field `GP0` reader - General Purpose 0 Register Busy"] +pub type GP0_R = crate::BitReader; +#[doc = "Field `GP1` reader - General Purpose 1 Register Busy"] +pub type GP1_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Software Reset Bit Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable Bit Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - FREQCORR Register Busy"] + #[inline(always)] + pub fn freqcorr(&self) -> FREQCORR_R { + FREQCORR_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - CLOCK Register Busy"] + #[inline(always)] + pub fn clock(&self) -> CLOCK_R { + CLOCK_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 5 - ALARM 0 Register Busy"] + #[inline(always)] + pub fn alarm0(&self) -> ALARM0_R { + ALARM0_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 11 - MASK 0 Register Busy"] + #[inline(always)] + pub fn mask0(&self) -> MASK0_R { + MASK0_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 15 - Clock Synchronization Enable Bit Busy"] + #[inline(always)] + pub fn clocksync(&self) -> CLOCKSYNC_R { + CLOCKSYNC_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - General Purpose 0 Register Busy"] + #[inline(always)] + pub fn gp0(&self) -> GP0_R { + GP0_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - General Purpose 1 Register Busy"] + #[inline(always)] + pub fn gp1(&self) -> GP1_R { + GP1_R::new(((self.bits >> 17) & 1) != 0) + } +} +#[doc = "MODE2 Synchronization Busy Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/rtc/mode2/tampctrl.rs b/pac/atsaml22j/src/rtc/mode2/tampctrl.rs new file mode 100644 index 000000000000..8765e653ee07 --- /dev/null +++ b/pac/atsaml22j/src/rtc/mode2/tampctrl.rs @@ -0,0 +1,665 @@ +#[doc = "Register `TAMPCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TAMPCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `IN0ACT` reader - Tamper Input 0 Action"] +pub type IN0ACT_R = crate::FieldReader; +#[doc = "Tamper Input 0 Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum IN0ACTSELECT_A { + #[doc = "0: Off (Disabled)"] + OFF = 0, + #[doc = "1: Wake without timestamp"] + WAKE = 1, + #[doc = "2: Capture timestamp"] + CAPTURE = 2, + #[doc = "3: Compare IN0 to OUT"] + ACTL = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: IN0ACTSELECT_A) -> Self { + variant as _ + } +} +impl IN0ACT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> IN0ACTSELECT_A { + match self.bits { + 0 => IN0ACTSELECT_A::OFF, + 1 => IN0ACTSELECT_A::WAKE, + 2 => IN0ACTSELECT_A::CAPTURE, + 3 => IN0ACTSELECT_A::ACTL, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == IN0ACTSELECT_A::OFF + } + #[doc = "Checks if the value of the field is `WAKE`"] + #[inline(always)] + pub fn is_wake(&self) -> bool { + *self == IN0ACTSELECT_A::WAKE + } + #[doc = "Checks if the value of the field is `CAPTURE`"] + #[inline(always)] + pub fn is_capture(&self) -> bool { + *self == IN0ACTSELECT_A::CAPTURE + } + #[doc = "Checks if the value of the field is `ACTL`"] + #[inline(always)] + pub fn is_actl(&self) -> bool { + *self == IN0ACTSELECT_A::ACTL + } +} +#[doc = "Field `IN0ACT` writer - Tamper Input 0 Action"] +pub type IN0ACT_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, TAMPCTRL_SPEC, u8, IN0ACTSELECT_A, 2, O>; +impl<'a, const O: u8> IN0ACT_W<'a, O> { + #[doc = "Off (Disabled)"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(IN0ACTSELECT_A::OFF) + } + #[doc = "Wake without timestamp"] + #[inline(always)] + pub fn wake(self) -> &'a mut W { + self.variant(IN0ACTSELECT_A::WAKE) + } + #[doc = "Capture timestamp"] + #[inline(always)] + pub fn capture(self) -> &'a mut W { + self.variant(IN0ACTSELECT_A::CAPTURE) + } + #[doc = "Compare IN0 to OUT"] + #[inline(always)] + pub fn actl(self) -> &'a mut W { + self.variant(IN0ACTSELECT_A::ACTL) + } +} +#[doc = "Field `IN1ACT` reader - Tamper Input 1 Action"] +pub type IN1ACT_R = crate::FieldReader; +#[doc = "Tamper Input 1 Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum IN1ACTSELECT_A { + #[doc = "0: Off (Disabled)"] + OFF = 0, + #[doc = "1: Wake without timestamp"] + WAKE = 1, + #[doc = "2: Capture timestamp"] + CAPTURE = 2, + #[doc = "3: Compare IN1 to OUT"] + ACTL = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: IN1ACTSELECT_A) -> Self { + variant as _ + } +} +impl IN1ACT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> IN1ACTSELECT_A { + match self.bits { + 0 => IN1ACTSELECT_A::OFF, + 1 => IN1ACTSELECT_A::WAKE, + 2 => IN1ACTSELECT_A::CAPTURE, + 3 => IN1ACTSELECT_A::ACTL, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == IN1ACTSELECT_A::OFF + } + #[doc = "Checks if the value of the field is `WAKE`"] + #[inline(always)] + pub fn is_wake(&self) -> bool { + *self == IN1ACTSELECT_A::WAKE + } + #[doc = "Checks if the value of the field is `CAPTURE`"] + #[inline(always)] + pub fn is_capture(&self) -> bool { + *self == IN1ACTSELECT_A::CAPTURE + } + #[doc = "Checks if the value of the field is `ACTL`"] + #[inline(always)] + pub fn is_actl(&self) -> bool { + *self == IN1ACTSELECT_A::ACTL + } +} +#[doc = "Field `IN1ACT` writer - Tamper Input 1 Action"] +pub type IN1ACT_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, TAMPCTRL_SPEC, u8, IN1ACTSELECT_A, 2, O>; +impl<'a, const O: u8> IN1ACT_W<'a, O> { + #[doc = "Off (Disabled)"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(IN1ACTSELECT_A::OFF) + } + #[doc = "Wake without timestamp"] + #[inline(always)] + pub fn wake(self) -> &'a mut W { + self.variant(IN1ACTSELECT_A::WAKE) + } + #[doc = "Capture timestamp"] + #[inline(always)] + pub fn capture(self) -> &'a mut W { + self.variant(IN1ACTSELECT_A::CAPTURE) + } + #[doc = "Compare IN1 to OUT"] + #[inline(always)] + pub fn actl(self) -> &'a mut W { + self.variant(IN1ACTSELECT_A::ACTL) + } +} +#[doc = "Field `IN2ACT` reader - Tamper Input 2 Action"] +pub type IN2ACT_R = crate::FieldReader; +#[doc = "Tamper Input 2 Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum IN2ACTSELECT_A { + #[doc = "0: Off (Disabled)"] + OFF = 0, + #[doc = "1: Wake without timestamp"] + WAKE = 1, + #[doc = "2: Capture timestamp"] + CAPTURE = 2, + #[doc = "3: Compare IN2 to OUT"] + ACTL = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: IN2ACTSELECT_A) -> Self { + variant as _ + } +} +impl IN2ACT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> IN2ACTSELECT_A { + match self.bits { + 0 => IN2ACTSELECT_A::OFF, + 1 => IN2ACTSELECT_A::WAKE, + 2 => IN2ACTSELECT_A::CAPTURE, + 3 => IN2ACTSELECT_A::ACTL, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == IN2ACTSELECT_A::OFF + } + #[doc = "Checks if the value of the field is `WAKE`"] + #[inline(always)] + pub fn is_wake(&self) -> bool { + *self == IN2ACTSELECT_A::WAKE + } + #[doc = "Checks if the value of the field is `CAPTURE`"] + #[inline(always)] + pub fn is_capture(&self) -> bool { + *self == IN2ACTSELECT_A::CAPTURE + } + #[doc = "Checks if the value of the field is `ACTL`"] + #[inline(always)] + pub fn is_actl(&self) -> bool { + *self == IN2ACTSELECT_A::ACTL + } +} +#[doc = "Field `IN2ACT` writer - Tamper Input 2 Action"] +pub type IN2ACT_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, TAMPCTRL_SPEC, u8, IN2ACTSELECT_A, 2, O>; +impl<'a, const O: u8> IN2ACT_W<'a, O> { + #[doc = "Off (Disabled)"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(IN2ACTSELECT_A::OFF) + } + #[doc = "Wake without timestamp"] + #[inline(always)] + pub fn wake(self) -> &'a mut W { + self.variant(IN2ACTSELECT_A::WAKE) + } + #[doc = "Capture timestamp"] + #[inline(always)] + pub fn capture(self) -> &'a mut W { + self.variant(IN2ACTSELECT_A::CAPTURE) + } + #[doc = "Compare IN2 to OUT"] + #[inline(always)] + pub fn actl(self) -> &'a mut W { + self.variant(IN2ACTSELECT_A::ACTL) + } +} +#[doc = "Field `IN3ACT` reader - Tamper Input 3 Action"] +pub type IN3ACT_R = crate::FieldReader; +#[doc = "Tamper Input 3 Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum IN3ACTSELECT_A { + #[doc = "0: Off (Disabled)"] + OFF = 0, + #[doc = "1: Wake without timestamp"] + WAKE = 1, + #[doc = "2: Capture timestamp"] + CAPTURE = 2, + #[doc = "3: Compare IN3 to OUT"] + ACTL = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: IN3ACTSELECT_A) -> Self { + variant as _ + } +} +impl IN3ACT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> IN3ACTSELECT_A { + match self.bits { + 0 => IN3ACTSELECT_A::OFF, + 1 => IN3ACTSELECT_A::WAKE, + 2 => IN3ACTSELECT_A::CAPTURE, + 3 => IN3ACTSELECT_A::ACTL, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == IN3ACTSELECT_A::OFF + } + #[doc = "Checks if the value of the field is `WAKE`"] + #[inline(always)] + pub fn is_wake(&self) -> bool { + *self == IN3ACTSELECT_A::WAKE + } + #[doc = "Checks if the value of the field is `CAPTURE`"] + #[inline(always)] + pub fn is_capture(&self) -> bool { + *self == IN3ACTSELECT_A::CAPTURE + } + #[doc = "Checks if the value of the field is `ACTL`"] + #[inline(always)] + pub fn is_actl(&self) -> bool { + *self == IN3ACTSELECT_A::ACTL + } +} +#[doc = "Field `IN3ACT` writer - Tamper Input 3 Action"] +pub type IN3ACT_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, TAMPCTRL_SPEC, u8, IN3ACTSELECT_A, 2, O>; +impl<'a, const O: u8> IN3ACT_W<'a, O> { + #[doc = "Off (Disabled)"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(IN3ACTSELECT_A::OFF) + } + #[doc = "Wake without timestamp"] + #[inline(always)] + pub fn wake(self) -> &'a mut W { + self.variant(IN3ACTSELECT_A::WAKE) + } + #[doc = "Capture timestamp"] + #[inline(always)] + pub fn capture(self) -> &'a mut W { + self.variant(IN3ACTSELECT_A::CAPTURE) + } + #[doc = "Compare IN3 to OUT"] + #[inline(always)] + pub fn actl(self) -> &'a mut W { + self.variant(IN3ACTSELECT_A::ACTL) + } +} +#[doc = "Field `IN4ACT` reader - Tamper Input 4 Action"] +pub type IN4ACT_R = crate::FieldReader; +#[doc = "Tamper Input 4 Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum IN4ACTSELECT_A { + #[doc = "0: Off (Disabled)"] + OFF = 0, + #[doc = "1: Wake without timestamp"] + WAKE = 1, + #[doc = "2: Capture timestamp"] + CAPTURE = 2, + #[doc = "3: Compare IN4 to OUT"] + ACTL = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: IN4ACTSELECT_A) -> Self { + variant as _ + } +} +impl IN4ACT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> IN4ACTSELECT_A { + match self.bits { + 0 => IN4ACTSELECT_A::OFF, + 1 => IN4ACTSELECT_A::WAKE, + 2 => IN4ACTSELECT_A::CAPTURE, + 3 => IN4ACTSELECT_A::ACTL, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == IN4ACTSELECT_A::OFF + } + #[doc = "Checks if the value of the field is `WAKE`"] + #[inline(always)] + pub fn is_wake(&self) -> bool { + *self == IN4ACTSELECT_A::WAKE + } + #[doc = "Checks if the value of the field is `CAPTURE`"] + #[inline(always)] + pub fn is_capture(&self) -> bool { + *self == IN4ACTSELECT_A::CAPTURE + } + #[doc = "Checks if the value of the field is `ACTL`"] + #[inline(always)] + pub fn is_actl(&self) -> bool { + *self == IN4ACTSELECT_A::ACTL + } +} +#[doc = "Field `IN4ACT` writer - Tamper Input 4 Action"] +pub type IN4ACT_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, TAMPCTRL_SPEC, u8, IN4ACTSELECT_A, 2, O>; +impl<'a, const O: u8> IN4ACT_W<'a, O> { + #[doc = "Off (Disabled)"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(IN4ACTSELECT_A::OFF) + } + #[doc = "Wake without timestamp"] + #[inline(always)] + pub fn wake(self) -> &'a mut W { + self.variant(IN4ACTSELECT_A::WAKE) + } + #[doc = "Capture timestamp"] + #[inline(always)] + pub fn capture(self) -> &'a mut W { + self.variant(IN4ACTSELECT_A::CAPTURE) + } + #[doc = "Compare IN4 to OUT"] + #[inline(always)] + pub fn actl(self) -> &'a mut W { + self.variant(IN4ACTSELECT_A::ACTL) + } +} +#[doc = "Field `TAMLVL0` reader - Tamper Level Select 0"] +pub type TAMLVL0_R = crate::BitReader; +#[doc = "Field `TAMLVL0` writer - Tamper Level Select 0"] +pub type TAMLVL0_W<'a, const O: u8> = crate::BitWriter<'a, u32, TAMPCTRL_SPEC, bool, O>; +#[doc = "Field `TAMLVL1` reader - Tamper Level Select 1"] +pub type TAMLVL1_R = crate::BitReader; +#[doc = "Field `TAMLVL1` writer - Tamper Level Select 1"] +pub type TAMLVL1_W<'a, const O: u8> = crate::BitWriter<'a, u32, TAMPCTRL_SPEC, bool, O>; +#[doc = "Field `TAMLVL2` reader - Tamper Level Select 2"] +pub type TAMLVL2_R = crate::BitReader; +#[doc = "Field `TAMLVL2` writer - Tamper Level Select 2"] +pub type TAMLVL2_W<'a, const O: u8> = crate::BitWriter<'a, u32, TAMPCTRL_SPEC, bool, O>; +#[doc = "Field `TAMLVL3` reader - Tamper Level Select 3"] +pub type TAMLVL3_R = crate::BitReader; +#[doc = "Field `TAMLVL3` writer - Tamper Level Select 3"] +pub type TAMLVL3_W<'a, const O: u8> = crate::BitWriter<'a, u32, TAMPCTRL_SPEC, bool, O>; +#[doc = "Field `TAMLVL4` reader - Tamper Level Select 4"] +pub type TAMLVL4_R = crate::BitReader; +#[doc = "Field `TAMLVL4` writer - Tamper Level Select 4"] +pub type TAMLVL4_W<'a, const O: u8> = crate::BitWriter<'a, u32, TAMPCTRL_SPEC, bool, O>; +#[doc = "Field `DEBNC0` reader - Debouncer Enable 0"] +pub type DEBNC0_R = crate::BitReader; +#[doc = "Field `DEBNC0` writer - Debouncer Enable 0"] +pub type DEBNC0_W<'a, const O: u8> = crate::BitWriter<'a, u32, TAMPCTRL_SPEC, bool, O>; +#[doc = "Field `DEBNC1` reader - Debouncer Enable 1"] +pub type DEBNC1_R = crate::BitReader; +#[doc = "Field `DEBNC1` writer - Debouncer Enable 1"] +pub type DEBNC1_W<'a, const O: u8> = crate::BitWriter<'a, u32, TAMPCTRL_SPEC, bool, O>; +#[doc = "Field `DEBNC2` reader - Debouncer Enable 2"] +pub type DEBNC2_R = crate::BitReader; +#[doc = "Field `DEBNC2` writer - Debouncer Enable 2"] +pub type DEBNC2_W<'a, const O: u8> = crate::BitWriter<'a, u32, TAMPCTRL_SPEC, bool, O>; +#[doc = "Field `DEBNC3` reader - Debouncer Enable 3"] +pub type DEBNC3_R = crate::BitReader; +#[doc = "Field `DEBNC3` writer - Debouncer Enable 3"] +pub type DEBNC3_W<'a, const O: u8> = crate::BitWriter<'a, u32, TAMPCTRL_SPEC, bool, O>; +#[doc = "Field `DEBNC4` reader - Debouncer Enable 4"] +pub type DEBNC4_R = crate::BitReader; +#[doc = "Field `DEBNC4` writer - Debouncer Enable 4"] +pub type DEBNC4_W<'a, const O: u8> = crate::BitWriter<'a, u32, TAMPCTRL_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:1 - Tamper Input 0 Action"] + #[inline(always)] + pub fn in0act(&self) -> IN0ACT_R { + IN0ACT_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 2:3 - Tamper Input 1 Action"] + #[inline(always)] + pub fn in1act(&self) -> IN1ACT_R { + IN1ACT_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Tamper Input 2 Action"] + #[inline(always)] + pub fn in2act(&self) -> IN2ACT_R { + IN2ACT_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bits 6:7 - Tamper Input 3 Action"] + #[inline(always)] + pub fn in3act(&self) -> IN3ACT_R { + IN3ACT_R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bits 8:9 - Tamper Input 4 Action"] + #[inline(always)] + pub fn in4act(&self) -> IN4ACT_R { + IN4ACT_R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bit 16 - Tamper Level Select 0"] + #[inline(always)] + pub fn tamlvl0(&self) -> TAMLVL0_R { + TAMLVL0_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Tamper Level Select 1"] + #[inline(always)] + pub fn tamlvl1(&self) -> TAMLVL1_R { + TAMLVL1_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Tamper Level Select 2"] + #[inline(always)] + pub fn tamlvl2(&self) -> TAMLVL2_R { + TAMLVL2_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Tamper Level Select 3"] + #[inline(always)] + pub fn tamlvl3(&self) -> TAMLVL3_R { + TAMLVL3_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Tamper Level Select 4"] + #[inline(always)] + pub fn tamlvl4(&self) -> TAMLVL4_R { + TAMLVL4_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 24 - Debouncer Enable 0"] + #[inline(always)] + pub fn debnc0(&self) -> DEBNC0_R { + DEBNC0_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Debouncer Enable 1"] + #[inline(always)] + pub fn debnc1(&self) -> DEBNC1_R { + DEBNC1_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Debouncer Enable 2"] + #[inline(always)] + pub fn debnc2(&self) -> DEBNC2_R { + DEBNC2_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Debouncer Enable 3"] + #[inline(always)] + pub fn debnc3(&self) -> DEBNC3_R { + DEBNC3_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 28 - Debouncer Enable 4"] + #[inline(always)] + pub fn debnc4(&self) -> DEBNC4_R { + DEBNC4_R::new(((self.bits >> 28) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:1 - Tamper Input 0 Action"] + #[inline(always)] + #[must_use] + pub fn in0act(&mut self) -> IN0ACT_W<0> { + IN0ACT_W::new(self) + } + #[doc = "Bits 2:3 - Tamper Input 1 Action"] + #[inline(always)] + #[must_use] + pub fn in1act(&mut self) -> IN1ACT_W<2> { + IN1ACT_W::new(self) + } + #[doc = "Bits 4:5 - Tamper Input 2 Action"] + #[inline(always)] + #[must_use] + pub fn in2act(&mut self) -> IN2ACT_W<4> { + IN2ACT_W::new(self) + } + #[doc = "Bits 6:7 - Tamper Input 3 Action"] + #[inline(always)] + #[must_use] + pub fn in3act(&mut self) -> IN3ACT_W<6> { + IN3ACT_W::new(self) + } + #[doc = "Bits 8:9 - Tamper Input 4 Action"] + #[inline(always)] + #[must_use] + pub fn in4act(&mut self) -> IN4ACT_W<8> { + IN4ACT_W::new(self) + } + #[doc = "Bit 16 - Tamper Level Select 0"] + #[inline(always)] + #[must_use] + pub fn tamlvl0(&mut self) -> TAMLVL0_W<16> { + TAMLVL0_W::new(self) + } + #[doc = "Bit 17 - Tamper Level Select 1"] + #[inline(always)] + #[must_use] + pub fn tamlvl1(&mut self) -> TAMLVL1_W<17> { + TAMLVL1_W::new(self) + } + #[doc = "Bit 18 - Tamper Level Select 2"] + #[inline(always)] + #[must_use] + pub fn tamlvl2(&mut self) -> TAMLVL2_W<18> { + TAMLVL2_W::new(self) + } + #[doc = "Bit 19 - Tamper Level Select 3"] + #[inline(always)] + #[must_use] + pub fn tamlvl3(&mut self) -> TAMLVL3_W<19> { + TAMLVL3_W::new(self) + } + #[doc = "Bit 20 - Tamper Level Select 4"] + #[inline(always)] + #[must_use] + pub fn tamlvl4(&mut self) -> TAMLVL4_W<20> { + TAMLVL4_W::new(self) + } + #[doc = "Bit 24 - Debouncer Enable 0"] + #[inline(always)] + #[must_use] + pub fn debnc0(&mut self) -> DEBNC0_W<24> { + DEBNC0_W::new(self) + } + #[doc = "Bit 25 - Debouncer Enable 1"] + #[inline(always)] + #[must_use] + pub fn debnc1(&mut self) -> DEBNC1_W<25> { + DEBNC1_W::new(self) + } + #[doc = "Bit 26 - Debouncer Enable 2"] + #[inline(always)] + #[must_use] + pub fn debnc2(&mut self) -> DEBNC2_W<26> { + DEBNC2_W::new(self) + } + #[doc = "Bit 27 - Debouncer Enable 3"] + #[inline(always)] + #[must_use] + pub fn debnc3(&mut self) -> DEBNC3_W<27> { + DEBNC3_W::new(self) + } + #[doc = "Bit 28 - Debouncer Enable 4"] + #[inline(always)] + #[must_use] + pub fn debnc4(&mut self) -> DEBNC4_W<28> { + DEBNC4_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Tamper Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tampctrl](index.html) module"] +pub struct TAMPCTRL_SPEC; +impl crate::RegisterSpec for TAMPCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tampctrl::R](R) reader structure"] +impl crate::Readable for TAMPCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [tampctrl::W](W) writer structure"] +impl crate::Writable for TAMPCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TAMPCTRL to value 0"] +impl crate::Resettable for TAMPCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/rtc/mode2/tampid.rs b/pac/atsaml22j/src/rtc/mode2/tampid.rs new file mode 100644 index 000000000000..3677f47b1990 --- /dev/null +++ b/pac/atsaml22j/src/rtc/mode2/tampid.rs @@ -0,0 +1,155 @@ +#[doc = "Register `TAMPID` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `TAMPID` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TAMPID0` reader - Tamper Input 0 Detected"] +pub type TAMPID0_R = crate::BitReader; +#[doc = "Field `TAMPID0` writer - Tamper Input 0 Detected"] +pub type TAMPID0_W<'a, const O: u8> = crate::BitWriter<'a, u32, TAMPID_SPEC, bool, O>; +#[doc = "Field `TAMPID1` reader - Tamper Input 1 Detected"] +pub type TAMPID1_R = crate::BitReader; +#[doc = "Field `TAMPID1` writer - Tamper Input 1 Detected"] +pub type TAMPID1_W<'a, const O: u8> = crate::BitWriter<'a, u32, TAMPID_SPEC, bool, O>; +#[doc = "Field `TAMPID2` reader - Tamper Input 2 Detected"] +pub type TAMPID2_R = crate::BitReader; +#[doc = "Field `TAMPID2` writer - Tamper Input 2 Detected"] +pub type TAMPID2_W<'a, const O: u8> = crate::BitWriter<'a, u32, TAMPID_SPEC, bool, O>; +#[doc = "Field `TAMPID3` reader - Tamper Input 3 Detected"] +pub type TAMPID3_R = crate::BitReader; +#[doc = "Field `TAMPID3` writer - Tamper Input 3 Detected"] +pub type TAMPID3_W<'a, const O: u8> = crate::BitWriter<'a, u32, TAMPID_SPEC, bool, O>; +#[doc = "Field `TAMPID4` reader - Tamper Input 4 Detected"] +pub type TAMPID4_R = crate::BitReader; +#[doc = "Field `TAMPID4` writer - Tamper Input 4 Detected"] +pub type TAMPID4_W<'a, const O: u8> = crate::BitWriter<'a, u32, TAMPID_SPEC, bool, O>; +#[doc = "Field `TAMPEVT` reader - Tamper Event Detected"] +pub type TAMPEVT_R = crate::BitReader; +#[doc = "Field `TAMPEVT` writer - Tamper Event Detected"] +pub type TAMPEVT_W<'a, const O: u8> = crate::BitWriter<'a, u32, TAMPID_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Tamper Input 0 Detected"] + #[inline(always)] + pub fn tampid0(&self) -> TAMPID0_R { + TAMPID0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Tamper Input 1 Detected"] + #[inline(always)] + pub fn tampid1(&self) -> TAMPID1_R { + TAMPID1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Tamper Input 2 Detected"] + #[inline(always)] + pub fn tampid2(&self) -> TAMPID2_R { + TAMPID2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Tamper Input 3 Detected"] + #[inline(always)] + pub fn tampid3(&self) -> TAMPID3_R { + TAMPID3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Tamper Input 4 Detected"] + #[inline(always)] + pub fn tampid4(&self) -> TAMPID4_R { + TAMPID4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 31 - Tamper Event Detected"] + #[inline(always)] + pub fn tampevt(&self) -> TAMPEVT_R { + TAMPEVT_R::new(((self.bits >> 31) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Tamper Input 0 Detected"] + #[inline(always)] + #[must_use] + pub fn tampid0(&mut self) -> TAMPID0_W<0> { + TAMPID0_W::new(self) + } + #[doc = "Bit 1 - Tamper Input 1 Detected"] + #[inline(always)] + #[must_use] + pub fn tampid1(&mut self) -> TAMPID1_W<1> { + TAMPID1_W::new(self) + } + #[doc = "Bit 2 - Tamper Input 2 Detected"] + #[inline(always)] + #[must_use] + pub fn tampid2(&mut self) -> TAMPID2_W<2> { + TAMPID2_W::new(self) + } + #[doc = "Bit 3 - Tamper Input 3 Detected"] + #[inline(always)] + #[must_use] + pub fn tampid3(&mut self) -> TAMPID3_W<3> { + TAMPID3_W::new(self) + } + #[doc = "Bit 4 - Tamper Input 4 Detected"] + #[inline(always)] + #[must_use] + pub fn tampid4(&mut self) -> TAMPID4_W<4> { + TAMPID4_W::new(self) + } + #[doc = "Bit 31 - Tamper Event Detected"] + #[inline(always)] + #[must_use] + pub fn tampevt(&mut self) -> TAMPEVT_W<31> { + TAMPEVT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Tamper ID\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [tampid](index.html) module"] +pub struct TAMPID_SPEC; +impl crate::RegisterSpec for TAMPID_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [tampid::R](R) reader structure"] +impl crate::Readable for TAMPID_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [tampid::W](W) writer structure"] +impl crate::Writable for TAMPID_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets TAMPID to value 0"] +impl crate::Resettable for TAMPID_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/rtc/mode2/timestamp.rs b/pac/atsaml22j/src/rtc/mode2/timestamp.rs new file mode 100644 index 000000000000..12a12b646c1b --- /dev/null +++ b/pac/atsaml22j/src/rtc/mode2/timestamp.rs @@ -0,0 +1,108 @@ +#[doc = "Register `TIMESTAMP` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SECOND` reader - Second Timestamp Value"] +pub type SECOND_R = crate::FieldReader; +#[doc = "Field `MINUTE` reader - Minute Timestamp Value"] +pub type MINUTE_R = crate::FieldReader; +#[doc = "Field `HOUR` reader - Hour Timestamp Value"] +pub type HOUR_R = crate::FieldReader; +#[doc = "Hour Timestamp Value\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum HOURSELECT_A { + #[doc = "0: AM when CLKREP in 12-hour"] + AM = 0, + #[doc = "16: PM when CLKREP in 12-hour"] + PM = 16, +} +impl From for u8 { + #[inline(always)] + fn from(variant: HOURSELECT_A) -> Self { + variant as _ + } +} +impl HOUR_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(HOURSELECT_A::AM), + 16 => Some(HOURSELECT_A::PM), + _ => None, + } + } + #[doc = "Checks if the value of the field is `AM`"] + #[inline(always)] + pub fn is_am(&self) -> bool { + *self == HOURSELECT_A::AM + } + #[doc = "Checks if the value of the field is `PM`"] + #[inline(always)] + pub fn is_pm(&self) -> bool { + *self == HOURSELECT_A::PM + } +} +#[doc = "Field `DAY` reader - Day Timestamp Value"] +pub type DAY_R = crate::FieldReader; +#[doc = "Field `MONTH` reader - Month Timestamp Value"] +pub type MONTH_R = crate::FieldReader; +#[doc = "Field `YEAR` reader - Year Timestamp Value"] +pub type YEAR_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:5 - Second Timestamp Value"] + #[inline(always)] + pub fn second(&self) -> SECOND_R { + SECOND_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:11 - Minute Timestamp Value"] + #[inline(always)] + pub fn minute(&self) -> MINUTE_R { + MINUTE_R::new(((self.bits >> 6) & 0x3f) as u8) + } + #[doc = "Bits 12:16 - Hour Timestamp Value"] + #[inline(always)] + pub fn hour(&self) -> HOUR_R { + HOUR_R::new(((self.bits >> 12) & 0x1f) as u8) + } + #[doc = "Bits 17:21 - Day Timestamp Value"] + #[inline(always)] + pub fn day(&self) -> DAY_R { + DAY_R::new(((self.bits >> 17) & 0x1f) as u8) + } + #[doc = "Bits 22:25 - Month Timestamp Value"] + #[inline(always)] + pub fn month(&self) -> MONTH_R { + MONTH_R::new(((self.bits >> 22) & 0x0f) as u8) + } + #[doc = "Bits 26:31 - Year Timestamp Value"] + #[inline(always)] + pub fn year(&self) -> YEAR_R { + YEAR_R::new(((self.bits >> 26) & 0x3f) as u8) + } +} +#[doc = "MODE2 Timestamp\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [timestamp](index.html) module"] +pub struct TIMESTAMP_SPEC; +impl crate::RegisterSpec for TIMESTAMP_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [timestamp::R](R) reader structure"] +impl crate::Readable for TIMESTAMP_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets TIMESTAMP to value 0"] +impl crate::Resettable for TIMESTAMP_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/sercom0.rs b/pac/atsaml22j/src/sercom0.rs new file mode 100644 index 000000000000..cd4d8cb2b399 --- /dev/null +++ b/pac/atsaml22j/src/sercom0.rs @@ -0,0 +1,47 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved_0_spi: [u8; 0x31], +} +impl RegisterBlock { + #[doc = "0x00..0x31 - USART Mode"] + #[inline(always)] + pub const fn usart(&self) -> &USART { + unsafe { &*(self as *const Self).cast::().add(0usize).cast() } + } + #[doc = "0x00..0x31 - SPI Mode"] + #[inline(always)] + pub const fn spi(&self) -> &SPI { + unsafe { &*(self as *const Self).cast::().add(0usize).cast() } + } + #[doc = "0x00..0x29 - I2C Slave Mode"] + #[inline(always)] + pub const fn i2cs(&self) -> &I2CS { + unsafe { &*(self as *const Self).cast::().add(0usize).cast() } + } + #[doc = "0x00..0x31 - I2C Master Mode"] + #[inline(always)] + pub const fn i2cm(&self) -> &I2CM { + unsafe { &*(self as *const Self).cast::().add(0usize).cast() } + } +} +#[doc = "I2C Master Mode"] +pub use self::i2cm::I2CM; +#[doc = r"Cluster"] +#[doc = "I2C Master Mode"] +pub mod i2cm; +#[doc = "I2C Slave Mode"] +pub use self::i2cs::I2CS; +#[doc = r"Cluster"] +#[doc = "I2C Slave Mode"] +pub mod i2cs; +#[doc = "SPI Mode"] +pub use self::spi::SPI; +#[doc = r"Cluster"] +#[doc = "SPI Mode"] +pub mod spi; +#[doc = "USART Mode"] +pub use self::usart::USART; +#[doc = r"Cluster"] +#[doc = "USART Mode"] +pub mod usart; diff --git a/pac/atsaml22j/src/sercom0/i2cm.rs b/pac/atsaml22j/src/sercom0/i2cm.rs new file mode 100644 index 000000000000..181f65512675 --- /dev/null +++ b/pac/atsaml22j/src/sercom0/i2cm.rs @@ -0,0 +1,77 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct I2CM { + #[doc = "0x00 - I2CM Control A"] + pub ctrla: CTRLA, + #[doc = "0x04 - I2CM Control B"] + pub ctrlb: CTRLB, + _reserved2: [u8; 0x04], + #[doc = "0x0c - I2CM Baud Rate"] + pub baud: BAUD, + _reserved3: [u8; 0x04], + #[doc = "0x14 - I2CM Interrupt Enable Clear"] + pub intenclr: INTENCLR, + _reserved4: [u8; 0x01], + #[doc = "0x16 - I2CM Interrupt Enable Set"] + pub intenset: INTENSET, + _reserved5: [u8; 0x01], + #[doc = "0x18 - I2CM Interrupt Flag Status and Clear"] + pub intflag: INTFLAG, + _reserved6: [u8; 0x01], + #[doc = "0x1a - I2CM Status"] + pub status: STATUS, + #[doc = "0x1c - I2CM Synchronization Busy"] + pub syncbusy: SYNCBUSY, + _reserved8: [u8; 0x04], + #[doc = "0x24 - I2CM Address"] + pub addr: ADDR, + #[doc = "0x28 - I2CM Data"] + pub data: DATA, + _reserved10: [u8; 0x07], + #[doc = "0x30 - I2CM Debug Control"] + pub dbgctrl: DBGCTRL, +} +#[doc = "CTRLA (rw) register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "I2CM Control A"] +pub mod ctrla; +#[doc = "CTRLB (rw) register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "I2CM Control B"] +pub mod ctrlb; +#[doc = "BAUD (rw) register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "I2CM Baud Rate"] +pub mod baud; +#[doc = "INTENCLR (rw) register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "I2CM Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET (rw) register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "I2CM Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG (rw) register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "I2CM Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS (rw) register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "I2CM Status"] +pub mod status; +#[doc = "SYNCBUSY (r) register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "I2CM Synchronization Busy"] +pub mod syncbusy; +#[doc = "ADDR (rw) register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "I2CM Address"] +pub mod addr; +#[doc = "DATA (rw) register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "I2CM Data"] +pub mod data; +#[doc = "DBGCTRL (rw) register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "I2CM Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsaml22j/src/sercom0/i2cm/addr.rs b/pac/atsaml22j/src/sercom0/i2cm/addr.rs new file mode 100644 index 000000000000..54d03da754fd --- /dev/null +++ b/pac/atsaml22j/src/sercom0/i2cm/addr.rs @@ -0,0 +1,140 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Address Value"] +pub type ADDR_R = crate::FieldReader; +#[doc = "Field `ADDR` writer - Address Value"] +pub type ADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ADDR_SPEC, u16, u16, 11, O>; +#[doc = "Field `LENEN` reader - Length Enable"] +pub type LENEN_R = crate::BitReader; +#[doc = "Field `LENEN` writer - Length Enable"] +pub type LENEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADDR_SPEC, bool, O>; +#[doc = "Field `HS` reader - High Speed Mode"] +pub type HS_R = crate::BitReader; +#[doc = "Field `HS` writer - High Speed Mode"] +pub type HS_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADDR_SPEC, bool, O>; +#[doc = "Field `TENBITEN` reader - Ten Bit Addressing Enable"] +pub type TENBITEN_R = crate::BitReader; +#[doc = "Field `TENBITEN` writer - Ten Bit Addressing Enable"] +pub type TENBITEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADDR_SPEC, bool, O>; +#[doc = "Field `LEN` reader - Length"] +pub type LEN_R = crate::FieldReader; +#[doc = "Field `LEN` writer - Length"] +pub type LEN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ADDR_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:10 - Address Value"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0x07ff) as u16) + } + #[doc = "Bit 13 - Length Enable"] + #[inline(always)] + pub fn lenen(&self) -> LENEN_R { + LENEN_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - High Speed Mode"] + #[inline(always)] + pub fn hs(&self) -> HS_R { + HS_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Ten Bit Addressing Enable"] + #[inline(always)] + pub fn tenbiten(&self) -> TENBITEN_R { + TENBITEN_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:23 - Length"] + #[inline(always)] + pub fn len(&self) -> LEN_R { + LEN_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:10 - Address Value"] + #[inline(always)] + #[must_use] + pub fn addr(&mut self) -> ADDR_W<0> { + ADDR_W::new(self) + } + #[doc = "Bit 13 - Length Enable"] + #[inline(always)] + #[must_use] + pub fn lenen(&mut self) -> LENEN_W<13> { + LENEN_W::new(self) + } + #[doc = "Bit 14 - High Speed Mode"] + #[inline(always)] + #[must_use] + pub fn hs(&mut self) -> HS_W<14> { + HS_W::new(self) + } + #[doc = "Bit 15 - Ten Bit Addressing Enable"] + #[inline(always)] + #[must_use] + pub fn tenbiten(&mut self) -> TENBITEN_W<15> { + TENBITEN_W::new(self) + } + #[doc = "Bits 16:23 - Length"] + #[inline(always)] + #[must_use] + pub fn len(&mut self) -> LEN_W<16> { + LEN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/sercom0/i2cm/baud.rs b/pac/atsaml22j/src/sercom0/i2cm/baud.rs new file mode 100644 index 000000000000..49369b8a9348 --- /dev/null +++ b/pac/atsaml22j/src/sercom0/i2cm/baud.rs @@ -0,0 +1,125 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub type BAUD_R = crate::FieldReader; +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub type BAUD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, BAUD_SPEC, u8, u8, 8, O>; +#[doc = "Field `BAUDLOW` reader - Baud Rate Value Low"] +pub type BAUDLOW_R = crate::FieldReader; +#[doc = "Field `BAUDLOW` writer - Baud Rate Value Low"] +pub type BAUDLOW_W<'a, const O: u8> = crate::FieldWriter<'a, u32, BAUD_SPEC, u8, u8, 8, O>; +#[doc = "Field `HSBAUD` reader - High Speed Baud Rate Value"] +pub type HSBAUD_R = crate::FieldReader; +#[doc = "Field `HSBAUD` writer - High Speed Baud Rate Value"] +pub type HSBAUD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, BAUD_SPEC, u8, u8, 8, O>; +#[doc = "Field `HSBAUDLOW` reader - High Speed Baud Rate Value Low"] +pub type HSBAUDLOW_R = crate::FieldReader; +#[doc = "Field `HSBAUDLOW` writer - High Speed Baud Rate Value Low"] +pub type HSBAUDLOW_W<'a, const O: u8> = crate::FieldWriter<'a, u32, BAUD_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 8:15 - Baud Rate Value Low"] + #[inline(always)] + pub fn baudlow(&self) -> BAUDLOW_R { + BAUDLOW_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - High Speed Baud Rate Value"] + #[inline(always)] + pub fn hsbaud(&self) -> HSBAUD_R { + HSBAUD_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - High Speed Baud Rate Value Low"] + #[inline(always)] + pub fn hsbaudlow(&self) -> HSBAUDLOW_R { + HSBAUDLOW_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + #[must_use] + pub fn baud(&mut self) -> BAUD_W<0> { + BAUD_W::new(self) + } + #[doc = "Bits 8:15 - Baud Rate Value Low"] + #[inline(always)] + #[must_use] + pub fn baudlow(&mut self) -> BAUDLOW_W<8> { + BAUDLOW_W::new(self) + } + #[doc = "Bits 16:23 - High Speed Baud Rate Value"] + #[inline(always)] + #[must_use] + pub fn hsbaud(&mut self) -> HSBAUD_W<16> { + HSBAUD_W::new(self) + } + #[doc = "Bits 24:31 - High Speed Baud Rate Value Low"] + #[inline(always)] + #[must_use] + pub fn hsbaudlow(&mut self) -> HSBAUDLOW_W<24> { + HSBAUDLOW_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/sercom0/i2cm/ctrla.rs b/pac/atsaml22j/src/sercom0/i2cm/ctrla.rs new file mode 100644 index 000000000000..5a8aa8d52036 --- /dev/null +++ b/pac/atsaml22j/src/sercom0/i2cm/ctrla.rs @@ -0,0 +1,245 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub type SWRST_R = crate::BitReader; +#[doc = "Field `SWRST` writer - Software Reset"] +pub type SWRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `ENABLE` reader - Enable"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - Enable"] +pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `MODE` reader - Operating Mode"] +pub type MODE_R = crate::FieldReader; +#[doc = "Field `MODE` writer - Operating Mode"] +pub type MODE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRLA_SPEC, u8, u8, 3, O>; +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub type RUNSTDBY_R = crate::BitReader; +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub type RUNSTDBY_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `PINOUT` reader - Pin Usage"] +pub type PINOUT_R = crate::BitReader; +#[doc = "Field `PINOUT` writer - Pin Usage"] +pub type PINOUT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `SDAHOLD` reader - SDA Hold Time"] +pub type SDAHOLD_R = crate::FieldReader; +#[doc = "Field `SDAHOLD` writer - SDA Hold Time"] +pub type SDAHOLD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRLA_SPEC, u8, u8, 2, O>; +#[doc = "Field `MEXTTOEN` reader - Master SCL Low Extend Timeout"] +pub type MEXTTOEN_R = crate::BitReader; +#[doc = "Field `MEXTTOEN` writer - Master SCL Low Extend Timeout"] +pub type MEXTTOEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `SEXTTOEN` reader - Slave SCL Low Extend Timeout"] +pub type SEXTTOEN_R = crate::BitReader; +#[doc = "Field `SEXTTOEN` writer - Slave SCL Low Extend Timeout"] +pub type SEXTTOEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `SPEED` reader - Transfer Speed"] +pub type SPEED_R = crate::FieldReader; +#[doc = "Field `SPEED` writer - Transfer Speed"] +pub type SPEED_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRLA_SPEC, u8, u8, 2, O>; +#[doc = "Field `SCLSM` reader - SCL Clock Stretch Mode"] +pub type SCLSM_R = crate::BitReader; +#[doc = "Field `SCLSM` writer - SCL Clock Stretch Mode"] +pub type SCLSM_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `INACTOUT` reader - Inactive Time-Out"] +pub type INACTOUT_R = crate::FieldReader; +#[doc = "Field `INACTOUT` writer - Inactive Time-Out"] +pub type INACTOUT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRLA_SPEC, u8, u8, 2, O>; +#[doc = "Field `LOWTOUTEN` reader - SCL Low Timeout Enable"] +pub type LOWTOUTEN_R = crate::BitReader; +#[doc = "Field `LOWTOUTEN` writer - SCL Low Timeout Enable"] +pub type LOWTOUTEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 7) as u8) + } + #[doc = "Bit 7 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 16 - Pin Usage"] + #[inline(always)] + pub fn pinout(&self) -> PINOUT_R { + PINOUT_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bits 20:21 - SDA Hold Time"] + #[inline(always)] + pub fn sdahold(&self) -> SDAHOLD_R { + SDAHOLD_R::new(((self.bits >> 20) & 3) as u8) + } + #[doc = "Bit 22 - Master SCL Low Extend Timeout"] + #[inline(always)] + pub fn mexttoen(&self) -> MEXTTOEN_R { + MEXTTOEN_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttoen(&self) -> SEXTTOEN_R { + SEXTTOEN_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bits 24:25 - Transfer Speed"] + #[inline(always)] + pub fn speed(&self) -> SPEED_R { + SPEED_R::new(((self.bits >> 24) & 3) as u8) + } + #[doc = "Bit 27 - SCL Clock Stretch Mode"] + #[inline(always)] + pub fn sclsm(&self) -> SCLSM_R { + SCLSM_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bits 28:29 - Inactive Time-Out"] + #[inline(always)] + pub fn inactout(&self) -> INACTOUT_R { + INACTOUT_R::new(((self.bits >> 28) & 3) as u8) + } + #[doc = "Bit 30 - SCL Low Timeout Enable"] + #[inline(always)] + pub fn lowtouten(&self) -> LOWTOUTEN_R { + LOWTOUTEN_R::new(((self.bits >> 30) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + #[must_use] + pub fn swrst(&mut self) -> SWRST_W<0> { + SWRST_W::new(self) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W<1> { + ENABLE_W::new(self) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> MODE_W<2> { + MODE_W::new(self) + } + #[doc = "Bit 7 - Run in Standby"] + #[inline(always)] + #[must_use] + pub fn runstdby(&mut self) -> RUNSTDBY_W<7> { + RUNSTDBY_W::new(self) + } + #[doc = "Bit 16 - Pin Usage"] + #[inline(always)] + #[must_use] + pub fn pinout(&mut self) -> PINOUT_W<16> { + PINOUT_W::new(self) + } + #[doc = "Bits 20:21 - SDA Hold Time"] + #[inline(always)] + #[must_use] + pub fn sdahold(&mut self) -> SDAHOLD_W<20> { + SDAHOLD_W::new(self) + } + #[doc = "Bit 22 - Master SCL Low Extend Timeout"] + #[inline(always)] + #[must_use] + pub fn mexttoen(&mut self) -> MEXTTOEN_W<22> { + MEXTTOEN_W::new(self) + } + #[doc = "Bit 23 - Slave SCL Low Extend Timeout"] + #[inline(always)] + #[must_use] + pub fn sexttoen(&mut self) -> SEXTTOEN_W<23> { + SEXTTOEN_W::new(self) + } + #[doc = "Bits 24:25 - Transfer Speed"] + #[inline(always)] + #[must_use] + pub fn speed(&mut self) -> SPEED_W<24> { + SPEED_W::new(self) + } + #[doc = "Bit 27 - SCL Clock Stretch Mode"] + #[inline(always)] + #[must_use] + pub fn sclsm(&mut self) -> SCLSM_W<27> { + SCLSM_W::new(self) + } + #[doc = "Bits 28:29 - Inactive Time-Out"] + #[inline(always)] + #[must_use] + pub fn inactout(&mut self) -> INACTOUT_W<28> { + INACTOUT_W::new(self) + } + #[doc = "Bit 30 - SCL Low Timeout Enable"] + #[inline(always)] + #[must_use] + pub fn lowtouten(&mut self) -> LOWTOUTEN_W<30> { + LOWTOUTEN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/sercom0/i2cm/ctrlb.rs b/pac/atsaml22j/src/sercom0/i2cm/ctrlb.rs new file mode 100644 index 000000000000..01c6c7176733 --- /dev/null +++ b/pac/atsaml22j/src/sercom0/i2cm/ctrlb.rs @@ -0,0 +1,118 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SMEN` reader - Smart Mode Enable"] +pub type SMEN_R = crate::BitReader; +#[doc = "Field `SMEN` writer - Smart Mode Enable"] +pub type SMEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLB_SPEC, bool, O>; +#[doc = "Field `QCEN` reader - Quick Command Enable"] +pub type QCEN_R = crate::BitReader; +#[doc = "Field `QCEN` writer - Quick Command Enable"] +pub type QCEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLB_SPEC, bool, O>; +#[doc = "Field `CMD` writer - Command"] +pub type CMD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRLB_SPEC, u8, u8, 2, O>; +#[doc = "Field `ACKACT` reader - Acknowledge Action"] +pub type ACKACT_R = crate::BitReader; +#[doc = "Field `ACKACT` writer - Acknowledge Action"] +pub type ACKACT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLB_SPEC, bool, O>; +impl R { + #[doc = "Bit 8 - Smart Mode Enable"] + #[inline(always)] + pub fn smen(&self) -> SMEN_R { + SMEN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Quick Command Enable"] + #[inline(always)] + pub fn qcen(&self) -> QCEN_R { + QCEN_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 18 - Acknowledge Action"] + #[inline(always)] + pub fn ackact(&self) -> ACKACT_R { + ACKACT_R::new(((self.bits >> 18) & 1) != 0) + } +} +impl W { + #[doc = "Bit 8 - Smart Mode Enable"] + #[inline(always)] + #[must_use] + pub fn smen(&mut self) -> SMEN_W<8> { + SMEN_W::new(self) + } + #[doc = "Bit 9 - Quick Command Enable"] + #[inline(always)] + #[must_use] + pub fn qcen(&mut self) -> QCEN_W<9> { + QCEN_W::new(self) + } + #[doc = "Bits 16:17 - Command"] + #[inline(always)] + #[must_use] + pub fn cmd(&mut self) -> CMD_W<16> { + CMD_W::new(self) + } + #[doc = "Bit 18 - Acknowledge Action"] + #[inline(always)] + #[must_use] + pub fn ackact(&mut self) -> ACKACT_W<18> { + ACKACT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/sercom0/i2cm/data.rs b/pac/atsaml22j/src/sercom0/i2cm/data.rs new file mode 100644 index 000000000000..585cba7a8689 --- /dev/null +++ b/pac/atsaml22j/src/sercom0/i2cm/data.rs @@ -0,0 +1,80 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub type DATA_R = crate::FieldReader; +#[doc = "Field `DATA` writer - Data Value"] +pub type DATA_W<'a, const O: u8> = crate::FieldWriter<'a, u8, DATA_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:7 - Data Value"] + #[inline(always)] + #[must_use] + pub fn data(&mut self) -> DATA_W<0> { + DATA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/sercom0/i2cm/dbgctrl.rs b/pac/atsaml22j/src/sercom0/i2cm/dbgctrl.rs new file mode 100644 index 000000000000..667598de0b76 --- /dev/null +++ b/pac/atsaml22j/src/sercom0/i2cm/dbgctrl.rs @@ -0,0 +1,80 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub type DBGSTOP_R = crate::BitReader; +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub type DBGSTOP_W<'a, const O: u8> = crate::BitWriter<'a, u8, DBGCTRL_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + #[must_use] + pub fn dbgstop(&mut self) -> DBGSTOP_W<0> { + DBGSTOP_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/sercom0/i2cm/intenclr.rs b/pac/atsaml22j/src/sercom0/i2cm/intenclr.rs new file mode 100644 index 000000000000..594c011fa3a9 --- /dev/null +++ b/pac/atsaml22j/src/sercom0/i2cm/intenclr.rs @@ -0,0 +1,110 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MB` reader - Master On Bus Interrupt Disable"] +pub type MB_R = crate::BitReader; +#[doc = "Field `MB` writer - Master On Bus Interrupt Disable"] +pub type MB_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>; +#[doc = "Field `SB` reader - Slave On Bus Interrupt Disable"] +pub type SB_R = crate::BitReader; +#[doc = "Field `SB` writer - Slave On Bus Interrupt Disable"] +pub type SB_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>; +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub type ERROR_R = crate::BitReader; +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub type ERROR_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Master On Bus Interrupt Disable"] + #[inline(always)] + pub fn mb(&self) -> MB_R { + MB_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Slave On Bus Interrupt Disable"] + #[inline(always)] + pub fn sb(&self) -> SB_R { + SB_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Master On Bus Interrupt Disable"] + #[inline(always)] + #[must_use] + pub fn mb(&mut self) -> MB_W<0> { + MB_W::new(self) + } + #[doc = "Bit 1 - Slave On Bus Interrupt Disable"] + #[inline(always)] + #[must_use] + pub fn sb(&mut self) -> SB_W<1> { + SB_W::new(self) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + #[must_use] + pub fn error(&mut self) -> ERROR_W<7> { + ERROR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/sercom0/i2cm/intenset.rs b/pac/atsaml22j/src/sercom0/i2cm/intenset.rs new file mode 100644 index 000000000000..269473075409 --- /dev/null +++ b/pac/atsaml22j/src/sercom0/i2cm/intenset.rs @@ -0,0 +1,110 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MB` reader - Master On Bus Interrupt Enable"] +pub type MB_R = crate::BitReader; +#[doc = "Field `MB` writer - Master On Bus Interrupt Enable"] +pub type MB_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENSET_SPEC, bool, O>; +#[doc = "Field `SB` reader - Slave On Bus Interrupt Enable"] +pub type SB_R = crate::BitReader; +#[doc = "Field `SB` writer - Slave On Bus Interrupt Enable"] +pub type SB_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENSET_SPEC, bool, O>; +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub type ERROR_R = crate::BitReader; +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub type ERROR_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENSET_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Master On Bus Interrupt Enable"] + #[inline(always)] + pub fn mb(&self) -> MB_R { + MB_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Slave On Bus Interrupt Enable"] + #[inline(always)] + pub fn sb(&self) -> SB_R { + SB_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Master On Bus Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn mb(&mut self) -> MB_W<0> { + MB_W::new(self) + } + #[doc = "Bit 1 - Slave On Bus Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn sb(&mut self) -> SB_W<1> { + SB_W::new(self) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn error(&mut self) -> ERROR_W<7> { + ERROR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/sercom0/i2cm/intflag.rs b/pac/atsaml22j/src/sercom0/i2cm/intflag.rs new file mode 100644 index 000000000000..6d3c2fb0b544 --- /dev/null +++ b/pac/atsaml22j/src/sercom0/i2cm/intflag.rs @@ -0,0 +1,110 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MB` reader - Master On Bus Interrupt"] +pub type MB_R = crate::BitReader; +#[doc = "Field `MB` writer - Master On Bus Interrupt"] +pub type MB_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTFLAG_SPEC, bool, O>; +#[doc = "Field `SB` reader - Slave On Bus Interrupt"] +pub type SB_R = crate::BitReader; +#[doc = "Field `SB` writer - Slave On Bus Interrupt"] +pub type SB_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTFLAG_SPEC, bool, O>; +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub type ERROR_R = crate::BitReader; +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub type ERROR_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTFLAG_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Master On Bus Interrupt"] + #[inline(always)] + pub fn mb(&self) -> MB_R { + MB_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Slave On Bus Interrupt"] + #[inline(always)] + pub fn sb(&self) -> SB_R { + SB_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Master On Bus Interrupt"] + #[inline(always)] + #[must_use] + pub fn mb(&mut self) -> MB_W<0> { + MB_W::new(self) + } + #[doc = "Bit 1 - Slave On Bus Interrupt"] + #[inline(always)] + #[must_use] + pub fn sb(&mut self) -> SB_W<1> { + SB_W::new(self) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + #[must_use] + pub fn error(&mut self) -> ERROR_W<7> { + ERROR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/sercom0/i2cm/status.rs b/pac/atsaml22j/src/sercom0/i2cm/status.rs new file mode 100644 index 000000000000..723f1d283f3a --- /dev/null +++ b/pac/atsaml22j/src/sercom0/i2cm/status.rs @@ -0,0 +1,184 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUSERR` reader - Bus Error"] +pub type BUSERR_R = crate::BitReader; +#[doc = "Field `BUSERR` writer - Bus Error"] +pub type BUSERR_W<'a, const O: u8> = crate::BitWriter<'a, u16, STATUS_SPEC, bool, O>; +#[doc = "Field `ARBLOST` reader - Arbitration Lost"] +pub type ARBLOST_R = crate::BitReader; +#[doc = "Field `ARBLOST` writer - Arbitration Lost"] +pub type ARBLOST_W<'a, const O: u8> = crate::BitWriter<'a, u16, STATUS_SPEC, bool, O>; +#[doc = "Field `RXNACK` reader - Received Not Acknowledge"] +pub type RXNACK_R = crate::BitReader; +#[doc = "Field `BUSSTATE` reader - Bus State"] +pub type BUSSTATE_R = crate::FieldReader; +#[doc = "Field `BUSSTATE` writer - Bus State"] +pub type BUSSTATE_W<'a, const O: u8> = crate::FieldWriter<'a, u16, STATUS_SPEC, u8, u8, 2, O>; +#[doc = "Field `LOWTOUT` reader - SCL Low Timeout"] +pub type LOWTOUT_R = crate::BitReader; +#[doc = "Field `LOWTOUT` writer - SCL Low Timeout"] +pub type LOWTOUT_W<'a, const O: u8> = crate::BitWriter<'a, u16, STATUS_SPEC, bool, O>; +#[doc = "Field `CLKHOLD` reader - Clock Hold"] +pub type CLKHOLD_R = crate::BitReader; +#[doc = "Field `MEXTTOUT` reader - Master SCL Low Extend Timeout"] +pub type MEXTTOUT_R = crate::BitReader; +#[doc = "Field `MEXTTOUT` writer - Master SCL Low Extend Timeout"] +pub type MEXTTOUT_W<'a, const O: u8> = crate::BitWriter<'a, u16, STATUS_SPEC, bool, O>; +#[doc = "Field `SEXTTOUT` reader - Slave SCL Low Extend Timeout"] +pub type SEXTTOUT_R = crate::BitReader; +#[doc = "Field `SEXTTOUT` writer - Slave SCL Low Extend Timeout"] +pub type SEXTTOUT_W<'a, const O: u8> = crate::BitWriter<'a, u16, STATUS_SPEC, bool, O>; +#[doc = "Field `LENERR` reader - Length Error"] +pub type LENERR_R = crate::BitReader; +#[doc = "Field `LENERR` writer - Length Error"] +pub type LENERR_W<'a, const O: u8> = crate::BitWriter<'a, u16, STATUS_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Bus Error"] + #[inline(always)] + pub fn buserr(&self) -> BUSERR_R { + BUSERR_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Arbitration Lost"] + #[inline(always)] + pub fn arblost(&self) -> ARBLOST_R { + ARBLOST_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Received Not Acknowledge"] + #[inline(always)] + pub fn rxnack(&self) -> RXNACK_R { + RXNACK_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 4:5 - Bus State"] + #[inline(always)] + pub fn busstate(&self) -> BUSSTATE_R { + BUSSTATE_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 6 - SCL Low Timeout"] + #[inline(always)] + pub fn lowtout(&self) -> LOWTOUT_R { + LOWTOUT_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Clock Hold"] + #[inline(always)] + pub fn clkhold(&self) -> CLKHOLD_R { + CLKHOLD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Master SCL Low Extend Timeout"] + #[inline(always)] + pub fn mexttout(&self) -> MEXTTOUT_R { + MEXTTOUT_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttout(&self) -> SEXTTOUT_R { + SEXTTOUT_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Length Error"] + #[inline(always)] + pub fn lenerr(&self) -> LENERR_R { + LENERR_R::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Bus Error"] + #[inline(always)] + #[must_use] + pub fn buserr(&mut self) -> BUSERR_W<0> { + BUSERR_W::new(self) + } + #[doc = "Bit 1 - Arbitration Lost"] + #[inline(always)] + #[must_use] + pub fn arblost(&mut self) -> ARBLOST_W<1> { + ARBLOST_W::new(self) + } + #[doc = "Bits 4:5 - Bus State"] + #[inline(always)] + #[must_use] + pub fn busstate(&mut self) -> BUSSTATE_W<4> { + BUSSTATE_W::new(self) + } + #[doc = "Bit 6 - SCL Low Timeout"] + #[inline(always)] + #[must_use] + pub fn lowtout(&mut self) -> LOWTOUT_W<6> { + LOWTOUT_W::new(self) + } + #[doc = "Bit 8 - Master SCL Low Extend Timeout"] + #[inline(always)] + #[must_use] + pub fn mexttout(&mut self) -> MEXTTOUT_W<8> { + MEXTTOUT_W::new(self) + } + #[doc = "Bit 9 - Slave SCL Low Extend Timeout"] + #[inline(always)] + #[must_use] + pub fn sexttout(&mut self) -> SEXTTOUT_W<9> { + SEXTTOUT_W::new(self) + } + #[doc = "Bit 10 - Length Error"] + #[inline(always)] + #[must_use] + pub fn lenerr(&mut self) -> LENERR_W<10> { + LENERR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CM Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/sercom0/i2cm/syncbusy.rs b/pac/atsaml22j/src/sercom0/i2cm/syncbusy.rs new file mode 100644 index 000000000000..f595b27dee97 --- /dev/null +++ b/pac/atsaml22j/src/sercom0/i2cm/syncbusy.rs @@ -0,0 +1,51 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub type SWRST_R = crate::BitReader; +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `SYSOP` reader - System Operation Synchronization Busy"] +pub type SYSOP_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - System Operation Synchronization Busy"] + #[inline(always)] + pub fn sysop(&self) -> SYSOP_R { + SYSOP_R::new(((self.bits >> 2) & 1) != 0) + } +} +#[doc = "I2CM Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/sercom0/i2cs.rs b/pac/atsaml22j/src/sercom0/i2cs.rs new file mode 100644 index 000000000000..6c9d3a7a1569 --- /dev/null +++ b/pac/atsaml22j/src/sercom0/i2cs.rs @@ -0,0 +1,63 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct I2CS { + #[doc = "0x00 - I2CS Control A"] + pub ctrla: CTRLA, + #[doc = "0x04 - I2CS Control B"] + pub ctrlb: CTRLB, + _reserved2: [u8; 0x0c], + #[doc = "0x14 - I2CS Interrupt Enable Clear"] + pub intenclr: INTENCLR, + _reserved3: [u8; 0x01], + #[doc = "0x16 - I2CS Interrupt Enable Set"] + pub intenset: INTENSET, + _reserved4: [u8; 0x01], + #[doc = "0x18 - I2CS Interrupt Flag Status and Clear"] + pub intflag: INTFLAG, + _reserved5: [u8; 0x01], + #[doc = "0x1a - I2CS Status"] + pub status: STATUS, + #[doc = "0x1c - I2CS Synchronization Busy"] + pub syncbusy: SYNCBUSY, + _reserved7: [u8; 0x04], + #[doc = "0x24 - I2CS Address"] + pub addr: ADDR, + #[doc = "0x28 - I2CS Data"] + pub data: DATA, +} +#[doc = "CTRLA (rw) register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "I2CS Control A"] +pub mod ctrla; +#[doc = "CTRLB (rw) register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "I2CS Control B"] +pub mod ctrlb; +#[doc = "INTENCLR (rw) register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "I2CS Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET (rw) register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "I2CS Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG (rw) register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "I2CS Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS (rw) register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "I2CS Status"] +pub mod status; +#[doc = "SYNCBUSY (r) register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "I2CS Synchronization Busy"] +pub mod syncbusy; +#[doc = "ADDR (rw) register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "I2CS Address"] +pub mod addr; +#[doc = "DATA (rw) register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "I2CS Data"] +pub mod data; diff --git a/pac/atsaml22j/src/sercom0/i2cs/addr.rs b/pac/atsaml22j/src/sercom0/i2cs/addr.rs new file mode 100644 index 000000000000..7abd0ae2217e --- /dev/null +++ b/pac/atsaml22j/src/sercom0/i2cs/addr.rs @@ -0,0 +1,125 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GENCEN` reader - General Call Address Enable"] +pub type GENCEN_R = crate::BitReader; +#[doc = "Field `GENCEN` writer - General Call Address Enable"] +pub type GENCEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADDR_SPEC, bool, O>; +#[doc = "Field `ADDR` reader - Address Value"] +pub type ADDR_R = crate::FieldReader; +#[doc = "Field `ADDR` writer - Address Value"] +pub type ADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ADDR_SPEC, u16, u16, 10, O>; +#[doc = "Field `TENBITEN` reader - Ten Bit Addressing Enable"] +pub type TENBITEN_R = crate::BitReader; +#[doc = "Field `TENBITEN` writer - Ten Bit Addressing Enable"] +pub type TENBITEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADDR_SPEC, bool, O>; +#[doc = "Field `ADDRMASK` reader - Address Mask"] +pub type ADDRMASK_R = crate::FieldReader; +#[doc = "Field `ADDRMASK` writer - Address Mask"] +pub type ADDRMASK_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ADDR_SPEC, u16, u16, 10, O>; +impl R { + #[doc = "Bit 0 - General Call Address Enable"] + #[inline(always)] + pub fn gencen(&self) -> GENCEN_R { + GENCEN_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:10 - Address Value"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new(((self.bits >> 1) & 0x03ff) as u16) + } + #[doc = "Bit 15 - Ten Bit Addressing Enable"] + #[inline(always)] + pub fn tenbiten(&self) -> TENBITEN_R { + TENBITEN_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 17:26 - Address Mask"] + #[inline(always)] + pub fn addrmask(&self) -> ADDRMASK_R { + ADDRMASK_R::new(((self.bits >> 17) & 0x03ff) as u16) + } +} +impl W { + #[doc = "Bit 0 - General Call Address Enable"] + #[inline(always)] + #[must_use] + pub fn gencen(&mut self) -> GENCEN_W<0> { + GENCEN_W::new(self) + } + #[doc = "Bits 1:10 - Address Value"] + #[inline(always)] + #[must_use] + pub fn addr(&mut self) -> ADDR_W<1> { + ADDR_W::new(self) + } + #[doc = "Bit 15 - Ten Bit Addressing Enable"] + #[inline(always)] + #[must_use] + pub fn tenbiten(&mut self) -> TENBITEN_W<15> { + TENBITEN_W::new(self) + } + #[doc = "Bits 17:26 - Address Mask"] + #[inline(always)] + #[must_use] + pub fn addrmask(&mut self) -> ADDRMASK_W<17> { + ADDRMASK_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/sercom0/i2cs/ctrla.rs b/pac/atsaml22j/src/sercom0/i2cs/ctrla.rs new file mode 100644 index 000000000000..9e14c0dc2978 --- /dev/null +++ b/pac/atsaml22j/src/sercom0/i2cs/ctrla.rs @@ -0,0 +1,215 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub type SWRST_R = crate::BitReader; +#[doc = "Field `SWRST` writer - Software Reset"] +pub type SWRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `ENABLE` reader - Enable"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - Enable"] +pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `MODE` reader - Operating Mode"] +pub type MODE_R = crate::FieldReader; +#[doc = "Field `MODE` writer - Operating Mode"] +pub type MODE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRLA_SPEC, u8, u8, 3, O>; +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub type RUNSTDBY_R = crate::BitReader; +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub type RUNSTDBY_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `PINOUT` reader - Pin Usage"] +pub type PINOUT_R = crate::BitReader; +#[doc = "Field `PINOUT` writer - Pin Usage"] +pub type PINOUT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `SDAHOLD` reader - SDA Hold Time"] +pub type SDAHOLD_R = crate::FieldReader; +#[doc = "Field `SDAHOLD` writer - SDA Hold Time"] +pub type SDAHOLD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRLA_SPEC, u8, u8, 2, O>; +#[doc = "Field `SEXTTOEN` reader - Slave SCL Low Extend Timeout"] +pub type SEXTTOEN_R = crate::BitReader; +#[doc = "Field `SEXTTOEN` writer - Slave SCL Low Extend Timeout"] +pub type SEXTTOEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `SPEED` reader - Transfer Speed"] +pub type SPEED_R = crate::FieldReader; +#[doc = "Field `SPEED` writer - Transfer Speed"] +pub type SPEED_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRLA_SPEC, u8, u8, 2, O>; +#[doc = "Field `SCLSM` reader - SCL Clock Stretch Mode"] +pub type SCLSM_R = crate::BitReader; +#[doc = "Field `SCLSM` writer - SCL Clock Stretch Mode"] +pub type SCLSM_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `LOWTOUTEN` reader - SCL Low Timeout Enable"] +pub type LOWTOUTEN_R = crate::BitReader; +#[doc = "Field `LOWTOUTEN` writer - SCL Low Timeout Enable"] +pub type LOWTOUTEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 7) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 16 - Pin Usage"] + #[inline(always)] + pub fn pinout(&self) -> PINOUT_R { + PINOUT_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bits 20:21 - SDA Hold Time"] + #[inline(always)] + pub fn sdahold(&self) -> SDAHOLD_R { + SDAHOLD_R::new(((self.bits >> 20) & 3) as u8) + } + #[doc = "Bit 23 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttoen(&self) -> SEXTTOEN_R { + SEXTTOEN_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bits 24:25 - Transfer Speed"] + #[inline(always)] + pub fn speed(&self) -> SPEED_R { + SPEED_R::new(((self.bits >> 24) & 3) as u8) + } + #[doc = "Bit 27 - SCL Clock Stretch Mode"] + #[inline(always)] + pub fn sclsm(&self) -> SCLSM_R { + SCLSM_R::new(((self.bits >> 27) & 1) != 0) + } + #[doc = "Bit 30 - SCL Low Timeout Enable"] + #[inline(always)] + pub fn lowtouten(&self) -> LOWTOUTEN_R { + LOWTOUTEN_R::new(((self.bits >> 30) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + #[must_use] + pub fn swrst(&mut self) -> SWRST_W<0> { + SWRST_W::new(self) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W<1> { + ENABLE_W::new(self) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> MODE_W<2> { + MODE_W::new(self) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + #[must_use] + pub fn runstdby(&mut self) -> RUNSTDBY_W<7> { + RUNSTDBY_W::new(self) + } + #[doc = "Bit 16 - Pin Usage"] + #[inline(always)] + #[must_use] + pub fn pinout(&mut self) -> PINOUT_W<16> { + PINOUT_W::new(self) + } + #[doc = "Bits 20:21 - SDA Hold Time"] + #[inline(always)] + #[must_use] + pub fn sdahold(&mut self) -> SDAHOLD_W<20> { + SDAHOLD_W::new(self) + } + #[doc = "Bit 23 - Slave SCL Low Extend Timeout"] + #[inline(always)] + #[must_use] + pub fn sexttoen(&mut self) -> SEXTTOEN_W<23> { + SEXTTOEN_W::new(self) + } + #[doc = "Bits 24:25 - Transfer Speed"] + #[inline(always)] + #[must_use] + pub fn speed(&mut self) -> SPEED_W<24> { + SPEED_W::new(self) + } + #[doc = "Bit 27 - SCL Clock Stretch Mode"] + #[inline(always)] + #[must_use] + pub fn sclsm(&mut self) -> SCLSM_W<27> { + SCLSM_W::new(self) + } + #[doc = "Bit 30 - SCL Low Timeout Enable"] + #[inline(always)] + #[must_use] + pub fn lowtouten(&mut self) -> LOWTOUTEN_W<30> { + LOWTOUTEN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/sercom0/i2cs/ctrlb.rs b/pac/atsaml22j/src/sercom0/i2cs/ctrlb.rs new file mode 100644 index 000000000000..b1c6a5ffdcb9 --- /dev/null +++ b/pac/atsaml22j/src/sercom0/i2cs/ctrlb.rs @@ -0,0 +1,148 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SMEN` reader - Smart Mode Enable"] +pub type SMEN_R = crate::BitReader; +#[doc = "Field `SMEN` writer - Smart Mode Enable"] +pub type SMEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLB_SPEC, bool, O>; +#[doc = "Field `GCMD` reader - PMBus Group Command"] +pub type GCMD_R = crate::BitReader; +#[doc = "Field `GCMD` writer - PMBus Group Command"] +pub type GCMD_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLB_SPEC, bool, O>; +#[doc = "Field `AACKEN` reader - Automatic Address Acknowledge"] +pub type AACKEN_R = crate::BitReader; +#[doc = "Field `AACKEN` writer - Automatic Address Acknowledge"] +pub type AACKEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLB_SPEC, bool, O>; +#[doc = "Field `AMODE` reader - Address Mode"] +pub type AMODE_R = crate::FieldReader; +#[doc = "Field `AMODE` writer - Address Mode"] +pub type AMODE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRLB_SPEC, u8, u8, 2, O>; +#[doc = "Field `CMD` writer - Command"] +pub type CMD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRLB_SPEC, u8, u8, 2, O>; +#[doc = "Field `ACKACT` reader - Acknowledge Action"] +pub type ACKACT_R = crate::BitReader; +#[doc = "Field `ACKACT` writer - Acknowledge Action"] +pub type ACKACT_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLB_SPEC, bool, O>; +impl R { + #[doc = "Bit 8 - Smart Mode Enable"] + #[inline(always)] + pub fn smen(&self) -> SMEN_R { + SMEN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - PMBus Group Command"] + #[inline(always)] + pub fn gcmd(&self) -> GCMD_R { + GCMD_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Automatic Address Acknowledge"] + #[inline(always)] + pub fn aacken(&self) -> AACKEN_R { + AACKEN_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&self) -> AMODE_R { + AMODE_R::new(((self.bits >> 14) & 3) as u8) + } + #[doc = "Bit 18 - Acknowledge Action"] + #[inline(always)] + pub fn ackact(&self) -> ACKACT_R { + ACKACT_R::new(((self.bits >> 18) & 1) != 0) + } +} +impl W { + #[doc = "Bit 8 - Smart Mode Enable"] + #[inline(always)] + #[must_use] + pub fn smen(&mut self) -> SMEN_W<8> { + SMEN_W::new(self) + } + #[doc = "Bit 9 - PMBus Group Command"] + #[inline(always)] + #[must_use] + pub fn gcmd(&mut self) -> GCMD_W<9> { + GCMD_W::new(self) + } + #[doc = "Bit 10 - Automatic Address Acknowledge"] + #[inline(always)] + #[must_use] + pub fn aacken(&mut self) -> AACKEN_W<10> { + AACKEN_W::new(self) + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + #[must_use] + pub fn amode(&mut self) -> AMODE_W<14> { + AMODE_W::new(self) + } + #[doc = "Bits 16:17 - Command"] + #[inline(always)] + #[must_use] + pub fn cmd(&mut self) -> CMD_W<16> { + CMD_W::new(self) + } + #[doc = "Bit 18 - Acknowledge Action"] + #[inline(always)] + #[must_use] + pub fn ackact(&mut self) -> ACKACT_W<18> { + ACKACT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/sercom0/i2cs/data.rs b/pac/atsaml22j/src/sercom0/i2cs/data.rs new file mode 100644 index 000000000000..c0a9912691f3 --- /dev/null +++ b/pac/atsaml22j/src/sercom0/i2cs/data.rs @@ -0,0 +1,80 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub type DATA_R = crate::FieldReader; +#[doc = "Field `DATA` writer - Data Value"] +pub type DATA_W<'a, const O: u8> = crate::FieldWriter<'a, u8, DATA_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:7 - Data Value"] + #[inline(always)] + #[must_use] + pub fn data(&mut self) -> DATA_W<0> { + DATA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/sercom0/i2cs/intenclr.rs b/pac/atsaml22j/src/sercom0/i2cs/intenclr.rs new file mode 100644 index 000000000000..ccb3c04be18d --- /dev/null +++ b/pac/atsaml22j/src/sercom0/i2cs/intenclr.rs @@ -0,0 +1,125 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PREC` reader - Stop Received Interrupt Disable"] +pub type PREC_R = crate::BitReader; +#[doc = "Field `PREC` writer - Stop Received Interrupt Disable"] +pub type PREC_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>; +#[doc = "Field `AMATCH` reader - Address Match Interrupt Disable"] +pub type AMATCH_R = crate::BitReader; +#[doc = "Field `AMATCH` writer - Address Match Interrupt Disable"] +pub type AMATCH_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>; +#[doc = "Field `DRDY` reader - Data Interrupt Disable"] +pub type DRDY_R = crate::BitReader; +#[doc = "Field `DRDY` writer - Data Interrupt Disable"] +pub type DRDY_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>; +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub type ERROR_R = crate::BitReader; +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub type ERROR_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Stop Received Interrupt Disable"] + #[inline(always)] + pub fn prec(&self) -> PREC_R { + PREC_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Address Match Interrupt Disable"] + #[inline(always)] + pub fn amatch(&self) -> AMATCH_R { + AMATCH_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Data Interrupt Disable"] + #[inline(always)] + pub fn drdy(&self) -> DRDY_R { + DRDY_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Received Interrupt Disable"] + #[inline(always)] + #[must_use] + pub fn prec(&mut self) -> PREC_W<0> { + PREC_W::new(self) + } + #[doc = "Bit 1 - Address Match Interrupt Disable"] + #[inline(always)] + #[must_use] + pub fn amatch(&mut self) -> AMATCH_W<1> { + AMATCH_W::new(self) + } + #[doc = "Bit 2 - Data Interrupt Disable"] + #[inline(always)] + #[must_use] + pub fn drdy(&mut self) -> DRDY_W<2> { + DRDY_W::new(self) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + #[must_use] + pub fn error(&mut self) -> ERROR_W<7> { + ERROR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/sercom0/i2cs/intenset.rs b/pac/atsaml22j/src/sercom0/i2cs/intenset.rs new file mode 100644 index 000000000000..33f304be4552 --- /dev/null +++ b/pac/atsaml22j/src/sercom0/i2cs/intenset.rs @@ -0,0 +1,125 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PREC` reader - Stop Received Interrupt Enable"] +pub type PREC_R = crate::BitReader; +#[doc = "Field `PREC` writer - Stop Received Interrupt Enable"] +pub type PREC_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENSET_SPEC, bool, O>; +#[doc = "Field `AMATCH` reader - Address Match Interrupt Enable"] +pub type AMATCH_R = crate::BitReader; +#[doc = "Field `AMATCH` writer - Address Match Interrupt Enable"] +pub type AMATCH_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENSET_SPEC, bool, O>; +#[doc = "Field `DRDY` reader - Data Interrupt Enable"] +pub type DRDY_R = crate::BitReader; +#[doc = "Field `DRDY` writer - Data Interrupt Enable"] +pub type DRDY_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENSET_SPEC, bool, O>; +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub type ERROR_R = crate::BitReader; +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub type ERROR_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENSET_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Stop Received Interrupt Enable"] + #[inline(always)] + pub fn prec(&self) -> PREC_R { + PREC_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Address Match Interrupt Enable"] + #[inline(always)] + pub fn amatch(&self) -> AMATCH_R { + AMATCH_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Data Interrupt Enable"] + #[inline(always)] + pub fn drdy(&self) -> DRDY_R { + DRDY_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Received Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn prec(&mut self) -> PREC_W<0> { + PREC_W::new(self) + } + #[doc = "Bit 1 - Address Match Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn amatch(&mut self) -> AMATCH_W<1> { + AMATCH_W::new(self) + } + #[doc = "Bit 2 - Data Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn drdy(&mut self) -> DRDY_W<2> { + DRDY_W::new(self) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn error(&mut self) -> ERROR_W<7> { + ERROR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/sercom0/i2cs/intflag.rs b/pac/atsaml22j/src/sercom0/i2cs/intflag.rs new file mode 100644 index 000000000000..40b506de4cc3 --- /dev/null +++ b/pac/atsaml22j/src/sercom0/i2cs/intflag.rs @@ -0,0 +1,125 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PREC` reader - Stop Received Interrupt"] +pub type PREC_R = crate::BitReader; +#[doc = "Field `PREC` writer - Stop Received Interrupt"] +pub type PREC_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTFLAG_SPEC, bool, O>; +#[doc = "Field `AMATCH` reader - Address Match Interrupt"] +pub type AMATCH_R = crate::BitReader; +#[doc = "Field `AMATCH` writer - Address Match Interrupt"] +pub type AMATCH_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTFLAG_SPEC, bool, O>; +#[doc = "Field `DRDY` reader - Data Interrupt"] +pub type DRDY_R = crate::BitReader; +#[doc = "Field `DRDY` writer - Data Interrupt"] +pub type DRDY_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTFLAG_SPEC, bool, O>; +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub type ERROR_R = crate::BitReader; +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub type ERROR_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTFLAG_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Stop Received Interrupt"] + #[inline(always)] + pub fn prec(&self) -> PREC_R { + PREC_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Address Match Interrupt"] + #[inline(always)] + pub fn amatch(&self) -> AMATCH_R { + AMATCH_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Data Interrupt"] + #[inline(always)] + pub fn drdy(&self) -> DRDY_R { + DRDY_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Stop Received Interrupt"] + #[inline(always)] + #[must_use] + pub fn prec(&mut self) -> PREC_W<0> { + PREC_W::new(self) + } + #[doc = "Bit 1 - Address Match Interrupt"] + #[inline(always)] + #[must_use] + pub fn amatch(&mut self) -> AMATCH_W<1> { + AMATCH_W::new(self) + } + #[doc = "Bit 2 - Data Interrupt"] + #[inline(always)] + #[must_use] + pub fn drdy(&mut self) -> DRDY_W<2> { + DRDY_W::new(self) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + #[must_use] + pub fn error(&mut self) -> ERROR_W<7> { + ERROR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/sercom0/i2cs/status.rs b/pac/atsaml22j/src/sercom0/i2cs/status.rs new file mode 100644 index 000000000000..551c1edbefa0 --- /dev/null +++ b/pac/atsaml22j/src/sercom0/i2cs/status.rs @@ -0,0 +1,168 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUSERR` reader - Bus Error"] +pub type BUSERR_R = crate::BitReader; +#[doc = "Field `BUSERR` writer - Bus Error"] +pub type BUSERR_W<'a, const O: u8> = crate::BitWriter<'a, u16, STATUS_SPEC, bool, O>; +#[doc = "Field `COLL` reader - Transmit Collision"] +pub type COLL_R = crate::BitReader; +#[doc = "Field `COLL` writer - Transmit Collision"] +pub type COLL_W<'a, const O: u8> = crate::BitWriter<'a, u16, STATUS_SPEC, bool, O>; +#[doc = "Field `RXNACK` reader - Received Not Acknowledge"] +pub type RXNACK_R = crate::BitReader; +#[doc = "Field `DIR` reader - Read/Write Direction"] +pub type DIR_R = crate::BitReader; +#[doc = "Field `SR` reader - Repeated Start"] +pub type SR_R = crate::BitReader; +#[doc = "Field `LOWTOUT` reader - SCL Low Timeout"] +pub type LOWTOUT_R = crate::BitReader; +#[doc = "Field `LOWTOUT` writer - SCL Low Timeout"] +pub type LOWTOUT_W<'a, const O: u8> = crate::BitWriter<'a, u16, STATUS_SPEC, bool, O>; +#[doc = "Field `CLKHOLD` reader - Clock Hold"] +pub type CLKHOLD_R = crate::BitReader; +#[doc = "Field `SEXTTOUT` reader - Slave SCL Low Extend Timeout"] +pub type SEXTTOUT_R = crate::BitReader; +#[doc = "Field `SEXTTOUT` writer - Slave SCL Low Extend Timeout"] +pub type SEXTTOUT_W<'a, const O: u8> = crate::BitWriter<'a, u16, STATUS_SPEC, bool, O>; +#[doc = "Field `HS` reader - High Speed"] +pub type HS_R = crate::BitReader; +#[doc = "Field `HS` writer - High Speed"] +pub type HS_W<'a, const O: u8> = crate::BitWriter<'a, u16, STATUS_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Bus Error"] + #[inline(always)] + pub fn buserr(&self) -> BUSERR_R { + BUSERR_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transmit Collision"] + #[inline(always)] + pub fn coll(&self) -> COLL_R { + COLL_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Received Not Acknowledge"] + #[inline(always)] + pub fn rxnack(&self) -> RXNACK_R { + RXNACK_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Read/Write Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Repeated Start"] + #[inline(always)] + pub fn sr(&self) -> SR_R { + SR_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 6 - SCL Low Timeout"] + #[inline(always)] + pub fn lowtout(&self) -> LOWTOUT_R { + LOWTOUT_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Clock Hold"] + #[inline(always)] + pub fn clkhold(&self) -> CLKHOLD_R { + CLKHOLD_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 9 - Slave SCL Low Extend Timeout"] + #[inline(always)] + pub fn sexttout(&self) -> SEXTTOUT_R { + SEXTTOUT_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - High Speed"] + #[inline(always)] + pub fn hs(&self) -> HS_R { + HS_R::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Bus Error"] + #[inline(always)] + #[must_use] + pub fn buserr(&mut self) -> BUSERR_W<0> { + BUSERR_W::new(self) + } + #[doc = "Bit 1 - Transmit Collision"] + #[inline(always)] + #[must_use] + pub fn coll(&mut self) -> COLL_W<1> { + COLL_W::new(self) + } + #[doc = "Bit 6 - SCL Low Timeout"] + #[inline(always)] + #[must_use] + pub fn lowtout(&mut self) -> LOWTOUT_W<6> { + LOWTOUT_W::new(self) + } + #[doc = "Bit 9 - Slave SCL Low Extend Timeout"] + #[inline(always)] + #[must_use] + pub fn sexttout(&mut self) -> SEXTTOUT_W<9> { + SEXTTOUT_W::new(self) + } + #[doc = "Bit 10 - High Speed"] + #[inline(always)] + #[must_use] + pub fn hs(&mut self) -> HS_W<10> { + HS_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "I2CS Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/sercom0/i2cs/syncbusy.rs b/pac/atsaml22j/src/sercom0/i2cs/syncbusy.rs new file mode 100644 index 000000000000..7d04fa8d9aee --- /dev/null +++ b/pac/atsaml22j/src/sercom0/i2cs/syncbusy.rs @@ -0,0 +1,44 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub type SWRST_R = crate::BitReader; +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub type ENABLE_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[doc = "I2CS Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/sercom0/spi.rs b/pac/atsaml22j/src/sercom0/spi.rs new file mode 100644 index 000000000000..762ae018d655 --- /dev/null +++ b/pac/atsaml22j/src/sercom0/spi.rs @@ -0,0 +1,77 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct SPI { + #[doc = "0x00 - SPI Control A"] + pub ctrla: CTRLA, + #[doc = "0x04 - SPI Control B"] + pub ctrlb: CTRLB, + _reserved2: [u8; 0x04], + #[doc = "0x0c - SPI Baud Rate"] + pub baud: BAUD, + _reserved3: [u8; 0x07], + #[doc = "0x14 - SPI Interrupt Enable Clear"] + pub intenclr: INTENCLR, + _reserved4: [u8; 0x01], + #[doc = "0x16 - SPI Interrupt Enable Set"] + pub intenset: INTENSET, + _reserved5: [u8; 0x01], + #[doc = "0x18 - SPI Interrupt Flag Status and Clear"] + pub intflag: INTFLAG, + _reserved6: [u8; 0x01], + #[doc = "0x1a - SPI Status"] + pub status: STATUS, + #[doc = "0x1c - SPI Synchronization Busy"] + pub syncbusy: SYNCBUSY, + _reserved8: [u8; 0x04], + #[doc = "0x24 - SPI Address"] + pub addr: ADDR, + #[doc = "0x28 - SPI Data"] + pub data: DATA, + _reserved10: [u8; 0x04], + #[doc = "0x30 - SPI Debug Control"] + pub dbgctrl: DBGCTRL, +} +#[doc = "CTRLA (rw) register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "SPI Control A"] +pub mod ctrla; +#[doc = "CTRLB (rw) register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "SPI Control B"] +pub mod ctrlb; +#[doc = "BAUD (rw) register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "SPI Baud Rate"] +pub mod baud; +#[doc = "INTENCLR (rw) register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "SPI Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET (rw) register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "SPI Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG (rw) register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "SPI Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS (rw) register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "SPI Status"] +pub mod status; +#[doc = "SYNCBUSY (r) register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "SPI Synchronization Busy"] +pub mod syncbusy; +#[doc = "ADDR (rw) register accessor: an alias for `Reg`"] +pub type ADDR = crate::Reg; +#[doc = "SPI Address"] +pub mod addr; +#[doc = "DATA (rw) register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "SPI Data"] +pub mod data; +#[doc = "DBGCTRL (rw) register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "SPI Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsaml22j/src/sercom0/spi/addr.rs b/pac/atsaml22j/src/sercom0/spi/addr.rs new file mode 100644 index 000000000000..46bee2db6440 --- /dev/null +++ b/pac/atsaml22j/src/sercom0/spi/addr.rs @@ -0,0 +1,95 @@ +#[doc = "Register `ADDR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ADDR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ADDR` reader - Address Value"] +pub type ADDR_R = crate::FieldReader; +#[doc = "Field `ADDR` writer - Address Value"] +pub type ADDR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ADDR_SPEC, u8, u8, 8, O>; +#[doc = "Field `ADDRMASK` reader - Address Mask"] +pub type ADDRMASK_R = crate::FieldReader; +#[doc = "Field `ADDRMASK` writer - Address Mask"] +pub type ADDRMASK_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ADDR_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Address Value"] + #[inline(always)] + pub fn addr(&self) -> ADDR_R { + ADDR_R::new((self.bits & 0xff) as u8) + } + #[doc = "Bits 16:23 - Address Mask"] + #[inline(always)] + pub fn addrmask(&self) -> ADDRMASK_R { + ADDRMASK_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Address Value"] + #[inline(always)] + #[must_use] + pub fn addr(&mut self) -> ADDR_W<0> { + ADDR_W::new(self) + } + #[doc = "Bits 16:23 - Address Mask"] + #[inline(always)] + #[must_use] + pub fn addrmask(&mut self) -> ADDRMASK_W<16> { + ADDRMASK_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPI Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [addr](index.html) module"] +pub struct ADDR_SPEC; +impl crate::RegisterSpec for ADDR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [addr::R](R) reader structure"] +impl crate::Readable for ADDR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [addr::W](W) writer structure"] +impl crate::Writable for ADDR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ADDR to value 0"] +impl crate::Resettable for ADDR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/sercom0/spi/baud.rs b/pac/atsaml22j/src/sercom0/spi/baud.rs new file mode 100644 index 000000000000..140feeb1e6a0 --- /dev/null +++ b/pac/atsaml22j/src/sercom0/spi/baud.rs @@ -0,0 +1,80 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub type BAUD_R = crate::FieldReader; +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub type BAUD_W<'a, const O: u8> = crate::FieldWriter<'a, u8, BAUD_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:7 - Baud Rate Value"] + #[inline(always)] + #[must_use] + pub fn baud(&mut self) -> BAUD_W<0> { + BAUD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPI Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/sercom0/spi/ctrla.rs b/pac/atsaml22j/src/sercom0/spi/ctrla.rs new file mode 100644 index 000000000000..b77bd7e6f2df --- /dev/null +++ b/pac/atsaml22j/src/sercom0/spi/ctrla.rs @@ -0,0 +1,230 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub type SWRST_R = crate::BitReader; +#[doc = "Field `SWRST` writer - Software Reset"] +pub type SWRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `ENABLE` reader - Enable"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - Enable"] +pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `MODE` reader - Operating Mode"] +pub type MODE_R = crate::FieldReader; +#[doc = "Field `MODE` writer - Operating Mode"] +pub type MODE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRLA_SPEC, u8, u8, 3, O>; +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub type RUNSTDBY_R = crate::BitReader; +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub type RUNSTDBY_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `IBON` reader - Immediate Buffer Overflow Notification"] +pub type IBON_R = crate::BitReader; +#[doc = "Field `IBON` writer - Immediate Buffer Overflow Notification"] +pub type IBON_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `DOPO` reader - Data Out Pinout"] +pub type DOPO_R = crate::FieldReader; +#[doc = "Field `DOPO` writer - Data Out Pinout"] +pub type DOPO_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRLA_SPEC, u8, u8, 2, O>; +#[doc = "Field `DIPO` reader - Data In Pinout"] +pub type DIPO_R = crate::FieldReader; +#[doc = "Field `DIPO` writer - Data In Pinout"] +pub type DIPO_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRLA_SPEC, u8, u8, 2, O>; +#[doc = "Field `FORM` reader - Frame Format"] +pub type FORM_R = crate::FieldReader; +#[doc = "Field `FORM` writer - Frame Format"] +pub type FORM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRLA_SPEC, u8, u8, 4, O>; +#[doc = "Field `CPHA` reader - Clock Phase"] +pub type CPHA_R = crate::BitReader; +#[doc = "Field `CPHA` writer - Clock Phase"] +pub type CPHA_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `CPOL` reader - Clock Polarity"] +pub type CPOL_R = crate::BitReader; +#[doc = "Field `CPOL` writer - Clock Polarity"] +pub type CPOL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `DORD` reader - Data Order"] +pub type DORD_R = crate::BitReader; +#[doc = "Field `DORD` writer - Data Order"] +pub type DORD_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 7) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&self) -> IBON_R { + IBON_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bits 16:17 - Data Out Pinout"] + #[inline(always)] + pub fn dopo(&self) -> DOPO_R { + DOPO_R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bits 20:21 - Data In Pinout"] + #[inline(always)] + pub fn dipo(&self) -> DIPO_R { + DIPO_R::new(((self.bits >> 20) & 3) as u8) + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&self) -> FORM_R { + FORM_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 28 - Clock Phase"] + #[inline(always)] + pub fn cpha(&self) -> CPHA_R { + CPHA_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&self) -> CPOL_R { + CPOL_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&self) -> DORD_R { + DORD_R::new(((self.bits >> 30) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + #[must_use] + pub fn swrst(&mut self) -> SWRST_W<0> { + SWRST_W::new(self) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W<1> { + ENABLE_W::new(self) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> MODE_W<2> { + MODE_W::new(self) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + #[must_use] + pub fn runstdby(&mut self) -> RUNSTDBY_W<7> { + RUNSTDBY_W::new(self) + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + #[must_use] + pub fn ibon(&mut self) -> IBON_W<8> { + IBON_W::new(self) + } + #[doc = "Bits 16:17 - Data Out Pinout"] + #[inline(always)] + #[must_use] + pub fn dopo(&mut self) -> DOPO_W<16> { + DOPO_W::new(self) + } + #[doc = "Bits 20:21 - Data In Pinout"] + #[inline(always)] + #[must_use] + pub fn dipo(&mut self) -> DIPO_W<20> { + DIPO_W::new(self) + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + #[must_use] + pub fn form(&mut self) -> FORM_W<24> { + FORM_W::new(self) + } + #[doc = "Bit 28 - Clock Phase"] + #[inline(always)] + #[must_use] + pub fn cpha(&mut self) -> CPHA_W<28> { + CPHA_W::new(self) + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + #[must_use] + pub fn cpol(&mut self) -> CPOL_W<29> { + CPOL_W::new(self) + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + #[must_use] + pub fn dord(&mut self) -> DORD_W<30> { + DORD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPI Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/sercom0/spi/ctrlb.rs b/pac/atsaml22j/src/sercom0/spi/ctrlb.rs new file mode 100644 index 000000000000..822bb4628fa2 --- /dev/null +++ b/pac/atsaml22j/src/sercom0/spi/ctrlb.rs @@ -0,0 +1,155 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHSIZE` reader - Character Size"] +pub type CHSIZE_R = crate::FieldReader; +#[doc = "Field `CHSIZE` writer - Character Size"] +pub type CHSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRLB_SPEC, u8, u8, 3, O>; +#[doc = "Field `PLOADEN` reader - Data Preload Enable"] +pub type PLOADEN_R = crate::BitReader; +#[doc = "Field `PLOADEN` writer - Data Preload Enable"] +pub type PLOADEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLB_SPEC, bool, O>; +#[doc = "Field `SSDE` reader - Slave Select Low Detect Enable"] +pub type SSDE_R = crate::BitReader; +#[doc = "Field `SSDE` writer - Slave Select Low Detect Enable"] +pub type SSDE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLB_SPEC, bool, O>; +#[doc = "Field `MSSEN` reader - Master Slave Select Enable"] +pub type MSSEN_R = crate::BitReader; +#[doc = "Field `MSSEN` writer - Master Slave Select Enable"] +pub type MSSEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLB_SPEC, bool, O>; +#[doc = "Field `AMODE` reader - Address Mode"] +pub type AMODE_R = crate::FieldReader; +#[doc = "Field `AMODE` writer - Address Mode"] +pub type AMODE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRLB_SPEC, u8, u8, 2, O>; +#[doc = "Field `RXEN` reader - Receiver Enable"] +pub type RXEN_R = crate::BitReader; +#[doc = "Field `RXEN` writer - Receiver Enable"] +pub type RXEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLB_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&self) -> CHSIZE_R { + CHSIZE_R::new((self.bits & 7) as u8) + } + #[doc = "Bit 6 - Data Preload Enable"] + #[inline(always)] + pub fn ploaden(&self) -> PLOADEN_R { + PLOADEN_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 9 - Slave Select Low Detect Enable"] + #[inline(always)] + pub fn ssde(&self) -> SSDE_R { + SSDE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 13 - Master Slave Select Enable"] + #[inline(always)] + pub fn mssen(&self) -> MSSEN_R { + MSSEN_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + pub fn amode(&self) -> AMODE_R { + AMODE_R::new(((self.bits >> 14) & 3) as u8) + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&self) -> RXEN_R { + RXEN_R::new(((self.bits >> 17) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + #[must_use] + pub fn chsize(&mut self) -> CHSIZE_W<0> { + CHSIZE_W::new(self) + } + #[doc = "Bit 6 - Data Preload Enable"] + #[inline(always)] + #[must_use] + pub fn ploaden(&mut self) -> PLOADEN_W<6> { + PLOADEN_W::new(self) + } + #[doc = "Bit 9 - Slave Select Low Detect Enable"] + #[inline(always)] + #[must_use] + pub fn ssde(&mut self) -> SSDE_W<9> { + SSDE_W::new(self) + } + #[doc = "Bit 13 - Master Slave Select Enable"] + #[inline(always)] + #[must_use] + pub fn mssen(&mut self) -> MSSEN_W<13> { + MSSEN_W::new(self) + } + #[doc = "Bits 14:15 - Address Mode"] + #[inline(always)] + #[must_use] + pub fn amode(&mut self) -> AMODE_W<14> { + AMODE_W::new(self) + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + #[must_use] + pub fn rxen(&mut self) -> RXEN_W<17> { + RXEN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPI Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/sercom0/spi/data.rs b/pac/atsaml22j/src/sercom0/spi/data.rs new file mode 100644 index 000000000000..5f034fb4df25 --- /dev/null +++ b/pac/atsaml22j/src/sercom0/spi/data.rs @@ -0,0 +1,80 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub type DATA_R = crate::FieldReader; +#[doc = "Field `DATA` writer - Data Value"] +pub type DATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DATA_SPEC, u16, u16, 9, O>; +impl R { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new((self.bits & 0x01ff) as u16) + } +} +impl W { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + #[must_use] + pub fn data(&mut self) -> DATA_W<0> { + DATA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPI Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/sercom0/spi/dbgctrl.rs b/pac/atsaml22j/src/sercom0/spi/dbgctrl.rs new file mode 100644 index 000000000000..c6d42bb4c814 --- /dev/null +++ b/pac/atsaml22j/src/sercom0/spi/dbgctrl.rs @@ -0,0 +1,80 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub type DBGSTOP_R = crate::BitReader; +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub type DBGSTOP_W<'a, const O: u8> = crate::BitWriter<'a, u8, DBGCTRL_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + #[must_use] + pub fn dbgstop(&mut self) -> DBGSTOP_W<0> { + DBGSTOP_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPI Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/sercom0/spi/intenclr.rs b/pac/atsaml22j/src/sercom0/spi/intenclr.rs new file mode 100644 index 000000000000..f4ab798b2fa1 --- /dev/null +++ b/pac/atsaml22j/src/sercom0/spi/intenclr.rs @@ -0,0 +1,140 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Disable"] +pub type DRE_R = crate::BitReader; +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Disable"] +pub type DRE_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>; +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Disable"] +pub type TXC_R = crate::BitReader; +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Disable"] +pub type TXC_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>; +#[doc = "Field `RXC` reader - Receive Complete Interrupt Disable"] +pub type RXC_R = crate::BitReader; +#[doc = "Field `RXC` writer - Receive Complete Interrupt Disable"] +pub type RXC_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>; +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Disable"] +pub type SSL_R = crate::BitReader; +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Disable"] +pub type SSL_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>; +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub type ERROR_R = crate::BitReader; +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub type ERROR_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Disable"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + #[must_use] + pub fn dre(&mut self) -> DRE_W<0> { + DRE_W::new(self) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + #[must_use] + pub fn txc(&mut self) -> TXC_W<1> { + TXC_W::new(self) + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + #[must_use] + pub fn rxc(&mut self) -> RXC_W<2> { + RXC_W::new(self) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Disable"] + #[inline(always)] + #[must_use] + pub fn ssl(&mut self) -> SSL_W<3> { + SSL_W::new(self) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + #[must_use] + pub fn error(&mut self) -> ERROR_W<7> { + ERROR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPI Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/sercom0/spi/intenset.rs b/pac/atsaml22j/src/sercom0/spi/intenset.rs new file mode 100644 index 000000000000..ddb9ede10ba6 --- /dev/null +++ b/pac/atsaml22j/src/sercom0/spi/intenset.rs @@ -0,0 +1,140 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Enable"] +pub type DRE_R = crate::BitReader; +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Enable"] +pub type DRE_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENSET_SPEC, bool, O>; +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Enable"] +pub type TXC_R = crate::BitReader; +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Enable"] +pub type TXC_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENSET_SPEC, bool, O>; +#[doc = "Field `RXC` reader - Receive Complete Interrupt Enable"] +pub type RXC_R = crate::BitReader; +#[doc = "Field `RXC` writer - Receive Complete Interrupt Enable"] +pub type RXC_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENSET_SPEC, bool, O>; +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Enable"] +pub type SSL_R = crate::BitReader; +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Enable"] +pub type SSL_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENSET_SPEC, bool, O>; +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub type ERROR_R = crate::BitReader; +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub type ERROR_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENSET_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Enable"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn dre(&mut self) -> DRE_W<0> { + DRE_W::new(self) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn txc(&mut self) -> TXC_W<1> { + TXC_W::new(self) + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn rxc(&mut self) -> RXC_W<2> { + RXC_W::new(self) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn ssl(&mut self) -> SSL_W<3> { + SSL_W::new(self) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn error(&mut self) -> ERROR_W<7> { + ERROR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPI Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/sercom0/spi/intflag.rs b/pac/atsaml22j/src/sercom0/spi/intflag.rs new file mode 100644 index 000000000000..5fcacb2cc611 --- /dev/null +++ b/pac/atsaml22j/src/sercom0/spi/intflag.rs @@ -0,0 +1,124 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt"] +pub type DRE_R = crate::BitReader; +#[doc = "Field `TXC` reader - Transmit Complete Interrupt"] +pub type TXC_R = crate::BitReader; +#[doc = "Field `TXC` writer - Transmit Complete Interrupt"] +pub type TXC_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTFLAG_SPEC, bool, O>; +#[doc = "Field `RXC` reader - Receive Complete Interrupt"] +pub type RXC_R = crate::BitReader; +#[doc = "Field `SSL` reader - Slave Select Low Interrupt Flag"] +pub type SSL_R = crate::BitReader; +#[doc = "Field `SSL` writer - Slave Select Low Interrupt Flag"] +pub type SSL_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTFLAG_SPEC, bool, O>; +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub type ERROR_R = crate::BitReader; +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub type ERROR_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTFLAG_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Flag"] + #[inline(always)] + pub fn ssl(&self) -> SSL_R { + SSL_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + #[must_use] + pub fn txc(&mut self) -> TXC_W<1> { + TXC_W::new(self) + } + #[doc = "Bit 3 - Slave Select Low Interrupt Flag"] + #[inline(always)] + #[must_use] + pub fn ssl(&mut self) -> SSL_W<3> { + SSL_W::new(self) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + #[must_use] + pub fn error(&mut self) -> ERROR_W<7> { + ERROR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPI Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/sercom0/spi/status.rs b/pac/atsaml22j/src/sercom0/spi/status.rs new file mode 100644 index 000000000000..fb4090978443 --- /dev/null +++ b/pac/atsaml22j/src/sercom0/spi/status.rs @@ -0,0 +1,80 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BUFOVF` reader - Buffer Overflow"] +pub type BUFOVF_R = crate::BitReader; +#[doc = "Field `BUFOVF` writer - Buffer Overflow"] +pub type BUFOVF_W<'a, const O: u8> = crate::BitWriter<'a, u16, STATUS_SPEC, bool, O>; +impl R { + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&self) -> BUFOVF_R { + BUFOVF_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + #[must_use] + pub fn bufovf(&mut self) -> BUFOVF_W<2> { + BUFOVF_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "SPI Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/sercom0/spi/syncbusy.rs b/pac/atsaml22j/src/sercom0/spi/syncbusy.rs new file mode 100644 index 000000000000..0dacc160cc0e --- /dev/null +++ b/pac/atsaml22j/src/sercom0/spi/syncbusy.rs @@ -0,0 +1,51 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub type SWRST_R = crate::BitReader; +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `CTRLB` reader - CTRLB Synchronization Busy"] +pub type CTRLB_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - CTRLB Synchronization Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 1) != 0) + } +} +#[doc = "SPI Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/sercom0/usart.rs b/pac/atsaml22j/src/sercom0/usart.rs new file mode 100644 index 000000000000..5081c341236d --- /dev/null +++ b/pac/atsaml22j/src/sercom0/usart.rs @@ -0,0 +1,121 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct USART { + #[doc = "0x00 - USART Control A"] + pub ctrla: CTRLA, + #[doc = "0x04 - USART Control B"] + pub ctrlb: CTRLB, + #[doc = "0x08 - USART Control C"] + pub ctrlc: CTRLC, + _reserved_3_baud: [u8; 0x02], + #[doc = "0x0e - USART Receive Pulse Length"] + pub rxpl: RXPL, + _reserved5: [u8; 0x05], + #[doc = "0x14 - USART Interrupt Enable Clear"] + pub intenclr: INTENCLR, + _reserved6: [u8; 0x01], + #[doc = "0x16 - USART Interrupt Enable Set"] + pub intenset: INTENSET, + _reserved7: [u8; 0x01], + #[doc = "0x18 - USART Interrupt Flag Status and Clear"] + pub intflag: INTFLAG, + _reserved8: [u8; 0x01], + #[doc = "0x1a - USART Status"] + pub status: STATUS, + #[doc = "0x1c - USART Synchronization Busy"] + pub syncbusy: SYNCBUSY, + #[doc = "0x20 - USART Receive Error Count"] + pub rxerrcnt: RXERRCNT, + _reserved11: [u8; 0x07], + #[doc = "0x28 - USART Data"] + pub data: DATA, + _reserved12: [u8; 0x06], + #[doc = "0x30 - USART Debug Control"] + pub dbgctrl: DBGCTRL, +} +impl USART { + #[doc = "0x0c - USART Baud Rate"] + #[inline(always)] + pub const fn baud_usartfp_mode(&self) -> &BAUD_USARTFP_MODE { + unsafe { &*(self as *const Self).cast::().add(12usize).cast() } + } + #[doc = "0x0c - USART Baud Rate"] + #[inline(always)] + pub const fn baud_fracfp_mode(&self) -> &BAUD_FRACFP_MODE { + unsafe { &*(self as *const Self).cast::().add(12usize).cast() } + } + #[doc = "0x0c - USART Baud Rate"] + #[inline(always)] + pub const fn baud_frac_mode(&self) -> &BAUD_FRAC_MODE { + unsafe { &*(self as *const Self).cast::().add(12usize).cast() } + } + #[doc = "0x0c - USART Baud Rate"] + #[inline(always)] + pub const fn baud(&self) -> &BAUD { + unsafe { &*(self as *const Self).cast::().add(12usize).cast() } + } +} +#[doc = "CTRLA (rw) register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "USART Control A"] +pub mod ctrla; +#[doc = "CTRLB (rw) register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "USART Control B"] +pub mod ctrlb; +#[doc = "CTRLC (rw) register accessor: an alias for `Reg`"] +pub type CTRLC = crate::Reg; +#[doc = "USART Control C"] +pub mod ctrlc; +#[doc = "BAUD (rw) register accessor: an alias for `Reg`"] +pub type BAUD = crate::Reg; +#[doc = "USART Baud Rate"] +pub mod baud; +#[doc = "BAUD_FRAC_MODE (rw) register accessor: an alias for `Reg`"] +pub type BAUD_FRAC_MODE = crate::Reg; +#[doc = "USART Baud Rate"] +pub mod baud_frac_mode; +#[doc = "BAUD_FRACFP_MODE (rw) register accessor: an alias for `Reg`"] +pub type BAUD_FRACFP_MODE = crate::Reg; +#[doc = "USART Baud Rate"] +pub mod baud_fracfp_mode; +#[doc = "BAUD_USARTFP_MODE (rw) register accessor: an alias for `Reg`"] +pub type BAUD_USARTFP_MODE = crate::Reg; +#[doc = "USART Baud Rate"] +pub mod baud_usartfp_mode; +#[doc = "RXPL (rw) register accessor: an alias for `Reg`"] +pub type RXPL = crate::Reg; +#[doc = "USART Receive Pulse Length"] +pub mod rxpl; +#[doc = "INTENCLR (rw) register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "USART Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET (rw) register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "USART Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG (rw) register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "USART Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS (rw) register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "USART Status"] +pub mod status; +#[doc = "SYNCBUSY (r) register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "USART Synchronization Busy"] +pub mod syncbusy; +#[doc = "RXERRCNT (r) register accessor: an alias for `Reg`"] +pub type RXERRCNT = crate::Reg; +#[doc = "USART Receive Error Count"] +pub mod rxerrcnt; +#[doc = "DATA (rw) register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "USART Data"] +pub mod data; +#[doc = "DBGCTRL (rw) register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "USART Debug Control"] +pub mod dbgctrl; diff --git a/pac/atsaml22j/src/sercom0/usart/baud.rs b/pac/atsaml22j/src/sercom0/usart/baud.rs new file mode 100644 index 000000000000..b93642275dbd --- /dev/null +++ b/pac/atsaml22j/src/sercom0/usart/baud.rs @@ -0,0 +1,80 @@ +#[doc = "Register `BAUD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub type BAUD_R = crate::FieldReader; +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub type BAUD_W<'a, const O: u8> = crate::FieldWriter<'a, u16, BAUD_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + #[must_use] + pub fn baud(&mut self) -> BAUD_W<0> { + BAUD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud](index.html) module"] +pub struct BAUD_SPEC; +impl crate::RegisterSpec for BAUD_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud::R](R) reader structure"] +impl crate::Readable for BAUD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud::W](W) writer structure"] +impl crate::Writable for BAUD_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BAUD to value 0"] +impl crate::Resettable for BAUD_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/sercom0/usart/baud_frac_mode.rs b/pac/atsaml22j/src/sercom0/usart/baud_frac_mode.rs new file mode 100644 index 000000000000..9d67a38236e4 --- /dev/null +++ b/pac/atsaml22j/src/sercom0/usart/baud_frac_mode.rs @@ -0,0 +1,96 @@ +#[doc = "Register `BAUD_FRAC_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_FRAC_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub type BAUD_R = crate::FieldReader; +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub type BAUD_W<'a, const O: u8> = + crate::FieldWriter<'a, u16, BAUD_FRAC_MODE_SPEC, u16, u16, 13, O>; +#[doc = "Field `FP` reader - Fractional Part"] +pub type FP_R = crate::FieldReader; +#[doc = "Field `FP` writer - Fractional Part"] +pub type FP_W<'a, const O: u8> = crate::FieldWriter<'a, u16, BAUD_FRAC_MODE_SPEC, u8, u8, 3, O>; +impl R { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits & 0x1fff) + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&self) -> FP_R { + FP_R::new(((self.bits >> 13) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + #[must_use] + pub fn baud(&mut self) -> BAUD_W<0> { + BAUD_W::new(self) + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + #[must_use] + pub fn fp(&mut self) -> FP_W<13> { + FP_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_frac_mode](index.html) module"] +pub struct BAUD_FRAC_MODE_SPEC; +impl crate::RegisterSpec for BAUD_FRAC_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_frac_mode::R](R) reader structure"] +impl crate::Readable for BAUD_FRAC_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_frac_mode::W](W) writer structure"] +impl crate::Writable for BAUD_FRAC_MODE_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BAUD_FRAC_MODE to value 0"] +impl crate::Resettable for BAUD_FRAC_MODE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/sercom0/usart/baud_fracfp_mode.rs b/pac/atsaml22j/src/sercom0/usart/baud_fracfp_mode.rs new file mode 100644 index 000000000000..d6da9420cfcf --- /dev/null +++ b/pac/atsaml22j/src/sercom0/usart/baud_fracfp_mode.rs @@ -0,0 +1,96 @@ +#[doc = "Register `BAUD_FRACFP_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_FRACFP_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub type BAUD_R = crate::FieldReader; +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub type BAUD_W<'a, const O: u8> = + crate::FieldWriter<'a, u16, BAUD_FRACFP_MODE_SPEC, u16, u16, 13, O>; +#[doc = "Field `FP` reader - Fractional Part"] +pub type FP_R = crate::FieldReader; +#[doc = "Field `FP` writer - Fractional Part"] +pub type FP_W<'a, const O: u8> = crate::FieldWriter<'a, u16, BAUD_FRACFP_MODE_SPEC, u8, u8, 3, O>; +impl R { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits & 0x1fff) + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + pub fn fp(&self) -> FP_R { + FP_R::new(((self.bits >> 13) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:12 - Baud Rate Value"] + #[inline(always)] + #[must_use] + pub fn baud(&mut self) -> BAUD_W<0> { + BAUD_W::new(self) + } + #[doc = "Bits 13:15 - Fractional Part"] + #[inline(always)] + #[must_use] + pub fn fp(&mut self) -> FP_W<13> { + FP_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_fracfp_mode](index.html) module"] +pub struct BAUD_FRACFP_MODE_SPEC; +impl crate::RegisterSpec for BAUD_FRACFP_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_fracfp_mode::R](R) reader structure"] +impl crate::Readable for BAUD_FRACFP_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_fracfp_mode::W](W) writer structure"] +impl crate::Writable for BAUD_FRACFP_MODE_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BAUD_FRACFP_MODE to value 0"] +impl crate::Resettable for BAUD_FRACFP_MODE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/sercom0/usart/baud_usartfp_mode.rs b/pac/atsaml22j/src/sercom0/usart/baud_usartfp_mode.rs new file mode 100644 index 000000000000..1e7a145efda1 --- /dev/null +++ b/pac/atsaml22j/src/sercom0/usart/baud_usartfp_mode.rs @@ -0,0 +1,81 @@ +#[doc = "Register `BAUD_USARTFP_MODE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BAUD_USARTFP_MODE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BAUD` reader - Baud Rate Value"] +pub type BAUD_R = crate::FieldReader; +#[doc = "Field `BAUD` writer - Baud Rate Value"] +pub type BAUD_W<'a, const O: u8> = + crate::FieldWriter<'a, u16, BAUD_USARTFP_MODE_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + pub fn baud(&self) -> BAUD_R { + BAUD_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - Baud Rate Value"] + #[inline(always)] + #[must_use] + pub fn baud(&mut self) -> BAUD_W<0> { + BAUD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART Baud Rate\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [baud_usartfp_mode](index.html) module"] +pub struct BAUD_USARTFP_MODE_SPEC; +impl crate::RegisterSpec for BAUD_USARTFP_MODE_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [baud_usartfp_mode::R](R) reader structure"] +impl crate::Readable for BAUD_USARTFP_MODE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [baud_usartfp_mode::W](W) writer structure"] +impl crate::Writable for BAUD_USARTFP_MODE_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BAUD_USARTFP_MODE to value 0"] +impl crate::Resettable for BAUD_USARTFP_MODE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/sercom0/usart/ctrla.rs b/pac/atsaml22j/src/sercom0/usart/ctrla.rs new file mode 100644 index 000000000000..0bf49e27ea79 --- /dev/null +++ b/pac/atsaml22j/src/sercom0/usart/ctrla.rs @@ -0,0 +1,290 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub type SWRST_R = crate::BitReader; +#[doc = "Field `SWRST` writer - Software Reset"] +pub type SWRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `ENABLE` reader - Enable"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - Enable"] +pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `MODE` reader - Operating Mode"] +pub type MODE_R = crate::FieldReader; +#[doc = "Field `MODE` writer - Operating Mode"] +pub type MODE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRLA_SPEC, u8, u8, 3, O>; +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub type RUNSTDBY_R = crate::BitReader; +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub type RUNSTDBY_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `IBON` reader - Immediate Buffer Overflow Notification"] +pub type IBON_R = crate::BitReader; +#[doc = "Field `IBON` writer - Immediate Buffer Overflow Notification"] +pub type IBON_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `TXINV` reader - Transmit Data Invert"] +pub type TXINV_R = crate::BitReader; +#[doc = "Field `TXINV` writer - Transmit Data Invert"] +pub type TXINV_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `RXINV` reader - Receive Data Invert"] +pub type RXINV_R = crate::BitReader; +#[doc = "Field `RXINV` writer - Receive Data Invert"] +pub type RXINV_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `SAMPR` reader - Sample"] +pub type SAMPR_R = crate::FieldReader; +#[doc = "Field `SAMPR` writer - Sample"] +pub type SAMPR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRLA_SPEC, u8, u8, 3, O>; +#[doc = "Field `TXPO` reader - Transmit Data Pinout"] +pub type TXPO_R = crate::FieldReader; +#[doc = "Field `TXPO` writer - Transmit Data Pinout"] +pub type TXPO_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRLA_SPEC, u8, u8, 2, O>; +#[doc = "Field `RXPO` reader - Receive Data Pinout"] +pub type RXPO_R = crate::FieldReader; +#[doc = "Field `RXPO` writer - Receive Data Pinout"] +pub type RXPO_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRLA_SPEC, u8, u8, 2, O>; +#[doc = "Field `SAMPA` reader - Sample Adjustment"] +pub type SAMPA_R = crate::FieldReader; +#[doc = "Field `SAMPA` writer - Sample Adjustment"] +pub type SAMPA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRLA_SPEC, u8, u8, 2, O>; +#[doc = "Field `FORM` reader - Frame Format"] +pub type FORM_R = crate::FieldReader; +#[doc = "Field `FORM` writer - Frame Format"] +pub type FORM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRLA_SPEC, u8, u8, 4, O>; +#[doc = "Field `CMODE` reader - Communication Mode"] +pub type CMODE_R = crate::BitReader; +#[doc = "Field `CMODE` writer - Communication Mode"] +pub type CMODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `CPOL` reader - Clock Polarity"] +pub type CPOL_R = crate::BitReader; +#[doc = "Field `CPOL` writer - Clock Polarity"] +pub type CPOL_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `DORD` reader - Data Order"] +pub type DORD_R = crate::BitReader; +#[doc = "Field `DORD` writer - Data Order"] +pub type DORD_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 7) as u8) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + pub fn ibon(&self) -> IBON_R { + IBON_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Transmit Data Invert"] + #[inline(always)] + pub fn txinv(&self) -> TXINV_R { + TXINV_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Receive Data Invert"] + #[inline(always)] + pub fn rxinv(&self) -> RXINV_R { + RXINV_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bits 13:15 - Sample"] + #[inline(always)] + pub fn sampr(&self) -> SAMPR_R { + SAMPR_R::new(((self.bits >> 13) & 7) as u8) + } + #[doc = "Bits 16:17 - Transmit Data Pinout"] + #[inline(always)] + pub fn txpo(&self) -> TXPO_R { + TXPO_R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bits 20:21 - Receive Data Pinout"] + #[inline(always)] + pub fn rxpo(&self) -> RXPO_R { + RXPO_R::new(((self.bits >> 20) & 3) as u8) + } + #[doc = "Bits 22:23 - Sample Adjustment"] + #[inline(always)] + pub fn sampa(&self) -> SAMPA_R { + SAMPA_R::new(((self.bits >> 22) & 3) as u8) + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + pub fn form(&self) -> FORM_R { + FORM_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bit 28 - Communication Mode"] + #[inline(always)] + pub fn cmode(&self) -> CMODE_R { + CMODE_R::new(((self.bits >> 28) & 1) != 0) + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + pub fn cpol(&self) -> CPOL_R { + CPOL_R::new(((self.bits >> 29) & 1) != 0) + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + pub fn dord(&self) -> DORD_R { + DORD_R::new(((self.bits >> 30) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + #[must_use] + pub fn swrst(&mut self) -> SWRST_W<0> { + SWRST_W::new(self) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W<1> { + ENABLE_W::new(self) + } + #[doc = "Bits 2:4 - Operating Mode"] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> MODE_W<2> { + MODE_W::new(self) + } + #[doc = "Bit 7 - Run during Standby"] + #[inline(always)] + #[must_use] + pub fn runstdby(&mut self) -> RUNSTDBY_W<7> { + RUNSTDBY_W::new(self) + } + #[doc = "Bit 8 - Immediate Buffer Overflow Notification"] + #[inline(always)] + #[must_use] + pub fn ibon(&mut self) -> IBON_W<8> { + IBON_W::new(self) + } + #[doc = "Bit 9 - Transmit Data Invert"] + #[inline(always)] + #[must_use] + pub fn txinv(&mut self) -> TXINV_W<9> { + TXINV_W::new(self) + } + #[doc = "Bit 10 - Receive Data Invert"] + #[inline(always)] + #[must_use] + pub fn rxinv(&mut self) -> RXINV_W<10> { + RXINV_W::new(self) + } + #[doc = "Bits 13:15 - Sample"] + #[inline(always)] + #[must_use] + pub fn sampr(&mut self) -> SAMPR_W<13> { + SAMPR_W::new(self) + } + #[doc = "Bits 16:17 - Transmit Data Pinout"] + #[inline(always)] + #[must_use] + pub fn txpo(&mut self) -> TXPO_W<16> { + TXPO_W::new(self) + } + #[doc = "Bits 20:21 - Receive Data Pinout"] + #[inline(always)] + #[must_use] + pub fn rxpo(&mut self) -> RXPO_W<20> { + RXPO_W::new(self) + } + #[doc = "Bits 22:23 - Sample Adjustment"] + #[inline(always)] + #[must_use] + pub fn sampa(&mut self) -> SAMPA_W<22> { + SAMPA_W::new(self) + } + #[doc = "Bits 24:27 - Frame Format"] + #[inline(always)] + #[must_use] + pub fn form(&mut self) -> FORM_W<24> { + FORM_W::new(self) + } + #[doc = "Bit 28 - Communication Mode"] + #[inline(always)] + #[must_use] + pub fn cmode(&mut self) -> CMODE_W<28> { + CMODE_W::new(self) + } + #[doc = "Bit 29 - Clock Polarity"] + #[inline(always)] + #[must_use] + pub fn cpol(&mut self) -> CPOL_W<29> { + CPOL_W::new(self) + } + #[doc = "Bit 30 - Data Order"] + #[inline(always)] + #[must_use] + pub fn dord(&mut self) -> DORD_W<30> { + DORD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/sercom0/usart/ctrlb.rs b/pac/atsaml22j/src/sercom0/usart/ctrlb.rs new file mode 100644 index 000000000000..451b8d33e00f --- /dev/null +++ b/pac/atsaml22j/src/sercom0/usart/ctrlb.rs @@ -0,0 +1,185 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CHSIZE` reader - Character Size"] +pub type CHSIZE_R = crate::FieldReader; +#[doc = "Field `CHSIZE` writer - Character Size"] +pub type CHSIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRLB_SPEC, u8, u8, 3, O>; +#[doc = "Field `SBMODE` reader - Stop Bit Mode"] +pub type SBMODE_R = crate::BitReader; +#[doc = "Field `SBMODE` writer - Stop Bit Mode"] +pub type SBMODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLB_SPEC, bool, O>; +#[doc = "Field `COLDEN` reader - Collision Detection Enable"] +pub type COLDEN_R = crate::BitReader; +#[doc = "Field `COLDEN` writer - Collision Detection Enable"] +pub type COLDEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLB_SPEC, bool, O>; +#[doc = "Field `SFDE` reader - Start of Frame Detection Enable"] +pub type SFDE_R = crate::BitReader; +#[doc = "Field `SFDE` writer - Start of Frame Detection Enable"] +pub type SFDE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLB_SPEC, bool, O>; +#[doc = "Field `ENC` reader - Encoding Format"] +pub type ENC_R = crate::BitReader; +#[doc = "Field `ENC` writer - Encoding Format"] +pub type ENC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLB_SPEC, bool, O>; +#[doc = "Field `PMODE` reader - Parity Mode"] +pub type PMODE_R = crate::BitReader; +#[doc = "Field `PMODE` writer - Parity Mode"] +pub type PMODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLB_SPEC, bool, O>; +#[doc = "Field `TXEN` reader - Transmitter Enable"] +pub type TXEN_R = crate::BitReader; +#[doc = "Field `TXEN` writer - Transmitter Enable"] +pub type TXEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLB_SPEC, bool, O>; +#[doc = "Field `RXEN` reader - Receiver Enable"] +pub type RXEN_R = crate::BitReader; +#[doc = "Field `RXEN` writer - Receiver Enable"] +pub type RXEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLB_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + pub fn chsize(&self) -> CHSIZE_R { + CHSIZE_R::new((self.bits & 7) as u8) + } + #[doc = "Bit 6 - Stop Bit Mode"] + #[inline(always)] + pub fn sbmode(&self) -> SBMODE_R { + SBMODE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 8 - Collision Detection Enable"] + #[inline(always)] + pub fn colden(&self) -> COLDEN_R { + COLDEN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Start of Frame Detection Enable"] + #[inline(always)] + pub fn sfde(&self) -> SFDE_R { + SFDE_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Encoding Format"] + #[inline(always)] + pub fn enc(&self) -> ENC_R { + ENC_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 13 - Parity Mode"] + #[inline(always)] + pub fn pmode(&self) -> PMODE_R { + PMODE_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 16 - Transmitter Enable"] + #[inline(always)] + pub fn txen(&self) -> TXEN_R { + TXEN_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + pub fn rxen(&self) -> RXEN_R { + RXEN_R::new(((self.bits >> 17) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Character Size"] + #[inline(always)] + #[must_use] + pub fn chsize(&mut self) -> CHSIZE_W<0> { + CHSIZE_W::new(self) + } + #[doc = "Bit 6 - Stop Bit Mode"] + #[inline(always)] + #[must_use] + pub fn sbmode(&mut self) -> SBMODE_W<6> { + SBMODE_W::new(self) + } + #[doc = "Bit 8 - Collision Detection Enable"] + #[inline(always)] + #[must_use] + pub fn colden(&mut self) -> COLDEN_W<8> { + COLDEN_W::new(self) + } + #[doc = "Bit 9 - Start of Frame Detection Enable"] + #[inline(always)] + #[must_use] + pub fn sfde(&mut self) -> SFDE_W<9> { + SFDE_W::new(self) + } + #[doc = "Bit 10 - Encoding Format"] + #[inline(always)] + #[must_use] + pub fn enc(&mut self) -> ENC_W<10> { + ENC_W::new(self) + } + #[doc = "Bit 13 - Parity Mode"] + #[inline(always)] + #[must_use] + pub fn pmode(&mut self) -> PMODE_W<13> { + PMODE_W::new(self) + } + #[doc = "Bit 16 - Transmitter Enable"] + #[inline(always)] + #[must_use] + pub fn txen(&mut self) -> TXEN_W<16> { + TXEN_W::new(self) + } + #[doc = "Bit 17 - Receiver Enable"] + #[inline(always)] + #[must_use] + pub fn rxen(&mut self) -> RXEN_W<17> { + RXEN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/sercom0/usart/ctrlc.rs b/pac/atsaml22j/src/sercom0/usart/ctrlc.rs new file mode 100644 index 000000000000..5e9adea7dddd --- /dev/null +++ b/pac/atsaml22j/src/sercom0/usart/ctrlc.rs @@ -0,0 +1,125 @@ +#[doc = "Register `CTRLC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `GTIME` reader - Guard Time"] +pub type GTIME_R = crate::FieldReader; +#[doc = "Field `GTIME` writer - Guard Time"] +pub type GTIME_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRLC_SPEC, u8, u8, 3, O>; +#[doc = "Field `INACK` reader - Inhibit Not Acknowledge"] +pub type INACK_R = crate::BitReader; +#[doc = "Field `INACK` writer - Inhibit Not Acknowledge"] +pub type INACK_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLC_SPEC, bool, O>; +#[doc = "Field `DSNACK` reader - Disable Successive NACK"] +pub type DSNACK_R = crate::BitReader; +#[doc = "Field `DSNACK` writer - Disable Successive NACK"] +pub type DSNACK_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLC_SPEC, bool, O>; +#[doc = "Field `MAXITER` reader - Maximum Iterations"] +pub type MAXITER_R = crate::FieldReader; +#[doc = "Field `MAXITER` writer - Maximum Iterations"] +pub type MAXITER_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRLC_SPEC, u8, u8, 3, O>; +impl R { + #[doc = "Bits 0:2 - Guard Time"] + #[inline(always)] + pub fn gtime(&self) -> GTIME_R { + GTIME_R::new((self.bits & 7) as u8) + } + #[doc = "Bit 16 - Inhibit Not Acknowledge"] + #[inline(always)] + pub fn inack(&self) -> INACK_R { + INACK_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Disable Successive NACK"] + #[inline(always)] + pub fn dsnack(&self) -> DSNACK_R { + DSNACK_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bits 20:22 - Maximum Iterations"] + #[inline(always)] + pub fn maxiter(&self) -> MAXITER_R { + MAXITER_R::new(((self.bits >> 20) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - Guard Time"] + #[inline(always)] + #[must_use] + pub fn gtime(&mut self) -> GTIME_W<0> { + GTIME_W::new(self) + } + #[doc = "Bit 16 - Inhibit Not Acknowledge"] + #[inline(always)] + #[must_use] + pub fn inack(&mut self) -> INACK_W<16> { + INACK_W::new(self) + } + #[doc = "Bit 17 - Disable Successive NACK"] + #[inline(always)] + #[must_use] + pub fn dsnack(&mut self) -> DSNACK_W<17> { + DSNACK_W::new(self) + } + #[doc = "Bits 20:22 - Maximum Iterations"] + #[inline(always)] + #[must_use] + pub fn maxiter(&mut self) -> MAXITER_W<20> { + MAXITER_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlc](index.html) module"] +pub struct CTRLC_SPEC; +impl crate::RegisterSpec for CTRLC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrlc::R](R) reader structure"] +impl crate::Readable for CTRLC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlc::W](W) writer structure"] +impl crate::Writable for CTRLC_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRLC to value 0"] +impl crate::Resettable for CTRLC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/sercom0/usart/data.rs b/pac/atsaml22j/src/sercom0/usart/data.rs new file mode 100644 index 000000000000..547ed853f90f --- /dev/null +++ b/pac/atsaml22j/src/sercom0/usart/data.rs @@ -0,0 +1,80 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATA` reader - Data Value"] +pub type DATA_R = crate::FieldReader; +#[doc = "Field `DATA` writer - Data Value"] +pub type DATA_W<'a, const O: u8> = crate::FieldWriter<'a, u16, DATA_SPEC, u16, u16, 9, O>; +impl R { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits & 0x01ff) + } +} +impl W { + #[doc = "Bits 0:8 - Data Value"] + #[inline(always)] + #[must_use] + pub fn data(&mut self) -> DATA_W<0> { + DATA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART Data\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [data::W](W) writer structure"] +impl crate::Writable for DATA_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/sercom0/usart/dbgctrl.rs b/pac/atsaml22j/src/sercom0/usart/dbgctrl.rs new file mode 100644 index 000000000000..471bea024272 --- /dev/null +++ b/pac/atsaml22j/src/sercom0/usart/dbgctrl.rs @@ -0,0 +1,80 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGSTOP` reader - Debug Mode"] +pub type DBGSTOP_R = crate::BitReader; +#[doc = "Field `DBGSTOP` writer - Debug Mode"] +pub type DBGSTOP_W<'a, const O: u8> = crate::BitWriter<'a, u8, DBGCTRL_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + pub fn dbgstop(&self) -> DBGSTOP_R { + DBGSTOP_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Mode"] + #[inline(always)] + #[must_use] + pub fn dbgstop(&mut self) -> DBGSTOP_W<0> { + DBGSTOP_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/sercom0/usart/intenclr.rs b/pac/atsaml22j/src/sercom0/usart/intenclr.rs new file mode 100644 index 000000000000..8c2f065d7333 --- /dev/null +++ b/pac/atsaml22j/src/sercom0/usart/intenclr.rs @@ -0,0 +1,170 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Disable"] +pub type DRE_R = crate::BitReader; +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Disable"] +pub type DRE_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>; +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Disable"] +pub type TXC_R = crate::BitReader; +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Disable"] +pub type TXC_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>; +#[doc = "Field `RXC` reader - Receive Complete Interrupt Disable"] +pub type RXC_R = crate::BitReader; +#[doc = "Field `RXC` writer - Receive Complete Interrupt Disable"] +pub type RXC_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>; +#[doc = "Field `RXS` reader - Receive Start Interrupt Disable"] +pub type RXS_R = crate::BitReader; +#[doc = "Field `RXS` writer - Receive Start Interrupt Disable"] +pub type RXS_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>; +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt Disable"] +pub type CTSIC_R = crate::BitReader; +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt Disable"] +pub type CTSIC_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>; +#[doc = "Field `RXBRK` reader - Break Received Interrupt Disable"] +pub type RXBRK_R = crate::BitReader; +#[doc = "Field `RXBRK` writer - Break Received Interrupt Disable"] +pub type RXBRK_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>; +#[doc = "Field `ERROR` reader - Combined Error Interrupt Disable"] +pub type ERROR_R = crate::BitReader; +#[doc = "Field `ERROR` writer - Combined Error Interrupt Disable"] +pub type ERROR_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt Disable"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Disable"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt Disable"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Disable"] + #[inline(always)] + #[must_use] + pub fn dre(&mut self) -> DRE_W<0> { + DRE_W::new(self) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Disable"] + #[inline(always)] + #[must_use] + pub fn txc(&mut self) -> TXC_W<1> { + TXC_W::new(self) + } + #[doc = "Bit 2 - Receive Complete Interrupt Disable"] + #[inline(always)] + #[must_use] + pub fn rxc(&mut self) -> RXC_W<2> { + RXC_W::new(self) + } + #[doc = "Bit 3 - Receive Start Interrupt Disable"] + #[inline(always)] + #[must_use] + pub fn rxs(&mut self) -> RXS_W<3> { + RXS_W::new(self) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Disable"] + #[inline(always)] + #[must_use] + pub fn ctsic(&mut self) -> CTSIC_W<4> { + CTSIC_W::new(self) + } + #[doc = "Bit 5 - Break Received Interrupt Disable"] + #[inline(always)] + #[must_use] + pub fn rxbrk(&mut self) -> RXBRK_W<5> { + RXBRK_W::new(self) + } + #[doc = "Bit 7 - Combined Error Interrupt Disable"] + #[inline(always)] + #[must_use] + pub fn error(&mut self) -> ERROR_W<7> { + ERROR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/sercom0/usart/intenset.rs b/pac/atsaml22j/src/sercom0/usart/intenset.rs new file mode 100644 index 000000000000..d67049968b15 --- /dev/null +++ b/pac/atsaml22j/src/sercom0/usart/intenset.rs @@ -0,0 +1,170 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt Enable"] +pub type DRE_R = crate::BitReader; +#[doc = "Field `DRE` writer - Data Register Empty Interrupt Enable"] +pub type DRE_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENSET_SPEC, bool, O>; +#[doc = "Field `TXC` reader - Transmit Complete Interrupt Enable"] +pub type TXC_R = crate::BitReader; +#[doc = "Field `TXC` writer - Transmit Complete Interrupt Enable"] +pub type TXC_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENSET_SPEC, bool, O>; +#[doc = "Field `RXC` reader - Receive Complete Interrupt Enable"] +pub type RXC_R = crate::BitReader; +#[doc = "Field `RXC` writer - Receive Complete Interrupt Enable"] +pub type RXC_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENSET_SPEC, bool, O>; +#[doc = "Field `RXS` reader - Receive Start Interrupt Enable"] +pub type RXS_R = crate::BitReader; +#[doc = "Field `RXS` writer - Receive Start Interrupt Enable"] +pub type RXS_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENSET_SPEC, bool, O>; +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt Enable"] +pub type CTSIC_R = crate::BitReader; +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt Enable"] +pub type CTSIC_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENSET_SPEC, bool, O>; +#[doc = "Field `RXBRK` reader - Break Received Interrupt Enable"] +pub type RXBRK_R = crate::BitReader; +#[doc = "Field `RXBRK` writer - Break Received Interrupt Enable"] +pub type RXBRK_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENSET_SPEC, bool, O>; +#[doc = "Field `ERROR` reader - Combined Error Interrupt Enable"] +pub type ERROR_R = crate::BitReader; +#[doc = "Field `ERROR` writer - Combined Error Interrupt Enable"] +pub type ERROR_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENSET_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Receive Start Interrupt Enable"] + #[inline(always)] + pub fn rxs(&self) -> RXS_R { + RXS_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Enable"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt Enable"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Register Empty Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn dre(&mut self) -> DRE_W<0> { + DRE_W::new(self) + } + #[doc = "Bit 1 - Transmit Complete Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn txc(&mut self) -> TXC_W<1> { + TXC_W::new(self) + } + #[doc = "Bit 2 - Receive Complete Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn rxc(&mut self) -> RXC_W<2> { + RXC_W::new(self) + } + #[doc = "Bit 3 - Receive Start Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn rxs(&mut self) -> RXS_W<3> { + RXS_W::new(self) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn ctsic(&mut self) -> CTSIC_W<4> { + CTSIC_W::new(self) + } + #[doc = "Bit 5 - Break Received Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn rxbrk(&mut self) -> RXBRK_W<5> { + RXBRK_W::new(self) + } + #[doc = "Bit 7 - Combined Error Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn error(&mut self) -> ERROR_W<7> { + ERROR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/sercom0/usart/intflag.rs b/pac/atsaml22j/src/sercom0/usart/intflag.rs new file mode 100644 index 000000000000..25a790b1fd25 --- /dev/null +++ b/pac/atsaml22j/src/sercom0/usart/intflag.rs @@ -0,0 +1,147 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DRE` reader - Data Register Empty Interrupt"] +pub type DRE_R = crate::BitReader; +#[doc = "Field `TXC` reader - Transmit Complete Interrupt"] +pub type TXC_R = crate::BitReader; +#[doc = "Field `TXC` writer - Transmit Complete Interrupt"] +pub type TXC_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTFLAG_SPEC, bool, O>; +#[doc = "Field `RXC` reader - Receive Complete Interrupt"] +pub type RXC_R = crate::BitReader; +#[doc = "Field `RXS` writer - Receive Start Interrupt"] +pub type RXS_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTFLAG_SPEC, bool, O>; +#[doc = "Field `CTSIC` reader - Clear To Send Input Change Interrupt"] +pub type CTSIC_R = crate::BitReader; +#[doc = "Field `CTSIC` writer - Clear To Send Input Change Interrupt"] +pub type CTSIC_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTFLAG_SPEC, bool, O>; +#[doc = "Field `RXBRK` reader - Break Received Interrupt"] +pub type RXBRK_R = crate::BitReader; +#[doc = "Field `RXBRK` writer - Break Received Interrupt"] +pub type RXBRK_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTFLAG_SPEC, bool, O>; +#[doc = "Field `ERROR` reader - Combined Error Interrupt"] +pub type ERROR_R = crate::BitReader; +#[doc = "Field `ERROR` writer - Combined Error Interrupt"] +pub type ERROR_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTFLAG_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Data Register Empty Interrupt"] + #[inline(always)] + pub fn dre(&self) -> DRE_R { + DRE_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + pub fn txc(&self) -> TXC_R { + TXC_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Receive Complete Interrupt"] + #[inline(always)] + pub fn rxc(&self) -> RXC_R { + RXC_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt"] + #[inline(always)] + pub fn ctsic(&self) -> CTSIC_R { + CTSIC_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Break Received Interrupt"] + #[inline(always)] + pub fn rxbrk(&self) -> RXBRK_R { + RXBRK_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + pub fn error(&self) -> ERROR_R { + ERROR_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Transmit Complete Interrupt"] + #[inline(always)] + #[must_use] + pub fn txc(&mut self) -> TXC_W<1> { + TXC_W::new(self) + } + #[doc = "Bit 3 - Receive Start Interrupt"] + #[inline(always)] + #[must_use] + pub fn rxs(&mut self) -> RXS_W<3> { + RXS_W::new(self) + } + #[doc = "Bit 4 - Clear To Send Input Change Interrupt"] + #[inline(always)] + #[must_use] + pub fn ctsic(&mut self) -> CTSIC_W<4> { + CTSIC_W::new(self) + } + #[doc = "Bit 5 - Break Received Interrupt"] + #[inline(always)] + #[must_use] + pub fn rxbrk(&mut self) -> RXBRK_W<5> { + RXBRK_W::new(self) + } + #[doc = "Bit 7 - Combined Error Interrupt"] + #[inline(always)] + #[must_use] + pub fn error(&mut self) -> ERROR_W<7> { + ERROR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/sercom0/usart/rxerrcnt.rs b/pac/atsaml22j/src/sercom0/usart/rxerrcnt.rs new file mode 100644 index 000000000000..77ec67f2e864 --- /dev/null +++ b/pac/atsaml22j/src/sercom0/usart/rxerrcnt.rs @@ -0,0 +1,28 @@ +#[doc = "Register `RXERRCNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "USART Receive Error Count\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxerrcnt](index.html) module"] +pub struct RXERRCNT_SPEC; +impl crate::RegisterSpec for RXERRCNT_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [rxerrcnt::R](R) reader structure"] +impl crate::Readable for RXERRCNT_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets RXERRCNT to value 0"] +impl crate::Resettable for RXERRCNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/sercom0/usart/rxpl.rs b/pac/atsaml22j/src/sercom0/usart/rxpl.rs new file mode 100644 index 000000000000..4f0fc2e4eaa4 --- /dev/null +++ b/pac/atsaml22j/src/sercom0/usart/rxpl.rs @@ -0,0 +1,80 @@ +#[doc = "Register `RXPL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `RXPL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `RXPL` reader - Receive Pulse Length"] +pub type RXPL_R = crate::FieldReader; +#[doc = "Field `RXPL` writer - Receive Pulse Length"] +pub type RXPL_W<'a, const O: u8> = crate::FieldWriter<'a, u8, RXPL_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Receive Pulse Length"] + #[inline(always)] + pub fn rxpl(&self) -> RXPL_R { + RXPL_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:7 - Receive Pulse Length"] + #[inline(always)] + #[must_use] + pub fn rxpl(&mut self) -> RXPL_W<0> { + RXPL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART Receive Pulse Length\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxpl](index.html) module"] +pub struct RXPL_SPEC; +impl crate::RegisterSpec for RXPL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [rxpl::R](R) reader structure"] +impl crate::Readable for RXPL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [rxpl::W](W) writer structure"] +impl crate::Writable for RXPL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets RXPL to value 0"] +impl crate::Resettable for RXPL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/sercom0/usart/status.rs b/pac/atsaml22j/src/sercom0/usart/status.rs new file mode 100644 index 000000000000..ebf6c0e83c9c --- /dev/null +++ b/pac/atsaml22j/src/sercom0/usart/status.rs @@ -0,0 +1,169 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PERR` reader - Parity Error"] +pub type PERR_R = crate::BitReader; +#[doc = "Field `PERR` writer - Parity Error"] +pub type PERR_W<'a, const O: u8> = crate::BitWriter<'a, u16, STATUS_SPEC, bool, O>; +#[doc = "Field `FERR` reader - Frame Error"] +pub type FERR_R = crate::BitReader; +#[doc = "Field `FERR` writer - Frame Error"] +pub type FERR_W<'a, const O: u8> = crate::BitWriter<'a, u16, STATUS_SPEC, bool, O>; +#[doc = "Field `BUFOVF` reader - Buffer Overflow"] +pub type BUFOVF_R = crate::BitReader; +#[doc = "Field `BUFOVF` writer - Buffer Overflow"] +pub type BUFOVF_W<'a, const O: u8> = crate::BitWriter<'a, u16, STATUS_SPEC, bool, O>; +#[doc = "Field `CTS` reader - Clear To Send"] +pub type CTS_R = crate::BitReader; +#[doc = "Field `ISF` reader - Inconsistent Sync Field"] +pub type ISF_R = crate::BitReader; +#[doc = "Field `ISF` writer - Inconsistent Sync Field"] +pub type ISF_W<'a, const O: u8> = crate::BitWriter<'a, u16, STATUS_SPEC, bool, O>; +#[doc = "Field `COLL` reader - Collision Detected"] +pub type COLL_R = crate::BitReader; +#[doc = "Field `COLL` writer - Collision Detected"] +pub type COLL_W<'a, const O: u8> = crate::BitWriter<'a, u16, STATUS_SPEC, bool, O>; +#[doc = "Field `TXE` reader - Transmitter Empty"] +pub type TXE_R = crate::BitReader; +#[doc = "Field `ITER` reader - Maximum Number of Repetitions Reached"] +pub type ITER_R = crate::BitReader; +#[doc = "Field `ITER` writer - Maximum Number of Repetitions Reached"] +pub type ITER_W<'a, const O: u8> = crate::BitWriter<'a, u16, STATUS_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Parity Error"] + #[inline(always)] + pub fn perr(&self) -> PERR_R { + PERR_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Frame Error"] + #[inline(always)] + pub fn ferr(&self) -> FERR_R { + FERR_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + pub fn bufovf(&self) -> BUFOVF_R { + BUFOVF_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Clear To Send"] + #[inline(always)] + pub fn cts(&self) -> CTS_R { + CTS_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Inconsistent Sync Field"] + #[inline(always)] + pub fn isf(&self) -> ISF_R { + ISF_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Collision Detected"] + #[inline(always)] + pub fn coll(&self) -> COLL_R { + COLL_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Transmitter Empty"] + #[inline(always)] + pub fn txe(&self) -> TXE_R { + TXE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Maximum Number of Repetitions Reached"] + #[inline(always)] + pub fn iter(&self) -> ITER_R { + ITER_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Parity Error"] + #[inline(always)] + #[must_use] + pub fn perr(&mut self) -> PERR_W<0> { + PERR_W::new(self) + } + #[doc = "Bit 1 - Frame Error"] + #[inline(always)] + #[must_use] + pub fn ferr(&mut self) -> FERR_W<1> { + FERR_W::new(self) + } + #[doc = "Bit 2 - Buffer Overflow"] + #[inline(always)] + #[must_use] + pub fn bufovf(&mut self) -> BUFOVF_W<2> { + BUFOVF_W::new(self) + } + #[doc = "Bit 4 - Inconsistent Sync Field"] + #[inline(always)] + #[must_use] + pub fn isf(&mut self) -> ISF_W<4> { + ISF_W::new(self) + } + #[doc = "Bit 5 - Collision Detected"] + #[inline(always)] + #[must_use] + pub fn coll(&mut self) -> COLL_W<5> { + COLL_W::new(self) + } + #[doc = "Bit 7 - Maximum Number of Repetitions Reached"] + #[inline(always)] + #[must_use] + pub fn iter(&mut self) -> ITER_W<7> { + ITER_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USART Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/sercom0/usart/syncbusy.rs b/pac/atsaml22j/src/sercom0/usart/syncbusy.rs new file mode 100644 index 000000000000..59e38e2193c3 --- /dev/null +++ b/pac/atsaml22j/src/sercom0/usart/syncbusy.rs @@ -0,0 +1,51 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub type SWRST_R = crate::BitReader; +#[doc = "Field `ENABLE` reader - SERCOM Enable Synchronization Busy"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `CTRLB` reader - CTRLB Synchronization Busy"] +pub type CTRLB_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - SERCOM Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - CTRLB Synchronization Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 1) != 0) + } +} +#[doc = "USART Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/slcd.rs b/pac/atsaml22j/src/slcd.rs new file mode 100644 index 000000000000..e4e618d0fc58 --- /dev/null +++ b/pac/atsaml22j/src/slcd.rs @@ -0,0 +1,249 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: CTRLA, + #[doc = "0x04 - Control B"] + pub ctrlb: CTRLB, + #[doc = "0x06 - Control C"] + pub ctrlc: CTRLC, + #[doc = "0x08 - Control D"] + pub ctrld: CTRLD, + _reserved4: [u8; 0x03], + #[doc = "0x0c - Event Control"] + pub evctrl: EVCTRL, + #[doc = "0x0d - Interrupt Enable Clear"] + pub intenclr: INTENCLR, + #[doc = "0x0e - Interrupt Enable Set"] + pub intenset: INTENSET, + #[doc = "0x0f - Interrupt Flag Status and Clear"] + pub intflag: INTFLAG, + #[doc = "0x10 - Status"] + pub status: STATUS, + _reserved9: [u8; 0x03], + #[doc = "0x14 - Synchronization Busy"] + pub syncbusy: SYNCBUSY, + #[doc = "0x18 - Frame Counter 0 Configuration"] + pub fc0: FC0, + #[doc = "0x19 - Frame Counter 1 Configuration"] + pub fc1: FC1, + #[doc = "0x1a - Frame Counter 2 Configuration"] + pub fc2: FC2, + _reserved13: [u8; 0x01], + #[doc = "0x1c - LCD Pin Enable Low"] + pub lpenl: LPENL, + #[doc = "0x20 - LCD Pin Enable High"] + pub lpenh: LPENH, + #[doc = "0x24 - Segments Data Low for COM0 Line"] + pub sdatal0: SDATAL0, + #[doc = "0x28 - Segments Data High for COM0 Line"] + pub sdatah0: SDATAH0, + #[doc = "0x2c - Segments Data Low for COM1 Line"] + pub sdatal1: SDATAL1, + #[doc = "0x30 - Segments Data High for COM1 Line"] + pub sdatah1: SDATAH1, + #[doc = "0x34 - Segments Data Low for COM2 Line"] + pub sdatal2: SDATAL2, + #[doc = "0x38 - Segments Data High for COM2 Line"] + pub sdatah2: SDATAH2, + #[doc = "0x3c - Segments Data Low for COM3 Line"] + pub sdatal3: SDATAL3, + #[doc = "0x40 - Segments Data High for COM3 Line"] + pub sdatah3: SDATAH3, + #[doc = "0x44 - Segments Data Low for COM4 Line"] + pub sdatal4: SDATAL4, + #[doc = "0x48 - Segments Data High for COM4 Line"] + pub sdatah4: SDATAH4, + #[doc = "0x4c - Segments Data Low for COM5 Line"] + pub sdatal5: SDATAL5, + #[doc = "0x50 - Segments Data High for COM5 Line"] + pub sdatah5: SDATAH5, + #[doc = "0x54 - Segments Data Low for COM6 Line"] + pub sdatal6: SDATAL6, + #[doc = "0x58 - Segments Data High for COM6 Line"] + pub sdatah6: SDATAH6, + #[doc = "0x5c - Segments Data Low for COM7 Line"] + pub sdatal7: SDATAL7, + #[doc = "0x60 - Segments Data High for COM7 Line"] + pub sdatah7: SDATAH7, + #[doc = "0x64 - Indirect Segments Data Access"] + pub isdata: ISDATA, + #[doc = "0x68 - Blink Configuration"] + pub bcfg: BCFG, + #[doc = "0x6c - Circular Shift Register Configuration"] + pub csrcfg: CSRCFG, + #[doc = "0x70 - Character Mapping Configuration"] + pub cmcfg: CMCFG, + _reserved35: [u8; 0x03], + #[doc = "0x74 - Automated Character Mapping Configuration"] + pub acmcfg: ACMCFG, + #[doc = "0x78 - Automated Bit Mapping Configuration"] + pub abmcfg: ABMCFG, + _reserved37: [u8; 0x03], + #[doc = "0x7c - Character Mapping Segments Data"] + pub cmdata: CMDATA, + #[doc = "0x80 - Character Mapping Segments Data Mask"] + pub cmdmask: CMDMASK, + #[doc = "0x84 - Character Mapping SEG/COM Index"] + pub cmindex: CMINDEX, +} +#[doc = "CTRLA (rw) register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLB (rw) register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "Control B"] +pub mod ctrlb; +#[doc = "CTRLC (rw) register accessor: an alias for `Reg`"] +pub type CTRLC = crate::Reg; +#[doc = "Control C"] +pub mod ctrlc; +#[doc = "CTRLD (rw) register accessor: an alias for `Reg`"] +pub type CTRLD = crate::Reg; +#[doc = "Control D"] +pub mod ctrld; +#[doc = "EVCTRL (rw) register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR (rw) register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET (rw) register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG (rw) register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS (r) register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "SYNCBUSY (r) register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; +#[doc = "FC0 (rw) register accessor: an alias for `Reg`"] +pub type FC0 = crate::Reg; +#[doc = "Frame Counter 0 Configuration"] +pub mod fc0; +#[doc = "FC1 (rw) register accessor: an alias for `Reg`"] +pub type FC1 = crate::Reg; +#[doc = "Frame Counter 1 Configuration"] +pub mod fc1; +#[doc = "FC2 (rw) register accessor: an alias for `Reg`"] +pub type FC2 = crate::Reg; +#[doc = "Frame Counter 2 Configuration"] +pub mod fc2; +#[doc = "LPENL (rw) register accessor: an alias for `Reg`"] +pub type LPENL = crate::Reg; +#[doc = "LCD Pin Enable Low"] +pub mod lpenl; +#[doc = "LPENH (rw) register accessor: an alias for `Reg`"] +pub type LPENH = crate::Reg; +#[doc = "LCD Pin Enable High"] +pub mod lpenh; +#[doc = "SDATAL0 (rw) register accessor: an alias for `Reg`"] +pub type SDATAL0 = crate::Reg; +#[doc = "Segments Data Low for COM0 Line"] +pub mod sdatal0; +#[doc = "SDATAH0 (rw) register accessor: an alias for `Reg`"] +pub type SDATAH0 = crate::Reg; +#[doc = "Segments Data High for COM0 Line"] +pub mod sdatah0; +#[doc = "SDATAL1 (rw) register accessor: an alias for `Reg`"] +pub type SDATAL1 = crate::Reg; +#[doc = "Segments Data Low for COM1 Line"] +pub mod sdatal1; +#[doc = "SDATAH1 (rw) register accessor: an alias for `Reg`"] +pub type SDATAH1 = crate::Reg; +#[doc = "Segments Data High for COM1 Line"] +pub mod sdatah1; +#[doc = "SDATAL2 (rw) register accessor: an alias for `Reg`"] +pub type SDATAL2 = crate::Reg; +#[doc = "Segments Data Low for COM2 Line"] +pub mod sdatal2; +#[doc = "SDATAH2 (rw) register accessor: an alias for `Reg`"] +pub type SDATAH2 = crate::Reg; +#[doc = "Segments Data High for COM2 Line"] +pub mod sdatah2; +#[doc = "SDATAL3 (rw) register accessor: an alias for `Reg`"] +pub type SDATAL3 = crate::Reg; +#[doc = "Segments Data Low for COM3 Line"] +pub mod sdatal3; +#[doc = "SDATAH3 (rw) register accessor: an alias for `Reg`"] +pub type SDATAH3 = crate::Reg; +#[doc = "Segments Data High for COM3 Line"] +pub mod sdatah3; +#[doc = "SDATAL4 (rw) register accessor: an alias for `Reg`"] +pub type SDATAL4 = crate::Reg; +#[doc = "Segments Data Low for COM4 Line"] +pub mod sdatal4; +#[doc = "SDATAH4 (rw) register accessor: an alias for `Reg`"] +pub type SDATAH4 = crate::Reg; +#[doc = "Segments Data High for COM4 Line"] +pub mod sdatah4; +#[doc = "SDATAL5 (rw) register accessor: an alias for `Reg`"] +pub type SDATAL5 = crate::Reg; +#[doc = "Segments Data Low for COM5 Line"] +pub mod sdatal5; +#[doc = "SDATAH5 (rw) register accessor: an alias for `Reg`"] +pub type SDATAH5 = crate::Reg; +#[doc = "Segments Data High for COM5 Line"] +pub mod sdatah5; +#[doc = "SDATAL6 (rw) register accessor: an alias for `Reg`"] +pub type SDATAL6 = crate::Reg; +#[doc = "Segments Data Low for COM6 Line"] +pub mod sdatal6; +#[doc = "SDATAH6 (rw) register accessor: an alias for `Reg`"] +pub type SDATAH6 = crate::Reg; +#[doc = "Segments Data High for COM6 Line"] +pub mod sdatah6; +#[doc = "SDATAL7 (rw) register accessor: an alias for `Reg`"] +pub type SDATAL7 = crate::Reg; +#[doc = "Segments Data Low for COM7 Line"] +pub mod sdatal7; +#[doc = "SDATAH7 (rw) register accessor: an alias for `Reg`"] +pub type SDATAH7 = crate::Reg; +#[doc = "Segments Data High for COM7 Line"] +pub mod sdatah7; +#[doc = "ISDATA (w) register accessor: an alias for `Reg`"] +pub type ISDATA = crate::Reg; +#[doc = "Indirect Segments Data Access"] +pub mod isdata; +#[doc = "BCFG (rw) register accessor: an alias for `Reg`"] +pub type BCFG = crate::Reg; +#[doc = "Blink Configuration"] +pub mod bcfg; +#[doc = "CSRCFG (rw) register accessor: an alias for `Reg`"] +pub type CSRCFG = crate::Reg; +#[doc = "Circular Shift Register Configuration"] +pub mod csrcfg; +#[doc = "CMCFG (rw) register accessor: an alias for `Reg`"] +pub type CMCFG = crate::Reg; +#[doc = "Character Mapping Configuration"] +pub mod cmcfg; +#[doc = "ACMCFG (rw) register accessor: an alias for `Reg`"] +pub type ACMCFG = crate::Reg; +#[doc = "Automated Character Mapping Configuration"] +pub mod acmcfg; +#[doc = "ABMCFG (rw) register accessor: an alias for `Reg`"] +pub type ABMCFG = crate::Reg; +#[doc = "Automated Bit Mapping Configuration"] +pub mod abmcfg; +#[doc = "CMDATA (w) register accessor: an alias for `Reg`"] +pub type CMDATA = crate::Reg; +#[doc = "Character Mapping Segments Data"] +pub mod cmdata; +#[doc = "CMDMASK (rw) register accessor: an alias for `Reg`"] +pub type CMDMASK = crate::Reg; +#[doc = "Character Mapping Segments Data Mask"] +pub mod cmdmask; +#[doc = "CMINDEX (rw) register accessor: an alias for `Reg`"] +pub type CMINDEX = crate::Reg; +#[doc = "Character Mapping SEG/COM Index"] +pub mod cmindex; diff --git a/pac/atsaml22j/src/slcd/abmcfg.rs b/pac/atsaml22j/src/slcd/abmcfg.rs new file mode 100644 index 000000000000..b6ac068949e1 --- /dev/null +++ b/pac/atsaml22j/src/slcd/abmcfg.rs @@ -0,0 +1,156 @@ +#[doc = "Register `ABMCFG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ABMCFG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FCS` reader - Frame Counter Selection"] +pub type FCS_R = crate::FieldReader; +#[doc = "Frame Counter Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FCSSELECT_A { + #[doc = "0: Frame Counter 0"] + FC0 = 0, + #[doc = "1: Frame Counter 1"] + FC1 = 1, + #[doc = "2: Frame Counter 2"] + FC2 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FCSSELECT_A) -> Self { + variant as _ + } +} +impl FCS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FCSSELECT_A::FC0), + 1 => Some(FCSSELECT_A::FC1), + 2 => Some(FCSSELECT_A::FC2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `FC0`"] + #[inline(always)] + pub fn is_fc0(&self) -> bool { + *self == FCSSELECT_A::FC0 + } + #[doc = "Checks if the value of the field is `FC1`"] + #[inline(always)] + pub fn is_fc1(&self) -> bool { + *self == FCSSELECT_A::FC1 + } + #[doc = "Checks if the value of the field is `FC2`"] + #[inline(always)] + pub fn is_fc2(&self) -> bool { + *self == FCSSELECT_A::FC2 + } +} +#[doc = "Field `FCS` writer - Frame Counter Selection"] +pub type FCS_W<'a, const O: u8> = crate::FieldWriter<'a, u8, ABMCFG_SPEC, u8, FCSSELECT_A, 2, O>; +impl<'a, const O: u8> FCS_W<'a, O> { + #[doc = "Frame Counter 0"] + #[inline(always)] + pub fn fc0(self) -> &'a mut W { + self.variant(FCSSELECT_A::FC0) + } + #[doc = "Frame Counter 1"] + #[inline(always)] + pub fn fc1(self) -> &'a mut W { + self.variant(FCSSELECT_A::FC1) + } + #[doc = "Frame Counter 2"] + #[inline(always)] + pub fn fc2(self) -> &'a mut W { + self.variant(FCSSELECT_A::FC2) + } +} +#[doc = "Field `SIZE` reader - Size"] +pub type SIZE_R = crate::FieldReader; +#[doc = "Field `SIZE` writer - Size"] +pub type SIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u8, ABMCFG_SPEC, u8, u8, 6, O>; +impl R { + #[doc = "Bits 0:1 - Frame Counter Selection"] + #[inline(always)] + pub fn fcs(&self) -> FCS_R { + FCS_R::new(self.bits & 3) + } + #[doc = "Bits 2:7 - Size"] + #[inline(always)] + pub fn size(&self) -> SIZE_R { + SIZE_R::new((self.bits >> 2) & 0x3f) + } +} +impl W { + #[doc = "Bits 0:1 - Frame Counter Selection"] + #[inline(always)] + #[must_use] + pub fn fcs(&mut self) -> FCS_W<0> { + FCS_W::new(self) + } + #[doc = "Bits 2:7 - Size"] + #[inline(always)] + #[must_use] + pub fn size(&mut self) -> SIZE_W<2> { + SIZE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Automated Bit Mapping Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [abmcfg](index.html) module"] +pub struct ABMCFG_SPEC; +impl crate::RegisterSpec for ABMCFG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [abmcfg::R](R) reader structure"] +impl crate::Readable for ABMCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [abmcfg::W](W) writer structure"] +impl crate::Writable for ABMCFG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ABMCFG to value 0"] +impl crate::Resettable for ABMCFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/slcd/acmcfg.rs b/pac/atsaml22j/src/slcd/acmcfg.rs new file mode 100644 index 000000000000..35166c49ea21 --- /dev/null +++ b/pac/atsaml22j/src/slcd/acmcfg.rs @@ -0,0 +1,277 @@ +#[doc = "Register `ACMCFG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `ACMCFG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `NCOM` reader - COM Lines per Row"] +pub type NCOM_R = crate::FieldReader; +#[doc = "Field `NCOM` writer - COM Lines per Row"] +pub type NCOM_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ACMCFG_SPEC, u8, u8, 3, O>; +#[doc = "Field `NDIG` reader - Number of Digit"] +pub type NDIG_R = crate::FieldReader; +#[doc = "Field `NDIG` writer - Number of Digit"] +pub type NDIG_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ACMCFG_SPEC, u8, u8, 4, O>; +#[doc = "Field `STEPS` reader - Scrolling Steps"] +pub type STEPS_R = crate::FieldReader; +#[doc = "Field `STEPS` writer - Scrolling Steps"] +pub type STEPS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ACMCFG_SPEC, u8, u8, 8, O>; +#[doc = "Field `NDROW` reader - Number of Digit per Row"] +pub type NDROW_R = crate::FieldReader; +#[doc = "Field `NDROW` writer - Number of Digit per Row"] +pub type NDROW_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ACMCFG_SPEC, u8, u8, 6, O>; +#[doc = "Field `MODE` reader - Mode"] +pub type MODE_R = crate::BitReader; +#[doc = "Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum MODESELECT_A { + #[doc = "0: Sequential Display Mode"] + SEQ = 0, + #[doc = "1: Scrolling Display Mode"] + SCROLL = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: MODESELECT_A) -> Self { + variant as u8 != 0 + } +} +impl MODE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> MODESELECT_A { + match self.bits { + false => MODESELECT_A::SEQ, + true => MODESELECT_A::SCROLL, + } + } + #[doc = "Checks if the value of the field is `SEQ`"] + #[inline(always)] + pub fn is_seq(&self) -> bool { + *self == MODESELECT_A::SEQ + } + #[doc = "Checks if the value of the field is `SCROLL`"] + #[inline(always)] + pub fn is_scroll(&self) -> bool { + *self == MODESELECT_A::SCROLL + } +} +#[doc = "Field `MODE` writer - Mode"] +pub type MODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, ACMCFG_SPEC, MODESELECT_A, O>; +impl<'a, const O: u8> MODE_W<'a, O> { + #[doc = "Sequential Display Mode"] + #[inline(always)] + pub fn seq(self) -> &'a mut W { + self.variant(MODESELECT_A::SEQ) + } + #[doc = "Scrolling Display Mode"] + #[inline(always)] + pub fn scroll(self) -> &'a mut W { + self.variant(MODESELECT_A::SCROLL) + } +} +#[doc = "Field `STSEG` reader - Start SEG Line"] +pub type STSEG_R = crate::FieldReader; +#[doc = "Field `STSEG` writer - Start SEG Line"] +pub type STSEG_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ACMCFG_SPEC, u8, u8, 6, O>; +#[doc = "Field `FCS` reader - Frame Counter Selection"] +pub type FCS_R = crate::FieldReader; +#[doc = "Frame Counter Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FCSSELECT_A { + #[doc = "0: Frame Counter 0"] + FC0 = 0, + #[doc = "1: Frame Counter 1"] + FC1 = 1, + #[doc = "2: Frame Counter 2"] + FC2 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FCSSELECT_A) -> Self { + variant as _ + } +} +impl FCS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FCSSELECT_A::FC0), + 1 => Some(FCSSELECT_A::FC1), + 2 => Some(FCSSELECT_A::FC2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `FC0`"] + #[inline(always)] + pub fn is_fc0(&self) -> bool { + *self == FCSSELECT_A::FC0 + } + #[doc = "Checks if the value of the field is `FC1`"] + #[inline(always)] + pub fn is_fc1(&self) -> bool { + *self == FCSSELECT_A::FC1 + } + #[doc = "Checks if the value of the field is `FC2`"] + #[inline(always)] + pub fn is_fc2(&self) -> bool { + *self == FCSSELECT_A::FC2 + } +} +#[doc = "Field `FCS` writer - Frame Counter Selection"] +pub type FCS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ACMCFG_SPEC, u8, FCSSELECT_A, 2, O>; +impl<'a, const O: u8> FCS_W<'a, O> { + #[doc = "Frame Counter 0"] + #[inline(always)] + pub fn fc0(self) -> &'a mut W { + self.variant(FCSSELECT_A::FC0) + } + #[doc = "Frame Counter 1"] + #[inline(always)] + pub fn fc1(self) -> &'a mut W { + self.variant(FCSSELECT_A::FC1) + } + #[doc = "Frame Counter 2"] + #[inline(always)] + pub fn fc2(self) -> &'a mut W { + self.variant(FCSSELECT_A::FC2) + } +} +impl R { + #[doc = "Bits 0:2 - COM Lines per Row"] + #[inline(always)] + pub fn ncom(&self) -> NCOM_R { + NCOM_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 4:7 - Number of Digit"] + #[inline(always)] + pub fn ndig(&self) -> NDIG_R { + NDIG_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:15 - Scrolling Steps"] + #[inline(always)] + pub fn steps(&self) -> STEPS_R { + STEPS_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:21 - Number of Digit per Row"] + #[inline(always)] + pub fn ndrow(&self) -> NDROW_R { + NDROW_R::new(((self.bits >> 16) & 0x3f) as u8) + } + #[doc = "Bit 23 - Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bits 24:29 - Start SEG Line"] + #[inline(always)] + pub fn stseg(&self) -> STSEG_R { + STSEG_R::new(((self.bits >> 24) & 0x3f) as u8) + } + #[doc = "Bits 30:31 - Frame Counter Selection"] + #[inline(always)] + pub fn fcs(&self) -> FCS_R { + FCS_R::new(((self.bits >> 30) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:2 - COM Lines per Row"] + #[inline(always)] + #[must_use] + pub fn ncom(&mut self) -> NCOM_W<0> { + NCOM_W::new(self) + } + #[doc = "Bits 4:7 - Number of Digit"] + #[inline(always)] + #[must_use] + pub fn ndig(&mut self) -> NDIG_W<4> { + NDIG_W::new(self) + } + #[doc = "Bits 8:15 - Scrolling Steps"] + #[inline(always)] + #[must_use] + pub fn steps(&mut self) -> STEPS_W<8> { + STEPS_W::new(self) + } + #[doc = "Bits 16:21 - Number of Digit per Row"] + #[inline(always)] + #[must_use] + pub fn ndrow(&mut self) -> NDROW_W<16> { + NDROW_W::new(self) + } + #[doc = "Bit 23 - Mode"] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> MODE_W<23> { + MODE_W::new(self) + } + #[doc = "Bits 24:29 - Start SEG Line"] + #[inline(always)] + #[must_use] + pub fn stseg(&mut self) -> STSEG_W<24> { + STSEG_W::new(self) + } + #[doc = "Bits 30:31 - Frame Counter Selection"] + #[inline(always)] + #[must_use] + pub fn fcs(&mut self) -> FCS_W<30> { + FCS_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Automated Character Mapping Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [acmcfg](index.html) module"] +pub struct ACMCFG_SPEC; +impl crate::RegisterSpec for ACMCFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [acmcfg::R](R) reader structure"] +impl crate::Readable for ACMCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [acmcfg::W](W) writer structure"] +impl crate::Writable for ACMCFG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ACMCFG to value 0"] +impl crate::Resettable for ACMCFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/slcd/bcfg.rs b/pac/atsaml22j/src/slcd/bcfg.rs new file mode 100644 index 000000000000..4c9374bd8cf8 --- /dev/null +++ b/pac/atsaml22j/src/slcd/bcfg.rs @@ -0,0 +1,232 @@ +#[doc = "Register `BCFG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BCFG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `MODE` reader - Blinking Mode"] +pub type MODE_R = crate::BitReader; +#[doc = "Blinking Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum MODESELECT_A { + #[doc = "0: Blink all segments"] + BLINKALL = 0, + #[doc = "1: Blink selected segments"] + BLINKSEL = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: MODESELECT_A) -> Self { + variant as u8 != 0 + } +} +impl MODE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> MODESELECT_A { + match self.bits { + false => MODESELECT_A::BLINKALL, + true => MODESELECT_A::BLINKSEL, + } + } + #[doc = "Checks if the value of the field is `BLINKALL`"] + #[inline(always)] + pub fn is_blinkall(&self) -> bool { + *self == MODESELECT_A::BLINKALL + } + #[doc = "Checks if the value of the field is `BLINKSEL`"] + #[inline(always)] + pub fn is_blinksel(&self) -> bool { + *self == MODESELECT_A::BLINKSEL + } +} +#[doc = "Field `MODE` writer - Blinking Mode"] +pub type MODE_W<'a, const O: u8> = crate::BitWriter<'a, u32, BCFG_SPEC, MODESELECT_A, O>; +impl<'a, const O: u8> MODE_W<'a, O> { + #[doc = "Blink all segments"] + #[inline(always)] + pub fn blinkall(self) -> &'a mut W { + self.variant(MODESELECT_A::BLINKALL) + } + #[doc = "Blink selected segments"] + #[inline(always)] + pub fn blinksel(self) -> &'a mut W { + self.variant(MODESELECT_A::BLINKSEL) + } +} +#[doc = "Field `FCS` reader - Frame Counter Selection"] +pub type FCS_R = crate::FieldReader; +#[doc = "Frame Counter Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FCSSELECT_A { + #[doc = "0: Frame Counter 0"] + FC0 = 0, + #[doc = "1: Frame Counter 1"] + FC1 = 1, + #[doc = "2: Frame Counter 2"] + FC2 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FCSSELECT_A) -> Self { + variant as _ + } +} +impl FCS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FCSSELECT_A::FC0), + 1 => Some(FCSSELECT_A::FC1), + 2 => Some(FCSSELECT_A::FC2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `FC0`"] + #[inline(always)] + pub fn is_fc0(&self) -> bool { + *self == FCSSELECT_A::FC0 + } + #[doc = "Checks if the value of the field is `FC1`"] + #[inline(always)] + pub fn is_fc1(&self) -> bool { + *self == FCSSELECT_A::FC1 + } + #[doc = "Checks if the value of the field is `FC2`"] + #[inline(always)] + pub fn is_fc2(&self) -> bool { + *self == FCSSELECT_A::FC2 + } +} +#[doc = "Field `FCS` writer - Frame Counter Selection"] +pub type FCS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, BCFG_SPEC, u8, FCSSELECT_A, 2, O>; +impl<'a, const O: u8> FCS_W<'a, O> { + #[doc = "Frame Counter 0"] + #[inline(always)] + pub fn fc0(self) -> &'a mut W { + self.variant(FCSSELECT_A::FC0) + } + #[doc = "Frame Counter 1"] + #[inline(always)] + pub fn fc1(self) -> &'a mut W { + self.variant(FCSSELECT_A::FC1) + } + #[doc = "Frame Counter 2"] + #[inline(always)] + pub fn fc2(self) -> &'a mut W { + self.variant(FCSSELECT_A::FC2) + } +} +#[doc = "Field `BSS0` reader - Blink Segment Selection 0"] +pub type BSS0_R = crate::FieldReader; +#[doc = "Field `BSS0` writer - Blink Segment Selection 0"] +pub type BSS0_W<'a, const O: u8> = crate::FieldWriter<'a, u32, BCFG_SPEC, u8, u8, 8, O>; +#[doc = "Field `BSS1` reader - Blink Segment Selection 1"] +pub type BSS1_R = crate::FieldReader; +#[doc = "Field `BSS1` writer - Blink Segment Selection 1"] +pub type BSS1_W<'a, const O: u8> = crate::FieldWriter<'a, u32, BCFG_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bit 0 - Blinking Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:2 - Frame Counter Selection"] + #[inline(always)] + pub fn fcs(&self) -> FCS_R { + FCS_R::new(((self.bits >> 1) & 3) as u8) + } + #[doc = "Bits 8:15 - Blink Segment Selection 0"] + #[inline(always)] + pub fn bss0(&self) -> BSS0_R { + BSS0_R::new(((self.bits >> 8) & 0xff) as u8) + } + #[doc = "Bits 16:23 - Blink Segment Selection 1"] + #[inline(always)] + pub fn bss1(&self) -> BSS1_R { + BSS1_R::new(((self.bits >> 16) & 0xff) as u8) + } +} +impl W { + #[doc = "Bit 0 - Blinking Mode"] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> MODE_W<0> { + MODE_W::new(self) + } + #[doc = "Bits 1:2 - Frame Counter Selection"] + #[inline(always)] + #[must_use] + pub fn fcs(&mut self) -> FCS_W<1> { + FCS_W::new(self) + } + #[doc = "Bits 8:15 - Blink Segment Selection 0"] + #[inline(always)] + #[must_use] + pub fn bss0(&mut self) -> BSS0_W<8> { + BSS0_W::new(self) + } + #[doc = "Bits 16:23 - Blink Segment Selection 1"] + #[inline(always)] + #[must_use] + pub fn bss1(&mut self) -> BSS1_W<16> { + BSS1_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Blink Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bcfg](index.html) module"] +pub struct BCFG_SPEC; +impl crate::RegisterSpec for BCFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [bcfg::R](R) reader structure"] +impl crate::Readable for BCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [bcfg::W](W) writer structure"] +impl crate::Writable for BCFG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BCFG to value 0"] +impl crate::Resettable for BCFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/slcd/cmcfg.rs b/pac/atsaml22j/src/slcd/cmcfg.rs new file mode 100644 index 000000000000..c9f14d359d23 --- /dev/null +++ b/pac/atsaml22j/src/slcd/cmcfg.rs @@ -0,0 +1,95 @@ +#[doc = "Register `CMCFG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CMCFG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `NSEG` reader - Number of SEG lines"] +pub type NSEG_R = crate::FieldReader; +#[doc = "Field `NSEG` writer - Number of SEG lines"] +pub type NSEG_W<'a, const O: u8> = crate::FieldWriter<'a, u8, CMCFG_SPEC, u8, u8, 3, O>; +#[doc = "Field `DEC` reader - Decrement SEG Line Index"] +pub type DEC_R = crate::BitReader; +#[doc = "Field `DEC` writer - Decrement SEG Line Index"] +pub type DEC_W<'a, const O: u8> = crate::BitWriter<'a, u8, CMCFG_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:2 - Number of SEG lines"] + #[inline(always)] + pub fn nseg(&self) -> NSEG_R { + NSEG_R::new(self.bits & 7) + } + #[doc = "Bit 3 - Decrement SEG Line Index"] + #[inline(always)] + pub fn dec(&self) -> DEC_R { + DEC_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Number of SEG lines"] + #[inline(always)] + #[must_use] + pub fn nseg(&mut self) -> NSEG_W<0> { + NSEG_W::new(self) + } + #[doc = "Bit 3 - Decrement SEG Line Index"] + #[inline(always)] + #[must_use] + pub fn dec(&mut self) -> DEC_W<3> { + DEC_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Character Mapping Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cmcfg](index.html) module"] +pub struct CMCFG_SPEC; +impl crate::RegisterSpec for CMCFG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [cmcfg::R](R) reader structure"] +impl crate::Readable for CMCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cmcfg::W](W) writer structure"] +impl crate::Writable for CMCFG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CMCFG to value 0"] +impl crate::Resettable for CMCFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/slcd/cmdata.rs b/pac/atsaml22j/src/slcd/cmdata.rs new file mode 100644 index 000000000000..03a72436d593 --- /dev/null +++ b/pac/atsaml22j/src/slcd/cmdata.rs @@ -0,0 +1,52 @@ +#[doc = "Register `CMDATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SDATA` writer - Segments Data"] +pub type SDATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CMDATA_SPEC, u32, u32, 24, O>; +impl W { + #[doc = "Bits 0:23 - Segments Data"] + #[inline(always)] + #[must_use] + pub fn sdata(&mut self) -> SDATA_W<0> { + SDATA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Character Mapping Segments Data\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cmdata](index.html) module"] +pub struct CMDATA_SPEC; +impl crate::RegisterSpec for CMDATA_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [cmdata::W](W) writer structure"] +impl crate::Writable for CMDATA_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CMDATA to value 0"] +impl crate::Resettable for CMDATA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/slcd/cmdmask.rs b/pac/atsaml22j/src/slcd/cmdmask.rs new file mode 100644 index 000000000000..32164ebf422f --- /dev/null +++ b/pac/atsaml22j/src/slcd/cmdmask.rs @@ -0,0 +1,80 @@ +#[doc = "Register `CMDMASK` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CMDMASK` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SDMASK` reader - Segments Data Mask"] +pub type SDMASK_R = crate::FieldReader; +#[doc = "Field `SDMASK` writer - Segments Data Mask"] +pub type SDMASK_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CMDMASK_SPEC, u32, u32, 24, O>; +impl R { + #[doc = "Bits 0:23 - Segments Data Mask"] + #[inline(always)] + pub fn sdmask(&self) -> SDMASK_R { + SDMASK_R::new(self.bits & 0x00ff_ffff) + } +} +impl W { + #[doc = "Bits 0:23 - Segments Data Mask"] + #[inline(always)] + #[must_use] + pub fn sdmask(&mut self) -> SDMASK_W<0> { + SDMASK_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Character Mapping Segments Data Mask\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cmdmask](index.html) module"] +pub struct CMDMASK_SPEC; +impl crate::RegisterSpec for CMDMASK_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cmdmask::R](R) reader structure"] +impl crate::Readable for CMDMASK_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cmdmask::W](W) writer structure"] +impl crate::Writable for CMDMASK_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CMDMASK to value 0"] +impl crate::Resettable for CMDMASK_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/slcd/cmindex.rs b/pac/atsaml22j/src/slcd/cmindex.rs new file mode 100644 index 000000000000..242259aea80c --- /dev/null +++ b/pac/atsaml22j/src/slcd/cmindex.rs @@ -0,0 +1,95 @@ +#[doc = "Register `CMINDEX` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CMINDEX` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SINDEX` reader - SEG Line Index"] +pub type SINDEX_R = crate::FieldReader; +#[doc = "Field `SINDEX` writer - SEG Line Index"] +pub type SINDEX_W<'a, const O: u8> = crate::FieldWriter<'a, u16, CMINDEX_SPEC, u8, u8, 6, O>; +#[doc = "Field `CINDEX` reader - COM Line Index"] +pub type CINDEX_R = crate::FieldReader; +#[doc = "Field `CINDEX` writer - COM Line Index"] +pub type CINDEX_W<'a, const O: u8> = crate::FieldWriter<'a, u16, CMINDEX_SPEC, u8, u8, 3, O>; +impl R { + #[doc = "Bits 0:5 - SEG Line Index"] + #[inline(always)] + pub fn sindex(&self) -> SINDEX_R { + SINDEX_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 8:10 - COM Line Index"] + #[inline(always)] + pub fn cindex(&self) -> CINDEX_R { + CINDEX_R::new(((self.bits >> 8) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:5 - SEG Line Index"] + #[inline(always)] + #[must_use] + pub fn sindex(&mut self) -> SINDEX_W<0> { + SINDEX_W::new(self) + } + #[doc = "Bits 8:10 - COM Line Index"] + #[inline(always)] + #[must_use] + pub fn cindex(&mut self) -> CINDEX_W<8> { + CINDEX_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Character Mapping SEG/COM Index\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cmindex](index.html) module"] +pub struct CMINDEX_SPEC; +impl crate::RegisterSpec for CMINDEX_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [cmindex::R](R) reader structure"] +impl crate::Readable for CMINDEX_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cmindex::W](W) writer structure"] +impl crate::Writable for CMINDEX_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CMINDEX to value 0"] +impl crate::Resettable for CMINDEX_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/slcd/csrcfg.rs b/pac/atsaml22j/src/slcd/csrcfg.rs new file mode 100644 index 000000000000..a386f6219355 --- /dev/null +++ b/pac/atsaml22j/src/slcd/csrcfg.rs @@ -0,0 +1,186 @@ +#[doc = "Register `CSRCFG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CSRCFG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Direction"] +pub type DIR_R = crate::BitReader; +#[doc = "Field `DIR` writer - Direction"] +pub type DIR_W<'a, const O: u8> = crate::BitWriter<'a, u32, CSRCFG_SPEC, bool, O>; +#[doc = "Field `FCS` reader - Frame Counter Selection"] +pub type FCS_R = crate::FieldReader; +#[doc = "Frame Counter Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FCSSELECT_A { + #[doc = "0: Frame Counter 0"] + FC0 = 0, + #[doc = "1: Frame Counter 1"] + FC1 = 1, + #[doc = "2: Frame Counter 2"] + FC2 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FCSSELECT_A) -> Self { + variant as _ + } +} +impl FCS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(FCSSELECT_A::FC0), + 1 => Some(FCSSELECT_A::FC1), + 2 => Some(FCSSELECT_A::FC2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `FC0`"] + #[inline(always)] + pub fn is_fc0(&self) -> bool { + *self == FCSSELECT_A::FC0 + } + #[doc = "Checks if the value of the field is `FC1`"] + #[inline(always)] + pub fn is_fc1(&self) -> bool { + *self == FCSSELECT_A::FC1 + } + #[doc = "Checks if the value of the field is `FC2`"] + #[inline(always)] + pub fn is_fc2(&self) -> bool { + *self == FCSSELECT_A::FC2 + } +} +#[doc = "Field `FCS` writer - Frame Counter Selection"] +pub type FCS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CSRCFG_SPEC, u8, FCSSELECT_A, 2, O>; +impl<'a, const O: u8> FCS_W<'a, O> { + #[doc = "Frame Counter 0"] + #[inline(always)] + pub fn fc0(self) -> &'a mut W { + self.variant(FCSSELECT_A::FC0) + } + #[doc = "Frame Counter 1"] + #[inline(always)] + pub fn fc1(self) -> &'a mut W { + self.variant(FCSSELECT_A::FC1) + } + #[doc = "Frame Counter 2"] + #[inline(always)] + pub fn fc2(self) -> &'a mut W { + self.variant(FCSSELECT_A::FC2) + } +} +#[doc = "Field `SIZE` reader - Circular Shift Register Size"] +pub type SIZE_R = crate::FieldReader; +#[doc = "Field `SIZE` writer - Circular Shift Register Size"] +pub type SIZE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CSRCFG_SPEC, u8, u8, 4, O>; +#[doc = "Field `DATA` reader - Circular Shift Register Value"] +pub type DATA_R = crate::FieldReader; +#[doc = "Field `DATA` writer - Circular Shift Register Value"] +pub type DATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CSRCFG_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bit 0 - Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 1) != 0) + } + #[doc = "Bits 1:2 - Frame Counter Selection"] + #[inline(always)] + pub fn fcs(&self) -> FCS_R { + FCS_R::new(((self.bits >> 1) & 3) as u8) + } + #[doc = "Bits 4:7 - Circular Shift Register Size"] + #[inline(always)] + pub fn size(&self) -> SIZE_R { + SIZE_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:23 - Circular Shift Register Value"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(((self.bits >> 8) & 0xffff) as u16) + } +} +impl W { + #[doc = "Bit 0 - Direction"] + #[inline(always)] + #[must_use] + pub fn dir(&mut self) -> DIR_W<0> { + DIR_W::new(self) + } + #[doc = "Bits 1:2 - Frame Counter Selection"] + #[inline(always)] + #[must_use] + pub fn fcs(&mut self) -> FCS_W<1> { + FCS_W::new(self) + } + #[doc = "Bits 4:7 - Circular Shift Register Size"] + #[inline(always)] + #[must_use] + pub fn size(&mut self) -> SIZE_W<4> { + SIZE_W::new(self) + } + #[doc = "Bits 8:23 - Circular Shift Register Value"] + #[inline(always)] + #[must_use] + pub fn data(&mut self) -> DATA_W<8> { + DATA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Circular Shift Register Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [csrcfg](index.html) module"] +pub struct CSRCFG_SPEC; +impl crate::RegisterSpec for CSRCFG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [csrcfg::R](R) reader structure"] +impl crate::Readable for CSRCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [csrcfg::W](W) writer structure"] +impl crate::Writable for CSRCFG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CSRCFG to value 0"] +impl crate::Resettable for CSRCFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/slcd/ctrla.rs b/pac/atsaml22j/src/slcd/ctrla.rs new file mode 100644 index 000000000000..a243ba007fff --- /dev/null +++ b/pac/atsaml22j/src/slcd/ctrla.rs @@ -0,0 +1,791 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub type SWRST_R = crate::BitReader; +#[doc = "Field `SWRST` writer - Software Reset"] +pub type SWRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `ENABLE` reader - Enable"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - Enable"] +pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `DUTY` reader - Duty Ratio"] +pub type DUTY_R = crate::FieldReader; +#[doc = "Duty Ratio\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum DUTYSELECT_A { + #[doc = "0: Static duty"] + STATIC = 0, + #[doc = "1: 1/2 duty"] + HALF = 1, + #[doc = "2: 1/3 duty"] + THIRD = 2, + #[doc = "3: 1/4 duty"] + FOURTH = 3, + #[doc = "4: 1/6 duty"] + SIXTH = 4, + #[doc = "5: 1/8 duty"] + EIGHT = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DUTYSELECT_A) -> Self { + variant as _ + } +} +impl DUTY_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(DUTYSELECT_A::STATIC), + 1 => Some(DUTYSELECT_A::HALF), + 2 => Some(DUTYSELECT_A::THIRD), + 3 => Some(DUTYSELECT_A::FOURTH), + 4 => Some(DUTYSELECT_A::SIXTH), + 5 => Some(DUTYSELECT_A::EIGHT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `STATIC`"] + #[inline(always)] + pub fn is_static(&self) -> bool { + *self == DUTYSELECT_A::STATIC + } + #[doc = "Checks if the value of the field is `HALF`"] + #[inline(always)] + pub fn is_half(&self) -> bool { + *self == DUTYSELECT_A::HALF + } + #[doc = "Checks if the value of the field is `THIRD`"] + #[inline(always)] + pub fn is_third(&self) -> bool { + *self == DUTYSELECT_A::THIRD + } + #[doc = "Checks if the value of the field is `FOURTH`"] + #[inline(always)] + pub fn is_fourth(&self) -> bool { + *self == DUTYSELECT_A::FOURTH + } + #[doc = "Checks if the value of the field is `SIXTH`"] + #[inline(always)] + pub fn is_sixth(&self) -> bool { + *self == DUTYSELECT_A::SIXTH + } + #[doc = "Checks if the value of the field is `EIGHT`"] + #[inline(always)] + pub fn is_eight(&self) -> bool { + *self == DUTYSELECT_A::EIGHT + } +} +#[doc = "Field `DUTY` writer - Duty Ratio"] +pub type DUTY_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRLA_SPEC, u8, DUTYSELECT_A, 3, O>; +impl<'a, const O: u8> DUTY_W<'a, O> { + #[doc = "Static duty"] + #[inline(always)] + pub fn static_(self) -> &'a mut W { + self.variant(DUTYSELECT_A::STATIC) + } + #[doc = "1/2 duty"] + #[inline(always)] + pub fn half(self) -> &'a mut W { + self.variant(DUTYSELECT_A::HALF) + } + #[doc = "1/3 duty"] + #[inline(always)] + pub fn third(self) -> &'a mut W { + self.variant(DUTYSELECT_A::THIRD) + } + #[doc = "1/4 duty"] + #[inline(always)] + pub fn fourth(self) -> &'a mut W { + self.variant(DUTYSELECT_A::FOURTH) + } + #[doc = "1/6 duty"] + #[inline(always)] + pub fn sixth(self) -> &'a mut W { + self.variant(DUTYSELECT_A::SIXTH) + } + #[doc = "1/8 duty"] + #[inline(always)] + pub fn eight(self) -> &'a mut W { + self.variant(DUTYSELECT_A::EIGHT) + } +} +#[doc = "Field `WMOD` reader - Waveform Mode"] +pub type WMOD_R = crate::BitReader; +#[doc = "Waveform Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum WMODSELECT_A { + #[doc = "0: Low Power Waveform Mode"] + LP = 0, + #[doc = "1: Standard Waveform Mode"] + STD = 1, +} +impl From for bool { + #[inline(always)] + fn from(variant: WMODSELECT_A) -> Self { + variant as u8 != 0 + } +} +impl WMOD_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WMODSELECT_A { + match self.bits { + false => WMODSELECT_A::LP, + true => WMODSELECT_A::STD, + } + } + #[doc = "Checks if the value of the field is `LP`"] + #[inline(always)] + pub fn is_lp(&self) -> bool { + *self == WMODSELECT_A::LP + } + #[doc = "Checks if the value of the field is `STD`"] + #[inline(always)] + pub fn is_std(&self) -> bool { + *self == WMODSELECT_A::STD + } +} +#[doc = "Field `WMOD` writer - Waveform Mode"] +pub type WMOD_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, WMODSELECT_A, O>; +impl<'a, const O: u8> WMOD_W<'a, O> { + #[doc = "Low Power Waveform Mode"] + #[inline(always)] + pub fn lp(self) -> &'a mut W { + self.variant(WMODSELECT_A::LP) + } + #[doc = "Standard Waveform Mode"] + #[inline(always)] + pub fn std(self) -> &'a mut W { + self.variant(WMODSELECT_A::STD) + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub type RUNSTDBY_R = crate::BitReader; +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub type RUNSTDBY_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `PRESC` reader - Clock Prescaler"] +pub type PRESC_R = crate::FieldReader; +#[doc = "Clock Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum PRESCSELECT_A { + #[doc = "0: 16"] + PRESC16 = 0, + #[doc = "1: 32"] + PRESC32 = 1, + #[doc = "2: 64"] + PRESC64 = 2, + #[doc = "3: 128"] + PRESC128 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCSELECT_A) -> Self { + variant as _ + } +} +impl PRESC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCSELECT_A { + match self.bits { + 0 => PRESCSELECT_A::PRESC16, + 1 => PRESCSELECT_A::PRESC32, + 2 => PRESCSELECT_A::PRESC64, + 3 => PRESCSELECT_A::PRESC128, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PRESC16`"] + #[inline(always)] + pub fn is_presc16(&self) -> bool { + *self == PRESCSELECT_A::PRESC16 + } + #[doc = "Checks if the value of the field is `PRESC32`"] + #[inline(always)] + pub fn is_presc32(&self) -> bool { + *self == PRESCSELECT_A::PRESC32 + } + #[doc = "Checks if the value of the field is `PRESC64`"] + #[inline(always)] + pub fn is_presc64(&self) -> bool { + *self == PRESCSELECT_A::PRESC64 + } + #[doc = "Checks if the value of the field is `PRESC128`"] + #[inline(always)] + pub fn is_presc128(&self) -> bool { + *self == PRESCSELECT_A::PRESC128 + } +} +#[doc = "Field `PRESC` writer - Clock Prescaler"] +pub type PRESC_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, CTRLA_SPEC, u8, PRESCSELECT_A, 2, O>; +impl<'a, const O: u8> PRESC_W<'a, O> { + #[doc = "16"] + #[inline(always)] + pub fn presc16(self) -> &'a mut W { + self.variant(PRESCSELECT_A::PRESC16) + } + #[doc = "32"] + #[inline(always)] + pub fn presc32(self) -> &'a mut W { + self.variant(PRESCSELECT_A::PRESC32) + } + #[doc = "64"] + #[inline(always)] + pub fn presc64(self) -> &'a mut W { + self.variant(PRESCSELECT_A::PRESC64) + } + #[doc = "128"] + #[inline(always)] + pub fn presc128(self) -> &'a mut W { + self.variant(PRESCSELECT_A::PRESC128) + } +} +#[doc = "Field `CKDIV` reader - Clock Divider"] +pub type CKDIV_R = crate::FieldReader; +#[doc = "Field `CKDIV` writer - Clock Divider"] +pub type CKDIV_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRLA_SPEC, u8, u8, 3, O>; +#[doc = "Field `BIAS` reader - Bias Setting"] +pub type BIAS_R = crate::FieldReader; +#[doc = "Bias Setting\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum BIASSELECT_A { + #[doc = "0: Static"] + STATIC = 0, + #[doc = "1: 1/2 bias"] + HALF = 1, + #[doc = "2: 1/3 bias"] + THIRD = 2, + #[doc = "3: 1/4 bias"] + FOURTH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: BIASSELECT_A) -> Self { + variant as _ + } +} +impl BIAS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> BIASSELECT_A { + match self.bits { + 0 => BIASSELECT_A::STATIC, + 1 => BIASSELECT_A::HALF, + 2 => BIASSELECT_A::THIRD, + 3 => BIASSELECT_A::FOURTH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `STATIC`"] + #[inline(always)] + pub fn is_static(&self) -> bool { + *self == BIASSELECT_A::STATIC + } + #[doc = "Checks if the value of the field is `HALF`"] + #[inline(always)] + pub fn is_half(&self) -> bool { + *self == BIASSELECT_A::HALF + } + #[doc = "Checks if the value of the field is `THIRD`"] + #[inline(always)] + pub fn is_third(&self) -> bool { + *self == BIASSELECT_A::THIRD + } + #[doc = "Checks if the value of the field is `FOURTH`"] + #[inline(always)] + pub fn is_fourth(&self) -> bool { + *self == BIASSELECT_A::FOURTH + } +} +#[doc = "Field `BIAS` writer - Bias Setting"] +pub type BIAS_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, CTRLA_SPEC, u8, BIASSELECT_A, 2, O>; +impl<'a, const O: u8> BIAS_W<'a, O> { + #[doc = "Static"] + #[inline(always)] + pub fn static_(self) -> &'a mut W { + self.variant(BIASSELECT_A::STATIC) + } + #[doc = "1/2 bias"] + #[inline(always)] + pub fn half(self) -> &'a mut W { + self.variant(BIASSELECT_A::HALF) + } + #[doc = "1/3 bias"] + #[inline(always)] + pub fn third(self) -> &'a mut W { + self.variant(BIASSELECT_A::THIRD) + } + #[doc = "1/4 bias"] + #[inline(always)] + pub fn fourth(self) -> &'a mut W { + self.variant(BIASSELECT_A::FOURTH) + } +} +#[doc = "Field `XVLCD` reader - External VLCD"] +pub type XVLCD_R = crate::BitReader; +#[doc = "Field `XVLCD` writer - External VLCD"] +pub type XVLCD_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `PRF` reader - Power Refresh Frequency"] +pub type PRF_R = crate::FieldReader; +#[doc = "Power Refresh Frequency\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum PRFSELECT_A { + #[doc = "0: 2kHz"] + PR2000 = 0, + #[doc = "1: 1kHz"] + PR1000 = 1, + #[doc = "2: 500Hz"] + PR500 = 2, + #[doc = "3: 250Hz"] + PR250 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRFSELECT_A) -> Self { + variant as _ + } +} +impl PRF_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRFSELECT_A { + match self.bits { + 0 => PRFSELECT_A::PR2000, + 1 => PRFSELECT_A::PR1000, + 2 => PRFSELECT_A::PR500, + 3 => PRFSELECT_A::PR250, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `PR2000`"] + #[inline(always)] + pub fn is_pr2000(&self) -> bool { + *self == PRFSELECT_A::PR2000 + } + #[doc = "Checks if the value of the field is `PR1000`"] + #[inline(always)] + pub fn is_pr1000(&self) -> bool { + *self == PRFSELECT_A::PR1000 + } + #[doc = "Checks if the value of the field is `PR500`"] + #[inline(always)] + pub fn is_pr500(&self) -> bool { + *self == PRFSELECT_A::PR500 + } + #[doc = "Checks if the value of the field is `PR250`"] + #[inline(always)] + pub fn is_pr250(&self) -> bool { + *self == PRFSELECT_A::PR250 + } +} +#[doc = "Field `PRF` writer - Power Refresh Frequency"] +pub type PRF_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, CTRLA_SPEC, u8, PRFSELECT_A, 2, O>; +impl<'a, const O: u8> PRF_W<'a, O> { + #[doc = "2kHz"] + #[inline(always)] + pub fn pr2000(self) -> &'a mut W { + self.variant(PRFSELECT_A::PR2000) + } + #[doc = "1kHz"] + #[inline(always)] + pub fn pr1000(self) -> &'a mut W { + self.variant(PRFSELECT_A::PR1000) + } + #[doc = "500Hz"] + #[inline(always)] + pub fn pr500(self) -> &'a mut W { + self.variant(PRFSELECT_A::PR500) + } + #[doc = "250Hz"] + #[inline(always)] + pub fn pr250(self) -> &'a mut W { + self.variant(PRFSELECT_A::PR250) + } +} +#[doc = "Field `DMFCS` reader - Display Memory Update Frame Counter Selection"] +pub type DMFCS_R = crate::FieldReader; +#[doc = "Display Memory Update Frame Counter Selection\n\nValue on reset: 3"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum DMFCSSELECT_A { + #[doc = "0: Frame Counter 0"] + FC0 = 0, + #[doc = "1: Frame Counter 1"] + FC1 = 1, + #[doc = "2: Frame Counter 2"] + FC2 = 2, + #[doc = "3: Frame Counter event to DMU is forced to 0"] + NFC = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: DMFCSSELECT_A) -> Self { + variant as _ + } +} +impl DMFCS_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> DMFCSSELECT_A { + match self.bits { + 0 => DMFCSSELECT_A::FC0, + 1 => DMFCSSELECT_A::FC1, + 2 => DMFCSSELECT_A::FC2, + 3 => DMFCSSELECT_A::NFC, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `FC0`"] + #[inline(always)] + pub fn is_fc0(&self) -> bool { + *self == DMFCSSELECT_A::FC0 + } + #[doc = "Checks if the value of the field is `FC1`"] + #[inline(always)] + pub fn is_fc1(&self) -> bool { + *self == DMFCSSELECT_A::FC1 + } + #[doc = "Checks if the value of the field is `FC2`"] + #[inline(always)] + pub fn is_fc2(&self) -> bool { + *self == DMFCSSELECT_A::FC2 + } + #[doc = "Checks if the value of the field is `NFC`"] + #[inline(always)] + pub fn is_nfc(&self) -> bool { + *self == DMFCSSELECT_A::NFC + } +} +#[doc = "Field `DMFCS` writer - Display Memory Update Frame Counter Selection"] +pub type DMFCS_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, CTRLA_SPEC, u8, DMFCSSELECT_A, 2, O>; +impl<'a, const O: u8> DMFCS_W<'a, O> { + #[doc = "Frame Counter 0"] + #[inline(always)] + pub fn fc0(self) -> &'a mut W { + self.variant(DMFCSSELECT_A::FC0) + } + #[doc = "Frame Counter 1"] + #[inline(always)] + pub fn fc1(self) -> &'a mut W { + self.variant(DMFCSSELECT_A::FC1) + } + #[doc = "Frame Counter 2"] + #[inline(always)] + pub fn fc2(self) -> &'a mut W { + self.variant(DMFCSSELECT_A::FC2) + } + #[doc = "Frame Counter event to DMU is forced to 0"] + #[inline(always)] + pub fn nfc(self) -> &'a mut W { + self.variant(DMFCSSELECT_A::NFC) + } +} +#[doc = "Field `RRF` reader - Reference Refresh Frequency"] +pub type RRF_R = crate::FieldReader; +#[doc = "Reference Refresh Frequency\n\nValue on reset: 3"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum RRFSELECT_A { + #[doc = "0: 2kHz"] + RR2000 = 0, + #[doc = "1: 1kHz"] + RR1000 = 1, + #[doc = "2: 500Hz"] + RR500 = 2, + #[doc = "3: 250Hz"] + RR250 = 3, + #[doc = "4: 125Hz"] + RR125 = 4, + #[doc = "5: 62.5Hz"] + RR62 = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RRFSELECT_A) -> Self { + variant as _ + } +} +impl RRF_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(RRFSELECT_A::RR2000), + 1 => Some(RRFSELECT_A::RR1000), + 2 => Some(RRFSELECT_A::RR500), + 3 => Some(RRFSELECT_A::RR250), + 4 => Some(RRFSELECT_A::RR125), + 5 => Some(RRFSELECT_A::RR62), + _ => None, + } + } + #[doc = "Checks if the value of the field is `RR2000`"] + #[inline(always)] + pub fn is_rr2000(&self) -> bool { + *self == RRFSELECT_A::RR2000 + } + #[doc = "Checks if the value of the field is `RR1000`"] + #[inline(always)] + pub fn is_rr1000(&self) -> bool { + *self == RRFSELECT_A::RR1000 + } + #[doc = "Checks if the value of the field is `RR500`"] + #[inline(always)] + pub fn is_rr500(&self) -> bool { + *self == RRFSELECT_A::RR500 + } + #[doc = "Checks if the value of the field is `RR250`"] + #[inline(always)] + pub fn is_rr250(&self) -> bool { + *self == RRFSELECT_A::RR250 + } + #[doc = "Checks if the value of the field is `RR125`"] + #[inline(always)] + pub fn is_rr125(&self) -> bool { + *self == RRFSELECT_A::RR125 + } + #[doc = "Checks if the value of the field is `RR62`"] + #[inline(always)] + pub fn is_rr62(&self) -> bool { + *self == RRFSELECT_A::RR62 + } +} +#[doc = "Field `RRF` writer - Reference Refresh Frequency"] +pub type RRF_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRLA_SPEC, u8, RRFSELECT_A, 3, O>; +impl<'a, const O: u8> RRF_W<'a, O> { + #[doc = "2kHz"] + #[inline(always)] + pub fn rr2000(self) -> &'a mut W { + self.variant(RRFSELECT_A::RR2000) + } + #[doc = "1kHz"] + #[inline(always)] + pub fn rr1000(self) -> &'a mut W { + self.variant(RRFSELECT_A::RR1000) + } + #[doc = "500Hz"] + #[inline(always)] + pub fn rr500(self) -> &'a mut W { + self.variant(RRFSELECT_A::RR500) + } + #[doc = "250Hz"] + #[inline(always)] + pub fn rr250(self) -> &'a mut W { + self.variant(RRFSELECT_A::RR250) + } + #[doc = "125Hz"] + #[inline(always)] + pub fn rr125(self) -> &'a mut W { + self.variant(RRFSELECT_A::RR125) + } + #[doc = "62.5Hz"] + #[inline(always)] + pub fn rr62(self) -> &'a mut W { + self.variant(RRFSELECT_A::RR62) + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:4 - Duty Ratio"] + #[inline(always)] + pub fn duty(&self) -> DUTY_R { + DUTY_R::new(((self.bits >> 2) & 7) as u8) + } + #[doc = "Bit 5 - Waveform Mode"] + #[inline(always)] + pub fn wmod(&self) -> WMOD_R { + WMOD_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bits 8:9 - Clock Prescaler"] + #[inline(always)] + pub fn presc(&self) -> PRESC_R { + PRESC_R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 12:14 - Clock Divider"] + #[inline(always)] + pub fn ckdiv(&self) -> CKDIV_R { + CKDIV_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bits 16:17 - Bias Setting"] + #[inline(always)] + pub fn bias(&self) -> BIAS_R { + BIAS_R::new(((self.bits >> 16) & 3) as u8) + } + #[doc = "Bit 19 - External VLCD"] + #[inline(always)] + pub fn xvlcd(&self) -> XVLCD_R { + XVLCD_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bits 20:21 - Power Refresh Frequency"] + #[inline(always)] + pub fn prf(&self) -> PRF_R { + PRF_R::new(((self.bits >> 20) & 3) as u8) + } + #[doc = "Bits 22:23 - Display Memory Update Frame Counter Selection"] + #[inline(always)] + pub fn dmfcs(&self) -> DMFCS_R { + DMFCS_R::new(((self.bits >> 22) & 3) as u8) + } + #[doc = "Bits 24:26 - Reference Refresh Frequency"] + #[inline(always)] + pub fn rrf(&self) -> RRF_R { + RRF_R::new(((self.bits >> 24) & 7) as u8) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + #[must_use] + pub fn swrst(&mut self) -> SWRST_W<0> { + SWRST_W::new(self) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W<1> { + ENABLE_W::new(self) + } + #[doc = "Bits 2:4 - Duty Ratio"] + #[inline(always)] + #[must_use] + pub fn duty(&mut self) -> DUTY_W<2> { + DUTY_W::new(self) + } + #[doc = "Bit 5 - Waveform Mode"] + #[inline(always)] + #[must_use] + pub fn wmod(&mut self) -> WMOD_W<5> { + WMOD_W::new(self) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + #[must_use] + pub fn runstdby(&mut self) -> RUNSTDBY_W<6> { + RUNSTDBY_W::new(self) + } + #[doc = "Bits 8:9 - Clock Prescaler"] + #[inline(always)] + #[must_use] + pub fn presc(&mut self) -> PRESC_W<8> { + PRESC_W::new(self) + } + #[doc = "Bits 12:14 - Clock Divider"] + #[inline(always)] + #[must_use] + pub fn ckdiv(&mut self) -> CKDIV_W<12> { + CKDIV_W::new(self) + } + #[doc = "Bits 16:17 - Bias Setting"] + #[inline(always)] + #[must_use] + pub fn bias(&mut self) -> BIAS_W<16> { + BIAS_W::new(self) + } + #[doc = "Bit 19 - External VLCD"] + #[inline(always)] + #[must_use] + pub fn xvlcd(&mut self) -> XVLCD_W<19> { + XVLCD_W::new(self) + } + #[doc = "Bits 20:21 - Power Refresh Frequency"] + #[inline(always)] + #[must_use] + pub fn prf(&mut self) -> PRF_W<20> { + PRF_W::new(self) + } + #[doc = "Bits 22:23 - Display Memory Update Frame Counter Selection"] + #[inline(always)] + #[must_use] + pub fn dmfcs(&mut self) -> DMFCS_W<22> { + DMFCS_W::new(self) + } + #[doc = "Bits 24:26 - Reference Refresh Frequency"] + #[inline(always)] + #[must_use] + pub fn rrf(&mut self) -> RRF_W<24> { + RRF_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRLA to value 0x03d8_0000"] +impl crate::Resettable for CTRLA_SPEC { + const RESET_VALUE: Self::Ux = 0x03d8_0000; +} diff --git a/pac/atsaml22j/src/slcd/ctrlb.rs b/pac/atsaml22j/src/slcd/ctrlb.rs new file mode 100644 index 000000000000..68d633ace3d8 --- /dev/null +++ b/pac/atsaml22j/src/slcd/ctrlb.rs @@ -0,0 +1,125 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BBD` reader - Bias Buffer Enable Duration"] +pub type BBD_R = crate::FieldReader; +#[doc = "Field `BBD` writer - Bias Buffer Enable Duration"] +pub type BBD_W<'a, const O: u8> = crate::FieldWriter<'a, u16, CTRLB_SPEC, u8, u8, 4, O>; +#[doc = "Field `BBEN` reader - Bias Buffer Enable"] +pub type BBEN_R = crate::BitReader; +#[doc = "Field `BBEN` writer - Bias Buffer Enable"] +pub type BBEN_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRLB_SPEC, bool, O>; +#[doc = "Field `LRD` reader - Low Resistance Enable Duration"] +pub type LRD_R = crate::FieldReader; +#[doc = "Field `LRD` writer - Low Resistance Enable Duration"] +pub type LRD_W<'a, const O: u8> = crate::FieldWriter<'a, u16, CTRLB_SPEC, u8, u8, 4, O>; +#[doc = "Field `LREN` reader - Low Resistance Enable"] +pub type LREN_R = crate::BitReader; +#[doc = "Field `LREN` writer - Low Resistance Enable"] +pub type LREN_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRLB_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:3 - Bias Buffer Enable Duration"] + #[inline(always)] + pub fn bbd(&self) -> BBD_R { + BBD_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bit 7 - Bias Buffer Enable"] + #[inline(always)] + pub fn bben(&self) -> BBEN_R { + BBEN_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:11 - Low Resistance Enable Duration"] + #[inline(always)] + pub fn lrd(&self) -> LRD_R { + LRD_R::new(((self.bits >> 8) & 0x0f) as u8) + } + #[doc = "Bit 15 - Low Resistance Enable"] + #[inline(always)] + pub fn lren(&self) -> LREN_R { + LREN_R::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:3 - Bias Buffer Enable Duration"] + #[inline(always)] + #[must_use] + pub fn bbd(&mut self) -> BBD_W<0> { + BBD_W::new(self) + } + #[doc = "Bit 7 - Bias Buffer Enable"] + #[inline(always)] + #[must_use] + pub fn bben(&mut self) -> BBEN_W<7> { + BBEN_W::new(self) + } + #[doc = "Bits 8:11 - Low Resistance Enable Duration"] + #[inline(always)] + #[must_use] + pub fn lrd(&mut self) -> LRD_W<8> { + LRD_W::new(self) + } + #[doc = "Bit 15 - Low Resistance Enable"] + #[inline(always)] + #[must_use] + pub fn lren(&mut self) -> LREN_W<15> { + LREN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRLB to value 0"] +impl crate::Resettable for CTRLB_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/slcd/ctrlc.rs b/pac/atsaml22j/src/slcd/ctrlc.rs new file mode 100644 index 000000000000..5a01eb577f8f --- /dev/null +++ b/pac/atsaml22j/src/slcd/ctrlc.rs @@ -0,0 +1,216 @@ +#[doc = "Register `CTRLC` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLC` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CLEAR` reader - Clear Display Memory"] +pub type CLEAR_R = crate::BitReader; +#[doc = "Field `CLEAR` writer - Clear Display Memory"] +pub type CLEAR_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRLC_SPEC, bool, O>; +#[doc = "Field `LOCK` reader - Lock Shadow Memory"] +pub type LOCK_R = crate::BitReader; +#[doc = "Field `LOCK` writer - Lock Shadow Memory"] +pub type LOCK_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRLC_SPEC, bool, O>; +#[doc = "Field `ABMEN` reader - Automated Bit Mapping Enable"] +pub type ABMEN_R = crate::BitReader; +#[doc = "Field `ABMEN` writer - Automated Bit Mapping Enable"] +pub type ABMEN_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRLC_SPEC, bool, O>; +#[doc = "Field `ACMEN` reader - Automated Character Mapping Enable"] +pub type ACMEN_R = crate::BitReader; +#[doc = "Field `ACMEN` writer - Automated Character Mapping Enable"] +pub type ACMEN_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRLC_SPEC, bool, O>; +#[doc = "Field `CTST` reader - Contrast Adjustment"] +pub type CTST_R = crate::FieldReader; +#[doc = "Field `CTST` writer - Contrast Adjustment"] +pub type CTST_W<'a, const O: u8> = crate::FieldWriter<'a, u16, CTRLC_SPEC, u8, u8, 4, O>; +#[doc = "Field `LPPM` reader - LCD Power Macro Power mode"] +pub type LPPM_R = crate::FieldReader; +#[doc = "LCD Power Macro Power mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LPPMSELECT_A { + #[doc = "0: LCD power automatically select regualation mode or pump mode"] + AUTO = 0, + #[doc = "1: LCD power use step-up pump loop only"] + STEPUP = 1, + #[doc = "2: LCD power use step-down drop-out regulation loop only"] + STEPDOWN = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LPPMSELECT_A) -> Self { + variant as _ + } +} +impl LPPM_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(LPPMSELECT_A::AUTO), + 1 => Some(LPPMSELECT_A::STEPUP), + 2 => Some(LPPMSELECT_A::STEPDOWN), + _ => None, + } + } + #[doc = "Checks if the value of the field is `AUTO`"] + #[inline(always)] + pub fn is_auto(&self) -> bool { + *self == LPPMSELECT_A::AUTO + } + #[doc = "Checks if the value of the field is `STEPUP`"] + #[inline(always)] + pub fn is_stepup(&self) -> bool { + *self == LPPMSELECT_A::STEPUP + } + #[doc = "Checks if the value of the field is `STEPDOWN`"] + #[inline(always)] + pub fn is_stepdown(&self) -> bool { + *self == LPPMSELECT_A::STEPDOWN + } +} +#[doc = "Field `LPPM` writer - LCD Power Macro Power mode"] +pub type LPPM_W<'a, const O: u8> = crate::FieldWriter<'a, u16, CTRLC_SPEC, u8, LPPMSELECT_A, 2, O>; +impl<'a, const O: u8> LPPM_W<'a, O> { + #[doc = "LCD power automatically select regualation mode or pump mode"] + #[inline(always)] + pub fn auto(self) -> &'a mut W { + self.variant(LPPMSELECT_A::AUTO) + } + #[doc = "LCD power use step-up pump loop only"] + #[inline(always)] + pub fn stepup(self) -> &'a mut W { + self.variant(LPPMSELECT_A::STEPUP) + } + #[doc = "LCD power use step-down drop-out regulation loop only"] + #[inline(always)] + pub fn stepdown(self) -> &'a mut W { + self.variant(LPPMSELECT_A::STEPDOWN) + } +} +impl R { + #[doc = "Bit 0 - Clear Display Memory"] + #[inline(always)] + pub fn clear(&self) -> CLEAR_R { + CLEAR_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Lock Shadow Memory"] + #[inline(always)] + pub fn lock(&self) -> LOCK_R { + LOCK_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Automated Bit Mapping Enable"] + #[inline(always)] + pub fn abmen(&self) -> ABMEN_R { + ABMEN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Automated Character Mapping Enable"] + #[inline(always)] + pub fn acmen(&self) -> ACMEN_R { + ACMEN_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bits 4:7 - Contrast Adjustment"] + #[inline(always)] + pub fn ctst(&self) -> CTST_R { + CTST_R::new(((self.bits >> 4) & 0x0f) as u8) + } + #[doc = "Bits 8:9 - LCD Power Macro Power mode"] + #[inline(always)] + pub fn lppm(&self) -> LPPM_R { + LPPM_R::new(((self.bits >> 8) & 3) as u8) + } +} +impl W { + #[doc = "Bit 0 - Clear Display Memory"] + #[inline(always)] + #[must_use] + pub fn clear(&mut self) -> CLEAR_W<0> { + CLEAR_W::new(self) + } + #[doc = "Bit 1 - Lock Shadow Memory"] + #[inline(always)] + #[must_use] + pub fn lock(&mut self) -> LOCK_W<1> { + LOCK_W::new(self) + } + #[doc = "Bit 2 - Automated Bit Mapping Enable"] + #[inline(always)] + #[must_use] + pub fn abmen(&mut self) -> ABMEN_W<2> { + ABMEN_W::new(self) + } + #[doc = "Bit 3 - Automated Character Mapping Enable"] + #[inline(always)] + #[must_use] + pub fn acmen(&mut self) -> ACMEN_W<3> { + ACMEN_W::new(self) + } + #[doc = "Bits 4:7 - Contrast Adjustment"] + #[inline(always)] + #[must_use] + pub fn ctst(&mut self) -> CTST_W<4> { + CTST_W::new(self) + } + #[doc = "Bits 8:9 - LCD Power Macro Power mode"] + #[inline(always)] + #[must_use] + pub fn lppm(&mut self) -> LPPM_W<8> { + LPPM_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlc](index.html) module"] +pub struct CTRLC_SPEC; +impl crate::RegisterSpec for CTRLC_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrlc::R](R) reader structure"] +impl crate::Readable for CTRLC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlc::W](W) writer structure"] +impl crate::Writable for CTRLC_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRLC to value 0"] +impl crate::Resettable for CTRLC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/slcd/ctrld.rs b/pac/atsaml22j/src/slcd/ctrld.rs new file mode 100644 index 000000000000..dd1c111f947f --- /dev/null +++ b/pac/atsaml22j/src/slcd/ctrld.rs @@ -0,0 +1,170 @@ +#[doc = "Register `CTRLD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BLANK` reader - Blank LCD"] +pub type BLANK_R = crate::BitReader; +#[doc = "Field `BLANK` writer - Blank LCD"] +pub type BLANK_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLD_SPEC, bool, O>; +#[doc = "Field `BLINK` reader - Blinking Enable"] +pub type BLINK_R = crate::BitReader; +#[doc = "Field `BLINK` writer - Blinking Enable"] +pub type BLINK_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLD_SPEC, bool, O>; +#[doc = "Field `CSREN` reader - Circular Shift Register Enable"] +pub type CSREN_R = crate::BitReader; +#[doc = "Field `CSREN` writer - Circular Shift Register Enable"] +pub type CSREN_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLD_SPEC, bool, O>; +#[doc = "Field `FC0EN` reader - Frame Counter 0 Enable"] +pub type FC0EN_R = crate::BitReader; +#[doc = "Field `FC0EN` writer - Frame Counter 0 Enable"] +pub type FC0EN_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLD_SPEC, bool, O>; +#[doc = "Field `FC1EN` reader - Frame Counter 1 Enable"] +pub type FC1EN_R = crate::BitReader; +#[doc = "Field `FC1EN` writer - Frame Counter 1 Enable"] +pub type FC1EN_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLD_SPEC, bool, O>; +#[doc = "Field `FC2EN` reader - Frame Counter 2 Enable"] +pub type FC2EN_R = crate::BitReader; +#[doc = "Field `FC2EN` writer - Frame Counter 2 Enable"] +pub type FC2EN_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLD_SPEC, bool, O>; +#[doc = "Field `DISPEN` reader - Display enable"] +pub type DISPEN_R = crate::BitReader; +#[doc = "Field `DISPEN` writer - Display enable"] +pub type DISPEN_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLD_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Blank LCD"] + #[inline(always)] + pub fn blank(&self) -> BLANK_R { + BLANK_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Blinking Enable"] + #[inline(always)] + pub fn blink(&self) -> BLINK_R { + BLINK_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Circular Shift Register Enable"] + #[inline(always)] + pub fn csren(&self) -> CSREN_R { + CSREN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - Frame Counter 0 Enable"] + #[inline(always)] + pub fn fc0en(&self) -> FC0EN_R { + FC0EN_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Frame Counter 1 Enable"] + #[inline(always)] + pub fn fc1en(&self) -> FC1EN_R { + FC1EN_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Frame Counter 2 Enable"] + #[inline(always)] + pub fn fc2en(&self) -> FC2EN_R { + FC2EN_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Display enable"] + #[inline(always)] + pub fn dispen(&self) -> DISPEN_R { + DISPEN_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Blank LCD"] + #[inline(always)] + #[must_use] + pub fn blank(&mut self) -> BLANK_W<0> { + BLANK_W::new(self) + } + #[doc = "Bit 1 - Blinking Enable"] + #[inline(always)] + #[must_use] + pub fn blink(&mut self) -> BLINK_W<1> { + BLINK_W::new(self) + } + #[doc = "Bit 2 - Circular Shift Register Enable"] + #[inline(always)] + #[must_use] + pub fn csren(&mut self) -> CSREN_W<2> { + CSREN_W::new(self) + } + #[doc = "Bit 4 - Frame Counter 0 Enable"] + #[inline(always)] + #[must_use] + pub fn fc0en(&mut self) -> FC0EN_W<4> { + FC0EN_W::new(self) + } + #[doc = "Bit 5 - Frame Counter 1 Enable"] + #[inline(always)] + #[must_use] + pub fn fc1en(&mut self) -> FC1EN_W<5> { + FC1EN_W::new(self) + } + #[doc = "Bit 6 - Frame Counter 2 Enable"] + #[inline(always)] + #[must_use] + pub fn fc2en(&mut self) -> FC2EN_W<6> { + FC2EN_W::new(self) + } + #[doc = "Bit 7 - Display enable"] + #[inline(always)] + #[must_use] + pub fn dispen(&mut self) -> DISPEN_W<7> { + DISPEN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control D\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrld](index.html) module"] +pub struct CTRLD_SPEC; +impl crate::RegisterSpec for CTRLD_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrld::R](R) reader structure"] +impl crate::Readable for CTRLD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrld::W](W) writer structure"] +impl crate::Writable for CTRLD_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRLD to value 0x80"] +impl crate::Resettable for CTRLD_SPEC { + const RESET_VALUE: Self::Ux = 0x80; +} diff --git a/pac/atsaml22j/src/slcd/evctrl.rs b/pac/atsaml22j/src/slcd/evctrl.rs new file mode 100644 index 000000000000..546c515fcaa8 --- /dev/null +++ b/pac/atsaml22j/src/slcd/evctrl.rs @@ -0,0 +1,110 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FC0OEO` reader - Frame Counter 0 Overflow Event Output Enable"] +pub type FC0OEO_R = crate::BitReader; +#[doc = "Field `FC0OEO` writer - Frame Counter 0 Overflow Event Output Enable"] +pub type FC0OEO_W<'a, const O: u8> = crate::BitWriter<'a, u8, EVCTRL_SPEC, bool, O>; +#[doc = "Field `FC1OEO` reader - Frame Counter 1 Overflow Event Output Enable"] +pub type FC1OEO_R = crate::BitReader; +#[doc = "Field `FC1OEO` writer - Frame Counter 1 Overflow Event Output Enable"] +pub type FC1OEO_W<'a, const O: u8> = crate::BitWriter<'a, u8, EVCTRL_SPEC, bool, O>; +#[doc = "Field `FC2OEO` reader - Frame Counter 2 Overflow Event Output Enable"] +pub type FC2OEO_R = crate::BitReader; +#[doc = "Field `FC2OEO` writer - Frame Counter 2 Overflow Event Output Enable"] +pub type FC2OEO_W<'a, const O: u8> = crate::BitWriter<'a, u8, EVCTRL_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Frame Counter 0 Overflow Event Output Enable"] + #[inline(always)] + pub fn fc0oeo(&self) -> FC0OEO_R { + FC0OEO_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Frame Counter 1 Overflow Event Output Enable"] + #[inline(always)] + pub fn fc1oeo(&self) -> FC1OEO_R { + FC1OEO_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Frame Counter 2 Overflow Event Output Enable"] + #[inline(always)] + pub fn fc2oeo(&self) -> FC2OEO_R { + FC2OEO_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Frame Counter 0 Overflow Event Output Enable"] + #[inline(always)] + #[must_use] + pub fn fc0oeo(&mut self) -> FC0OEO_W<0> { + FC0OEO_W::new(self) + } + #[doc = "Bit 1 - Frame Counter 1 Overflow Event Output Enable"] + #[inline(always)] + #[must_use] + pub fn fc1oeo(&mut self) -> FC1OEO_W<1> { + FC1OEO_W::new(self) + } + #[doc = "Bit 2 - Frame Counter 2 Overflow Event Output Enable"] + #[inline(always)] + #[must_use] + pub fn fc2oeo(&mut self) -> FC2OEO_W<2> { + FC2OEO_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/slcd/fc0.rs b/pac/atsaml22j/src/slcd/fc0.rs new file mode 100644 index 000000000000..40f3cca4d414 --- /dev/null +++ b/pac/atsaml22j/src/slcd/fc0.rs @@ -0,0 +1,95 @@ +#[doc = "Register `FC0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FC0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Frame Counter Overflow Value"] +pub type OVF_R = crate::FieldReader; +#[doc = "Field `OVF` writer - Frame Counter Overflow Value"] +pub type OVF_W<'a, const O: u8> = crate::FieldWriter<'a, u8, FC0_SPEC, u8, u8, 5, O>; +#[doc = "Field `PB` reader - Prescaler Bypass"] +pub type PB_R = crate::BitReader; +#[doc = "Field `PB` writer - Prescaler Bypass"] +pub type PB_W<'a, const O: u8> = crate::BitWriter<'a, u8, FC0_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:4 - Frame Counter Overflow Value"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(self.bits & 0x1f) + } + #[doc = "Bit 7 - Prescaler Bypass"] + #[inline(always)] + pub fn pb(&self) -> PB_R { + PB_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Frame Counter Overflow Value"] + #[inline(always)] + #[must_use] + pub fn ovf(&mut self) -> OVF_W<0> { + OVF_W::new(self) + } + #[doc = "Bit 7 - Prescaler Bypass"] + #[inline(always)] + #[must_use] + pub fn pb(&mut self) -> PB_W<7> { + PB_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Frame Counter 0 Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fc0](index.html) module"] +pub struct FC0_SPEC; +impl crate::RegisterSpec for FC0_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [fc0::R](R) reader structure"] +impl crate::Readable for FC0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [fc0::W](W) writer structure"] +impl crate::Writable for FC0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FC0 to value 0"] +impl crate::Resettable for FC0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/slcd/fc1.rs b/pac/atsaml22j/src/slcd/fc1.rs new file mode 100644 index 000000000000..d5116bcab56a --- /dev/null +++ b/pac/atsaml22j/src/slcd/fc1.rs @@ -0,0 +1,95 @@ +#[doc = "Register `FC1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FC1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Frame Counter Overflow Value"] +pub type OVF_R = crate::FieldReader; +#[doc = "Field `OVF` writer - Frame Counter Overflow Value"] +pub type OVF_W<'a, const O: u8> = crate::FieldWriter<'a, u8, FC1_SPEC, u8, u8, 5, O>; +#[doc = "Field `PB` reader - Prescaler Bypass"] +pub type PB_R = crate::BitReader; +#[doc = "Field `PB` writer - Prescaler Bypass"] +pub type PB_W<'a, const O: u8> = crate::BitWriter<'a, u8, FC1_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:4 - Frame Counter Overflow Value"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(self.bits & 0x1f) + } + #[doc = "Bit 7 - Prescaler Bypass"] + #[inline(always)] + pub fn pb(&self) -> PB_R { + PB_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Frame Counter Overflow Value"] + #[inline(always)] + #[must_use] + pub fn ovf(&mut self) -> OVF_W<0> { + OVF_W::new(self) + } + #[doc = "Bit 7 - Prescaler Bypass"] + #[inline(always)] + #[must_use] + pub fn pb(&mut self) -> PB_W<7> { + PB_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Frame Counter 1 Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fc1](index.html) module"] +pub struct FC1_SPEC; +impl crate::RegisterSpec for FC1_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [fc1::R](R) reader structure"] +impl crate::Readable for FC1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [fc1::W](W) writer structure"] +impl crate::Writable for FC1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FC1 to value 0"] +impl crate::Resettable for FC1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/slcd/fc2.rs b/pac/atsaml22j/src/slcd/fc2.rs new file mode 100644 index 000000000000..130f0e5106c6 --- /dev/null +++ b/pac/atsaml22j/src/slcd/fc2.rs @@ -0,0 +1,95 @@ +#[doc = "Register `FC2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FC2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Frame Counter Overflow Value"] +pub type OVF_R = crate::FieldReader; +#[doc = "Field `OVF` writer - Frame Counter Overflow Value"] +pub type OVF_W<'a, const O: u8> = crate::FieldWriter<'a, u8, FC2_SPEC, u8, u8, 5, O>; +#[doc = "Field `PB` reader - Prescaler Bypass"] +pub type PB_R = crate::BitReader; +#[doc = "Field `PB` writer - Prescaler Bypass"] +pub type PB_W<'a, const O: u8> = crate::BitWriter<'a, u8, FC2_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:4 - Frame Counter Overflow Value"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new(self.bits & 0x1f) + } + #[doc = "Bit 7 - Prescaler Bypass"] + #[inline(always)] + pub fn pb(&self) -> PB_R { + PB_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:4 - Frame Counter Overflow Value"] + #[inline(always)] + #[must_use] + pub fn ovf(&mut self) -> OVF_W<0> { + OVF_W::new(self) + } + #[doc = "Bit 7 - Prescaler Bypass"] + #[inline(always)] + #[must_use] + pub fn pb(&mut self) -> PB_W<7> { + PB_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Frame Counter 2 Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fc2](index.html) module"] +pub struct FC2_SPEC; +impl crate::RegisterSpec for FC2_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [fc2::R](R) reader structure"] +impl crate::Readable for FC2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [fc2::W](W) writer structure"] +impl crate::Writable for FC2_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FC2 to value 0"] +impl crate::Resettable for FC2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/slcd/intenclr.rs b/pac/atsaml22j/src/slcd/intenclr.rs new file mode 100644 index 000000000000..9903bebd2454 --- /dev/null +++ b/pac/atsaml22j/src/slcd/intenclr.rs @@ -0,0 +1,155 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FC0O` reader - Frame Counter 0 Overflow Interrupt Disable"] +pub type FC0O_R = crate::BitReader; +#[doc = "Field `FC0O` writer - Frame Counter 0 Overflow Interrupt Disable"] +pub type FC0O_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>; +#[doc = "Field `FC1O` reader - Frame Counter 1 Overflow Interrupt Disable"] +pub type FC1O_R = crate::BitReader; +#[doc = "Field `FC1O` writer - Frame Counter 1 Overflow Interrupt Disable"] +pub type FC1O_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>; +#[doc = "Field `FC2O` reader - Frame Counter 2 Overflow Interrupt Disable"] +pub type FC2O_R = crate::BitReader; +#[doc = "Field `FC2O` writer - Frame Counter 2 Overflow Interrupt Disable"] +pub type FC2O_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>; +#[doc = "Field `VLCDRT` reader - VLCD Ready Toggle Interrupt Disable"] +pub type VLCDRT_R = crate::BitReader; +#[doc = "Field `VLCDRT` writer - VLCD Ready Toggle Interrupt Disable"] +pub type VLCDRT_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>; +#[doc = "Field `VLCDST` reader - VLCD Status Toggle Interrupt Disable"] +pub type VLCDST_R = crate::BitReader; +#[doc = "Field `VLCDST` writer - VLCD Status Toggle Interrupt Disable"] +pub type VLCDST_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>; +#[doc = "Field `PRST` reader - Pump Run Status Toggle Interrupt Disable"] +pub type PRST_R = crate::BitReader; +#[doc = "Field `PRST` writer - Pump Run Status Toggle Interrupt Disable"] +pub type PRST_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Frame Counter 0 Overflow Interrupt Disable"] + #[inline(always)] + pub fn fc0o(&self) -> FC0O_R { + FC0O_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Frame Counter 1 Overflow Interrupt Disable"] + #[inline(always)] + pub fn fc1o(&self) -> FC1O_R { + FC1O_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Frame Counter 2 Overflow Interrupt Disable"] + #[inline(always)] + pub fn fc2o(&self) -> FC2O_R { + FC2O_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - VLCD Ready Toggle Interrupt Disable"] + #[inline(always)] + pub fn vlcdrt(&self) -> VLCDRT_R { + VLCDRT_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - VLCD Status Toggle Interrupt Disable"] + #[inline(always)] + pub fn vlcdst(&self) -> VLCDST_R { + VLCDST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Pump Run Status Toggle Interrupt Disable"] + #[inline(always)] + pub fn prst(&self) -> PRST_R { + PRST_R::new(((self.bits >> 5) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Frame Counter 0 Overflow Interrupt Disable"] + #[inline(always)] + #[must_use] + pub fn fc0o(&mut self) -> FC0O_W<0> { + FC0O_W::new(self) + } + #[doc = "Bit 1 - Frame Counter 1 Overflow Interrupt Disable"] + #[inline(always)] + #[must_use] + pub fn fc1o(&mut self) -> FC1O_W<1> { + FC1O_W::new(self) + } + #[doc = "Bit 2 - Frame Counter 2 Overflow Interrupt Disable"] + #[inline(always)] + #[must_use] + pub fn fc2o(&mut self) -> FC2O_W<2> { + FC2O_W::new(self) + } + #[doc = "Bit 3 - VLCD Ready Toggle Interrupt Disable"] + #[inline(always)] + #[must_use] + pub fn vlcdrt(&mut self) -> VLCDRT_W<3> { + VLCDRT_W::new(self) + } + #[doc = "Bit 4 - VLCD Status Toggle Interrupt Disable"] + #[inline(always)] + #[must_use] + pub fn vlcdst(&mut self) -> VLCDST_W<4> { + VLCDST_W::new(self) + } + #[doc = "Bit 5 - Pump Run Status Toggle Interrupt Disable"] + #[inline(always)] + #[must_use] + pub fn prst(&mut self) -> PRST_W<5> { + PRST_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/slcd/intenset.rs b/pac/atsaml22j/src/slcd/intenset.rs new file mode 100644 index 000000000000..f1f36ae57b1f --- /dev/null +++ b/pac/atsaml22j/src/slcd/intenset.rs @@ -0,0 +1,155 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FC0O` reader - Frame Counter 0 Overflow Interrupt Enable"] +pub type FC0O_R = crate::BitReader; +#[doc = "Field `FC0O` writer - Frame Counter 0 Overflow Interrupt Enable"] +pub type FC0O_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENSET_SPEC, bool, O>; +#[doc = "Field `FC1O` reader - Frame Counter 1 Overflow Interrupt Enable"] +pub type FC1O_R = crate::BitReader; +#[doc = "Field `FC1O` writer - Frame Counter 1 Overflow Interrupt Enable"] +pub type FC1O_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENSET_SPEC, bool, O>; +#[doc = "Field `FC2O` reader - Frame Counter 2 Overflow Interrupt Enable"] +pub type FC2O_R = crate::BitReader; +#[doc = "Field `FC2O` writer - Frame Counter 2 Overflow Interrupt Enable"] +pub type FC2O_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENSET_SPEC, bool, O>; +#[doc = "Field `VLCDRT` reader - VLCD Ready Toggle Interrupt Enable"] +pub type VLCDRT_R = crate::BitReader; +#[doc = "Field `VLCDRT` writer - VLCD Ready Toggle Interrupt Enable"] +pub type VLCDRT_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENSET_SPEC, bool, O>; +#[doc = "Field `VLCDST` reader - VLCD Status Toggle Interrupt Enable"] +pub type VLCDST_R = crate::BitReader; +#[doc = "Field `VLCDST` writer - VLCD Status Toggle Interrupt Enable"] +pub type VLCDST_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENSET_SPEC, bool, O>; +#[doc = "Field `PRST` reader - Pump Run Status Toggle Interrupt Enable"] +pub type PRST_R = crate::BitReader; +#[doc = "Field `PRST` writer - Pump Run Status Toggle Interrupt Enable"] +pub type PRST_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENSET_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Frame Counter 0 Overflow Interrupt Enable"] + #[inline(always)] + pub fn fc0o(&self) -> FC0O_R { + FC0O_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Frame Counter 1 Overflow Interrupt Enable"] + #[inline(always)] + pub fn fc1o(&self) -> FC1O_R { + FC1O_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Frame Counter 2 Overflow Interrupt Enable"] + #[inline(always)] + pub fn fc2o(&self) -> FC2O_R { + FC2O_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - VLCD Ready Toggle Interrupt Enable"] + #[inline(always)] + pub fn vlcdrt(&self) -> VLCDRT_R { + VLCDRT_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - VLCD Status Toggle Interrupt Enable"] + #[inline(always)] + pub fn vlcdst(&self) -> VLCDST_R { + VLCDST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Pump Run Status Toggle Interrupt Enable"] + #[inline(always)] + pub fn prst(&self) -> PRST_R { + PRST_R::new(((self.bits >> 5) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Frame Counter 0 Overflow Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn fc0o(&mut self) -> FC0O_W<0> { + FC0O_W::new(self) + } + #[doc = "Bit 1 - Frame Counter 1 Overflow Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn fc1o(&mut self) -> FC1O_W<1> { + FC1O_W::new(self) + } + #[doc = "Bit 2 - Frame Counter 2 Overflow Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn fc2o(&mut self) -> FC2O_W<2> { + FC2O_W::new(self) + } + #[doc = "Bit 3 - VLCD Ready Toggle Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn vlcdrt(&mut self) -> VLCDRT_W<3> { + VLCDRT_W::new(self) + } + #[doc = "Bit 4 - VLCD Status Toggle Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn vlcdst(&mut self) -> VLCDST_W<4> { + VLCDST_W::new(self) + } + #[doc = "Bit 5 - Pump Run Status Toggle Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn prst(&mut self) -> PRST_W<5> { + PRST_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/slcd/intflag.rs b/pac/atsaml22j/src/slcd/intflag.rs new file mode 100644 index 000000000000..a9a1c1458522 --- /dev/null +++ b/pac/atsaml22j/src/slcd/intflag.rs @@ -0,0 +1,155 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `FC0O` reader - Frame Counter 0 Overflow"] +pub type FC0O_R = crate::BitReader; +#[doc = "Field `FC0O` writer - Frame Counter 0 Overflow"] +pub type FC0O_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTFLAG_SPEC, bool, O>; +#[doc = "Field `FC1O` reader - Frame Counter 1 Overflow"] +pub type FC1O_R = crate::BitReader; +#[doc = "Field `FC1O` writer - Frame Counter 1 Overflow"] +pub type FC1O_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTFLAG_SPEC, bool, O>; +#[doc = "Field `FC2O` reader - Frame Counter 2 Overflow"] +pub type FC2O_R = crate::BitReader; +#[doc = "Field `FC2O` writer - Frame Counter 2 Overflow"] +pub type FC2O_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTFLAG_SPEC, bool, O>; +#[doc = "Field `VLCDRT` reader - VLCD Ready Toggle"] +pub type VLCDRT_R = crate::BitReader; +#[doc = "Field `VLCDRT` writer - VLCD Ready Toggle"] +pub type VLCDRT_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTFLAG_SPEC, bool, O>; +#[doc = "Field `VLCDST` reader - VLCD Status Toggle"] +pub type VLCDST_R = crate::BitReader; +#[doc = "Field `VLCDST` writer - VLCD Status Toggle"] +pub type VLCDST_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTFLAG_SPEC, bool, O>; +#[doc = "Field `PRST` reader - Pump Run Status Toggle"] +pub type PRST_R = crate::BitReader; +#[doc = "Field `PRST` writer - Pump Run Status Toggle"] +pub type PRST_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTFLAG_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Frame Counter 0 Overflow"] + #[inline(always)] + pub fn fc0o(&self) -> FC0O_R { + FC0O_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Frame Counter 1 Overflow"] + #[inline(always)] + pub fn fc1o(&self) -> FC1O_R { + FC1O_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Frame Counter 2 Overflow"] + #[inline(always)] + pub fn fc2o(&self) -> FC2O_R { + FC2O_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - VLCD Ready Toggle"] + #[inline(always)] + pub fn vlcdrt(&self) -> VLCDRT_R { + VLCDRT_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - VLCD Status Toggle"] + #[inline(always)] + pub fn vlcdst(&self) -> VLCDST_R { + VLCDST_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Pump Run Status Toggle"] + #[inline(always)] + pub fn prst(&self) -> PRST_R { + PRST_R::new(((self.bits >> 5) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Frame Counter 0 Overflow"] + #[inline(always)] + #[must_use] + pub fn fc0o(&mut self) -> FC0O_W<0> { + FC0O_W::new(self) + } + #[doc = "Bit 1 - Frame Counter 1 Overflow"] + #[inline(always)] + #[must_use] + pub fn fc1o(&mut self) -> FC1O_W<1> { + FC1O_W::new(self) + } + #[doc = "Bit 2 - Frame Counter 2 Overflow"] + #[inline(always)] + #[must_use] + pub fn fc2o(&mut self) -> FC2O_W<2> { + FC2O_W::new(self) + } + #[doc = "Bit 3 - VLCD Ready Toggle"] + #[inline(always)] + #[must_use] + pub fn vlcdrt(&mut self) -> VLCDRT_W<3> { + VLCDRT_W::new(self) + } + #[doc = "Bit 4 - VLCD Status Toggle"] + #[inline(always)] + #[must_use] + pub fn vlcdst(&mut self) -> VLCDST_W<4> { + VLCDST_W::new(self) + } + #[doc = "Bit 5 - Pump Run Status Toggle"] + #[inline(always)] + #[must_use] + pub fn prst(&mut self) -> PRST_W<5> { + PRST_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/slcd/isdata.rs b/pac/atsaml22j/src/slcd/isdata.rs new file mode 100644 index 000000000000..76b33a5e0e3c --- /dev/null +++ b/pac/atsaml22j/src/slcd/isdata.rs @@ -0,0 +1,68 @@ +#[doc = "Register `ISDATA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SDATA` writer - Segments Data"] +pub type SDATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ISDATA_SPEC, u8, u8, 8, O>; +#[doc = "Field `SDMASK` writer - Segments Data Mask"] +pub type SDMASK_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ISDATA_SPEC, u8, u8, 8, O>; +#[doc = "Field `OFF` writer - Byte Offset"] +pub type OFF_W<'a, const O: u8> = crate::FieldWriter<'a, u32, ISDATA_SPEC, u8, u8, 6, O>; +impl W { + #[doc = "Bits 0:7 - Segments Data"] + #[inline(always)] + #[must_use] + pub fn sdata(&mut self) -> SDATA_W<0> { + SDATA_W::new(self) + } + #[doc = "Bits 8:15 - Segments Data Mask"] + #[inline(always)] + #[must_use] + pub fn sdmask(&mut self) -> SDMASK_W<8> { + SDMASK_W::new(self) + } + #[doc = "Bits 16:21 - Byte Offset"] + #[inline(always)] + #[must_use] + pub fn off(&mut self) -> OFF_W<16> { + OFF_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Indirect Segments Data Access\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [isdata](index.html) module"] +pub struct ISDATA_SPEC; +impl crate::RegisterSpec for ISDATA_SPEC { + type Ux = u32; +} +#[doc = "`write(|w| ..)` method takes [isdata::W](W) writer structure"] +impl crate::Writable for ISDATA_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets ISDATA to value 0"] +impl crate::Resettable for ISDATA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/slcd/lpenh.rs b/pac/atsaml22j/src/slcd/lpenh.rs new file mode 100644 index 000000000000..974113ebeda7 --- /dev/null +++ b/pac/atsaml22j/src/slcd/lpenh.rs @@ -0,0 +1,80 @@ +#[doc = "Register `LPENH` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LPENH` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LPEN` reader - LCD Pin Enable"] +pub type LPEN_R = crate::FieldReader; +#[doc = "Field `LPEN` writer - LCD Pin Enable"] +pub type LPEN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, LPENH_SPEC, u32, u32, 20, O>; +impl R { + #[doc = "Bits 0:19 - LCD Pin Enable"] + #[inline(always)] + pub fn lpen(&self) -> LPEN_R { + LPEN_R::new(self.bits & 0x000f_ffff) + } +} +impl W { + #[doc = "Bits 0:19 - LCD Pin Enable"] + #[inline(always)] + #[must_use] + pub fn lpen(&mut self) -> LPEN_W<0> { + LPEN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "LCD Pin Enable High\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lpenh](index.html) module"] +pub struct LPENH_SPEC; +impl crate::RegisterSpec for LPENH_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [lpenh::R](R) reader structure"] +impl crate::Readable for LPENH_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [lpenh::W](W) writer structure"] +impl crate::Writable for LPENH_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LPENH to value 0"] +impl crate::Resettable for LPENH_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/slcd/lpenl.rs b/pac/atsaml22j/src/slcd/lpenl.rs new file mode 100644 index 000000000000..ff76d166fb17 --- /dev/null +++ b/pac/atsaml22j/src/slcd/lpenl.rs @@ -0,0 +1,80 @@ +#[doc = "Register `LPENL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `LPENL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `LPEN` reader - LCD Pin Enable"] +pub type LPEN_R = crate::FieldReader; +#[doc = "Field `LPEN` writer - LCD Pin Enable"] +pub type LPEN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, LPENL_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - LCD Pin Enable"] + #[inline(always)] + pub fn lpen(&self) -> LPEN_R { + LPEN_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - LCD Pin Enable"] + #[inline(always)] + #[must_use] + pub fn lpen(&mut self) -> LPEN_W<0> { + LPEN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "LCD Pin Enable Low\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lpenl](index.html) module"] +pub struct LPENL_SPEC; +impl crate::RegisterSpec for LPENL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [lpenl::R](R) reader structure"] +impl crate::Readable for LPENL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [lpenl::W](W) writer structure"] +impl crate::Writable for LPENL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets LPENL to value 0"] +impl crate::Resettable for LPENL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/slcd/sdatah0.rs b/pac/atsaml22j/src/slcd/sdatah0.rs new file mode 100644 index 000000000000..f42f0b3c87a7 --- /dev/null +++ b/pac/atsaml22j/src/slcd/sdatah0.rs @@ -0,0 +1,80 @@ +#[doc = "Register `SDATAH0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SDATAH0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SDATA` reader - Segments Data"] +pub type SDATA_R = crate::FieldReader; +#[doc = "Field `SDATA` writer - Segments Data"] +pub type SDATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SDATAH0_SPEC, u16, u16, 12, O>; +impl R { + #[doc = "Bits 0:11 - Segments Data"] + #[inline(always)] + pub fn sdata(&self) -> SDATA_R { + SDATA_R::new((self.bits & 0x0fff) as u16) + } +} +impl W { + #[doc = "Bits 0:11 - Segments Data"] + #[inline(always)] + #[must_use] + pub fn sdata(&mut self) -> SDATA_W<0> { + SDATA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Segments Data High for COM0 Line\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sdatah0](index.html) module"] +pub struct SDATAH0_SPEC; +impl crate::RegisterSpec for SDATAH0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sdatah0::R](R) reader structure"] +impl crate::Readable for SDATAH0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sdatah0::W](W) writer structure"] +impl crate::Writable for SDATAH0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SDATAH0 to value 0"] +impl crate::Resettable for SDATAH0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/slcd/sdatah1.rs b/pac/atsaml22j/src/slcd/sdatah1.rs new file mode 100644 index 000000000000..e31237507cf7 --- /dev/null +++ b/pac/atsaml22j/src/slcd/sdatah1.rs @@ -0,0 +1,80 @@ +#[doc = "Register `SDATAH1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SDATAH1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SDATA` reader - Segments Data"] +pub type SDATA_R = crate::FieldReader; +#[doc = "Field `SDATA` writer - Segments Data"] +pub type SDATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SDATAH1_SPEC, u16, u16, 12, O>; +impl R { + #[doc = "Bits 0:11 - Segments Data"] + #[inline(always)] + pub fn sdata(&self) -> SDATA_R { + SDATA_R::new((self.bits & 0x0fff) as u16) + } +} +impl W { + #[doc = "Bits 0:11 - Segments Data"] + #[inline(always)] + #[must_use] + pub fn sdata(&mut self) -> SDATA_W<0> { + SDATA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Segments Data High for COM1 Line\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sdatah1](index.html) module"] +pub struct SDATAH1_SPEC; +impl crate::RegisterSpec for SDATAH1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sdatah1::R](R) reader structure"] +impl crate::Readable for SDATAH1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sdatah1::W](W) writer structure"] +impl crate::Writable for SDATAH1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SDATAH1 to value 0"] +impl crate::Resettable for SDATAH1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/slcd/sdatah2.rs b/pac/atsaml22j/src/slcd/sdatah2.rs new file mode 100644 index 000000000000..64c2a7a32547 --- /dev/null +++ b/pac/atsaml22j/src/slcd/sdatah2.rs @@ -0,0 +1,80 @@ +#[doc = "Register `SDATAH2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SDATAH2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SDATA` reader - Segments Data"] +pub type SDATA_R = crate::FieldReader; +#[doc = "Field `SDATA` writer - Segments Data"] +pub type SDATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SDATAH2_SPEC, u16, u16, 12, O>; +impl R { + #[doc = "Bits 0:11 - Segments Data"] + #[inline(always)] + pub fn sdata(&self) -> SDATA_R { + SDATA_R::new((self.bits & 0x0fff) as u16) + } +} +impl W { + #[doc = "Bits 0:11 - Segments Data"] + #[inline(always)] + #[must_use] + pub fn sdata(&mut self) -> SDATA_W<0> { + SDATA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Segments Data High for COM2 Line\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sdatah2](index.html) module"] +pub struct SDATAH2_SPEC; +impl crate::RegisterSpec for SDATAH2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sdatah2::R](R) reader structure"] +impl crate::Readable for SDATAH2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sdatah2::W](W) writer structure"] +impl crate::Writable for SDATAH2_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SDATAH2 to value 0"] +impl crate::Resettable for SDATAH2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/slcd/sdatah3.rs b/pac/atsaml22j/src/slcd/sdatah3.rs new file mode 100644 index 000000000000..4f4ca6f53fd2 --- /dev/null +++ b/pac/atsaml22j/src/slcd/sdatah3.rs @@ -0,0 +1,80 @@ +#[doc = "Register `SDATAH3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SDATAH3` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SDATA` reader - Segments Data"] +pub type SDATA_R = crate::FieldReader; +#[doc = "Field `SDATA` writer - Segments Data"] +pub type SDATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SDATAH3_SPEC, u16, u16, 12, O>; +impl R { + #[doc = "Bits 0:11 - Segments Data"] + #[inline(always)] + pub fn sdata(&self) -> SDATA_R { + SDATA_R::new((self.bits & 0x0fff) as u16) + } +} +impl W { + #[doc = "Bits 0:11 - Segments Data"] + #[inline(always)] + #[must_use] + pub fn sdata(&mut self) -> SDATA_W<0> { + SDATA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Segments Data High for COM3 Line\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sdatah3](index.html) module"] +pub struct SDATAH3_SPEC; +impl crate::RegisterSpec for SDATAH3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sdatah3::R](R) reader structure"] +impl crate::Readable for SDATAH3_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sdatah3::W](W) writer structure"] +impl crate::Writable for SDATAH3_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SDATAH3 to value 0"] +impl crate::Resettable for SDATAH3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/slcd/sdatah4.rs b/pac/atsaml22j/src/slcd/sdatah4.rs new file mode 100644 index 000000000000..e66a362c23fd --- /dev/null +++ b/pac/atsaml22j/src/slcd/sdatah4.rs @@ -0,0 +1,80 @@ +#[doc = "Register `SDATAH4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SDATAH4` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SDATA` reader - Segments Data"] +pub type SDATA_R = crate::FieldReader; +#[doc = "Field `SDATA` writer - Segments Data"] +pub type SDATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SDATAH4_SPEC, u16, u16, 10, O>; +impl R { + #[doc = "Bits 0:9 - Segments Data"] + #[inline(always)] + pub fn sdata(&self) -> SDATA_R { + SDATA_R::new((self.bits & 0x03ff) as u16) + } +} +impl W { + #[doc = "Bits 0:9 - Segments Data"] + #[inline(always)] + #[must_use] + pub fn sdata(&mut self) -> SDATA_W<0> { + SDATA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Segments Data High for COM4 Line\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sdatah4](index.html) module"] +pub struct SDATAH4_SPEC; +impl crate::RegisterSpec for SDATAH4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sdatah4::R](R) reader structure"] +impl crate::Readable for SDATAH4_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sdatah4::W](W) writer structure"] +impl crate::Writable for SDATAH4_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SDATAH4 to value 0"] +impl crate::Resettable for SDATAH4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/slcd/sdatah5.rs b/pac/atsaml22j/src/slcd/sdatah5.rs new file mode 100644 index 000000000000..8390d367224b --- /dev/null +++ b/pac/atsaml22j/src/slcd/sdatah5.rs @@ -0,0 +1,80 @@ +#[doc = "Register `SDATAH5` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SDATAH5` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SDATA` reader - Segments Data"] +pub type SDATA_R = crate::FieldReader; +#[doc = "Field `SDATA` writer - Segments Data"] +pub type SDATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SDATAH5_SPEC, u16, u16, 10, O>; +impl R { + #[doc = "Bits 0:9 - Segments Data"] + #[inline(always)] + pub fn sdata(&self) -> SDATA_R { + SDATA_R::new((self.bits & 0x03ff) as u16) + } +} +impl W { + #[doc = "Bits 0:9 - Segments Data"] + #[inline(always)] + #[must_use] + pub fn sdata(&mut self) -> SDATA_W<0> { + SDATA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Segments Data High for COM5 Line\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sdatah5](index.html) module"] +pub struct SDATAH5_SPEC; +impl crate::RegisterSpec for SDATAH5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sdatah5::R](R) reader structure"] +impl crate::Readable for SDATAH5_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sdatah5::W](W) writer structure"] +impl crate::Writable for SDATAH5_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SDATAH5 to value 0"] +impl crate::Resettable for SDATAH5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/slcd/sdatah6.rs b/pac/atsaml22j/src/slcd/sdatah6.rs new file mode 100644 index 000000000000..c43117408cbf --- /dev/null +++ b/pac/atsaml22j/src/slcd/sdatah6.rs @@ -0,0 +1,80 @@ +#[doc = "Register `SDATAH6` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SDATAH6` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SDATA` reader - Segments Data"] +pub type SDATA_R = crate::FieldReader; +#[doc = "Field `SDATA` writer - Segments Data"] +pub type SDATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SDATAH6_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Segments Data"] + #[inline(always)] + pub fn sdata(&self) -> SDATA_R { + SDATA_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Segments Data"] + #[inline(always)] + #[must_use] + pub fn sdata(&mut self) -> SDATA_W<0> { + SDATA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Segments Data High for COM6 Line\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sdatah6](index.html) module"] +pub struct SDATAH6_SPEC; +impl crate::RegisterSpec for SDATAH6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sdatah6::R](R) reader structure"] +impl crate::Readable for SDATAH6_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sdatah6::W](W) writer structure"] +impl crate::Writable for SDATAH6_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SDATAH6 to value 0"] +impl crate::Resettable for SDATAH6_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/slcd/sdatah7.rs b/pac/atsaml22j/src/slcd/sdatah7.rs new file mode 100644 index 000000000000..f86038460daa --- /dev/null +++ b/pac/atsaml22j/src/slcd/sdatah7.rs @@ -0,0 +1,80 @@ +#[doc = "Register `SDATAH7` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SDATAH7` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SDATA` reader - Segments Data"] +pub type SDATA_R = crate::FieldReader; +#[doc = "Field `SDATA` writer - Segments Data"] +pub type SDATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SDATAH7_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Segments Data"] + #[inline(always)] + pub fn sdata(&self) -> SDATA_R { + SDATA_R::new((self.bits & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:7 - Segments Data"] + #[inline(always)] + #[must_use] + pub fn sdata(&mut self) -> SDATA_W<0> { + SDATA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Segments Data High for COM7 Line\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sdatah7](index.html) module"] +pub struct SDATAH7_SPEC; +impl crate::RegisterSpec for SDATAH7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sdatah7::R](R) reader structure"] +impl crate::Readable for SDATAH7_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sdatah7::W](W) writer structure"] +impl crate::Writable for SDATAH7_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SDATAH7 to value 0"] +impl crate::Resettable for SDATAH7_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/slcd/sdatal0.rs b/pac/atsaml22j/src/slcd/sdatal0.rs new file mode 100644 index 000000000000..9f22c41b66e3 --- /dev/null +++ b/pac/atsaml22j/src/slcd/sdatal0.rs @@ -0,0 +1,80 @@ +#[doc = "Register `SDATAL0` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SDATAL0` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SDATA` reader - Segments Data"] +pub type SDATA_R = crate::FieldReader; +#[doc = "Field `SDATA` writer - Segments Data"] +pub type SDATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SDATAL0_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - Segments Data"] + #[inline(always)] + pub fn sdata(&self) -> SDATA_R { + SDATA_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Segments Data"] + #[inline(always)] + #[must_use] + pub fn sdata(&mut self) -> SDATA_W<0> { + SDATA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Segments Data Low for COM0 Line\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sdatal0](index.html) module"] +pub struct SDATAL0_SPEC; +impl crate::RegisterSpec for SDATAL0_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sdatal0::R](R) reader structure"] +impl crate::Readable for SDATAL0_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sdatal0::W](W) writer structure"] +impl crate::Writable for SDATAL0_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SDATAL0 to value 0"] +impl crate::Resettable for SDATAL0_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/slcd/sdatal1.rs b/pac/atsaml22j/src/slcd/sdatal1.rs new file mode 100644 index 000000000000..fec15a286f32 --- /dev/null +++ b/pac/atsaml22j/src/slcd/sdatal1.rs @@ -0,0 +1,80 @@ +#[doc = "Register `SDATAL1` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SDATAL1` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SDATA` reader - Segments Data"] +pub type SDATA_R = crate::FieldReader; +#[doc = "Field `SDATA` writer - Segments Data"] +pub type SDATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SDATAL1_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - Segments Data"] + #[inline(always)] + pub fn sdata(&self) -> SDATA_R { + SDATA_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Segments Data"] + #[inline(always)] + #[must_use] + pub fn sdata(&mut self) -> SDATA_W<0> { + SDATA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Segments Data Low for COM1 Line\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sdatal1](index.html) module"] +pub struct SDATAL1_SPEC; +impl crate::RegisterSpec for SDATAL1_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sdatal1::R](R) reader structure"] +impl crate::Readable for SDATAL1_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sdatal1::W](W) writer structure"] +impl crate::Writable for SDATAL1_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SDATAL1 to value 0"] +impl crate::Resettable for SDATAL1_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/slcd/sdatal2.rs b/pac/atsaml22j/src/slcd/sdatal2.rs new file mode 100644 index 000000000000..95eae04cec2c --- /dev/null +++ b/pac/atsaml22j/src/slcd/sdatal2.rs @@ -0,0 +1,80 @@ +#[doc = "Register `SDATAL2` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SDATAL2` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SDATA` reader - Segments Data"] +pub type SDATA_R = crate::FieldReader; +#[doc = "Field `SDATA` writer - Segments Data"] +pub type SDATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SDATAL2_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - Segments Data"] + #[inline(always)] + pub fn sdata(&self) -> SDATA_R { + SDATA_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Segments Data"] + #[inline(always)] + #[must_use] + pub fn sdata(&mut self) -> SDATA_W<0> { + SDATA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Segments Data Low for COM2 Line\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sdatal2](index.html) module"] +pub struct SDATAL2_SPEC; +impl crate::RegisterSpec for SDATAL2_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sdatal2::R](R) reader structure"] +impl crate::Readable for SDATAL2_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sdatal2::W](W) writer structure"] +impl crate::Writable for SDATAL2_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SDATAL2 to value 0"] +impl crate::Resettable for SDATAL2_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/slcd/sdatal3.rs b/pac/atsaml22j/src/slcd/sdatal3.rs new file mode 100644 index 000000000000..e4f6d7c046bb --- /dev/null +++ b/pac/atsaml22j/src/slcd/sdatal3.rs @@ -0,0 +1,80 @@ +#[doc = "Register `SDATAL3` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SDATAL3` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SDATA` reader - Segments Data"] +pub type SDATA_R = crate::FieldReader; +#[doc = "Field `SDATA` writer - Segments Data"] +pub type SDATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SDATAL3_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - Segments Data"] + #[inline(always)] + pub fn sdata(&self) -> SDATA_R { + SDATA_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Segments Data"] + #[inline(always)] + #[must_use] + pub fn sdata(&mut self) -> SDATA_W<0> { + SDATA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Segments Data Low for COM3 Line\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sdatal3](index.html) module"] +pub struct SDATAL3_SPEC; +impl crate::RegisterSpec for SDATAL3_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sdatal3::R](R) reader structure"] +impl crate::Readable for SDATAL3_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sdatal3::W](W) writer structure"] +impl crate::Writable for SDATAL3_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SDATAL3 to value 0"] +impl crate::Resettable for SDATAL3_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/slcd/sdatal4.rs b/pac/atsaml22j/src/slcd/sdatal4.rs new file mode 100644 index 000000000000..7d03e81436df --- /dev/null +++ b/pac/atsaml22j/src/slcd/sdatal4.rs @@ -0,0 +1,80 @@ +#[doc = "Register `SDATAL4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SDATAL4` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SDATA` reader - Segments Data"] +pub type SDATA_R = crate::FieldReader; +#[doc = "Field `SDATA` writer - Segments Data"] +pub type SDATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SDATAL4_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - Segments Data"] + #[inline(always)] + pub fn sdata(&self) -> SDATA_R { + SDATA_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Segments Data"] + #[inline(always)] + #[must_use] + pub fn sdata(&mut self) -> SDATA_W<0> { + SDATA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Segments Data Low for COM4 Line\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sdatal4](index.html) module"] +pub struct SDATAL4_SPEC; +impl crate::RegisterSpec for SDATAL4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sdatal4::R](R) reader structure"] +impl crate::Readable for SDATAL4_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sdatal4::W](W) writer structure"] +impl crate::Writable for SDATAL4_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SDATAL4 to value 0"] +impl crate::Resettable for SDATAL4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/slcd/sdatal5.rs b/pac/atsaml22j/src/slcd/sdatal5.rs new file mode 100644 index 000000000000..31e6f2fc4eee --- /dev/null +++ b/pac/atsaml22j/src/slcd/sdatal5.rs @@ -0,0 +1,80 @@ +#[doc = "Register `SDATAL5` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SDATAL5` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SDATA` reader - Segments Data"] +pub type SDATA_R = crate::FieldReader; +#[doc = "Field `SDATA` writer - Segments Data"] +pub type SDATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SDATAL5_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - Segments Data"] + #[inline(always)] + pub fn sdata(&self) -> SDATA_R { + SDATA_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Segments Data"] + #[inline(always)] + #[must_use] + pub fn sdata(&mut self) -> SDATA_W<0> { + SDATA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Segments Data Low for COM5 Line\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sdatal5](index.html) module"] +pub struct SDATAL5_SPEC; +impl crate::RegisterSpec for SDATAL5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sdatal5::R](R) reader structure"] +impl crate::Readable for SDATAL5_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sdatal5::W](W) writer structure"] +impl crate::Writable for SDATAL5_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SDATAL5 to value 0"] +impl crate::Resettable for SDATAL5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/slcd/sdatal6.rs b/pac/atsaml22j/src/slcd/sdatal6.rs new file mode 100644 index 000000000000..dc2f90f2793b --- /dev/null +++ b/pac/atsaml22j/src/slcd/sdatal6.rs @@ -0,0 +1,80 @@ +#[doc = "Register `SDATAL6` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SDATAL6` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SDATA` reader - Segments Data"] +pub type SDATA_R = crate::FieldReader; +#[doc = "Field `SDATA` writer - Segments Data"] +pub type SDATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SDATAL6_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - Segments Data"] + #[inline(always)] + pub fn sdata(&self) -> SDATA_R { + SDATA_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Segments Data"] + #[inline(always)] + #[must_use] + pub fn sdata(&mut self) -> SDATA_W<0> { + SDATA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Segments Data Low for COM6 Line\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sdatal6](index.html) module"] +pub struct SDATAL6_SPEC; +impl crate::RegisterSpec for SDATAL6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sdatal6::R](R) reader structure"] +impl crate::Readable for SDATAL6_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sdatal6::W](W) writer structure"] +impl crate::Writable for SDATAL6_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SDATAL6 to value 0"] +impl crate::Resettable for SDATAL6_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/slcd/sdatal7.rs b/pac/atsaml22j/src/slcd/sdatal7.rs new file mode 100644 index 000000000000..af40329cca61 --- /dev/null +++ b/pac/atsaml22j/src/slcd/sdatal7.rs @@ -0,0 +1,80 @@ +#[doc = "Register `SDATAL7` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `SDATAL7` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SDATA` reader - Segments Data"] +pub type SDATA_R = crate::FieldReader; +#[doc = "Field `SDATA` writer - Segments Data"] +pub type SDATA_W<'a, const O: u8> = crate::FieldWriter<'a, u32, SDATAL7_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - Segments Data"] + #[inline(always)] + pub fn sdata(&self) -> SDATA_R { + SDATA_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Segments Data"] + #[inline(always)] + #[must_use] + pub fn sdata(&mut self) -> SDATA_W<0> { + SDATA_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Segments Data Low for COM7 Line\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sdatal7](index.html) module"] +pub struct SDATAL7_SPEC; +impl crate::RegisterSpec for SDATAL7_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [sdatal7::R](R) reader structure"] +impl crate::Readable for SDATAL7_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [sdatal7::W](W) writer structure"] +impl crate::Writable for SDATAL7_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets SDATAL7 to value 0"] +impl crate::Resettable for SDATAL7_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/slcd/status.rs b/pac/atsaml22j/src/slcd/status.rs new file mode 100644 index 000000000000..4a5fe6b9c2a4 --- /dev/null +++ b/pac/atsaml22j/src/slcd/status.rs @@ -0,0 +1,72 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `VLCDR` reader - VLCD Ready"] +pub type VLCDR_R = crate::BitReader; +#[doc = "Field `PRUN` reader - LCD Charge Pump is Running"] +pub type PRUN_R = crate::BitReader; +#[doc = "Field `VLCDS` reader - VLCD Status"] +pub type VLCDS_R = crate::BitReader; +#[doc = "Field `CMWRBUSY` reader - Character mapping write busy"] +pub type CMWRBUSY_R = crate::BitReader; +#[doc = "Field `ACMBUSY` reader - ACM state machine busy"] +pub type ACMBUSY_R = crate::BitReader; +#[doc = "Field `ABMBUSY` reader - ABM state machine busy"] +pub type ABMBUSY_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - VLCD Ready"] + #[inline(always)] + pub fn vlcdr(&self) -> VLCDR_R { + VLCDR_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - LCD Charge Pump is Running"] + #[inline(always)] + pub fn prun(&self) -> PRUN_R { + PRUN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - VLCD Status"] + #[inline(always)] + pub fn vlcds(&self) -> VLCDS_R { + VLCDS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Character mapping write busy"] + #[inline(always)] + pub fn cmwrbusy(&self) -> CMWRBUSY_R { + CMWRBUSY_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - ACM state machine busy"] + #[inline(always)] + pub fn acmbusy(&self) -> ACMBUSY_R { + ACMBUSY_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - ABM state machine busy"] + #[inline(always)] + pub fn abmbusy(&self) -> ABMBUSY_R { + ABMBUSY_R::new(((self.bits >> 5) & 1) != 0) + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/slcd/syncbusy.rs b/pac/atsaml22j/src/slcd/syncbusy.rs new file mode 100644 index 000000000000..2cbeeb08130d --- /dev/null +++ b/pac/atsaml22j/src/slcd/syncbusy.rs @@ -0,0 +1,51 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub type SWRST_R = crate::BitReader; +#[doc = "Field `ENABLE` reader - Enable"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `CTRLD` reader - Control D"] +pub type CTRLD_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Control D"] + #[inline(always)] + pub fn ctrld(&self) -> CTRLD_R { + CTRLD_R::new(((self.bits >> 2) & 1) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/supc.rs b/pac/atsaml22j/src/supc.rs new file mode 100644 index 000000000000..f3ab123d6f5d --- /dev/null +++ b/pac/atsaml22j/src/supc.rs @@ -0,0 +1,70 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Interrupt Enable Clear"] + pub intenclr: INTENCLR, + #[doc = "0x04 - Interrupt Enable Set"] + pub intenset: INTENSET, + #[doc = "0x08 - Interrupt Flag Status and Clear"] + pub intflag: INTFLAG, + #[doc = "0x0c - Power and Clocks Status"] + pub status: STATUS, + #[doc = "0x10 - BOD33 Control"] + pub bod33: BOD33, + #[doc = "0x14 - BOD12 Control"] + pub bod12: BOD12, + #[doc = "0x18 - VREG Control"] + pub vreg: VREG, + #[doc = "0x1c - VREF Control"] + pub vref: VREF, + #[doc = "0x20 - Battery Backup Power Switch"] + pub bbps: BBPS, + #[doc = "0x24 - Backup Output Control"] + pub bkout: BKOUT, + #[doc = "0x28 - Backup Input Control"] + pub bkin: BKIN, +} +#[doc = "INTENCLR (rw) register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET (rw) register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG (rw) register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS (r) register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Power and Clocks Status"] +pub mod status; +#[doc = "BOD33 (rw) register accessor: an alias for `Reg`"] +pub type BOD33 = crate::Reg; +#[doc = "BOD33 Control"] +pub mod bod33; +#[doc = "BOD12 (rw) register accessor: an alias for `Reg`"] +pub type BOD12 = crate::Reg; +#[doc = "BOD12 Control"] +pub mod bod12; +#[doc = "VREG (rw) register accessor: an alias for `Reg`"] +pub type VREG = crate::Reg; +#[doc = "VREG Control"] +pub mod vreg; +#[doc = "VREF (rw) register accessor: an alias for `Reg`"] +pub type VREF = crate::Reg; +#[doc = "VREF Control"] +pub mod vref; +#[doc = "BBPS (rw) register accessor: an alias for `Reg`"] +pub type BBPS = crate::Reg; +#[doc = "Battery Backup Power Switch"] +pub mod bbps; +#[doc = "BKOUT (rw) register accessor: an alias for `Reg`"] +pub type BKOUT = crate::Reg; +#[doc = "Backup Output Control"] +pub mod bkout; +#[doc = "BKIN (r) register accessor: an alias for `Reg`"] +pub type BKIN = crate::Reg; +#[doc = "Backup Input Control"] +pub mod bkin; diff --git a/pac/atsaml22j/src/supc/bbps.rs b/pac/atsaml22j/src/supc/bbps.rs new file mode 100644 index 000000000000..14b90ef7f18c --- /dev/null +++ b/pac/atsaml22j/src/supc/bbps.rs @@ -0,0 +1,185 @@ +#[doc = "Register `BBPS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BBPS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CONF` reader - Battery Backup Configuration"] +pub type CONF_R = crate::FieldReader; +#[doc = "Battery Backup Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum CONFSELECT_A { + #[doc = "0: The backup domain is always supplied by main power"] + NONE = 0, + #[doc = "1: The power switch is handled by the automatic power switch"] + APWS = 1, + #[doc = "2: The backup domain is always supplied by battery backup power"] + FORCED = 2, + #[doc = "3: The power switch is handled by the BOD33"] + BOD33 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CONFSELECT_A) -> Self { + variant as _ + } +} +impl CONF_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CONFSELECT_A { + match self.bits { + 0 => CONFSELECT_A::NONE, + 1 => CONFSELECT_A::APWS, + 2 => CONFSELECT_A::FORCED, + 3 => CONFSELECT_A::BOD33, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == CONFSELECT_A::NONE + } + #[doc = "Checks if the value of the field is `APWS`"] + #[inline(always)] + pub fn is_apws(&self) -> bool { + *self == CONFSELECT_A::APWS + } + #[doc = "Checks if the value of the field is `FORCED`"] + #[inline(always)] + pub fn is_forced(&self) -> bool { + *self == CONFSELECT_A::FORCED + } + #[doc = "Checks if the value of the field is `BOD33`"] + #[inline(always)] + pub fn is_bod33(&self) -> bool { + *self == CONFSELECT_A::BOD33 + } +} +#[doc = "Field `CONF` writer - Battery Backup Configuration"] +pub type CONF_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, BBPS_SPEC, u8, CONFSELECT_A, 2, O>; +impl<'a, const O: u8> CONF_W<'a, O> { + #[doc = "The backup domain is always supplied by main power"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CONFSELECT_A::NONE) + } + #[doc = "The power switch is handled by the automatic power switch"] + #[inline(always)] + pub fn apws(self) -> &'a mut W { + self.variant(CONFSELECT_A::APWS) + } + #[doc = "The backup domain is always supplied by battery backup power"] + #[inline(always)] + pub fn forced(self) -> &'a mut W { + self.variant(CONFSELECT_A::FORCED) + } + #[doc = "The power switch is handled by the BOD33"] + #[inline(always)] + pub fn bod33(self) -> &'a mut W { + self.variant(CONFSELECT_A::BOD33) + } +} +#[doc = "Field `WAKEEN` reader - Wake Enable"] +pub type WAKEEN_R = crate::BitReader; +#[doc = "Field `WAKEEN` writer - Wake Enable"] +pub type WAKEEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, BBPS_SPEC, bool, O>; +#[doc = "Field `PSOKEN` reader - Power Supply OK Enable"] +pub type PSOKEN_R = crate::BitReader; +#[doc = "Field `PSOKEN` writer - Power Supply OK Enable"] +pub type PSOKEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, BBPS_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:1 - Battery Backup Configuration"] + #[inline(always)] + pub fn conf(&self) -> CONF_R { + CONF_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 2 - Wake Enable"] + #[inline(always)] + pub fn wakeen(&self) -> WAKEEN_R { + WAKEEN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Power Supply OK Enable"] + #[inline(always)] + pub fn psoken(&self) -> PSOKEN_R { + PSOKEN_R::new(((self.bits >> 3) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:1 - Battery Backup Configuration"] + #[inline(always)] + #[must_use] + pub fn conf(&mut self) -> CONF_W<0> { + CONF_W::new(self) + } + #[doc = "Bit 2 - Wake Enable"] + #[inline(always)] + #[must_use] + pub fn wakeen(&mut self) -> WAKEEN_W<2> { + WAKEEN_W::new(self) + } + #[doc = "Bit 3 - Power Supply OK Enable"] + #[inline(always)] + #[must_use] + pub fn psoken(&mut self) -> PSOKEN_W<3> { + PSOKEN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Battery Backup Power Switch\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bbps](index.html) module"] +pub struct BBPS_SPEC; +impl crate::RegisterSpec for BBPS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [bbps::R](R) reader structure"] +impl crate::Readable for BBPS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [bbps::W](W) writer structure"] +impl crate::Writable for BBPS_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BBPS to value 0"] +impl crate::Resettable for BBPS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/supc/bkin.rs b/pac/atsaml22j/src/supc/bkin.rs new file mode 100644 index 000000000000..7952eda85bb1 --- /dev/null +++ b/pac/atsaml22j/src/supc/bkin.rs @@ -0,0 +1,37 @@ +#[doc = "Register `BKIN` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `BKIN` reader - Backup Input Value"] +pub type BKIN_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:7 - Backup Input Value"] + #[inline(always)] + pub fn bkin(&self) -> BKIN_R { + BKIN_R::new((self.bits & 0xff) as u8) + } +} +#[doc = "Backup Input Control\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bkin](index.html) module"] +pub struct BKIN_SPEC; +impl crate::RegisterSpec for BKIN_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [bkin::R](R) reader structure"] +impl crate::Readable for BKIN_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets BKIN to value 0"] +impl crate::Resettable for BKIN_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/supc/bkout.rs b/pac/atsaml22j/src/supc/bkout.rs new file mode 100644 index 000000000000..67d65a248374 --- /dev/null +++ b/pac/atsaml22j/src/supc/bkout.rs @@ -0,0 +1,111 @@ +#[doc = "Register `BKOUT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BKOUT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EN` reader - Enable Output"] +pub type EN_R = crate::FieldReader; +#[doc = "Field `EN` writer - Enable Output"] +pub type EN_W<'a, const O: u8> = crate::FieldWriter<'a, u32, BKOUT_SPEC, u8, u8, 2, O>; +#[doc = "Field `CLR` writer - Clear Output"] +pub type CLR_W<'a, const O: u8> = crate::FieldWriter<'a, u32, BKOUT_SPEC, u8, u8, 2, O>; +#[doc = "Field `SET` writer - Set Output"] +pub type SET_W<'a, const O: u8> = crate::FieldWriter<'a, u32, BKOUT_SPEC, u8, u8, 2, O>; +#[doc = "Field `RTCTGL` reader - RTC Toggle Output"] +pub type RTCTGL_R = crate::FieldReader; +#[doc = "Field `RTCTGL` writer - RTC Toggle Output"] +pub type RTCTGL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, BKOUT_SPEC, u8, u8, 2, O>; +impl R { + #[doc = "Bits 0:1 - Enable Output"] + #[inline(always)] + pub fn en(&self) -> EN_R { + EN_R::new((self.bits & 3) as u8) + } + #[doc = "Bits 24:25 - RTC Toggle Output"] + #[inline(always)] + pub fn rtctgl(&self) -> RTCTGL_R { + RTCTGL_R::new(((self.bits >> 24) & 3) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Enable Output"] + #[inline(always)] + #[must_use] + pub fn en(&mut self) -> EN_W<0> { + EN_W::new(self) + } + #[doc = "Bits 8:9 - Clear Output"] + #[inline(always)] + #[must_use] + pub fn clr(&mut self) -> CLR_W<8> { + CLR_W::new(self) + } + #[doc = "Bits 16:17 - Set Output"] + #[inline(always)] + #[must_use] + pub fn set(&mut self) -> SET_W<16> { + SET_W::new(self) + } + #[doc = "Bits 24:25 - RTC Toggle Output"] + #[inline(always)] + #[must_use] + pub fn rtctgl(&mut self) -> RTCTGL_W<24> { + RTCTGL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Backup Output Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bkout](index.html) module"] +pub struct BKOUT_SPEC; +impl crate::RegisterSpec for BKOUT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [bkout::R](R) reader structure"] +impl crate::Readable for BKOUT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [bkout::W](W) writer structure"] +impl crate::Writable for BKOUT_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BKOUT to value 0"] +impl crate::Resettable for BKOUT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/supc/bod12.rs b/pac/atsaml22j/src/supc/bod12.rs new file mode 100644 index 000000000000..178c7bdb942f --- /dev/null +++ b/pac/atsaml22j/src/supc/bod12.rs @@ -0,0 +1,478 @@ +#[doc = "Register `BOD12` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BOD12` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - Enable"] +pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, BOD12_SPEC, bool, O>; +#[doc = "Field `HYST` reader - Hysteresis Enable"] +pub type HYST_R = crate::BitReader; +#[doc = "Field `HYST` writer - Hysteresis Enable"] +pub type HYST_W<'a, const O: u8> = crate::BitWriter<'a, u32, BOD12_SPEC, bool, O>; +#[doc = "Field `ACTION` reader - Action when Threshold Crossed"] +pub type ACTION_R = crate::FieldReader; +#[doc = "Action when Threshold Crossed\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum ACTIONSELECT_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: The BOD12 generates a reset"] + RESET = 1, + #[doc = "2: The BOD12 generates an interrupt"] + INT = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ACTIONSELECT_A) -> Self { + variant as _ + } +} +impl ACTION_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(ACTIONSELECT_A::NONE), + 1 => Some(ACTIONSELECT_A::RESET), + 2 => Some(ACTIONSELECT_A::INT), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == ACTIONSELECT_A::NONE + } + #[doc = "Checks if the value of the field is `RESET`"] + #[inline(always)] + pub fn is_reset(&self) -> bool { + *self == ACTIONSELECT_A::RESET + } + #[doc = "Checks if the value of the field is `INT`"] + #[inline(always)] + pub fn is_int(&self) -> bool { + *self == ACTIONSELECT_A::INT + } +} +#[doc = "Field `ACTION` writer - Action when Threshold Crossed"] +pub type ACTION_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, BOD12_SPEC, u8, ACTIONSELECT_A, 2, O>; +impl<'a, const O: u8> ACTION_W<'a, O> { + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(ACTIONSELECT_A::NONE) + } + #[doc = "The BOD12 generates a reset"] + #[inline(always)] + pub fn reset(self) -> &'a mut W { + self.variant(ACTIONSELECT_A::RESET) + } + #[doc = "The BOD12 generates an interrupt"] + #[inline(always)] + pub fn int(self) -> &'a mut W { + self.variant(ACTIONSELECT_A::INT) + } +} +#[doc = "Field `STDBYCFG` reader - Configuration in Standby mode"] +pub type STDBYCFG_R = crate::BitReader; +#[doc = "Field `STDBYCFG` writer - Configuration in Standby mode"] +pub type STDBYCFG_W<'a, const O: u8> = crate::BitWriter<'a, u32, BOD12_SPEC, bool, O>; +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub type RUNSTDBY_R = crate::BitReader; +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub type RUNSTDBY_W<'a, const O: u8> = crate::BitWriter<'a, u32, BOD12_SPEC, bool, O>; +#[doc = "Field `ACTCFG` reader - Configuration in Active mode"] +pub type ACTCFG_R = crate::BitReader; +#[doc = "Field `ACTCFG` writer - Configuration in Active mode"] +pub type ACTCFG_W<'a, const O: u8> = crate::BitWriter<'a, u32, BOD12_SPEC, bool, O>; +#[doc = "Field `PSEL` reader - Prescaler Select"] +pub type PSEL_R = crate::FieldReader; +#[doc = "Prescaler Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum PSELSELECT_A { + #[doc = "0: Divide clock by 2"] + DIV2 = 0, + #[doc = "1: Divide clock by 4"] + DIV4 = 1, + #[doc = "2: Divide clock by 8"] + DIV8 = 2, + #[doc = "3: Divide clock by 16"] + DIV16 = 3, + #[doc = "4: Divide clock by 32"] + DIV32 = 4, + #[doc = "5: Divide clock by 64"] + DIV64 = 5, + #[doc = "6: Divide clock by 128"] + DIV128 = 6, + #[doc = "7: Divide clock by 256"] + DIV256 = 7, + #[doc = "8: Divide clock by 512"] + DIV512 = 8, + #[doc = "9: Divide clock by 1024"] + DIV1024 = 9, + #[doc = "10: Divide clock by 2048"] + DIV2048 = 10, + #[doc = "11: Divide clock by 4096"] + DIV4096 = 11, + #[doc = "12: Divide clock by 8192"] + DIV8192 = 12, + #[doc = "13: Divide clock by 16384"] + DIV16384 = 13, + #[doc = "14: Divide clock by 32768"] + DIV32768 = 14, + #[doc = "15: Divide clock by 65536"] + DIV65536 = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PSELSELECT_A) -> Self { + variant as _ + } +} +impl PSEL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PSELSELECT_A { + match self.bits { + 0 => PSELSELECT_A::DIV2, + 1 => PSELSELECT_A::DIV4, + 2 => PSELSELECT_A::DIV8, + 3 => PSELSELECT_A::DIV16, + 4 => PSELSELECT_A::DIV32, + 5 => PSELSELECT_A::DIV64, + 6 => PSELSELECT_A::DIV128, + 7 => PSELSELECT_A::DIV256, + 8 => PSELSELECT_A::DIV512, + 9 => PSELSELECT_A::DIV1024, + 10 => PSELSELECT_A::DIV2048, + 11 => PSELSELECT_A::DIV4096, + 12 => PSELSELECT_A::DIV8192, + 13 => PSELSELECT_A::DIV16384, + 14 => PSELSELECT_A::DIV32768, + 15 => PSELSELECT_A::DIV65536, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + *self == PSELSELECT_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + *self == PSELSELECT_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + *self == PSELSELECT_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + *self == PSELSELECT_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + *self == PSELSELECT_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + *self == PSELSELECT_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + *self == PSELSELECT_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + *self == PSELSELECT_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV512`"] + #[inline(always)] + pub fn is_div512(&self) -> bool { + *self == PSELSELECT_A::DIV512 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + *self == PSELSELECT_A::DIV1024 + } + #[doc = "Checks if the value of the field is `DIV2048`"] + #[inline(always)] + pub fn is_div2048(&self) -> bool { + *self == PSELSELECT_A::DIV2048 + } + #[doc = "Checks if the value of the field is `DIV4096`"] + #[inline(always)] + pub fn is_div4096(&self) -> bool { + *self == PSELSELECT_A::DIV4096 + } + #[doc = "Checks if the value of the field is `DIV8192`"] + #[inline(always)] + pub fn is_div8192(&self) -> bool { + *self == PSELSELECT_A::DIV8192 + } + #[doc = "Checks if the value of the field is `DIV16384`"] + #[inline(always)] + pub fn is_div16384(&self) -> bool { + *self == PSELSELECT_A::DIV16384 + } + #[doc = "Checks if the value of the field is `DIV32768`"] + #[inline(always)] + pub fn is_div32768(&self) -> bool { + *self == PSELSELECT_A::DIV32768 + } + #[doc = "Checks if the value of the field is `DIV65536`"] + #[inline(always)] + pub fn is_div65536(&self) -> bool { + *self == PSELSELECT_A::DIV65536 + } +} +#[doc = "Field `PSEL` writer - Prescaler Select"] +pub type PSEL_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, BOD12_SPEC, u8, PSELSELECT_A, 4, O>; +impl<'a, const O: u8> PSEL_W<'a, O> { + #[doc = "Divide clock by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PSELSELECT_A::DIV2) + } + #[doc = "Divide clock by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PSELSELECT_A::DIV4) + } + #[doc = "Divide clock by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PSELSELECT_A::DIV8) + } + #[doc = "Divide clock by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PSELSELECT_A::DIV16) + } + #[doc = "Divide clock by 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PSELSELECT_A::DIV32) + } + #[doc = "Divide clock by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PSELSELECT_A::DIV64) + } + #[doc = "Divide clock by 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PSELSELECT_A::DIV128) + } + #[doc = "Divide clock by 256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PSELSELECT_A::DIV256) + } + #[doc = "Divide clock by 512"] + #[inline(always)] + pub fn div512(self) -> &'a mut W { + self.variant(PSELSELECT_A::DIV512) + } + #[doc = "Divide clock by 1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PSELSELECT_A::DIV1024) + } + #[doc = "Divide clock by 2048"] + #[inline(always)] + pub fn div2048(self) -> &'a mut W { + self.variant(PSELSELECT_A::DIV2048) + } + #[doc = "Divide clock by 4096"] + #[inline(always)] + pub fn div4096(self) -> &'a mut W { + self.variant(PSELSELECT_A::DIV4096) + } + #[doc = "Divide clock by 8192"] + #[inline(always)] + pub fn div8192(self) -> &'a mut W { + self.variant(PSELSELECT_A::DIV8192) + } + #[doc = "Divide clock by 16384"] + #[inline(always)] + pub fn div16384(self) -> &'a mut W { + self.variant(PSELSELECT_A::DIV16384) + } + #[doc = "Divide clock by 32768"] + #[inline(always)] + pub fn div32768(self) -> &'a mut W { + self.variant(PSELSELECT_A::DIV32768) + } + #[doc = "Divide clock by 65536"] + #[inline(always)] + pub fn div65536(self) -> &'a mut W { + self.variant(PSELSELECT_A::DIV65536) + } +} +#[doc = "Field `LEVEL` reader - Threshold Level"] +pub type LEVEL_R = crate::FieldReader; +#[doc = "Field `LEVEL` writer - Threshold Level"] +pub type LEVEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, BOD12_SPEC, u8, u8, 6, O>; +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Hysteresis Enable"] + #[inline(always)] + pub fn hyst(&self) -> HYST_R { + HYST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 3:4 - Action when Threshold Crossed"] + #[inline(always)] + pub fn action(&self) -> ACTION_R { + ACTION_R::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bit 5 - Configuration in Standby mode"] + #[inline(always)] + pub fn stdbycfg(&self) -> STDBYCFG_R { + STDBYCFG_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 8 - Configuration in Active mode"] + #[inline(always)] + pub fn actcfg(&self) -> ACTCFG_R { + ACTCFG_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bits 12:15 - Prescaler Select"] + #[inline(always)] + pub fn psel(&self) -> PSEL_R { + PSEL_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:21 - Threshold Level"] + #[inline(always)] + pub fn level(&self) -> LEVEL_R { + LEVEL_R::new(((self.bits >> 16) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W<1> { + ENABLE_W::new(self) + } + #[doc = "Bit 2 - Hysteresis Enable"] + #[inline(always)] + #[must_use] + pub fn hyst(&mut self) -> HYST_W<2> { + HYST_W::new(self) + } + #[doc = "Bits 3:4 - Action when Threshold Crossed"] + #[inline(always)] + #[must_use] + pub fn action(&mut self) -> ACTION_W<3> { + ACTION_W::new(self) + } + #[doc = "Bit 5 - Configuration in Standby mode"] + #[inline(always)] + #[must_use] + pub fn stdbycfg(&mut self) -> STDBYCFG_W<5> { + STDBYCFG_W::new(self) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + #[must_use] + pub fn runstdby(&mut self) -> RUNSTDBY_W<6> { + RUNSTDBY_W::new(self) + } + #[doc = "Bit 8 - Configuration in Active mode"] + #[inline(always)] + #[must_use] + pub fn actcfg(&mut self) -> ACTCFG_W<8> { + ACTCFG_W::new(self) + } + #[doc = "Bits 12:15 - Prescaler Select"] + #[inline(always)] + #[must_use] + pub fn psel(&mut self) -> PSEL_W<12> { + PSEL_W::new(self) + } + #[doc = "Bits 16:21 - Threshold Level"] + #[inline(always)] + #[must_use] + pub fn level(&mut self) -> LEVEL_W<16> { + LEVEL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "BOD12 Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bod12](index.html) module"] +pub struct BOD12_SPEC; +impl crate::RegisterSpec for BOD12_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [bod12::R](R) reader structure"] +impl crate::Readable for BOD12_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [bod12::W](W) writer structure"] +impl crate::Writable for BOD12_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BOD12 to value 0"] +impl crate::Resettable for BOD12_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/supc/bod33.rs b/pac/atsaml22j/src/supc/bod33.rs new file mode 100644 index 000000000000..5985c463aac1 --- /dev/null +++ b/pac/atsaml22j/src/supc/bod33.rs @@ -0,0 +1,536 @@ +#[doc = "Register `BOD33` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `BOD33` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - Enable"] +pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, BOD33_SPEC, bool, O>; +#[doc = "Field `HYST` reader - Hysteresis Enable"] +pub type HYST_R = crate::BitReader; +#[doc = "Field `HYST` writer - Hysteresis Enable"] +pub type HYST_W<'a, const O: u8> = crate::BitWriter<'a, u32, BOD33_SPEC, bool, O>; +#[doc = "Field `ACTION` reader - Action when Threshold Crossed"] +pub type ACTION_R = crate::FieldReader; +#[doc = "Action when Threshold Crossed\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum ACTIONSELECT_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: The BOD33 generates a reset"] + RESET = 1, + #[doc = "2: The BOD33 generates an interrupt"] + INT = 2, + #[doc = "3: The BOD33 puts the device in backup sleep mode if VMON=0"] + BKUP = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: ACTIONSELECT_A) -> Self { + variant as _ + } +} +impl ACTION_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> ACTIONSELECT_A { + match self.bits { + 0 => ACTIONSELECT_A::NONE, + 1 => ACTIONSELECT_A::RESET, + 2 => ACTIONSELECT_A::INT, + 3 => ACTIONSELECT_A::BKUP, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == ACTIONSELECT_A::NONE + } + #[doc = "Checks if the value of the field is `RESET`"] + #[inline(always)] + pub fn is_reset(&self) -> bool { + *self == ACTIONSELECT_A::RESET + } + #[doc = "Checks if the value of the field is `INT`"] + #[inline(always)] + pub fn is_int(&self) -> bool { + *self == ACTIONSELECT_A::INT + } + #[doc = "Checks if the value of the field is `BKUP`"] + #[inline(always)] + pub fn is_bkup(&self) -> bool { + *self == ACTIONSELECT_A::BKUP + } +} +#[doc = "Field `ACTION` writer - Action when Threshold Crossed"] +pub type ACTION_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, BOD33_SPEC, u8, ACTIONSELECT_A, 2, O>; +impl<'a, const O: u8> ACTION_W<'a, O> { + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(ACTIONSELECT_A::NONE) + } + #[doc = "The BOD33 generates a reset"] + #[inline(always)] + pub fn reset(self) -> &'a mut W { + self.variant(ACTIONSELECT_A::RESET) + } + #[doc = "The BOD33 generates an interrupt"] + #[inline(always)] + pub fn int(self) -> &'a mut W { + self.variant(ACTIONSELECT_A::INT) + } + #[doc = "The BOD33 puts the device in backup sleep mode if VMON=0"] + #[inline(always)] + pub fn bkup(self) -> &'a mut W { + self.variant(ACTIONSELECT_A::BKUP) + } +} +#[doc = "Field `STDBYCFG` reader - Configuration in Standby mode"] +pub type STDBYCFG_R = crate::BitReader; +#[doc = "Field `STDBYCFG` writer - Configuration in Standby mode"] +pub type STDBYCFG_W<'a, const O: u8> = crate::BitWriter<'a, u32, BOD33_SPEC, bool, O>; +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub type RUNSTDBY_R = crate::BitReader; +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub type RUNSTDBY_W<'a, const O: u8> = crate::BitWriter<'a, u32, BOD33_SPEC, bool, O>; +#[doc = "Field `RUNBKUP` reader - Configuration in Backup mode"] +pub type RUNBKUP_R = crate::BitReader; +#[doc = "Field `RUNBKUP` writer - Configuration in Backup mode"] +pub type RUNBKUP_W<'a, const O: u8> = crate::BitWriter<'a, u32, BOD33_SPEC, bool, O>; +#[doc = "Field `ACTCFG` reader - Configuration in Active mode"] +pub type ACTCFG_R = crate::BitReader; +#[doc = "Field `ACTCFG` writer - Configuration in Active mode"] +pub type ACTCFG_W<'a, const O: u8> = crate::BitWriter<'a, u32, BOD33_SPEC, bool, O>; +#[doc = "Field `VMON` reader - Voltage Monitored in active and standby mode"] +pub type VMON_R = crate::BitReader; +#[doc = "Field `VMON` writer - Voltage Monitored in active and standby mode"] +pub type VMON_W<'a, const O: u8> = crate::BitWriter<'a, u32, BOD33_SPEC, bool, O>; +#[doc = "Field `PSEL` reader - Prescaler Select"] +pub type PSEL_R = crate::FieldReader; +#[doc = "Prescaler Select\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum PSELSELECT_A { + #[doc = "0: Divide clock by 2"] + DIV2 = 0, + #[doc = "1: Divide clock by 4"] + DIV4 = 1, + #[doc = "2: Divide clock by 8"] + DIV8 = 2, + #[doc = "3: Divide clock by 16"] + DIV16 = 3, + #[doc = "4: Divide clock by 32"] + DIV32 = 4, + #[doc = "5: Divide clock by 64"] + DIV64 = 5, + #[doc = "6: Divide clock by 128"] + DIV128 = 6, + #[doc = "7: Divide clock by 256"] + DIV256 = 7, + #[doc = "8: Divide clock by 512"] + DIV512 = 8, + #[doc = "9: Divide clock by 1024"] + DIV1024 = 9, + #[doc = "10: Divide clock by 2048"] + DIV2048 = 10, + #[doc = "11: Divide clock by 4096"] + DIV4096 = 11, + #[doc = "12: Divide clock by 8192"] + DIV8192 = 12, + #[doc = "13: Divide clock by 16384"] + DIV16384 = 13, + #[doc = "14: Divide clock by 32768"] + DIV32768 = 14, + #[doc = "15: Divide clock by 65536"] + DIV65536 = 15, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PSELSELECT_A) -> Self { + variant as _ + } +} +impl PSEL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PSELSELECT_A { + match self.bits { + 0 => PSELSELECT_A::DIV2, + 1 => PSELSELECT_A::DIV4, + 2 => PSELSELECT_A::DIV8, + 3 => PSELSELECT_A::DIV16, + 4 => PSELSELECT_A::DIV32, + 5 => PSELSELECT_A::DIV64, + 6 => PSELSELECT_A::DIV128, + 7 => PSELSELECT_A::DIV256, + 8 => PSELSELECT_A::DIV512, + 9 => PSELSELECT_A::DIV1024, + 10 => PSELSELECT_A::DIV2048, + 11 => PSELSELECT_A::DIV4096, + 12 => PSELSELECT_A::DIV8192, + 13 => PSELSELECT_A::DIV16384, + 14 => PSELSELECT_A::DIV32768, + 15 => PSELSELECT_A::DIV65536, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + *self == PSELSELECT_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + *self == PSELSELECT_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + *self == PSELSELECT_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + *self == PSELSELECT_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV32`"] + #[inline(always)] + pub fn is_div32(&self) -> bool { + *self == PSELSELECT_A::DIV32 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + *self == PSELSELECT_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV128`"] + #[inline(always)] + pub fn is_div128(&self) -> bool { + *self == PSELSELECT_A::DIV128 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + *self == PSELSELECT_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV512`"] + #[inline(always)] + pub fn is_div512(&self) -> bool { + *self == PSELSELECT_A::DIV512 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + *self == PSELSELECT_A::DIV1024 + } + #[doc = "Checks if the value of the field is `DIV2048`"] + #[inline(always)] + pub fn is_div2048(&self) -> bool { + *self == PSELSELECT_A::DIV2048 + } + #[doc = "Checks if the value of the field is `DIV4096`"] + #[inline(always)] + pub fn is_div4096(&self) -> bool { + *self == PSELSELECT_A::DIV4096 + } + #[doc = "Checks if the value of the field is `DIV8192`"] + #[inline(always)] + pub fn is_div8192(&self) -> bool { + *self == PSELSELECT_A::DIV8192 + } + #[doc = "Checks if the value of the field is `DIV16384`"] + #[inline(always)] + pub fn is_div16384(&self) -> bool { + *self == PSELSELECT_A::DIV16384 + } + #[doc = "Checks if the value of the field is `DIV32768`"] + #[inline(always)] + pub fn is_div32768(&self) -> bool { + *self == PSELSELECT_A::DIV32768 + } + #[doc = "Checks if the value of the field is `DIV65536`"] + #[inline(always)] + pub fn is_div65536(&self) -> bool { + *self == PSELSELECT_A::DIV65536 + } +} +#[doc = "Field `PSEL` writer - Prescaler Select"] +pub type PSEL_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, BOD33_SPEC, u8, PSELSELECT_A, 4, O>; +impl<'a, const O: u8> PSEL_W<'a, O> { + #[doc = "Divide clock by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PSELSELECT_A::DIV2) + } + #[doc = "Divide clock by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PSELSELECT_A::DIV4) + } + #[doc = "Divide clock by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PSELSELECT_A::DIV8) + } + #[doc = "Divide clock by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PSELSELECT_A::DIV16) + } + #[doc = "Divide clock by 32"] + #[inline(always)] + pub fn div32(self) -> &'a mut W { + self.variant(PSELSELECT_A::DIV32) + } + #[doc = "Divide clock by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PSELSELECT_A::DIV64) + } + #[doc = "Divide clock by 128"] + #[inline(always)] + pub fn div128(self) -> &'a mut W { + self.variant(PSELSELECT_A::DIV128) + } + #[doc = "Divide clock by 256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PSELSELECT_A::DIV256) + } + #[doc = "Divide clock by 512"] + #[inline(always)] + pub fn div512(self) -> &'a mut W { + self.variant(PSELSELECT_A::DIV512) + } + #[doc = "Divide clock by 1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PSELSELECT_A::DIV1024) + } + #[doc = "Divide clock by 2048"] + #[inline(always)] + pub fn div2048(self) -> &'a mut W { + self.variant(PSELSELECT_A::DIV2048) + } + #[doc = "Divide clock by 4096"] + #[inline(always)] + pub fn div4096(self) -> &'a mut W { + self.variant(PSELSELECT_A::DIV4096) + } + #[doc = "Divide clock by 8192"] + #[inline(always)] + pub fn div8192(self) -> &'a mut W { + self.variant(PSELSELECT_A::DIV8192) + } + #[doc = "Divide clock by 16384"] + #[inline(always)] + pub fn div16384(self) -> &'a mut W { + self.variant(PSELSELECT_A::DIV16384) + } + #[doc = "Divide clock by 32768"] + #[inline(always)] + pub fn div32768(self) -> &'a mut W { + self.variant(PSELSELECT_A::DIV32768) + } + #[doc = "Divide clock by 65536"] + #[inline(always)] + pub fn div65536(self) -> &'a mut W { + self.variant(PSELSELECT_A::DIV65536) + } +} +#[doc = "Field `LEVEL` reader - Threshold Level for VDD"] +pub type LEVEL_R = crate::FieldReader; +#[doc = "Field `LEVEL` writer - Threshold Level for VDD"] +pub type LEVEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, BOD33_SPEC, u8, u8, 6, O>; +#[doc = "Field `BKUPLEVEL` reader - Threshold Level in backup sleep mode or for VBAT"] +pub type BKUPLEVEL_R = crate::FieldReader; +#[doc = "Field `BKUPLEVEL` writer - Threshold Level in backup sleep mode or for VBAT"] +pub type BKUPLEVEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, BOD33_SPEC, u8, u8, 6, O>; +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Hysteresis Enable"] + #[inline(always)] + pub fn hyst(&self) -> HYST_R { + HYST_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 3:4 - Action when Threshold Crossed"] + #[inline(always)] + pub fn action(&self) -> ACTION_R { + ACTION_R::new(((self.bits >> 3) & 3) as u8) + } + #[doc = "Bit 5 - Configuration in Standby mode"] + #[inline(always)] + pub fn stdbycfg(&self) -> STDBYCFG_R { + STDBYCFG_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Configuration in Backup mode"] + #[inline(always)] + pub fn runbkup(&self) -> RUNBKUP_R { + RUNBKUP_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Configuration in Active mode"] + #[inline(always)] + pub fn actcfg(&self) -> ACTCFG_R { + ACTCFG_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 10 - Voltage Monitored in active and standby mode"] + #[inline(always)] + pub fn vmon(&self) -> VMON_R { + VMON_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bits 12:15 - Prescaler Select"] + #[inline(always)] + pub fn psel(&self) -> PSEL_R { + PSEL_R::new(((self.bits >> 12) & 0x0f) as u8) + } + #[doc = "Bits 16:21 - Threshold Level for VDD"] + #[inline(always)] + pub fn level(&self) -> LEVEL_R { + LEVEL_R::new(((self.bits >> 16) & 0x3f) as u8) + } + #[doc = "Bits 24:29 - Threshold Level in backup sleep mode or for VBAT"] + #[inline(always)] + pub fn bkuplevel(&self) -> BKUPLEVEL_R { + BKUPLEVEL_R::new(((self.bits >> 24) & 0x3f) as u8) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W<1> { + ENABLE_W::new(self) + } + #[doc = "Bit 2 - Hysteresis Enable"] + #[inline(always)] + #[must_use] + pub fn hyst(&mut self) -> HYST_W<2> { + HYST_W::new(self) + } + #[doc = "Bits 3:4 - Action when Threshold Crossed"] + #[inline(always)] + #[must_use] + pub fn action(&mut self) -> ACTION_W<3> { + ACTION_W::new(self) + } + #[doc = "Bit 5 - Configuration in Standby mode"] + #[inline(always)] + #[must_use] + pub fn stdbycfg(&mut self) -> STDBYCFG_W<5> { + STDBYCFG_W::new(self) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + #[must_use] + pub fn runstdby(&mut self) -> RUNSTDBY_W<6> { + RUNSTDBY_W::new(self) + } + #[doc = "Bit 7 - Configuration in Backup mode"] + #[inline(always)] + #[must_use] + pub fn runbkup(&mut self) -> RUNBKUP_W<7> { + RUNBKUP_W::new(self) + } + #[doc = "Bit 8 - Configuration in Active mode"] + #[inline(always)] + #[must_use] + pub fn actcfg(&mut self) -> ACTCFG_W<8> { + ACTCFG_W::new(self) + } + #[doc = "Bit 10 - Voltage Monitored in active and standby mode"] + #[inline(always)] + #[must_use] + pub fn vmon(&mut self) -> VMON_W<10> { + VMON_W::new(self) + } + #[doc = "Bits 12:15 - Prescaler Select"] + #[inline(always)] + #[must_use] + pub fn psel(&mut self) -> PSEL_W<12> { + PSEL_W::new(self) + } + #[doc = "Bits 16:21 - Threshold Level for VDD"] + #[inline(always)] + #[must_use] + pub fn level(&mut self) -> LEVEL_W<16> { + LEVEL_W::new(self) + } + #[doc = "Bits 24:29 - Threshold Level in backup sleep mode or for VBAT"] + #[inline(always)] + #[must_use] + pub fn bkuplevel(&mut self) -> BKUPLEVEL_W<24> { + BKUPLEVEL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "BOD33 Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [bod33](index.html) module"] +pub struct BOD33_SPEC; +impl crate::RegisterSpec for BOD33_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [bod33::R](R) reader structure"] +impl crate::Readable for BOD33_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [bod33::W](W) writer structure"] +impl crate::Writable for BOD33_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets BOD33 to value 0"] +impl crate::Resettable for BOD33_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/supc/intenclr.rs b/pac/atsaml22j/src/supc/intenclr.rs new file mode 100644 index 000000000000..f5e2c93f3fff --- /dev/null +++ b/pac/atsaml22j/src/supc/intenclr.rs @@ -0,0 +1,200 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BOD33RDY` reader - BOD33 Ready"] +pub type BOD33RDY_R = crate::BitReader; +#[doc = "Field `BOD33RDY` writer - BOD33 Ready"] +pub type BOD33RDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>; +#[doc = "Field `BOD33DET` reader - BOD33 Detection"] +pub type BOD33DET_R = crate::BitReader; +#[doc = "Field `BOD33DET` writer - BOD33 Detection"] +pub type BOD33DET_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>; +#[doc = "Field `B33SRDY` reader - BOD33 Synchronization Ready"] +pub type B33SRDY_R = crate::BitReader; +#[doc = "Field `B33SRDY` writer - BOD33 Synchronization Ready"] +pub type B33SRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>; +#[doc = "Field `BOD12RDY` reader - BOD12 Ready"] +pub type BOD12RDY_R = crate::BitReader; +#[doc = "Field `BOD12RDY` writer - BOD12 Ready"] +pub type BOD12RDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>; +#[doc = "Field `BOD12DET` reader - BOD12 Detection"] +pub type BOD12DET_R = crate::BitReader; +#[doc = "Field `BOD12DET` writer - BOD12 Detection"] +pub type BOD12DET_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>; +#[doc = "Field `B12SRDY` reader - BOD12 Synchronization Ready"] +pub type B12SRDY_R = crate::BitReader; +#[doc = "Field `B12SRDY` writer - BOD12 Synchronization Ready"] +pub type B12SRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>; +#[doc = "Field `VREGRDY` reader - Voltage Regulator Ready"] +pub type VREGRDY_R = crate::BitReader; +#[doc = "Field `VREGRDY` writer - Voltage Regulator Ready"] +pub type VREGRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>; +#[doc = "Field `APWSRDY` reader - Automatic Power Switch Ready"] +pub type APWSRDY_R = crate::BitReader; +#[doc = "Field `APWSRDY` writer - Automatic Power Switch Ready"] +pub type APWSRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>; +#[doc = "Field `VCORERDY` reader - VDDCORE Ready"] +pub type VCORERDY_R = crate::BitReader; +#[doc = "Field `VCORERDY` writer - VDDCORE Ready"] +pub type VCORERDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - BOD33 Ready"] + #[inline(always)] + pub fn bod33rdy(&self) -> BOD33RDY_R { + BOD33RDY_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - BOD33 Detection"] + #[inline(always)] + pub fn bod33det(&self) -> BOD33DET_R { + BOD33DET_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - BOD33 Synchronization Ready"] + #[inline(always)] + pub fn b33srdy(&self) -> B33SRDY_R { + B33SRDY_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - BOD12 Ready"] + #[inline(always)] + pub fn bod12rdy(&self) -> BOD12RDY_R { + BOD12RDY_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - BOD12 Detection"] + #[inline(always)] + pub fn bod12det(&self) -> BOD12DET_R { + BOD12DET_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - BOD12 Synchronization Ready"] + #[inline(always)] + pub fn b12srdy(&self) -> B12SRDY_R { + B12SRDY_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 8 - Voltage Regulator Ready"] + #[inline(always)] + pub fn vregrdy(&self) -> VREGRDY_R { + VREGRDY_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Automatic Power Switch Ready"] + #[inline(always)] + pub fn apwsrdy(&self) -> APWSRDY_R { + APWSRDY_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - VDDCORE Ready"] + #[inline(always)] + pub fn vcorerdy(&self) -> VCORERDY_R { + VCORERDY_R::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - BOD33 Ready"] + #[inline(always)] + #[must_use] + pub fn bod33rdy(&mut self) -> BOD33RDY_W<0> { + BOD33RDY_W::new(self) + } + #[doc = "Bit 1 - BOD33 Detection"] + #[inline(always)] + #[must_use] + pub fn bod33det(&mut self) -> BOD33DET_W<1> { + BOD33DET_W::new(self) + } + #[doc = "Bit 2 - BOD33 Synchronization Ready"] + #[inline(always)] + #[must_use] + pub fn b33srdy(&mut self) -> B33SRDY_W<2> { + B33SRDY_W::new(self) + } + #[doc = "Bit 3 - BOD12 Ready"] + #[inline(always)] + #[must_use] + pub fn bod12rdy(&mut self) -> BOD12RDY_W<3> { + BOD12RDY_W::new(self) + } + #[doc = "Bit 4 - BOD12 Detection"] + #[inline(always)] + #[must_use] + pub fn bod12det(&mut self) -> BOD12DET_W<4> { + BOD12DET_W::new(self) + } + #[doc = "Bit 5 - BOD12 Synchronization Ready"] + #[inline(always)] + #[must_use] + pub fn b12srdy(&mut self) -> B12SRDY_W<5> { + B12SRDY_W::new(self) + } + #[doc = "Bit 8 - Voltage Regulator Ready"] + #[inline(always)] + #[must_use] + pub fn vregrdy(&mut self) -> VREGRDY_W<8> { + VREGRDY_W::new(self) + } + #[doc = "Bit 9 - Automatic Power Switch Ready"] + #[inline(always)] + #[must_use] + pub fn apwsrdy(&mut self) -> APWSRDY_W<9> { + APWSRDY_W::new(self) + } + #[doc = "Bit 10 - VDDCORE Ready"] + #[inline(always)] + #[must_use] + pub fn vcorerdy(&mut self) -> VCORERDY_W<10> { + VCORERDY_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/supc/intenset.rs b/pac/atsaml22j/src/supc/intenset.rs new file mode 100644 index 000000000000..d8d299a8935a --- /dev/null +++ b/pac/atsaml22j/src/supc/intenset.rs @@ -0,0 +1,200 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BOD33RDY` reader - BOD33 Ready"] +pub type BOD33RDY_R = crate::BitReader; +#[doc = "Field `BOD33RDY` writer - BOD33 Ready"] +pub type BOD33RDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>; +#[doc = "Field `BOD33DET` reader - BOD33 Detection"] +pub type BOD33DET_R = crate::BitReader; +#[doc = "Field `BOD33DET` writer - BOD33 Detection"] +pub type BOD33DET_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>; +#[doc = "Field `B33SRDY` reader - BOD33 Synchronization Ready"] +pub type B33SRDY_R = crate::BitReader; +#[doc = "Field `B33SRDY` writer - BOD33 Synchronization Ready"] +pub type B33SRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>; +#[doc = "Field `BOD12RDY` reader - BOD12 Ready"] +pub type BOD12RDY_R = crate::BitReader; +#[doc = "Field `BOD12RDY` writer - BOD12 Ready"] +pub type BOD12RDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>; +#[doc = "Field `BOD12DET` reader - BOD12 Detection"] +pub type BOD12DET_R = crate::BitReader; +#[doc = "Field `BOD12DET` writer - BOD12 Detection"] +pub type BOD12DET_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>; +#[doc = "Field `B12SRDY` reader - BOD12 Synchronization Ready"] +pub type B12SRDY_R = crate::BitReader; +#[doc = "Field `B12SRDY` writer - BOD12 Synchronization Ready"] +pub type B12SRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>; +#[doc = "Field `VREGRDY` reader - Voltage Regulator Ready"] +pub type VREGRDY_R = crate::BitReader; +#[doc = "Field `VREGRDY` writer - Voltage Regulator Ready"] +pub type VREGRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>; +#[doc = "Field `APWSRDY` reader - Automatic Power Switch Ready"] +pub type APWSRDY_R = crate::BitReader; +#[doc = "Field `APWSRDY` writer - Automatic Power Switch Ready"] +pub type APWSRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>; +#[doc = "Field `VCORERDY` reader - VDDCORE Ready"] +pub type VCORERDY_R = crate::BitReader; +#[doc = "Field `VCORERDY` writer - VDDCORE Ready"] +pub type VCORERDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - BOD33 Ready"] + #[inline(always)] + pub fn bod33rdy(&self) -> BOD33RDY_R { + BOD33RDY_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - BOD33 Detection"] + #[inline(always)] + pub fn bod33det(&self) -> BOD33DET_R { + BOD33DET_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - BOD33 Synchronization Ready"] + #[inline(always)] + pub fn b33srdy(&self) -> B33SRDY_R { + B33SRDY_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - BOD12 Ready"] + #[inline(always)] + pub fn bod12rdy(&self) -> BOD12RDY_R { + BOD12RDY_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - BOD12 Detection"] + #[inline(always)] + pub fn bod12det(&self) -> BOD12DET_R { + BOD12DET_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - BOD12 Synchronization Ready"] + #[inline(always)] + pub fn b12srdy(&self) -> B12SRDY_R { + B12SRDY_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 8 - Voltage Regulator Ready"] + #[inline(always)] + pub fn vregrdy(&self) -> VREGRDY_R { + VREGRDY_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Automatic Power Switch Ready"] + #[inline(always)] + pub fn apwsrdy(&self) -> APWSRDY_R { + APWSRDY_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - VDDCORE Ready"] + #[inline(always)] + pub fn vcorerdy(&self) -> VCORERDY_R { + VCORERDY_R::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - BOD33 Ready"] + #[inline(always)] + #[must_use] + pub fn bod33rdy(&mut self) -> BOD33RDY_W<0> { + BOD33RDY_W::new(self) + } + #[doc = "Bit 1 - BOD33 Detection"] + #[inline(always)] + #[must_use] + pub fn bod33det(&mut self) -> BOD33DET_W<1> { + BOD33DET_W::new(self) + } + #[doc = "Bit 2 - BOD33 Synchronization Ready"] + #[inline(always)] + #[must_use] + pub fn b33srdy(&mut self) -> B33SRDY_W<2> { + B33SRDY_W::new(self) + } + #[doc = "Bit 3 - BOD12 Ready"] + #[inline(always)] + #[must_use] + pub fn bod12rdy(&mut self) -> BOD12RDY_W<3> { + BOD12RDY_W::new(self) + } + #[doc = "Bit 4 - BOD12 Detection"] + #[inline(always)] + #[must_use] + pub fn bod12det(&mut self) -> BOD12DET_W<4> { + BOD12DET_W::new(self) + } + #[doc = "Bit 5 - BOD12 Synchronization Ready"] + #[inline(always)] + #[must_use] + pub fn b12srdy(&mut self) -> B12SRDY_W<5> { + B12SRDY_W::new(self) + } + #[doc = "Bit 8 - Voltage Regulator Ready"] + #[inline(always)] + #[must_use] + pub fn vregrdy(&mut self) -> VREGRDY_W<8> { + VREGRDY_W::new(self) + } + #[doc = "Bit 9 - Automatic Power Switch Ready"] + #[inline(always)] + #[must_use] + pub fn apwsrdy(&mut self) -> APWSRDY_W<9> { + APWSRDY_W::new(self) + } + #[doc = "Bit 10 - VDDCORE Ready"] + #[inline(always)] + #[must_use] + pub fn vcorerdy(&mut self) -> VCORERDY_W<10> { + VCORERDY_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/supc/intflag.rs b/pac/atsaml22j/src/supc/intflag.rs new file mode 100644 index 000000000000..bb3f06ff2c9a --- /dev/null +++ b/pac/atsaml22j/src/supc/intflag.rs @@ -0,0 +1,200 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `BOD33RDY` reader - BOD33 Ready"] +pub type BOD33RDY_R = crate::BitReader; +#[doc = "Field `BOD33RDY` writer - BOD33 Ready"] +pub type BOD33RDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAG_SPEC, bool, O>; +#[doc = "Field `BOD33DET` reader - BOD33 Detection"] +pub type BOD33DET_R = crate::BitReader; +#[doc = "Field `BOD33DET` writer - BOD33 Detection"] +pub type BOD33DET_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAG_SPEC, bool, O>; +#[doc = "Field `B33SRDY` reader - BOD33 Synchronization Ready"] +pub type B33SRDY_R = crate::BitReader; +#[doc = "Field `B33SRDY` writer - BOD33 Synchronization Ready"] +pub type B33SRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAG_SPEC, bool, O>; +#[doc = "Field `BOD12RDY` reader - BOD12 Ready"] +pub type BOD12RDY_R = crate::BitReader; +#[doc = "Field `BOD12RDY` writer - BOD12 Ready"] +pub type BOD12RDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAG_SPEC, bool, O>; +#[doc = "Field `BOD12DET` reader - BOD12 Detection"] +pub type BOD12DET_R = crate::BitReader; +#[doc = "Field `BOD12DET` writer - BOD12 Detection"] +pub type BOD12DET_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAG_SPEC, bool, O>; +#[doc = "Field `B12SRDY` reader - BOD12 Synchronization Ready"] +pub type B12SRDY_R = crate::BitReader; +#[doc = "Field `B12SRDY` writer - BOD12 Synchronization Ready"] +pub type B12SRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAG_SPEC, bool, O>; +#[doc = "Field `VREGRDY` reader - Voltage Regulator Ready"] +pub type VREGRDY_R = crate::BitReader; +#[doc = "Field `VREGRDY` writer - Voltage Regulator Ready"] +pub type VREGRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAG_SPEC, bool, O>; +#[doc = "Field `APWSRDY` reader - Automatic Power Switch Ready"] +pub type APWSRDY_R = crate::BitReader; +#[doc = "Field `APWSRDY` writer - Automatic Power Switch Ready"] +pub type APWSRDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAG_SPEC, bool, O>; +#[doc = "Field `VCORERDY` reader - VDDCORE Ready"] +pub type VCORERDY_R = crate::BitReader; +#[doc = "Field `VCORERDY` writer - VDDCORE Ready"] +pub type VCORERDY_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAG_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - BOD33 Ready"] + #[inline(always)] + pub fn bod33rdy(&self) -> BOD33RDY_R { + BOD33RDY_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - BOD33 Detection"] + #[inline(always)] + pub fn bod33det(&self) -> BOD33DET_R { + BOD33DET_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - BOD33 Synchronization Ready"] + #[inline(always)] + pub fn b33srdy(&self) -> B33SRDY_R { + B33SRDY_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - BOD12 Ready"] + #[inline(always)] + pub fn bod12rdy(&self) -> BOD12RDY_R { + BOD12RDY_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - BOD12 Detection"] + #[inline(always)] + pub fn bod12det(&self) -> BOD12DET_R { + BOD12DET_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - BOD12 Synchronization Ready"] + #[inline(always)] + pub fn b12srdy(&self) -> B12SRDY_R { + B12SRDY_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 8 - Voltage Regulator Ready"] + #[inline(always)] + pub fn vregrdy(&self) -> VREGRDY_R { + VREGRDY_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Automatic Power Switch Ready"] + #[inline(always)] + pub fn apwsrdy(&self) -> APWSRDY_R { + APWSRDY_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - VDDCORE Ready"] + #[inline(always)] + pub fn vcorerdy(&self) -> VCORERDY_R { + VCORERDY_R::new(((self.bits >> 10) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - BOD33 Ready"] + #[inline(always)] + #[must_use] + pub fn bod33rdy(&mut self) -> BOD33RDY_W<0> { + BOD33RDY_W::new(self) + } + #[doc = "Bit 1 - BOD33 Detection"] + #[inline(always)] + #[must_use] + pub fn bod33det(&mut self) -> BOD33DET_W<1> { + BOD33DET_W::new(self) + } + #[doc = "Bit 2 - BOD33 Synchronization Ready"] + #[inline(always)] + #[must_use] + pub fn b33srdy(&mut self) -> B33SRDY_W<2> { + B33SRDY_W::new(self) + } + #[doc = "Bit 3 - BOD12 Ready"] + #[inline(always)] + #[must_use] + pub fn bod12rdy(&mut self) -> BOD12RDY_W<3> { + BOD12RDY_W::new(self) + } + #[doc = "Bit 4 - BOD12 Detection"] + #[inline(always)] + #[must_use] + pub fn bod12det(&mut self) -> BOD12DET_W<4> { + BOD12DET_W::new(self) + } + #[doc = "Bit 5 - BOD12 Synchronization Ready"] + #[inline(always)] + #[must_use] + pub fn b12srdy(&mut self) -> B12SRDY_W<5> { + B12SRDY_W::new(self) + } + #[doc = "Bit 8 - Voltage Regulator Ready"] + #[inline(always)] + #[must_use] + pub fn vregrdy(&mut self) -> VREGRDY_W<8> { + VREGRDY_W::new(self) + } + #[doc = "Bit 9 - Automatic Power Switch Ready"] + #[inline(always)] + #[must_use] + pub fn apwsrdy(&mut self) -> APWSRDY_W<9> { + APWSRDY_W::new(self) + } + #[doc = "Bit 10 - VDDCORE Ready"] + #[inline(always)] + #[must_use] + pub fn vcorerdy(&mut self) -> VCORERDY_W<10> { + VCORERDY_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/supc/status.rs b/pac/atsaml22j/src/supc/status.rs new file mode 100644 index 000000000000..f3e7ba68b27a --- /dev/null +++ b/pac/atsaml22j/src/supc/status.rs @@ -0,0 +1,100 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `BOD33RDY` reader - BOD33 Ready"] +pub type BOD33RDY_R = crate::BitReader; +#[doc = "Field `BOD33DET` reader - BOD33 Detection"] +pub type BOD33DET_R = crate::BitReader; +#[doc = "Field `B33SRDY` reader - BOD33 Synchronization Ready"] +pub type B33SRDY_R = crate::BitReader; +#[doc = "Field `BOD12RDY` reader - BOD12 Ready"] +pub type BOD12RDY_R = crate::BitReader; +#[doc = "Field `BOD12DET` reader - BOD12 Detection"] +pub type BOD12DET_R = crate::BitReader; +#[doc = "Field `B12SRDY` reader - BOD12 Synchronization Ready"] +pub type B12SRDY_R = crate::BitReader; +#[doc = "Field `VREGRDY` reader - Voltage Regulator Ready"] +pub type VREGRDY_R = crate::BitReader; +#[doc = "Field `APWSRDY` reader - Automatic Power Switch Ready"] +pub type APWSRDY_R = crate::BitReader; +#[doc = "Field `VCORERDY` reader - VDDCORE Ready"] +pub type VCORERDY_R = crate::BitReader; +#[doc = "Field `BBPS` reader - Battery Backup Power Switch"] +pub type BBPS_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - BOD33 Ready"] + #[inline(always)] + pub fn bod33rdy(&self) -> BOD33RDY_R { + BOD33RDY_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - BOD33 Detection"] + #[inline(always)] + pub fn bod33det(&self) -> BOD33DET_R { + BOD33DET_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - BOD33 Synchronization Ready"] + #[inline(always)] + pub fn b33srdy(&self) -> B33SRDY_R { + B33SRDY_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - BOD12 Ready"] + #[inline(always)] + pub fn bod12rdy(&self) -> BOD12RDY_R { + BOD12RDY_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - BOD12 Detection"] + #[inline(always)] + pub fn bod12det(&self) -> BOD12DET_R { + BOD12DET_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - BOD12 Synchronization Ready"] + #[inline(always)] + pub fn b12srdy(&self) -> B12SRDY_R { + B12SRDY_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 8 - Voltage Regulator Ready"] + #[inline(always)] + pub fn vregrdy(&self) -> VREGRDY_R { + VREGRDY_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Automatic Power Switch Ready"] + #[inline(always)] + pub fn apwsrdy(&self) -> APWSRDY_R { + APWSRDY_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - VDDCORE Ready"] + #[inline(always)] + pub fn vcorerdy(&self) -> VCORERDY_R { + VCORERDY_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Battery Backup Power Switch"] + #[inline(always)] + pub fn bbps(&self) -> BBPS_R { + BBPS_R::new(((self.bits >> 11) & 1) != 0) + } +} +#[doc = "Power and Clocks Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0"] +impl crate::Resettable for STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/supc/vref.rs b/pac/atsaml22j/src/supc/vref.rs new file mode 100644 index 000000000000..187aa03307f4 --- /dev/null +++ b/pac/atsaml22j/src/supc/vref.rs @@ -0,0 +1,281 @@ +#[doc = "Register `VREF` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `VREF` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TSEN` reader - Temperature Sensor Output Enable"] +pub type TSEN_R = crate::BitReader; +#[doc = "Field `TSEN` writer - Temperature Sensor Output Enable"] +pub type TSEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, VREF_SPEC, bool, O>; +#[doc = "Field `VREFOE` reader - Voltage Reference Output Enable"] +pub type VREFOE_R = crate::BitReader; +#[doc = "Field `VREFOE` writer - Voltage Reference Output Enable"] +pub type VREFOE_W<'a, const O: u8> = crate::BitWriter<'a, u32, VREF_SPEC, bool, O>; +#[doc = "Field `TSSEL` reader - Temperature Sensor Selection"] +pub type TSSEL_R = crate::BitReader; +#[doc = "Field `TSSEL` writer - Temperature Sensor Selection"] +pub type TSSEL_W<'a, const O: u8> = crate::BitWriter<'a, u32, VREF_SPEC, bool, O>; +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub type RUNSTDBY_R = crate::BitReader; +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub type RUNSTDBY_W<'a, const O: u8> = crate::BitWriter<'a, u32, VREF_SPEC, bool, O>; +#[doc = "Field `ONDEMAND` reader - On Demand Contrl"] +pub type ONDEMAND_R = crate::BitReader; +#[doc = "Field `ONDEMAND` writer - On Demand Contrl"] +pub type ONDEMAND_W<'a, const O: u8> = crate::BitWriter<'a, u32, VREF_SPEC, bool, O>; +#[doc = "Field `SEL` reader - Voltage Reference Selection"] +pub type SEL_R = crate::FieldReader; +#[doc = "Voltage Reference Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SELSELECT_A { + #[doc = "0: 1.0V voltage reference typical value"] + _1V0 = 0, + #[doc = "1: 1.1V voltage reference typical value"] + _1V1 = 1, + #[doc = "2: 1.2V voltage reference typical value"] + _1V2 = 2, + #[doc = "3: 1.25V voltage reference typical value"] + _1V25 = 3, + #[doc = "4: 2.0V voltage reference typical value"] + _2V0 = 4, + #[doc = "5: 2.2V voltage reference typical value"] + _2V2 = 5, + #[doc = "6: 2.4V voltage reference typical value"] + _2V4 = 6, + #[doc = "7: 2.5V voltage reference typical value"] + _2V5 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SELSELECT_A) -> Self { + variant as _ + } +} +impl SEL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SELSELECT_A::_1V0), + 1 => Some(SELSELECT_A::_1V1), + 2 => Some(SELSELECT_A::_1V2), + 3 => Some(SELSELECT_A::_1V25), + 4 => Some(SELSELECT_A::_2V0), + 5 => Some(SELSELECT_A::_2V2), + 6 => Some(SELSELECT_A::_2V4), + 7 => Some(SELSELECT_A::_2V5), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_1V0`"] + #[inline(always)] + pub fn is_1v0(&self) -> bool { + *self == SELSELECT_A::_1V0 + } + #[doc = "Checks if the value of the field is `_1V1`"] + #[inline(always)] + pub fn is_1v1(&self) -> bool { + *self == SELSELECT_A::_1V1 + } + #[doc = "Checks if the value of the field is `_1V2`"] + #[inline(always)] + pub fn is_1v2(&self) -> bool { + *self == SELSELECT_A::_1V2 + } + #[doc = "Checks if the value of the field is `_1V25`"] + #[inline(always)] + pub fn is_1v25(&self) -> bool { + *self == SELSELECT_A::_1V25 + } + #[doc = "Checks if the value of the field is `_2V0`"] + #[inline(always)] + pub fn is_2v0(&self) -> bool { + *self == SELSELECT_A::_2V0 + } + #[doc = "Checks if the value of the field is `_2V2`"] + #[inline(always)] + pub fn is_2v2(&self) -> bool { + *self == SELSELECT_A::_2V2 + } + #[doc = "Checks if the value of the field is `_2V4`"] + #[inline(always)] + pub fn is_2v4(&self) -> bool { + *self == SELSELECT_A::_2V4 + } + #[doc = "Checks if the value of the field is `_2V5`"] + #[inline(always)] + pub fn is_2v5(&self) -> bool { + *self == SELSELECT_A::_2V5 + } +} +#[doc = "Field `SEL` writer - Voltage Reference Selection"] +pub type SEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, VREF_SPEC, u8, SELSELECT_A, 4, O>; +impl<'a, const O: u8> SEL_W<'a, O> { + #[doc = "1.0V voltage reference typical value"] + #[inline(always)] + pub fn _1v0(self) -> &'a mut W { + self.variant(SELSELECT_A::_1V0) + } + #[doc = "1.1V voltage reference typical value"] + #[inline(always)] + pub fn _1v1(self) -> &'a mut W { + self.variant(SELSELECT_A::_1V1) + } + #[doc = "1.2V voltage reference typical value"] + #[inline(always)] + pub fn _1v2(self) -> &'a mut W { + self.variant(SELSELECT_A::_1V2) + } + #[doc = "1.25V voltage reference typical value"] + #[inline(always)] + pub fn _1v25(self) -> &'a mut W { + self.variant(SELSELECT_A::_1V25) + } + #[doc = "2.0V voltage reference typical value"] + #[inline(always)] + pub fn _2v0(self) -> &'a mut W { + self.variant(SELSELECT_A::_2V0) + } + #[doc = "2.2V voltage reference typical value"] + #[inline(always)] + pub fn _2v2(self) -> &'a mut W { + self.variant(SELSELECT_A::_2V2) + } + #[doc = "2.4V voltage reference typical value"] + #[inline(always)] + pub fn _2v4(self) -> &'a mut W { + self.variant(SELSELECT_A::_2V4) + } + #[doc = "2.5V voltage reference typical value"] + #[inline(always)] + pub fn _2v5(self) -> &'a mut W { + self.variant(SELSELECT_A::_2V5) + } +} +impl R { + #[doc = "Bit 1 - Temperature Sensor Output Enable"] + #[inline(always)] + pub fn tsen(&self) -> TSEN_R { + TSEN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Voltage Reference Output Enable"] + #[inline(always)] + pub fn vrefoe(&self) -> VREFOE_R { + VREFOE_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Temperature Sensor Selection"] + #[inline(always)] + pub fn tssel(&self) -> TSSEL_R { + TSSEL_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - On Demand Contrl"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 16:19 - Voltage Reference Selection"] + #[inline(always)] + pub fn sel(&self) -> SEL_R { + SEL_R::new(((self.bits >> 16) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 1 - Temperature Sensor Output Enable"] + #[inline(always)] + #[must_use] + pub fn tsen(&mut self) -> TSEN_W<1> { + TSEN_W::new(self) + } + #[doc = "Bit 2 - Voltage Reference Output Enable"] + #[inline(always)] + #[must_use] + pub fn vrefoe(&mut self) -> VREFOE_W<2> { + VREFOE_W::new(self) + } + #[doc = "Bit 3 - Temperature Sensor Selection"] + #[inline(always)] + #[must_use] + pub fn tssel(&mut self) -> TSSEL_W<3> { + TSSEL_W::new(self) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + #[must_use] + pub fn runstdby(&mut self) -> RUNSTDBY_W<6> { + RUNSTDBY_W::new(self) + } + #[doc = "Bit 7 - On Demand Contrl"] + #[inline(always)] + #[must_use] + pub fn ondemand(&mut self) -> ONDEMAND_W<7> { + ONDEMAND_W::new(self) + } + #[doc = "Bits 16:19 - Voltage Reference Selection"] + #[inline(always)] + #[must_use] + pub fn sel(&mut self) -> SEL_W<16> { + SEL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "VREF Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [vref](index.html) module"] +pub struct VREF_SPEC; +impl crate::RegisterSpec for VREF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [vref::R](R) reader structure"] +impl crate::Readable for VREF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [vref::W](W) writer structure"] +impl crate::Writable for VREF_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets VREF to value 0"] +impl crate::Resettable for VREF_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/supc/vreg.rs b/pac/atsaml22j/src/supc/vreg.rs new file mode 100644 index 000000000000..b34789e520e5 --- /dev/null +++ b/pac/atsaml22j/src/supc/vreg.rs @@ -0,0 +1,231 @@ +#[doc = "Register `VREG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `VREG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - Enable"] +pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, VREG_SPEC, bool, O>; +#[doc = "Field `SEL` reader - Voltage Regulator Selection in active mode"] +pub type SEL_R = crate::FieldReader; +#[doc = "Voltage Regulator Selection in active mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SELSELECT_A { + #[doc = "0: LDO selection"] + LDO = 0, + #[doc = "1: Buck selection"] + BUCK = 1, + #[doc = "2: Switched Cap selection"] + SCVREG = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SELSELECT_A) -> Self { + variant as _ + } +} +impl SEL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SELSELECT_A::LDO), + 1 => Some(SELSELECT_A::BUCK), + 2 => Some(SELSELECT_A::SCVREG), + _ => None, + } + } + #[doc = "Checks if the value of the field is `LDO`"] + #[inline(always)] + pub fn is_ldo(&self) -> bool { + *self == SELSELECT_A::LDO + } + #[doc = "Checks if the value of the field is `BUCK`"] + #[inline(always)] + pub fn is_buck(&self) -> bool { + *self == SELSELECT_A::BUCK + } + #[doc = "Checks if the value of the field is `SCVREG`"] + #[inline(always)] + pub fn is_scvreg(&self) -> bool { + *self == SELSELECT_A::SCVREG + } +} +#[doc = "Field `SEL` writer - Voltage Regulator Selection in active mode"] +pub type SEL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, VREG_SPEC, u8, SELSELECT_A, 2, O>; +impl<'a, const O: u8> SEL_W<'a, O> { + #[doc = "LDO selection"] + #[inline(always)] + pub fn ldo(self) -> &'a mut W { + self.variant(SELSELECT_A::LDO) + } + #[doc = "Buck selection"] + #[inline(always)] + pub fn buck(self) -> &'a mut W { + self.variant(SELSELECT_A::BUCK) + } + #[doc = "Switched Cap selection"] + #[inline(always)] + pub fn scvreg(self) -> &'a mut W { + self.variant(SELSELECT_A::SCVREG) + } +} +#[doc = "Field `STDBYPL0` reader - Standby in PL0"] +pub type STDBYPL0_R = crate::BitReader; +#[doc = "Field `STDBYPL0` writer - Standby in PL0"] +pub type STDBYPL0_W<'a, const O: u8> = crate::BitWriter<'a, u32, VREG_SPEC, bool, O>; +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub type RUNSTDBY_R = crate::BitReader; +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub type RUNSTDBY_W<'a, const O: u8> = crate::BitWriter<'a, u32, VREG_SPEC, bool, O>; +#[doc = "Field `LPEFF` reader - Low Power efficiency"] +pub type LPEFF_R = crate::BitReader; +#[doc = "Field `LPEFF` writer - Low Power efficiency"] +pub type LPEFF_W<'a, const O: u8> = crate::BitWriter<'a, u32, VREG_SPEC, bool, O>; +#[doc = "Field `VSVSTEP` reader - Voltage Scaling Voltage Step"] +pub type VSVSTEP_R = crate::FieldReader; +#[doc = "Field `VSVSTEP` writer - Voltage Scaling Voltage Step"] +pub type VSVSTEP_W<'a, const O: u8> = crate::FieldWriter<'a, u32, VREG_SPEC, u8, u8, 4, O>; +#[doc = "Field `VSPER` reader - Voltage Scaling Period"] +pub type VSPER_R = crate::FieldReader; +#[doc = "Field `VSPER` writer - Voltage Scaling Period"] +pub type VSPER_W<'a, const O: u8> = crate::FieldWriter<'a, u32, VREG_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:3 - Voltage Regulator Selection in active mode"] + #[inline(always)] + pub fn sel(&self) -> SEL_R { + SEL_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bit 5 - Standby in PL0"] + #[inline(always)] + pub fn stdbypl0(&self) -> STDBYPL0_R { + STDBYPL0_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 8 - Low Power efficiency"] + #[inline(always)] + pub fn lpeff(&self) -> LPEFF_R { + LPEFF_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bits 16:19 - Voltage Scaling Voltage Step"] + #[inline(always)] + pub fn vsvstep(&self) -> VSVSTEP_R { + VSVSTEP_R::new(((self.bits >> 16) & 0x0f) as u8) + } + #[doc = "Bits 24:31 - Voltage Scaling Period"] + #[inline(always)] + pub fn vsper(&self) -> VSPER_R { + VSPER_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W<1> { + ENABLE_W::new(self) + } + #[doc = "Bits 2:3 - Voltage Regulator Selection in active mode"] + #[inline(always)] + #[must_use] + pub fn sel(&mut self) -> SEL_W<2> { + SEL_W::new(self) + } + #[doc = "Bit 5 - Standby in PL0"] + #[inline(always)] + #[must_use] + pub fn stdbypl0(&mut self) -> STDBYPL0_W<5> { + STDBYPL0_W::new(self) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + #[must_use] + pub fn runstdby(&mut self) -> RUNSTDBY_W<6> { + RUNSTDBY_W::new(self) + } + #[doc = "Bit 8 - Low Power efficiency"] + #[inline(always)] + #[must_use] + pub fn lpeff(&mut self) -> LPEFF_W<8> { + LPEFF_W::new(self) + } + #[doc = "Bits 16:19 - Voltage Scaling Voltage Step"] + #[inline(always)] + #[must_use] + pub fn vsvstep(&mut self) -> VSVSTEP_W<16> { + VSVSTEP_W::new(self) + } + #[doc = "Bits 24:31 - Voltage Scaling Period"] + #[inline(always)] + #[must_use] + pub fn vsper(&mut self) -> VSPER_W<24> { + VSPER_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "VREG Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [vreg](index.html) module"] +pub struct VREG_SPEC; +impl crate::RegisterSpec for VREG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [vreg::R](R) reader structure"] +impl crate::Readable for VREG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [vreg::W](W) writer structure"] +impl crate::Writable for VREG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets VREG to value 0"] +impl crate::Resettable for VREG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tc0.rs b/pac/atsaml22j/src/tc0.rs new file mode 100644 index 000000000000..48f4eed16e42 --- /dev/null +++ b/pac/atsaml22j/src/tc0.rs @@ -0,0 +1,37 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + _reserved_0_count8: [u8; 0x38], +} +impl RegisterBlock { + #[doc = "0x00..0x38 - 32-bit Counter Mode"] + #[inline(always)] + pub const fn count32(&self) -> &COUNT32 { + unsafe { &*(self as *const Self).cast::().add(0usize).cast() } + } + #[doc = "0x00..0x34 - 16-bit Counter Mode"] + #[inline(always)] + pub const fn count16(&self) -> &COUNT16 { + unsafe { &*(self as *const Self).cast::().add(0usize).cast() } + } + #[doc = "0x00..0x32 - 8-bit Counter Mode"] + #[inline(always)] + pub const fn count8(&self) -> &COUNT8 { + unsafe { &*(self as *const Self).cast::().add(0usize).cast() } + } +} +#[doc = "8-bit Counter Mode"] +pub use self::count8::COUNT8; +#[doc = r"Cluster"] +#[doc = "8-bit Counter Mode"] +pub mod count8; +#[doc = "16-bit Counter Mode"] +pub use self::count16::COUNT16; +#[doc = r"Cluster"] +#[doc = "16-bit Counter Mode"] +pub mod count16; +#[doc = "32-bit Counter Mode"] +pub use self::count32::COUNT32; +#[doc = r"Cluster"] +#[doc = "32-bit Counter Mode"] +pub mod count32; diff --git a/pac/atsaml22j/src/tc0/count16.rs b/pac/atsaml22j/src/tc0/count16.rs new file mode 100644 index 000000000000..c8014290fbdf --- /dev/null +++ b/pac/atsaml22j/src/tc0/count16.rs @@ -0,0 +1,97 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct COUNT16 { + #[doc = "0x00 - Control A"] + pub ctrla: CTRLA, + #[doc = "0x04 - Control B Clear"] + pub ctrlbclr: CTRLBCLR, + #[doc = "0x05 - Control B Set"] + pub ctrlbset: CTRLBSET, + #[doc = "0x06 - Event Control"] + pub evctrl: EVCTRL, + #[doc = "0x08 - Interrupt Enable Clear"] + pub intenclr: INTENCLR, + #[doc = "0x09 - Interrupt Enable Set"] + pub intenset: INTENSET, + #[doc = "0x0a - Interrupt Flag Status and Clear"] + pub intflag: INTFLAG, + #[doc = "0x0b - Status"] + pub status: STATUS, + #[doc = "0x0c - Waveform Generation Control"] + pub wave: WAVE, + #[doc = "0x0d - Control C"] + pub drvctrl: DRVCTRL, + _reserved10: [u8; 0x01], + #[doc = "0x0f - Debug Control"] + pub dbgctrl: DBGCTRL, + #[doc = "0x10 - Synchronization Status"] + pub syncbusy: SYNCBUSY, + #[doc = "0x14 - COUNT16 Count"] + pub count: COUNT, + _reserved13: [u8; 0x06], + #[doc = "0x1c - COUNT16 Compare and Capture"] + pub cc: [CC; 2], + _reserved14: [u8; 0x10], + #[doc = "0x30 - COUNT16 Compare and Capture Buffer"] + pub ccbuf: [CCBUF; 2], +} +#[doc = "CTRLA (rw) register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLBCLR (rw) register accessor: an alias for `Reg`"] +pub type CTRLBCLR = crate::Reg; +#[doc = "Control B Clear"] +pub mod ctrlbclr; +#[doc = "CTRLBSET (rw) register accessor: an alias for `Reg`"] +pub type CTRLBSET = crate::Reg; +#[doc = "Control B Set"] +pub mod ctrlbset; +#[doc = "EVCTRL (rw) register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR (rw) register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET (rw) register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG (rw) register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS (rw) register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "WAVE (rw) register accessor: an alias for `Reg`"] +pub type WAVE = crate::Reg; +#[doc = "Waveform Generation Control"] +pub mod wave; +#[doc = "DRVCTRL (rw) register accessor: an alias for `Reg`"] +pub type DRVCTRL = crate::Reg; +#[doc = "Control C"] +pub mod drvctrl; +#[doc = "DBGCTRL (rw) register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY (r) register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Status"] +pub mod syncbusy; +#[doc = "COUNT (rw) register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "COUNT16 Count"] +pub mod count; +#[doc = "CC (rw) register accessor: an alias for `Reg`"] +pub type CC = crate::Reg; +#[doc = "COUNT16 Compare and Capture"] +pub mod cc; +#[doc = "CCBUF (rw) register accessor: an alias for `Reg`"] +pub type CCBUF = crate::Reg; +#[doc = "COUNT16 Compare and Capture Buffer"] +pub mod ccbuf; diff --git a/pac/atsaml22j/src/tc0/count16/cc.rs b/pac/atsaml22j/src/tc0/count16/cc.rs new file mode 100644 index 000000000000..44216cfe6216 --- /dev/null +++ b/pac/atsaml22j/src/tc0/count16/cc.rs @@ -0,0 +1,80 @@ +#[doc = "Register `CC%s` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC%s` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CC` reader - Counter/Compare Value"] +pub type CC_R = crate::FieldReader; +#[doc = "Field `CC` writer - Counter/Compare Value"] +pub type CC_W<'a, const O: u8> = crate::FieldWriter<'a, u16, CC_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - Counter/Compare Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - Counter/Compare Value"] + #[inline(always)] + #[must_use] + pub fn cc(&mut self) -> CC_W<0> { + CC_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT16 Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc](index.html) module"] +pub struct CC_SPEC; +impl crate::RegisterSpec for CC_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [cc::R](R) reader structure"] +impl crate::Readable for CC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc::W](W) writer structure"] +impl crate::Writable for CC_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CC%s to value 0"] +impl crate::Resettable for CC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tc0/count16/ccbuf.rs b/pac/atsaml22j/src/tc0/count16/ccbuf.rs new file mode 100644 index 000000000000..d68571c7af56 --- /dev/null +++ b/pac/atsaml22j/src/tc0/count16/ccbuf.rs @@ -0,0 +1,80 @@ +#[doc = "Register `CCBUF%s` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF%s` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CCBUF` reader - Counter/Compare Buffer Value"] +pub type CCBUF_R = crate::FieldReader; +#[doc = "Field `CCBUF` writer - Counter/Compare Buffer Value"] +pub type CCBUF_W<'a, const O: u8> = crate::FieldWriter<'a, u16, CCBUF_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - Counter/Compare Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - Counter/Compare Buffer Value"] + #[inline(always)] + #[must_use] + pub fn ccbuf(&mut self) -> CCBUF_W<0> { + CCBUF_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT16 Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf](index.html) module"] +pub struct CCBUF_SPEC; +impl crate::RegisterSpec for CCBUF_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ccbuf::R](R) reader structure"] +impl crate::Readable for CCBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf::W](W) writer structure"] +impl crate::Writable for CCBUF_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CCBUF%s to value 0"] +impl crate::Resettable for CCBUF_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tc0/count16/count.rs b/pac/atsaml22j/src/tc0/count16/count.rs new file mode 100644 index 000000000000..5a65db1b0694 --- /dev/null +++ b/pac/atsaml22j/src/tc0/count16/count.rs @@ -0,0 +1,80 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub type COUNT_R = crate::FieldReader; +#[doc = "Field `COUNT` writer - Counter Value"] +pub type COUNT_W<'a, const O: u8> = crate::FieldWriter<'a, u16, COUNT_SPEC, u16, u16, 16, O>; +impl R { + #[doc = "Bits 0:15 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:15 - Counter Value"] + #[inline(always)] + #[must_use] + pub fn count(&mut self) -> COUNT_W<0> { + COUNT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT16 Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tc0/count16/ctrla.rs b/pac/atsaml22j/src/tc0/count16/ctrla.rs new file mode 100644 index 000000000000..e8bee55276ae --- /dev/null +++ b/pac/atsaml22j/src/tc0/count16/ctrla.rs @@ -0,0 +1,488 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub type SWRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `ENABLE` reader - Enable"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - Enable"] +pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `MODE` reader - Timer Counter Mode"] +pub type MODE_R = crate::FieldReader; +#[doc = "Timer Counter Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum MODESELECT_A { + #[doc = "0: Counter in 16-bit mode"] + COUNT16 = 0, + #[doc = "1: Counter in 8-bit mode"] + COUNT8 = 1, + #[doc = "2: Counter in 32-bit mode"] + COUNT32 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODESELECT_A) -> Self { + variant as _ + } +} +impl MODE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODESELECT_A::COUNT16), + 1 => Some(MODESELECT_A::COUNT8), + 2 => Some(MODESELECT_A::COUNT32), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + *self == MODESELECT_A::COUNT16 + } + #[doc = "Checks if the value of the field is `COUNT8`"] + #[inline(always)] + pub fn is_count8(&self) -> bool { + *self == MODESELECT_A::COUNT8 + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + *self == MODESELECT_A::COUNT32 + } +} +#[doc = "Field `MODE` writer - Timer Counter Mode"] +pub type MODE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRLA_SPEC, u8, MODESELECT_A, 2, O>; +impl<'a, const O: u8> MODE_W<'a, O> { + #[doc = "Counter in 16-bit mode"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODESELECT_A::COUNT16) + } + #[doc = "Counter in 8-bit mode"] + #[inline(always)] + pub fn count8(self) -> &'a mut W { + self.variant(MODESELECT_A::COUNT8) + } + #[doc = "Counter in 32-bit mode"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODESELECT_A::COUNT32) + } +} +#[doc = "Field `PRESCSYNC` reader - Prescaler and Counter Synchronization"] +pub type PRESCSYNC_R = crate::FieldReader; +#[doc = "Prescaler and Counter Synchronization\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum PRESCSYNCSELECT_A { + #[doc = "0: Reload or reset the counter on next generic clock"] + GCLK = 0, + #[doc = "1: Reload or reset the counter on next prescaler clock"] + PRESC = 1, + #[doc = "2: Reload or reset the counter on next generic clock and reset the prescaler counter"] + RESYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCSYNCSELECT_A) -> Self { + variant as _ + } +} +impl PRESCSYNC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCSYNCSELECT_A::GCLK), + 1 => Some(PRESCSYNCSELECT_A::PRESC), + 2 => Some(PRESCSYNCSELECT_A::RESYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + *self == PRESCSYNCSELECT_A::GCLK + } + #[doc = "Checks if the value of the field is `PRESC`"] + #[inline(always)] + pub fn is_presc(&self) -> bool { + *self == PRESCSYNCSELECT_A::PRESC + } + #[doc = "Checks if the value of the field is `RESYNC`"] + #[inline(always)] + pub fn is_resync(&self) -> bool { + *self == PRESCSYNCSELECT_A::RESYNC + } +} +#[doc = "Field `PRESCSYNC` writer - Prescaler and Counter Synchronization"] +pub type PRESCSYNC_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, CTRLA_SPEC, u8, PRESCSYNCSELECT_A, 2, O>; +impl<'a, const O: u8> PRESCSYNC_W<'a, O> { + #[doc = "Reload or reset the counter on next generic clock"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(PRESCSYNCSELECT_A::GCLK) + } + #[doc = "Reload or reset the counter on next prescaler clock"] + #[inline(always)] + pub fn presc(self) -> &'a mut W { + self.variant(PRESCSYNCSELECT_A::PRESC) + } + #[doc = "Reload or reset the counter on next generic clock and reset the prescaler counter"] + #[inline(always)] + pub fn resync(self) -> &'a mut W { + self.variant(PRESCSYNCSELECT_A::RESYNC) + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub type RUNSTDBY_R = crate::BitReader; +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub type RUNSTDBY_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `ONDEMAND` reader - Clock On Demand"] +pub type ONDEMAND_R = crate::BitReader; +#[doc = "Field `ONDEMAND` writer - Clock On Demand"] +pub type ONDEMAND_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub type PRESCALER_R = crate::FieldReader; +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum PRESCALERSELECT_A { + #[doc = "0: Prescaler: GCLK_TC"] + DIV1 = 0, + #[doc = "1: Prescaler: GCLK_TC/2"] + DIV2 = 1, + #[doc = "2: Prescaler: GCLK_TC/4"] + DIV4 = 2, + #[doc = "3: Prescaler: GCLK_TC/8"] + DIV8 = 3, + #[doc = "4: Prescaler: GCLK_TC/16"] + DIV16 = 4, + #[doc = "5: Prescaler: GCLK_TC/64"] + DIV64 = 5, + #[doc = "6: Prescaler: GCLK_TC/256"] + DIV256 = 6, + #[doc = "7: Prescaler: GCLK_TC/1024"] + DIV1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALERSELECT_A) -> Self { + variant as _ + } +} +impl PRESCALER_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALERSELECT_A { + match self.bits { + 0 => PRESCALERSELECT_A::DIV1, + 1 => PRESCALERSELECT_A::DIV2, + 2 => PRESCALERSELECT_A::DIV4, + 3 => PRESCALERSELECT_A::DIV8, + 4 => PRESCALERSELECT_A::DIV16, + 5 => PRESCALERSELECT_A::DIV64, + 6 => PRESCALERSELECT_A::DIV256, + 7 => PRESCALERSELECT_A::DIV1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + *self == PRESCALERSELECT_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + *self == PRESCALERSELECT_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + *self == PRESCALERSELECT_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + *self == PRESCALERSELECT_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + *self == PRESCALERSELECT_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + *self == PRESCALERSELECT_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + *self == PRESCALERSELECT_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + *self == PRESCALERSELECT_A::DIV1024 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub type PRESCALER_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, CTRLA_SPEC, u8, PRESCALERSELECT_A, 3, O>; +impl<'a, const O: u8> PRESCALER_W<'a, O> { + #[doc = "Prescaler: GCLK_TC"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV1) + } + #[doc = "Prescaler: GCLK_TC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV2) + } + #[doc = "Prescaler: GCLK_TC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV4) + } + #[doc = "Prescaler: GCLK_TC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV8) + } + #[doc = "Prescaler: GCLK_TC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV16) + } + #[doc = "Prescaler: GCLK_TC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV64) + } + #[doc = "Prescaler: GCLK_TC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV256) + } + #[doc = "Prescaler: GCLK_TC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV1024) + } +} +#[doc = "Field `ALOCK` reader - Auto Lock"] +pub type ALOCK_R = crate::BitReader; +#[doc = "Field `ALOCK` writer - Auto Lock"] +pub type ALOCK_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `CAPTEN0` reader - Capture Channel 0 Enable"] +pub type CAPTEN0_R = crate::BitReader; +#[doc = "Field `CAPTEN0` writer - Capture Channel 0 Enable"] +pub type CAPTEN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `CAPTEN1` reader - Capture Channel 1 Enable"] +pub type CAPTEN1_R = crate::BitReader; +#[doc = "Field `CAPTEN1` writer - Capture Channel 1 Enable"] +pub type CAPTEN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `COPEN0` reader - Capture On Pin 0 Enable"] +pub type COPEN0_R = crate::BitReader; +#[doc = "Field `COPEN0` writer - Capture On Pin 0 Enable"] +pub type COPEN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `COPEN1` reader - Capture On Pin 1 Enable"] +pub type COPEN1_R = crate::BitReader; +#[doc = "Field `COPEN1` writer - Capture On Pin 1 Enable"] +pub type COPEN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:3 - Timer Counter Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&self) -> PRESCSYNC_R { + PRESCSYNC_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Clock On Demand"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 11 - Auto Lock"] + #[inline(always)] + pub fn alock(&self) -> ALOCK_R { + ALOCK_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 16 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn capten0(&self) -> CAPTEN0_R { + CAPTEN0_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn capten1(&self) -> CAPTEN1_R { + CAPTEN1_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 20 - Capture On Pin 0 Enable"] + #[inline(always)] + pub fn copen0(&self) -> COPEN0_R { + COPEN0_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Capture On Pin 1 Enable"] + #[inline(always)] + pub fn copen1(&self) -> COPEN1_R { + COPEN1_R::new(((self.bits >> 21) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + #[must_use] + pub fn swrst(&mut self) -> SWRST_W<0> { + SWRST_W::new(self) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W<1> { + ENABLE_W::new(self) + } + #[doc = "Bits 2:3 - Timer Counter Mode"] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> MODE_W<2> { + MODE_W::new(self) + } + #[doc = "Bits 4:5 - Prescaler and Counter Synchronization"] + #[inline(always)] + #[must_use] + pub fn prescsync(&mut self) -> PRESCSYNC_W<4> { + PRESCSYNC_W::new(self) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + #[must_use] + pub fn runstdby(&mut self) -> RUNSTDBY_W<6> { + RUNSTDBY_W::new(self) + } + #[doc = "Bit 7 - Clock On Demand"] + #[inline(always)] + #[must_use] + pub fn ondemand(&mut self) -> ONDEMAND_W<7> { + ONDEMAND_W::new(self) + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + #[must_use] + pub fn prescaler(&mut self) -> PRESCALER_W<8> { + PRESCALER_W::new(self) + } + #[doc = "Bit 11 - Auto Lock"] + #[inline(always)] + #[must_use] + pub fn alock(&mut self) -> ALOCK_W<11> { + ALOCK_W::new(self) + } + #[doc = "Bit 16 - Capture Channel 0 Enable"] + #[inline(always)] + #[must_use] + pub fn capten0(&mut self) -> CAPTEN0_W<16> { + CAPTEN0_W::new(self) + } + #[doc = "Bit 17 - Capture Channel 1 Enable"] + #[inline(always)] + #[must_use] + pub fn capten1(&mut self) -> CAPTEN1_W<17> { + CAPTEN1_W::new(self) + } + #[doc = "Bit 20 - Capture On Pin 0 Enable"] + #[inline(always)] + #[must_use] + pub fn copen0(&mut self) -> COPEN0_W<20> { + COPEN0_W::new(self) + } + #[doc = "Bit 21 - Capture On Pin 1 Enable"] + #[inline(always)] + #[must_use] + pub fn copen1(&mut self) -> COPEN1_W<21> { + COPEN1_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tc0/count16/ctrlbclr.rs b/pac/atsaml22j/src/tc0/count16/ctrlbclr.rs new file mode 100644 index 000000000000..aea0a17cba36 --- /dev/null +++ b/pac/atsaml22j/src/tc0/count16/ctrlbclr.rs @@ -0,0 +1,225 @@ +#[doc = "Register `CTRLBCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub type DIR_R = crate::BitReader; +#[doc = "Field `DIR` writer - Counter Direction"] +pub type DIR_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLBCLR_SPEC, bool, O>; +#[doc = "Field `LUPD` reader - Lock Update"] +pub type LUPD_R = crate::BitReader; +#[doc = "Field `LUPD` writer - Lock Update"] +pub type LUPD_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLBCLR_SPEC, bool, O>; +#[doc = "Field `ONESHOT` reader - One-Shot on Counter"] +pub type ONESHOT_R = crate::BitReader; +#[doc = "Field `ONESHOT` writer - One-Shot on Counter"] +pub type ONESHOT_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLBCLR_SPEC, bool, O>; +#[doc = "Field `CMD` reader - Command"] +pub type CMD_R = crate::FieldReader; +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum CMDSELECT_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, + #[doc = "3: Force update of double-buffered register"] + UPDATE = 3, + #[doc = "4: Force a read synchronization of COUNT"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMDSELECT_A) -> Self { + variant as _ + } +} +impl CMD_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMDSELECT_A::NONE), + 1 => Some(CMDSELECT_A::RETRIGGER), + 2 => Some(CMDSELECT_A::STOP), + 3 => Some(CMDSELECT_A::UPDATE), + 4 => Some(CMDSELECT_A::READSYNC), + 5 => Some(CMDSELECT_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == CMDSELECT_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + *self == CMDSELECT_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + *self == CMDSELECT_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + *self == CMDSELECT_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + *self == CMDSELECT_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + *self == CMDSELECT_A::DMAOS + } +} +#[doc = "Field `CMD` writer - Command"] +pub type CMD_W<'a, const O: u8> = crate::FieldWriter<'a, u8, CTRLBCLR_SPEC, u8, CMDSELECT_A, 3, O>; +impl<'a, const O: u8> CMD_W<'a, O> { + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMDSELECT_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMDSELECT_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMDSELECT_A::STOP) + } + #[doc = "Force update of double-buffered register"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMDSELECT_A::UPDATE) + } + #[doc = "Force a read synchronization of COUNT"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMDSELECT_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMDSELECT_A::DMAOS) + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new((self.bits >> 5) & 7) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + #[must_use] + pub fn dir(&mut self) -> DIR_W<0> { + DIR_W::new(self) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + #[must_use] + pub fn lupd(&mut self) -> LUPD_W<1> { + LUPD_W::new(self) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + #[must_use] + pub fn oneshot(&mut self) -> ONESHOT_W<2> { + ONESHOT_W::new(self) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + #[must_use] + pub fn cmd(&mut self) -> CMD_W<5> { + CMD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbclr](index.html) module"] +pub struct CTRLBCLR_SPEC; +impl crate::RegisterSpec for CTRLBCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbclr::R](R) reader structure"] +impl crate::Readable for CTRLBCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbclr::W](W) writer structure"] +impl crate::Writable for CTRLBCLR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRLBCLR to value 0"] +impl crate::Resettable for CTRLBCLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tc0/count16/ctrlbset.rs b/pac/atsaml22j/src/tc0/count16/ctrlbset.rs new file mode 100644 index 000000000000..759f260623a2 --- /dev/null +++ b/pac/atsaml22j/src/tc0/count16/ctrlbset.rs @@ -0,0 +1,225 @@ +#[doc = "Register `CTRLBSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub type DIR_R = crate::BitReader; +#[doc = "Field `DIR` writer - Counter Direction"] +pub type DIR_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLBSET_SPEC, bool, O>; +#[doc = "Field `LUPD` reader - Lock Update"] +pub type LUPD_R = crate::BitReader; +#[doc = "Field `LUPD` writer - Lock Update"] +pub type LUPD_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLBSET_SPEC, bool, O>; +#[doc = "Field `ONESHOT` reader - One-Shot on Counter"] +pub type ONESHOT_R = crate::BitReader; +#[doc = "Field `ONESHOT` writer - One-Shot on Counter"] +pub type ONESHOT_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLBSET_SPEC, bool, O>; +#[doc = "Field `CMD` reader - Command"] +pub type CMD_R = crate::FieldReader; +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum CMDSELECT_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, + #[doc = "3: Force update of double-buffered register"] + UPDATE = 3, + #[doc = "4: Force a read synchronization of COUNT"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMDSELECT_A) -> Self { + variant as _ + } +} +impl CMD_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMDSELECT_A::NONE), + 1 => Some(CMDSELECT_A::RETRIGGER), + 2 => Some(CMDSELECT_A::STOP), + 3 => Some(CMDSELECT_A::UPDATE), + 4 => Some(CMDSELECT_A::READSYNC), + 5 => Some(CMDSELECT_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == CMDSELECT_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + *self == CMDSELECT_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + *self == CMDSELECT_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + *self == CMDSELECT_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + *self == CMDSELECT_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + *self == CMDSELECT_A::DMAOS + } +} +#[doc = "Field `CMD` writer - Command"] +pub type CMD_W<'a, const O: u8> = crate::FieldWriter<'a, u8, CTRLBSET_SPEC, u8, CMDSELECT_A, 3, O>; +impl<'a, const O: u8> CMD_W<'a, O> { + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMDSELECT_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMDSELECT_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMDSELECT_A::STOP) + } + #[doc = "Force update of double-buffered register"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMDSELECT_A::UPDATE) + } + #[doc = "Force a read synchronization of COUNT"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMDSELECT_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMDSELECT_A::DMAOS) + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new((self.bits >> 5) & 7) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + #[must_use] + pub fn dir(&mut self) -> DIR_W<0> { + DIR_W::new(self) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + #[must_use] + pub fn lupd(&mut self) -> LUPD_W<1> { + LUPD_W::new(self) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + #[must_use] + pub fn oneshot(&mut self) -> ONESHOT_W<2> { + ONESHOT_W::new(self) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + #[must_use] + pub fn cmd(&mut self) -> CMD_W<5> { + CMD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbset](index.html) module"] +pub struct CTRLBSET_SPEC; +impl crate::RegisterSpec for CTRLBSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbset::R](R) reader structure"] +impl crate::Readable for CTRLBSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbset::W](W) writer structure"] +impl crate::Writable for CTRLBSET_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRLBSET to value 0"] +impl crate::Resettable for CTRLBSET_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tc0/count16/dbgctrl.rs b/pac/atsaml22j/src/tc0/count16/dbgctrl.rs new file mode 100644 index 000000000000..271f8aa633ac --- /dev/null +++ b/pac/atsaml22j/src/tc0/count16/dbgctrl.rs @@ -0,0 +1,80 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub type DBGRUN_R = crate::BitReader; +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub type DBGRUN_W<'a, const O: u8> = crate::BitWriter<'a, u8, DBGCTRL_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + #[must_use] + pub fn dbgrun(&mut self) -> DBGRUN_W<0> { + DBGRUN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tc0/count16/drvctrl.rs b/pac/atsaml22j/src/tc0/count16/drvctrl.rs new file mode 100644 index 000000000000..b6e499c1e0fe --- /dev/null +++ b/pac/atsaml22j/src/tc0/count16/drvctrl.rs @@ -0,0 +1,95 @@ +#[doc = "Register `DRVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DRVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INVEN0` reader - Output Waveform Invert Enable 0"] +pub type INVEN0_R = crate::BitReader; +#[doc = "Field `INVEN0` writer - Output Waveform Invert Enable 0"] +pub type INVEN0_W<'a, const O: u8> = crate::BitWriter<'a, u8, DRVCTRL_SPEC, bool, O>; +#[doc = "Field `INVEN1` reader - Output Waveform Invert Enable 1"] +pub type INVEN1_R = crate::BitReader; +#[doc = "Field `INVEN1` writer - Output Waveform Invert Enable 1"] +pub type INVEN1_W<'a, const O: u8> = crate::BitWriter<'a, u8, DRVCTRL_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Output Waveform Invert Enable 0"] + #[inline(always)] + pub fn inven0(&self) -> INVEN0_R { + INVEN0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Output Waveform Invert Enable 1"] + #[inline(always)] + pub fn inven1(&self) -> INVEN1_R { + INVEN1_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Output Waveform Invert Enable 0"] + #[inline(always)] + #[must_use] + pub fn inven0(&mut self) -> INVEN0_W<0> { + INVEN0_W::new(self) + } + #[doc = "Bit 1 - Output Waveform Invert Enable 1"] + #[inline(always)] + #[must_use] + pub fn inven1(&mut self) -> INVEN1_W<1> { + INVEN1_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [drvctrl](index.html) module"] +pub struct DRVCTRL_SPEC; +impl crate::RegisterSpec for DRVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [drvctrl::R](R) reader structure"] +impl crate::Readable for DRVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [drvctrl::W](W) writer structure"] +impl crate::Writable for DRVCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DRVCTRL to value 0"] +impl crate::Resettable for DRVCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tc0/count16/evctrl.rs b/pac/atsaml22j/src/tc0/count16/evctrl.rs new file mode 100644 index 000000000000..9238d1566f09 --- /dev/null +++ b/pac/atsaml22j/src/tc0/count16/evctrl.rs @@ -0,0 +1,282 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVACT` reader - Event Action"] +pub type EVACT_R = crate::FieldReader; +#[doc = "Event Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum EVACTSELECT_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Start, restart or retrigger TC on event"] + RETRIGGER = 1, + #[doc = "2: Count on event"] + COUNT = 2, + #[doc = "3: Start TC on event"] + START = 3, + #[doc = "4: Time stamp capture"] + STAMP = 4, + #[doc = "5: Period catured in CC0, pulse width in CC1"] + PPW = 5, + #[doc = "6: Period catured in CC1, pulse width in CC0"] + PWP = 6, + #[doc = "7: Pulse width capture"] + PW = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACTSELECT_A) -> Self { + variant as _ + } +} +impl EVACT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVACTSELECT_A { + match self.bits { + 0 => EVACTSELECT_A::OFF, + 1 => EVACTSELECT_A::RETRIGGER, + 2 => EVACTSELECT_A::COUNT, + 3 => EVACTSELECT_A::START, + 4 => EVACTSELECT_A::STAMP, + 5 => EVACTSELECT_A::PPW, + 6 => EVACTSELECT_A::PWP, + 7 => EVACTSELECT_A::PW, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == EVACTSELECT_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + *self == EVACTSELECT_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `COUNT`"] + #[inline(always)] + pub fn is_count(&self) -> bool { + *self == EVACTSELECT_A::COUNT + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + *self == EVACTSELECT_A::START + } + #[doc = "Checks if the value of the field is `STAMP`"] + #[inline(always)] + pub fn is_stamp(&self) -> bool { + *self == EVACTSELECT_A::STAMP + } + #[doc = "Checks if the value of the field is `PPW`"] + #[inline(always)] + pub fn is_ppw(&self) -> bool { + *self == EVACTSELECT_A::PPW + } + #[doc = "Checks if the value of the field is `PWP`"] + #[inline(always)] + pub fn is_pwp(&self) -> bool { + *self == EVACTSELECT_A::PWP + } + #[doc = "Checks if the value of the field is `PW`"] + #[inline(always)] + pub fn is_pw(&self) -> bool { + *self == EVACTSELECT_A::PW + } +} +#[doc = "Field `EVACT` writer - Event Action"] +pub type EVACT_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u16, EVCTRL_SPEC, u8, EVACTSELECT_A, 3, O>; +impl<'a, const O: u8> EVACT_W<'a, O> { + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACTSELECT_A::OFF) + } + #[doc = "Start, restart or retrigger TC on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACTSELECT_A::RETRIGGER) + } + #[doc = "Count on event"] + #[inline(always)] + pub fn count(self) -> &'a mut W { + self.variant(EVACTSELECT_A::COUNT) + } + #[doc = "Start TC on event"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(EVACTSELECT_A::START) + } + #[doc = "Time stamp capture"] + #[inline(always)] + pub fn stamp(self) -> &'a mut W { + self.variant(EVACTSELECT_A::STAMP) + } + #[doc = "Period catured in CC0, pulse width in CC1"] + #[inline(always)] + pub fn ppw(self) -> &'a mut W { + self.variant(EVACTSELECT_A::PPW) + } + #[doc = "Period catured in CC1, pulse width in CC0"] + #[inline(always)] + pub fn pwp(self) -> &'a mut W { + self.variant(EVACTSELECT_A::PWP) + } + #[doc = "Pulse width capture"] + #[inline(always)] + pub fn pw(self) -> &'a mut W { + self.variant(EVACTSELECT_A::PW) + } +} +#[doc = "Field `TCINV` reader - TC Event Input Polarity"] +pub type TCINV_R = crate::BitReader; +#[doc = "Field `TCINV` writer - TC Event Input Polarity"] +pub type TCINV_W<'a, const O: u8> = crate::BitWriter<'a, u16, EVCTRL_SPEC, bool, O>; +#[doc = "Field `TCEI` reader - TC Event Enable"] +pub type TCEI_R = crate::BitReader; +#[doc = "Field `TCEI` writer - TC Event Enable"] +pub type TCEI_W<'a, const O: u8> = crate::BitWriter<'a, u16, EVCTRL_SPEC, bool, O>; +#[doc = "Field `OVFEO` reader - Event Output Enable"] +pub type OVFEO_R = crate::BitReader; +#[doc = "Field `OVFEO` writer - Event Output Enable"] +pub type OVFEO_W<'a, const O: u8> = crate::BitWriter<'a, u16, EVCTRL_SPEC, bool, O>; +#[doc = "Field `MCEO0` reader - MC Event Output Enable 0"] +pub type MCEO0_R = crate::BitReader; +#[doc = "Field `MCEO0` writer - MC Event Output Enable 0"] +pub type MCEO0_W<'a, const O: u8> = crate::BitWriter<'a, u16, EVCTRL_SPEC, bool, O>; +#[doc = "Field `MCEO1` reader - MC Event Output Enable 1"] +pub type MCEO1_R = crate::BitReader; +#[doc = "Field `MCEO1` writer - MC Event Output Enable 1"] +pub type MCEO1_W<'a, const O: u8> = crate::BitWriter<'a, u16, EVCTRL_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&self) -> EVACT_R { + EVACT_R::new((self.bits & 7) as u8) + } + #[doc = "Bit 4 - TC Event Input Polarity"] + #[inline(always)] + pub fn tcinv(&self) -> TCINV_R { + TCINV_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - TC Event Enable"] + #[inline(always)] + pub fn tcei(&self) -> TCEI_R { + TCEI_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 8 - Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 12 - MC Event Output Enable 0"] + #[inline(always)] + pub fn mceo0(&self) -> MCEO0_R { + MCEO0_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - MC Event Output Enable 1"] + #[inline(always)] + pub fn mceo1(&self) -> MCEO1_R { + MCEO1_R::new(((self.bits >> 13) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + #[must_use] + pub fn evact(&mut self) -> EVACT_W<0> { + EVACT_W::new(self) + } + #[doc = "Bit 4 - TC Event Input Polarity"] + #[inline(always)] + #[must_use] + pub fn tcinv(&mut self) -> TCINV_W<4> { + TCINV_W::new(self) + } + #[doc = "Bit 5 - TC Event Enable"] + #[inline(always)] + #[must_use] + pub fn tcei(&mut self) -> TCEI_W<5> { + TCEI_W::new(self) + } + #[doc = "Bit 8 - Event Output Enable"] + #[inline(always)] + #[must_use] + pub fn ovfeo(&mut self) -> OVFEO_W<8> { + OVFEO_W::new(self) + } + #[doc = "Bit 12 - MC Event Output Enable 0"] + #[inline(always)] + #[must_use] + pub fn mceo0(&mut self) -> MCEO0_W<12> { + MCEO0_W::new(self) + } + #[doc = "Bit 13 - MC Event Output Enable 1"] + #[inline(always)] + #[must_use] + pub fn mceo1(&mut self) -> MCEO1_W<13> { + MCEO1_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tc0/count16/intenclr.rs b/pac/atsaml22j/src/tc0/count16/intenclr.rs new file mode 100644 index 000000000000..940e1f9474a1 --- /dev/null +++ b/pac/atsaml22j/src/tc0/count16/intenclr.rs @@ -0,0 +1,125 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Disable"] +pub type OVF_R = crate::BitReader; +#[doc = "Field `OVF` writer - OVF Interrupt Disable"] +pub type OVF_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>; +#[doc = "Field `ERR` reader - ERR Interrupt Disable"] +pub type ERR_R = crate::BitReader; +#[doc = "Field `ERR` writer - ERR Interrupt Disable"] +pub type ERR_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>; +#[doc = "Field `MC0` reader - MC Interrupt Disable 0"] +pub type MC0_R = crate::BitReader; +#[doc = "Field `MC0` writer - MC Interrupt Disable 0"] +pub type MC0_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>; +#[doc = "Field `MC1` reader - MC Interrupt Disable 1"] +pub type MC1_R = crate::BitReader; +#[doc = "Field `MC1` writer - MC Interrupt Disable 1"] +pub type MC1_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - OVF Interrupt Disable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Disable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 4 - MC Interrupt Disable 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - MC Interrupt Disable 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Disable"] + #[inline(always)] + #[must_use] + pub fn ovf(&mut self) -> OVF_W<0> { + OVF_W::new(self) + } + #[doc = "Bit 1 - ERR Interrupt Disable"] + #[inline(always)] + #[must_use] + pub fn err(&mut self) -> ERR_W<1> { + ERR_W::new(self) + } + #[doc = "Bit 4 - MC Interrupt Disable 0"] + #[inline(always)] + #[must_use] + pub fn mc0(&mut self) -> MC0_W<4> { + MC0_W::new(self) + } + #[doc = "Bit 5 - MC Interrupt Disable 1"] + #[inline(always)] + #[must_use] + pub fn mc1(&mut self) -> MC1_W<5> { + MC1_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tc0/count16/intenset.rs b/pac/atsaml22j/src/tc0/count16/intenset.rs new file mode 100644 index 000000000000..308be3696676 --- /dev/null +++ b/pac/atsaml22j/src/tc0/count16/intenset.rs @@ -0,0 +1,125 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Enable"] +pub type OVF_R = crate::BitReader; +#[doc = "Field `OVF` writer - OVF Interrupt Enable"] +pub type OVF_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENSET_SPEC, bool, O>; +#[doc = "Field `ERR` reader - ERR Interrupt Enable"] +pub type ERR_R = crate::BitReader; +#[doc = "Field `ERR` writer - ERR Interrupt Enable"] +pub type ERR_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENSET_SPEC, bool, O>; +#[doc = "Field `MC0` reader - MC Interrupt Enable 0"] +pub type MC0_R = crate::BitReader; +#[doc = "Field `MC0` writer - MC Interrupt Enable 0"] +pub type MC0_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENSET_SPEC, bool, O>; +#[doc = "Field `MC1` reader - MC Interrupt Enable 1"] +pub type MC1_R = crate::BitReader; +#[doc = "Field `MC1` writer - MC Interrupt Enable 1"] +pub type MC1_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENSET_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - OVF Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 4 - MC Interrupt Enable 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - MC Interrupt Enable 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn ovf(&mut self) -> OVF_W<0> { + OVF_W::new(self) + } + #[doc = "Bit 1 - ERR Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn err(&mut self) -> ERR_W<1> { + ERR_W::new(self) + } + #[doc = "Bit 4 - MC Interrupt Enable 0"] + #[inline(always)] + #[must_use] + pub fn mc0(&mut self) -> MC0_W<4> { + MC0_W::new(self) + } + #[doc = "Bit 5 - MC Interrupt Enable 1"] + #[inline(always)] + #[must_use] + pub fn mc1(&mut self) -> MC1_W<5> { + MC1_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tc0/count16/intflag.rs b/pac/atsaml22j/src/tc0/count16/intflag.rs new file mode 100644 index 000000000000..e168641a7cfd --- /dev/null +++ b/pac/atsaml22j/src/tc0/count16/intflag.rs @@ -0,0 +1,125 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Flag"] +pub type OVF_R = crate::BitReader; +#[doc = "Field `OVF` writer - OVF Interrupt Flag"] +pub type OVF_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTFLAG_SPEC, bool, O>; +#[doc = "Field `ERR` reader - ERR Interrupt Flag"] +pub type ERR_R = crate::BitReader; +#[doc = "Field `ERR` writer - ERR Interrupt Flag"] +pub type ERR_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTFLAG_SPEC, bool, O>; +#[doc = "Field `MC0` reader - MC Interrupt Flag 0"] +pub type MC0_R = crate::BitReader; +#[doc = "Field `MC0` writer - MC Interrupt Flag 0"] +pub type MC0_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTFLAG_SPEC, bool, O>; +#[doc = "Field `MC1` reader - MC Interrupt Flag 1"] +pub type MC1_R = crate::BitReader; +#[doc = "Field `MC1` writer - MC Interrupt Flag 1"] +pub type MC1_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTFLAG_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - OVF Interrupt Flag"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Flag"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 4 - MC Interrupt Flag 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - MC Interrupt Flag 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Flag"] + #[inline(always)] + #[must_use] + pub fn ovf(&mut self) -> OVF_W<0> { + OVF_W::new(self) + } + #[doc = "Bit 1 - ERR Interrupt Flag"] + #[inline(always)] + #[must_use] + pub fn err(&mut self) -> ERR_W<1> { + ERR_W::new(self) + } + #[doc = "Bit 4 - MC Interrupt Flag 0"] + #[inline(always)] + #[must_use] + pub fn mc0(&mut self) -> MC0_W<4> { + MC0_W::new(self) + } + #[doc = "Bit 5 - MC Interrupt Flag 1"] + #[inline(always)] + #[must_use] + pub fn mc1(&mut self) -> MC1_W<5> { + MC1_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tc0/count16/status.rs b/pac/atsaml22j/src/tc0/count16/status.rs new file mode 100644 index 000000000000..d970ceba0574 --- /dev/null +++ b/pac/atsaml22j/src/tc0/count16/status.rs @@ -0,0 +1,124 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STOP` reader - Stop Status Flag"] +pub type STOP_R = crate::BitReader; +#[doc = "Field `SLAVE` reader - Slave Status Flag"] +pub type SLAVE_R = crate::BitReader; +#[doc = "Field `PERBUFV` reader - Synchronization Busy Status"] +pub type PERBUFV_R = crate::BitReader; +#[doc = "Field `PERBUFV` writer - Synchronization Busy Status"] +pub type PERBUFV_W<'a, const O: u8> = crate::BitWriter<'a, u8, STATUS_SPEC, bool, O>; +#[doc = "Field `CCBUFV0` reader - Compare channel buffer 0 valid"] +pub type CCBUFV0_R = crate::BitReader; +#[doc = "Field `CCBUFV0` writer - Compare channel buffer 0 valid"] +pub type CCBUFV0_W<'a, const O: u8> = crate::BitWriter<'a, u8, STATUS_SPEC, bool, O>; +#[doc = "Field `CCBUFV1` reader - Compare channel buffer 1 valid"] +pub type CCBUFV1_R = crate::BitReader; +#[doc = "Field `CCBUFV1` writer - Compare channel buffer 1 valid"] +pub type CCBUFV1_W<'a, const O: u8> = crate::BitWriter<'a, u8, STATUS_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Stop Status Flag"] + #[inline(always)] + pub fn stop(&self) -> STOP_R { + STOP_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Slave Status Flag"] + #[inline(always)] + pub fn slave(&self) -> SLAVE_R { + SLAVE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Synchronization Busy Status"] + #[inline(always)] + pub fn perbufv(&self) -> PERBUFV_R { + PERBUFV_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Compare channel buffer 0 valid"] + #[inline(always)] + pub fn ccbufv0(&self) -> CCBUFV0_R { + CCBUFV0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Compare channel buffer 1 valid"] + #[inline(always)] + pub fn ccbufv1(&self) -> CCBUFV1_R { + CCBUFV1_R::new(((self.bits >> 5) & 1) != 0) + } +} +impl W { + #[doc = "Bit 3 - Synchronization Busy Status"] + #[inline(always)] + #[must_use] + pub fn perbufv(&mut self) -> PERBUFV_W<3> { + PERBUFV_W::new(self) + } + #[doc = "Bit 4 - Compare channel buffer 0 valid"] + #[inline(always)] + #[must_use] + pub fn ccbufv0(&mut self) -> CCBUFV0_W<4> { + CCBUFV0_W::new(self) + } + #[doc = "Bit 5 - Compare channel buffer 1 valid"] + #[inline(always)] + #[must_use] + pub fn ccbufv1(&mut self) -> CCBUFV1_W<5> { + CCBUFV1_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets STATUS to value 0x01"] +impl crate::Resettable for STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/pac/atsaml22j/src/tc0/count16/syncbusy.rs b/pac/atsaml22j/src/tc0/count16/syncbusy.rs new file mode 100644 index 000000000000..901c6571d922 --- /dev/null +++ b/pac/atsaml22j/src/tc0/count16/syncbusy.rs @@ -0,0 +1,86 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - swrst"] +pub type SWRST_R = crate::BitReader; +#[doc = "Field `ENABLE` reader - enable"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `CTRLB` reader - CTRLB"] +pub type CTRLB_R = crate::BitReader; +#[doc = "Field `STATUS` reader - STATUS"] +pub type STATUS_R = crate::BitReader; +#[doc = "Field `COUNT` reader - Counter"] +pub type COUNT_R = crate::BitReader; +#[doc = "Field `PER` reader - Period"] +pub type PER_R = crate::BitReader; +#[doc = "Field `CC0` reader - Compare Channel 0"] +pub type CC0_R = crate::BitReader; +#[doc = "Field `CC1` reader - Compare Channel 1"] +pub type CC1_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - swrst"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - CTRLB"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - STATUS"] + #[inline(always)] + pub fn status(&self) -> STATUS_R { + STATUS_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Counter"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Period"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Compare Channel 0"] + #[inline(always)] + pub fn cc0(&self) -> CC0_R { + CC0_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Compare Channel 1"] + #[inline(always)] + pub fn cc1(&self) -> CC1_R { + CC1_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[doc = "Synchronization Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tc0/count16/wave.rs b/pac/atsaml22j/src/tc0/count16/wave.rs new file mode 100644 index 000000000000..c6776ad1adeb --- /dev/null +++ b/pac/atsaml22j/src/tc0/count16/wave.rs @@ -0,0 +1,155 @@ +#[doc = "Register `WAVE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WAVE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WAVEGEN` reader - Waveform Generation Mode"] +pub type WAVEGEN_R = crate::FieldReader; +#[doc = "Waveform Generation Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum WAVEGENSELECT_A { + #[doc = "0: Normal frequency"] + NFRQ = 0, + #[doc = "1: Match frequency"] + MFRQ = 1, + #[doc = "2: Normal PWM"] + NPWM = 2, + #[doc = "3: Match PWM"] + MPWM = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WAVEGENSELECT_A) -> Self { + variant as _ + } +} +impl WAVEGEN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WAVEGENSELECT_A { + match self.bits { + 0 => WAVEGENSELECT_A::NFRQ, + 1 => WAVEGENSELECT_A::MFRQ, + 2 => WAVEGENSELECT_A::NPWM, + 3 => WAVEGENSELECT_A::MPWM, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NFRQ`"] + #[inline(always)] + pub fn is_nfrq(&self) -> bool { + *self == WAVEGENSELECT_A::NFRQ + } + #[doc = "Checks if the value of the field is `MFRQ`"] + #[inline(always)] + pub fn is_mfrq(&self) -> bool { + *self == WAVEGENSELECT_A::MFRQ + } + #[doc = "Checks if the value of the field is `NPWM`"] + #[inline(always)] + pub fn is_npwm(&self) -> bool { + *self == WAVEGENSELECT_A::NPWM + } + #[doc = "Checks if the value of the field is `MPWM`"] + #[inline(always)] + pub fn is_mpwm(&self) -> bool { + *self == WAVEGENSELECT_A::MPWM + } +} +#[doc = "Field `WAVEGEN` writer - Waveform Generation Mode"] +pub type WAVEGEN_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u8, WAVE_SPEC, u8, WAVEGENSELECT_A, 2, O>; +impl<'a, const O: u8> WAVEGEN_W<'a, O> { + #[doc = "Normal frequency"] + #[inline(always)] + pub fn nfrq(self) -> &'a mut W { + self.variant(WAVEGENSELECT_A::NFRQ) + } + #[doc = "Match frequency"] + #[inline(always)] + pub fn mfrq(self) -> &'a mut W { + self.variant(WAVEGENSELECT_A::MFRQ) + } + #[doc = "Normal PWM"] + #[inline(always)] + pub fn npwm(self) -> &'a mut W { + self.variant(WAVEGENSELECT_A::NPWM) + } + #[doc = "Match PWM"] + #[inline(always)] + pub fn mpwm(self) -> &'a mut W { + self.variant(WAVEGENSELECT_A::MPWM) + } +} +impl R { + #[doc = "Bits 0:1 - Waveform Generation Mode"] + #[inline(always)] + pub fn wavegen(&self) -> WAVEGEN_R { + WAVEGEN_R::new(self.bits & 3) + } +} +impl W { + #[doc = "Bits 0:1 - Waveform Generation Mode"] + #[inline(always)] + #[must_use] + pub fn wavegen(&mut self) -> WAVEGEN_W<0> { + WAVEGEN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Waveform Generation Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wave](index.html) module"] +pub struct WAVE_SPEC; +impl crate::RegisterSpec for WAVE_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [wave::R](R) reader structure"] +impl crate::Readable for WAVE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wave::W](W) writer structure"] +impl crate::Writable for WAVE_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets WAVE to value 0"] +impl crate::Resettable for WAVE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tc0/count32.rs b/pac/atsaml22j/src/tc0/count32.rs new file mode 100644 index 000000000000..63f3be71bad5 --- /dev/null +++ b/pac/atsaml22j/src/tc0/count32.rs @@ -0,0 +1,97 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct COUNT32 { + #[doc = "0x00 - Control A"] + pub ctrla: CTRLA, + #[doc = "0x04 - Control B Clear"] + pub ctrlbclr: CTRLBCLR, + #[doc = "0x05 - Control B Set"] + pub ctrlbset: CTRLBSET, + #[doc = "0x06 - Event Control"] + pub evctrl: EVCTRL, + #[doc = "0x08 - Interrupt Enable Clear"] + pub intenclr: INTENCLR, + #[doc = "0x09 - Interrupt Enable Set"] + pub intenset: INTENSET, + #[doc = "0x0a - Interrupt Flag Status and Clear"] + pub intflag: INTFLAG, + #[doc = "0x0b - Status"] + pub status: STATUS, + #[doc = "0x0c - Waveform Generation Control"] + pub wave: WAVE, + #[doc = "0x0d - Control C"] + pub drvctrl: DRVCTRL, + _reserved10: [u8; 0x01], + #[doc = "0x0f - Debug Control"] + pub dbgctrl: DBGCTRL, + #[doc = "0x10 - Synchronization Status"] + pub syncbusy: SYNCBUSY, + #[doc = "0x14 - COUNT32 Count"] + pub count: COUNT, + _reserved13: [u8; 0x04], + #[doc = "0x1c..0x24 - COUNT32 Compare and Capture"] + pub cc: [CC; 2], + _reserved14: [u8; 0x0c], + #[doc = "0x30..0x38 - COUNT32 Compare and Capture Buffer"] + pub ccbuf: [CCBUF; 2], +} +#[doc = "CTRLA (rw) register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLBCLR (rw) register accessor: an alias for `Reg`"] +pub type CTRLBCLR = crate::Reg; +#[doc = "Control B Clear"] +pub mod ctrlbclr; +#[doc = "CTRLBSET (rw) register accessor: an alias for `Reg`"] +pub type CTRLBSET = crate::Reg; +#[doc = "Control B Set"] +pub mod ctrlbset; +#[doc = "EVCTRL (rw) register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR (rw) register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET (rw) register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG (rw) register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS (rw) register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "WAVE (rw) register accessor: an alias for `Reg`"] +pub type WAVE = crate::Reg; +#[doc = "Waveform Generation Control"] +pub mod wave; +#[doc = "DRVCTRL (rw) register accessor: an alias for `Reg`"] +pub type DRVCTRL = crate::Reg; +#[doc = "Control C"] +pub mod drvctrl; +#[doc = "DBGCTRL (rw) register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY (r) register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Status"] +pub mod syncbusy; +#[doc = "COUNT (rw) register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "COUNT32 Count"] +pub mod count; +#[doc = "CC (rw) register accessor: an alias for `Reg`"] +pub type CC = crate::Reg; +#[doc = "COUNT32 Compare and Capture"] +pub mod cc; +#[doc = "CCBUF (rw) register accessor: an alias for `Reg`"] +pub type CCBUF = crate::Reg; +#[doc = "COUNT32 Compare and Capture Buffer"] +pub mod ccbuf; diff --git a/pac/atsaml22j/src/tc0/count32/cc.rs b/pac/atsaml22j/src/tc0/count32/cc.rs new file mode 100644 index 000000000000..d089d63974dd --- /dev/null +++ b/pac/atsaml22j/src/tc0/count32/cc.rs @@ -0,0 +1,80 @@ +#[doc = "Register `CC%s` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC%s` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CC` reader - Counter/Compare Value"] +pub type CC_R = crate::FieldReader; +#[doc = "Field `CC` writer - Counter/Compare Value"] +pub type CC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CC_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - Counter/Compare Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Counter/Compare Value"] + #[inline(always)] + #[must_use] + pub fn cc(&mut self) -> CC_W<0> { + CC_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT32 Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc](index.html) module"] +pub struct CC_SPEC; +impl crate::RegisterSpec for CC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc::R](R) reader structure"] +impl crate::Readable for CC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc::W](W) writer structure"] +impl crate::Writable for CC_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CC%s to value 0"] +impl crate::Resettable for CC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tc0/count32/ccbuf.rs b/pac/atsaml22j/src/tc0/count32/ccbuf.rs new file mode 100644 index 000000000000..b1f7dd17d15a --- /dev/null +++ b/pac/atsaml22j/src/tc0/count32/ccbuf.rs @@ -0,0 +1,80 @@ +#[doc = "Register `CCBUF%s` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF%s` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CCBUF` reader - Counter/Compare Buffer Value"] +pub type CCBUF_R = crate::FieldReader; +#[doc = "Field `CCBUF` writer - Counter/Compare Buffer Value"] +pub type CCBUF_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CCBUF_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - Counter/Compare Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Counter/Compare Buffer Value"] + #[inline(always)] + #[must_use] + pub fn ccbuf(&mut self) -> CCBUF_W<0> { + CCBUF_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT32 Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf](index.html) module"] +pub struct CCBUF_SPEC; +impl crate::RegisterSpec for CCBUF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccbuf::R](R) reader structure"] +impl crate::Readable for CCBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf::W](W) writer structure"] +impl crate::Writable for CCBUF_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CCBUF%s to value 0"] +impl crate::Resettable for CCBUF_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tc0/count32/count.rs b/pac/atsaml22j/src/tc0/count32/count.rs new file mode 100644 index 000000000000..1d133bb0a3fc --- /dev/null +++ b/pac/atsaml22j/src/tc0/count32/count.rs @@ -0,0 +1,80 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub type COUNT_R = crate::FieldReader; +#[doc = "Field `COUNT` writer - Counter Value"] +pub type COUNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, COUNT_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Counter Value"] + #[inline(always)] + #[must_use] + pub fn count(&mut self) -> COUNT_W<0> { + COUNT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT32 Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tc0/count32/ctrla.rs b/pac/atsaml22j/src/tc0/count32/ctrla.rs new file mode 100644 index 000000000000..e8bee55276ae --- /dev/null +++ b/pac/atsaml22j/src/tc0/count32/ctrla.rs @@ -0,0 +1,488 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub type SWRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `ENABLE` reader - Enable"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - Enable"] +pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `MODE` reader - Timer Counter Mode"] +pub type MODE_R = crate::FieldReader; +#[doc = "Timer Counter Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum MODESELECT_A { + #[doc = "0: Counter in 16-bit mode"] + COUNT16 = 0, + #[doc = "1: Counter in 8-bit mode"] + COUNT8 = 1, + #[doc = "2: Counter in 32-bit mode"] + COUNT32 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODESELECT_A) -> Self { + variant as _ + } +} +impl MODE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODESELECT_A::COUNT16), + 1 => Some(MODESELECT_A::COUNT8), + 2 => Some(MODESELECT_A::COUNT32), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + *self == MODESELECT_A::COUNT16 + } + #[doc = "Checks if the value of the field is `COUNT8`"] + #[inline(always)] + pub fn is_count8(&self) -> bool { + *self == MODESELECT_A::COUNT8 + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + *self == MODESELECT_A::COUNT32 + } +} +#[doc = "Field `MODE` writer - Timer Counter Mode"] +pub type MODE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRLA_SPEC, u8, MODESELECT_A, 2, O>; +impl<'a, const O: u8> MODE_W<'a, O> { + #[doc = "Counter in 16-bit mode"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODESELECT_A::COUNT16) + } + #[doc = "Counter in 8-bit mode"] + #[inline(always)] + pub fn count8(self) -> &'a mut W { + self.variant(MODESELECT_A::COUNT8) + } + #[doc = "Counter in 32-bit mode"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODESELECT_A::COUNT32) + } +} +#[doc = "Field `PRESCSYNC` reader - Prescaler and Counter Synchronization"] +pub type PRESCSYNC_R = crate::FieldReader; +#[doc = "Prescaler and Counter Synchronization\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum PRESCSYNCSELECT_A { + #[doc = "0: Reload or reset the counter on next generic clock"] + GCLK = 0, + #[doc = "1: Reload or reset the counter on next prescaler clock"] + PRESC = 1, + #[doc = "2: Reload or reset the counter on next generic clock and reset the prescaler counter"] + RESYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCSYNCSELECT_A) -> Self { + variant as _ + } +} +impl PRESCSYNC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCSYNCSELECT_A::GCLK), + 1 => Some(PRESCSYNCSELECT_A::PRESC), + 2 => Some(PRESCSYNCSELECT_A::RESYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + *self == PRESCSYNCSELECT_A::GCLK + } + #[doc = "Checks if the value of the field is `PRESC`"] + #[inline(always)] + pub fn is_presc(&self) -> bool { + *self == PRESCSYNCSELECT_A::PRESC + } + #[doc = "Checks if the value of the field is `RESYNC`"] + #[inline(always)] + pub fn is_resync(&self) -> bool { + *self == PRESCSYNCSELECT_A::RESYNC + } +} +#[doc = "Field `PRESCSYNC` writer - Prescaler and Counter Synchronization"] +pub type PRESCSYNC_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, CTRLA_SPEC, u8, PRESCSYNCSELECT_A, 2, O>; +impl<'a, const O: u8> PRESCSYNC_W<'a, O> { + #[doc = "Reload or reset the counter on next generic clock"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(PRESCSYNCSELECT_A::GCLK) + } + #[doc = "Reload or reset the counter on next prescaler clock"] + #[inline(always)] + pub fn presc(self) -> &'a mut W { + self.variant(PRESCSYNCSELECT_A::PRESC) + } + #[doc = "Reload or reset the counter on next generic clock and reset the prescaler counter"] + #[inline(always)] + pub fn resync(self) -> &'a mut W { + self.variant(PRESCSYNCSELECT_A::RESYNC) + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub type RUNSTDBY_R = crate::BitReader; +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub type RUNSTDBY_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `ONDEMAND` reader - Clock On Demand"] +pub type ONDEMAND_R = crate::BitReader; +#[doc = "Field `ONDEMAND` writer - Clock On Demand"] +pub type ONDEMAND_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub type PRESCALER_R = crate::FieldReader; +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum PRESCALERSELECT_A { + #[doc = "0: Prescaler: GCLK_TC"] + DIV1 = 0, + #[doc = "1: Prescaler: GCLK_TC/2"] + DIV2 = 1, + #[doc = "2: Prescaler: GCLK_TC/4"] + DIV4 = 2, + #[doc = "3: Prescaler: GCLK_TC/8"] + DIV8 = 3, + #[doc = "4: Prescaler: GCLK_TC/16"] + DIV16 = 4, + #[doc = "5: Prescaler: GCLK_TC/64"] + DIV64 = 5, + #[doc = "6: Prescaler: GCLK_TC/256"] + DIV256 = 6, + #[doc = "7: Prescaler: GCLK_TC/1024"] + DIV1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALERSELECT_A) -> Self { + variant as _ + } +} +impl PRESCALER_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALERSELECT_A { + match self.bits { + 0 => PRESCALERSELECT_A::DIV1, + 1 => PRESCALERSELECT_A::DIV2, + 2 => PRESCALERSELECT_A::DIV4, + 3 => PRESCALERSELECT_A::DIV8, + 4 => PRESCALERSELECT_A::DIV16, + 5 => PRESCALERSELECT_A::DIV64, + 6 => PRESCALERSELECT_A::DIV256, + 7 => PRESCALERSELECT_A::DIV1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + *self == PRESCALERSELECT_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + *self == PRESCALERSELECT_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + *self == PRESCALERSELECT_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + *self == PRESCALERSELECT_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + *self == PRESCALERSELECT_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + *self == PRESCALERSELECT_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + *self == PRESCALERSELECT_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + *self == PRESCALERSELECT_A::DIV1024 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub type PRESCALER_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, CTRLA_SPEC, u8, PRESCALERSELECT_A, 3, O>; +impl<'a, const O: u8> PRESCALER_W<'a, O> { + #[doc = "Prescaler: GCLK_TC"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV1) + } + #[doc = "Prescaler: GCLK_TC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV2) + } + #[doc = "Prescaler: GCLK_TC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV4) + } + #[doc = "Prescaler: GCLK_TC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV8) + } + #[doc = "Prescaler: GCLK_TC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV16) + } + #[doc = "Prescaler: GCLK_TC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV64) + } + #[doc = "Prescaler: GCLK_TC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV256) + } + #[doc = "Prescaler: GCLK_TC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV1024) + } +} +#[doc = "Field `ALOCK` reader - Auto Lock"] +pub type ALOCK_R = crate::BitReader; +#[doc = "Field `ALOCK` writer - Auto Lock"] +pub type ALOCK_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `CAPTEN0` reader - Capture Channel 0 Enable"] +pub type CAPTEN0_R = crate::BitReader; +#[doc = "Field `CAPTEN0` writer - Capture Channel 0 Enable"] +pub type CAPTEN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `CAPTEN1` reader - Capture Channel 1 Enable"] +pub type CAPTEN1_R = crate::BitReader; +#[doc = "Field `CAPTEN1` writer - Capture Channel 1 Enable"] +pub type CAPTEN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `COPEN0` reader - Capture On Pin 0 Enable"] +pub type COPEN0_R = crate::BitReader; +#[doc = "Field `COPEN0` writer - Capture On Pin 0 Enable"] +pub type COPEN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `COPEN1` reader - Capture On Pin 1 Enable"] +pub type COPEN1_R = crate::BitReader; +#[doc = "Field `COPEN1` writer - Capture On Pin 1 Enable"] +pub type COPEN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:3 - Timer Counter Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&self) -> PRESCSYNC_R { + PRESCSYNC_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Clock On Demand"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 11 - Auto Lock"] + #[inline(always)] + pub fn alock(&self) -> ALOCK_R { + ALOCK_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 16 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn capten0(&self) -> CAPTEN0_R { + CAPTEN0_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn capten1(&self) -> CAPTEN1_R { + CAPTEN1_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 20 - Capture On Pin 0 Enable"] + #[inline(always)] + pub fn copen0(&self) -> COPEN0_R { + COPEN0_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Capture On Pin 1 Enable"] + #[inline(always)] + pub fn copen1(&self) -> COPEN1_R { + COPEN1_R::new(((self.bits >> 21) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + #[must_use] + pub fn swrst(&mut self) -> SWRST_W<0> { + SWRST_W::new(self) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W<1> { + ENABLE_W::new(self) + } + #[doc = "Bits 2:3 - Timer Counter Mode"] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> MODE_W<2> { + MODE_W::new(self) + } + #[doc = "Bits 4:5 - Prescaler and Counter Synchronization"] + #[inline(always)] + #[must_use] + pub fn prescsync(&mut self) -> PRESCSYNC_W<4> { + PRESCSYNC_W::new(self) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + #[must_use] + pub fn runstdby(&mut self) -> RUNSTDBY_W<6> { + RUNSTDBY_W::new(self) + } + #[doc = "Bit 7 - Clock On Demand"] + #[inline(always)] + #[must_use] + pub fn ondemand(&mut self) -> ONDEMAND_W<7> { + ONDEMAND_W::new(self) + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + #[must_use] + pub fn prescaler(&mut self) -> PRESCALER_W<8> { + PRESCALER_W::new(self) + } + #[doc = "Bit 11 - Auto Lock"] + #[inline(always)] + #[must_use] + pub fn alock(&mut self) -> ALOCK_W<11> { + ALOCK_W::new(self) + } + #[doc = "Bit 16 - Capture Channel 0 Enable"] + #[inline(always)] + #[must_use] + pub fn capten0(&mut self) -> CAPTEN0_W<16> { + CAPTEN0_W::new(self) + } + #[doc = "Bit 17 - Capture Channel 1 Enable"] + #[inline(always)] + #[must_use] + pub fn capten1(&mut self) -> CAPTEN1_W<17> { + CAPTEN1_W::new(self) + } + #[doc = "Bit 20 - Capture On Pin 0 Enable"] + #[inline(always)] + #[must_use] + pub fn copen0(&mut self) -> COPEN0_W<20> { + COPEN0_W::new(self) + } + #[doc = "Bit 21 - Capture On Pin 1 Enable"] + #[inline(always)] + #[must_use] + pub fn copen1(&mut self) -> COPEN1_W<21> { + COPEN1_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tc0/count32/ctrlbclr.rs b/pac/atsaml22j/src/tc0/count32/ctrlbclr.rs new file mode 100644 index 000000000000..aea0a17cba36 --- /dev/null +++ b/pac/atsaml22j/src/tc0/count32/ctrlbclr.rs @@ -0,0 +1,225 @@ +#[doc = "Register `CTRLBCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub type DIR_R = crate::BitReader; +#[doc = "Field `DIR` writer - Counter Direction"] +pub type DIR_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLBCLR_SPEC, bool, O>; +#[doc = "Field `LUPD` reader - Lock Update"] +pub type LUPD_R = crate::BitReader; +#[doc = "Field `LUPD` writer - Lock Update"] +pub type LUPD_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLBCLR_SPEC, bool, O>; +#[doc = "Field `ONESHOT` reader - One-Shot on Counter"] +pub type ONESHOT_R = crate::BitReader; +#[doc = "Field `ONESHOT` writer - One-Shot on Counter"] +pub type ONESHOT_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLBCLR_SPEC, bool, O>; +#[doc = "Field `CMD` reader - Command"] +pub type CMD_R = crate::FieldReader; +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum CMDSELECT_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, + #[doc = "3: Force update of double-buffered register"] + UPDATE = 3, + #[doc = "4: Force a read synchronization of COUNT"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMDSELECT_A) -> Self { + variant as _ + } +} +impl CMD_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMDSELECT_A::NONE), + 1 => Some(CMDSELECT_A::RETRIGGER), + 2 => Some(CMDSELECT_A::STOP), + 3 => Some(CMDSELECT_A::UPDATE), + 4 => Some(CMDSELECT_A::READSYNC), + 5 => Some(CMDSELECT_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == CMDSELECT_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + *self == CMDSELECT_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + *self == CMDSELECT_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + *self == CMDSELECT_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + *self == CMDSELECT_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + *self == CMDSELECT_A::DMAOS + } +} +#[doc = "Field `CMD` writer - Command"] +pub type CMD_W<'a, const O: u8> = crate::FieldWriter<'a, u8, CTRLBCLR_SPEC, u8, CMDSELECT_A, 3, O>; +impl<'a, const O: u8> CMD_W<'a, O> { + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMDSELECT_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMDSELECT_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMDSELECT_A::STOP) + } + #[doc = "Force update of double-buffered register"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMDSELECT_A::UPDATE) + } + #[doc = "Force a read synchronization of COUNT"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMDSELECT_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMDSELECT_A::DMAOS) + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new((self.bits >> 5) & 7) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + #[must_use] + pub fn dir(&mut self) -> DIR_W<0> { + DIR_W::new(self) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + #[must_use] + pub fn lupd(&mut self) -> LUPD_W<1> { + LUPD_W::new(self) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + #[must_use] + pub fn oneshot(&mut self) -> ONESHOT_W<2> { + ONESHOT_W::new(self) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + #[must_use] + pub fn cmd(&mut self) -> CMD_W<5> { + CMD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbclr](index.html) module"] +pub struct CTRLBCLR_SPEC; +impl crate::RegisterSpec for CTRLBCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbclr::R](R) reader structure"] +impl crate::Readable for CTRLBCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbclr::W](W) writer structure"] +impl crate::Writable for CTRLBCLR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRLBCLR to value 0"] +impl crate::Resettable for CTRLBCLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tc0/count32/ctrlbset.rs b/pac/atsaml22j/src/tc0/count32/ctrlbset.rs new file mode 100644 index 000000000000..759f260623a2 --- /dev/null +++ b/pac/atsaml22j/src/tc0/count32/ctrlbset.rs @@ -0,0 +1,225 @@ +#[doc = "Register `CTRLBSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub type DIR_R = crate::BitReader; +#[doc = "Field `DIR` writer - Counter Direction"] +pub type DIR_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLBSET_SPEC, bool, O>; +#[doc = "Field `LUPD` reader - Lock Update"] +pub type LUPD_R = crate::BitReader; +#[doc = "Field `LUPD` writer - Lock Update"] +pub type LUPD_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLBSET_SPEC, bool, O>; +#[doc = "Field `ONESHOT` reader - One-Shot on Counter"] +pub type ONESHOT_R = crate::BitReader; +#[doc = "Field `ONESHOT` writer - One-Shot on Counter"] +pub type ONESHOT_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLBSET_SPEC, bool, O>; +#[doc = "Field `CMD` reader - Command"] +pub type CMD_R = crate::FieldReader; +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum CMDSELECT_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, + #[doc = "3: Force update of double-buffered register"] + UPDATE = 3, + #[doc = "4: Force a read synchronization of COUNT"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMDSELECT_A) -> Self { + variant as _ + } +} +impl CMD_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMDSELECT_A::NONE), + 1 => Some(CMDSELECT_A::RETRIGGER), + 2 => Some(CMDSELECT_A::STOP), + 3 => Some(CMDSELECT_A::UPDATE), + 4 => Some(CMDSELECT_A::READSYNC), + 5 => Some(CMDSELECT_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == CMDSELECT_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + *self == CMDSELECT_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + *self == CMDSELECT_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + *self == CMDSELECT_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + *self == CMDSELECT_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + *self == CMDSELECT_A::DMAOS + } +} +#[doc = "Field `CMD` writer - Command"] +pub type CMD_W<'a, const O: u8> = crate::FieldWriter<'a, u8, CTRLBSET_SPEC, u8, CMDSELECT_A, 3, O>; +impl<'a, const O: u8> CMD_W<'a, O> { + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMDSELECT_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMDSELECT_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMDSELECT_A::STOP) + } + #[doc = "Force update of double-buffered register"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMDSELECT_A::UPDATE) + } + #[doc = "Force a read synchronization of COUNT"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMDSELECT_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMDSELECT_A::DMAOS) + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new((self.bits >> 5) & 7) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + #[must_use] + pub fn dir(&mut self) -> DIR_W<0> { + DIR_W::new(self) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + #[must_use] + pub fn lupd(&mut self) -> LUPD_W<1> { + LUPD_W::new(self) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + #[must_use] + pub fn oneshot(&mut self) -> ONESHOT_W<2> { + ONESHOT_W::new(self) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + #[must_use] + pub fn cmd(&mut self) -> CMD_W<5> { + CMD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbset](index.html) module"] +pub struct CTRLBSET_SPEC; +impl crate::RegisterSpec for CTRLBSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbset::R](R) reader structure"] +impl crate::Readable for CTRLBSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbset::W](W) writer structure"] +impl crate::Writable for CTRLBSET_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRLBSET to value 0"] +impl crate::Resettable for CTRLBSET_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tc0/count32/dbgctrl.rs b/pac/atsaml22j/src/tc0/count32/dbgctrl.rs new file mode 100644 index 000000000000..271f8aa633ac --- /dev/null +++ b/pac/atsaml22j/src/tc0/count32/dbgctrl.rs @@ -0,0 +1,80 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub type DBGRUN_R = crate::BitReader; +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub type DBGRUN_W<'a, const O: u8> = crate::BitWriter<'a, u8, DBGCTRL_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + #[must_use] + pub fn dbgrun(&mut self) -> DBGRUN_W<0> { + DBGRUN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tc0/count32/drvctrl.rs b/pac/atsaml22j/src/tc0/count32/drvctrl.rs new file mode 100644 index 000000000000..b6e499c1e0fe --- /dev/null +++ b/pac/atsaml22j/src/tc0/count32/drvctrl.rs @@ -0,0 +1,95 @@ +#[doc = "Register `DRVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DRVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INVEN0` reader - Output Waveform Invert Enable 0"] +pub type INVEN0_R = crate::BitReader; +#[doc = "Field `INVEN0` writer - Output Waveform Invert Enable 0"] +pub type INVEN0_W<'a, const O: u8> = crate::BitWriter<'a, u8, DRVCTRL_SPEC, bool, O>; +#[doc = "Field `INVEN1` reader - Output Waveform Invert Enable 1"] +pub type INVEN1_R = crate::BitReader; +#[doc = "Field `INVEN1` writer - Output Waveform Invert Enable 1"] +pub type INVEN1_W<'a, const O: u8> = crate::BitWriter<'a, u8, DRVCTRL_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Output Waveform Invert Enable 0"] + #[inline(always)] + pub fn inven0(&self) -> INVEN0_R { + INVEN0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Output Waveform Invert Enable 1"] + #[inline(always)] + pub fn inven1(&self) -> INVEN1_R { + INVEN1_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Output Waveform Invert Enable 0"] + #[inline(always)] + #[must_use] + pub fn inven0(&mut self) -> INVEN0_W<0> { + INVEN0_W::new(self) + } + #[doc = "Bit 1 - Output Waveform Invert Enable 1"] + #[inline(always)] + #[must_use] + pub fn inven1(&mut self) -> INVEN1_W<1> { + INVEN1_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [drvctrl](index.html) module"] +pub struct DRVCTRL_SPEC; +impl crate::RegisterSpec for DRVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [drvctrl::R](R) reader structure"] +impl crate::Readable for DRVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [drvctrl::W](W) writer structure"] +impl crate::Writable for DRVCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DRVCTRL to value 0"] +impl crate::Resettable for DRVCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tc0/count32/evctrl.rs b/pac/atsaml22j/src/tc0/count32/evctrl.rs new file mode 100644 index 000000000000..9238d1566f09 --- /dev/null +++ b/pac/atsaml22j/src/tc0/count32/evctrl.rs @@ -0,0 +1,282 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVACT` reader - Event Action"] +pub type EVACT_R = crate::FieldReader; +#[doc = "Event Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum EVACTSELECT_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Start, restart or retrigger TC on event"] + RETRIGGER = 1, + #[doc = "2: Count on event"] + COUNT = 2, + #[doc = "3: Start TC on event"] + START = 3, + #[doc = "4: Time stamp capture"] + STAMP = 4, + #[doc = "5: Period catured in CC0, pulse width in CC1"] + PPW = 5, + #[doc = "6: Period catured in CC1, pulse width in CC0"] + PWP = 6, + #[doc = "7: Pulse width capture"] + PW = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACTSELECT_A) -> Self { + variant as _ + } +} +impl EVACT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVACTSELECT_A { + match self.bits { + 0 => EVACTSELECT_A::OFF, + 1 => EVACTSELECT_A::RETRIGGER, + 2 => EVACTSELECT_A::COUNT, + 3 => EVACTSELECT_A::START, + 4 => EVACTSELECT_A::STAMP, + 5 => EVACTSELECT_A::PPW, + 6 => EVACTSELECT_A::PWP, + 7 => EVACTSELECT_A::PW, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == EVACTSELECT_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + *self == EVACTSELECT_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `COUNT`"] + #[inline(always)] + pub fn is_count(&self) -> bool { + *self == EVACTSELECT_A::COUNT + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + *self == EVACTSELECT_A::START + } + #[doc = "Checks if the value of the field is `STAMP`"] + #[inline(always)] + pub fn is_stamp(&self) -> bool { + *self == EVACTSELECT_A::STAMP + } + #[doc = "Checks if the value of the field is `PPW`"] + #[inline(always)] + pub fn is_ppw(&self) -> bool { + *self == EVACTSELECT_A::PPW + } + #[doc = "Checks if the value of the field is `PWP`"] + #[inline(always)] + pub fn is_pwp(&self) -> bool { + *self == EVACTSELECT_A::PWP + } + #[doc = "Checks if the value of the field is `PW`"] + #[inline(always)] + pub fn is_pw(&self) -> bool { + *self == EVACTSELECT_A::PW + } +} +#[doc = "Field `EVACT` writer - Event Action"] +pub type EVACT_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u16, EVCTRL_SPEC, u8, EVACTSELECT_A, 3, O>; +impl<'a, const O: u8> EVACT_W<'a, O> { + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACTSELECT_A::OFF) + } + #[doc = "Start, restart or retrigger TC on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACTSELECT_A::RETRIGGER) + } + #[doc = "Count on event"] + #[inline(always)] + pub fn count(self) -> &'a mut W { + self.variant(EVACTSELECT_A::COUNT) + } + #[doc = "Start TC on event"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(EVACTSELECT_A::START) + } + #[doc = "Time stamp capture"] + #[inline(always)] + pub fn stamp(self) -> &'a mut W { + self.variant(EVACTSELECT_A::STAMP) + } + #[doc = "Period catured in CC0, pulse width in CC1"] + #[inline(always)] + pub fn ppw(self) -> &'a mut W { + self.variant(EVACTSELECT_A::PPW) + } + #[doc = "Period catured in CC1, pulse width in CC0"] + #[inline(always)] + pub fn pwp(self) -> &'a mut W { + self.variant(EVACTSELECT_A::PWP) + } + #[doc = "Pulse width capture"] + #[inline(always)] + pub fn pw(self) -> &'a mut W { + self.variant(EVACTSELECT_A::PW) + } +} +#[doc = "Field `TCINV` reader - TC Event Input Polarity"] +pub type TCINV_R = crate::BitReader; +#[doc = "Field `TCINV` writer - TC Event Input Polarity"] +pub type TCINV_W<'a, const O: u8> = crate::BitWriter<'a, u16, EVCTRL_SPEC, bool, O>; +#[doc = "Field `TCEI` reader - TC Event Enable"] +pub type TCEI_R = crate::BitReader; +#[doc = "Field `TCEI` writer - TC Event Enable"] +pub type TCEI_W<'a, const O: u8> = crate::BitWriter<'a, u16, EVCTRL_SPEC, bool, O>; +#[doc = "Field `OVFEO` reader - Event Output Enable"] +pub type OVFEO_R = crate::BitReader; +#[doc = "Field `OVFEO` writer - Event Output Enable"] +pub type OVFEO_W<'a, const O: u8> = crate::BitWriter<'a, u16, EVCTRL_SPEC, bool, O>; +#[doc = "Field `MCEO0` reader - MC Event Output Enable 0"] +pub type MCEO0_R = crate::BitReader; +#[doc = "Field `MCEO0` writer - MC Event Output Enable 0"] +pub type MCEO0_W<'a, const O: u8> = crate::BitWriter<'a, u16, EVCTRL_SPEC, bool, O>; +#[doc = "Field `MCEO1` reader - MC Event Output Enable 1"] +pub type MCEO1_R = crate::BitReader; +#[doc = "Field `MCEO1` writer - MC Event Output Enable 1"] +pub type MCEO1_W<'a, const O: u8> = crate::BitWriter<'a, u16, EVCTRL_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&self) -> EVACT_R { + EVACT_R::new((self.bits & 7) as u8) + } + #[doc = "Bit 4 - TC Event Input Polarity"] + #[inline(always)] + pub fn tcinv(&self) -> TCINV_R { + TCINV_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - TC Event Enable"] + #[inline(always)] + pub fn tcei(&self) -> TCEI_R { + TCEI_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 8 - Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 12 - MC Event Output Enable 0"] + #[inline(always)] + pub fn mceo0(&self) -> MCEO0_R { + MCEO0_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - MC Event Output Enable 1"] + #[inline(always)] + pub fn mceo1(&self) -> MCEO1_R { + MCEO1_R::new(((self.bits >> 13) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + #[must_use] + pub fn evact(&mut self) -> EVACT_W<0> { + EVACT_W::new(self) + } + #[doc = "Bit 4 - TC Event Input Polarity"] + #[inline(always)] + #[must_use] + pub fn tcinv(&mut self) -> TCINV_W<4> { + TCINV_W::new(self) + } + #[doc = "Bit 5 - TC Event Enable"] + #[inline(always)] + #[must_use] + pub fn tcei(&mut self) -> TCEI_W<5> { + TCEI_W::new(self) + } + #[doc = "Bit 8 - Event Output Enable"] + #[inline(always)] + #[must_use] + pub fn ovfeo(&mut self) -> OVFEO_W<8> { + OVFEO_W::new(self) + } + #[doc = "Bit 12 - MC Event Output Enable 0"] + #[inline(always)] + #[must_use] + pub fn mceo0(&mut self) -> MCEO0_W<12> { + MCEO0_W::new(self) + } + #[doc = "Bit 13 - MC Event Output Enable 1"] + #[inline(always)] + #[must_use] + pub fn mceo1(&mut self) -> MCEO1_W<13> { + MCEO1_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tc0/count32/intenclr.rs b/pac/atsaml22j/src/tc0/count32/intenclr.rs new file mode 100644 index 000000000000..940e1f9474a1 --- /dev/null +++ b/pac/atsaml22j/src/tc0/count32/intenclr.rs @@ -0,0 +1,125 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Disable"] +pub type OVF_R = crate::BitReader; +#[doc = "Field `OVF` writer - OVF Interrupt Disable"] +pub type OVF_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>; +#[doc = "Field `ERR` reader - ERR Interrupt Disable"] +pub type ERR_R = crate::BitReader; +#[doc = "Field `ERR` writer - ERR Interrupt Disable"] +pub type ERR_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>; +#[doc = "Field `MC0` reader - MC Interrupt Disable 0"] +pub type MC0_R = crate::BitReader; +#[doc = "Field `MC0` writer - MC Interrupt Disable 0"] +pub type MC0_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>; +#[doc = "Field `MC1` reader - MC Interrupt Disable 1"] +pub type MC1_R = crate::BitReader; +#[doc = "Field `MC1` writer - MC Interrupt Disable 1"] +pub type MC1_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - OVF Interrupt Disable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Disable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 4 - MC Interrupt Disable 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - MC Interrupt Disable 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Disable"] + #[inline(always)] + #[must_use] + pub fn ovf(&mut self) -> OVF_W<0> { + OVF_W::new(self) + } + #[doc = "Bit 1 - ERR Interrupt Disable"] + #[inline(always)] + #[must_use] + pub fn err(&mut self) -> ERR_W<1> { + ERR_W::new(self) + } + #[doc = "Bit 4 - MC Interrupt Disable 0"] + #[inline(always)] + #[must_use] + pub fn mc0(&mut self) -> MC0_W<4> { + MC0_W::new(self) + } + #[doc = "Bit 5 - MC Interrupt Disable 1"] + #[inline(always)] + #[must_use] + pub fn mc1(&mut self) -> MC1_W<5> { + MC1_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tc0/count32/intenset.rs b/pac/atsaml22j/src/tc0/count32/intenset.rs new file mode 100644 index 000000000000..308be3696676 --- /dev/null +++ b/pac/atsaml22j/src/tc0/count32/intenset.rs @@ -0,0 +1,125 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Enable"] +pub type OVF_R = crate::BitReader; +#[doc = "Field `OVF` writer - OVF Interrupt Enable"] +pub type OVF_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENSET_SPEC, bool, O>; +#[doc = "Field `ERR` reader - ERR Interrupt Enable"] +pub type ERR_R = crate::BitReader; +#[doc = "Field `ERR` writer - ERR Interrupt Enable"] +pub type ERR_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENSET_SPEC, bool, O>; +#[doc = "Field `MC0` reader - MC Interrupt Enable 0"] +pub type MC0_R = crate::BitReader; +#[doc = "Field `MC0` writer - MC Interrupt Enable 0"] +pub type MC0_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENSET_SPEC, bool, O>; +#[doc = "Field `MC1` reader - MC Interrupt Enable 1"] +pub type MC1_R = crate::BitReader; +#[doc = "Field `MC1` writer - MC Interrupt Enable 1"] +pub type MC1_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENSET_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - OVF Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 4 - MC Interrupt Enable 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - MC Interrupt Enable 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn ovf(&mut self) -> OVF_W<0> { + OVF_W::new(self) + } + #[doc = "Bit 1 - ERR Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn err(&mut self) -> ERR_W<1> { + ERR_W::new(self) + } + #[doc = "Bit 4 - MC Interrupt Enable 0"] + #[inline(always)] + #[must_use] + pub fn mc0(&mut self) -> MC0_W<4> { + MC0_W::new(self) + } + #[doc = "Bit 5 - MC Interrupt Enable 1"] + #[inline(always)] + #[must_use] + pub fn mc1(&mut self) -> MC1_W<5> { + MC1_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tc0/count32/intflag.rs b/pac/atsaml22j/src/tc0/count32/intflag.rs new file mode 100644 index 000000000000..e168641a7cfd --- /dev/null +++ b/pac/atsaml22j/src/tc0/count32/intflag.rs @@ -0,0 +1,125 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Flag"] +pub type OVF_R = crate::BitReader; +#[doc = "Field `OVF` writer - OVF Interrupt Flag"] +pub type OVF_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTFLAG_SPEC, bool, O>; +#[doc = "Field `ERR` reader - ERR Interrupt Flag"] +pub type ERR_R = crate::BitReader; +#[doc = "Field `ERR` writer - ERR Interrupt Flag"] +pub type ERR_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTFLAG_SPEC, bool, O>; +#[doc = "Field `MC0` reader - MC Interrupt Flag 0"] +pub type MC0_R = crate::BitReader; +#[doc = "Field `MC0` writer - MC Interrupt Flag 0"] +pub type MC0_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTFLAG_SPEC, bool, O>; +#[doc = "Field `MC1` reader - MC Interrupt Flag 1"] +pub type MC1_R = crate::BitReader; +#[doc = "Field `MC1` writer - MC Interrupt Flag 1"] +pub type MC1_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTFLAG_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - OVF Interrupt Flag"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Flag"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 4 - MC Interrupt Flag 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - MC Interrupt Flag 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Flag"] + #[inline(always)] + #[must_use] + pub fn ovf(&mut self) -> OVF_W<0> { + OVF_W::new(self) + } + #[doc = "Bit 1 - ERR Interrupt Flag"] + #[inline(always)] + #[must_use] + pub fn err(&mut self) -> ERR_W<1> { + ERR_W::new(self) + } + #[doc = "Bit 4 - MC Interrupt Flag 0"] + #[inline(always)] + #[must_use] + pub fn mc0(&mut self) -> MC0_W<4> { + MC0_W::new(self) + } + #[doc = "Bit 5 - MC Interrupt Flag 1"] + #[inline(always)] + #[must_use] + pub fn mc1(&mut self) -> MC1_W<5> { + MC1_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tc0/count32/status.rs b/pac/atsaml22j/src/tc0/count32/status.rs new file mode 100644 index 000000000000..d970ceba0574 --- /dev/null +++ b/pac/atsaml22j/src/tc0/count32/status.rs @@ -0,0 +1,124 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STOP` reader - Stop Status Flag"] +pub type STOP_R = crate::BitReader; +#[doc = "Field `SLAVE` reader - Slave Status Flag"] +pub type SLAVE_R = crate::BitReader; +#[doc = "Field `PERBUFV` reader - Synchronization Busy Status"] +pub type PERBUFV_R = crate::BitReader; +#[doc = "Field `PERBUFV` writer - Synchronization Busy Status"] +pub type PERBUFV_W<'a, const O: u8> = crate::BitWriter<'a, u8, STATUS_SPEC, bool, O>; +#[doc = "Field `CCBUFV0` reader - Compare channel buffer 0 valid"] +pub type CCBUFV0_R = crate::BitReader; +#[doc = "Field `CCBUFV0` writer - Compare channel buffer 0 valid"] +pub type CCBUFV0_W<'a, const O: u8> = crate::BitWriter<'a, u8, STATUS_SPEC, bool, O>; +#[doc = "Field `CCBUFV1` reader - Compare channel buffer 1 valid"] +pub type CCBUFV1_R = crate::BitReader; +#[doc = "Field `CCBUFV1` writer - Compare channel buffer 1 valid"] +pub type CCBUFV1_W<'a, const O: u8> = crate::BitWriter<'a, u8, STATUS_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Stop Status Flag"] + #[inline(always)] + pub fn stop(&self) -> STOP_R { + STOP_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Slave Status Flag"] + #[inline(always)] + pub fn slave(&self) -> SLAVE_R { + SLAVE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Synchronization Busy Status"] + #[inline(always)] + pub fn perbufv(&self) -> PERBUFV_R { + PERBUFV_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Compare channel buffer 0 valid"] + #[inline(always)] + pub fn ccbufv0(&self) -> CCBUFV0_R { + CCBUFV0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Compare channel buffer 1 valid"] + #[inline(always)] + pub fn ccbufv1(&self) -> CCBUFV1_R { + CCBUFV1_R::new(((self.bits >> 5) & 1) != 0) + } +} +impl W { + #[doc = "Bit 3 - Synchronization Busy Status"] + #[inline(always)] + #[must_use] + pub fn perbufv(&mut self) -> PERBUFV_W<3> { + PERBUFV_W::new(self) + } + #[doc = "Bit 4 - Compare channel buffer 0 valid"] + #[inline(always)] + #[must_use] + pub fn ccbufv0(&mut self) -> CCBUFV0_W<4> { + CCBUFV0_W::new(self) + } + #[doc = "Bit 5 - Compare channel buffer 1 valid"] + #[inline(always)] + #[must_use] + pub fn ccbufv1(&mut self) -> CCBUFV1_W<5> { + CCBUFV1_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets STATUS to value 0x01"] +impl crate::Resettable for STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/pac/atsaml22j/src/tc0/count32/syncbusy.rs b/pac/atsaml22j/src/tc0/count32/syncbusy.rs new file mode 100644 index 000000000000..901c6571d922 --- /dev/null +++ b/pac/atsaml22j/src/tc0/count32/syncbusy.rs @@ -0,0 +1,86 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - swrst"] +pub type SWRST_R = crate::BitReader; +#[doc = "Field `ENABLE` reader - enable"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `CTRLB` reader - CTRLB"] +pub type CTRLB_R = crate::BitReader; +#[doc = "Field `STATUS` reader - STATUS"] +pub type STATUS_R = crate::BitReader; +#[doc = "Field `COUNT` reader - Counter"] +pub type COUNT_R = crate::BitReader; +#[doc = "Field `PER` reader - Period"] +pub type PER_R = crate::BitReader; +#[doc = "Field `CC0` reader - Compare Channel 0"] +pub type CC0_R = crate::BitReader; +#[doc = "Field `CC1` reader - Compare Channel 1"] +pub type CC1_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - swrst"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - CTRLB"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - STATUS"] + #[inline(always)] + pub fn status(&self) -> STATUS_R { + STATUS_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Counter"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Period"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Compare Channel 0"] + #[inline(always)] + pub fn cc0(&self) -> CC0_R { + CC0_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Compare Channel 1"] + #[inline(always)] + pub fn cc1(&self) -> CC1_R { + CC1_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[doc = "Synchronization Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tc0/count32/wave.rs b/pac/atsaml22j/src/tc0/count32/wave.rs new file mode 100644 index 000000000000..c6776ad1adeb --- /dev/null +++ b/pac/atsaml22j/src/tc0/count32/wave.rs @@ -0,0 +1,155 @@ +#[doc = "Register `WAVE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WAVE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WAVEGEN` reader - Waveform Generation Mode"] +pub type WAVEGEN_R = crate::FieldReader; +#[doc = "Waveform Generation Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum WAVEGENSELECT_A { + #[doc = "0: Normal frequency"] + NFRQ = 0, + #[doc = "1: Match frequency"] + MFRQ = 1, + #[doc = "2: Normal PWM"] + NPWM = 2, + #[doc = "3: Match PWM"] + MPWM = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WAVEGENSELECT_A) -> Self { + variant as _ + } +} +impl WAVEGEN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WAVEGENSELECT_A { + match self.bits { + 0 => WAVEGENSELECT_A::NFRQ, + 1 => WAVEGENSELECT_A::MFRQ, + 2 => WAVEGENSELECT_A::NPWM, + 3 => WAVEGENSELECT_A::MPWM, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NFRQ`"] + #[inline(always)] + pub fn is_nfrq(&self) -> bool { + *self == WAVEGENSELECT_A::NFRQ + } + #[doc = "Checks if the value of the field is `MFRQ`"] + #[inline(always)] + pub fn is_mfrq(&self) -> bool { + *self == WAVEGENSELECT_A::MFRQ + } + #[doc = "Checks if the value of the field is `NPWM`"] + #[inline(always)] + pub fn is_npwm(&self) -> bool { + *self == WAVEGENSELECT_A::NPWM + } + #[doc = "Checks if the value of the field is `MPWM`"] + #[inline(always)] + pub fn is_mpwm(&self) -> bool { + *self == WAVEGENSELECT_A::MPWM + } +} +#[doc = "Field `WAVEGEN` writer - Waveform Generation Mode"] +pub type WAVEGEN_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u8, WAVE_SPEC, u8, WAVEGENSELECT_A, 2, O>; +impl<'a, const O: u8> WAVEGEN_W<'a, O> { + #[doc = "Normal frequency"] + #[inline(always)] + pub fn nfrq(self) -> &'a mut W { + self.variant(WAVEGENSELECT_A::NFRQ) + } + #[doc = "Match frequency"] + #[inline(always)] + pub fn mfrq(self) -> &'a mut W { + self.variant(WAVEGENSELECT_A::MFRQ) + } + #[doc = "Normal PWM"] + #[inline(always)] + pub fn npwm(self) -> &'a mut W { + self.variant(WAVEGENSELECT_A::NPWM) + } + #[doc = "Match PWM"] + #[inline(always)] + pub fn mpwm(self) -> &'a mut W { + self.variant(WAVEGENSELECT_A::MPWM) + } +} +impl R { + #[doc = "Bits 0:1 - Waveform Generation Mode"] + #[inline(always)] + pub fn wavegen(&self) -> WAVEGEN_R { + WAVEGEN_R::new(self.bits & 3) + } +} +impl W { + #[doc = "Bits 0:1 - Waveform Generation Mode"] + #[inline(always)] + #[must_use] + pub fn wavegen(&mut self) -> WAVEGEN_W<0> { + WAVEGEN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Waveform Generation Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wave](index.html) module"] +pub struct WAVE_SPEC; +impl crate::RegisterSpec for WAVE_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [wave::R](R) reader structure"] +impl crate::Readable for WAVE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wave::W](W) writer structure"] +impl crate::Writable for WAVE_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets WAVE to value 0"] +impl crate::Resettable for WAVE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tc0/count8.rs b/pac/atsaml22j/src/tc0/count8.rs new file mode 100644 index 000000000000..a9dc33daad77 --- /dev/null +++ b/pac/atsaml22j/src/tc0/count8.rs @@ -0,0 +1,109 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct COUNT8 { + #[doc = "0x00 - Control A"] + pub ctrla: CTRLA, + #[doc = "0x04 - Control B Clear"] + pub ctrlbclr: CTRLBCLR, + #[doc = "0x05 - Control B Set"] + pub ctrlbset: CTRLBSET, + #[doc = "0x06 - Event Control"] + pub evctrl: EVCTRL, + #[doc = "0x08 - Interrupt Enable Clear"] + pub intenclr: INTENCLR, + #[doc = "0x09 - Interrupt Enable Set"] + pub intenset: INTENSET, + #[doc = "0x0a - Interrupt Flag Status and Clear"] + pub intflag: INTFLAG, + #[doc = "0x0b - Status"] + pub status: STATUS, + #[doc = "0x0c - Waveform Generation Control"] + pub wave: WAVE, + #[doc = "0x0d - Control C"] + pub drvctrl: DRVCTRL, + _reserved10: [u8; 0x01], + #[doc = "0x0f - Debug Control"] + pub dbgctrl: DBGCTRL, + #[doc = "0x10 - Synchronization Status"] + pub syncbusy: SYNCBUSY, + #[doc = "0x14 - COUNT8 Count"] + pub count: COUNT, + _reserved13: [u8; 0x06], + #[doc = "0x1b - COUNT8 Period"] + pub per: PER, + #[doc = "0x1c - COUNT8 Compare and Capture"] + pub cc: [CC; 2], + _reserved15: [u8; 0x11], + #[doc = "0x2f - COUNT8 Period Buffer"] + pub perbuf: PERBUF, + #[doc = "0x30 - COUNT8 Compare and Capture Buffer"] + pub ccbuf: [CCBUF; 2], +} +#[doc = "CTRLA (rw) register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLBCLR (rw) register accessor: an alias for `Reg`"] +pub type CTRLBCLR = crate::Reg; +#[doc = "Control B Clear"] +pub mod ctrlbclr; +#[doc = "CTRLBSET (rw) register accessor: an alias for `Reg`"] +pub type CTRLBSET = crate::Reg; +#[doc = "Control B Set"] +pub mod ctrlbset; +#[doc = "EVCTRL (rw) register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR (rw) register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET (rw) register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG (rw) register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS (rw) register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "WAVE (rw) register accessor: an alias for `Reg`"] +pub type WAVE = crate::Reg; +#[doc = "Waveform Generation Control"] +pub mod wave; +#[doc = "DRVCTRL (rw) register accessor: an alias for `Reg`"] +pub type DRVCTRL = crate::Reg; +#[doc = "Control C"] +pub mod drvctrl; +#[doc = "DBGCTRL (rw) register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "SYNCBUSY (r) register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Status"] +pub mod syncbusy; +#[doc = "COUNT (rw) register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "COUNT8 Count"] +pub mod count; +#[doc = "PER (rw) register accessor: an alias for `Reg`"] +pub type PER = crate::Reg; +#[doc = "COUNT8 Period"] +pub mod per; +#[doc = "CC (rw) register accessor: an alias for `Reg`"] +pub type CC = crate::Reg; +#[doc = "COUNT8 Compare and Capture"] +pub mod cc; +#[doc = "PERBUF (rw) register accessor: an alias for `Reg`"] +pub type PERBUF = crate::Reg; +#[doc = "COUNT8 Period Buffer"] +pub mod perbuf; +#[doc = "CCBUF (rw) register accessor: an alias for `Reg`"] +pub type CCBUF = crate::Reg; +#[doc = "COUNT8 Compare and Capture Buffer"] +pub mod ccbuf; diff --git a/pac/atsaml22j/src/tc0/count8/cc.rs b/pac/atsaml22j/src/tc0/count8/cc.rs new file mode 100644 index 000000000000..247a1cb49559 --- /dev/null +++ b/pac/atsaml22j/src/tc0/count8/cc.rs @@ -0,0 +1,80 @@ +#[doc = "Register `CC%s` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC%s` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CC` reader - Counter/Compare Value"] +pub type CC_R = crate::FieldReader; +#[doc = "Field `CC` writer - Counter/Compare Value"] +pub type CC_W<'a, const O: u8> = crate::FieldWriter<'a, u8, CC_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Counter/Compare Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:7 - Counter/Compare Value"] + #[inline(always)] + #[must_use] + pub fn cc(&mut self) -> CC_W<0> { + CC_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT8 Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc](index.html) module"] +pub struct CC_SPEC; +impl crate::RegisterSpec for CC_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [cc::R](R) reader structure"] +impl crate::Readable for CC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc::W](W) writer structure"] +impl crate::Writable for CC_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CC%s to value 0"] +impl crate::Resettable for CC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tc0/count8/ccbuf.rs b/pac/atsaml22j/src/tc0/count8/ccbuf.rs new file mode 100644 index 000000000000..2a88478d6f34 --- /dev/null +++ b/pac/atsaml22j/src/tc0/count8/ccbuf.rs @@ -0,0 +1,80 @@ +#[doc = "Register `CCBUF%s` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF%s` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CCBUF` reader - Counter/Compare Buffer Value"] +pub type CCBUF_R = crate::FieldReader; +#[doc = "Field `CCBUF` writer - Counter/Compare Buffer Value"] +pub type CCBUF_W<'a, const O: u8> = crate::FieldWriter<'a, u8, CCBUF_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Counter/Compare Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:7 - Counter/Compare Buffer Value"] + #[inline(always)] + #[must_use] + pub fn ccbuf(&mut self) -> CCBUF_W<0> { + CCBUF_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT8 Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf](index.html) module"] +pub struct CCBUF_SPEC; +impl crate::RegisterSpec for CCBUF_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ccbuf::R](R) reader structure"] +impl crate::Readable for CCBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf::W](W) writer structure"] +impl crate::Writable for CCBUF_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CCBUF%s to value 0"] +impl crate::Resettable for CCBUF_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tc0/count8/count.rs b/pac/atsaml22j/src/tc0/count8/count.rs new file mode 100644 index 000000000000..ae0c02a519ce --- /dev/null +++ b/pac/atsaml22j/src/tc0/count8/count.rs @@ -0,0 +1,80 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub type COUNT_R = crate::FieldReader; +#[doc = "Field `COUNT` writer - Counter Value"] +pub type COUNT_W<'a, const O: u8> = crate::FieldWriter<'a, u8, COUNT_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:7 - Counter Value"] + #[inline(always)] + #[must_use] + pub fn count(&mut self) -> COUNT_W<0> { + COUNT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT8 Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tc0/count8/ctrla.rs b/pac/atsaml22j/src/tc0/count8/ctrla.rs new file mode 100644 index 000000000000..e8bee55276ae --- /dev/null +++ b/pac/atsaml22j/src/tc0/count8/ctrla.rs @@ -0,0 +1,488 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` writer - Software Reset"] +pub type SWRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `ENABLE` reader - Enable"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - Enable"] +pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `MODE` reader - Timer Counter Mode"] +pub type MODE_R = crate::FieldReader; +#[doc = "Timer Counter Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum MODESELECT_A { + #[doc = "0: Counter in 16-bit mode"] + COUNT16 = 0, + #[doc = "1: Counter in 8-bit mode"] + COUNT8 = 1, + #[doc = "2: Counter in 32-bit mode"] + COUNT32 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: MODESELECT_A) -> Self { + variant as _ + } +} +impl MODE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(MODESELECT_A::COUNT16), + 1 => Some(MODESELECT_A::COUNT8), + 2 => Some(MODESELECT_A::COUNT32), + _ => None, + } + } + #[doc = "Checks if the value of the field is `COUNT16`"] + #[inline(always)] + pub fn is_count16(&self) -> bool { + *self == MODESELECT_A::COUNT16 + } + #[doc = "Checks if the value of the field is `COUNT8`"] + #[inline(always)] + pub fn is_count8(&self) -> bool { + *self == MODESELECT_A::COUNT8 + } + #[doc = "Checks if the value of the field is `COUNT32`"] + #[inline(always)] + pub fn is_count32(&self) -> bool { + *self == MODESELECT_A::COUNT32 + } +} +#[doc = "Field `MODE` writer - Timer Counter Mode"] +pub type MODE_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CTRLA_SPEC, u8, MODESELECT_A, 2, O>; +impl<'a, const O: u8> MODE_W<'a, O> { + #[doc = "Counter in 16-bit mode"] + #[inline(always)] + pub fn count16(self) -> &'a mut W { + self.variant(MODESELECT_A::COUNT16) + } + #[doc = "Counter in 8-bit mode"] + #[inline(always)] + pub fn count8(self) -> &'a mut W { + self.variant(MODESELECT_A::COUNT8) + } + #[doc = "Counter in 32-bit mode"] + #[inline(always)] + pub fn count32(self) -> &'a mut W { + self.variant(MODESELECT_A::COUNT32) + } +} +#[doc = "Field `PRESCSYNC` reader - Prescaler and Counter Synchronization"] +pub type PRESCSYNC_R = crate::FieldReader; +#[doc = "Prescaler and Counter Synchronization\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum PRESCSYNCSELECT_A { + #[doc = "0: Reload or reset the counter on next generic clock"] + GCLK = 0, + #[doc = "1: Reload or reset the counter on next prescaler clock"] + PRESC = 1, + #[doc = "2: Reload or reset the counter on next generic clock and reset the prescaler counter"] + RESYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCSYNCSELECT_A) -> Self { + variant as _ + } +} +impl PRESCSYNC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCSYNCSELECT_A::GCLK), + 1 => Some(PRESCSYNCSELECT_A::PRESC), + 2 => Some(PRESCSYNCSELECT_A::RESYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + *self == PRESCSYNCSELECT_A::GCLK + } + #[doc = "Checks if the value of the field is `PRESC`"] + #[inline(always)] + pub fn is_presc(&self) -> bool { + *self == PRESCSYNCSELECT_A::PRESC + } + #[doc = "Checks if the value of the field is `RESYNC`"] + #[inline(always)] + pub fn is_resync(&self) -> bool { + *self == PRESCSYNCSELECT_A::RESYNC + } +} +#[doc = "Field `PRESCSYNC` writer - Prescaler and Counter Synchronization"] +pub type PRESCSYNC_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, CTRLA_SPEC, u8, PRESCSYNCSELECT_A, 2, O>; +impl<'a, const O: u8> PRESCSYNC_W<'a, O> { + #[doc = "Reload or reset the counter on next generic clock"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(PRESCSYNCSELECT_A::GCLK) + } + #[doc = "Reload or reset the counter on next prescaler clock"] + #[inline(always)] + pub fn presc(self) -> &'a mut W { + self.variant(PRESCSYNCSELECT_A::PRESC) + } + #[doc = "Reload or reset the counter on next generic clock and reset the prescaler counter"] + #[inline(always)] + pub fn resync(self) -> &'a mut W { + self.variant(PRESCSYNCSELECT_A::RESYNC) + } +} +#[doc = "Field `RUNSTDBY` reader - Run during Standby"] +pub type RUNSTDBY_R = crate::BitReader; +#[doc = "Field `RUNSTDBY` writer - Run during Standby"] +pub type RUNSTDBY_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `ONDEMAND` reader - Clock On Demand"] +pub type ONDEMAND_R = crate::BitReader; +#[doc = "Field `ONDEMAND` writer - Clock On Demand"] +pub type ONDEMAND_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub type PRESCALER_R = crate::FieldReader; +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum PRESCALERSELECT_A { + #[doc = "0: Prescaler: GCLK_TC"] + DIV1 = 0, + #[doc = "1: Prescaler: GCLK_TC/2"] + DIV2 = 1, + #[doc = "2: Prescaler: GCLK_TC/4"] + DIV4 = 2, + #[doc = "3: Prescaler: GCLK_TC/8"] + DIV8 = 3, + #[doc = "4: Prescaler: GCLK_TC/16"] + DIV16 = 4, + #[doc = "5: Prescaler: GCLK_TC/64"] + DIV64 = 5, + #[doc = "6: Prescaler: GCLK_TC/256"] + DIV256 = 6, + #[doc = "7: Prescaler: GCLK_TC/1024"] + DIV1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALERSELECT_A) -> Self { + variant as _ + } +} +impl PRESCALER_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALERSELECT_A { + match self.bits { + 0 => PRESCALERSELECT_A::DIV1, + 1 => PRESCALERSELECT_A::DIV2, + 2 => PRESCALERSELECT_A::DIV4, + 3 => PRESCALERSELECT_A::DIV8, + 4 => PRESCALERSELECT_A::DIV16, + 5 => PRESCALERSELECT_A::DIV64, + 6 => PRESCALERSELECT_A::DIV256, + 7 => PRESCALERSELECT_A::DIV1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + *self == PRESCALERSELECT_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + *self == PRESCALERSELECT_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + *self == PRESCALERSELECT_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + *self == PRESCALERSELECT_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + *self == PRESCALERSELECT_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + *self == PRESCALERSELECT_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + *self == PRESCALERSELECT_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + *self == PRESCALERSELECT_A::DIV1024 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub type PRESCALER_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, CTRLA_SPEC, u8, PRESCALERSELECT_A, 3, O>; +impl<'a, const O: u8> PRESCALER_W<'a, O> { + #[doc = "Prescaler: GCLK_TC"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV1) + } + #[doc = "Prescaler: GCLK_TC/2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV2) + } + #[doc = "Prescaler: GCLK_TC/4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV4) + } + #[doc = "Prescaler: GCLK_TC/8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV8) + } + #[doc = "Prescaler: GCLK_TC/16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV16) + } + #[doc = "Prescaler: GCLK_TC/64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV64) + } + #[doc = "Prescaler: GCLK_TC/256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV256) + } + #[doc = "Prescaler: GCLK_TC/1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV1024) + } +} +#[doc = "Field `ALOCK` reader - Auto Lock"] +pub type ALOCK_R = crate::BitReader; +#[doc = "Field `ALOCK` writer - Auto Lock"] +pub type ALOCK_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `CAPTEN0` reader - Capture Channel 0 Enable"] +pub type CAPTEN0_R = crate::BitReader; +#[doc = "Field `CAPTEN0` writer - Capture Channel 0 Enable"] +pub type CAPTEN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `CAPTEN1` reader - Capture Channel 1 Enable"] +pub type CAPTEN1_R = crate::BitReader; +#[doc = "Field `CAPTEN1` writer - Capture Channel 1 Enable"] +pub type CAPTEN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `COPEN0` reader - Capture On Pin 0 Enable"] +pub type COPEN0_R = crate::BitReader; +#[doc = "Field `COPEN0` writer - Capture On Pin 0 Enable"] +pub type COPEN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `COPEN1` reader - Capture On Pin 1 Enable"] +pub type COPEN1_R = crate::BitReader; +#[doc = "Field `COPEN1` writer - Capture On Pin 1 Enable"] +pub type COPEN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:3 - Timer Counter Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bits 4:5 - Prescaler and Counter Synchronization"] + #[inline(always)] + pub fn prescsync(&self) -> PRESCSYNC_R { + PRESCSYNC_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Clock On Demand"] + #[inline(always)] + pub fn ondemand(&self) -> ONDEMAND_R { + ONDEMAND_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 11 - Auto Lock"] + #[inline(always)] + pub fn alock(&self) -> ALOCK_R { + ALOCK_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 16 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn capten0(&self) -> CAPTEN0_R { + CAPTEN0_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn capten1(&self) -> CAPTEN1_R { + CAPTEN1_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 20 - Capture On Pin 0 Enable"] + #[inline(always)] + pub fn copen0(&self) -> COPEN0_R { + COPEN0_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Capture On Pin 1 Enable"] + #[inline(always)] + pub fn copen1(&self) -> COPEN1_R { + COPEN1_R::new(((self.bits >> 21) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + #[must_use] + pub fn swrst(&mut self) -> SWRST_W<0> { + SWRST_W::new(self) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W<1> { + ENABLE_W::new(self) + } + #[doc = "Bits 2:3 - Timer Counter Mode"] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> MODE_W<2> { + MODE_W::new(self) + } + #[doc = "Bits 4:5 - Prescaler and Counter Synchronization"] + #[inline(always)] + #[must_use] + pub fn prescsync(&mut self) -> PRESCSYNC_W<4> { + PRESCSYNC_W::new(self) + } + #[doc = "Bit 6 - Run during Standby"] + #[inline(always)] + #[must_use] + pub fn runstdby(&mut self) -> RUNSTDBY_W<6> { + RUNSTDBY_W::new(self) + } + #[doc = "Bit 7 - Clock On Demand"] + #[inline(always)] + #[must_use] + pub fn ondemand(&mut self) -> ONDEMAND_W<7> { + ONDEMAND_W::new(self) + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + #[must_use] + pub fn prescaler(&mut self) -> PRESCALER_W<8> { + PRESCALER_W::new(self) + } + #[doc = "Bit 11 - Auto Lock"] + #[inline(always)] + #[must_use] + pub fn alock(&mut self) -> ALOCK_W<11> { + ALOCK_W::new(self) + } + #[doc = "Bit 16 - Capture Channel 0 Enable"] + #[inline(always)] + #[must_use] + pub fn capten0(&mut self) -> CAPTEN0_W<16> { + CAPTEN0_W::new(self) + } + #[doc = "Bit 17 - Capture Channel 1 Enable"] + #[inline(always)] + #[must_use] + pub fn capten1(&mut self) -> CAPTEN1_W<17> { + CAPTEN1_W::new(self) + } + #[doc = "Bit 20 - Capture On Pin 0 Enable"] + #[inline(always)] + #[must_use] + pub fn copen0(&mut self) -> COPEN0_W<20> { + COPEN0_W::new(self) + } + #[doc = "Bit 21 - Capture On Pin 1 Enable"] + #[inline(always)] + #[must_use] + pub fn copen1(&mut self) -> COPEN1_W<21> { + COPEN1_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tc0/count8/ctrlbclr.rs b/pac/atsaml22j/src/tc0/count8/ctrlbclr.rs new file mode 100644 index 000000000000..aea0a17cba36 --- /dev/null +++ b/pac/atsaml22j/src/tc0/count8/ctrlbclr.rs @@ -0,0 +1,225 @@ +#[doc = "Register `CTRLBCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub type DIR_R = crate::BitReader; +#[doc = "Field `DIR` writer - Counter Direction"] +pub type DIR_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLBCLR_SPEC, bool, O>; +#[doc = "Field `LUPD` reader - Lock Update"] +pub type LUPD_R = crate::BitReader; +#[doc = "Field `LUPD` writer - Lock Update"] +pub type LUPD_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLBCLR_SPEC, bool, O>; +#[doc = "Field `ONESHOT` reader - One-Shot on Counter"] +pub type ONESHOT_R = crate::BitReader; +#[doc = "Field `ONESHOT` writer - One-Shot on Counter"] +pub type ONESHOT_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLBCLR_SPEC, bool, O>; +#[doc = "Field `CMD` reader - Command"] +pub type CMD_R = crate::FieldReader; +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum CMDSELECT_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, + #[doc = "3: Force update of double-buffered register"] + UPDATE = 3, + #[doc = "4: Force a read synchronization of COUNT"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMDSELECT_A) -> Self { + variant as _ + } +} +impl CMD_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMDSELECT_A::NONE), + 1 => Some(CMDSELECT_A::RETRIGGER), + 2 => Some(CMDSELECT_A::STOP), + 3 => Some(CMDSELECT_A::UPDATE), + 4 => Some(CMDSELECT_A::READSYNC), + 5 => Some(CMDSELECT_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == CMDSELECT_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + *self == CMDSELECT_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + *self == CMDSELECT_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + *self == CMDSELECT_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + *self == CMDSELECT_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + *self == CMDSELECT_A::DMAOS + } +} +#[doc = "Field `CMD` writer - Command"] +pub type CMD_W<'a, const O: u8> = crate::FieldWriter<'a, u8, CTRLBCLR_SPEC, u8, CMDSELECT_A, 3, O>; +impl<'a, const O: u8> CMD_W<'a, O> { + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMDSELECT_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMDSELECT_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMDSELECT_A::STOP) + } + #[doc = "Force update of double-buffered register"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMDSELECT_A::UPDATE) + } + #[doc = "Force a read synchronization of COUNT"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMDSELECT_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMDSELECT_A::DMAOS) + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new((self.bits >> 5) & 7) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + #[must_use] + pub fn dir(&mut self) -> DIR_W<0> { + DIR_W::new(self) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + #[must_use] + pub fn lupd(&mut self) -> LUPD_W<1> { + LUPD_W::new(self) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + #[must_use] + pub fn oneshot(&mut self) -> ONESHOT_W<2> { + ONESHOT_W::new(self) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + #[must_use] + pub fn cmd(&mut self) -> CMD_W<5> { + CMD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbclr](index.html) module"] +pub struct CTRLBCLR_SPEC; +impl crate::RegisterSpec for CTRLBCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbclr::R](R) reader structure"] +impl crate::Readable for CTRLBCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbclr::W](W) writer structure"] +impl crate::Writable for CTRLBCLR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRLBCLR to value 0"] +impl crate::Resettable for CTRLBCLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tc0/count8/ctrlbset.rs b/pac/atsaml22j/src/tc0/count8/ctrlbset.rs new file mode 100644 index 000000000000..759f260623a2 --- /dev/null +++ b/pac/atsaml22j/src/tc0/count8/ctrlbset.rs @@ -0,0 +1,225 @@ +#[doc = "Register `CTRLBSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub type DIR_R = crate::BitReader; +#[doc = "Field `DIR` writer - Counter Direction"] +pub type DIR_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLBSET_SPEC, bool, O>; +#[doc = "Field `LUPD` reader - Lock Update"] +pub type LUPD_R = crate::BitReader; +#[doc = "Field `LUPD` writer - Lock Update"] +pub type LUPD_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLBSET_SPEC, bool, O>; +#[doc = "Field `ONESHOT` reader - One-Shot on Counter"] +pub type ONESHOT_R = crate::BitReader; +#[doc = "Field `ONESHOT` writer - One-Shot on Counter"] +pub type ONESHOT_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLBSET_SPEC, bool, O>; +#[doc = "Field `CMD` reader - Command"] +pub type CMD_R = crate::FieldReader; +#[doc = "Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum CMDSELECT_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Force a start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force a stop"] + STOP = 2, + #[doc = "3: Force update of double-buffered register"] + UPDATE = 3, + #[doc = "4: Force a read synchronization of COUNT"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMDSELECT_A) -> Self { + variant as _ + } +} +impl CMD_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMDSELECT_A::NONE), + 1 => Some(CMDSELECT_A::RETRIGGER), + 2 => Some(CMDSELECT_A::STOP), + 3 => Some(CMDSELECT_A::UPDATE), + 4 => Some(CMDSELECT_A::READSYNC), + 5 => Some(CMDSELECT_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == CMDSELECT_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + *self == CMDSELECT_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + *self == CMDSELECT_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + *self == CMDSELECT_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + *self == CMDSELECT_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + *self == CMDSELECT_A::DMAOS + } +} +#[doc = "Field `CMD` writer - Command"] +pub type CMD_W<'a, const O: u8> = crate::FieldWriter<'a, u8, CTRLBSET_SPEC, u8, CMDSELECT_A, 3, O>; +impl<'a, const O: u8> CMD_W<'a, O> { + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMDSELECT_A::NONE) + } + #[doc = "Force a start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMDSELECT_A::RETRIGGER) + } + #[doc = "Force a stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMDSELECT_A::STOP) + } + #[doc = "Force update of double-buffered register"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMDSELECT_A::UPDATE) + } + #[doc = "Force a read synchronization of COUNT"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMDSELECT_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMDSELECT_A::DMAOS) + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new((self.bits >> 5) & 7) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + #[must_use] + pub fn dir(&mut self) -> DIR_W<0> { + DIR_W::new(self) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + #[must_use] + pub fn lupd(&mut self) -> LUPD_W<1> { + LUPD_W::new(self) + } + #[doc = "Bit 2 - One-Shot on Counter"] + #[inline(always)] + #[must_use] + pub fn oneshot(&mut self) -> ONESHOT_W<2> { + ONESHOT_W::new(self) + } + #[doc = "Bits 5:7 - Command"] + #[inline(always)] + #[must_use] + pub fn cmd(&mut self) -> CMD_W<5> { + CMD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbset](index.html) module"] +pub struct CTRLBSET_SPEC; +impl crate::RegisterSpec for CTRLBSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbset::R](R) reader structure"] +impl crate::Readable for CTRLBSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbset::W](W) writer structure"] +impl crate::Writable for CTRLBSET_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRLBSET to value 0"] +impl crate::Resettable for CTRLBSET_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tc0/count8/dbgctrl.rs b/pac/atsaml22j/src/tc0/count8/dbgctrl.rs new file mode 100644 index 000000000000..271f8aa633ac --- /dev/null +++ b/pac/atsaml22j/src/tc0/count8/dbgctrl.rs @@ -0,0 +1,80 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Run During Debug"] +pub type DBGRUN_R = crate::BitReader; +#[doc = "Field `DBGRUN` writer - Run During Debug"] +pub type DBGRUN_W<'a, const O: u8> = crate::BitWriter<'a, u8, DBGCTRL_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Run During Debug"] + #[inline(always)] + #[must_use] + pub fn dbgrun(&mut self) -> DBGRUN_W<0> { + DBGRUN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tc0/count8/drvctrl.rs b/pac/atsaml22j/src/tc0/count8/drvctrl.rs new file mode 100644 index 000000000000..b6e499c1e0fe --- /dev/null +++ b/pac/atsaml22j/src/tc0/count8/drvctrl.rs @@ -0,0 +1,95 @@ +#[doc = "Register `DRVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DRVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `INVEN0` reader - Output Waveform Invert Enable 0"] +pub type INVEN0_R = crate::BitReader; +#[doc = "Field `INVEN0` writer - Output Waveform Invert Enable 0"] +pub type INVEN0_W<'a, const O: u8> = crate::BitWriter<'a, u8, DRVCTRL_SPEC, bool, O>; +#[doc = "Field `INVEN1` reader - Output Waveform Invert Enable 1"] +pub type INVEN1_R = crate::BitReader; +#[doc = "Field `INVEN1` writer - Output Waveform Invert Enable 1"] +pub type INVEN1_W<'a, const O: u8> = crate::BitWriter<'a, u8, DRVCTRL_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Output Waveform Invert Enable 0"] + #[inline(always)] + pub fn inven0(&self) -> INVEN0_R { + INVEN0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Output Waveform Invert Enable 1"] + #[inline(always)] + pub fn inven1(&self) -> INVEN1_R { + INVEN1_R::new(((self.bits >> 1) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Output Waveform Invert Enable 0"] + #[inline(always)] + #[must_use] + pub fn inven0(&mut self) -> INVEN0_W<0> { + INVEN0_W::new(self) + } + #[doc = "Bit 1 - Output Waveform Invert Enable 1"] + #[inline(always)] + #[must_use] + pub fn inven1(&mut self) -> INVEN1_W<1> { + INVEN1_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control C\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [drvctrl](index.html) module"] +pub struct DRVCTRL_SPEC; +impl crate::RegisterSpec for DRVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [drvctrl::R](R) reader structure"] +impl crate::Readable for DRVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [drvctrl::W](W) writer structure"] +impl crate::Writable for DRVCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DRVCTRL to value 0"] +impl crate::Resettable for DRVCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tc0/count8/evctrl.rs b/pac/atsaml22j/src/tc0/count8/evctrl.rs new file mode 100644 index 000000000000..9238d1566f09 --- /dev/null +++ b/pac/atsaml22j/src/tc0/count8/evctrl.rs @@ -0,0 +1,282 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVACT` reader - Event Action"] +pub type EVACT_R = crate::FieldReader; +#[doc = "Event Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum EVACTSELECT_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Start, restart or retrigger TC on event"] + RETRIGGER = 1, + #[doc = "2: Count on event"] + COUNT = 2, + #[doc = "3: Start TC on event"] + START = 3, + #[doc = "4: Time stamp capture"] + STAMP = 4, + #[doc = "5: Period catured in CC0, pulse width in CC1"] + PPW = 5, + #[doc = "6: Period catured in CC1, pulse width in CC0"] + PWP = 6, + #[doc = "7: Pulse width capture"] + PW = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACTSELECT_A) -> Self { + variant as _ + } +} +impl EVACT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVACTSELECT_A { + match self.bits { + 0 => EVACTSELECT_A::OFF, + 1 => EVACTSELECT_A::RETRIGGER, + 2 => EVACTSELECT_A::COUNT, + 3 => EVACTSELECT_A::START, + 4 => EVACTSELECT_A::STAMP, + 5 => EVACTSELECT_A::PPW, + 6 => EVACTSELECT_A::PWP, + 7 => EVACTSELECT_A::PW, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == EVACTSELECT_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + *self == EVACTSELECT_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `COUNT`"] + #[inline(always)] + pub fn is_count(&self) -> bool { + *self == EVACTSELECT_A::COUNT + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + *self == EVACTSELECT_A::START + } + #[doc = "Checks if the value of the field is `STAMP`"] + #[inline(always)] + pub fn is_stamp(&self) -> bool { + *self == EVACTSELECT_A::STAMP + } + #[doc = "Checks if the value of the field is `PPW`"] + #[inline(always)] + pub fn is_ppw(&self) -> bool { + *self == EVACTSELECT_A::PPW + } + #[doc = "Checks if the value of the field is `PWP`"] + #[inline(always)] + pub fn is_pwp(&self) -> bool { + *self == EVACTSELECT_A::PWP + } + #[doc = "Checks if the value of the field is `PW`"] + #[inline(always)] + pub fn is_pw(&self) -> bool { + *self == EVACTSELECT_A::PW + } +} +#[doc = "Field `EVACT` writer - Event Action"] +pub type EVACT_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u16, EVCTRL_SPEC, u8, EVACTSELECT_A, 3, O>; +impl<'a, const O: u8> EVACT_W<'a, O> { + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACTSELECT_A::OFF) + } + #[doc = "Start, restart or retrigger TC on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACTSELECT_A::RETRIGGER) + } + #[doc = "Count on event"] + #[inline(always)] + pub fn count(self) -> &'a mut W { + self.variant(EVACTSELECT_A::COUNT) + } + #[doc = "Start TC on event"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(EVACTSELECT_A::START) + } + #[doc = "Time stamp capture"] + #[inline(always)] + pub fn stamp(self) -> &'a mut W { + self.variant(EVACTSELECT_A::STAMP) + } + #[doc = "Period catured in CC0, pulse width in CC1"] + #[inline(always)] + pub fn ppw(self) -> &'a mut W { + self.variant(EVACTSELECT_A::PPW) + } + #[doc = "Period catured in CC1, pulse width in CC0"] + #[inline(always)] + pub fn pwp(self) -> &'a mut W { + self.variant(EVACTSELECT_A::PWP) + } + #[doc = "Pulse width capture"] + #[inline(always)] + pub fn pw(self) -> &'a mut W { + self.variant(EVACTSELECT_A::PW) + } +} +#[doc = "Field `TCINV` reader - TC Event Input Polarity"] +pub type TCINV_R = crate::BitReader; +#[doc = "Field `TCINV` writer - TC Event Input Polarity"] +pub type TCINV_W<'a, const O: u8> = crate::BitWriter<'a, u16, EVCTRL_SPEC, bool, O>; +#[doc = "Field `TCEI` reader - TC Event Enable"] +pub type TCEI_R = crate::BitReader; +#[doc = "Field `TCEI` writer - TC Event Enable"] +pub type TCEI_W<'a, const O: u8> = crate::BitWriter<'a, u16, EVCTRL_SPEC, bool, O>; +#[doc = "Field `OVFEO` reader - Event Output Enable"] +pub type OVFEO_R = crate::BitReader; +#[doc = "Field `OVFEO` writer - Event Output Enable"] +pub type OVFEO_W<'a, const O: u8> = crate::BitWriter<'a, u16, EVCTRL_SPEC, bool, O>; +#[doc = "Field `MCEO0` reader - MC Event Output Enable 0"] +pub type MCEO0_R = crate::BitReader; +#[doc = "Field `MCEO0` writer - MC Event Output Enable 0"] +pub type MCEO0_W<'a, const O: u8> = crate::BitWriter<'a, u16, EVCTRL_SPEC, bool, O>; +#[doc = "Field `MCEO1` reader - MC Event Output Enable 1"] +pub type MCEO1_R = crate::BitReader; +#[doc = "Field `MCEO1` writer - MC Event Output Enable 1"] +pub type MCEO1_W<'a, const O: u8> = crate::BitWriter<'a, u16, EVCTRL_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + pub fn evact(&self) -> EVACT_R { + EVACT_R::new((self.bits & 7) as u8) + } + #[doc = "Bit 4 - TC Event Input Polarity"] + #[inline(always)] + pub fn tcinv(&self) -> TCINV_R { + TCINV_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - TC Event Enable"] + #[inline(always)] + pub fn tcei(&self) -> TCEI_R { + TCEI_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 8 - Event Output Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 12 - MC Event Output Enable 0"] + #[inline(always)] + pub fn mceo0(&self) -> MCEO0_R { + MCEO0_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - MC Event Output Enable 1"] + #[inline(always)] + pub fn mceo1(&self) -> MCEO1_R { + MCEO1_R::new(((self.bits >> 13) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Event Action"] + #[inline(always)] + #[must_use] + pub fn evact(&mut self) -> EVACT_W<0> { + EVACT_W::new(self) + } + #[doc = "Bit 4 - TC Event Input Polarity"] + #[inline(always)] + #[must_use] + pub fn tcinv(&mut self) -> TCINV_W<4> { + TCINV_W::new(self) + } + #[doc = "Bit 5 - TC Event Enable"] + #[inline(always)] + #[must_use] + pub fn tcei(&mut self) -> TCEI_W<5> { + TCEI_W::new(self) + } + #[doc = "Bit 8 - Event Output Enable"] + #[inline(always)] + #[must_use] + pub fn ovfeo(&mut self) -> OVFEO_W<8> { + OVFEO_W::new(self) + } + #[doc = "Bit 12 - MC Event Output Enable 0"] + #[inline(always)] + #[must_use] + pub fn mceo0(&mut self) -> MCEO0_W<12> { + MCEO0_W::new(self) + } + #[doc = "Bit 13 - MC Event Output Enable 1"] + #[inline(always)] + #[must_use] + pub fn mceo1(&mut self) -> MCEO1_W<13> { + MCEO1_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tc0/count8/intenclr.rs b/pac/atsaml22j/src/tc0/count8/intenclr.rs new file mode 100644 index 000000000000..940e1f9474a1 --- /dev/null +++ b/pac/atsaml22j/src/tc0/count8/intenclr.rs @@ -0,0 +1,125 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Disable"] +pub type OVF_R = crate::BitReader; +#[doc = "Field `OVF` writer - OVF Interrupt Disable"] +pub type OVF_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>; +#[doc = "Field `ERR` reader - ERR Interrupt Disable"] +pub type ERR_R = crate::BitReader; +#[doc = "Field `ERR` writer - ERR Interrupt Disable"] +pub type ERR_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>; +#[doc = "Field `MC0` reader - MC Interrupt Disable 0"] +pub type MC0_R = crate::BitReader; +#[doc = "Field `MC0` writer - MC Interrupt Disable 0"] +pub type MC0_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>; +#[doc = "Field `MC1` reader - MC Interrupt Disable 1"] +pub type MC1_R = crate::BitReader; +#[doc = "Field `MC1` writer - MC Interrupt Disable 1"] +pub type MC1_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - OVF Interrupt Disable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Disable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 4 - MC Interrupt Disable 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - MC Interrupt Disable 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Disable"] + #[inline(always)] + #[must_use] + pub fn ovf(&mut self) -> OVF_W<0> { + OVF_W::new(self) + } + #[doc = "Bit 1 - ERR Interrupt Disable"] + #[inline(always)] + #[must_use] + pub fn err(&mut self) -> ERR_W<1> { + ERR_W::new(self) + } + #[doc = "Bit 4 - MC Interrupt Disable 0"] + #[inline(always)] + #[must_use] + pub fn mc0(&mut self) -> MC0_W<4> { + MC0_W::new(self) + } + #[doc = "Bit 5 - MC Interrupt Disable 1"] + #[inline(always)] + #[must_use] + pub fn mc1(&mut self) -> MC1_W<5> { + MC1_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tc0/count8/intenset.rs b/pac/atsaml22j/src/tc0/count8/intenset.rs new file mode 100644 index 000000000000..308be3696676 --- /dev/null +++ b/pac/atsaml22j/src/tc0/count8/intenset.rs @@ -0,0 +1,125 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Enable"] +pub type OVF_R = crate::BitReader; +#[doc = "Field `OVF` writer - OVF Interrupt Enable"] +pub type OVF_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENSET_SPEC, bool, O>; +#[doc = "Field `ERR` reader - ERR Interrupt Enable"] +pub type ERR_R = crate::BitReader; +#[doc = "Field `ERR` writer - ERR Interrupt Enable"] +pub type ERR_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENSET_SPEC, bool, O>; +#[doc = "Field `MC0` reader - MC Interrupt Enable 0"] +pub type MC0_R = crate::BitReader; +#[doc = "Field `MC0` writer - MC Interrupt Enable 0"] +pub type MC0_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENSET_SPEC, bool, O>; +#[doc = "Field `MC1` reader - MC Interrupt Enable 1"] +pub type MC1_R = crate::BitReader; +#[doc = "Field `MC1` writer - MC Interrupt Enable 1"] +pub type MC1_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENSET_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - OVF Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 4 - MC Interrupt Enable 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - MC Interrupt Enable 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn ovf(&mut self) -> OVF_W<0> { + OVF_W::new(self) + } + #[doc = "Bit 1 - ERR Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn err(&mut self) -> ERR_W<1> { + ERR_W::new(self) + } + #[doc = "Bit 4 - MC Interrupt Enable 0"] + #[inline(always)] + #[must_use] + pub fn mc0(&mut self) -> MC0_W<4> { + MC0_W::new(self) + } + #[doc = "Bit 5 - MC Interrupt Enable 1"] + #[inline(always)] + #[must_use] + pub fn mc1(&mut self) -> MC1_W<5> { + MC1_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tc0/count8/intflag.rs b/pac/atsaml22j/src/tc0/count8/intflag.rs new file mode 100644 index 000000000000..e168641a7cfd --- /dev/null +++ b/pac/atsaml22j/src/tc0/count8/intflag.rs @@ -0,0 +1,125 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - OVF Interrupt Flag"] +pub type OVF_R = crate::BitReader; +#[doc = "Field `OVF` writer - OVF Interrupt Flag"] +pub type OVF_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTFLAG_SPEC, bool, O>; +#[doc = "Field `ERR` reader - ERR Interrupt Flag"] +pub type ERR_R = crate::BitReader; +#[doc = "Field `ERR` writer - ERR Interrupt Flag"] +pub type ERR_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTFLAG_SPEC, bool, O>; +#[doc = "Field `MC0` reader - MC Interrupt Flag 0"] +pub type MC0_R = crate::BitReader; +#[doc = "Field `MC0` writer - MC Interrupt Flag 0"] +pub type MC0_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTFLAG_SPEC, bool, O>; +#[doc = "Field `MC1` reader - MC Interrupt Flag 1"] +pub type MC1_R = crate::BitReader; +#[doc = "Field `MC1` writer - MC Interrupt Flag 1"] +pub type MC1_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTFLAG_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - OVF Interrupt Flag"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - ERR Interrupt Flag"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 4 - MC Interrupt Flag 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - MC Interrupt Flag 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 5) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - OVF Interrupt Flag"] + #[inline(always)] + #[must_use] + pub fn ovf(&mut self) -> OVF_W<0> { + OVF_W::new(self) + } + #[doc = "Bit 1 - ERR Interrupt Flag"] + #[inline(always)] + #[must_use] + pub fn err(&mut self) -> ERR_W<1> { + ERR_W::new(self) + } + #[doc = "Bit 4 - MC Interrupt Flag 0"] + #[inline(always)] + #[must_use] + pub fn mc0(&mut self) -> MC0_W<4> { + MC0_W::new(self) + } + #[doc = "Bit 5 - MC Interrupt Flag 1"] + #[inline(always)] + #[must_use] + pub fn mc1(&mut self) -> MC1_W<5> { + MC1_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tc0/count8/per.rs b/pac/atsaml22j/src/tc0/count8/per.rs new file mode 100644 index 000000000000..6690d440d1b1 --- /dev/null +++ b/pac/atsaml22j/src/tc0/count8/per.rs @@ -0,0 +1,80 @@ +#[doc = "Register `PER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER` reader - Period Value"] +pub type PER_R = crate::FieldReader; +#[doc = "Field `PER` writer - Period Value"] +pub type PER_W<'a, const O: u8> = crate::FieldWriter<'a, u8, PER_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:7 - Period Value"] + #[inline(always)] + #[must_use] + pub fn per(&mut self) -> PER_W<0> { + PER_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT8 Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per](index.html) module"] +pub struct PER_SPEC; +impl crate::RegisterSpec for PER_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [per::R](R) reader structure"] +impl crate::Readable for PER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per::W](W) writer structure"] +impl crate::Writable for PER_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PER to value 0xff"] +impl crate::Resettable for PER_SPEC { + const RESET_VALUE: Self::Ux = 0xff; +} diff --git a/pac/atsaml22j/src/tc0/count8/perbuf.rs b/pac/atsaml22j/src/tc0/count8/perbuf.rs new file mode 100644 index 000000000000..a7dbdfd921aa --- /dev/null +++ b/pac/atsaml22j/src/tc0/count8/perbuf.rs @@ -0,0 +1,80 @@ +#[doc = "Register `PERBUF` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERBUF` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PERBUF` reader - Period Buffer Value"] +pub type PERBUF_R = crate::FieldReader; +#[doc = "Field `PERBUF` writer - Period Buffer Value"] +pub type PERBUF_W<'a, const O: u8> = crate::FieldWriter<'a, u8, PERBUF_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:7 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&self) -> PERBUF_R { + PERBUF_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:7 - Period Buffer Value"] + #[inline(always)] + #[must_use] + pub fn perbuf(&mut self) -> PERBUF_W<0> { + PERBUF_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "COUNT8 Period Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perbuf](index.html) module"] +pub struct PERBUF_SPEC; +impl crate::RegisterSpec for PERBUF_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [perbuf::R](R) reader structure"] +impl crate::Readable for PERBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perbuf::W](W) writer structure"] +impl crate::Writable for PERBUF_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PERBUF to value 0xff"] +impl crate::Resettable for PERBUF_SPEC { + const RESET_VALUE: Self::Ux = 0xff; +} diff --git a/pac/atsaml22j/src/tc0/count8/status.rs b/pac/atsaml22j/src/tc0/count8/status.rs new file mode 100644 index 000000000000..d970ceba0574 --- /dev/null +++ b/pac/atsaml22j/src/tc0/count8/status.rs @@ -0,0 +1,124 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STOP` reader - Stop Status Flag"] +pub type STOP_R = crate::BitReader; +#[doc = "Field `SLAVE` reader - Slave Status Flag"] +pub type SLAVE_R = crate::BitReader; +#[doc = "Field `PERBUFV` reader - Synchronization Busy Status"] +pub type PERBUFV_R = crate::BitReader; +#[doc = "Field `PERBUFV` writer - Synchronization Busy Status"] +pub type PERBUFV_W<'a, const O: u8> = crate::BitWriter<'a, u8, STATUS_SPEC, bool, O>; +#[doc = "Field `CCBUFV0` reader - Compare channel buffer 0 valid"] +pub type CCBUFV0_R = crate::BitReader; +#[doc = "Field `CCBUFV0` writer - Compare channel buffer 0 valid"] +pub type CCBUFV0_W<'a, const O: u8> = crate::BitWriter<'a, u8, STATUS_SPEC, bool, O>; +#[doc = "Field `CCBUFV1` reader - Compare channel buffer 1 valid"] +pub type CCBUFV1_R = crate::BitReader; +#[doc = "Field `CCBUFV1` writer - Compare channel buffer 1 valid"] +pub type CCBUFV1_W<'a, const O: u8> = crate::BitWriter<'a, u8, STATUS_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Stop Status Flag"] + #[inline(always)] + pub fn stop(&self) -> STOP_R { + STOP_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Slave Status Flag"] + #[inline(always)] + pub fn slave(&self) -> SLAVE_R { + SLAVE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 3 - Synchronization Busy Status"] + #[inline(always)] + pub fn perbufv(&self) -> PERBUFV_R { + PERBUFV_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Compare channel buffer 0 valid"] + #[inline(always)] + pub fn ccbufv0(&self) -> CCBUFV0_R { + CCBUFV0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Compare channel buffer 1 valid"] + #[inline(always)] + pub fn ccbufv1(&self) -> CCBUFV1_R { + CCBUFV1_R::new(((self.bits >> 5) & 1) != 0) + } +} +impl W { + #[doc = "Bit 3 - Synchronization Busy Status"] + #[inline(always)] + #[must_use] + pub fn perbufv(&mut self) -> PERBUFV_W<3> { + PERBUFV_W::new(self) + } + #[doc = "Bit 4 - Compare channel buffer 0 valid"] + #[inline(always)] + #[must_use] + pub fn ccbufv0(&mut self) -> CCBUFV0_W<4> { + CCBUFV0_W::new(self) + } + #[doc = "Bit 5 - Compare channel buffer 1 valid"] + #[inline(always)] + #[must_use] + pub fn ccbufv1(&mut self) -> CCBUFV1_W<5> { + CCBUFV1_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets STATUS to value 0x01"] +impl crate::Resettable for STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/pac/atsaml22j/src/tc0/count8/syncbusy.rs b/pac/atsaml22j/src/tc0/count8/syncbusy.rs new file mode 100644 index 000000000000..901c6571d922 --- /dev/null +++ b/pac/atsaml22j/src/tc0/count8/syncbusy.rs @@ -0,0 +1,86 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - swrst"] +pub type SWRST_R = crate::BitReader; +#[doc = "Field `ENABLE` reader - enable"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `CTRLB` reader - CTRLB"] +pub type CTRLB_R = crate::BitReader; +#[doc = "Field `STATUS` reader - STATUS"] +pub type STATUS_R = crate::BitReader; +#[doc = "Field `COUNT` reader - Counter"] +pub type COUNT_R = crate::BitReader; +#[doc = "Field `PER` reader - Period"] +pub type PER_R = crate::BitReader; +#[doc = "Field `CC0` reader - Compare Channel 0"] +pub type CC0_R = crate::BitReader; +#[doc = "Field `CC1` reader - Compare Channel 1"] +pub type CC1_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - swrst"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - CTRLB"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - STATUS"] + #[inline(always)] + pub fn status(&self) -> STATUS_R { + STATUS_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Counter"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Period"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Compare Channel 0"] + #[inline(always)] + pub fn cc0(&self) -> CC0_R { + CC0_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Compare Channel 1"] + #[inline(always)] + pub fn cc1(&self) -> CC1_R { + CC1_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[doc = "Synchronization Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tc0/count8/wave.rs b/pac/atsaml22j/src/tc0/count8/wave.rs new file mode 100644 index 000000000000..c6776ad1adeb --- /dev/null +++ b/pac/atsaml22j/src/tc0/count8/wave.rs @@ -0,0 +1,155 @@ +#[doc = "Register `WAVE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WAVE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WAVEGEN` reader - Waveform Generation Mode"] +pub type WAVEGEN_R = crate::FieldReader; +#[doc = "Waveform Generation Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum WAVEGENSELECT_A { + #[doc = "0: Normal frequency"] + NFRQ = 0, + #[doc = "1: Match frequency"] + MFRQ = 1, + #[doc = "2: Normal PWM"] + NPWM = 2, + #[doc = "3: Match PWM"] + MPWM = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WAVEGENSELECT_A) -> Self { + variant as _ + } +} +impl WAVEGEN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> WAVEGENSELECT_A { + match self.bits { + 0 => WAVEGENSELECT_A::NFRQ, + 1 => WAVEGENSELECT_A::MFRQ, + 2 => WAVEGENSELECT_A::NPWM, + 3 => WAVEGENSELECT_A::MPWM, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NFRQ`"] + #[inline(always)] + pub fn is_nfrq(&self) -> bool { + *self == WAVEGENSELECT_A::NFRQ + } + #[doc = "Checks if the value of the field is `MFRQ`"] + #[inline(always)] + pub fn is_mfrq(&self) -> bool { + *self == WAVEGENSELECT_A::MFRQ + } + #[doc = "Checks if the value of the field is `NPWM`"] + #[inline(always)] + pub fn is_npwm(&self) -> bool { + *self == WAVEGENSELECT_A::NPWM + } + #[doc = "Checks if the value of the field is `MPWM`"] + #[inline(always)] + pub fn is_mpwm(&self) -> bool { + *self == WAVEGENSELECT_A::MPWM + } +} +#[doc = "Field `WAVEGEN` writer - Waveform Generation Mode"] +pub type WAVEGEN_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u8, WAVE_SPEC, u8, WAVEGENSELECT_A, 2, O>; +impl<'a, const O: u8> WAVEGEN_W<'a, O> { + #[doc = "Normal frequency"] + #[inline(always)] + pub fn nfrq(self) -> &'a mut W { + self.variant(WAVEGENSELECT_A::NFRQ) + } + #[doc = "Match frequency"] + #[inline(always)] + pub fn mfrq(self) -> &'a mut W { + self.variant(WAVEGENSELECT_A::MFRQ) + } + #[doc = "Normal PWM"] + #[inline(always)] + pub fn npwm(self) -> &'a mut W { + self.variant(WAVEGENSELECT_A::NPWM) + } + #[doc = "Match PWM"] + #[inline(always)] + pub fn mpwm(self) -> &'a mut W { + self.variant(WAVEGENSELECT_A::MPWM) + } +} +impl R { + #[doc = "Bits 0:1 - Waveform Generation Mode"] + #[inline(always)] + pub fn wavegen(&self) -> WAVEGEN_R { + WAVEGEN_R::new(self.bits & 3) + } +} +impl W { + #[doc = "Bits 0:1 - Waveform Generation Mode"] + #[inline(always)] + #[must_use] + pub fn wavegen(&mut self) -> WAVEGEN_W<0> { + WAVEGEN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Waveform Generation Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wave](index.html) module"] +pub struct WAVE_SPEC; +impl crate::RegisterSpec for WAVE_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [wave::R](R) reader structure"] +impl crate::Readable for WAVE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wave::W](W) writer structure"] +impl crate::Writable for WAVE_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets WAVE to value 0"] +impl crate::Resettable for WAVE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tcc0.rs b/pac/atsaml22j/src/tcc0.rs new file mode 100644 index 000000000000..de55541c4b0d --- /dev/null +++ b/pac/atsaml22j/src/tcc0.rs @@ -0,0 +1,299 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: CTRLA, + #[doc = "0x04 - Control B Clear"] + pub ctrlbclr: CTRLBCLR, + #[doc = "0x05 - Control B Set"] + pub ctrlbset: CTRLBSET, + _reserved3: [u8; 0x02], + #[doc = "0x08 - Synchronization Busy"] + pub syncbusy: SYNCBUSY, + #[doc = "0x0c - Recoverable Fault A Configuration"] + pub fctrla: FCTRLA, + #[doc = "0x10 - Recoverable Fault B Configuration"] + pub fctrlb: FCTRLB, + #[doc = "0x14 - Waveform Extension Configuration"] + pub wexctrl: WEXCTRL, + #[doc = "0x18 - Driver Control"] + pub drvctrl: DRVCTRL, + _reserved8: [u8; 0x02], + #[doc = "0x1e - Debug Control"] + pub dbgctrl: DBGCTRL, + _reserved9: [u8; 0x01], + #[doc = "0x20 - Event Control"] + pub evctrl: EVCTRL, + #[doc = "0x24 - Interrupt Enable Clear"] + pub intenclr: INTENCLR, + #[doc = "0x28 - Interrupt Enable Set"] + pub intenset: INTENSET, + #[doc = "0x2c - Interrupt Flag Status and Clear"] + pub intflag: INTFLAG, + #[doc = "0x30 - Status"] + pub status: STATUS, + _reserved_14_count: [u8; 0x04], + #[doc = "0x38 - Pattern"] + pub patt: PATT, + _reserved16: [u8; 0x02], + #[doc = "0x3c - Waveform Control"] + pub wave: WAVE, + _reserved_17_per: [u8; 0x04], + _reserved_18_cc: [u8; 0x10], + _reserved19: [u8; 0x10], + #[doc = "0x64 - Pattern Buffer"] + pub pattbuf: PATTBUF, + _reserved20: [u8; 0x06], + _reserved_20_perbuf: [u8; 0x04], + _reserved_21_ccbuf: [u8; 0x10], +} +impl RegisterBlock { + #[doc = "0x34 - Count"] + #[inline(always)] + pub const fn count_dith6(&self) -> &COUNT_DITH6 { + unsafe { &*(self as *const Self).cast::().add(52usize).cast() } + } + #[doc = "0x34 - Count"] + #[inline(always)] + pub const fn count_dith5(&self) -> &COUNT_DITH5 { + unsafe { &*(self as *const Self).cast::().add(52usize).cast() } + } + #[doc = "0x34 - Count"] + #[inline(always)] + pub const fn count_dith4(&self) -> &COUNT_DITH4 { + unsafe { &*(self as *const Self).cast::().add(52usize).cast() } + } + #[doc = "0x34 - Count"] + #[inline(always)] + pub const fn count(&self) -> &COUNT { + unsafe { &*(self as *const Self).cast::().add(52usize).cast() } + } + #[doc = "0x40 - Period"] + #[inline(always)] + pub const fn per_dith6(&self) -> &PER_DITH6 { + unsafe { &*(self as *const Self).cast::().add(64usize).cast() } + } + #[doc = "0x40 - Period"] + #[inline(always)] + pub const fn per_dith5(&self) -> &PER_DITH5 { + unsafe { &*(self as *const Self).cast::().add(64usize).cast() } + } + #[doc = "0x40 - Period"] + #[inline(always)] + pub const fn per_dith4(&self) -> &PER_DITH4 { + unsafe { &*(self as *const Self).cast::().add(64usize).cast() } + } + #[doc = "0x40 - Period"] + #[inline(always)] + pub const fn per(&self) -> &PER { + unsafe { &*(self as *const Self).cast::().add(64usize).cast() } + } + #[doc = "0x44..0x54 - Compare and Capture"] + #[inline(always)] + pub const fn cc_dith6(&self) -> &[CC_DITH6; 4] { + unsafe { &*(self as *const Self).cast::().add(68usize).cast() } + } + #[doc = "0x44..0x54 - Compare and Capture"] + #[inline(always)] + pub const fn cc_dith5(&self) -> &[CC_DITH5; 4] { + unsafe { &*(self as *const Self).cast::().add(68usize).cast() } + } + #[doc = "0x44..0x54 - Compare and Capture"] + #[inline(always)] + pub const fn cc_dith4(&self) -> &[CC_DITH4; 4] { + unsafe { &*(self as *const Self).cast::().add(68usize).cast() } + } + #[doc = "0x44..0x54 - Compare and Capture"] + #[inline(always)] + pub const fn cc(&self) -> &[CC; 4] { + unsafe { &*(self as *const Self).cast::().add(68usize).cast() } + } + #[doc = "0x6c - Period Buffer"] + #[inline(always)] + pub const fn perbuf_dith6(&self) -> &PERBUF_DITH6 { + unsafe { &*(self as *const Self).cast::().add(108usize).cast() } + } + #[doc = "0x6c - Period Buffer"] + #[inline(always)] + pub const fn perbuf_dith5(&self) -> &PERBUF_DITH5 { + unsafe { &*(self as *const Self).cast::().add(108usize).cast() } + } + #[doc = "0x6c - Period Buffer"] + #[inline(always)] + pub const fn perbuf_dith4(&self) -> &PERBUF_DITH4 { + unsafe { &*(self as *const Self).cast::().add(108usize).cast() } + } + #[doc = "0x6c - Period Buffer"] + #[inline(always)] + pub const fn perbuf(&self) -> &PERBUF { + unsafe { &*(self as *const Self).cast::().add(108usize).cast() } + } + #[doc = "0x70..0x80 - Compare and Capture Buffer"] + #[inline(always)] + pub const fn ccbuf_dith6(&self) -> &[CCBUF_DITH6; 4] { + unsafe { &*(self as *const Self).cast::().add(112usize).cast() } + } + #[doc = "0x70..0x80 - Compare and Capture Buffer"] + #[inline(always)] + pub const fn ccbuf_dith5(&self) -> &[CCBUF_DITH5; 4] { + unsafe { &*(self as *const Self).cast::().add(112usize).cast() } + } + #[doc = "0x70..0x80 - Compare and Capture Buffer"] + #[inline(always)] + pub const fn ccbuf_dith4(&self) -> &[CCBUF_DITH4; 4] { + unsafe { &*(self as *const Self).cast::().add(112usize).cast() } + } + #[doc = "0x70..0x80 - Compare and Capture Buffer"] + #[inline(always)] + pub const fn ccbuf(&self) -> &[CCBUF; 4] { + unsafe { &*(self as *const Self).cast::().add(112usize).cast() } + } +} +#[doc = "CTRLA (rw) register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "CTRLBCLR (rw) register accessor: an alias for `Reg`"] +pub type CTRLBCLR = crate::Reg; +#[doc = "Control B Clear"] +pub mod ctrlbclr; +#[doc = "CTRLBSET (rw) register accessor: an alias for `Reg`"] +pub type CTRLBSET = crate::Reg; +#[doc = "Control B Set"] +pub mod ctrlbset; +#[doc = "SYNCBUSY (r) register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; +#[doc = "FCTRLA (rw) register accessor: an alias for `Reg`"] +pub type FCTRLA = crate::Reg; +#[doc = "Recoverable Fault A Configuration"] +pub mod fctrla; +#[doc = "FCTRLB (rw) register accessor: an alias for `Reg`"] +pub type FCTRLB = crate::Reg; +#[doc = "Recoverable Fault B Configuration"] +pub mod fctrlb; +#[doc = "WEXCTRL (rw) register accessor: an alias for `Reg`"] +pub type WEXCTRL = crate::Reg; +#[doc = "Waveform Extension Configuration"] +pub mod wexctrl; +#[doc = "DRVCTRL (rw) register accessor: an alias for `Reg`"] +pub type DRVCTRL = crate::Reg; +#[doc = "Driver Control"] +pub mod drvctrl; +#[doc = "DBGCTRL (rw) register accessor: an alias for `Reg`"] +pub type DBGCTRL = crate::Reg; +#[doc = "Debug Control"] +pub mod dbgctrl; +#[doc = "EVCTRL (rw) register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR (rw) register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET (rw) register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG (rw) register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "STATUS (rw) register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "Status"] +pub mod status; +#[doc = "COUNT (rw) register accessor: an alias for `Reg`"] +pub type COUNT = crate::Reg; +#[doc = "Count"] +pub mod count; +#[doc = "COUNT_DITH4 (rw) register accessor: an alias for `Reg`"] +pub type COUNT_DITH4 = crate::Reg; +#[doc = "Count"] +pub mod count_dith4; +#[doc = "COUNT_DITH5 (rw) register accessor: an alias for `Reg`"] +pub type COUNT_DITH5 = crate::Reg; +#[doc = "Count"] +pub mod count_dith5; +#[doc = "COUNT_DITH6 (rw) register accessor: an alias for `Reg`"] +pub type COUNT_DITH6 = crate::Reg; +#[doc = "Count"] +pub mod count_dith6; +#[doc = "PATT (rw) register accessor: an alias for `Reg`"] +pub type PATT = crate::Reg; +#[doc = "Pattern"] +pub mod patt; +#[doc = "WAVE (rw) register accessor: an alias for `Reg`"] +pub type WAVE = crate::Reg; +#[doc = "Waveform Control"] +pub mod wave; +#[doc = "PER (rw) register accessor: an alias for `Reg`"] +pub type PER = crate::Reg; +#[doc = "Period"] +pub mod per; +#[doc = "PER_DITH4 (rw) register accessor: an alias for `Reg`"] +pub type PER_DITH4 = crate::Reg; +#[doc = "Period"] +pub mod per_dith4; +#[doc = "PER_DITH5 (rw) register accessor: an alias for `Reg`"] +pub type PER_DITH5 = crate::Reg; +#[doc = "Period"] +pub mod per_dith5; +#[doc = "PER_DITH6 (rw) register accessor: an alias for `Reg`"] +pub type PER_DITH6 = crate::Reg; +#[doc = "Period"] +pub mod per_dith6; +#[doc = "CC (rw) register accessor: an alias for `Reg`"] +pub type CC = crate::Reg; +#[doc = "Compare and Capture"] +pub mod cc; +#[doc = "CC_DITH4 (rw) register accessor: an alias for `Reg`"] +pub type CC_DITH4 = crate::Reg; +#[doc = "Compare and Capture"] +pub mod cc_dith4; +#[doc = "CC_DITH5 (rw) register accessor: an alias for `Reg`"] +pub type CC_DITH5 = crate::Reg; +#[doc = "Compare and Capture"] +pub mod cc_dith5; +#[doc = "CC_DITH6 (rw) register accessor: an alias for `Reg`"] +pub type CC_DITH6 = crate::Reg; +#[doc = "Compare and Capture"] +pub mod cc_dith6; +#[doc = "PATTBUF (rw) register accessor: an alias for `Reg`"] +pub type PATTBUF = crate::Reg; +#[doc = "Pattern Buffer"] +pub mod pattbuf; +#[doc = "PERBUF (rw) register accessor: an alias for `Reg`"] +pub type PERBUF = crate::Reg; +#[doc = "Period Buffer"] +pub mod perbuf; +#[doc = "PERBUF_DITH4 (rw) register accessor: an alias for `Reg`"] +pub type PERBUF_DITH4 = crate::Reg; +#[doc = "Period Buffer"] +pub mod perbuf_dith4; +#[doc = "PERBUF_DITH5 (rw) register accessor: an alias for `Reg`"] +pub type PERBUF_DITH5 = crate::Reg; +#[doc = "Period Buffer"] +pub mod perbuf_dith5; +#[doc = "PERBUF_DITH6 (rw) register accessor: an alias for `Reg`"] +pub type PERBUF_DITH6 = crate::Reg; +#[doc = "Period Buffer"] +pub mod perbuf_dith6; +#[doc = "CCBUF (rw) register accessor: an alias for `Reg`"] +pub type CCBUF = crate::Reg; +#[doc = "Compare and Capture Buffer"] +pub mod ccbuf; +#[doc = "CCBUF_DITH4 (rw) register accessor: an alias for `Reg`"] +pub type CCBUF_DITH4 = crate::Reg; +#[doc = "Compare and Capture Buffer"] +pub mod ccbuf_dith4; +#[doc = "CCBUF_DITH5 (rw) register accessor: an alias for `Reg`"] +pub type CCBUF_DITH5 = crate::Reg; +#[doc = "Compare and Capture Buffer"] +pub mod ccbuf_dith5; +#[doc = "CCBUF_DITH6 (rw) register accessor: an alias for `Reg`"] +pub type CCBUF_DITH6 = crate::Reg; +#[doc = "Compare and Capture Buffer"] +pub mod ccbuf_dith6; diff --git a/pac/atsaml22j/src/tcc0/cc.rs b/pac/atsaml22j/src/tcc0/cc.rs new file mode 100644 index 000000000000..fbdf98b62cf5 --- /dev/null +++ b/pac/atsaml22j/src/tcc0/cc.rs @@ -0,0 +1,80 @@ +#[doc = "Register `CC%s` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC%s` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CC` reader - Channel Compare/Capture Value"] +pub type CC_R = crate::FieldReader; +#[doc = "Field `CC` writer - Channel Compare/Capture Value"] +pub type CC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CC_SPEC, u32, u32, 24, O>; +impl R { + #[doc = "Bits 0:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new(self.bits & 0x00ff_ffff) + } +} +impl W { + #[doc = "Bits 0:23 - Channel Compare/Capture Value"] + #[inline(always)] + #[must_use] + pub fn cc(&mut self) -> CC_W<0> { + CC_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc](index.html) module"] +pub struct CC_SPEC; +impl crate::RegisterSpec for CC_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc::R](R) reader structure"] +impl crate::Readable for CC_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc::W](W) writer structure"] +impl crate::Writable for CC_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CC%s to value 0"] +impl crate::Resettable for CC_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tcc0/cc_dith4.rs b/pac/atsaml22j/src/tcc0/cc_dith4.rs new file mode 100644 index 000000000000..cc7237653ff7 --- /dev/null +++ b/pac/atsaml22j/src/tcc0/cc_dith4.rs @@ -0,0 +1,95 @@ +#[doc = "Register `CC%s_DITH4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC%s_DITH4` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHER` reader - Dithering Cycle Number"] +pub type DITHER_R = crate::FieldReader; +#[doc = "Field `DITHER` writer - Dithering Cycle Number"] +pub type DITHER_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CC_DITH4_SPEC, u8, u8, 4, O>; +#[doc = "Field `CC` reader - Channel Compare/Capture Value"] +pub type CC_R = crate::FieldReader; +#[doc = "Field `CC` writer - Channel Compare/Capture Value"] +pub type CC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CC_DITH4_SPEC, u32, u32, 20, O>; +impl R { + #[doc = "Bits 0:3 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&self) -> DITHER_R { + DITHER_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new((self.bits >> 4) & 0x000f_ffff) + } +} +impl W { + #[doc = "Bits 0:3 - Dithering Cycle Number"] + #[inline(always)] + #[must_use] + pub fn dither(&mut self) -> DITHER_W<0> { + DITHER_W::new(self) + } + #[doc = "Bits 4:23 - Channel Compare/Capture Value"] + #[inline(always)] + #[must_use] + pub fn cc(&mut self) -> CC_W<4> { + CC_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc_dith4](index.html) module"] +pub struct CC_DITH4_SPEC; +impl crate::RegisterSpec for CC_DITH4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc_dith4::R](R) reader structure"] +impl crate::Readable for CC_DITH4_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc_dith4::W](W) writer structure"] +impl crate::Writable for CC_DITH4_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CC%s_DITH4 to value 0"] +impl crate::Resettable for CC_DITH4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tcc0/cc_dith5.rs b/pac/atsaml22j/src/tcc0/cc_dith5.rs new file mode 100644 index 000000000000..19665efa9c02 --- /dev/null +++ b/pac/atsaml22j/src/tcc0/cc_dith5.rs @@ -0,0 +1,95 @@ +#[doc = "Register `CC%s_DITH5` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC%s_DITH5` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHER` reader - Dithering Cycle Number"] +pub type DITHER_R = crate::FieldReader; +#[doc = "Field `DITHER` writer - Dithering Cycle Number"] +pub type DITHER_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CC_DITH5_SPEC, u8, u8, 5, O>; +#[doc = "Field `CC` reader - Channel Compare/Capture Value"] +pub type CC_R = crate::FieldReader; +#[doc = "Field `CC` writer - Channel Compare/Capture Value"] +pub type CC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CC_DITH5_SPEC, u32, u32, 19, O>; +impl R { + #[doc = "Bits 0:4 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&self) -> DITHER_R { + DITHER_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new((self.bits >> 5) & 0x0007_ffff) + } +} +impl W { + #[doc = "Bits 0:4 - Dithering Cycle Number"] + #[inline(always)] + #[must_use] + pub fn dither(&mut self) -> DITHER_W<0> { + DITHER_W::new(self) + } + #[doc = "Bits 5:23 - Channel Compare/Capture Value"] + #[inline(always)] + #[must_use] + pub fn cc(&mut self) -> CC_W<5> { + CC_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc_dith5](index.html) module"] +pub struct CC_DITH5_SPEC; +impl crate::RegisterSpec for CC_DITH5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc_dith5::R](R) reader structure"] +impl crate::Readable for CC_DITH5_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc_dith5::W](W) writer structure"] +impl crate::Writable for CC_DITH5_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CC%s_DITH5 to value 0"] +impl crate::Resettable for CC_DITH5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tcc0/cc_dith6.rs b/pac/atsaml22j/src/tcc0/cc_dith6.rs new file mode 100644 index 000000000000..341d852a2423 --- /dev/null +++ b/pac/atsaml22j/src/tcc0/cc_dith6.rs @@ -0,0 +1,95 @@ +#[doc = "Register `CC%s_DITH6` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CC%s_DITH6` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHER` reader - Dithering Cycle Number"] +pub type DITHER_R = crate::FieldReader; +#[doc = "Field `DITHER` writer - Dithering Cycle Number"] +pub type DITHER_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CC_DITH6_SPEC, u8, u8, 6, O>; +#[doc = "Field `CC` reader - Channel Compare/Capture Value"] +pub type CC_R = crate::FieldReader; +#[doc = "Field `CC` writer - Channel Compare/Capture Value"] +pub type CC_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CC_DITH6_SPEC, u32, u32, 18, O>; +impl R { + #[doc = "Bits 0:5 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&self) -> DITHER_R { + DITHER_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:23 - Channel Compare/Capture Value"] + #[inline(always)] + pub fn cc(&self) -> CC_R { + CC_R::new((self.bits >> 6) & 0x0003_ffff) + } +} +impl W { + #[doc = "Bits 0:5 - Dithering Cycle Number"] + #[inline(always)] + #[must_use] + pub fn dither(&mut self) -> DITHER_W<0> { + DITHER_W::new(self) + } + #[doc = "Bits 6:23 - Channel Compare/Capture Value"] + #[inline(always)] + #[must_use] + pub fn cc(&mut self) -> CC_W<6> { + CC_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cc_dith6](index.html) module"] +pub struct CC_DITH6_SPEC; +impl crate::RegisterSpec for CC_DITH6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [cc_dith6::R](R) reader structure"] +impl crate::Readable for CC_DITH6_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [cc_dith6::W](W) writer structure"] +impl crate::Writable for CC_DITH6_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CC%s_DITH6 to value 0"] +impl crate::Resettable for CC_DITH6_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tcc0/ccbuf.rs b/pac/atsaml22j/src/tcc0/ccbuf.rs new file mode 100644 index 000000000000..75d7008fdab3 --- /dev/null +++ b/pac/atsaml22j/src/tcc0/ccbuf.rs @@ -0,0 +1,80 @@ +#[doc = "Register `CCBUF%s` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF%s` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CCBUF` reader - Channel Compare/Capture Buffer Value"] +pub type CCBUF_R = crate::FieldReader; +#[doc = "Field `CCBUF` writer - Channel Compare/Capture Buffer Value"] +pub type CCBUF_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CCBUF_SPEC, u32, u32, 24, O>; +impl R { + #[doc = "Bits 0:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new(self.bits & 0x00ff_ffff) + } +} +impl W { + #[doc = "Bits 0:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + #[must_use] + pub fn ccbuf(&mut self) -> CCBUF_W<0> { + CCBUF_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf](index.html) module"] +pub struct CCBUF_SPEC; +impl crate::RegisterSpec for CCBUF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccbuf::R](R) reader structure"] +impl crate::Readable for CCBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf::W](W) writer structure"] +impl crate::Writable for CCBUF_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CCBUF%s to value 0"] +impl crate::Resettable for CCBUF_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tcc0/ccbuf_dith4.rs b/pac/atsaml22j/src/tcc0/ccbuf_dith4.rs new file mode 100644 index 000000000000..f37141ddb1b5 --- /dev/null +++ b/pac/atsaml22j/src/tcc0/ccbuf_dith4.rs @@ -0,0 +1,96 @@ +#[doc = "Register `CCBUF%s_DITH4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF%s_DITH4` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CCBUF` reader - Channel Compare/Capture Buffer Value"] +pub type CCBUF_R = crate::FieldReader; +#[doc = "Field `CCBUF` writer - Channel Compare/Capture Buffer Value"] +pub type CCBUF_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CCBUF_DITH4_SPEC, u8, u8, 4, O>; +#[doc = "Field `DITHERBUF` reader - Dithering Buffer Cycle Number"] +pub type DITHERBUF_R = crate::FieldReader; +#[doc = "Field `DITHERBUF` writer - Dithering Buffer Cycle Number"] +pub type DITHERBUF_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, CCBUF_DITH4_SPEC, u32, u32, 20, O>; +impl R { + #[doc = "Bits 0:3 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:23 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&self) -> DITHERBUF_R { + DITHERBUF_R::new((self.bits >> 4) & 0x000f_ffff) + } +} +impl W { + #[doc = "Bits 0:3 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + #[must_use] + pub fn ccbuf(&mut self) -> CCBUF_W<0> { + CCBUF_W::new(self) + } + #[doc = "Bits 4:23 - Dithering Buffer Cycle Number"] + #[inline(always)] + #[must_use] + pub fn ditherbuf(&mut self) -> DITHERBUF_W<4> { + DITHERBUF_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf_dith4](index.html) module"] +pub struct CCBUF_DITH4_SPEC; +impl crate::RegisterSpec for CCBUF_DITH4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccbuf_dith4::R](R) reader structure"] +impl crate::Readable for CCBUF_DITH4_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf_dith4::W](W) writer structure"] +impl crate::Writable for CCBUF_DITH4_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CCBUF%s_DITH4 to value 0"] +impl crate::Resettable for CCBUF_DITH4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tcc0/ccbuf_dith5.rs b/pac/atsaml22j/src/tcc0/ccbuf_dith5.rs new file mode 100644 index 000000000000..71d87093959b --- /dev/null +++ b/pac/atsaml22j/src/tcc0/ccbuf_dith5.rs @@ -0,0 +1,95 @@ +#[doc = "Register `CCBUF%s_DITH5` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF%s_DITH5` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERBUF` reader - Dithering Buffer Cycle Number"] +pub type DITHERBUF_R = crate::FieldReader; +#[doc = "Field `DITHERBUF` writer - Dithering Buffer Cycle Number"] +pub type DITHERBUF_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CCBUF_DITH5_SPEC, u8, u8, 5, O>; +#[doc = "Field `CCBUF` reader - Channel Compare/Capture Buffer Value"] +pub type CCBUF_R = crate::FieldReader; +#[doc = "Field `CCBUF` writer - Channel Compare/Capture Buffer Value"] +pub type CCBUF_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CCBUF_DITH5_SPEC, u32, u32, 19, O>; +impl R { + #[doc = "Bits 0:4 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&self) -> DITHERBUF_R { + DITHERBUF_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new((self.bits >> 5) & 0x0007_ffff) + } +} +impl W { + #[doc = "Bits 0:4 - Dithering Buffer Cycle Number"] + #[inline(always)] + #[must_use] + pub fn ditherbuf(&mut self) -> DITHERBUF_W<0> { + DITHERBUF_W::new(self) + } + #[doc = "Bits 5:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + #[must_use] + pub fn ccbuf(&mut self) -> CCBUF_W<5> { + CCBUF_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf_dith5](index.html) module"] +pub struct CCBUF_DITH5_SPEC; +impl crate::RegisterSpec for CCBUF_DITH5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccbuf_dith5::R](R) reader structure"] +impl crate::Readable for CCBUF_DITH5_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf_dith5::W](W) writer structure"] +impl crate::Writable for CCBUF_DITH5_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CCBUF%s_DITH5 to value 0"] +impl crate::Resettable for CCBUF_DITH5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tcc0/ccbuf_dith6.rs b/pac/atsaml22j/src/tcc0/ccbuf_dith6.rs new file mode 100644 index 000000000000..dcbda96c01e7 --- /dev/null +++ b/pac/atsaml22j/src/tcc0/ccbuf_dith6.rs @@ -0,0 +1,95 @@ +#[doc = "Register `CCBUF%s_DITH6` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CCBUF%s_DITH6` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERBUF` reader - Dithering Buffer Cycle Number"] +pub type DITHERBUF_R = crate::FieldReader; +#[doc = "Field `DITHERBUF` writer - Dithering Buffer Cycle Number"] +pub type DITHERBUF_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CCBUF_DITH6_SPEC, u8, u8, 6, O>; +#[doc = "Field `CCBUF` reader - Channel Compare/Capture Buffer Value"] +pub type CCBUF_R = crate::FieldReader; +#[doc = "Field `CCBUF` writer - Channel Compare/Capture Buffer Value"] +pub type CCBUF_W<'a, const O: u8> = crate::FieldWriter<'a, u32, CCBUF_DITH6_SPEC, u32, u32, 18, O>; +impl R { + #[doc = "Bits 0:5 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&self) -> DITHERBUF_R { + DITHERBUF_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + pub fn ccbuf(&self) -> CCBUF_R { + CCBUF_R::new((self.bits >> 6) & 0x0003_ffff) + } +} +impl W { + #[doc = "Bits 0:5 - Dithering Buffer Cycle Number"] + #[inline(always)] + #[must_use] + pub fn ditherbuf(&mut self) -> DITHERBUF_W<0> { + DITHERBUF_W::new(self) + } + #[doc = "Bits 6:23 - Channel Compare/Capture Buffer Value"] + #[inline(always)] + #[must_use] + pub fn ccbuf(&mut self) -> CCBUF_W<6> { + CCBUF_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Compare and Capture Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ccbuf_dith6](index.html) module"] +pub struct CCBUF_DITH6_SPEC; +impl crate::RegisterSpec for CCBUF_DITH6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ccbuf_dith6::R](R) reader structure"] +impl crate::Readable for CCBUF_DITH6_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ccbuf_dith6::W](W) writer structure"] +impl crate::Writable for CCBUF_DITH6_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CCBUF%s_DITH6 to value 0"] +impl crate::Resettable for CCBUF_DITH6_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tcc0/count.rs b/pac/atsaml22j/src/tcc0/count.rs new file mode 100644 index 000000000000..1c80d12a9676 --- /dev/null +++ b/pac/atsaml22j/src/tcc0/count.rs @@ -0,0 +1,80 @@ +#[doc = "Register `COUNT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub type COUNT_R = crate::FieldReader; +#[doc = "Field `COUNT` writer - Counter Value"] +pub type COUNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, COUNT_SPEC, u32, u32, 24, O>; +impl R { + #[doc = "Bits 0:23 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(self.bits & 0x00ff_ffff) + } +} +impl W { + #[doc = "Bits 0:23 - Counter Value"] + #[inline(always)] + #[must_use] + pub fn count(&mut self) -> COUNT_W<0> { + COUNT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count](index.html) module"] +pub struct COUNT_SPEC; +impl crate::RegisterSpec for COUNT_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count::R](R) reader structure"] +impl crate::Readable for COUNT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count::W](W) writer structure"] +impl crate::Writable for COUNT_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COUNT to value 0"] +impl crate::Resettable for COUNT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tcc0/count_dith4.rs b/pac/atsaml22j/src/tcc0/count_dith4.rs new file mode 100644 index 000000000000..e806020a315c --- /dev/null +++ b/pac/atsaml22j/src/tcc0/count_dith4.rs @@ -0,0 +1,80 @@ +#[doc = "Register `COUNT_DITH4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT_DITH4` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub type COUNT_R = crate::FieldReader; +#[doc = "Field `COUNT` writer - Counter Value"] +pub type COUNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, COUNT_DITH4_SPEC, u32, u32, 20, O>; +impl R { + #[doc = "Bits 4:23 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits >> 4) & 0x000f_ffff) + } +} +impl W { + #[doc = "Bits 4:23 - Counter Value"] + #[inline(always)] + #[must_use] + pub fn count(&mut self) -> COUNT_W<4> { + COUNT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count_dith4](index.html) module"] +pub struct COUNT_DITH4_SPEC; +impl crate::RegisterSpec for COUNT_DITH4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count_dith4::R](R) reader structure"] +impl crate::Readable for COUNT_DITH4_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count_dith4::W](W) writer structure"] +impl crate::Writable for COUNT_DITH4_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COUNT_DITH4 to value 0"] +impl crate::Resettable for COUNT_DITH4_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tcc0/count_dith5.rs b/pac/atsaml22j/src/tcc0/count_dith5.rs new file mode 100644 index 000000000000..85f6c4ce8b98 --- /dev/null +++ b/pac/atsaml22j/src/tcc0/count_dith5.rs @@ -0,0 +1,80 @@ +#[doc = "Register `COUNT_DITH5` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT_DITH5` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub type COUNT_R = crate::FieldReader; +#[doc = "Field `COUNT` writer - Counter Value"] +pub type COUNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, COUNT_DITH5_SPEC, u32, u32, 19, O>; +impl R { + #[doc = "Bits 5:23 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits >> 5) & 0x0007_ffff) + } +} +impl W { + #[doc = "Bits 5:23 - Counter Value"] + #[inline(always)] + #[must_use] + pub fn count(&mut self) -> COUNT_W<5> { + COUNT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count_dith5](index.html) module"] +pub struct COUNT_DITH5_SPEC; +impl crate::RegisterSpec for COUNT_DITH5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count_dith5::R](R) reader structure"] +impl crate::Readable for COUNT_DITH5_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count_dith5::W](W) writer structure"] +impl crate::Writable for COUNT_DITH5_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COUNT_DITH5 to value 0"] +impl crate::Resettable for COUNT_DITH5_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tcc0/count_dith6.rs b/pac/atsaml22j/src/tcc0/count_dith6.rs new file mode 100644 index 000000000000..3d0ab01d19a0 --- /dev/null +++ b/pac/atsaml22j/src/tcc0/count_dith6.rs @@ -0,0 +1,80 @@ +#[doc = "Register `COUNT_DITH6` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `COUNT_DITH6` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `COUNT` reader - Counter Value"] +pub type COUNT_R = crate::FieldReader; +#[doc = "Field `COUNT` writer - Counter Value"] +pub type COUNT_W<'a, const O: u8> = crate::FieldWriter<'a, u32, COUNT_DITH6_SPEC, u32, u32, 18, O>; +impl R { + #[doc = "Bits 6:23 - Counter Value"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new((self.bits >> 6) & 0x0003_ffff) + } +} +impl W { + #[doc = "Bits 6:23 - Counter Value"] + #[inline(always)] + #[must_use] + pub fn count(&mut self) -> COUNT_W<6> { + COUNT_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Count\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [count_dith6](index.html) module"] +pub struct COUNT_DITH6_SPEC; +impl crate::RegisterSpec for COUNT_DITH6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [count_dith6::R](R) reader structure"] +impl crate::Readable for COUNT_DITH6_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [count_dith6::W](W) writer structure"] +impl crate::Writable for COUNT_DITH6_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets COUNT_DITH6 to value 0"] +impl crate::Resettable for COUNT_DITH6_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tcc0/ctrla.rs b/pac/atsaml22j/src/tcc0/ctrla.rs new file mode 100644 index 000000000000..b064914bf0ba --- /dev/null +++ b/pac/atsaml22j/src/tcc0/ctrla.rs @@ -0,0 +1,524 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub type SWRST_R = crate::BitReader; +#[doc = "Field `SWRST` writer - Software Reset"] +pub type SWRST_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `ENABLE` reader - Enable"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - Enable"] +pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `RESOLUTION` reader - Enhanced Resolution"] +pub type RESOLUTION_R = crate::FieldReader; +#[doc = "Enhanced Resolution\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum RESOLUTIONSELECT_A { + #[doc = "0: Dithering is disabled"] + NONE = 0, + #[doc = "1: Dithering is done every 16 PWM frames"] + DITH4 = 1, + #[doc = "2: Dithering is done every 32 PWM frames"] + DITH5 = 2, + #[doc = "3: Dithering is done every 64 PWM frames"] + DITH6 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RESOLUTIONSELECT_A) -> Self { + variant as _ + } +} +impl RESOLUTION_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RESOLUTIONSELECT_A { + match self.bits { + 0 => RESOLUTIONSELECT_A::NONE, + 1 => RESOLUTIONSELECT_A::DITH4, + 2 => RESOLUTIONSELECT_A::DITH5, + 3 => RESOLUTIONSELECT_A::DITH6, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == RESOLUTIONSELECT_A::NONE + } + #[doc = "Checks if the value of the field is `DITH4`"] + #[inline(always)] + pub fn is_dith4(&self) -> bool { + *self == RESOLUTIONSELECT_A::DITH4 + } + #[doc = "Checks if the value of the field is `DITH5`"] + #[inline(always)] + pub fn is_dith5(&self) -> bool { + *self == RESOLUTIONSELECT_A::DITH5 + } + #[doc = "Checks if the value of the field is `DITH6`"] + #[inline(always)] + pub fn is_dith6(&self) -> bool { + *self == RESOLUTIONSELECT_A::DITH6 + } +} +#[doc = "Field `RESOLUTION` writer - Enhanced Resolution"] +pub type RESOLUTION_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, CTRLA_SPEC, u8, RESOLUTIONSELECT_A, 2, O>; +impl<'a, const O: u8> RESOLUTION_W<'a, O> { + #[doc = "Dithering is disabled"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(RESOLUTIONSELECT_A::NONE) + } + #[doc = "Dithering is done every 16 PWM frames"] + #[inline(always)] + pub fn dith4(self) -> &'a mut W { + self.variant(RESOLUTIONSELECT_A::DITH4) + } + #[doc = "Dithering is done every 32 PWM frames"] + #[inline(always)] + pub fn dith5(self) -> &'a mut W { + self.variant(RESOLUTIONSELECT_A::DITH5) + } + #[doc = "Dithering is done every 64 PWM frames"] + #[inline(always)] + pub fn dith6(self) -> &'a mut W { + self.variant(RESOLUTIONSELECT_A::DITH6) + } +} +#[doc = "Field `PRESCALER` reader - Prescaler"] +pub type PRESCALER_R = crate::FieldReader; +#[doc = "Prescaler\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum PRESCALERSELECT_A { + #[doc = "0: No division"] + DIV1 = 0, + #[doc = "1: Divide by 2"] + DIV2 = 1, + #[doc = "2: Divide by 4"] + DIV4 = 2, + #[doc = "3: Divide by 8"] + DIV8 = 3, + #[doc = "4: Divide by 16"] + DIV16 = 4, + #[doc = "5: Divide by 64"] + DIV64 = 5, + #[doc = "6: Divide by 256"] + DIV256 = 6, + #[doc = "7: Divide by 1024"] + DIV1024 = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCALERSELECT_A) -> Self { + variant as _ + } +} +impl PRESCALER_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> PRESCALERSELECT_A { + match self.bits { + 0 => PRESCALERSELECT_A::DIV1, + 1 => PRESCALERSELECT_A::DIV2, + 2 => PRESCALERSELECT_A::DIV4, + 3 => PRESCALERSELECT_A::DIV8, + 4 => PRESCALERSELECT_A::DIV16, + 5 => PRESCALERSELECT_A::DIV64, + 6 => PRESCALERSELECT_A::DIV256, + 7 => PRESCALERSELECT_A::DIV1024, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DIV1`"] + #[inline(always)] + pub fn is_div1(&self) -> bool { + *self == PRESCALERSELECT_A::DIV1 + } + #[doc = "Checks if the value of the field is `DIV2`"] + #[inline(always)] + pub fn is_div2(&self) -> bool { + *self == PRESCALERSELECT_A::DIV2 + } + #[doc = "Checks if the value of the field is `DIV4`"] + #[inline(always)] + pub fn is_div4(&self) -> bool { + *self == PRESCALERSELECT_A::DIV4 + } + #[doc = "Checks if the value of the field is `DIV8`"] + #[inline(always)] + pub fn is_div8(&self) -> bool { + *self == PRESCALERSELECT_A::DIV8 + } + #[doc = "Checks if the value of the field is `DIV16`"] + #[inline(always)] + pub fn is_div16(&self) -> bool { + *self == PRESCALERSELECT_A::DIV16 + } + #[doc = "Checks if the value of the field is `DIV64`"] + #[inline(always)] + pub fn is_div64(&self) -> bool { + *self == PRESCALERSELECT_A::DIV64 + } + #[doc = "Checks if the value of the field is `DIV256`"] + #[inline(always)] + pub fn is_div256(&self) -> bool { + *self == PRESCALERSELECT_A::DIV256 + } + #[doc = "Checks if the value of the field is `DIV1024`"] + #[inline(always)] + pub fn is_div1024(&self) -> bool { + *self == PRESCALERSELECT_A::DIV1024 + } +} +#[doc = "Field `PRESCALER` writer - Prescaler"] +pub type PRESCALER_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, CTRLA_SPEC, u8, PRESCALERSELECT_A, 3, O>; +impl<'a, const O: u8> PRESCALER_W<'a, O> { + #[doc = "No division"] + #[inline(always)] + pub fn div1(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV1) + } + #[doc = "Divide by 2"] + #[inline(always)] + pub fn div2(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV2) + } + #[doc = "Divide by 4"] + #[inline(always)] + pub fn div4(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV4) + } + #[doc = "Divide by 8"] + #[inline(always)] + pub fn div8(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV8) + } + #[doc = "Divide by 16"] + #[inline(always)] + pub fn div16(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV16) + } + #[doc = "Divide by 64"] + #[inline(always)] + pub fn div64(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV64) + } + #[doc = "Divide by 256"] + #[inline(always)] + pub fn div256(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV256) + } + #[doc = "Divide by 1024"] + #[inline(always)] + pub fn div1024(self) -> &'a mut W { + self.variant(PRESCALERSELECT_A::DIV1024) + } +} +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub type RUNSTDBY_R = crate::BitReader; +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub type RUNSTDBY_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `PRESCSYNC` reader - Prescaler and Counter Synchronization Selection"] +pub type PRESCSYNC_R = crate::FieldReader; +#[doc = "Prescaler and Counter Synchronization Selection\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum PRESCSYNCSELECT_A { + #[doc = "0: Reload or reset counter on next GCLK"] + GCLK = 0, + #[doc = "1: Reload or reset counter on next prescaler clock"] + PRESC = 1, + #[doc = "2: Reload or reset counter on next GCLK and reset prescaler counter"] + RESYNC = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PRESCSYNCSELECT_A) -> Self { + variant as _ + } +} +impl PRESCSYNC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PRESCSYNCSELECT_A::GCLK), + 1 => Some(PRESCSYNCSELECT_A::PRESC), + 2 => Some(PRESCSYNCSELECT_A::RESYNC), + _ => None, + } + } + #[doc = "Checks if the value of the field is `GCLK`"] + #[inline(always)] + pub fn is_gclk(&self) -> bool { + *self == PRESCSYNCSELECT_A::GCLK + } + #[doc = "Checks if the value of the field is `PRESC`"] + #[inline(always)] + pub fn is_presc(&self) -> bool { + *self == PRESCSYNCSELECT_A::PRESC + } + #[doc = "Checks if the value of the field is `RESYNC`"] + #[inline(always)] + pub fn is_resync(&self) -> bool { + *self == PRESCSYNCSELECT_A::RESYNC + } +} +#[doc = "Field `PRESCSYNC` writer - Prescaler and Counter Synchronization Selection"] +pub type PRESCSYNC_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, CTRLA_SPEC, u8, PRESCSYNCSELECT_A, 2, O>; +impl<'a, const O: u8> PRESCSYNC_W<'a, O> { + #[doc = "Reload or reset counter on next GCLK"] + #[inline(always)] + pub fn gclk(self) -> &'a mut W { + self.variant(PRESCSYNCSELECT_A::GCLK) + } + #[doc = "Reload or reset counter on next prescaler clock"] + #[inline(always)] + pub fn presc(self) -> &'a mut W { + self.variant(PRESCSYNCSELECT_A::PRESC) + } + #[doc = "Reload or reset counter on next GCLK and reset prescaler counter"] + #[inline(always)] + pub fn resync(self) -> &'a mut W { + self.variant(PRESCSYNCSELECT_A::RESYNC) + } +} +#[doc = "Field `ALOCK` reader - Auto Lock"] +pub type ALOCK_R = crate::BitReader; +#[doc = "Field `ALOCK` writer - Auto Lock"] +pub type ALOCK_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `MSYNC` reader - Master Synchronization (only for TCC Slave Instance)"] +pub type MSYNC_R = crate::BitReader; +#[doc = "Field `MSYNC` writer - Master Synchronization (only for TCC Slave Instance)"] +pub type MSYNC_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `DMAOS` reader - DMA One-shot Trigger Mode"] +pub type DMAOS_R = crate::BitReader; +#[doc = "Field `DMAOS` writer - DMA One-shot Trigger Mode"] +pub type DMAOS_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `CPTEN0` reader - Capture Channel 0 Enable"] +pub type CPTEN0_R = crate::BitReader; +#[doc = "Field `CPTEN0` writer - Capture Channel 0 Enable"] +pub type CPTEN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `CPTEN1` reader - Capture Channel 1 Enable"] +pub type CPTEN1_R = crate::BitReader; +#[doc = "Field `CPTEN1` writer - Capture Channel 1 Enable"] +pub type CPTEN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `CPTEN2` reader - Capture Channel 2 Enable"] +pub type CPTEN2_R = crate::BitReader; +#[doc = "Field `CPTEN2` writer - Capture Channel 2 Enable"] +pub type CPTEN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +#[doc = "Field `CPTEN3` reader - Capture Channel 3 Enable"] +pub type CPTEN3_R = crate::BitReader; +#[doc = "Field `CPTEN3` writer - Capture Channel 3 Enable"] +pub type CPTEN3_W<'a, const O: u8> = crate::BitWriter<'a, u32, CTRLA_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 5:6 - Enhanced Resolution"] + #[inline(always)] + pub fn resolution(&self) -> RESOLUTION_R { + RESOLUTION_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + pub fn prescaler(&self) -> PRESCALER_R { + PRESCALER_R::new(((self.bits >> 8) & 7) as u8) + } + #[doc = "Bit 11 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 12:13 - Prescaler and Counter Synchronization Selection"] + #[inline(always)] + pub fn prescsync(&self) -> PRESCSYNC_R { + PRESCSYNC_R::new(((self.bits >> 12) & 3) as u8) + } + #[doc = "Bit 14 - Auto Lock"] + #[inline(always)] + pub fn alock(&self) -> ALOCK_R { + ALOCK_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Master Synchronization (only for TCC Slave Instance)"] + #[inline(always)] + pub fn msync(&self) -> MSYNC_R { + MSYNC_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 23 - DMA One-shot Trigger Mode"] + #[inline(always)] + pub fn dmaos(&self) -> DMAOS_R { + DMAOS_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bit 24 - Capture Channel 0 Enable"] + #[inline(always)] + pub fn cpten0(&self) -> CPTEN0_R { + CPTEN0_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Capture Channel 1 Enable"] + #[inline(always)] + pub fn cpten1(&self) -> CPTEN1_R { + CPTEN1_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Capture Channel 2 Enable"] + #[inline(always)] + pub fn cpten2(&self) -> CPTEN2_R { + CPTEN2_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Capture Channel 3 Enable"] + #[inline(always)] + pub fn cpten3(&self) -> CPTEN3_R { + CPTEN3_R::new(((self.bits >> 27) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + #[must_use] + pub fn swrst(&mut self) -> SWRST_W<0> { + SWRST_W::new(self) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W<1> { + ENABLE_W::new(self) + } + #[doc = "Bits 5:6 - Enhanced Resolution"] + #[inline(always)] + #[must_use] + pub fn resolution(&mut self) -> RESOLUTION_W<5> { + RESOLUTION_W::new(self) + } + #[doc = "Bits 8:10 - Prescaler"] + #[inline(always)] + #[must_use] + pub fn prescaler(&mut self) -> PRESCALER_W<8> { + PRESCALER_W::new(self) + } + #[doc = "Bit 11 - Run in Standby"] + #[inline(always)] + #[must_use] + pub fn runstdby(&mut self) -> RUNSTDBY_W<11> { + RUNSTDBY_W::new(self) + } + #[doc = "Bits 12:13 - Prescaler and Counter Synchronization Selection"] + #[inline(always)] + #[must_use] + pub fn prescsync(&mut self) -> PRESCSYNC_W<12> { + PRESCSYNC_W::new(self) + } + #[doc = "Bit 14 - Auto Lock"] + #[inline(always)] + #[must_use] + pub fn alock(&mut self) -> ALOCK_W<14> { + ALOCK_W::new(self) + } + #[doc = "Bit 15 - Master Synchronization (only for TCC Slave Instance)"] + #[inline(always)] + #[must_use] + pub fn msync(&mut self) -> MSYNC_W<15> { + MSYNC_W::new(self) + } + #[doc = "Bit 23 - DMA One-shot Trigger Mode"] + #[inline(always)] + #[must_use] + pub fn dmaos(&mut self) -> DMAOS_W<23> { + DMAOS_W::new(self) + } + #[doc = "Bit 24 - Capture Channel 0 Enable"] + #[inline(always)] + #[must_use] + pub fn cpten0(&mut self) -> CPTEN0_W<24> { + CPTEN0_W::new(self) + } + #[doc = "Bit 25 - Capture Channel 1 Enable"] + #[inline(always)] + #[must_use] + pub fn cpten1(&mut self) -> CPTEN1_W<25> { + CPTEN1_W::new(self) + } + #[doc = "Bit 26 - Capture Channel 2 Enable"] + #[inline(always)] + #[must_use] + pub fn cpten2(&mut self) -> CPTEN2_W<26> { + CPTEN2_W::new(self) + } + #[doc = "Bit 27 - Capture Channel 3 Enable"] + #[inline(always)] + #[must_use] + pub fn cpten3(&mut self) -> CPTEN3_W<27> { + CPTEN3_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tcc0/ctrlbclr.rs b/pac/atsaml22j/src/tcc0/ctrlbclr.rs new file mode 100644 index 000000000000..ffd90221d137 --- /dev/null +++ b/pac/atsaml22j/src/tcc0/ctrlbclr.rs @@ -0,0 +1,315 @@ +#[doc = "Register `CTRLBCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub type DIR_R = crate::BitReader; +#[doc = "Field `DIR` writer - Counter Direction"] +pub type DIR_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLBCLR_SPEC, bool, O>; +#[doc = "Field `LUPD` reader - Lock Update"] +pub type LUPD_R = crate::BitReader; +#[doc = "Field `LUPD` writer - Lock Update"] +pub type LUPD_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLBCLR_SPEC, bool, O>; +#[doc = "Field `ONESHOT` reader - One-Shot"] +pub type ONESHOT_R = crate::BitReader; +#[doc = "Field `ONESHOT` writer - One-Shot"] +pub type ONESHOT_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLBCLR_SPEC, bool, O>; +#[doc = "Field `IDXCMD` reader - Ramp Index Command"] +pub type IDXCMD_R = crate::FieldReader; +#[doc = "Ramp Index Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum IDXCMDSELECT_A { + #[doc = "0: Command disabled: Index toggles between cycles A and B"] + DISABLE = 0, + #[doc = "1: Set index: cycle B will be forced in the next cycle"] + SET = 1, + #[doc = "2: Clear index: cycle A will be forced in the next cycle"] + CLEAR = 2, + #[doc = "3: Hold index: the next cycle will be the same as the current cycle"] + HOLD = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: IDXCMDSELECT_A) -> Self { + variant as _ + } +} +impl IDXCMD_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> IDXCMDSELECT_A { + match self.bits { + 0 => IDXCMDSELECT_A::DISABLE, + 1 => IDXCMDSELECT_A::SET, + 2 => IDXCMDSELECT_A::CLEAR, + 3 => IDXCMDSELECT_A::HOLD, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == IDXCMDSELECT_A::DISABLE + } + #[doc = "Checks if the value of the field is `SET`"] + #[inline(always)] + pub fn is_set(&self) -> bool { + *self == IDXCMDSELECT_A::SET + } + #[doc = "Checks if the value of the field is `CLEAR`"] + #[inline(always)] + pub fn is_clear(&self) -> bool { + *self == IDXCMDSELECT_A::CLEAR + } + #[doc = "Checks if the value of the field is `HOLD`"] + #[inline(always)] + pub fn is_hold(&self) -> bool { + *self == IDXCMDSELECT_A::HOLD + } +} +#[doc = "Field `IDXCMD` writer - Ramp Index Command"] +pub type IDXCMD_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u8, CTRLBCLR_SPEC, u8, IDXCMDSELECT_A, 2, O>; +impl<'a, const O: u8> IDXCMD_W<'a, O> { + #[doc = "Command disabled: Index toggles between cycles A and B"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(IDXCMDSELECT_A::DISABLE) + } + #[doc = "Set index: cycle B will be forced in the next cycle"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(IDXCMDSELECT_A::SET) + } + #[doc = "Clear index: cycle A will be forced in the next cycle"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(IDXCMDSELECT_A::CLEAR) + } + #[doc = "Hold index: the next cycle will be the same as the current cycle"] + #[inline(always)] + pub fn hold(self) -> &'a mut W { + self.variant(IDXCMDSELECT_A::HOLD) + } +} +#[doc = "Field `CMD` reader - TCC Command"] +pub type CMD_R = crate::FieldReader; +#[doc = "TCC Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum CMDSELECT_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Clear start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force stop"] + STOP = 2, + #[doc = "3: Force update or double buffered registers"] + UPDATE = 3, + #[doc = "4: Force COUNT read synchronization"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMDSELECT_A) -> Self { + variant as _ + } +} +impl CMD_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMDSELECT_A::NONE), + 1 => Some(CMDSELECT_A::RETRIGGER), + 2 => Some(CMDSELECT_A::STOP), + 3 => Some(CMDSELECT_A::UPDATE), + 4 => Some(CMDSELECT_A::READSYNC), + 5 => Some(CMDSELECT_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == CMDSELECT_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + *self == CMDSELECT_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + *self == CMDSELECT_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + *self == CMDSELECT_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + *self == CMDSELECT_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + *self == CMDSELECT_A::DMAOS + } +} +#[doc = "Field `CMD` writer - TCC Command"] +pub type CMD_W<'a, const O: u8> = crate::FieldWriter<'a, u8, CTRLBCLR_SPEC, u8, CMDSELECT_A, 3, O>; +impl<'a, const O: u8> CMD_W<'a, O> { + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMDSELECT_A::NONE) + } + #[doc = "Clear start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMDSELECT_A::RETRIGGER) + } + #[doc = "Force stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMDSELECT_A::STOP) + } + #[doc = "Force update or double buffered registers"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMDSELECT_A::UPDATE) + } + #[doc = "Force COUNT read synchronization"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMDSELECT_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMDSELECT_A::DMAOS) + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 3:4 - Ramp Index Command"] + #[inline(always)] + pub fn idxcmd(&self) -> IDXCMD_R { + IDXCMD_R::new((self.bits >> 3) & 3) + } + #[doc = "Bits 5:7 - TCC Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new((self.bits >> 5) & 7) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + #[must_use] + pub fn dir(&mut self) -> DIR_W<0> { + DIR_W::new(self) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + #[must_use] + pub fn lupd(&mut self) -> LUPD_W<1> { + LUPD_W::new(self) + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + #[must_use] + pub fn oneshot(&mut self) -> ONESHOT_W<2> { + ONESHOT_W::new(self) + } + #[doc = "Bits 3:4 - Ramp Index Command"] + #[inline(always)] + #[must_use] + pub fn idxcmd(&mut self) -> IDXCMD_W<3> { + IDXCMD_W::new(self) + } + #[doc = "Bits 5:7 - TCC Command"] + #[inline(always)] + #[must_use] + pub fn cmd(&mut self) -> CMD_W<5> { + CMD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbclr](index.html) module"] +pub struct CTRLBCLR_SPEC; +impl crate::RegisterSpec for CTRLBCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbclr::R](R) reader structure"] +impl crate::Readable for CTRLBCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbclr::W](W) writer structure"] +impl crate::Writable for CTRLBCLR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRLBCLR to value 0"] +impl crate::Resettable for CTRLBCLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tcc0/ctrlbset.rs b/pac/atsaml22j/src/tcc0/ctrlbset.rs new file mode 100644 index 000000000000..bc0e06f625d6 --- /dev/null +++ b/pac/atsaml22j/src/tcc0/ctrlbset.rs @@ -0,0 +1,315 @@ +#[doc = "Register `CTRLBSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLBSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DIR` reader - Counter Direction"] +pub type DIR_R = crate::BitReader; +#[doc = "Field `DIR` writer - Counter Direction"] +pub type DIR_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLBSET_SPEC, bool, O>; +#[doc = "Field `LUPD` reader - Lock Update"] +pub type LUPD_R = crate::BitReader; +#[doc = "Field `LUPD` writer - Lock Update"] +pub type LUPD_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLBSET_SPEC, bool, O>; +#[doc = "Field `ONESHOT` reader - One-Shot"] +pub type ONESHOT_R = crate::BitReader; +#[doc = "Field `ONESHOT` writer - One-Shot"] +pub type ONESHOT_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLBSET_SPEC, bool, O>; +#[doc = "Field `IDXCMD` reader - Ramp Index Command"] +pub type IDXCMD_R = crate::FieldReader; +#[doc = "Ramp Index Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum IDXCMDSELECT_A { + #[doc = "0: Command disabled: Index toggles between cycles A and B"] + DISABLE = 0, + #[doc = "1: Set index: cycle B will be forced in the next cycle"] + SET = 1, + #[doc = "2: Clear index: cycle A will be forced in the next cycle"] + CLEAR = 2, + #[doc = "3: Hold index: the next cycle will be the same as the current cycle"] + HOLD = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: IDXCMDSELECT_A) -> Self { + variant as _ + } +} +impl IDXCMD_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> IDXCMDSELECT_A { + match self.bits { + 0 => IDXCMDSELECT_A::DISABLE, + 1 => IDXCMDSELECT_A::SET, + 2 => IDXCMDSELECT_A::CLEAR, + 3 => IDXCMDSELECT_A::HOLD, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == IDXCMDSELECT_A::DISABLE + } + #[doc = "Checks if the value of the field is `SET`"] + #[inline(always)] + pub fn is_set(&self) -> bool { + *self == IDXCMDSELECT_A::SET + } + #[doc = "Checks if the value of the field is `CLEAR`"] + #[inline(always)] + pub fn is_clear(&self) -> bool { + *self == IDXCMDSELECT_A::CLEAR + } + #[doc = "Checks if the value of the field is `HOLD`"] + #[inline(always)] + pub fn is_hold(&self) -> bool { + *self == IDXCMDSELECT_A::HOLD + } +} +#[doc = "Field `IDXCMD` writer - Ramp Index Command"] +pub type IDXCMD_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u8, CTRLBSET_SPEC, u8, IDXCMDSELECT_A, 2, O>; +impl<'a, const O: u8> IDXCMD_W<'a, O> { + #[doc = "Command disabled: Index toggles between cycles A and B"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(IDXCMDSELECT_A::DISABLE) + } + #[doc = "Set index: cycle B will be forced in the next cycle"] + #[inline(always)] + pub fn set(self) -> &'a mut W { + self.variant(IDXCMDSELECT_A::SET) + } + #[doc = "Clear index: cycle A will be forced in the next cycle"] + #[inline(always)] + pub fn clear(self) -> &'a mut W { + self.variant(IDXCMDSELECT_A::CLEAR) + } + #[doc = "Hold index: the next cycle will be the same as the current cycle"] + #[inline(always)] + pub fn hold(self) -> &'a mut W { + self.variant(IDXCMDSELECT_A::HOLD) + } +} +#[doc = "Field `CMD` reader - TCC Command"] +pub type CMD_R = crate::FieldReader; +#[doc = "TCC Command\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum CMDSELECT_A { + #[doc = "0: No action"] + NONE = 0, + #[doc = "1: Clear start, restart or retrigger"] + RETRIGGER = 1, + #[doc = "2: Force stop"] + STOP = 2, + #[doc = "3: Force update or double buffered registers"] + UPDATE = 3, + #[doc = "4: Force COUNT read synchronization"] + READSYNC = 4, + #[doc = "5: One-shot DMA trigger"] + DMAOS = 5, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CMDSELECT_A) -> Self { + variant as _ + } +} +impl CMD_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(CMDSELECT_A::NONE), + 1 => Some(CMDSELECT_A::RETRIGGER), + 2 => Some(CMDSELECT_A::STOP), + 3 => Some(CMDSELECT_A::UPDATE), + 4 => Some(CMDSELECT_A::READSYNC), + 5 => Some(CMDSELECT_A::DMAOS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NONE`"] + #[inline(always)] + pub fn is_none(&self) -> bool { + *self == CMDSELECT_A::NONE + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + *self == CMDSELECT_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + *self == CMDSELECT_A::STOP + } + #[doc = "Checks if the value of the field is `UPDATE`"] + #[inline(always)] + pub fn is_update(&self) -> bool { + *self == CMDSELECT_A::UPDATE + } + #[doc = "Checks if the value of the field is `READSYNC`"] + #[inline(always)] + pub fn is_readsync(&self) -> bool { + *self == CMDSELECT_A::READSYNC + } + #[doc = "Checks if the value of the field is `DMAOS`"] + #[inline(always)] + pub fn is_dmaos(&self) -> bool { + *self == CMDSELECT_A::DMAOS + } +} +#[doc = "Field `CMD` writer - TCC Command"] +pub type CMD_W<'a, const O: u8> = crate::FieldWriter<'a, u8, CTRLBSET_SPEC, u8, CMDSELECT_A, 3, O>; +impl<'a, const O: u8> CMD_W<'a, O> { + #[doc = "No action"] + #[inline(always)] + pub fn none(self) -> &'a mut W { + self.variant(CMDSELECT_A::NONE) + } + #[doc = "Clear start, restart or retrigger"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(CMDSELECT_A::RETRIGGER) + } + #[doc = "Force stop"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(CMDSELECT_A::STOP) + } + #[doc = "Force update or double buffered registers"] + #[inline(always)] + pub fn update(self) -> &'a mut W { + self.variant(CMDSELECT_A::UPDATE) + } + #[doc = "Force COUNT read synchronization"] + #[inline(always)] + pub fn readsync(self) -> &'a mut W { + self.variant(CMDSELECT_A::READSYNC) + } + #[doc = "One-shot DMA trigger"] + #[inline(always)] + pub fn dmaos(self) -> &'a mut W { + self.variant(CMDSELECT_A::DMAOS) + } +} +impl R { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + pub fn dir(&self) -> DIR_R { + DIR_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + pub fn lupd(&self) -> LUPD_R { + LUPD_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + pub fn oneshot(&self) -> ONESHOT_R { + ONESHOT_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bits 3:4 - Ramp Index Command"] + #[inline(always)] + pub fn idxcmd(&self) -> IDXCMD_R { + IDXCMD_R::new((self.bits >> 3) & 3) + } + #[doc = "Bits 5:7 - TCC Command"] + #[inline(always)] + pub fn cmd(&self) -> CMD_R { + CMD_R::new((self.bits >> 5) & 7) + } +} +impl W { + #[doc = "Bit 0 - Counter Direction"] + #[inline(always)] + #[must_use] + pub fn dir(&mut self) -> DIR_W<0> { + DIR_W::new(self) + } + #[doc = "Bit 1 - Lock Update"] + #[inline(always)] + #[must_use] + pub fn lupd(&mut self) -> LUPD_W<1> { + LUPD_W::new(self) + } + #[doc = "Bit 2 - One-Shot"] + #[inline(always)] + #[must_use] + pub fn oneshot(&mut self) -> ONESHOT_W<2> { + ONESHOT_W::new(self) + } + #[doc = "Bits 3:4 - Ramp Index Command"] + #[inline(always)] + #[must_use] + pub fn idxcmd(&mut self) -> IDXCMD_W<3> { + IDXCMD_W::new(self) + } + #[doc = "Bits 5:7 - TCC Command"] + #[inline(always)] + #[must_use] + pub fn cmd(&mut self) -> CMD_W<5> { + CMD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control B Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlbset](index.html) module"] +pub struct CTRLBSET_SPEC; +impl crate::RegisterSpec for CTRLBSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrlbset::R](R) reader structure"] +impl crate::Readable for CTRLBSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlbset::W](W) writer structure"] +impl crate::Writable for CTRLBSET_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRLBSET to value 0"] +impl crate::Resettable for CTRLBSET_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tcc0/dbgctrl.rs b/pac/atsaml22j/src/tcc0/dbgctrl.rs new file mode 100644 index 000000000000..61e6b7cc5010 --- /dev/null +++ b/pac/atsaml22j/src/tcc0/dbgctrl.rs @@ -0,0 +1,95 @@ +#[doc = "Register `DBGCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DBGCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DBGRUN` reader - Debug Running Mode"] +pub type DBGRUN_R = crate::BitReader; +#[doc = "Field `DBGRUN` writer - Debug Running Mode"] +pub type DBGRUN_W<'a, const O: u8> = crate::BitWriter<'a, u8, DBGCTRL_SPEC, bool, O>; +#[doc = "Field `FDDBD` reader - Fault Detection on Debug Break Detection"] +pub type FDDBD_R = crate::BitReader; +#[doc = "Field `FDDBD` writer - Fault Detection on Debug Break Detection"] +pub type FDDBD_W<'a, const O: u8> = crate::BitWriter<'a, u8, DBGCTRL_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Debug Running Mode"] + #[inline(always)] + pub fn dbgrun(&self) -> DBGRUN_R { + DBGRUN_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 2 - Fault Detection on Debug Break Detection"] + #[inline(always)] + pub fn fddbd(&self) -> FDDBD_R { + FDDBD_R::new(((self.bits >> 2) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Debug Running Mode"] + #[inline(always)] + #[must_use] + pub fn dbgrun(&mut self) -> DBGRUN_W<0> { + DBGRUN_W::new(self) + } + #[doc = "Bit 2 - Fault Detection on Debug Break Detection"] + #[inline(always)] + #[must_use] + pub fn fddbd(&mut self) -> FDDBD_W<2> { + FDDBD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Debug Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dbgctrl](index.html) module"] +pub struct DBGCTRL_SPEC; +impl crate::RegisterSpec for DBGCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dbgctrl::R](R) reader structure"] +impl crate::Readable for DBGCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dbgctrl::W](W) writer structure"] +impl crate::Writable for DBGCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DBGCTRL to value 0"] +impl crate::Resettable for DBGCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tcc0/drvctrl.rs b/pac/atsaml22j/src/tcc0/drvctrl.rs new file mode 100644 index 000000000000..3da536fbf845 --- /dev/null +++ b/pac/atsaml22j/src/tcc0/drvctrl.rs @@ -0,0 +1,455 @@ +#[doc = "Register `DRVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DRVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `NRE0` reader - Non-Recoverable State 0 Output Enable"] +pub type NRE0_R = crate::BitReader; +#[doc = "Field `NRE0` writer - Non-Recoverable State 0 Output Enable"] +pub type NRE0_W<'a, const O: u8> = crate::BitWriter<'a, u32, DRVCTRL_SPEC, bool, O>; +#[doc = "Field `NRE1` reader - Non-Recoverable State 1 Output Enable"] +pub type NRE1_R = crate::BitReader; +#[doc = "Field `NRE1` writer - Non-Recoverable State 1 Output Enable"] +pub type NRE1_W<'a, const O: u8> = crate::BitWriter<'a, u32, DRVCTRL_SPEC, bool, O>; +#[doc = "Field `NRE2` reader - Non-Recoverable State 2 Output Enable"] +pub type NRE2_R = crate::BitReader; +#[doc = "Field `NRE2` writer - Non-Recoverable State 2 Output Enable"] +pub type NRE2_W<'a, const O: u8> = crate::BitWriter<'a, u32, DRVCTRL_SPEC, bool, O>; +#[doc = "Field `NRE3` reader - Non-Recoverable State 3 Output Enable"] +pub type NRE3_R = crate::BitReader; +#[doc = "Field `NRE3` writer - Non-Recoverable State 3 Output Enable"] +pub type NRE3_W<'a, const O: u8> = crate::BitWriter<'a, u32, DRVCTRL_SPEC, bool, O>; +#[doc = "Field `NRE4` reader - Non-Recoverable State 4 Output Enable"] +pub type NRE4_R = crate::BitReader; +#[doc = "Field `NRE4` writer - Non-Recoverable State 4 Output Enable"] +pub type NRE4_W<'a, const O: u8> = crate::BitWriter<'a, u32, DRVCTRL_SPEC, bool, O>; +#[doc = "Field `NRE5` reader - Non-Recoverable State 5 Output Enable"] +pub type NRE5_R = crate::BitReader; +#[doc = "Field `NRE5` writer - Non-Recoverable State 5 Output Enable"] +pub type NRE5_W<'a, const O: u8> = crate::BitWriter<'a, u32, DRVCTRL_SPEC, bool, O>; +#[doc = "Field `NRE6` reader - Non-Recoverable State 6 Output Enable"] +pub type NRE6_R = crate::BitReader; +#[doc = "Field `NRE6` writer - Non-Recoverable State 6 Output Enable"] +pub type NRE6_W<'a, const O: u8> = crate::BitWriter<'a, u32, DRVCTRL_SPEC, bool, O>; +#[doc = "Field `NRE7` reader - Non-Recoverable State 7 Output Enable"] +pub type NRE7_R = crate::BitReader; +#[doc = "Field `NRE7` writer - Non-Recoverable State 7 Output Enable"] +pub type NRE7_W<'a, const O: u8> = crate::BitWriter<'a, u32, DRVCTRL_SPEC, bool, O>; +#[doc = "Field `NRV0` reader - Non-Recoverable State 0 Output Value"] +pub type NRV0_R = crate::BitReader; +#[doc = "Field `NRV0` writer - Non-Recoverable State 0 Output Value"] +pub type NRV0_W<'a, const O: u8> = crate::BitWriter<'a, u32, DRVCTRL_SPEC, bool, O>; +#[doc = "Field `NRV1` reader - Non-Recoverable State 1 Output Value"] +pub type NRV1_R = crate::BitReader; +#[doc = "Field `NRV1` writer - Non-Recoverable State 1 Output Value"] +pub type NRV1_W<'a, const O: u8> = crate::BitWriter<'a, u32, DRVCTRL_SPEC, bool, O>; +#[doc = "Field `NRV2` reader - Non-Recoverable State 2 Output Value"] +pub type NRV2_R = crate::BitReader; +#[doc = "Field `NRV2` writer - Non-Recoverable State 2 Output Value"] +pub type NRV2_W<'a, const O: u8> = crate::BitWriter<'a, u32, DRVCTRL_SPEC, bool, O>; +#[doc = "Field `NRV3` reader - Non-Recoverable State 3 Output Value"] +pub type NRV3_R = crate::BitReader; +#[doc = "Field `NRV3` writer - Non-Recoverable State 3 Output Value"] +pub type NRV3_W<'a, const O: u8> = crate::BitWriter<'a, u32, DRVCTRL_SPEC, bool, O>; +#[doc = "Field `NRV4` reader - Non-Recoverable State 4 Output Value"] +pub type NRV4_R = crate::BitReader; +#[doc = "Field `NRV4` writer - Non-Recoverable State 4 Output Value"] +pub type NRV4_W<'a, const O: u8> = crate::BitWriter<'a, u32, DRVCTRL_SPEC, bool, O>; +#[doc = "Field `NRV5` reader - Non-Recoverable State 5 Output Value"] +pub type NRV5_R = crate::BitReader; +#[doc = "Field `NRV5` writer - Non-Recoverable State 5 Output Value"] +pub type NRV5_W<'a, const O: u8> = crate::BitWriter<'a, u32, DRVCTRL_SPEC, bool, O>; +#[doc = "Field `NRV6` reader - Non-Recoverable State 6 Output Value"] +pub type NRV6_R = crate::BitReader; +#[doc = "Field `NRV6` writer - Non-Recoverable State 6 Output Value"] +pub type NRV6_W<'a, const O: u8> = crate::BitWriter<'a, u32, DRVCTRL_SPEC, bool, O>; +#[doc = "Field `NRV7` reader - Non-Recoverable State 7 Output Value"] +pub type NRV7_R = crate::BitReader; +#[doc = "Field `NRV7` writer - Non-Recoverable State 7 Output Value"] +pub type NRV7_W<'a, const O: u8> = crate::BitWriter<'a, u32, DRVCTRL_SPEC, bool, O>; +#[doc = "Field `INVEN0` reader - Output Waveform 0 Inversion"] +pub type INVEN0_R = crate::BitReader; +#[doc = "Field `INVEN0` writer - Output Waveform 0 Inversion"] +pub type INVEN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, DRVCTRL_SPEC, bool, O>; +#[doc = "Field `INVEN1` reader - Output Waveform 1 Inversion"] +pub type INVEN1_R = crate::BitReader; +#[doc = "Field `INVEN1` writer - Output Waveform 1 Inversion"] +pub type INVEN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, DRVCTRL_SPEC, bool, O>; +#[doc = "Field `INVEN2` reader - Output Waveform 2 Inversion"] +pub type INVEN2_R = crate::BitReader; +#[doc = "Field `INVEN2` writer - Output Waveform 2 Inversion"] +pub type INVEN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, DRVCTRL_SPEC, bool, O>; +#[doc = "Field `INVEN3` reader - Output Waveform 3 Inversion"] +pub type INVEN3_R = crate::BitReader; +#[doc = "Field `INVEN3` writer - Output Waveform 3 Inversion"] +pub type INVEN3_W<'a, const O: u8> = crate::BitWriter<'a, u32, DRVCTRL_SPEC, bool, O>; +#[doc = "Field `INVEN4` reader - Output Waveform 4 Inversion"] +pub type INVEN4_R = crate::BitReader; +#[doc = "Field `INVEN4` writer - Output Waveform 4 Inversion"] +pub type INVEN4_W<'a, const O: u8> = crate::BitWriter<'a, u32, DRVCTRL_SPEC, bool, O>; +#[doc = "Field `INVEN5` reader - Output Waveform 5 Inversion"] +pub type INVEN5_R = crate::BitReader; +#[doc = "Field `INVEN5` writer - Output Waveform 5 Inversion"] +pub type INVEN5_W<'a, const O: u8> = crate::BitWriter<'a, u32, DRVCTRL_SPEC, bool, O>; +#[doc = "Field `INVEN6` reader - Output Waveform 6 Inversion"] +pub type INVEN6_R = crate::BitReader; +#[doc = "Field `INVEN6` writer - Output Waveform 6 Inversion"] +pub type INVEN6_W<'a, const O: u8> = crate::BitWriter<'a, u32, DRVCTRL_SPEC, bool, O>; +#[doc = "Field `INVEN7` reader - Output Waveform 7 Inversion"] +pub type INVEN7_R = crate::BitReader; +#[doc = "Field `INVEN7` writer - Output Waveform 7 Inversion"] +pub type INVEN7_W<'a, const O: u8> = crate::BitWriter<'a, u32, DRVCTRL_SPEC, bool, O>; +#[doc = "Field `FILTERVAL0` reader - Non-Recoverable Fault Input 0 Filter Value"] +pub type FILTERVAL0_R = crate::FieldReader; +#[doc = "Field `FILTERVAL0` writer - Non-Recoverable Fault Input 0 Filter Value"] +pub type FILTERVAL0_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DRVCTRL_SPEC, u8, u8, 4, O>; +#[doc = "Field `FILTERVAL1` reader - Non-Recoverable Fault Input 1 Filter Value"] +pub type FILTERVAL1_R = crate::FieldReader; +#[doc = "Field `FILTERVAL1` writer - Non-Recoverable Fault Input 1 Filter Value"] +pub type FILTERVAL1_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DRVCTRL_SPEC, u8, u8, 4, O>; +impl R { + #[doc = "Bit 0 - Non-Recoverable State 0 Output Enable"] + #[inline(always)] + pub fn nre0(&self) -> NRE0_R { + NRE0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Non-Recoverable State 1 Output Enable"] + #[inline(always)] + pub fn nre1(&self) -> NRE1_R { + NRE1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Non-Recoverable State 2 Output Enable"] + #[inline(always)] + pub fn nre2(&self) -> NRE2_R { + NRE2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Non-Recoverable State 3 Output Enable"] + #[inline(always)] + pub fn nre3(&self) -> NRE3_R { + NRE3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Non-Recoverable State 4 Output Enable"] + #[inline(always)] + pub fn nre4(&self) -> NRE4_R { + NRE4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Non-Recoverable State 5 Output Enable"] + #[inline(always)] + pub fn nre5(&self) -> NRE5_R { + NRE5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Non-Recoverable State 6 Output Enable"] + #[inline(always)] + pub fn nre6(&self) -> NRE6_R { + NRE6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Non-Recoverable State 7 Output Enable"] + #[inline(always)] + pub fn nre7(&self) -> NRE7_R { + NRE7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Non-Recoverable State 0 Output Value"] + #[inline(always)] + pub fn nrv0(&self) -> NRV0_R { + NRV0_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Non-Recoverable State 1 Output Value"] + #[inline(always)] + pub fn nrv1(&self) -> NRV1_R { + NRV1_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Non-Recoverable State 2 Output Value"] + #[inline(always)] + pub fn nrv2(&self) -> NRV2_R { + NRV2_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Non-Recoverable State 3 Output Value"] + #[inline(always)] + pub fn nrv3(&self) -> NRV3_R { + NRV3_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Non-Recoverable State 4 Output Value"] + #[inline(always)] + pub fn nrv4(&self) -> NRV4_R { + NRV4_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Non-Recoverable State 5 Output Value"] + #[inline(always)] + pub fn nrv5(&self) -> NRV5_R { + NRV5_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Non-Recoverable State 6 Output Value"] + #[inline(always)] + pub fn nrv6(&self) -> NRV6_R { + NRV6_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Non-Recoverable State 7 Output Value"] + #[inline(always)] + pub fn nrv7(&self) -> NRV7_R { + NRV7_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Output Waveform 0 Inversion"] + #[inline(always)] + pub fn inven0(&self) -> INVEN0_R { + INVEN0_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Output Waveform 1 Inversion"] + #[inline(always)] + pub fn inven1(&self) -> INVEN1_R { + INVEN1_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Output Waveform 2 Inversion"] + #[inline(always)] + pub fn inven2(&self) -> INVEN2_R { + INVEN2_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Output Waveform 3 Inversion"] + #[inline(always)] + pub fn inven3(&self) -> INVEN3_R { + INVEN3_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 20 - Output Waveform 4 Inversion"] + #[inline(always)] + pub fn inven4(&self) -> INVEN4_R { + INVEN4_R::new(((self.bits >> 20) & 1) != 0) + } + #[doc = "Bit 21 - Output Waveform 5 Inversion"] + #[inline(always)] + pub fn inven5(&self) -> INVEN5_R { + INVEN5_R::new(((self.bits >> 21) & 1) != 0) + } + #[doc = "Bit 22 - Output Waveform 6 Inversion"] + #[inline(always)] + pub fn inven6(&self) -> INVEN6_R { + INVEN6_R::new(((self.bits >> 22) & 1) != 0) + } + #[doc = "Bit 23 - Output Waveform 7 Inversion"] + #[inline(always)] + pub fn inven7(&self) -> INVEN7_R { + INVEN7_R::new(((self.bits >> 23) & 1) != 0) + } + #[doc = "Bits 24:27 - Non-Recoverable Fault Input 0 Filter Value"] + #[inline(always)] + pub fn filterval0(&self) -> FILTERVAL0_R { + FILTERVAL0_R::new(((self.bits >> 24) & 0x0f) as u8) + } + #[doc = "Bits 28:31 - Non-Recoverable Fault Input 1 Filter Value"] + #[inline(always)] + pub fn filterval1(&self) -> FILTERVAL1_R { + FILTERVAL1_R::new(((self.bits >> 28) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bit 0 - Non-Recoverable State 0 Output Enable"] + #[inline(always)] + #[must_use] + pub fn nre0(&mut self) -> NRE0_W<0> { + NRE0_W::new(self) + } + #[doc = "Bit 1 - Non-Recoverable State 1 Output Enable"] + #[inline(always)] + #[must_use] + pub fn nre1(&mut self) -> NRE1_W<1> { + NRE1_W::new(self) + } + #[doc = "Bit 2 - Non-Recoverable State 2 Output Enable"] + #[inline(always)] + #[must_use] + pub fn nre2(&mut self) -> NRE2_W<2> { + NRE2_W::new(self) + } + #[doc = "Bit 3 - Non-Recoverable State 3 Output Enable"] + #[inline(always)] + #[must_use] + pub fn nre3(&mut self) -> NRE3_W<3> { + NRE3_W::new(self) + } + #[doc = "Bit 4 - Non-Recoverable State 4 Output Enable"] + #[inline(always)] + #[must_use] + pub fn nre4(&mut self) -> NRE4_W<4> { + NRE4_W::new(self) + } + #[doc = "Bit 5 - Non-Recoverable State 5 Output Enable"] + #[inline(always)] + #[must_use] + pub fn nre5(&mut self) -> NRE5_W<5> { + NRE5_W::new(self) + } + #[doc = "Bit 6 - Non-Recoverable State 6 Output Enable"] + #[inline(always)] + #[must_use] + pub fn nre6(&mut self) -> NRE6_W<6> { + NRE6_W::new(self) + } + #[doc = "Bit 7 - Non-Recoverable State 7 Output Enable"] + #[inline(always)] + #[must_use] + pub fn nre7(&mut self) -> NRE7_W<7> { + NRE7_W::new(self) + } + #[doc = "Bit 8 - Non-Recoverable State 0 Output Value"] + #[inline(always)] + #[must_use] + pub fn nrv0(&mut self) -> NRV0_W<8> { + NRV0_W::new(self) + } + #[doc = "Bit 9 - Non-Recoverable State 1 Output Value"] + #[inline(always)] + #[must_use] + pub fn nrv1(&mut self) -> NRV1_W<9> { + NRV1_W::new(self) + } + #[doc = "Bit 10 - Non-Recoverable State 2 Output Value"] + #[inline(always)] + #[must_use] + pub fn nrv2(&mut self) -> NRV2_W<10> { + NRV2_W::new(self) + } + #[doc = "Bit 11 - Non-Recoverable State 3 Output Value"] + #[inline(always)] + #[must_use] + pub fn nrv3(&mut self) -> NRV3_W<11> { + NRV3_W::new(self) + } + #[doc = "Bit 12 - Non-Recoverable State 4 Output Value"] + #[inline(always)] + #[must_use] + pub fn nrv4(&mut self) -> NRV4_W<12> { + NRV4_W::new(self) + } + #[doc = "Bit 13 - Non-Recoverable State 5 Output Value"] + #[inline(always)] + #[must_use] + pub fn nrv5(&mut self) -> NRV5_W<13> { + NRV5_W::new(self) + } + #[doc = "Bit 14 - Non-Recoverable State 6 Output Value"] + #[inline(always)] + #[must_use] + pub fn nrv6(&mut self) -> NRV6_W<14> { + NRV6_W::new(self) + } + #[doc = "Bit 15 - Non-Recoverable State 7 Output Value"] + #[inline(always)] + #[must_use] + pub fn nrv7(&mut self) -> NRV7_W<15> { + NRV7_W::new(self) + } + #[doc = "Bit 16 - Output Waveform 0 Inversion"] + #[inline(always)] + #[must_use] + pub fn inven0(&mut self) -> INVEN0_W<16> { + INVEN0_W::new(self) + } + #[doc = "Bit 17 - Output Waveform 1 Inversion"] + #[inline(always)] + #[must_use] + pub fn inven1(&mut self) -> INVEN1_W<17> { + INVEN1_W::new(self) + } + #[doc = "Bit 18 - Output Waveform 2 Inversion"] + #[inline(always)] + #[must_use] + pub fn inven2(&mut self) -> INVEN2_W<18> { + INVEN2_W::new(self) + } + #[doc = "Bit 19 - Output Waveform 3 Inversion"] + #[inline(always)] + #[must_use] + pub fn inven3(&mut self) -> INVEN3_W<19> { + INVEN3_W::new(self) + } + #[doc = "Bit 20 - Output Waveform 4 Inversion"] + #[inline(always)] + #[must_use] + pub fn inven4(&mut self) -> INVEN4_W<20> { + INVEN4_W::new(self) + } + #[doc = "Bit 21 - Output Waveform 5 Inversion"] + #[inline(always)] + #[must_use] + pub fn inven5(&mut self) -> INVEN5_W<21> { + INVEN5_W::new(self) + } + #[doc = "Bit 22 - Output Waveform 6 Inversion"] + #[inline(always)] + #[must_use] + pub fn inven6(&mut self) -> INVEN6_W<22> { + INVEN6_W::new(self) + } + #[doc = "Bit 23 - Output Waveform 7 Inversion"] + #[inline(always)] + #[must_use] + pub fn inven7(&mut self) -> INVEN7_W<23> { + INVEN7_W::new(self) + } + #[doc = "Bits 24:27 - Non-Recoverable Fault Input 0 Filter Value"] + #[inline(always)] + #[must_use] + pub fn filterval0(&mut self) -> FILTERVAL0_W<24> { + FILTERVAL0_W::new(self) + } + #[doc = "Bits 28:31 - Non-Recoverable Fault Input 1 Filter Value"] + #[inline(always)] + #[must_use] + pub fn filterval1(&mut self) -> FILTERVAL1_W<28> { + FILTERVAL1_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Driver Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [drvctrl](index.html) module"] +pub struct DRVCTRL_SPEC; +impl crate::RegisterSpec for DRVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [drvctrl::R](R) reader structure"] +impl crate::Readable for DRVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [drvctrl::W](W) writer structure"] +impl crate::Writable for DRVCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DRVCTRL to value 0"] +impl crate::Resettable for DRVCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tcc0/evctrl.rs b/pac/atsaml22j/src/tcc0/evctrl.rs new file mode 100644 index 000000000000..72dee0d5ad40 --- /dev/null +++ b/pac/atsaml22j/src/tcc0/evctrl.rs @@ -0,0 +1,664 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EVACT0` reader - Timer/counter Input Event0 Action"] +pub type EVACT0_R = crate::FieldReader; +#[doc = "Timer/counter Input Event0 Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum EVACT0SELECT_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Start, restart or re-trigger counter on event"] + RETRIGGER = 1, + #[doc = "2: Count on event"] + COUNTEV = 2, + #[doc = "3: Start counter on event"] + START = 3, + #[doc = "4: Increment counter on event"] + INC = 4, + #[doc = "5: Count on active state of asynchronous event"] + COUNT = 5, + #[doc = "6: Stamp capture"] + STAMP = 6, + #[doc = "7: Non-recoverable fault"] + FAULT = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT0SELECT_A) -> Self { + variant as _ + } +} +impl EVACT0_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVACT0SELECT_A { + match self.bits { + 0 => EVACT0SELECT_A::OFF, + 1 => EVACT0SELECT_A::RETRIGGER, + 2 => EVACT0SELECT_A::COUNTEV, + 3 => EVACT0SELECT_A::START, + 4 => EVACT0SELECT_A::INC, + 5 => EVACT0SELECT_A::COUNT, + 6 => EVACT0SELECT_A::STAMP, + 7 => EVACT0SELECT_A::FAULT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == EVACT0SELECT_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + *self == EVACT0SELECT_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `COUNTEV`"] + #[inline(always)] + pub fn is_countev(&self) -> bool { + *self == EVACT0SELECT_A::COUNTEV + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + *self == EVACT0SELECT_A::START + } + #[doc = "Checks if the value of the field is `INC`"] + #[inline(always)] + pub fn is_inc(&self) -> bool { + *self == EVACT0SELECT_A::INC + } + #[doc = "Checks if the value of the field is `COUNT`"] + #[inline(always)] + pub fn is_count(&self) -> bool { + *self == EVACT0SELECT_A::COUNT + } + #[doc = "Checks if the value of the field is `STAMP`"] + #[inline(always)] + pub fn is_stamp(&self) -> bool { + *self == EVACT0SELECT_A::STAMP + } + #[doc = "Checks if the value of the field is `FAULT`"] + #[inline(always)] + pub fn is_fault(&self) -> bool { + *self == EVACT0SELECT_A::FAULT + } +} +#[doc = "Field `EVACT0` writer - Timer/counter Input Event0 Action"] +pub type EVACT0_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, EVCTRL_SPEC, u8, EVACT0SELECT_A, 3, O>; +impl<'a, const O: u8> EVACT0_W<'a, O> { + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACT0SELECT_A::OFF) + } + #[doc = "Start, restart or re-trigger counter on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACT0SELECT_A::RETRIGGER) + } + #[doc = "Count on event"] + #[inline(always)] + pub fn countev(self) -> &'a mut W { + self.variant(EVACT0SELECT_A::COUNTEV) + } + #[doc = "Start counter on event"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(EVACT0SELECT_A::START) + } + #[doc = "Increment counter on event"] + #[inline(always)] + pub fn inc(self) -> &'a mut W { + self.variant(EVACT0SELECT_A::INC) + } + #[doc = "Count on active state of asynchronous event"] + #[inline(always)] + pub fn count(self) -> &'a mut W { + self.variant(EVACT0SELECT_A::COUNT) + } + #[doc = "Stamp capture"] + #[inline(always)] + pub fn stamp(self) -> &'a mut W { + self.variant(EVACT0SELECT_A::STAMP) + } + #[doc = "Non-recoverable fault"] + #[inline(always)] + pub fn fault(self) -> &'a mut W { + self.variant(EVACT0SELECT_A::FAULT) + } +} +#[doc = "Field `EVACT1` reader - Timer/counter Input Event1 Action"] +pub type EVACT1_R = crate::FieldReader; +#[doc = "Timer/counter Input Event1 Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum EVACT1SELECT_A { + #[doc = "0: Event action disabled"] + OFF = 0, + #[doc = "1: Re-trigger counter on event"] + RETRIGGER = 1, + #[doc = "2: Direction control"] + DIR = 2, + #[doc = "3: Stop counter on event"] + STOP = 3, + #[doc = "4: Decrement counter on event"] + DEC = 4, + #[doc = "5: Period capture value in CC0 register, pulse width capture value in CC1 register"] + PPW = 5, + #[doc = "6: Period capture value in CC1 register, pulse width capture value in CC0 register"] + PWP = 6, + #[doc = "7: Non-recoverable fault"] + FAULT = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EVACT1SELECT_A) -> Self { + variant as _ + } +} +impl EVACT1_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> EVACT1SELECT_A { + match self.bits { + 0 => EVACT1SELECT_A::OFF, + 1 => EVACT1SELECT_A::RETRIGGER, + 2 => EVACT1SELECT_A::DIR, + 3 => EVACT1SELECT_A::STOP, + 4 => EVACT1SELECT_A::DEC, + 5 => EVACT1SELECT_A::PPW, + 6 => EVACT1SELECT_A::PWP, + 7 => EVACT1SELECT_A::FAULT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == EVACT1SELECT_A::OFF + } + #[doc = "Checks if the value of the field is `RETRIGGER`"] + #[inline(always)] + pub fn is_retrigger(&self) -> bool { + *self == EVACT1SELECT_A::RETRIGGER + } + #[doc = "Checks if the value of the field is `DIR`"] + #[inline(always)] + pub fn is_dir(&self) -> bool { + *self == EVACT1SELECT_A::DIR + } + #[doc = "Checks if the value of the field is `STOP`"] + #[inline(always)] + pub fn is_stop(&self) -> bool { + *self == EVACT1SELECT_A::STOP + } + #[doc = "Checks if the value of the field is `DEC`"] + #[inline(always)] + pub fn is_dec(&self) -> bool { + *self == EVACT1SELECT_A::DEC + } + #[doc = "Checks if the value of the field is `PPW`"] + #[inline(always)] + pub fn is_ppw(&self) -> bool { + *self == EVACT1SELECT_A::PPW + } + #[doc = "Checks if the value of the field is `PWP`"] + #[inline(always)] + pub fn is_pwp(&self) -> bool { + *self == EVACT1SELECT_A::PWP + } + #[doc = "Checks if the value of the field is `FAULT`"] + #[inline(always)] + pub fn is_fault(&self) -> bool { + *self == EVACT1SELECT_A::FAULT + } +} +#[doc = "Field `EVACT1` writer - Timer/counter Input Event1 Action"] +pub type EVACT1_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, EVCTRL_SPEC, u8, EVACT1SELECT_A, 3, O>; +impl<'a, const O: u8> EVACT1_W<'a, O> { + #[doc = "Event action disabled"] + #[inline(always)] + pub fn off(self) -> &'a mut W { + self.variant(EVACT1SELECT_A::OFF) + } + #[doc = "Re-trigger counter on event"] + #[inline(always)] + pub fn retrigger(self) -> &'a mut W { + self.variant(EVACT1SELECT_A::RETRIGGER) + } + #[doc = "Direction control"] + #[inline(always)] + pub fn dir(self) -> &'a mut W { + self.variant(EVACT1SELECT_A::DIR) + } + #[doc = "Stop counter on event"] + #[inline(always)] + pub fn stop(self) -> &'a mut W { + self.variant(EVACT1SELECT_A::STOP) + } + #[doc = "Decrement counter on event"] + #[inline(always)] + pub fn dec(self) -> &'a mut W { + self.variant(EVACT1SELECT_A::DEC) + } + #[doc = "Period capture value in CC0 register, pulse width capture value in CC1 register"] + #[inline(always)] + pub fn ppw(self) -> &'a mut W { + self.variant(EVACT1SELECT_A::PPW) + } + #[doc = "Period capture value in CC1 register, pulse width capture value in CC0 register"] + #[inline(always)] + pub fn pwp(self) -> &'a mut W { + self.variant(EVACT1SELECT_A::PWP) + } + #[doc = "Non-recoverable fault"] + #[inline(always)] + pub fn fault(self) -> &'a mut W { + self.variant(EVACT1SELECT_A::FAULT) + } +} +#[doc = "Field `CNTSEL` reader - Timer/counter Output Event Mode"] +pub type CNTSEL_R = crate::FieldReader; +#[doc = "Timer/counter Output Event Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum CNTSELSELECT_A { + #[doc = "0: An interrupt/event is generated when a new counter cycle starts"] + START = 0, + #[doc = "1: An interrupt/event is generated when a counter cycle ends"] + END = 1, + #[doc = "2: An interrupt/event is generated when a counter cycle ends, except for the first and last cycles"] + BETWEEN = 2, + #[doc = "3: An interrupt/event is generated when a new counter cycle starts or a counter cycle ends"] + BOUNDARY = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CNTSELSELECT_A) -> Self { + variant as _ + } +} +impl CNTSEL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CNTSELSELECT_A { + match self.bits { + 0 => CNTSELSELECT_A::START, + 1 => CNTSELSELECT_A::END, + 2 => CNTSELSELECT_A::BETWEEN, + 3 => CNTSELSELECT_A::BOUNDARY, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + *self == CNTSELSELECT_A::START + } + #[doc = "Checks if the value of the field is `END`"] + #[inline(always)] + pub fn is_end(&self) -> bool { + *self == CNTSELSELECT_A::END + } + #[doc = "Checks if the value of the field is `BETWEEN`"] + #[inline(always)] + pub fn is_between(&self) -> bool { + *self == CNTSELSELECT_A::BETWEEN + } + #[doc = "Checks if the value of the field is `BOUNDARY`"] + #[inline(always)] + pub fn is_boundary(&self) -> bool { + *self == CNTSELSELECT_A::BOUNDARY + } +} +#[doc = "Field `CNTSEL` writer - Timer/counter Output Event Mode"] +pub type CNTSEL_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, EVCTRL_SPEC, u8, CNTSELSELECT_A, 2, O>; +impl<'a, const O: u8> CNTSEL_W<'a, O> { + #[doc = "An interrupt/event is generated when a new counter cycle starts"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(CNTSELSELECT_A::START) + } + #[doc = "An interrupt/event is generated when a counter cycle ends"] + #[inline(always)] + pub fn end(self) -> &'a mut W { + self.variant(CNTSELSELECT_A::END) + } + #[doc = "An interrupt/event is generated when a counter cycle ends, except for the first and last cycles"] + #[inline(always)] + pub fn between(self) -> &'a mut W { + self.variant(CNTSELSELECT_A::BETWEEN) + } + #[doc = "An interrupt/event is generated when a new counter cycle starts or a counter cycle ends"] + #[inline(always)] + pub fn boundary(self) -> &'a mut W { + self.variant(CNTSELSELECT_A::BOUNDARY) + } +} +#[doc = "Field `OVFEO` reader - Overflow/Underflow Output Event Enable"] +pub type OVFEO_R = crate::BitReader; +#[doc = "Field `OVFEO` writer - Overflow/Underflow Output Event Enable"] +pub type OVFEO_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVCTRL_SPEC, bool, O>; +#[doc = "Field `TRGEO` reader - Retrigger Output Event Enable"] +pub type TRGEO_R = crate::BitReader; +#[doc = "Field `TRGEO` writer - Retrigger Output Event Enable"] +pub type TRGEO_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVCTRL_SPEC, bool, O>; +#[doc = "Field `CNTEO` reader - Timer/counter Output Event Enable"] +pub type CNTEO_R = crate::BitReader; +#[doc = "Field `CNTEO` writer - Timer/counter Output Event Enable"] +pub type CNTEO_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVCTRL_SPEC, bool, O>; +#[doc = "Field `TCINV0` reader - Inverted Event 0 Input Enable"] +pub type TCINV0_R = crate::BitReader; +#[doc = "Field `TCINV0` writer - Inverted Event 0 Input Enable"] +pub type TCINV0_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVCTRL_SPEC, bool, O>; +#[doc = "Field `TCINV1` reader - Inverted Event 1 Input Enable"] +pub type TCINV1_R = crate::BitReader; +#[doc = "Field `TCINV1` writer - Inverted Event 1 Input Enable"] +pub type TCINV1_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVCTRL_SPEC, bool, O>; +#[doc = "Field `TCEI0` reader - Timer/counter Event 0 Input Enable"] +pub type TCEI0_R = crate::BitReader; +#[doc = "Field `TCEI0` writer - Timer/counter Event 0 Input Enable"] +pub type TCEI0_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVCTRL_SPEC, bool, O>; +#[doc = "Field `TCEI1` reader - Timer/counter Event 1 Input Enable"] +pub type TCEI1_R = crate::BitReader; +#[doc = "Field `TCEI1` writer - Timer/counter Event 1 Input Enable"] +pub type TCEI1_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVCTRL_SPEC, bool, O>; +#[doc = "Field `MCEI0` reader - Match or Capture Channel 0 Event Input Enable"] +pub type MCEI0_R = crate::BitReader; +#[doc = "Field `MCEI0` writer - Match or Capture Channel 0 Event Input Enable"] +pub type MCEI0_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVCTRL_SPEC, bool, O>; +#[doc = "Field `MCEI1` reader - Match or Capture Channel 1 Event Input Enable"] +pub type MCEI1_R = crate::BitReader; +#[doc = "Field `MCEI1` writer - Match or Capture Channel 1 Event Input Enable"] +pub type MCEI1_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVCTRL_SPEC, bool, O>; +#[doc = "Field `MCEI2` reader - Match or Capture Channel 2 Event Input Enable"] +pub type MCEI2_R = crate::BitReader; +#[doc = "Field `MCEI2` writer - Match or Capture Channel 2 Event Input Enable"] +pub type MCEI2_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVCTRL_SPEC, bool, O>; +#[doc = "Field `MCEI3` reader - Match or Capture Channel 3 Event Input Enable"] +pub type MCEI3_R = crate::BitReader; +#[doc = "Field `MCEI3` writer - Match or Capture Channel 3 Event Input Enable"] +pub type MCEI3_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVCTRL_SPEC, bool, O>; +#[doc = "Field `MCEO0` reader - Match or Capture Channel 0 Event Output Enable"] +pub type MCEO0_R = crate::BitReader; +#[doc = "Field `MCEO0` writer - Match or Capture Channel 0 Event Output Enable"] +pub type MCEO0_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVCTRL_SPEC, bool, O>; +#[doc = "Field `MCEO1` reader - Match or Capture Channel 1 Event Output Enable"] +pub type MCEO1_R = crate::BitReader; +#[doc = "Field `MCEO1` writer - Match or Capture Channel 1 Event Output Enable"] +pub type MCEO1_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVCTRL_SPEC, bool, O>; +#[doc = "Field `MCEO2` reader - Match or Capture Channel 2 Event Output Enable"] +pub type MCEO2_R = crate::BitReader; +#[doc = "Field `MCEO2` writer - Match or Capture Channel 2 Event Output Enable"] +pub type MCEO2_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVCTRL_SPEC, bool, O>; +#[doc = "Field `MCEO3` reader - Match or Capture Channel 3 Event Output Enable"] +pub type MCEO3_R = crate::BitReader; +#[doc = "Field `MCEO3` writer - Match or Capture Channel 3 Event Output Enable"] +pub type MCEO3_W<'a, const O: u8> = crate::BitWriter<'a, u32, EVCTRL_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:2 - Timer/counter Input Event0 Action"] + #[inline(always)] + pub fn evact0(&self) -> EVACT0_R { + EVACT0_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:5 - Timer/counter Input Event1 Action"] + #[inline(always)] + pub fn evact1(&self) -> EVACT1_R { + EVACT1_R::new(((self.bits >> 3) & 7) as u8) + } + #[doc = "Bits 6:7 - Timer/counter Output Event Mode"] + #[inline(always)] + pub fn cntsel(&self) -> CNTSEL_R { + CNTSEL_R::new(((self.bits >> 6) & 3) as u8) + } + #[doc = "Bit 8 - Overflow/Underflow Output Event Enable"] + #[inline(always)] + pub fn ovfeo(&self) -> OVFEO_R { + OVFEO_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Retrigger Output Event Enable"] + #[inline(always)] + pub fn trgeo(&self) -> TRGEO_R { + TRGEO_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Timer/counter Output Event Enable"] + #[inline(always)] + pub fn cnteo(&self) -> CNTEO_R { + CNTEO_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 12 - Inverted Event 0 Input Enable"] + #[inline(always)] + pub fn tcinv0(&self) -> TCINV0_R { + TCINV0_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Inverted Event 1 Input Enable"] + #[inline(always)] + pub fn tcinv1(&self) -> TCINV1_R { + TCINV1_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Timer/counter Event 0 Input Enable"] + #[inline(always)] + pub fn tcei0(&self) -> TCEI0_R { + TCEI0_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Timer/counter Event 1 Input Enable"] + #[inline(always)] + pub fn tcei1(&self) -> TCEI1_R { + TCEI1_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Match or Capture Channel 0 Event Input Enable"] + #[inline(always)] + pub fn mcei0(&self) -> MCEI0_R { + MCEI0_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Match or Capture Channel 1 Event Input Enable"] + #[inline(always)] + pub fn mcei1(&self) -> MCEI1_R { + MCEI1_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Match or Capture Channel 2 Event Input Enable"] + #[inline(always)] + pub fn mcei2(&self) -> MCEI2_R { + MCEI2_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Match or Capture Channel 3 Event Input Enable"] + #[inline(always)] + pub fn mcei3(&self) -> MCEI3_R { + MCEI3_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 24 - Match or Capture Channel 0 Event Output Enable"] + #[inline(always)] + pub fn mceo0(&self) -> MCEO0_R { + MCEO0_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Match or Capture Channel 1 Event Output Enable"] + #[inline(always)] + pub fn mceo1(&self) -> MCEO1_R { + MCEO1_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Match or Capture Channel 2 Event Output Enable"] + #[inline(always)] + pub fn mceo2(&self) -> MCEO2_R { + MCEO2_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Match or Capture Channel 3 Event Output Enable"] + #[inline(always)] + pub fn mceo3(&self) -> MCEO3_R { + MCEO3_R::new(((self.bits >> 27) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Timer/counter Input Event0 Action"] + #[inline(always)] + #[must_use] + pub fn evact0(&mut self) -> EVACT0_W<0> { + EVACT0_W::new(self) + } + #[doc = "Bits 3:5 - Timer/counter Input Event1 Action"] + #[inline(always)] + #[must_use] + pub fn evact1(&mut self) -> EVACT1_W<3> { + EVACT1_W::new(self) + } + #[doc = "Bits 6:7 - Timer/counter Output Event Mode"] + #[inline(always)] + #[must_use] + pub fn cntsel(&mut self) -> CNTSEL_W<6> { + CNTSEL_W::new(self) + } + #[doc = "Bit 8 - Overflow/Underflow Output Event Enable"] + #[inline(always)] + #[must_use] + pub fn ovfeo(&mut self) -> OVFEO_W<8> { + OVFEO_W::new(self) + } + #[doc = "Bit 9 - Retrigger Output Event Enable"] + #[inline(always)] + #[must_use] + pub fn trgeo(&mut self) -> TRGEO_W<9> { + TRGEO_W::new(self) + } + #[doc = "Bit 10 - Timer/counter Output Event Enable"] + #[inline(always)] + #[must_use] + pub fn cnteo(&mut self) -> CNTEO_W<10> { + CNTEO_W::new(self) + } + #[doc = "Bit 12 - Inverted Event 0 Input Enable"] + #[inline(always)] + #[must_use] + pub fn tcinv0(&mut self) -> TCINV0_W<12> { + TCINV0_W::new(self) + } + #[doc = "Bit 13 - Inverted Event 1 Input Enable"] + #[inline(always)] + #[must_use] + pub fn tcinv1(&mut self) -> TCINV1_W<13> { + TCINV1_W::new(self) + } + #[doc = "Bit 14 - Timer/counter Event 0 Input Enable"] + #[inline(always)] + #[must_use] + pub fn tcei0(&mut self) -> TCEI0_W<14> { + TCEI0_W::new(self) + } + #[doc = "Bit 15 - Timer/counter Event 1 Input Enable"] + #[inline(always)] + #[must_use] + pub fn tcei1(&mut self) -> TCEI1_W<15> { + TCEI1_W::new(self) + } + #[doc = "Bit 16 - Match or Capture Channel 0 Event Input Enable"] + #[inline(always)] + #[must_use] + pub fn mcei0(&mut self) -> MCEI0_W<16> { + MCEI0_W::new(self) + } + #[doc = "Bit 17 - Match or Capture Channel 1 Event Input Enable"] + #[inline(always)] + #[must_use] + pub fn mcei1(&mut self) -> MCEI1_W<17> { + MCEI1_W::new(self) + } + #[doc = "Bit 18 - Match or Capture Channel 2 Event Input Enable"] + #[inline(always)] + #[must_use] + pub fn mcei2(&mut self) -> MCEI2_W<18> { + MCEI2_W::new(self) + } + #[doc = "Bit 19 - Match or Capture Channel 3 Event Input Enable"] + #[inline(always)] + #[must_use] + pub fn mcei3(&mut self) -> MCEI3_W<19> { + MCEI3_W::new(self) + } + #[doc = "Bit 24 - Match or Capture Channel 0 Event Output Enable"] + #[inline(always)] + #[must_use] + pub fn mceo0(&mut self) -> MCEO0_W<24> { + MCEO0_W::new(self) + } + #[doc = "Bit 25 - Match or Capture Channel 1 Event Output Enable"] + #[inline(always)] + #[must_use] + pub fn mceo1(&mut self) -> MCEO1_W<25> { + MCEO1_W::new(self) + } + #[doc = "Bit 26 - Match or Capture Channel 2 Event Output Enable"] + #[inline(always)] + #[must_use] + pub fn mceo2(&mut self) -> MCEO2_W<26> { + MCEO2_W::new(self) + } + #[doc = "Bit 27 - Match or Capture Channel 3 Event Output Enable"] + #[inline(always)] + #[must_use] + pub fn mceo3(&mut self) -> MCEO3_W<27> { + MCEO3_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tcc0/fctrla.rs b/pac/atsaml22j/src/tcc0/fctrla.rs new file mode 100644 index 000000000000..0bd6c4040389 --- /dev/null +++ b/pac/atsaml22j/src/tcc0/fctrla.rs @@ -0,0 +1,657 @@ +#[doc = "Register `FCTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FCTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SRC` reader - Fault A Source"] +pub type SRC_R = crate::FieldReader; +#[doc = "Fault A Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SRCSELECT_A { + #[doc = "0: Fault input disabled"] + DISABLE = 0, + #[doc = "1: MCEx (x=0,1) event input"] + ENABLE = 1, + #[doc = "2: Inverted MCEx (x=0,1) event input"] + INVERT = 2, + #[doc = "3: Alternate fault (A or B) state at the end of the previous period"] + ALTFAULT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SRCSELECT_A) -> Self { + variant as _ + } +} +impl SRC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SRCSELECT_A { + match self.bits { + 0 => SRCSELECT_A::DISABLE, + 1 => SRCSELECT_A::ENABLE, + 2 => SRCSELECT_A::INVERT, + 3 => SRCSELECT_A::ALTFAULT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == SRCSELECT_A::DISABLE + } + #[doc = "Checks if the value of the field is `ENABLE`"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == SRCSELECT_A::ENABLE + } + #[doc = "Checks if the value of the field is `INVERT`"] + #[inline(always)] + pub fn is_invert(&self) -> bool { + *self == SRCSELECT_A::INVERT + } + #[doc = "Checks if the value of the field is `ALTFAULT`"] + #[inline(always)] + pub fn is_altfault(&self) -> bool { + *self == SRCSELECT_A::ALTFAULT + } +} +#[doc = "Field `SRC` writer - Fault A Source"] +pub type SRC_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, FCTRLA_SPEC, u8, SRCSELECT_A, 2, O>; +impl<'a, const O: u8> SRC_W<'a, O> { + #[doc = "Fault input disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(SRCSELECT_A::DISABLE) + } + #[doc = "MCEx (x=0,1) event input"] + #[inline(always)] + pub fn enable(self) -> &'a mut W { + self.variant(SRCSELECT_A::ENABLE) + } + #[doc = "Inverted MCEx (x=0,1) event input"] + #[inline(always)] + pub fn invert(self) -> &'a mut W { + self.variant(SRCSELECT_A::INVERT) + } + #[doc = "Alternate fault (A or B) state at the end of the previous period"] + #[inline(always)] + pub fn altfault(self) -> &'a mut W { + self.variant(SRCSELECT_A::ALTFAULT) + } +} +#[doc = "Field `KEEP` reader - Fault A Keeper"] +pub type KEEP_R = crate::BitReader; +#[doc = "Field `KEEP` writer - Fault A Keeper"] +pub type KEEP_W<'a, const O: u8> = crate::BitWriter<'a, u32, FCTRLA_SPEC, bool, O>; +#[doc = "Field `QUAL` reader - Fault A Qualification"] +pub type QUAL_R = crate::BitReader; +#[doc = "Field `QUAL` writer - Fault A Qualification"] +pub type QUAL_W<'a, const O: u8> = crate::BitWriter<'a, u32, FCTRLA_SPEC, bool, O>; +#[doc = "Field `BLANK` reader - Fault A Blanking Mode"] +pub type BLANK_R = crate::FieldReader; +#[doc = "Fault A Blanking Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum BLANKSELECT_A { + #[doc = "0: Blanking applied from start of the ramp"] + START = 0, + #[doc = "1: Blanking applied from rising edge of the output waveform"] + RISE = 1, + #[doc = "2: Blanking applied from falling edge of the output waveform"] + FALL = 2, + #[doc = "3: Blanking applied from each toggle of the output waveform"] + BOTH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: BLANKSELECT_A) -> Self { + variant as _ + } +} +impl BLANK_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> BLANKSELECT_A { + match self.bits { + 0 => BLANKSELECT_A::START, + 1 => BLANKSELECT_A::RISE, + 2 => BLANKSELECT_A::FALL, + 3 => BLANKSELECT_A::BOTH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + *self == BLANKSELECT_A::START + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + *self == BLANKSELECT_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + *self == BLANKSELECT_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + *self == BLANKSELECT_A::BOTH + } +} +#[doc = "Field `BLANK` writer - Fault A Blanking Mode"] +pub type BLANK_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, FCTRLA_SPEC, u8, BLANKSELECT_A, 2, O>; +impl<'a, const O: u8> BLANK_W<'a, O> { + #[doc = "Blanking applied from start of the ramp"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(BLANKSELECT_A::START) + } + #[doc = "Blanking applied from rising edge of the output waveform"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(BLANKSELECT_A::RISE) + } + #[doc = "Blanking applied from falling edge of the output waveform"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(BLANKSELECT_A::FALL) + } + #[doc = "Blanking applied from each toggle of the output waveform"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(BLANKSELECT_A::BOTH) + } +} +#[doc = "Field `RESTART` reader - Fault A Restart"] +pub type RESTART_R = crate::BitReader; +#[doc = "Field `RESTART` writer - Fault A Restart"] +pub type RESTART_W<'a, const O: u8> = crate::BitWriter<'a, u32, FCTRLA_SPEC, bool, O>; +#[doc = "Field `HALT` reader - Fault A Halt Mode"] +pub type HALT_R = crate::FieldReader; +#[doc = "Fault A Halt Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum HALTSELECT_A { + #[doc = "0: Halt action disabled"] + DISABLE = 0, + #[doc = "1: Hardware halt action"] + HW = 1, + #[doc = "2: Software halt action"] + SW = 2, + #[doc = "3: Non-recoverable fault"] + NR = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: HALTSELECT_A) -> Self { + variant as _ + } +} +impl HALT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> HALTSELECT_A { + match self.bits { + 0 => HALTSELECT_A::DISABLE, + 1 => HALTSELECT_A::HW, + 2 => HALTSELECT_A::SW, + 3 => HALTSELECT_A::NR, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == HALTSELECT_A::DISABLE + } + #[doc = "Checks if the value of the field is `HW`"] + #[inline(always)] + pub fn is_hw(&self) -> bool { + *self == HALTSELECT_A::HW + } + #[doc = "Checks if the value of the field is `SW`"] + #[inline(always)] + pub fn is_sw(&self) -> bool { + *self == HALTSELECT_A::SW + } + #[doc = "Checks if the value of the field is `NR`"] + #[inline(always)] + pub fn is_nr(&self) -> bool { + *self == HALTSELECT_A::NR + } +} +#[doc = "Field `HALT` writer - Fault A Halt Mode"] +pub type HALT_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, FCTRLA_SPEC, u8, HALTSELECT_A, 2, O>; +impl<'a, const O: u8> HALT_W<'a, O> { + #[doc = "Halt action disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(HALTSELECT_A::DISABLE) + } + #[doc = "Hardware halt action"] + #[inline(always)] + pub fn hw(self) -> &'a mut W { + self.variant(HALTSELECT_A::HW) + } + #[doc = "Software halt action"] + #[inline(always)] + pub fn sw(self) -> &'a mut W { + self.variant(HALTSELECT_A::SW) + } + #[doc = "Non-recoverable fault"] + #[inline(always)] + pub fn nr(self) -> &'a mut W { + self.variant(HALTSELECT_A::NR) + } +} +#[doc = "Field `CHSEL` reader - Fault A Capture Channel"] +pub type CHSEL_R = crate::FieldReader; +#[doc = "Fault A Capture Channel\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum CHSELSELECT_A { + #[doc = "0: Capture value stored in channel 0"] + CC0 = 0, + #[doc = "1: Capture value stored in channel 1"] + CC1 = 1, + #[doc = "2: Capture value stored in channel 2"] + CC2 = 2, + #[doc = "3: Capture value stored in channel 3"] + CC3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSELSELECT_A) -> Self { + variant as _ + } +} +impl CHSEL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CHSELSELECT_A { + match self.bits { + 0 => CHSELSELECT_A::CC0, + 1 => CHSELSELECT_A::CC1, + 2 => CHSELSELECT_A::CC2, + 3 => CHSELSELECT_A::CC3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CC0`"] + #[inline(always)] + pub fn is_cc0(&self) -> bool { + *self == CHSELSELECT_A::CC0 + } + #[doc = "Checks if the value of the field is `CC1`"] + #[inline(always)] + pub fn is_cc1(&self) -> bool { + *self == CHSELSELECT_A::CC1 + } + #[doc = "Checks if the value of the field is `CC2`"] + #[inline(always)] + pub fn is_cc2(&self) -> bool { + *self == CHSELSELECT_A::CC2 + } + #[doc = "Checks if the value of the field is `CC3`"] + #[inline(always)] + pub fn is_cc3(&self) -> bool { + *self == CHSELSELECT_A::CC3 + } +} +#[doc = "Field `CHSEL` writer - Fault A Capture Channel"] +pub type CHSEL_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, FCTRLA_SPEC, u8, CHSELSELECT_A, 2, O>; +impl<'a, const O: u8> CHSEL_W<'a, O> { + #[doc = "Capture value stored in channel 0"] + #[inline(always)] + pub fn cc0(self) -> &'a mut W { + self.variant(CHSELSELECT_A::CC0) + } + #[doc = "Capture value stored in channel 1"] + #[inline(always)] + pub fn cc1(self) -> &'a mut W { + self.variant(CHSELSELECT_A::CC1) + } + #[doc = "Capture value stored in channel 2"] + #[inline(always)] + pub fn cc2(self) -> &'a mut W { + self.variant(CHSELSELECT_A::CC2) + } + #[doc = "Capture value stored in channel 3"] + #[inline(always)] + pub fn cc3(self) -> &'a mut W { + self.variant(CHSELSELECT_A::CC3) + } +} +#[doc = "Field `CAPTURE` reader - Fault A Capture Action"] +pub type CAPTURE_R = crate::FieldReader; +#[doc = "Fault A Capture Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum CAPTURESELECT_A { + #[doc = "0: No capture"] + DISABLE = 0, + #[doc = "1: Capture on fault"] + CAPT = 1, + #[doc = "2: Minimum capture"] + CAPTMIN = 2, + #[doc = "3: Maximum capture"] + CAPTMAX = 3, + #[doc = "4: Minimum local detection"] + LOCMIN = 4, + #[doc = "5: Maximum local detection"] + LOCMAX = 5, + #[doc = "6: Minimum and maximum local detection"] + DERIV0 = 6, + #[doc = "7: Capture with ramp index as MSB value"] + CAPTMARK = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CAPTURESELECT_A) -> Self { + variant as _ + } +} +impl CAPTURE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CAPTURESELECT_A { + match self.bits { + 0 => CAPTURESELECT_A::DISABLE, + 1 => CAPTURESELECT_A::CAPT, + 2 => CAPTURESELECT_A::CAPTMIN, + 3 => CAPTURESELECT_A::CAPTMAX, + 4 => CAPTURESELECT_A::LOCMIN, + 5 => CAPTURESELECT_A::LOCMAX, + 6 => CAPTURESELECT_A::DERIV0, + 7 => CAPTURESELECT_A::CAPTMARK, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == CAPTURESELECT_A::DISABLE + } + #[doc = "Checks if the value of the field is `CAPT`"] + #[inline(always)] + pub fn is_capt(&self) -> bool { + *self == CAPTURESELECT_A::CAPT + } + #[doc = "Checks if the value of the field is `CAPTMIN`"] + #[inline(always)] + pub fn is_captmin(&self) -> bool { + *self == CAPTURESELECT_A::CAPTMIN + } + #[doc = "Checks if the value of the field is `CAPTMAX`"] + #[inline(always)] + pub fn is_captmax(&self) -> bool { + *self == CAPTURESELECT_A::CAPTMAX + } + #[doc = "Checks if the value of the field is `LOCMIN`"] + #[inline(always)] + pub fn is_locmin(&self) -> bool { + *self == CAPTURESELECT_A::LOCMIN + } + #[doc = "Checks if the value of the field is `LOCMAX`"] + #[inline(always)] + pub fn is_locmax(&self) -> bool { + *self == CAPTURESELECT_A::LOCMAX + } + #[doc = "Checks if the value of the field is `DERIV0`"] + #[inline(always)] + pub fn is_deriv0(&self) -> bool { + *self == CAPTURESELECT_A::DERIV0 + } + #[doc = "Checks if the value of the field is `CAPTMARK`"] + #[inline(always)] + pub fn is_captmark(&self) -> bool { + *self == CAPTURESELECT_A::CAPTMARK + } +} +#[doc = "Field `CAPTURE` writer - Fault A Capture Action"] +pub type CAPTURE_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, FCTRLA_SPEC, u8, CAPTURESELECT_A, 3, O>; +impl<'a, const O: u8> CAPTURE_W<'a, O> { + #[doc = "No capture"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(CAPTURESELECT_A::DISABLE) + } + #[doc = "Capture on fault"] + #[inline(always)] + pub fn capt(self) -> &'a mut W { + self.variant(CAPTURESELECT_A::CAPT) + } + #[doc = "Minimum capture"] + #[inline(always)] + pub fn captmin(self) -> &'a mut W { + self.variant(CAPTURESELECT_A::CAPTMIN) + } + #[doc = "Maximum capture"] + #[inline(always)] + pub fn captmax(self) -> &'a mut W { + self.variant(CAPTURESELECT_A::CAPTMAX) + } + #[doc = "Minimum local detection"] + #[inline(always)] + pub fn locmin(self) -> &'a mut W { + self.variant(CAPTURESELECT_A::LOCMIN) + } + #[doc = "Maximum local detection"] + #[inline(always)] + pub fn locmax(self) -> &'a mut W { + self.variant(CAPTURESELECT_A::LOCMAX) + } + #[doc = "Minimum and maximum local detection"] + #[inline(always)] + pub fn deriv0(self) -> &'a mut W { + self.variant(CAPTURESELECT_A::DERIV0) + } + #[doc = "Capture with ramp index as MSB value"] + #[inline(always)] + pub fn captmark(self) -> &'a mut W { + self.variant(CAPTURESELECT_A::CAPTMARK) + } +} +#[doc = "Field `BLANKPRESC` reader - Fault A Blanking Prescaler"] +pub type BLANKPRESC_R = crate::BitReader; +#[doc = "Field `BLANKPRESC` writer - Fault A Blanking Prescaler"] +pub type BLANKPRESC_W<'a, const O: u8> = crate::BitWriter<'a, u32, FCTRLA_SPEC, bool, O>; +#[doc = "Field `BLANKVAL` reader - Fault A Blanking Time"] +pub type BLANKVAL_R = crate::FieldReader; +#[doc = "Field `BLANKVAL` writer - Fault A Blanking Time"] +pub type BLANKVAL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FCTRLA_SPEC, u8, u8, 8, O>; +#[doc = "Field `FILTERVAL` reader - Fault A Filter Value"] +pub type FILTERVAL_R = crate::FieldReader; +#[doc = "Field `FILTERVAL` writer - Fault A Filter Value"] +pub type FILTERVAL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FCTRLA_SPEC, u8, u8, 4, O>; +impl R { + #[doc = "Bits 0:1 - Fault A Source"] + #[inline(always)] + pub fn src(&self) -> SRC_R { + SRC_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 3 - Fault A Keeper"] + #[inline(always)] + pub fn keep(&self) -> KEEP_R { + KEEP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Fault A Qualification"] + #[inline(always)] + pub fn qual(&self) -> QUAL_R { + QUAL_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - Fault A Blanking Mode"] + #[inline(always)] + pub fn blank(&self) -> BLANK_R { + BLANK_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - Fault A Restart"] + #[inline(always)] + pub fn restart(&self) -> RESTART_R { + RESTART_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:9 - Fault A Halt Mode"] + #[inline(always)] + pub fn halt(&self) -> HALT_R { + HALT_R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:11 - Fault A Capture Channel"] + #[inline(always)] + pub fn chsel(&self) -> CHSEL_R { + CHSEL_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - Fault A Capture Action"] + #[inline(always)] + pub fn capture(&self) -> CAPTURE_R { + CAPTURE_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - Fault A Blanking Prescaler"] + #[inline(always)] + pub fn blankpresc(&self) -> BLANKPRESC_R { + BLANKPRESC_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:23 - Fault A Blanking Time"] + #[inline(always)] + pub fn blankval(&self) -> BLANKVAL_R { + BLANKVAL_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:27 - Fault A Filter Value"] + #[inline(always)] + pub fn filterval(&self) -> FILTERVAL_R { + FILTERVAL_R::new(((self.bits >> 24) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Fault A Source"] + #[inline(always)] + #[must_use] + pub fn src(&mut self) -> SRC_W<0> { + SRC_W::new(self) + } + #[doc = "Bit 3 - Fault A Keeper"] + #[inline(always)] + #[must_use] + pub fn keep(&mut self) -> KEEP_W<3> { + KEEP_W::new(self) + } + #[doc = "Bit 4 - Fault A Qualification"] + #[inline(always)] + #[must_use] + pub fn qual(&mut self) -> QUAL_W<4> { + QUAL_W::new(self) + } + #[doc = "Bits 5:6 - Fault A Blanking Mode"] + #[inline(always)] + #[must_use] + pub fn blank(&mut self) -> BLANK_W<5> { + BLANK_W::new(self) + } + #[doc = "Bit 7 - Fault A Restart"] + #[inline(always)] + #[must_use] + pub fn restart(&mut self) -> RESTART_W<7> { + RESTART_W::new(self) + } + #[doc = "Bits 8:9 - Fault A Halt Mode"] + #[inline(always)] + #[must_use] + pub fn halt(&mut self) -> HALT_W<8> { + HALT_W::new(self) + } + #[doc = "Bits 10:11 - Fault A Capture Channel"] + #[inline(always)] + #[must_use] + pub fn chsel(&mut self) -> CHSEL_W<10> { + CHSEL_W::new(self) + } + #[doc = "Bits 12:14 - Fault A Capture Action"] + #[inline(always)] + #[must_use] + pub fn capture(&mut self) -> CAPTURE_W<12> { + CAPTURE_W::new(self) + } + #[doc = "Bit 15 - Fault A Blanking Prescaler"] + #[inline(always)] + #[must_use] + pub fn blankpresc(&mut self) -> BLANKPRESC_W<15> { + BLANKPRESC_W::new(self) + } + #[doc = "Bits 16:23 - Fault A Blanking Time"] + #[inline(always)] + #[must_use] + pub fn blankval(&mut self) -> BLANKVAL_W<16> { + BLANKVAL_W::new(self) + } + #[doc = "Bits 24:27 - Fault A Filter Value"] + #[inline(always)] + #[must_use] + pub fn filterval(&mut self) -> FILTERVAL_W<24> { + FILTERVAL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Recoverable Fault A Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fctrla](index.html) module"] +pub struct FCTRLA_SPEC; +impl crate::RegisterSpec for FCTRLA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [fctrla::R](R) reader structure"] +impl crate::Readable for FCTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [fctrla::W](W) writer structure"] +impl crate::Writable for FCTRLA_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FCTRLA to value 0"] +impl crate::Resettable for FCTRLA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tcc0/fctrlb.rs b/pac/atsaml22j/src/tcc0/fctrlb.rs new file mode 100644 index 000000000000..4ee6fc1d381c --- /dev/null +++ b/pac/atsaml22j/src/tcc0/fctrlb.rs @@ -0,0 +1,657 @@ +#[doc = "Register `FCTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `FCTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SRC` reader - Fault B Source"] +pub type SRC_R = crate::FieldReader; +#[doc = "Fault B Source\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SRCSELECT_A { + #[doc = "0: Fault input disabled"] + DISABLE = 0, + #[doc = "1: MCEx (x=0,1) event input"] + ENABLE = 1, + #[doc = "2: Inverted MCEx (x=0,1) event input"] + INVERT = 2, + #[doc = "3: Alternate fault (A or B) state at the end of the previous period"] + ALTFAULT = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SRCSELECT_A) -> Self { + variant as _ + } +} +impl SRC_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SRCSELECT_A { + match self.bits { + 0 => SRCSELECT_A::DISABLE, + 1 => SRCSELECT_A::ENABLE, + 2 => SRCSELECT_A::INVERT, + 3 => SRCSELECT_A::ALTFAULT, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == SRCSELECT_A::DISABLE + } + #[doc = "Checks if the value of the field is `ENABLE`"] + #[inline(always)] + pub fn is_enable(&self) -> bool { + *self == SRCSELECT_A::ENABLE + } + #[doc = "Checks if the value of the field is `INVERT`"] + #[inline(always)] + pub fn is_invert(&self) -> bool { + *self == SRCSELECT_A::INVERT + } + #[doc = "Checks if the value of the field is `ALTFAULT`"] + #[inline(always)] + pub fn is_altfault(&self) -> bool { + *self == SRCSELECT_A::ALTFAULT + } +} +#[doc = "Field `SRC` writer - Fault B Source"] +pub type SRC_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, FCTRLB_SPEC, u8, SRCSELECT_A, 2, O>; +impl<'a, const O: u8> SRC_W<'a, O> { + #[doc = "Fault input disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(SRCSELECT_A::DISABLE) + } + #[doc = "MCEx (x=0,1) event input"] + #[inline(always)] + pub fn enable(self) -> &'a mut W { + self.variant(SRCSELECT_A::ENABLE) + } + #[doc = "Inverted MCEx (x=0,1) event input"] + #[inline(always)] + pub fn invert(self) -> &'a mut W { + self.variant(SRCSELECT_A::INVERT) + } + #[doc = "Alternate fault (A or B) state at the end of the previous period"] + #[inline(always)] + pub fn altfault(self) -> &'a mut W { + self.variant(SRCSELECT_A::ALTFAULT) + } +} +#[doc = "Field `KEEP` reader - Fault B Keeper"] +pub type KEEP_R = crate::BitReader; +#[doc = "Field `KEEP` writer - Fault B Keeper"] +pub type KEEP_W<'a, const O: u8> = crate::BitWriter<'a, u32, FCTRLB_SPEC, bool, O>; +#[doc = "Field `QUAL` reader - Fault B Qualification"] +pub type QUAL_R = crate::BitReader; +#[doc = "Field `QUAL` writer - Fault B Qualification"] +pub type QUAL_W<'a, const O: u8> = crate::BitWriter<'a, u32, FCTRLB_SPEC, bool, O>; +#[doc = "Field `BLANK` reader - Fault B Blanking Mode"] +pub type BLANK_R = crate::FieldReader; +#[doc = "Fault B Blanking Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum BLANKSELECT_A { + #[doc = "0: Blanking applied from start of the ramp"] + START = 0, + #[doc = "1: Blanking applied from rising edge of the output waveform"] + RISE = 1, + #[doc = "2: Blanking applied from falling edge of the output waveform"] + FALL = 2, + #[doc = "3: Blanking applied from each toggle of the output waveform"] + BOTH = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: BLANKSELECT_A) -> Self { + variant as _ + } +} +impl BLANK_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> BLANKSELECT_A { + match self.bits { + 0 => BLANKSELECT_A::START, + 1 => BLANKSELECT_A::RISE, + 2 => BLANKSELECT_A::FALL, + 3 => BLANKSELECT_A::BOTH, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `START`"] + #[inline(always)] + pub fn is_start(&self) -> bool { + *self == BLANKSELECT_A::START + } + #[doc = "Checks if the value of the field is `RISE`"] + #[inline(always)] + pub fn is_rise(&self) -> bool { + *self == BLANKSELECT_A::RISE + } + #[doc = "Checks if the value of the field is `FALL`"] + #[inline(always)] + pub fn is_fall(&self) -> bool { + *self == BLANKSELECT_A::FALL + } + #[doc = "Checks if the value of the field is `BOTH`"] + #[inline(always)] + pub fn is_both(&self) -> bool { + *self == BLANKSELECT_A::BOTH + } +} +#[doc = "Field `BLANK` writer - Fault B Blanking Mode"] +pub type BLANK_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, FCTRLB_SPEC, u8, BLANKSELECT_A, 2, O>; +impl<'a, const O: u8> BLANK_W<'a, O> { + #[doc = "Blanking applied from start of the ramp"] + #[inline(always)] + pub fn start(self) -> &'a mut W { + self.variant(BLANKSELECT_A::START) + } + #[doc = "Blanking applied from rising edge of the output waveform"] + #[inline(always)] + pub fn rise(self) -> &'a mut W { + self.variant(BLANKSELECT_A::RISE) + } + #[doc = "Blanking applied from falling edge of the output waveform"] + #[inline(always)] + pub fn fall(self) -> &'a mut W { + self.variant(BLANKSELECT_A::FALL) + } + #[doc = "Blanking applied from each toggle of the output waveform"] + #[inline(always)] + pub fn both(self) -> &'a mut W { + self.variant(BLANKSELECT_A::BOTH) + } +} +#[doc = "Field `RESTART` reader - Fault B Restart"] +pub type RESTART_R = crate::BitReader; +#[doc = "Field `RESTART` writer - Fault B Restart"] +pub type RESTART_W<'a, const O: u8> = crate::BitWriter<'a, u32, FCTRLB_SPEC, bool, O>; +#[doc = "Field `HALT` reader - Fault B Halt Mode"] +pub type HALT_R = crate::FieldReader; +#[doc = "Fault B Halt Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum HALTSELECT_A { + #[doc = "0: Halt action disabled"] + DISABLE = 0, + #[doc = "1: Hardware halt action"] + HW = 1, + #[doc = "2: Software halt action"] + SW = 2, + #[doc = "3: Non-recoverable fault"] + NR = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: HALTSELECT_A) -> Self { + variant as _ + } +} +impl HALT_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> HALTSELECT_A { + match self.bits { + 0 => HALTSELECT_A::DISABLE, + 1 => HALTSELECT_A::HW, + 2 => HALTSELECT_A::SW, + 3 => HALTSELECT_A::NR, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == HALTSELECT_A::DISABLE + } + #[doc = "Checks if the value of the field is `HW`"] + #[inline(always)] + pub fn is_hw(&self) -> bool { + *self == HALTSELECT_A::HW + } + #[doc = "Checks if the value of the field is `SW`"] + #[inline(always)] + pub fn is_sw(&self) -> bool { + *self == HALTSELECT_A::SW + } + #[doc = "Checks if the value of the field is `NR`"] + #[inline(always)] + pub fn is_nr(&self) -> bool { + *self == HALTSELECT_A::NR + } +} +#[doc = "Field `HALT` writer - Fault B Halt Mode"] +pub type HALT_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, FCTRLB_SPEC, u8, HALTSELECT_A, 2, O>; +impl<'a, const O: u8> HALT_W<'a, O> { + #[doc = "Halt action disabled"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(HALTSELECT_A::DISABLE) + } + #[doc = "Hardware halt action"] + #[inline(always)] + pub fn hw(self) -> &'a mut W { + self.variant(HALTSELECT_A::HW) + } + #[doc = "Software halt action"] + #[inline(always)] + pub fn sw(self) -> &'a mut W { + self.variant(HALTSELECT_A::SW) + } + #[doc = "Non-recoverable fault"] + #[inline(always)] + pub fn nr(self) -> &'a mut W { + self.variant(HALTSELECT_A::NR) + } +} +#[doc = "Field `CHSEL` reader - Fault B Capture Channel"] +pub type CHSEL_R = crate::FieldReader; +#[doc = "Fault B Capture Channel\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum CHSELSELECT_A { + #[doc = "0: Capture value stored in channel 0"] + CC0 = 0, + #[doc = "1: Capture value stored in channel 1"] + CC1 = 1, + #[doc = "2: Capture value stored in channel 2"] + CC2 = 2, + #[doc = "3: Capture value stored in channel 3"] + CC3 = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CHSELSELECT_A) -> Self { + variant as _ + } +} +impl CHSEL_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CHSELSELECT_A { + match self.bits { + 0 => CHSELSELECT_A::CC0, + 1 => CHSELSELECT_A::CC1, + 2 => CHSELSELECT_A::CC2, + 3 => CHSELSELECT_A::CC3, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `CC0`"] + #[inline(always)] + pub fn is_cc0(&self) -> bool { + *self == CHSELSELECT_A::CC0 + } + #[doc = "Checks if the value of the field is `CC1`"] + #[inline(always)] + pub fn is_cc1(&self) -> bool { + *self == CHSELSELECT_A::CC1 + } + #[doc = "Checks if the value of the field is `CC2`"] + #[inline(always)] + pub fn is_cc2(&self) -> bool { + *self == CHSELSELECT_A::CC2 + } + #[doc = "Checks if the value of the field is `CC3`"] + #[inline(always)] + pub fn is_cc3(&self) -> bool { + *self == CHSELSELECT_A::CC3 + } +} +#[doc = "Field `CHSEL` writer - Fault B Capture Channel"] +pub type CHSEL_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, FCTRLB_SPEC, u8, CHSELSELECT_A, 2, O>; +impl<'a, const O: u8> CHSEL_W<'a, O> { + #[doc = "Capture value stored in channel 0"] + #[inline(always)] + pub fn cc0(self) -> &'a mut W { + self.variant(CHSELSELECT_A::CC0) + } + #[doc = "Capture value stored in channel 1"] + #[inline(always)] + pub fn cc1(self) -> &'a mut W { + self.variant(CHSELSELECT_A::CC1) + } + #[doc = "Capture value stored in channel 2"] + #[inline(always)] + pub fn cc2(self) -> &'a mut W { + self.variant(CHSELSELECT_A::CC2) + } + #[doc = "Capture value stored in channel 3"] + #[inline(always)] + pub fn cc3(self) -> &'a mut W { + self.variant(CHSELSELECT_A::CC3) + } +} +#[doc = "Field `CAPTURE` reader - Fault B Capture Action"] +pub type CAPTURE_R = crate::FieldReader; +#[doc = "Fault B Capture Action\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum CAPTURESELECT_A { + #[doc = "0: No capture"] + DISABLE = 0, + #[doc = "1: Capture on fault"] + CAPT = 1, + #[doc = "2: Minimum capture"] + CAPTMIN = 2, + #[doc = "3: Maximum capture"] + CAPTMAX = 3, + #[doc = "4: Minimum local detection"] + LOCMIN = 4, + #[doc = "5: Maximum local detection"] + LOCMAX = 5, + #[doc = "6: Minimum and maximum local detection"] + DERIV0 = 6, + #[doc = "7: Capture with ramp index as MSB value"] + CAPTMARK = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CAPTURESELECT_A) -> Self { + variant as _ + } +} +impl CAPTURE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> CAPTURESELECT_A { + match self.bits { + 0 => CAPTURESELECT_A::DISABLE, + 1 => CAPTURESELECT_A::CAPT, + 2 => CAPTURESELECT_A::CAPTMIN, + 3 => CAPTURESELECT_A::CAPTMAX, + 4 => CAPTURESELECT_A::LOCMIN, + 5 => CAPTURESELECT_A::LOCMAX, + 6 => CAPTURESELECT_A::DERIV0, + 7 => CAPTURESELECT_A::CAPTMARK, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `DISABLE`"] + #[inline(always)] + pub fn is_disable(&self) -> bool { + *self == CAPTURESELECT_A::DISABLE + } + #[doc = "Checks if the value of the field is `CAPT`"] + #[inline(always)] + pub fn is_capt(&self) -> bool { + *self == CAPTURESELECT_A::CAPT + } + #[doc = "Checks if the value of the field is `CAPTMIN`"] + #[inline(always)] + pub fn is_captmin(&self) -> bool { + *self == CAPTURESELECT_A::CAPTMIN + } + #[doc = "Checks if the value of the field is `CAPTMAX`"] + #[inline(always)] + pub fn is_captmax(&self) -> bool { + *self == CAPTURESELECT_A::CAPTMAX + } + #[doc = "Checks if the value of the field is `LOCMIN`"] + #[inline(always)] + pub fn is_locmin(&self) -> bool { + *self == CAPTURESELECT_A::LOCMIN + } + #[doc = "Checks if the value of the field is `LOCMAX`"] + #[inline(always)] + pub fn is_locmax(&self) -> bool { + *self == CAPTURESELECT_A::LOCMAX + } + #[doc = "Checks if the value of the field is `DERIV0`"] + #[inline(always)] + pub fn is_deriv0(&self) -> bool { + *self == CAPTURESELECT_A::DERIV0 + } + #[doc = "Checks if the value of the field is `CAPTMARK`"] + #[inline(always)] + pub fn is_captmark(&self) -> bool { + *self == CAPTURESELECT_A::CAPTMARK + } +} +#[doc = "Field `CAPTURE` writer - Fault B Capture Action"] +pub type CAPTURE_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, FCTRLB_SPEC, u8, CAPTURESELECT_A, 3, O>; +impl<'a, const O: u8> CAPTURE_W<'a, O> { + #[doc = "No capture"] + #[inline(always)] + pub fn disable(self) -> &'a mut W { + self.variant(CAPTURESELECT_A::DISABLE) + } + #[doc = "Capture on fault"] + #[inline(always)] + pub fn capt(self) -> &'a mut W { + self.variant(CAPTURESELECT_A::CAPT) + } + #[doc = "Minimum capture"] + #[inline(always)] + pub fn captmin(self) -> &'a mut W { + self.variant(CAPTURESELECT_A::CAPTMIN) + } + #[doc = "Maximum capture"] + #[inline(always)] + pub fn captmax(self) -> &'a mut W { + self.variant(CAPTURESELECT_A::CAPTMAX) + } + #[doc = "Minimum local detection"] + #[inline(always)] + pub fn locmin(self) -> &'a mut W { + self.variant(CAPTURESELECT_A::LOCMIN) + } + #[doc = "Maximum local detection"] + #[inline(always)] + pub fn locmax(self) -> &'a mut W { + self.variant(CAPTURESELECT_A::LOCMAX) + } + #[doc = "Minimum and maximum local detection"] + #[inline(always)] + pub fn deriv0(self) -> &'a mut W { + self.variant(CAPTURESELECT_A::DERIV0) + } + #[doc = "Capture with ramp index as MSB value"] + #[inline(always)] + pub fn captmark(self) -> &'a mut W { + self.variant(CAPTURESELECT_A::CAPTMARK) + } +} +#[doc = "Field `BLANKPRESC` reader - Fault B Blanking Prescaler"] +pub type BLANKPRESC_R = crate::BitReader; +#[doc = "Field `BLANKPRESC` writer - Fault B Blanking Prescaler"] +pub type BLANKPRESC_W<'a, const O: u8> = crate::BitWriter<'a, u32, FCTRLB_SPEC, bool, O>; +#[doc = "Field `BLANKVAL` reader - Fault B Blanking Time"] +pub type BLANKVAL_R = crate::FieldReader; +#[doc = "Field `BLANKVAL` writer - Fault B Blanking Time"] +pub type BLANKVAL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FCTRLB_SPEC, u8, u8, 8, O>; +#[doc = "Field `FILTERVAL` reader - Fault B Filter Value"] +pub type FILTERVAL_R = crate::FieldReader; +#[doc = "Field `FILTERVAL` writer - Fault B Filter Value"] +pub type FILTERVAL_W<'a, const O: u8> = crate::FieldWriter<'a, u32, FCTRLB_SPEC, u8, u8, 4, O>; +impl R { + #[doc = "Bits 0:1 - Fault B Source"] + #[inline(always)] + pub fn src(&self) -> SRC_R { + SRC_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 3 - Fault B Keeper"] + #[inline(always)] + pub fn keep(&self) -> KEEP_R { + KEEP_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Fault B Qualification"] + #[inline(always)] + pub fn qual(&self) -> QUAL_R { + QUAL_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bits 5:6 - Fault B Blanking Mode"] + #[inline(always)] + pub fn blank(&self) -> BLANK_R { + BLANK_R::new(((self.bits >> 5) & 3) as u8) + } + #[doc = "Bit 7 - Fault B Restart"] + #[inline(always)] + pub fn restart(&self) -> RESTART_R { + RESTART_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bits 8:9 - Fault B Halt Mode"] + #[inline(always)] + pub fn halt(&self) -> HALT_R { + HALT_R::new(((self.bits >> 8) & 3) as u8) + } + #[doc = "Bits 10:11 - Fault B Capture Channel"] + #[inline(always)] + pub fn chsel(&self) -> CHSEL_R { + CHSEL_R::new(((self.bits >> 10) & 3) as u8) + } + #[doc = "Bits 12:14 - Fault B Capture Action"] + #[inline(always)] + pub fn capture(&self) -> CAPTURE_R { + CAPTURE_R::new(((self.bits >> 12) & 7) as u8) + } + #[doc = "Bit 15 - Fault B Blanking Prescaler"] + #[inline(always)] + pub fn blankpresc(&self) -> BLANKPRESC_R { + BLANKPRESC_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bits 16:23 - Fault B Blanking Time"] + #[inline(always)] + pub fn blankval(&self) -> BLANKVAL_R { + BLANKVAL_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:27 - Fault B Filter Value"] + #[inline(always)] + pub fn filterval(&self) -> FILTERVAL_R { + FILTERVAL_R::new(((self.bits >> 24) & 0x0f) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Fault B Source"] + #[inline(always)] + #[must_use] + pub fn src(&mut self) -> SRC_W<0> { + SRC_W::new(self) + } + #[doc = "Bit 3 - Fault B Keeper"] + #[inline(always)] + #[must_use] + pub fn keep(&mut self) -> KEEP_W<3> { + KEEP_W::new(self) + } + #[doc = "Bit 4 - Fault B Qualification"] + #[inline(always)] + #[must_use] + pub fn qual(&mut self) -> QUAL_W<4> { + QUAL_W::new(self) + } + #[doc = "Bits 5:6 - Fault B Blanking Mode"] + #[inline(always)] + #[must_use] + pub fn blank(&mut self) -> BLANK_W<5> { + BLANK_W::new(self) + } + #[doc = "Bit 7 - Fault B Restart"] + #[inline(always)] + #[must_use] + pub fn restart(&mut self) -> RESTART_W<7> { + RESTART_W::new(self) + } + #[doc = "Bits 8:9 - Fault B Halt Mode"] + #[inline(always)] + #[must_use] + pub fn halt(&mut self) -> HALT_W<8> { + HALT_W::new(self) + } + #[doc = "Bits 10:11 - Fault B Capture Channel"] + #[inline(always)] + #[must_use] + pub fn chsel(&mut self) -> CHSEL_W<10> { + CHSEL_W::new(self) + } + #[doc = "Bits 12:14 - Fault B Capture Action"] + #[inline(always)] + #[must_use] + pub fn capture(&mut self) -> CAPTURE_W<12> { + CAPTURE_W::new(self) + } + #[doc = "Bit 15 - Fault B Blanking Prescaler"] + #[inline(always)] + #[must_use] + pub fn blankpresc(&mut self) -> BLANKPRESC_W<15> { + BLANKPRESC_W::new(self) + } + #[doc = "Bits 16:23 - Fault B Blanking Time"] + #[inline(always)] + #[must_use] + pub fn blankval(&mut self) -> BLANKVAL_W<16> { + BLANKVAL_W::new(self) + } + #[doc = "Bits 24:27 - Fault B Filter Value"] + #[inline(always)] + #[must_use] + pub fn filterval(&mut self) -> FILTERVAL_W<24> { + FILTERVAL_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Recoverable Fault B Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fctrlb](index.html) module"] +pub struct FCTRLB_SPEC; +impl crate::RegisterSpec for FCTRLB_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [fctrlb::R](R) reader structure"] +impl crate::Readable for FCTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [fctrlb::W](W) writer structure"] +impl crate::Writable for FCTRLB_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets FCTRLB to value 0"] +impl crate::Resettable for FCTRLB_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tcc0/intenclr.rs b/pac/atsaml22j/src/tcc0/intenclr.rs new file mode 100644 index 000000000000..918e3591a4bb --- /dev/null +++ b/pac/atsaml22j/src/tcc0/intenclr.rs @@ -0,0 +1,275 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub type OVF_R = crate::BitReader; +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub type OVF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>; +#[doc = "Field `TRG` reader - Retrigger Interrupt Enable"] +pub type TRG_R = crate::BitReader; +#[doc = "Field `TRG` writer - Retrigger Interrupt Enable"] +pub type TRG_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>; +#[doc = "Field `CNT` reader - Counter Interrupt Enable"] +pub type CNT_R = crate::BitReader; +#[doc = "Field `CNT` writer - Counter Interrupt Enable"] +pub type CNT_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>; +#[doc = "Field `ERR` reader - Error Interrupt Enable"] +pub type ERR_R = crate::BitReader; +#[doc = "Field `ERR` writer - Error Interrupt Enable"] +pub type ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>; +#[doc = "Field `UFS` reader - Non-Recoverable Update Fault Interrupt Enable"] +pub type UFS_R = crate::BitReader; +#[doc = "Field `UFS` writer - Non-Recoverable Update Fault Interrupt Enable"] +pub type UFS_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>; +#[doc = "Field `DFS` reader - Non-Recoverable Debug Fault Interrupt Enable"] +pub type DFS_R = crate::BitReader; +#[doc = "Field `DFS` writer - Non-Recoverable Debug Fault Interrupt Enable"] +pub type DFS_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>; +#[doc = "Field `FAULTA` reader - Recoverable Fault A Interrupt Enable"] +pub type FAULTA_R = crate::BitReader; +#[doc = "Field `FAULTA` writer - Recoverable Fault A Interrupt Enable"] +pub type FAULTA_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>; +#[doc = "Field `FAULTB` reader - Recoverable Fault B Interrupt Enable"] +pub type FAULTB_R = crate::BitReader; +#[doc = "Field `FAULTB` writer - Recoverable Fault B Interrupt Enable"] +pub type FAULTB_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>; +#[doc = "Field `FAULT0` reader - Non-Recoverable Fault 0 Interrupt Enable"] +pub type FAULT0_R = crate::BitReader; +#[doc = "Field `FAULT0` writer - Non-Recoverable Fault 0 Interrupt Enable"] +pub type FAULT0_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>; +#[doc = "Field `FAULT1` reader - Non-Recoverable Fault 1 Interrupt Enable"] +pub type FAULT1_R = crate::BitReader; +#[doc = "Field `FAULT1` writer - Non-Recoverable Fault 1 Interrupt Enable"] +pub type FAULT1_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>; +#[doc = "Field `MC0` reader - Match or Capture Channel 0 Interrupt Enable"] +pub type MC0_R = crate::BitReader; +#[doc = "Field `MC0` writer - Match or Capture Channel 0 Interrupt Enable"] +pub type MC0_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>; +#[doc = "Field `MC1` reader - Match or Capture Channel 1 Interrupt Enable"] +pub type MC1_R = crate::BitReader; +#[doc = "Field `MC1` writer - Match or Capture Channel 1 Interrupt Enable"] +pub type MC1_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>; +#[doc = "Field `MC2` reader - Match or Capture Channel 2 Interrupt Enable"] +pub type MC2_R = crate::BitReader; +#[doc = "Field `MC2` writer - Match or Capture Channel 2 Interrupt Enable"] +pub type MC2_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>; +#[doc = "Field `MC3` reader - Match or Capture Channel 3 Interrupt Enable"] +pub type MC3_R = crate::BitReader; +#[doc = "Field `MC3` writer - Match or Capture Channel 3 Interrupt Enable"] +pub type MC3_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENCLR_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Retrigger Interrupt Enable"] + #[inline(always)] + pub fn trg(&self) -> TRG_R { + TRG_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Counter Interrupt Enable"] + #[inline(always)] + pub fn cnt(&self) -> CNT_R { + CNT_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 10 - Non-Recoverable Update Fault Interrupt Enable"] + #[inline(always)] + pub fn ufs(&self) -> UFS_R { + UFS_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault Interrupt Enable"] + #[inline(always)] + pub fn dfs(&self) -> DFS_R { + DFS_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Recoverable Fault A Interrupt Enable"] + #[inline(always)] + pub fn faulta(&self) -> FAULTA_R { + FAULTA_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Recoverable Fault B Interrupt Enable"] + #[inline(always)] + pub fn faultb(&self) -> FAULTB_R { + FAULTB_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 Interrupt Enable"] + #[inline(always)] + pub fn fault0(&self) -> FAULT0_R { + FAULT0_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 Interrupt Enable"] + #[inline(always)] + pub fn fault1(&self) -> FAULT1_R { + FAULT1_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Match or Capture Channel 2 Interrupt Enable"] + #[inline(always)] + pub fn mc2(&self) -> MC2_R { + MC2_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Match or Capture Channel 3 Interrupt Enable"] + #[inline(always)] + pub fn mc3(&self) -> MC3_R { + MC3_R::new(((self.bits >> 19) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn ovf(&mut self) -> OVF_W<0> { + OVF_W::new(self) + } + #[doc = "Bit 1 - Retrigger Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn trg(&mut self) -> TRG_W<1> { + TRG_W::new(self) + } + #[doc = "Bit 2 - Counter Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn cnt(&mut self) -> CNT_W<2> { + CNT_W::new(self) + } + #[doc = "Bit 3 - Error Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn err(&mut self) -> ERR_W<3> { + ERR_W::new(self) + } + #[doc = "Bit 10 - Non-Recoverable Update Fault Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn ufs(&mut self) -> UFS_W<10> { + UFS_W::new(self) + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn dfs(&mut self) -> DFS_W<11> { + DFS_W::new(self) + } + #[doc = "Bit 12 - Recoverable Fault A Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn faulta(&mut self) -> FAULTA_W<12> { + FAULTA_W::new(self) + } + #[doc = "Bit 13 - Recoverable Fault B Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn faultb(&mut self) -> FAULTB_W<13> { + FAULTB_W::new(self) + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn fault0(&mut self) -> FAULT0_W<14> { + FAULT0_W::new(self) + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn fault1(&mut self) -> FAULT1_W<15> { + FAULT1_W::new(self) + } + #[doc = "Bit 16 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn mc0(&mut self) -> MC0_W<16> { + MC0_W::new(self) + } + #[doc = "Bit 17 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn mc1(&mut self) -> MC1_W<17> { + MC1_W::new(self) + } + #[doc = "Bit 18 - Match or Capture Channel 2 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn mc2(&mut self) -> MC2_W<18> { + MC2_W::new(self) + } + #[doc = "Bit 19 - Match or Capture Channel 3 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn mc3(&mut self) -> MC3_W<19> { + MC3_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tcc0/intenset.rs b/pac/atsaml22j/src/tcc0/intenset.rs new file mode 100644 index 000000000000..793afc4018bb --- /dev/null +++ b/pac/atsaml22j/src/tcc0/intenset.rs @@ -0,0 +1,275 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow Interrupt Enable"] +pub type OVF_R = crate::BitReader; +#[doc = "Field `OVF` writer - Overflow Interrupt Enable"] +pub type OVF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>; +#[doc = "Field `TRG` reader - Retrigger Interrupt Enable"] +pub type TRG_R = crate::BitReader; +#[doc = "Field `TRG` writer - Retrigger Interrupt Enable"] +pub type TRG_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>; +#[doc = "Field `CNT` reader - Counter Interrupt Enable"] +pub type CNT_R = crate::BitReader; +#[doc = "Field `CNT` writer - Counter Interrupt Enable"] +pub type CNT_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>; +#[doc = "Field `ERR` reader - Error Interrupt Enable"] +pub type ERR_R = crate::BitReader; +#[doc = "Field `ERR` writer - Error Interrupt Enable"] +pub type ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>; +#[doc = "Field `UFS` reader - Non-Recoverable Update Fault Interrupt Enable"] +pub type UFS_R = crate::BitReader; +#[doc = "Field `UFS` writer - Non-Recoverable Update Fault Interrupt Enable"] +pub type UFS_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>; +#[doc = "Field `DFS` reader - Non-Recoverable Debug Fault Interrupt Enable"] +pub type DFS_R = crate::BitReader; +#[doc = "Field `DFS` writer - Non-Recoverable Debug Fault Interrupt Enable"] +pub type DFS_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>; +#[doc = "Field `FAULTA` reader - Recoverable Fault A Interrupt Enable"] +pub type FAULTA_R = crate::BitReader; +#[doc = "Field `FAULTA` writer - Recoverable Fault A Interrupt Enable"] +pub type FAULTA_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>; +#[doc = "Field `FAULTB` reader - Recoverable Fault B Interrupt Enable"] +pub type FAULTB_R = crate::BitReader; +#[doc = "Field `FAULTB` writer - Recoverable Fault B Interrupt Enable"] +pub type FAULTB_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>; +#[doc = "Field `FAULT0` reader - Non-Recoverable Fault 0 Interrupt Enable"] +pub type FAULT0_R = crate::BitReader; +#[doc = "Field `FAULT0` writer - Non-Recoverable Fault 0 Interrupt Enable"] +pub type FAULT0_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>; +#[doc = "Field `FAULT1` reader - Non-Recoverable Fault 1 Interrupt Enable"] +pub type FAULT1_R = crate::BitReader; +#[doc = "Field `FAULT1` writer - Non-Recoverable Fault 1 Interrupt Enable"] +pub type FAULT1_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>; +#[doc = "Field `MC0` reader - Match or Capture Channel 0 Interrupt Enable"] +pub type MC0_R = crate::BitReader; +#[doc = "Field `MC0` writer - Match or Capture Channel 0 Interrupt Enable"] +pub type MC0_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>; +#[doc = "Field `MC1` reader - Match or Capture Channel 1 Interrupt Enable"] +pub type MC1_R = crate::BitReader; +#[doc = "Field `MC1` writer - Match or Capture Channel 1 Interrupt Enable"] +pub type MC1_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>; +#[doc = "Field `MC2` reader - Match or Capture Channel 2 Interrupt Enable"] +pub type MC2_R = crate::BitReader; +#[doc = "Field `MC2` writer - Match or Capture Channel 2 Interrupt Enable"] +pub type MC2_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>; +#[doc = "Field `MC3` reader - Match or Capture Channel 3 Interrupt Enable"] +pub type MC3_R = crate::BitReader; +#[doc = "Field `MC3` writer - Match or Capture Channel 3 Interrupt Enable"] +pub type MC3_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTENSET_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Retrigger Interrupt Enable"] + #[inline(always)] + pub fn trg(&self) -> TRG_R { + TRG_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Counter Interrupt Enable"] + #[inline(always)] + pub fn cnt(&self) -> CNT_R { + CNT_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Error Interrupt Enable"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 10 - Non-Recoverable Update Fault Interrupt Enable"] + #[inline(always)] + pub fn ufs(&self) -> UFS_R { + UFS_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault Interrupt Enable"] + #[inline(always)] + pub fn dfs(&self) -> DFS_R { + DFS_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Recoverable Fault A Interrupt Enable"] + #[inline(always)] + pub fn faulta(&self) -> FAULTA_R { + FAULTA_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Recoverable Fault B Interrupt Enable"] + #[inline(always)] + pub fn faultb(&self) -> FAULTB_R { + FAULTB_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 Interrupt Enable"] + #[inline(always)] + pub fn fault0(&self) -> FAULT0_R { + FAULT0_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 Interrupt Enable"] + #[inline(always)] + pub fn fault1(&self) -> FAULT1_R { + FAULT1_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Match or Capture Channel 2 Interrupt Enable"] + #[inline(always)] + pub fn mc2(&self) -> MC2_R { + MC2_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Match or Capture Channel 3 Interrupt Enable"] + #[inline(always)] + pub fn mc3(&self) -> MC3_R { + MC3_R::new(((self.bits >> 19) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn ovf(&mut self) -> OVF_W<0> { + OVF_W::new(self) + } + #[doc = "Bit 1 - Retrigger Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn trg(&mut self) -> TRG_W<1> { + TRG_W::new(self) + } + #[doc = "Bit 2 - Counter Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn cnt(&mut self) -> CNT_W<2> { + CNT_W::new(self) + } + #[doc = "Bit 3 - Error Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn err(&mut self) -> ERR_W<3> { + ERR_W::new(self) + } + #[doc = "Bit 10 - Non-Recoverable Update Fault Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn ufs(&mut self) -> UFS_W<10> { + UFS_W::new(self) + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn dfs(&mut self) -> DFS_W<11> { + DFS_W::new(self) + } + #[doc = "Bit 12 - Recoverable Fault A Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn faulta(&mut self) -> FAULTA_W<12> { + FAULTA_W::new(self) + } + #[doc = "Bit 13 - Recoverable Fault B Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn faultb(&mut self) -> FAULTB_W<13> { + FAULTB_W::new(self) + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn fault0(&mut self) -> FAULT0_W<14> { + FAULT0_W::new(self) + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn fault1(&mut self) -> FAULT1_W<15> { + FAULT1_W::new(self) + } + #[doc = "Bit 16 - Match or Capture Channel 0 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn mc0(&mut self) -> MC0_W<16> { + MC0_W::new(self) + } + #[doc = "Bit 17 - Match or Capture Channel 1 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn mc1(&mut self) -> MC1_W<17> { + MC1_W::new(self) + } + #[doc = "Bit 18 - Match or Capture Channel 2 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn mc2(&mut self) -> MC2_W<18> { + MC2_W::new(self) + } + #[doc = "Bit 19 - Match or Capture Channel 3 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn mc3(&mut self) -> MC3_W<19> { + MC3_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tcc0/intflag.rs b/pac/atsaml22j/src/tcc0/intflag.rs new file mode 100644 index 000000000000..a5fda2381116 --- /dev/null +++ b/pac/atsaml22j/src/tcc0/intflag.rs @@ -0,0 +1,275 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OVF` reader - Overflow"] +pub type OVF_R = crate::BitReader; +#[doc = "Field `OVF` writer - Overflow"] +pub type OVF_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAG_SPEC, bool, O>; +#[doc = "Field `TRG` reader - Retrigger"] +pub type TRG_R = crate::BitReader; +#[doc = "Field `TRG` writer - Retrigger"] +pub type TRG_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAG_SPEC, bool, O>; +#[doc = "Field `CNT` reader - Counter"] +pub type CNT_R = crate::BitReader; +#[doc = "Field `CNT` writer - Counter"] +pub type CNT_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAG_SPEC, bool, O>; +#[doc = "Field `ERR` reader - Error"] +pub type ERR_R = crate::BitReader; +#[doc = "Field `ERR` writer - Error"] +pub type ERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAG_SPEC, bool, O>; +#[doc = "Field `UFS` reader - Non-Recoverable Update Fault"] +pub type UFS_R = crate::BitReader; +#[doc = "Field `UFS` writer - Non-Recoverable Update Fault"] +pub type UFS_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAG_SPEC, bool, O>; +#[doc = "Field `DFS` reader - Non-Recoverable Debug Fault"] +pub type DFS_R = crate::BitReader; +#[doc = "Field `DFS` writer - Non-Recoverable Debug Fault"] +pub type DFS_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAG_SPEC, bool, O>; +#[doc = "Field `FAULTA` reader - Recoverable Fault A"] +pub type FAULTA_R = crate::BitReader; +#[doc = "Field `FAULTA` writer - Recoverable Fault A"] +pub type FAULTA_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAG_SPEC, bool, O>; +#[doc = "Field `FAULTB` reader - Recoverable Fault B"] +pub type FAULTB_R = crate::BitReader; +#[doc = "Field `FAULTB` writer - Recoverable Fault B"] +pub type FAULTB_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAG_SPEC, bool, O>; +#[doc = "Field `FAULT0` reader - Non-Recoverable Fault 0"] +pub type FAULT0_R = crate::BitReader; +#[doc = "Field `FAULT0` writer - Non-Recoverable Fault 0"] +pub type FAULT0_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAG_SPEC, bool, O>; +#[doc = "Field `FAULT1` reader - Non-Recoverable Fault 1"] +pub type FAULT1_R = crate::BitReader; +#[doc = "Field `FAULT1` writer - Non-Recoverable Fault 1"] +pub type FAULT1_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAG_SPEC, bool, O>; +#[doc = "Field `MC0` reader - Match or Capture 0"] +pub type MC0_R = crate::BitReader; +#[doc = "Field `MC0` writer - Match or Capture 0"] +pub type MC0_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAG_SPEC, bool, O>; +#[doc = "Field `MC1` reader - Match or Capture 1"] +pub type MC1_R = crate::BitReader; +#[doc = "Field `MC1` writer - Match or Capture 1"] +pub type MC1_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAG_SPEC, bool, O>; +#[doc = "Field `MC2` reader - Match or Capture 2"] +pub type MC2_R = crate::BitReader; +#[doc = "Field `MC2` writer - Match or Capture 2"] +pub type MC2_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAG_SPEC, bool, O>; +#[doc = "Field `MC3` reader - Match or Capture 3"] +pub type MC3_R = crate::BitReader; +#[doc = "Field `MC3` writer - Match or Capture 3"] +pub type MC3_W<'a, const O: u8> = crate::BitWriter<'a, u32, INTFLAG_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Overflow"] + #[inline(always)] + pub fn ovf(&self) -> OVF_R { + OVF_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Retrigger"] + #[inline(always)] + pub fn trg(&self) -> TRG_R { + TRG_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Counter"] + #[inline(always)] + pub fn cnt(&self) -> CNT_R { + CNT_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Error"] + #[inline(always)] + pub fn err(&self) -> ERR_R { + ERR_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 10 - Non-Recoverable Update Fault"] + #[inline(always)] + pub fn ufs(&self) -> UFS_R { + UFS_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault"] + #[inline(always)] + pub fn dfs(&self) -> DFS_R { + DFS_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Recoverable Fault A"] + #[inline(always)] + pub fn faulta(&self) -> FAULTA_R { + FAULTA_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Recoverable Fault B"] + #[inline(always)] + pub fn faultb(&self) -> FAULTB_R { + FAULTB_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Non-Recoverable Fault 0"] + #[inline(always)] + pub fn fault0(&self) -> FAULT0_R { + FAULT0_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Non-Recoverable Fault 1"] + #[inline(always)] + pub fn fault1(&self) -> FAULT1_R { + FAULT1_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Match or Capture 0"] + #[inline(always)] + pub fn mc0(&self) -> MC0_R { + MC0_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Match or Capture 1"] + #[inline(always)] + pub fn mc1(&self) -> MC1_R { + MC1_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Match or Capture 2"] + #[inline(always)] + pub fn mc2(&self) -> MC2_R { + MC2_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Match or Capture 3"] + #[inline(always)] + pub fn mc3(&self) -> MC3_R { + MC3_R::new(((self.bits >> 19) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Overflow"] + #[inline(always)] + #[must_use] + pub fn ovf(&mut self) -> OVF_W<0> { + OVF_W::new(self) + } + #[doc = "Bit 1 - Retrigger"] + #[inline(always)] + #[must_use] + pub fn trg(&mut self) -> TRG_W<1> { + TRG_W::new(self) + } + #[doc = "Bit 2 - Counter"] + #[inline(always)] + #[must_use] + pub fn cnt(&mut self) -> CNT_W<2> { + CNT_W::new(self) + } + #[doc = "Bit 3 - Error"] + #[inline(always)] + #[must_use] + pub fn err(&mut self) -> ERR_W<3> { + ERR_W::new(self) + } + #[doc = "Bit 10 - Non-Recoverable Update Fault"] + #[inline(always)] + #[must_use] + pub fn ufs(&mut self) -> UFS_W<10> { + UFS_W::new(self) + } + #[doc = "Bit 11 - Non-Recoverable Debug Fault"] + #[inline(always)] + #[must_use] + pub fn dfs(&mut self) -> DFS_W<11> { + DFS_W::new(self) + } + #[doc = "Bit 12 - Recoverable Fault A"] + #[inline(always)] + #[must_use] + pub fn faulta(&mut self) -> FAULTA_W<12> { + FAULTA_W::new(self) + } + #[doc = "Bit 13 - Recoverable Fault B"] + #[inline(always)] + #[must_use] + pub fn faultb(&mut self) -> FAULTB_W<13> { + FAULTB_W::new(self) + } + #[doc = "Bit 14 - Non-Recoverable Fault 0"] + #[inline(always)] + #[must_use] + pub fn fault0(&mut self) -> FAULT0_W<14> { + FAULT0_W::new(self) + } + #[doc = "Bit 15 - Non-Recoverable Fault 1"] + #[inline(always)] + #[must_use] + pub fn fault1(&mut self) -> FAULT1_W<15> { + FAULT1_W::new(self) + } + #[doc = "Bit 16 - Match or Capture 0"] + #[inline(always)] + #[must_use] + pub fn mc0(&mut self) -> MC0_W<16> { + MC0_W::new(self) + } + #[doc = "Bit 17 - Match or Capture 1"] + #[inline(always)] + #[must_use] + pub fn mc1(&mut self) -> MC1_W<17> { + MC1_W::new(self) + } + #[doc = "Bit 18 - Match or Capture 2"] + #[inline(always)] + #[must_use] + pub fn mc2(&mut self) -> MC2_W<18> { + MC2_W::new(self) + } + #[doc = "Bit 19 - Match or Capture 3"] + #[inline(always)] + #[must_use] + pub fn mc3(&mut self) -> MC3_W<19> { + MC3_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tcc0/patt.rs b/pac/atsaml22j/src/tcc0/patt.rs new file mode 100644 index 000000000000..a4f328d87367 --- /dev/null +++ b/pac/atsaml22j/src/tcc0/patt.rs @@ -0,0 +1,305 @@ +#[doc = "Register `PATT` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PATT` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PGE0` reader - Pattern Generator 0 Output Enable"] +pub type PGE0_R = crate::BitReader; +#[doc = "Field `PGE0` writer - Pattern Generator 0 Output Enable"] +pub type PGE0_W<'a, const O: u8> = crate::BitWriter<'a, u16, PATT_SPEC, bool, O>; +#[doc = "Field `PGE1` reader - Pattern Generator 1 Output Enable"] +pub type PGE1_R = crate::BitReader; +#[doc = "Field `PGE1` writer - Pattern Generator 1 Output Enable"] +pub type PGE1_W<'a, const O: u8> = crate::BitWriter<'a, u16, PATT_SPEC, bool, O>; +#[doc = "Field `PGE2` reader - Pattern Generator 2 Output Enable"] +pub type PGE2_R = crate::BitReader; +#[doc = "Field `PGE2` writer - Pattern Generator 2 Output Enable"] +pub type PGE2_W<'a, const O: u8> = crate::BitWriter<'a, u16, PATT_SPEC, bool, O>; +#[doc = "Field `PGE3` reader - Pattern Generator 3 Output Enable"] +pub type PGE3_R = crate::BitReader; +#[doc = "Field `PGE3` writer - Pattern Generator 3 Output Enable"] +pub type PGE3_W<'a, const O: u8> = crate::BitWriter<'a, u16, PATT_SPEC, bool, O>; +#[doc = "Field `PGE4` reader - Pattern Generator 4 Output Enable"] +pub type PGE4_R = crate::BitReader; +#[doc = "Field `PGE4` writer - Pattern Generator 4 Output Enable"] +pub type PGE4_W<'a, const O: u8> = crate::BitWriter<'a, u16, PATT_SPEC, bool, O>; +#[doc = "Field `PGE5` reader - Pattern Generator 5 Output Enable"] +pub type PGE5_R = crate::BitReader; +#[doc = "Field `PGE5` writer - Pattern Generator 5 Output Enable"] +pub type PGE5_W<'a, const O: u8> = crate::BitWriter<'a, u16, PATT_SPEC, bool, O>; +#[doc = "Field `PGE6` reader - Pattern Generator 6 Output Enable"] +pub type PGE6_R = crate::BitReader; +#[doc = "Field `PGE6` writer - Pattern Generator 6 Output Enable"] +pub type PGE6_W<'a, const O: u8> = crate::BitWriter<'a, u16, PATT_SPEC, bool, O>; +#[doc = "Field `PGE7` reader - Pattern Generator 7 Output Enable"] +pub type PGE7_R = crate::BitReader; +#[doc = "Field `PGE7` writer - Pattern Generator 7 Output Enable"] +pub type PGE7_W<'a, const O: u8> = crate::BitWriter<'a, u16, PATT_SPEC, bool, O>; +#[doc = "Field `PGV0` reader - Pattern Generator 0 Output Value"] +pub type PGV0_R = crate::BitReader; +#[doc = "Field `PGV0` writer - Pattern Generator 0 Output Value"] +pub type PGV0_W<'a, const O: u8> = crate::BitWriter<'a, u16, PATT_SPEC, bool, O>; +#[doc = "Field `PGV1` reader - Pattern Generator 1 Output Value"] +pub type PGV1_R = crate::BitReader; +#[doc = "Field `PGV1` writer - Pattern Generator 1 Output Value"] +pub type PGV1_W<'a, const O: u8> = crate::BitWriter<'a, u16, PATT_SPEC, bool, O>; +#[doc = "Field `PGV2` reader - Pattern Generator 2 Output Value"] +pub type PGV2_R = crate::BitReader; +#[doc = "Field `PGV2` writer - Pattern Generator 2 Output Value"] +pub type PGV2_W<'a, const O: u8> = crate::BitWriter<'a, u16, PATT_SPEC, bool, O>; +#[doc = "Field `PGV3` reader - Pattern Generator 3 Output Value"] +pub type PGV3_R = crate::BitReader; +#[doc = "Field `PGV3` writer - Pattern Generator 3 Output Value"] +pub type PGV3_W<'a, const O: u8> = crate::BitWriter<'a, u16, PATT_SPEC, bool, O>; +#[doc = "Field `PGV4` reader - Pattern Generator 4 Output Value"] +pub type PGV4_R = crate::BitReader; +#[doc = "Field `PGV4` writer - Pattern Generator 4 Output Value"] +pub type PGV4_W<'a, const O: u8> = crate::BitWriter<'a, u16, PATT_SPEC, bool, O>; +#[doc = "Field `PGV5` reader - Pattern Generator 5 Output Value"] +pub type PGV5_R = crate::BitReader; +#[doc = "Field `PGV5` writer - Pattern Generator 5 Output Value"] +pub type PGV5_W<'a, const O: u8> = crate::BitWriter<'a, u16, PATT_SPEC, bool, O>; +#[doc = "Field `PGV6` reader - Pattern Generator 6 Output Value"] +pub type PGV6_R = crate::BitReader; +#[doc = "Field `PGV6` writer - Pattern Generator 6 Output Value"] +pub type PGV6_W<'a, const O: u8> = crate::BitWriter<'a, u16, PATT_SPEC, bool, O>; +#[doc = "Field `PGV7` reader - Pattern Generator 7 Output Value"] +pub type PGV7_R = crate::BitReader; +#[doc = "Field `PGV7` writer - Pattern Generator 7 Output Value"] +pub type PGV7_W<'a, const O: u8> = crate::BitWriter<'a, u16, PATT_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Pattern Generator 0 Output Enable"] + #[inline(always)] + pub fn pge0(&self) -> PGE0_R { + PGE0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pattern Generator 1 Output Enable"] + #[inline(always)] + pub fn pge1(&self) -> PGE1_R { + PGE1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Pattern Generator 2 Output Enable"] + #[inline(always)] + pub fn pge2(&self) -> PGE2_R { + PGE2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Pattern Generator 3 Output Enable"] + #[inline(always)] + pub fn pge3(&self) -> PGE3_R { + PGE3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Pattern Generator 4 Output Enable"] + #[inline(always)] + pub fn pge4(&self) -> PGE4_R { + PGE4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Pattern Generator 5 Output Enable"] + #[inline(always)] + pub fn pge5(&self) -> PGE5_R { + PGE5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Pattern Generator 6 Output Enable"] + #[inline(always)] + pub fn pge6(&self) -> PGE6_R { + PGE6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Pattern Generator 7 Output Enable"] + #[inline(always)] + pub fn pge7(&self) -> PGE7_R { + PGE7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Pattern Generator 0 Output Value"] + #[inline(always)] + pub fn pgv0(&self) -> PGV0_R { + PGV0_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Pattern Generator 1 Output Value"] + #[inline(always)] + pub fn pgv1(&self) -> PGV1_R { + PGV1_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Pattern Generator 2 Output Value"] + #[inline(always)] + pub fn pgv2(&self) -> PGV2_R { + PGV2_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Pattern Generator 3 Output Value"] + #[inline(always)] + pub fn pgv3(&self) -> PGV3_R { + PGV3_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Pattern Generator 4 Output Value"] + #[inline(always)] + pub fn pgv4(&self) -> PGV4_R { + PGV4_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Pattern Generator 5 Output Value"] + #[inline(always)] + pub fn pgv5(&self) -> PGV5_R { + PGV5_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Pattern Generator 6 Output Value"] + #[inline(always)] + pub fn pgv6(&self) -> PGV6_R { + PGV6_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Pattern Generator 7 Output Value"] + #[inline(always)] + pub fn pgv7(&self) -> PGV7_R { + PGV7_R::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pattern Generator 0 Output Enable"] + #[inline(always)] + #[must_use] + pub fn pge0(&mut self) -> PGE0_W<0> { + PGE0_W::new(self) + } + #[doc = "Bit 1 - Pattern Generator 1 Output Enable"] + #[inline(always)] + #[must_use] + pub fn pge1(&mut self) -> PGE1_W<1> { + PGE1_W::new(self) + } + #[doc = "Bit 2 - Pattern Generator 2 Output Enable"] + #[inline(always)] + #[must_use] + pub fn pge2(&mut self) -> PGE2_W<2> { + PGE2_W::new(self) + } + #[doc = "Bit 3 - Pattern Generator 3 Output Enable"] + #[inline(always)] + #[must_use] + pub fn pge3(&mut self) -> PGE3_W<3> { + PGE3_W::new(self) + } + #[doc = "Bit 4 - Pattern Generator 4 Output Enable"] + #[inline(always)] + #[must_use] + pub fn pge4(&mut self) -> PGE4_W<4> { + PGE4_W::new(self) + } + #[doc = "Bit 5 - Pattern Generator 5 Output Enable"] + #[inline(always)] + #[must_use] + pub fn pge5(&mut self) -> PGE5_W<5> { + PGE5_W::new(self) + } + #[doc = "Bit 6 - Pattern Generator 6 Output Enable"] + #[inline(always)] + #[must_use] + pub fn pge6(&mut self) -> PGE6_W<6> { + PGE6_W::new(self) + } + #[doc = "Bit 7 - Pattern Generator 7 Output Enable"] + #[inline(always)] + #[must_use] + pub fn pge7(&mut self) -> PGE7_W<7> { + PGE7_W::new(self) + } + #[doc = "Bit 8 - Pattern Generator 0 Output Value"] + #[inline(always)] + #[must_use] + pub fn pgv0(&mut self) -> PGV0_W<8> { + PGV0_W::new(self) + } + #[doc = "Bit 9 - Pattern Generator 1 Output Value"] + #[inline(always)] + #[must_use] + pub fn pgv1(&mut self) -> PGV1_W<9> { + PGV1_W::new(self) + } + #[doc = "Bit 10 - Pattern Generator 2 Output Value"] + #[inline(always)] + #[must_use] + pub fn pgv2(&mut self) -> PGV2_W<10> { + PGV2_W::new(self) + } + #[doc = "Bit 11 - Pattern Generator 3 Output Value"] + #[inline(always)] + #[must_use] + pub fn pgv3(&mut self) -> PGV3_W<11> { + PGV3_W::new(self) + } + #[doc = "Bit 12 - Pattern Generator 4 Output Value"] + #[inline(always)] + #[must_use] + pub fn pgv4(&mut self) -> PGV4_W<12> { + PGV4_W::new(self) + } + #[doc = "Bit 13 - Pattern Generator 5 Output Value"] + #[inline(always)] + #[must_use] + pub fn pgv5(&mut self) -> PGV5_W<13> { + PGV5_W::new(self) + } + #[doc = "Bit 14 - Pattern Generator 6 Output Value"] + #[inline(always)] + #[must_use] + pub fn pgv6(&mut self) -> PGV6_W<14> { + PGV6_W::new(self) + } + #[doc = "Bit 15 - Pattern Generator 7 Output Value"] + #[inline(always)] + #[must_use] + pub fn pgv7(&mut self) -> PGV7_W<15> { + PGV7_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pattern\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [patt](index.html) module"] +pub struct PATT_SPEC; +impl crate::RegisterSpec for PATT_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [patt::R](R) reader structure"] +impl crate::Readable for PATT_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [patt::W](W) writer structure"] +impl crate::Writable for PATT_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PATT to value 0"] +impl crate::Resettable for PATT_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tcc0/pattbuf.rs b/pac/atsaml22j/src/tcc0/pattbuf.rs new file mode 100644 index 000000000000..b1a27f9a37ff --- /dev/null +++ b/pac/atsaml22j/src/tcc0/pattbuf.rs @@ -0,0 +1,305 @@ +#[doc = "Register `PATTBUF` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PATTBUF` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PGEB0` reader - Pattern Generator 0 Output Enable Buffer"] +pub type PGEB0_R = crate::BitReader; +#[doc = "Field `PGEB0` writer - Pattern Generator 0 Output Enable Buffer"] +pub type PGEB0_W<'a, const O: u8> = crate::BitWriter<'a, u16, PATTBUF_SPEC, bool, O>; +#[doc = "Field `PGEB1` reader - Pattern Generator 1 Output Enable Buffer"] +pub type PGEB1_R = crate::BitReader; +#[doc = "Field `PGEB1` writer - Pattern Generator 1 Output Enable Buffer"] +pub type PGEB1_W<'a, const O: u8> = crate::BitWriter<'a, u16, PATTBUF_SPEC, bool, O>; +#[doc = "Field `PGEB2` reader - Pattern Generator 2 Output Enable Buffer"] +pub type PGEB2_R = crate::BitReader; +#[doc = "Field `PGEB2` writer - Pattern Generator 2 Output Enable Buffer"] +pub type PGEB2_W<'a, const O: u8> = crate::BitWriter<'a, u16, PATTBUF_SPEC, bool, O>; +#[doc = "Field `PGEB3` reader - Pattern Generator 3 Output Enable Buffer"] +pub type PGEB3_R = crate::BitReader; +#[doc = "Field `PGEB3` writer - Pattern Generator 3 Output Enable Buffer"] +pub type PGEB3_W<'a, const O: u8> = crate::BitWriter<'a, u16, PATTBUF_SPEC, bool, O>; +#[doc = "Field `PGEB4` reader - Pattern Generator 4 Output Enable Buffer"] +pub type PGEB4_R = crate::BitReader; +#[doc = "Field `PGEB4` writer - Pattern Generator 4 Output Enable Buffer"] +pub type PGEB4_W<'a, const O: u8> = crate::BitWriter<'a, u16, PATTBUF_SPEC, bool, O>; +#[doc = "Field `PGEB5` reader - Pattern Generator 5 Output Enable Buffer"] +pub type PGEB5_R = crate::BitReader; +#[doc = "Field `PGEB5` writer - Pattern Generator 5 Output Enable Buffer"] +pub type PGEB5_W<'a, const O: u8> = crate::BitWriter<'a, u16, PATTBUF_SPEC, bool, O>; +#[doc = "Field `PGEB6` reader - Pattern Generator 6 Output Enable Buffer"] +pub type PGEB6_R = crate::BitReader; +#[doc = "Field `PGEB6` writer - Pattern Generator 6 Output Enable Buffer"] +pub type PGEB6_W<'a, const O: u8> = crate::BitWriter<'a, u16, PATTBUF_SPEC, bool, O>; +#[doc = "Field `PGEB7` reader - Pattern Generator 7 Output Enable Buffer"] +pub type PGEB7_R = crate::BitReader; +#[doc = "Field `PGEB7` writer - Pattern Generator 7 Output Enable Buffer"] +pub type PGEB7_W<'a, const O: u8> = crate::BitWriter<'a, u16, PATTBUF_SPEC, bool, O>; +#[doc = "Field `PGVB0` reader - Pattern Generator 0 Output Enable"] +pub type PGVB0_R = crate::BitReader; +#[doc = "Field `PGVB0` writer - Pattern Generator 0 Output Enable"] +pub type PGVB0_W<'a, const O: u8> = crate::BitWriter<'a, u16, PATTBUF_SPEC, bool, O>; +#[doc = "Field `PGVB1` reader - Pattern Generator 1 Output Enable"] +pub type PGVB1_R = crate::BitReader; +#[doc = "Field `PGVB1` writer - Pattern Generator 1 Output Enable"] +pub type PGVB1_W<'a, const O: u8> = crate::BitWriter<'a, u16, PATTBUF_SPEC, bool, O>; +#[doc = "Field `PGVB2` reader - Pattern Generator 2 Output Enable"] +pub type PGVB2_R = crate::BitReader; +#[doc = "Field `PGVB2` writer - Pattern Generator 2 Output Enable"] +pub type PGVB2_W<'a, const O: u8> = crate::BitWriter<'a, u16, PATTBUF_SPEC, bool, O>; +#[doc = "Field `PGVB3` reader - Pattern Generator 3 Output Enable"] +pub type PGVB3_R = crate::BitReader; +#[doc = "Field `PGVB3` writer - Pattern Generator 3 Output Enable"] +pub type PGVB3_W<'a, const O: u8> = crate::BitWriter<'a, u16, PATTBUF_SPEC, bool, O>; +#[doc = "Field `PGVB4` reader - Pattern Generator 4 Output Enable"] +pub type PGVB4_R = crate::BitReader; +#[doc = "Field `PGVB4` writer - Pattern Generator 4 Output Enable"] +pub type PGVB4_W<'a, const O: u8> = crate::BitWriter<'a, u16, PATTBUF_SPEC, bool, O>; +#[doc = "Field `PGVB5` reader - Pattern Generator 5 Output Enable"] +pub type PGVB5_R = crate::BitReader; +#[doc = "Field `PGVB5` writer - Pattern Generator 5 Output Enable"] +pub type PGVB5_W<'a, const O: u8> = crate::BitWriter<'a, u16, PATTBUF_SPEC, bool, O>; +#[doc = "Field `PGVB6` reader - Pattern Generator 6 Output Enable"] +pub type PGVB6_R = crate::BitReader; +#[doc = "Field `PGVB6` writer - Pattern Generator 6 Output Enable"] +pub type PGVB6_W<'a, const O: u8> = crate::BitWriter<'a, u16, PATTBUF_SPEC, bool, O>; +#[doc = "Field `PGVB7` reader - Pattern Generator 7 Output Enable"] +pub type PGVB7_R = crate::BitReader; +#[doc = "Field `PGVB7` writer - Pattern Generator 7 Output Enable"] +pub type PGVB7_W<'a, const O: u8> = crate::BitWriter<'a, u16, PATTBUF_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Pattern Generator 0 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb0(&self) -> PGEB0_R { + PGEB0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Pattern Generator 1 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb1(&self) -> PGEB1_R { + PGEB1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Pattern Generator 2 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb2(&self) -> PGEB2_R { + PGEB2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Pattern Generator 3 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb3(&self) -> PGEB3_R { + PGEB3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Pattern Generator 4 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb4(&self) -> PGEB4_R { + PGEB4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Pattern Generator 5 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb5(&self) -> PGEB5_R { + PGEB5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Pattern Generator 6 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb6(&self) -> PGEB6_R { + PGEB6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Pattern Generator 7 Output Enable Buffer"] + #[inline(always)] + pub fn pgeb7(&self) -> PGEB7_R { + PGEB7_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Pattern Generator 0 Output Enable"] + #[inline(always)] + pub fn pgvb0(&self) -> PGVB0_R { + PGVB0_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Pattern Generator 1 Output Enable"] + #[inline(always)] + pub fn pgvb1(&self) -> PGVB1_R { + PGVB1_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Pattern Generator 2 Output Enable"] + #[inline(always)] + pub fn pgvb2(&self) -> PGVB2_R { + PGVB2_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Pattern Generator 3 Output Enable"] + #[inline(always)] + pub fn pgvb3(&self) -> PGVB3_R { + PGVB3_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Pattern Generator 4 Output Enable"] + #[inline(always)] + pub fn pgvb4(&self) -> PGVB4_R { + PGVB4_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Pattern Generator 5 Output Enable"] + #[inline(always)] + pub fn pgvb5(&self) -> PGVB5_R { + PGVB5_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Pattern Generator 6 Output Enable"] + #[inline(always)] + pub fn pgvb6(&self) -> PGVB6_R { + PGVB6_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Pattern Generator 7 Output Enable"] + #[inline(always)] + pub fn pgvb7(&self) -> PGVB7_R { + PGVB7_R::new(((self.bits >> 15) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Pattern Generator 0 Output Enable Buffer"] + #[inline(always)] + #[must_use] + pub fn pgeb0(&mut self) -> PGEB0_W<0> { + PGEB0_W::new(self) + } + #[doc = "Bit 1 - Pattern Generator 1 Output Enable Buffer"] + #[inline(always)] + #[must_use] + pub fn pgeb1(&mut self) -> PGEB1_W<1> { + PGEB1_W::new(self) + } + #[doc = "Bit 2 - Pattern Generator 2 Output Enable Buffer"] + #[inline(always)] + #[must_use] + pub fn pgeb2(&mut self) -> PGEB2_W<2> { + PGEB2_W::new(self) + } + #[doc = "Bit 3 - Pattern Generator 3 Output Enable Buffer"] + #[inline(always)] + #[must_use] + pub fn pgeb3(&mut self) -> PGEB3_W<3> { + PGEB3_W::new(self) + } + #[doc = "Bit 4 - Pattern Generator 4 Output Enable Buffer"] + #[inline(always)] + #[must_use] + pub fn pgeb4(&mut self) -> PGEB4_W<4> { + PGEB4_W::new(self) + } + #[doc = "Bit 5 - Pattern Generator 5 Output Enable Buffer"] + #[inline(always)] + #[must_use] + pub fn pgeb5(&mut self) -> PGEB5_W<5> { + PGEB5_W::new(self) + } + #[doc = "Bit 6 - Pattern Generator 6 Output Enable Buffer"] + #[inline(always)] + #[must_use] + pub fn pgeb6(&mut self) -> PGEB6_W<6> { + PGEB6_W::new(self) + } + #[doc = "Bit 7 - Pattern Generator 7 Output Enable Buffer"] + #[inline(always)] + #[must_use] + pub fn pgeb7(&mut self) -> PGEB7_W<7> { + PGEB7_W::new(self) + } + #[doc = "Bit 8 - Pattern Generator 0 Output Enable"] + #[inline(always)] + #[must_use] + pub fn pgvb0(&mut self) -> PGVB0_W<8> { + PGVB0_W::new(self) + } + #[doc = "Bit 9 - Pattern Generator 1 Output Enable"] + #[inline(always)] + #[must_use] + pub fn pgvb1(&mut self) -> PGVB1_W<9> { + PGVB1_W::new(self) + } + #[doc = "Bit 10 - Pattern Generator 2 Output Enable"] + #[inline(always)] + #[must_use] + pub fn pgvb2(&mut self) -> PGVB2_W<10> { + PGVB2_W::new(self) + } + #[doc = "Bit 11 - Pattern Generator 3 Output Enable"] + #[inline(always)] + #[must_use] + pub fn pgvb3(&mut self) -> PGVB3_W<11> { + PGVB3_W::new(self) + } + #[doc = "Bit 12 - Pattern Generator 4 Output Enable"] + #[inline(always)] + #[must_use] + pub fn pgvb4(&mut self) -> PGVB4_W<12> { + PGVB4_W::new(self) + } + #[doc = "Bit 13 - Pattern Generator 5 Output Enable"] + #[inline(always)] + #[must_use] + pub fn pgvb5(&mut self) -> PGVB5_W<13> { + PGVB5_W::new(self) + } + #[doc = "Bit 14 - Pattern Generator 6 Output Enable"] + #[inline(always)] + #[must_use] + pub fn pgvb6(&mut self) -> PGVB6_W<14> { + PGVB6_W::new(self) + } + #[doc = "Bit 15 - Pattern Generator 7 Output Enable"] + #[inline(always)] + #[must_use] + pub fn pgvb7(&mut self) -> PGVB7_W<15> { + PGVB7_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Pattern Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pattbuf](index.html) module"] +pub struct PATTBUF_SPEC; +impl crate::RegisterSpec for PATTBUF_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [pattbuf::R](R) reader structure"] +impl crate::Readable for PATTBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [pattbuf::W](W) writer structure"] +impl crate::Writable for PATTBUF_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PATTBUF to value 0"] +impl crate::Resettable for PATTBUF_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tcc0/per.rs b/pac/atsaml22j/src/tcc0/per.rs new file mode 100644 index 000000000000..c92a99b2ec71 --- /dev/null +++ b/pac/atsaml22j/src/tcc0/per.rs @@ -0,0 +1,80 @@ +#[doc = "Register `PER` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER` reader - Period Value"] +pub type PER_R = crate::FieldReader; +#[doc = "Field `PER` writer - Period Value"] +pub type PER_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PER_SPEC, u32, u32, 24, O>; +impl R { + #[doc = "Bits 0:23 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(self.bits & 0x00ff_ffff) + } +} +impl W { + #[doc = "Bits 0:23 - Period Value"] + #[inline(always)] + #[must_use] + pub fn per(&mut self) -> PER_W<0> { + PER_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per](index.html) module"] +pub struct PER_SPEC; +impl crate::RegisterSpec for PER_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [per::R](R) reader structure"] +impl crate::Readable for PER_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per::W](W) writer structure"] +impl crate::Writable for PER_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PER to value 0xffff_ffff"] +impl crate::Resettable for PER_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/pac/atsaml22j/src/tcc0/per_dith4.rs b/pac/atsaml22j/src/tcc0/per_dith4.rs new file mode 100644 index 000000000000..722ec0de87fe --- /dev/null +++ b/pac/atsaml22j/src/tcc0/per_dith4.rs @@ -0,0 +1,95 @@ +#[doc = "Register `PER_DITH4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER_DITH4` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHER` reader - Dithering Cycle Number"] +pub type DITHER_R = crate::FieldReader; +#[doc = "Field `DITHER` writer - Dithering Cycle Number"] +pub type DITHER_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PER_DITH4_SPEC, u8, u8, 4, O>; +#[doc = "Field `PER` reader - Period Value"] +pub type PER_R = crate::FieldReader; +#[doc = "Field `PER` writer - Period Value"] +pub type PER_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PER_DITH4_SPEC, u32, u32, 20, O>; +impl R { + #[doc = "Bits 0:3 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&self) -> DITHER_R { + DITHER_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:23 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new((self.bits >> 4) & 0x000f_ffff) + } +} +impl W { + #[doc = "Bits 0:3 - Dithering Cycle Number"] + #[inline(always)] + #[must_use] + pub fn dither(&mut self) -> DITHER_W<0> { + DITHER_W::new(self) + } + #[doc = "Bits 4:23 - Period Value"] + #[inline(always)] + #[must_use] + pub fn per(&mut self) -> PER_W<4> { + PER_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per_dith4](index.html) module"] +pub struct PER_DITH4_SPEC; +impl crate::RegisterSpec for PER_DITH4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [per_dith4::R](R) reader structure"] +impl crate::Readable for PER_DITH4_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per_dith4::W](W) writer structure"] +impl crate::Writable for PER_DITH4_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PER_DITH4 to value 0xffff_ffff"] +impl crate::Resettable for PER_DITH4_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/pac/atsaml22j/src/tcc0/per_dith5.rs b/pac/atsaml22j/src/tcc0/per_dith5.rs new file mode 100644 index 000000000000..137de3344d9e --- /dev/null +++ b/pac/atsaml22j/src/tcc0/per_dith5.rs @@ -0,0 +1,95 @@ +#[doc = "Register `PER_DITH5` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER_DITH5` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHER` reader - Dithering Cycle Number"] +pub type DITHER_R = crate::FieldReader; +#[doc = "Field `DITHER` writer - Dithering Cycle Number"] +pub type DITHER_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PER_DITH5_SPEC, u8, u8, 5, O>; +#[doc = "Field `PER` reader - Period Value"] +pub type PER_R = crate::FieldReader; +#[doc = "Field `PER` writer - Period Value"] +pub type PER_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PER_DITH5_SPEC, u32, u32, 19, O>; +impl R { + #[doc = "Bits 0:4 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&self) -> DITHER_R { + DITHER_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:23 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new((self.bits >> 5) & 0x0007_ffff) + } +} +impl W { + #[doc = "Bits 0:4 - Dithering Cycle Number"] + #[inline(always)] + #[must_use] + pub fn dither(&mut self) -> DITHER_W<0> { + DITHER_W::new(self) + } + #[doc = "Bits 5:23 - Period Value"] + #[inline(always)] + #[must_use] + pub fn per(&mut self) -> PER_W<5> { + PER_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per_dith5](index.html) module"] +pub struct PER_DITH5_SPEC; +impl crate::RegisterSpec for PER_DITH5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [per_dith5::R](R) reader structure"] +impl crate::Readable for PER_DITH5_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per_dith5::W](W) writer structure"] +impl crate::Writable for PER_DITH5_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PER_DITH5 to value 0xffff_ffff"] +impl crate::Resettable for PER_DITH5_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/pac/atsaml22j/src/tcc0/per_dith6.rs b/pac/atsaml22j/src/tcc0/per_dith6.rs new file mode 100644 index 000000000000..40f138085192 --- /dev/null +++ b/pac/atsaml22j/src/tcc0/per_dith6.rs @@ -0,0 +1,95 @@ +#[doc = "Register `PER_DITH6` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PER_DITH6` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHER` reader - Dithering Cycle Number"] +pub type DITHER_R = crate::FieldReader; +#[doc = "Field `DITHER` writer - Dithering Cycle Number"] +pub type DITHER_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PER_DITH6_SPEC, u8, u8, 6, O>; +#[doc = "Field `PER` reader - Period Value"] +pub type PER_R = crate::FieldReader; +#[doc = "Field `PER` writer - Period Value"] +pub type PER_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PER_DITH6_SPEC, u32, u32, 18, O>; +impl R { + #[doc = "Bits 0:5 - Dithering Cycle Number"] + #[inline(always)] + pub fn dither(&self) -> DITHER_R { + DITHER_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:23 - Period Value"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new((self.bits >> 6) & 0x0003_ffff) + } +} +impl W { + #[doc = "Bits 0:5 - Dithering Cycle Number"] + #[inline(always)] + #[must_use] + pub fn dither(&mut self) -> DITHER_W<0> { + DITHER_W::new(self) + } + #[doc = "Bits 6:23 - Period Value"] + #[inline(always)] + #[must_use] + pub fn per(&mut self) -> PER_W<6> { + PER_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [per_dith6](index.html) module"] +pub struct PER_DITH6_SPEC; +impl crate::RegisterSpec for PER_DITH6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [per_dith6::R](R) reader structure"] +impl crate::Readable for PER_DITH6_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [per_dith6::W](W) writer structure"] +impl crate::Writable for PER_DITH6_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PER_DITH6 to value 0xffff_ffff"] +impl crate::Resettable for PER_DITH6_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/pac/atsaml22j/src/tcc0/perbuf.rs b/pac/atsaml22j/src/tcc0/perbuf.rs new file mode 100644 index 000000000000..4be3c4eb5a24 --- /dev/null +++ b/pac/atsaml22j/src/tcc0/perbuf.rs @@ -0,0 +1,80 @@ +#[doc = "Register `PERBUF` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERBUF` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PERBUF` reader - Period Buffer Value"] +pub type PERBUF_R = crate::FieldReader; +#[doc = "Field `PERBUF` writer - Period Buffer Value"] +pub type PERBUF_W<'a, const O: u8> = crate::FieldWriter<'a, u32, PERBUF_SPEC, u32, u32, 24, O>; +impl R { + #[doc = "Bits 0:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&self) -> PERBUF_R { + PERBUF_R::new(self.bits & 0x00ff_ffff) + } +} +impl W { + #[doc = "Bits 0:23 - Period Buffer Value"] + #[inline(always)] + #[must_use] + pub fn perbuf(&mut self) -> PERBUF_W<0> { + PERBUF_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perbuf](index.html) module"] +pub struct PERBUF_SPEC; +impl crate::RegisterSpec for PERBUF_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perbuf::R](R) reader structure"] +impl crate::Readable for PERBUF_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perbuf::W](W) writer structure"] +impl crate::Writable for PERBUF_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PERBUF to value 0xffff_ffff"] +impl crate::Resettable for PERBUF_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/pac/atsaml22j/src/tcc0/perbuf_dith4.rs b/pac/atsaml22j/src/tcc0/perbuf_dith4.rs new file mode 100644 index 000000000000..33abe1e333f9 --- /dev/null +++ b/pac/atsaml22j/src/tcc0/perbuf_dith4.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PERBUF_DITH4` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERBUF_DITH4` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERBUF` reader - Dithering Buffer Cycle Number"] +pub type DITHERBUF_R = crate::FieldReader; +#[doc = "Field `DITHERBUF` writer - Dithering Buffer Cycle Number"] +pub type DITHERBUF_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, PERBUF_DITH4_SPEC, u8, u8, 4, O>; +#[doc = "Field `PERBUF` reader - Period Buffer Value"] +pub type PERBUF_R = crate::FieldReader; +#[doc = "Field `PERBUF` writer - Period Buffer Value"] +pub type PERBUF_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, PERBUF_DITH4_SPEC, u32, u32, 20, O>; +impl R { + #[doc = "Bits 0:3 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&self) -> DITHERBUF_R { + DITHERBUF_R::new((self.bits & 0x0f) as u8) + } + #[doc = "Bits 4:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&self) -> PERBUF_R { + PERBUF_R::new((self.bits >> 4) & 0x000f_ffff) + } +} +impl W { + #[doc = "Bits 0:3 - Dithering Buffer Cycle Number"] + #[inline(always)] + #[must_use] + pub fn ditherbuf(&mut self) -> DITHERBUF_W<0> { + DITHERBUF_W::new(self) + } + #[doc = "Bits 4:23 - Period Buffer Value"] + #[inline(always)] + #[must_use] + pub fn perbuf(&mut self) -> PERBUF_W<4> { + PERBUF_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perbuf_dith4](index.html) module"] +pub struct PERBUF_DITH4_SPEC; +impl crate::RegisterSpec for PERBUF_DITH4_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perbuf_dith4::R](R) reader structure"] +impl crate::Readable for PERBUF_DITH4_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perbuf_dith4::W](W) writer structure"] +impl crate::Writable for PERBUF_DITH4_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PERBUF_DITH4 to value 0xffff_ffff"] +impl crate::Resettable for PERBUF_DITH4_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/pac/atsaml22j/src/tcc0/perbuf_dith5.rs b/pac/atsaml22j/src/tcc0/perbuf_dith5.rs new file mode 100644 index 000000000000..caa39dee04be --- /dev/null +++ b/pac/atsaml22j/src/tcc0/perbuf_dith5.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PERBUF_DITH5` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERBUF_DITH5` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERBUF` reader - Dithering Buffer Cycle Number"] +pub type DITHERBUF_R = crate::FieldReader; +#[doc = "Field `DITHERBUF` writer - Dithering Buffer Cycle Number"] +pub type DITHERBUF_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, PERBUF_DITH5_SPEC, u8, u8, 5, O>; +#[doc = "Field `PERBUF` reader - Period Buffer Value"] +pub type PERBUF_R = crate::FieldReader; +#[doc = "Field `PERBUF` writer - Period Buffer Value"] +pub type PERBUF_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, PERBUF_DITH5_SPEC, u32, u32, 19, O>; +impl R { + #[doc = "Bits 0:4 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&self) -> DITHERBUF_R { + DITHERBUF_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 5:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&self) -> PERBUF_R { + PERBUF_R::new((self.bits >> 5) & 0x0007_ffff) + } +} +impl W { + #[doc = "Bits 0:4 - Dithering Buffer Cycle Number"] + #[inline(always)] + #[must_use] + pub fn ditherbuf(&mut self) -> DITHERBUF_W<0> { + DITHERBUF_W::new(self) + } + #[doc = "Bits 5:23 - Period Buffer Value"] + #[inline(always)] + #[must_use] + pub fn perbuf(&mut self) -> PERBUF_W<5> { + PERBUF_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perbuf_dith5](index.html) module"] +pub struct PERBUF_DITH5_SPEC; +impl crate::RegisterSpec for PERBUF_DITH5_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perbuf_dith5::R](R) reader structure"] +impl crate::Readable for PERBUF_DITH5_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perbuf_dith5::W](W) writer structure"] +impl crate::Writable for PERBUF_DITH5_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PERBUF_DITH5 to value 0xffff_ffff"] +impl crate::Resettable for PERBUF_DITH5_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/pac/atsaml22j/src/tcc0/perbuf_dith6.rs b/pac/atsaml22j/src/tcc0/perbuf_dith6.rs new file mode 100644 index 000000000000..e00bc433e7d4 --- /dev/null +++ b/pac/atsaml22j/src/tcc0/perbuf_dith6.rs @@ -0,0 +1,97 @@ +#[doc = "Register `PERBUF_DITH6` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PERBUF_DITH6` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DITHERBUF` reader - Dithering Buffer Cycle Number"] +pub type DITHERBUF_R = crate::FieldReader; +#[doc = "Field `DITHERBUF` writer - Dithering Buffer Cycle Number"] +pub type DITHERBUF_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, PERBUF_DITH6_SPEC, u8, u8, 6, O>; +#[doc = "Field `PERBUF` reader - Period Buffer Value"] +pub type PERBUF_R = crate::FieldReader; +#[doc = "Field `PERBUF` writer - Period Buffer Value"] +pub type PERBUF_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, PERBUF_DITH6_SPEC, u32, u32, 18, O>; +impl R { + #[doc = "Bits 0:5 - Dithering Buffer Cycle Number"] + #[inline(always)] + pub fn ditherbuf(&self) -> DITHERBUF_R { + DITHERBUF_R::new((self.bits & 0x3f) as u8) + } + #[doc = "Bits 6:23 - Period Buffer Value"] + #[inline(always)] + pub fn perbuf(&self) -> PERBUF_R { + PERBUF_R::new((self.bits >> 6) & 0x0003_ffff) + } +} +impl W { + #[doc = "Bits 0:5 - Dithering Buffer Cycle Number"] + #[inline(always)] + #[must_use] + pub fn ditherbuf(&mut self) -> DITHERBUF_W<0> { + DITHERBUF_W::new(self) + } + #[doc = "Bits 6:23 - Period Buffer Value"] + #[inline(always)] + #[must_use] + pub fn perbuf(&mut self) -> PERBUF_W<6> { + PERBUF_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Period Buffer\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [perbuf_dith6](index.html) module"] +pub struct PERBUF_DITH6_SPEC; +impl crate::RegisterSpec for PERBUF_DITH6_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [perbuf_dith6::R](R) reader structure"] +impl crate::Readable for PERBUF_DITH6_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [perbuf_dith6::W](W) writer structure"] +impl crate::Writable for PERBUF_DITH6_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PERBUF_DITH6 to value 0xffff_ffff"] +impl crate::Resettable for PERBUF_DITH6_SPEC { + const RESET_VALUE: Self::Ux = 0xffff_ffff; +} diff --git a/pac/atsaml22j/src/tcc0/status.rs b/pac/atsaml22j/src/tcc0/status.rs new file mode 100644 index 000000000000..b6fd68ddc581 --- /dev/null +++ b/pac/atsaml22j/src/tcc0/status.rs @@ -0,0 +1,322 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `STATUS` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `STOP` reader - Stop"] +pub type STOP_R = crate::BitReader; +#[doc = "Field `IDX` reader - Ramp"] +pub type IDX_R = crate::BitReader; +#[doc = "Field `UFS` reader - Non-recoverable Update Fault State"] +pub type UFS_R = crate::BitReader; +#[doc = "Field `UFS` writer - Non-recoverable Update Fault State"] +pub type UFS_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +#[doc = "Field `DFS` reader - Non-Recoverable Debug Fault State"] +pub type DFS_R = crate::BitReader; +#[doc = "Field `DFS` writer - Non-Recoverable Debug Fault State"] +pub type DFS_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +#[doc = "Field `SLAVE` reader - Slave"] +pub type SLAVE_R = crate::BitReader; +#[doc = "Field `PATTBUFV` reader - Pattern Buffer Valid"] +pub type PATTBUFV_R = crate::BitReader; +#[doc = "Field `PATTBUFV` writer - Pattern Buffer Valid"] +pub type PATTBUFV_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +#[doc = "Field `PERBUFV` reader - Period Buffer Valid"] +pub type PERBUFV_R = crate::BitReader; +#[doc = "Field `PERBUFV` writer - Period Buffer Valid"] +pub type PERBUFV_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +#[doc = "Field `FAULTAIN` reader - Recoverable Fault A Input"] +pub type FAULTAIN_R = crate::BitReader; +#[doc = "Field `FAULTBIN` reader - Recoverable Fault B Input"] +pub type FAULTBIN_R = crate::BitReader; +#[doc = "Field `FAULT0IN` reader - Non-Recoverable Fault0 Input"] +pub type FAULT0IN_R = crate::BitReader; +#[doc = "Field `FAULT1IN` reader - Non-Recoverable Fault1 Input"] +pub type FAULT1IN_R = crate::BitReader; +#[doc = "Field `FAULTA` reader - Recoverable Fault A State"] +pub type FAULTA_R = crate::BitReader; +#[doc = "Field `FAULTA` writer - Recoverable Fault A State"] +pub type FAULTA_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +#[doc = "Field `FAULTB` reader - Recoverable Fault B State"] +pub type FAULTB_R = crate::BitReader; +#[doc = "Field `FAULTB` writer - Recoverable Fault B State"] +pub type FAULTB_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +#[doc = "Field `FAULT0` reader - Non-Recoverable Fault 0 State"] +pub type FAULT0_R = crate::BitReader; +#[doc = "Field `FAULT0` writer - Non-Recoverable Fault 0 State"] +pub type FAULT0_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +#[doc = "Field `FAULT1` reader - Non-Recoverable Fault 1 State"] +pub type FAULT1_R = crate::BitReader; +#[doc = "Field `FAULT1` writer - Non-Recoverable Fault 1 State"] +pub type FAULT1_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +#[doc = "Field `CCBUFV0` reader - Compare Channel 0 Buffer Valid"] +pub type CCBUFV0_R = crate::BitReader; +#[doc = "Field `CCBUFV0` writer - Compare Channel 0 Buffer Valid"] +pub type CCBUFV0_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +#[doc = "Field `CCBUFV1` reader - Compare Channel 1 Buffer Valid"] +pub type CCBUFV1_R = crate::BitReader; +#[doc = "Field `CCBUFV1` writer - Compare Channel 1 Buffer Valid"] +pub type CCBUFV1_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +#[doc = "Field `CCBUFV2` reader - Compare Channel 2 Buffer Valid"] +pub type CCBUFV2_R = crate::BitReader; +#[doc = "Field `CCBUFV2` writer - Compare Channel 2 Buffer Valid"] +pub type CCBUFV2_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +#[doc = "Field `CCBUFV3` reader - Compare Channel 3 Buffer Valid"] +pub type CCBUFV3_R = crate::BitReader; +#[doc = "Field `CCBUFV3` writer - Compare Channel 3 Buffer Valid"] +pub type CCBUFV3_W<'a, const O: u8> = crate::BitWriter<'a, u32, STATUS_SPEC, bool, O>; +#[doc = "Field `CMP0` reader - Compare Channel 0 Value"] +pub type CMP0_R = crate::BitReader; +#[doc = "Field `CMP1` reader - Compare Channel 1 Value"] +pub type CMP1_R = crate::BitReader; +#[doc = "Field `CMP2` reader - Compare Channel 2 Value"] +pub type CMP2_R = crate::BitReader; +#[doc = "Field `CMP3` reader - Compare Channel 3 Value"] +pub type CMP3_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Stop"] + #[inline(always)] + pub fn stop(&self) -> STOP_R { + STOP_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Ramp"] + #[inline(always)] + pub fn idx(&self) -> IDX_R { + IDX_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Non-recoverable Update Fault State"] + #[inline(always)] + pub fn ufs(&self) -> UFS_R { + UFS_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Non-Recoverable Debug Fault State"] + #[inline(always)] + pub fn dfs(&self) -> DFS_R { + DFS_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Slave"] + #[inline(always)] + pub fn slave(&self) -> SLAVE_R { + SLAVE_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Pattern Buffer Valid"] + #[inline(always)] + pub fn pattbufv(&self) -> PATTBUFV_R { + PATTBUFV_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 7 - Period Buffer Valid"] + #[inline(always)] + pub fn perbufv(&self) -> PERBUFV_R { + PERBUFV_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Recoverable Fault A Input"] + #[inline(always)] + pub fn faultain(&self) -> FAULTAIN_R { + FAULTAIN_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Recoverable Fault B Input"] + #[inline(always)] + pub fn faultbin(&self) -> FAULTBIN_R { + FAULTBIN_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Non-Recoverable Fault0 Input"] + #[inline(always)] + pub fn fault0in(&self) -> FAULT0IN_R { + FAULT0IN_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Non-Recoverable Fault1 Input"] + #[inline(always)] + pub fn fault1in(&self) -> FAULT1IN_R { + FAULT1IN_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 12 - Recoverable Fault A State"] + #[inline(always)] + pub fn faulta(&self) -> FAULTA_R { + FAULTA_R::new(((self.bits >> 12) & 1) != 0) + } + #[doc = "Bit 13 - Recoverable Fault B State"] + #[inline(always)] + pub fn faultb(&self) -> FAULTB_R { + FAULTB_R::new(((self.bits >> 13) & 1) != 0) + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 State"] + #[inline(always)] + pub fn fault0(&self) -> FAULT0_R { + FAULT0_R::new(((self.bits >> 14) & 1) != 0) + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 State"] + #[inline(always)] + pub fn fault1(&self) -> FAULT1_R { + FAULT1_R::new(((self.bits >> 15) & 1) != 0) + } + #[doc = "Bit 16 - Compare Channel 0 Buffer Valid"] + #[inline(always)] + pub fn ccbufv0(&self) -> CCBUFV0_R { + CCBUFV0_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Compare Channel 1 Buffer Valid"] + #[inline(always)] + pub fn ccbufv1(&self) -> CCBUFV1_R { + CCBUFV1_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Compare Channel 2 Buffer Valid"] + #[inline(always)] + pub fn ccbufv2(&self) -> CCBUFV2_R { + CCBUFV2_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Compare Channel 3 Buffer Valid"] + #[inline(always)] + pub fn ccbufv3(&self) -> CCBUFV3_R { + CCBUFV3_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 24 - Compare Channel 0 Value"] + #[inline(always)] + pub fn cmp0(&self) -> CMP0_R { + CMP0_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Compare Channel 1 Value"] + #[inline(always)] + pub fn cmp1(&self) -> CMP1_R { + CMP1_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Compare Channel 2 Value"] + #[inline(always)] + pub fn cmp2(&self) -> CMP2_R { + CMP2_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Compare Channel 3 Value"] + #[inline(always)] + pub fn cmp3(&self) -> CMP3_R { + CMP3_R::new(((self.bits >> 27) & 1) != 0) + } +} +impl W { + #[doc = "Bit 2 - Non-recoverable Update Fault State"] + #[inline(always)] + #[must_use] + pub fn ufs(&mut self) -> UFS_W<2> { + UFS_W::new(self) + } + #[doc = "Bit 3 - Non-Recoverable Debug Fault State"] + #[inline(always)] + #[must_use] + pub fn dfs(&mut self) -> DFS_W<3> { + DFS_W::new(self) + } + #[doc = "Bit 5 - Pattern Buffer Valid"] + #[inline(always)] + #[must_use] + pub fn pattbufv(&mut self) -> PATTBUFV_W<5> { + PATTBUFV_W::new(self) + } + #[doc = "Bit 7 - Period Buffer Valid"] + #[inline(always)] + #[must_use] + pub fn perbufv(&mut self) -> PERBUFV_W<7> { + PERBUFV_W::new(self) + } + #[doc = "Bit 12 - Recoverable Fault A State"] + #[inline(always)] + #[must_use] + pub fn faulta(&mut self) -> FAULTA_W<12> { + FAULTA_W::new(self) + } + #[doc = "Bit 13 - Recoverable Fault B State"] + #[inline(always)] + #[must_use] + pub fn faultb(&mut self) -> FAULTB_W<13> { + FAULTB_W::new(self) + } + #[doc = "Bit 14 - Non-Recoverable Fault 0 State"] + #[inline(always)] + #[must_use] + pub fn fault0(&mut self) -> FAULT0_W<14> { + FAULT0_W::new(self) + } + #[doc = "Bit 15 - Non-Recoverable Fault 1 State"] + #[inline(always)] + #[must_use] + pub fn fault1(&mut self) -> FAULT1_W<15> { + FAULT1_W::new(self) + } + #[doc = "Bit 16 - Compare Channel 0 Buffer Valid"] + #[inline(always)] + #[must_use] + pub fn ccbufv0(&mut self) -> CCBUFV0_W<16> { + CCBUFV0_W::new(self) + } + #[doc = "Bit 17 - Compare Channel 1 Buffer Valid"] + #[inline(always)] + #[must_use] + pub fn ccbufv1(&mut self) -> CCBUFV1_W<17> { + CCBUFV1_W::new(self) + } + #[doc = "Bit 18 - Compare Channel 2 Buffer Valid"] + #[inline(always)] + #[must_use] + pub fn ccbufv2(&mut self) -> CCBUFV2_W<18> { + CCBUFV2_W::new(self) + } + #[doc = "Bit 19 - Compare Channel 3 Buffer Valid"] + #[inline(always)] + #[must_use] + pub fn ccbufv3(&mut self) -> CCBUFV3_W<19> { + CCBUFV3_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Status\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"] +impl crate::Writable for STATUS_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets STATUS to value 0x01"] +impl crate::Resettable for STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/pac/atsaml22j/src/tcc0/syncbusy.rs b/pac/atsaml22j/src/tcc0/syncbusy.rs new file mode 100644 index 000000000000..9a82ee0c69c1 --- /dev/null +++ b/pac/atsaml22j/src/tcc0/syncbusy.rs @@ -0,0 +1,114 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Swrst Busy"] +pub type SWRST_R = crate::BitReader; +#[doc = "Field `ENABLE` reader - Enable Busy"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `CTRLB` reader - Ctrlb Busy"] +pub type CTRLB_R = crate::BitReader; +#[doc = "Field `STATUS` reader - Status Busy"] +pub type STATUS_R = crate::BitReader; +#[doc = "Field `COUNT` reader - Count Busy"] +pub type COUNT_R = crate::BitReader; +#[doc = "Field `PATT` reader - Pattern Busy"] +pub type PATT_R = crate::BitReader; +#[doc = "Field `WAVE` reader - Wave Busy"] +pub type WAVE_R = crate::BitReader; +#[doc = "Field `PER` reader - Period Busy"] +pub type PER_R = crate::BitReader; +#[doc = "Field `CC0` reader - Compare Channel 0 Busy"] +pub type CC0_R = crate::BitReader; +#[doc = "Field `CC1` reader - Compare Channel 1 Busy"] +pub type CC1_R = crate::BitReader; +#[doc = "Field `CC2` reader - Compare Channel 2 Busy"] +pub type CC2_R = crate::BitReader; +#[doc = "Field `CC3` reader - Compare Channel 3 Busy"] +pub type CC3_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Swrst Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Ctrlb Busy"] + #[inline(always)] + pub fn ctrlb(&self) -> CTRLB_R { + CTRLB_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Status Busy"] + #[inline(always)] + pub fn status(&self) -> STATUS_R { + STATUS_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Count Busy"] + #[inline(always)] + pub fn count(&self) -> COUNT_R { + COUNT_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Pattern Busy"] + #[inline(always)] + pub fn patt(&self) -> PATT_R { + PATT_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Wave Busy"] + #[inline(always)] + pub fn wave(&self) -> WAVE_R { + WAVE_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Period Busy"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Compare Channel 0 Busy"] + #[inline(always)] + pub fn cc0(&self) -> CC0_R { + CC0_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Compare Channel 1 Busy"] + #[inline(always)] + pub fn cc1(&self) -> CC1_R { + CC1_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Compare Channel 2 Busy"] + #[inline(always)] + pub fn cc2(&self) -> CC2_R { + CC2_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Compare Channel 3 Busy"] + #[inline(always)] + pub fn cc3(&self) -> CC3_R { + CC3_R::new(((self.bits >> 11) & 1) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tcc0/wave.rs b/pac/atsaml22j/src/tcc0/wave.rs new file mode 100644 index 000000000000..e57c40c86d56 --- /dev/null +++ b/pac/atsaml22j/src/tcc0/wave.rs @@ -0,0 +1,479 @@ +#[doc = "Register `WAVE` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WAVE` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `WAVEGEN` reader - Waveform Generation"] +pub type WAVEGEN_R = crate::FieldReader; +#[doc = "Waveform Generation\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum WAVEGENSELECT_A { + #[doc = "0: Normal frequency"] + NFRQ = 0, + #[doc = "1: Match frequency"] + MFRQ = 1, + #[doc = "2: Normal PWM"] + NPWM = 2, + #[doc = "4: Dual-slope critical"] + DSCRITICAL = 4, + #[doc = "5: Dual-slope with interrupt/event condition when COUNT reaches ZERO"] + DSBOTTOM = 5, + #[doc = "6: Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP"] + DSBOTH = 6, + #[doc = "7: Dual-slope with interrupt/event condition when COUNT reaches TOP"] + DSTOP = 7, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WAVEGENSELECT_A) -> Self { + variant as _ + } +} +impl WAVEGEN_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WAVEGENSELECT_A::NFRQ), + 1 => Some(WAVEGENSELECT_A::MFRQ), + 2 => Some(WAVEGENSELECT_A::NPWM), + 4 => Some(WAVEGENSELECT_A::DSCRITICAL), + 5 => Some(WAVEGENSELECT_A::DSBOTTOM), + 6 => Some(WAVEGENSELECT_A::DSBOTH), + 7 => Some(WAVEGENSELECT_A::DSTOP), + _ => None, + } + } + #[doc = "Checks if the value of the field is `NFRQ`"] + #[inline(always)] + pub fn is_nfrq(&self) -> bool { + *self == WAVEGENSELECT_A::NFRQ + } + #[doc = "Checks if the value of the field is `MFRQ`"] + #[inline(always)] + pub fn is_mfrq(&self) -> bool { + *self == WAVEGENSELECT_A::MFRQ + } + #[doc = "Checks if the value of the field is `NPWM`"] + #[inline(always)] + pub fn is_npwm(&self) -> bool { + *self == WAVEGENSELECT_A::NPWM + } + #[doc = "Checks if the value of the field is `DSCRITICAL`"] + #[inline(always)] + pub fn is_dscritical(&self) -> bool { + *self == WAVEGENSELECT_A::DSCRITICAL + } + #[doc = "Checks if the value of the field is `DSBOTTOM`"] + #[inline(always)] + pub fn is_dsbottom(&self) -> bool { + *self == WAVEGENSELECT_A::DSBOTTOM + } + #[doc = "Checks if the value of the field is `DSBOTH`"] + #[inline(always)] + pub fn is_dsboth(&self) -> bool { + *self == WAVEGENSELECT_A::DSBOTH + } + #[doc = "Checks if the value of the field is `DSTOP`"] + #[inline(always)] + pub fn is_dstop(&self) -> bool { + *self == WAVEGENSELECT_A::DSTOP + } +} +#[doc = "Field `WAVEGEN` writer - Waveform Generation"] +pub type WAVEGEN_W<'a, const O: u8> = + crate::FieldWriter<'a, u32, WAVE_SPEC, u8, WAVEGENSELECT_A, 3, O>; +impl<'a, const O: u8> WAVEGEN_W<'a, O> { + #[doc = "Normal frequency"] + #[inline(always)] + pub fn nfrq(self) -> &'a mut W { + self.variant(WAVEGENSELECT_A::NFRQ) + } + #[doc = "Match frequency"] + #[inline(always)] + pub fn mfrq(self) -> &'a mut W { + self.variant(WAVEGENSELECT_A::MFRQ) + } + #[doc = "Normal PWM"] + #[inline(always)] + pub fn npwm(self) -> &'a mut W { + self.variant(WAVEGENSELECT_A::NPWM) + } + #[doc = "Dual-slope critical"] + #[inline(always)] + pub fn dscritical(self) -> &'a mut W { + self.variant(WAVEGENSELECT_A::DSCRITICAL) + } + #[doc = "Dual-slope with interrupt/event condition when COUNT reaches ZERO"] + #[inline(always)] + pub fn dsbottom(self) -> &'a mut W { + self.variant(WAVEGENSELECT_A::DSBOTTOM) + } + #[doc = "Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP"] + #[inline(always)] + pub fn dsboth(self) -> &'a mut W { + self.variant(WAVEGENSELECT_A::DSBOTH) + } + #[doc = "Dual-slope with interrupt/event condition when COUNT reaches TOP"] + #[inline(always)] + pub fn dstop(self) -> &'a mut W { + self.variant(WAVEGENSELECT_A::DSTOP) + } +} +#[doc = "Field `RAMP` reader - Ramp Mode"] +pub type RAMP_R = crate::FieldReader; +#[doc = "Ramp Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum RAMPSELECT_A { + #[doc = "0: RAMP1 operation"] + RAMP1 = 0, + #[doc = "1: Alternative RAMP2 operation"] + RAMP2A = 1, + #[doc = "2: RAMP2 operation"] + RAMP2 = 2, + #[doc = "3: Critical RAMP2 operation"] + RAMP2C = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: RAMPSELECT_A) -> Self { + variant as _ + } +} +impl RAMP_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> RAMPSELECT_A { + match self.bits { + 0 => RAMPSELECT_A::RAMP1, + 1 => RAMPSELECT_A::RAMP2A, + 2 => RAMPSELECT_A::RAMP2, + 3 => RAMPSELECT_A::RAMP2C, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `RAMP1`"] + #[inline(always)] + pub fn is_ramp1(&self) -> bool { + *self == RAMPSELECT_A::RAMP1 + } + #[doc = "Checks if the value of the field is `RAMP2A`"] + #[inline(always)] + pub fn is_ramp2a(&self) -> bool { + *self == RAMPSELECT_A::RAMP2A + } + #[doc = "Checks if the value of the field is `RAMP2`"] + #[inline(always)] + pub fn is_ramp2(&self) -> bool { + *self == RAMPSELECT_A::RAMP2 + } + #[doc = "Checks if the value of the field is `RAMP2C`"] + #[inline(always)] + pub fn is_ramp2c(&self) -> bool { + *self == RAMPSELECT_A::RAMP2C + } +} +#[doc = "Field `RAMP` writer - Ramp Mode"] +pub type RAMP_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u32, WAVE_SPEC, u8, RAMPSELECT_A, 2, O>; +impl<'a, const O: u8> RAMP_W<'a, O> { + #[doc = "RAMP1 operation"] + #[inline(always)] + pub fn ramp1(self) -> &'a mut W { + self.variant(RAMPSELECT_A::RAMP1) + } + #[doc = "Alternative RAMP2 operation"] + #[inline(always)] + pub fn ramp2a(self) -> &'a mut W { + self.variant(RAMPSELECT_A::RAMP2A) + } + #[doc = "RAMP2 operation"] + #[inline(always)] + pub fn ramp2(self) -> &'a mut W { + self.variant(RAMPSELECT_A::RAMP2) + } + #[doc = "Critical RAMP2 operation"] + #[inline(always)] + pub fn ramp2c(self) -> &'a mut W { + self.variant(RAMPSELECT_A::RAMP2C) + } +} +#[doc = "Field `CIPEREN` reader - Circular period Enable"] +pub type CIPEREN_R = crate::BitReader; +#[doc = "Field `CIPEREN` writer - Circular period Enable"] +pub type CIPEREN_W<'a, const O: u8> = crate::BitWriter<'a, u32, WAVE_SPEC, bool, O>; +#[doc = "Field `CICCEN0` reader - Circular Channel 0 Enable"] +pub type CICCEN0_R = crate::BitReader; +#[doc = "Field `CICCEN0` writer - Circular Channel 0 Enable"] +pub type CICCEN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, WAVE_SPEC, bool, O>; +#[doc = "Field `CICCEN1` reader - Circular Channel 1 Enable"] +pub type CICCEN1_R = crate::BitReader; +#[doc = "Field `CICCEN1` writer - Circular Channel 1 Enable"] +pub type CICCEN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, WAVE_SPEC, bool, O>; +#[doc = "Field `CICCEN2` reader - Circular Channel 2 Enable"] +pub type CICCEN2_R = crate::BitReader; +#[doc = "Field `CICCEN2` writer - Circular Channel 2 Enable"] +pub type CICCEN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, WAVE_SPEC, bool, O>; +#[doc = "Field `CICCEN3` reader - Circular Channel 3 Enable"] +pub type CICCEN3_R = crate::BitReader; +#[doc = "Field `CICCEN3` writer - Circular Channel 3 Enable"] +pub type CICCEN3_W<'a, const O: u8> = crate::BitWriter<'a, u32, WAVE_SPEC, bool, O>; +#[doc = "Field `POL0` reader - Channel 0 Polarity"] +pub type POL0_R = crate::BitReader; +#[doc = "Field `POL0` writer - Channel 0 Polarity"] +pub type POL0_W<'a, const O: u8> = crate::BitWriter<'a, u32, WAVE_SPEC, bool, O>; +#[doc = "Field `POL1` reader - Channel 1 Polarity"] +pub type POL1_R = crate::BitReader; +#[doc = "Field `POL1` writer - Channel 1 Polarity"] +pub type POL1_W<'a, const O: u8> = crate::BitWriter<'a, u32, WAVE_SPEC, bool, O>; +#[doc = "Field `POL2` reader - Channel 2 Polarity"] +pub type POL2_R = crate::BitReader; +#[doc = "Field `POL2` writer - Channel 2 Polarity"] +pub type POL2_W<'a, const O: u8> = crate::BitWriter<'a, u32, WAVE_SPEC, bool, O>; +#[doc = "Field `POL3` reader - Channel 3 Polarity"] +pub type POL3_R = crate::BitReader; +#[doc = "Field `POL3` writer - Channel 3 Polarity"] +pub type POL3_W<'a, const O: u8> = crate::BitWriter<'a, u32, WAVE_SPEC, bool, O>; +#[doc = "Field `SWAP0` reader - Swap DTI Output Pair 0"] +pub type SWAP0_R = crate::BitReader; +#[doc = "Field `SWAP0` writer - Swap DTI Output Pair 0"] +pub type SWAP0_W<'a, const O: u8> = crate::BitWriter<'a, u32, WAVE_SPEC, bool, O>; +#[doc = "Field `SWAP1` reader - Swap DTI Output Pair 1"] +pub type SWAP1_R = crate::BitReader; +#[doc = "Field `SWAP1` writer - Swap DTI Output Pair 1"] +pub type SWAP1_W<'a, const O: u8> = crate::BitWriter<'a, u32, WAVE_SPEC, bool, O>; +#[doc = "Field `SWAP2` reader - Swap DTI Output Pair 2"] +pub type SWAP2_R = crate::BitReader; +#[doc = "Field `SWAP2` writer - Swap DTI Output Pair 2"] +pub type SWAP2_W<'a, const O: u8> = crate::BitWriter<'a, u32, WAVE_SPEC, bool, O>; +#[doc = "Field `SWAP3` reader - Swap DTI Output Pair 3"] +pub type SWAP3_R = crate::BitReader; +#[doc = "Field `SWAP3` writer - Swap DTI Output Pair 3"] +pub type SWAP3_W<'a, const O: u8> = crate::BitWriter<'a, u32, WAVE_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:2 - Waveform Generation"] + #[inline(always)] + pub fn wavegen(&self) -> WAVEGEN_R { + WAVEGEN_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 4:5 - Ramp Mode"] + #[inline(always)] + pub fn ramp(&self) -> RAMP_R { + RAMP_R::new(((self.bits >> 4) & 3) as u8) + } + #[doc = "Bit 7 - Circular period Enable"] + #[inline(always)] + pub fn ciperen(&self) -> CIPEREN_R { + CIPEREN_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Circular Channel 0 Enable"] + #[inline(always)] + pub fn ciccen0(&self) -> CICCEN0_R { + CICCEN0_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Circular Channel 1 Enable"] + #[inline(always)] + pub fn ciccen1(&self) -> CICCEN1_R { + CICCEN1_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Circular Channel 2 Enable"] + #[inline(always)] + pub fn ciccen2(&self) -> CICCEN2_R { + CICCEN2_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Circular Channel 3 Enable"] + #[inline(always)] + pub fn ciccen3(&self) -> CICCEN3_R { + CICCEN3_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bit 16 - Channel 0 Polarity"] + #[inline(always)] + pub fn pol0(&self) -> POL0_R { + POL0_R::new(((self.bits >> 16) & 1) != 0) + } + #[doc = "Bit 17 - Channel 1 Polarity"] + #[inline(always)] + pub fn pol1(&self) -> POL1_R { + POL1_R::new(((self.bits >> 17) & 1) != 0) + } + #[doc = "Bit 18 - Channel 2 Polarity"] + #[inline(always)] + pub fn pol2(&self) -> POL2_R { + POL2_R::new(((self.bits >> 18) & 1) != 0) + } + #[doc = "Bit 19 - Channel 3 Polarity"] + #[inline(always)] + pub fn pol3(&self) -> POL3_R { + POL3_R::new(((self.bits >> 19) & 1) != 0) + } + #[doc = "Bit 24 - Swap DTI Output Pair 0"] + #[inline(always)] + pub fn swap0(&self) -> SWAP0_R { + SWAP0_R::new(((self.bits >> 24) & 1) != 0) + } + #[doc = "Bit 25 - Swap DTI Output Pair 1"] + #[inline(always)] + pub fn swap1(&self) -> SWAP1_R { + SWAP1_R::new(((self.bits >> 25) & 1) != 0) + } + #[doc = "Bit 26 - Swap DTI Output Pair 2"] + #[inline(always)] + pub fn swap2(&self) -> SWAP2_R { + SWAP2_R::new(((self.bits >> 26) & 1) != 0) + } + #[doc = "Bit 27 - Swap DTI Output Pair 3"] + #[inline(always)] + pub fn swap3(&self) -> SWAP3_R { + SWAP3_R::new(((self.bits >> 27) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - Waveform Generation"] + #[inline(always)] + #[must_use] + pub fn wavegen(&mut self) -> WAVEGEN_W<0> { + WAVEGEN_W::new(self) + } + #[doc = "Bits 4:5 - Ramp Mode"] + #[inline(always)] + #[must_use] + pub fn ramp(&mut self) -> RAMP_W<4> { + RAMP_W::new(self) + } + #[doc = "Bit 7 - Circular period Enable"] + #[inline(always)] + #[must_use] + pub fn ciperen(&mut self) -> CIPEREN_W<7> { + CIPEREN_W::new(self) + } + #[doc = "Bit 8 - Circular Channel 0 Enable"] + #[inline(always)] + #[must_use] + pub fn ciccen0(&mut self) -> CICCEN0_W<8> { + CICCEN0_W::new(self) + } + #[doc = "Bit 9 - Circular Channel 1 Enable"] + #[inline(always)] + #[must_use] + pub fn ciccen1(&mut self) -> CICCEN1_W<9> { + CICCEN1_W::new(self) + } + #[doc = "Bit 10 - Circular Channel 2 Enable"] + #[inline(always)] + #[must_use] + pub fn ciccen2(&mut self) -> CICCEN2_W<10> { + CICCEN2_W::new(self) + } + #[doc = "Bit 11 - Circular Channel 3 Enable"] + #[inline(always)] + #[must_use] + pub fn ciccen3(&mut self) -> CICCEN3_W<11> { + CICCEN3_W::new(self) + } + #[doc = "Bit 16 - Channel 0 Polarity"] + #[inline(always)] + #[must_use] + pub fn pol0(&mut self) -> POL0_W<16> { + POL0_W::new(self) + } + #[doc = "Bit 17 - Channel 1 Polarity"] + #[inline(always)] + #[must_use] + pub fn pol1(&mut self) -> POL1_W<17> { + POL1_W::new(self) + } + #[doc = "Bit 18 - Channel 2 Polarity"] + #[inline(always)] + #[must_use] + pub fn pol2(&mut self) -> POL2_W<18> { + POL2_W::new(self) + } + #[doc = "Bit 19 - Channel 3 Polarity"] + #[inline(always)] + #[must_use] + pub fn pol3(&mut self) -> POL3_W<19> { + POL3_W::new(self) + } + #[doc = "Bit 24 - Swap DTI Output Pair 0"] + #[inline(always)] + #[must_use] + pub fn swap0(&mut self) -> SWAP0_W<24> { + SWAP0_W::new(self) + } + #[doc = "Bit 25 - Swap DTI Output Pair 1"] + #[inline(always)] + #[must_use] + pub fn swap1(&mut self) -> SWAP1_W<25> { + SWAP1_W::new(self) + } + #[doc = "Bit 26 - Swap DTI Output Pair 2"] + #[inline(always)] + #[must_use] + pub fn swap2(&mut self) -> SWAP2_W<26> { + SWAP2_W::new(self) + } + #[doc = "Bit 27 - Swap DTI Output Pair 3"] + #[inline(always)] + #[must_use] + pub fn swap3(&mut self) -> SWAP3_W<27> { + SWAP3_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Waveform Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wave](index.html) module"] +pub struct WAVE_SPEC; +impl crate::RegisterSpec for WAVE_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wave::R](R) reader structure"] +impl crate::Readable for WAVE_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wave::W](W) writer structure"] +impl crate::Writable for WAVE_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets WAVE to value 0"] +impl crate::Resettable for WAVE_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/tcc0/wexctrl.rs b/pac/atsaml22j/src/tcc0/wexctrl.rs new file mode 100644 index 000000000000..c2f0cd967e49 --- /dev/null +++ b/pac/atsaml22j/src/tcc0/wexctrl.rs @@ -0,0 +1,170 @@ +#[doc = "Register `WEXCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `WEXCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `OTMX` reader - Output Matrix"] +pub type OTMX_R = crate::FieldReader; +#[doc = "Field `OTMX` writer - Output Matrix"] +pub type OTMX_W<'a, const O: u8> = crate::FieldWriter<'a, u32, WEXCTRL_SPEC, u8, u8, 2, O>; +#[doc = "Field `DTIEN0` reader - Dead-time Insertion Generator 0 Enable"] +pub type DTIEN0_R = crate::BitReader; +#[doc = "Field `DTIEN0` writer - Dead-time Insertion Generator 0 Enable"] +pub type DTIEN0_W<'a, const O: u8> = crate::BitWriter<'a, u32, WEXCTRL_SPEC, bool, O>; +#[doc = "Field `DTIEN1` reader - Dead-time Insertion Generator 1 Enable"] +pub type DTIEN1_R = crate::BitReader; +#[doc = "Field `DTIEN1` writer - Dead-time Insertion Generator 1 Enable"] +pub type DTIEN1_W<'a, const O: u8> = crate::BitWriter<'a, u32, WEXCTRL_SPEC, bool, O>; +#[doc = "Field `DTIEN2` reader - Dead-time Insertion Generator 2 Enable"] +pub type DTIEN2_R = crate::BitReader; +#[doc = "Field `DTIEN2` writer - Dead-time Insertion Generator 2 Enable"] +pub type DTIEN2_W<'a, const O: u8> = crate::BitWriter<'a, u32, WEXCTRL_SPEC, bool, O>; +#[doc = "Field `DTIEN3` reader - Dead-time Insertion Generator 3 Enable"] +pub type DTIEN3_R = crate::BitReader; +#[doc = "Field `DTIEN3` writer - Dead-time Insertion Generator 3 Enable"] +pub type DTIEN3_W<'a, const O: u8> = crate::BitWriter<'a, u32, WEXCTRL_SPEC, bool, O>; +#[doc = "Field `DTLS` reader - Dead-time Low Side Outputs Value"] +pub type DTLS_R = crate::FieldReader; +#[doc = "Field `DTLS` writer - Dead-time Low Side Outputs Value"] +pub type DTLS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, WEXCTRL_SPEC, u8, u8, 8, O>; +#[doc = "Field `DTHS` reader - Dead-time High Side Outputs Value"] +pub type DTHS_R = crate::FieldReader; +#[doc = "Field `DTHS` writer - Dead-time High Side Outputs Value"] +pub type DTHS_W<'a, const O: u8> = crate::FieldWriter<'a, u32, WEXCTRL_SPEC, u8, u8, 8, O>; +impl R { + #[doc = "Bits 0:1 - Output Matrix"] + #[inline(always)] + pub fn otmx(&self) -> OTMX_R { + OTMX_R::new((self.bits & 3) as u8) + } + #[doc = "Bit 8 - Dead-time Insertion Generator 0 Enable"] + #[inline(always)] + pub fn dtien0(&self) -> DTIEN0_R { + DTIEN0_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Dead-time Insertion Generator 1 Enable"] + #[inline(always)] + pub fn dtien1(&self) -> DTIEN1_R { + DTIEN1_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bit 10 - Dead-time Insertion Generator 2 Enable"] + #[inline(always)] + pub fn dtien2(&self) -> DTIEN2_R { + DTIEN2_R::new(((self.bits >> 10) & 1) != 0) + } + #[doc = "Bit 11 - Dead-time Insertion Generator 3 Enable"] + #[inline(always)] + pub fn dtien3(&self) -> DTIEN3_R { + DTIEN3_R::new(((self.bits >> 11) & 1) != 0) + } + #[doc = "Bits 16:23 - Dead-time Low Side Outputs Value"] + #[inline(always)] + pub fn dtls(&self) -> DTLS_R { + DTLS_R::new(((self.bits >> 16) & 0xff) as u8) + } + #[doc = "Bits 24:31 - Dead-time High Side Outputs Value"] + #[inline(always)] + pub fn dths(&self) -> DTHS_R { + DTHS_R::new(((self.bits >> 24) & 0xff) as u8) + } +} +impl W { + #[doc = "Bits 0:1 - Output Matrix"] + #[inline(always)] + #[must_use] + pub fn otmx(&mut self) -> OTMX_W<0> { + OTMX_W::new(self) + } + #[doc = "Bit 8 - Dead-time Insertion Generator 0 Enable"] + #[inline(always)] + #[must_use] + pub fn dtien0(&mut self) -> DTIEN0_W<8> { + DTIEN0_W::new(self) + } + #[doc = "Bit 9 - Dead-time Insertion Generator 1 Enable"] + #[inline(always)] + #[must_use] + pub fn dtien1(&mut self) -> DTIEN1_W<9> { + DTIEN1_W::new(self) + } + #[doc = "Bit 10 - Dead-time Insertion Generator 2 Enable"] + #[inline(always)] + #[must_use] + pub fn dtien2(&mut self) -> DTIEN2_W<10> { + DTIEN2_W::new(self) + } + #[doc = "Bit 11 - Dead-time Insertion Generator 3 Enable"] + #[inline(always)] + #[must_use] + pub fn dtien3(&mut self) -> DTIEN3_W<11> { + DTIEN3_W::new(self) + } + #[doc = "Bits 16:23 - Dead-time Low Side Outputs Value"] + #[inline(always)] + #[must_use] + pub fn dtls(&mut self) -> DTLS_W<16> { + DTLS_W::new(self) + } + #[doc = "Bits 24:31 - Dead-time High Side Outputs Value"] + #[inline(always)] + #[must_use] + pub fn dths(&mut self) -> DTHS_W<24> { + DTHS_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Waveform Extension Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [wexctrl](index.html) module"] +pub struct WEXCTRL_SPEC; +impl crate::RegisterSpec for WEXCTRL_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [wexctrl::R](R) reader structure"] +impl crate::Readable for WEXCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [wexctrl::W](W) writer structure"] +impl crate::Writable for WEXCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets WEXCTRL to value 0"] +impl crate::Resettable for WEXCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/trng.rs b/pac/atsaml22j/src/trng.rs new file mode 100644 index 000000000000..09d5362dda0d --- /dev/null +++ b/pac/atsaml22j/src/trng.rs @@ -0,0 +1,43 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control A"] + pub ctrla: CTRLA, + _reserved1: [u8; 0x03], + #[doc = "0x04 - Event Control"] + pub evctrl: EVCTRL, + _reserved2: [u8; 0x03], + #[doc = "0x08 - Interrupt Enable Clear"] + pub intenclr: INTENCLR, + #[doc = "0x09 - Interrupt Enable Set"] + pub intenset: INTENSET, + #[doc = "0x0a - Interrupt Flag Status and Clear"] + pub intflag: INTFLAG, + _reserved5: [u8; 0x15], + #[doc = "0x20 - Output Data"] + pub data: DATA, +} +#[doc = "CTRLA (rw) register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "EVCTRL (rw) register accessor: an alias for `Reg`"] +pub type EVCTRL = crate::Reg; +#[doc = "Event Control"] +pub mod evctrl; +#[doc = "INTENCLR (rw) register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET (rw) register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG (rw) register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "DATA (r) register accessor: an alias for `Reg`"] +pub type DATA = crate::Reg; +#[doc = "Output Data"] +pub mod data; diff --git a/pac/atsaml22j/src/trng/ctrla.rs b/pac/atsaml22j/src/trng/ctrla.rs new file mode 100644 index 000000000000..4c6dd21da716 --- /dev/null +++ b/pac/atsaml22j/src/trng/ctrla.rs @@ -0,0 +1,95 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - Enable"] +pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLA_SPEC, bool, O>; +#[doc = "Field `RUNSTDBY` reader - Run in Standby"] +pub type RUNSTDBY_R = crate::BitReader; +#[doc = "Field `RUNSTDBY` writer - Run in Standby"] +pub type RUNSTDBY_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLA_SPEC, bool, O>; +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 6) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W<1> { + ENABLE_W::new(self) + } + #[doc = "Bit 6 - Run in Standby"] + #[inline(always)] + #[must_use] + pub fn runstdby(&mut self) -> RUNSTDBY_W<6> { + RUNSTDBY_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/trng/data.rs b/pac/atsaml22j/src/trng/data.rs new file mode 100644 index 000000000000..713e05b598a7 --- /dev/null +++ b/pac/atsaml22j/src/trng/data.rs @@ -0,0 +1,37 @@ +#[doc = "Register `DATA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `DATA` reader - Output Data"] +pub type DATA_R = crate::FieldReader; +impl R { + #[doc = "Bits 0:31 - Output Data"] + #[inline(always)] + pub fn data(&self) -> DATA_R { + DATA_R::new(self.bits) + } +} +#[doc = "Output Data\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [data](index.html) module"] +pub struct DATA_SPEC; +impl crate::RegisterSpec for DATA_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [data::R](R) reader structure"] +impl crate::Readable for DATA_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets DATA to value 0"] +impl crate::Resettable for DATA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/trng/evctrl.rs b/pac/atsaml22j/src/trng/evctrl.rs new file mode 100644 index 000000000000..0980c7c53ca5 --- /dev/null +++ b/pac/atsaml22j/src/trng/evctrl.rs @@ -0,0 +1,80 @@ +#[doc = "Register `EVCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EVCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATARDYEO` reader - Data Ready Event Output"] +pub type DATARDYEO_R = crate::BitReader; +#[doc = "Field `DATARDYEO` writer - Data Ready Event Output"] +pub type DATARDYEO_W<'a, const O: u8> = crate::BitWriter<'a, u8, EVCTRL_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Data Ready Event Output"] + #[inline(always)] + pub fn datardyeo(&self) -> DATARDYEO_R { + DATARDYEO_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Ready Event Output"] + #[inline(always)] + #[must_use] + pub fn datardyeo(&mut self) -> DATARDYEO_W<0> { + DATARDYEO_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Event Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [evctrl](index.html) module"] +pub struct EVCTRL_SPEC; +impl crate::RegisterSpec for EVCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [evctrl::R](R) reader structure"] +impl crate::Readable for EVCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [evctrl::W](W) writer structure"] +impl crate::Writable for EVCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EVCTRL to value 0"] +impl crate::Resettable for EVCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/trng/intenclr.rs b/pac/atsaml22j/src/trng/intenclr.rs new file mode 100644 index 000000000000..72dddcd8af70 --- /dev/null +++ b/pac/atsaml22j/src/trng/intenclr.rs @@ -0,0 +1,80 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATARDY` reader - Data Ready Interrupt Enable"] +pub type DATARDY_R = crate::BitReader; +#[doc = "Field `DATARDY` writer - Data Ready Interrupt Enable"] +pub type DATARDY_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Data Ready Interrupt Enable"] + #[inline(always)] + pub fn datardy(&self) -> DATARDY_R { + DATARDY_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Ready Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn datardy(&mut self) -> DATARDY_W<0> { + DATARDY_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/trng/intenset.rs b/pac/atsaml22j/src/trng/intenset.rs new file mode 100644 index 000000000000..f44df463e65b --- /dev/null +++ b/pac/atsaml22j/src/trng/intenset.rs @@ -0,0 +1,80 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATARDY` reader - Data Ready Interrupt Enable"] +pub type DATARDY_R = crate::BitReader; +#[doc = "Field `DATARDY` writer - Data Ready Interrupt Enable"] +pub type DATARDY_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENSET_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Data Ready Interrupt Enable"] + #[inline(always)] + pub fn datardy(&self) -> DATARDY_R { + DATARDY_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Ready Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn datardy(&mut self) -> DATARDY_W<0> { + DATARDY_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/trng/intflag.rs b/pac/atsaml22j/src/trng/intflag.rs new file mode 100644 index 000000000000..3333f0e93670 --- /dev/null +++ b/pac/atsaml22j/src/trng/intflag.rs @@ -0,0 +1,80 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DATARDY` reader - Data Ready Interrupt Flag"] +pub type DATARDY_R = crate::BitReader; +#[doc = "Field `DATARDY` writer - Data Ready Interrupt Flag"] +pub type DATARDY_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTFLAG_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Data Ready Interrupt Flag"] + #[inline(always)] + pub fn datardy(&self) -> DATARDY_R { + DATARDY_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Data Ready Interrupt Flag"] + #[inline(always)] + #[must_use] + pub fn datardy(&mut self) -> DATARDY_W<0> { + DATARDY_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/usb.rs b/pac/atsaml22j/src/usb.rs new file mode 100644 index 000000000000..9cc881db4f03 --- /dev/null +++ b/pac/atsaml22j/src/usb.rs @@ -0,0 +1,11 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00..0x111 - USB is Device"] + pub device: DEVICE, +} +#[doc = "USB is Device"] +pub use self::device::DEVICE; +#[doc = r"Cluster"] +#[doc = "USB is Device"] +pub mod device; diff --git a/pac/atsaml22j/src/usb/device.rs b/pac/atsaml22j/src/usb/device.rs new file mode 100644 index 000000000000..a3cbad0b00a3 --- /dev/null +++ b/pac/atsaml22j/src/usb/device.rs @@ -0,0 +1,253 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct DEVICE { + #[doc = "0x00 - Control A"] + pub ctrla: CTRLA, + _reserved1: [u8; 0x01], + #[doc = "0x02 - Synchronization Busy"] + pub syncbusy: SYNCBUSY, + #[doc = "0x03 - USB Quality Of Service"] + pub qosctrl: QOSCTRL, + _reserved3: [u8; 0x04], + #[doc = "0x08 - DEVICE Control B"] + pub ctrlb: CTRLB, + #[doc = "0x0a - DEVICE Device Address"] + pub dadd: DADD, + _reserved5: [u8; 0x01], + #[doc = "0x0c - DEVICE Status"] + pub status: STATUS, + #[doc = "0x0d - Finite State Machine Status"] + pub fsmstatus: FSMSTATUS, + _reserved7: [u8; 0x02], + #[doc = "0x10 - DEVICE Device Frame Number"] + pub fnum: FNUM, + _reserved8: [u8; 0x02], + #[doc = "0x14 - DEVICE Device Interrupt Enable Clear"] + pub intenclr: INTENCLR, + _reserved9: [u8; 0x02], + #[doc = "0x18 - DEVICE Device Interrupt Enable Set"] + pub intenset: INTENSET, + _reserved10: [u8; 0x02], + #[doc = "0x1c - DEVICE Device Interrupt Flag"] + pub intflag: INTFLAG, + _reserved11: [u8; 0x02], + #[doc = "0x20 - DEVICE End Point Interrupt Summary"] + pub epintsmry: EPINTSMRY, + _reserved12: [u8; 0x02], + #[doc = "0x24 - Descriptor Address"] + pub descadd: DESCADD, + #[doc = "0x28 - USB PAD Calibration"] + pub padcal: PADCAL, + _reserved14: [u8; 0xd6], + #[doc = "0x100 - DEVICE End Point Configuration"] + pub epcfg0: EPCFG, + _reserved15: [u8; 0x03], + #[doc = "0x104 - DEVICE End Point Pipe Status Clear"] + pub epstatusclr0: EPSTATUSCLR, + #[doc = "0x105 - DEVICE End Point Pipe Status Set"] + pub epstatusset0: EPSTATUSSET, + #[doc = "0x106 - DEVICE End Point Pipe Status"] + pub epstatus0: EPSTATUS, + #[doc = "0x107 - DEVICE End Point Interrupt Flag"] + pub epintflag0: EPINTFLAG, + #[doc = "0x108 - DEVICE End Point Interrupt Clear Flag"] + pub epintenclr0: EPINTENCLR, + #[doc = "0x109 - DEVICE End Point Interrupt Set Flag"] + pub epintenset0: EPINTENSET, + _reserved21: [u8; 0x16], + #[doc = "0x120 - DEVICE End Point Configuration"] + pub epcfg1: EPCFG, + _reserved22: [u8; 0x03], + #[doc = "0x124 - DEVICE End Point Pipe Status Clear"] + pub epstatusclr1: EPSTATUSCLR, + #[doc = "0x125 - DEVICE End Point Pipe Status Set"] + pub epstatusset1: EPSTATUSSET, + #[doc = "0x126 - DEVICE End Point Pipe Status"] + pub epstatus1: EPSTATUS, + #[doc = "0x127 - DEVICE End Point Interrupt Flag"] + pub epintflag1: EPINTFLAG, + #[doc = "0x128 - DEVICE End Point Interrupt Clear Flag"] + pub epintenclr1: EPINTENCLR, + #[doc = "0x129 - DEVICE End Point Interrupt Set Flag"] + pub epintenset1: EPINTENSET, + _reserved28: [u8; 0x16], + #[doc = "0x140 - DEVICE End Point Configuration"] + pub epcfg2: EPCFG, + _reserved29: [u8; 0x03], + #[doc = "0x144 - DEVICE End Point Pipe Status Clear"] + pub epstatusclr2: EPSTATUSCLR, + #[doc = "0x145 - DEVICE End Point Pipe Status Set"] + pub epstatusset2: EPSTATUSSET, + #[doc = "0x146 - DEVICE End Point Pipe Status"] + pub epstatus2: EPSTATUS, + #[doc = "0x147 - DEVICE End Point Interrupt Flag"] + pub epintflag2: EPINTFLAG, + #[doc = "0x148 - DEVICE End Point Interrupt Clear Flag"] + pub epintenclr2: EPINTENCLR, + #[doc = "0x149 - DEVICE End Point Interrupt Set Flag"] + pub epintenset2: EPINTENSET, + _reserved35: [u8; 0x16], + #[doc = "0x160 - DEVICE End Point Configuration"] + pub epcfg3: EPCFG, + _reserved36: [u8; 0x03], + #[doc = "0x164 - DEVICE End Point Pipe Status Clear"] + pub epstatusclr3: EPSTATUSCLR, + #[doc = "0x165 - DEVICE End Point Pipe Status Set"] + pub epstatusset3: EPSTATUSSET, + #[doc = "0x166 - DEVICE End Point Pipe Status"] + pub epstatus3: EPSTATUS, + #[doc = "0x167 - DEVICE End Point Interrupt Flag"] + pub epintflag3: EPINTFLAG, + #[doc = "0x168 - DEVICE End Point Interrupt Clear Flag"] + pub epintenclr3: EPINTENCLR, + #[doc = "0x169 - DEVICE End Point Interrupt Set Flag"] + pub epintenset3: EPINTENSET, + _reserved42: [u8; 0x16], + #[doc = "0x180 - DEVICE End Point Configuration"] + pub epcfg4: EPCFG, + _reserved43: [u8; 0x03], + #[doc = "0x184 - DEVICE End Point Pipe Status Clear"] + pub epstatusclr4: EPSTATUSCLR, + #[doc = "0x185 - DEVICE End Point Pipe Status Set"] + pub epstatusset4: EPSTATUSSET, + #[doc = "0x186 - DEVICE End Point Pipe Status"] + pub epstatus4: EPSTATUS, + #[doc = "0x187 - DEVICE End Point Interrupt Flag"] + pub epintflag4: EPINTFLAG, + #[doc = "0x188 - DEVICE End Point Interrupt Clear Flag"] + pub epintenclr4: EPINTENCLR, + #[doc = "0x189 - DEVICE End Point Interrupt Set Flag"] + pub epintenset4: EPINTENSET, + _reserved49: [u8; 0x16], + #[doc = "0x1a0 - DEVICE End Point Configuration"] + pub epcfg5: EPCFG, + _reserved50: [u8; 0x03], + #[doc = "0x1a4 - DEVICE End Point Pipe Status Clear"] + pub epstatusclr5: EPSTATUSCLR, + #[doc = "0x1a5 - DEVICE End Point Pipe Status Set"] + pub epstatusset5: EPSTATUSSET, + #[doc = "0x1a6 - DEVICE End Point Pipe Status"] + pub epstatus5: EPSTATUS, + #[doc = "0x1a7 - DEVICE End Point Interrupt Flag"] + pub epintflag5: EPINTFLAG, + #[doc = "0x1a8 - DEVICE End Point Interrupt Clear Flag"] + pub epintenclr5: EPINTENCLR, + #[doc = "0x1a9 - DEVICE End Point Interrupt Set Flag"] + pub epintenset5: EPINTENSET, + _reserved56: [u8; 0x16], + #[doc = "0x1c0 - DEVICE End Point Configuration"] + pub epcfg6: EPCFG, + _reserved57: [u8; 0x03], + #[doc = "0x1c4 - DEVICE End Point Pipe Status Clear"] + pub epstatusclr6: EPSTATUSCLR, + #[doc = "0x1c5 - DEVICE End Point Pipe Status Set"] + pub epstatusset6: EPSTATUSSET, + #[doc = "0x1c6 - DEVICE End Point Pipe Status"] + pub epstatus6: EPSTATUS, + #[doc = "0x1c7 - DEVICE End Point Interrupt Flag"] + pub epintflag6: EPINTFLAG, + #[doc = "0x1c8 - DEVICE End Point Interrupt Clear Flag"] + pub epintenclr6: EPINTENCLR, + #[doc = "0x1c9 - DEVICE End Point Interrupt Set Flag"] + pub epintenset6: EPINTENSET, + _reserved63: [u8; 0x16], + #[doc = "0x1e0 - DEVICE End Point Configuration"] + pub epcfg7: EPCFG, + _reserved64: [u8; 0x03], + #[doc = "0x1e4 - DEVICE End Point Pipe Status Clear"] + pub epstatusclr7: EPSTATUSCLR, + #[doc = "0x1e5 - DEVICE End Point Pipe Status Set"] + pub epstatusset7: EPSTATUSSET, + #[doc = "0x1e6 - DEVICE End Point Pipe Status"] + pub epstatus7: EPSTATUS, + #[doc = "0x1e7 - DEVICE End Point Interrupt Flag"] + pub epintflag7: EPINTFLAG, + #[doc = "0x1e8 - DEVICE End Point Interrupt Clear Flag"] + pub epintenclr7: EPINTENCLR, + #[doc = "0x1e9 - DEVICE End Point Interrupt Set Flag"] + pub epintenset7: EPINTENSET, +} +#[doc = "CTRLA (rw) register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control A"] +pub mod ctrla; +#[doc = "SYNCBUSY (r) register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; +#[doc = "QOSCTRL (rw) register accessor: an alias for `Reg`"] +pub type QOSCTRL = crate::Reg; +#[doc = "USB Quality Of Service"] +pub mod qosctrl; +#[doc = "CTRLB (rw) register accessor: an alias for `Reg`"] +pub type CTRLB = crate::Reg; +#[doc = "DEVICE Control B"] +pub mod ctrlb; +#[doc = "DADD (rw) register accessor: an alias for `Reg`"] +pub type DADD = crate::Reg; +#[doc = "DEVICE Device Address"] +pub mod dadd; +#[doc = "STATUS (r) register accessor: an alias for `Reg`"] +pub type STATUS = crate::Reg; +#[doc = "DEVICE Status"] +pub mod status; +#[doc = "FSMSTATUS (r) register accessor: an alias for `Reg`"] +pub type FSMSTATUS = crate::Reg; +#[doc = "Finite State Machine Status"] +pub mod fsmstatus; +#[doc = "FNUM (r) register accessor: an alias for `Reg`"] +pub type FNUM = crate::Reg; +#[doc = "DEVICE Device Frame Number"] +pub mod fnum; +#[doc = "INTENCLR (rw) register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "DEVICE Device Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET (rw) register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "DEVICE Device Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG (rw) register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "DEVICE Device Interrupt Flag"] +pub mod intflag; +#[doc = "EPINTSMRY (r) register accessor: an alias for `Reg`"] +pub type EPINTSMRY = crate::Reg; +#[doc = "DEVICE End Point Interrupt Summary"] +pub mod epintsmry; +#[doc = "DESCADD (rw) register accessor: an alias for `Reg`"] +pub type DESCADD = crate::Reg; +#[doc = "Descriptor Address"] +pub mod descadd; +#[doc = "PADCAL (rw) register accessor: an alias for `Reg`"] +pub type PADCAL = crate::Reg; +#[doc = "USB PAD Calibration"] +pub mod padcal; +#[doc = "EPCFG (rw) register accessor: an alias for `Reg`"] +pub type EPCFG = crate::Reg; +#[doc = "DEVICE End Point Configuration"] +pub mod epcfg; +#[doc = "EPSTATUSCLR (w) register accessor: an alias for `Reg`"] +pub type EPSTATUSCLR = crate::Reg; +#[doc = "DEVICE End Point Pipe Status Clear"] +pub mod epstatusclr; +#[doc = "EPSTATUSSET (w) register accessor: an alias for `Reg`"] +pub type EPSTATUSSET = crate::Reg; +#[doc = "DEVICE End Point Pipe Status Set"] +pub mod epstatusset; +#[doc = "EPSTATUS (r) register accessor: an alias for `Reg`"] +pub type EPSTATUS = crate::Reg; +#[doc = "DEVICE End Point Pipe Status"] +pub mod epstatus; +#[doc = "EPINTFLAG (rw) register accessor: an alias for `Reg`"] +pub type EPINTFLAG = crate::Reg; +#[doc = "DEVICE End Point Interrupt Flag"] +pub mod epintflag; +#[doc = "EPINTENCLR (rw) register accessor: an alias for `Reg`"] +pub type EPINTENCLR = crate::Reg; +#[doc = "DEVICE End Point Interrupt Clear Flag"] +pub mod epintenclr; +#[doc = "EPINTENSET (rw) register accessor: an alias for `Reg`"] +pub type EPINTENSET = crate::Reg; +#[doc = "DEVICE End Point Interrupt Set Flag"] +pub mod epintenset; diff --git a/pac/atsaml22j/src/usb/device/ctrla.rs b/pac/atsaml22j/src/usb/device/ctrla.rs new file mode 100644 index 000000000000..5077062a8c54 --- /dev/null +++ b/pac/atsaml22j/src/usb/device/ctrla.rs @@ -0,0 +1,159 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SWRST` reader - Software Reset"] +pub type SWRST_R = crate::BitReader; +#[doc = "Field `SWRST` writer - Software Reset"] +pub type SWRST_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLA_SPEC, bool, O>; +#[doc = "Field `ENABLE` reader - Enable"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - Enable"] +pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLA_SPEC, bool, O>; +#[doc = "Field `RUNSTDBY` reader - Run in Standby Mode"] +pub type RUNSTDBY_R = crate::BitReader; +#[doc = "Field `RUNSTDBY` writer - Run in Standby Mode"] +pub type RUNSTDBY_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLA_SPEC, bool, O>; +#[doc = "Field `MODE` reader - Operating Mode"] +pub type MODE_R = crate::BitReader; +#[doc = "Operating Mode\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +pub enum MODESELECT_A { + #[doc = "0: Device Mode"] + DEVICE = 0, +} +impl From for bool { + #[inline(always)] + fn from(variant: MODESELECT_A) -> Self { + variant as u8 != 0 + } +} +impl MODE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + false => Some(MODESELECT_A::DEVICE), + _ => None, + } + } + #[doc = "Checks if the value of the field is `DEVICE`"] + #[inline(always)] + pub fn is_device(&self) -> bool { + *self == MODESELECT_A::DEVICE + } +} +#[doc = "Field `MODE` writer - Operating Mode"] +pub type MODE_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLA_SPEC, MODESELECT_A, O>; +impl<'a, const O: u8> MODE_W<'a, O> { + #[doc = "Device Mode"] + #[inline(always)] + pub fn device(self) -> &'a mut W { + self.variant(MODESELECT_A::DEVICE) + } +} +impl R { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Run in Standby Mode"] + #[inline(always)] + pub fn runstdby(&self) -> RUNSTDBY_R { + RUNSTDBY_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 7 - Operating Mode"] + #[inline(always)] + pub fn mode(&self) -> MODE_R { + MODE_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Software Reset"] + #[inline(always)] + #[must_use] + pub fn swrst(&mut self) -> SWRST_W<0> { + SWRST_W::new(self) + } + #[doc = "Bit 1 - Enable"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W<1> { + ENABLE_W::new(self) + } + #[doc = "Bit 2 - Run in Standby Mode"] + #[inline(always)] + #[must_use] + pub fn runstdby(&mut self) -> RUNSTDBY_W<2> { + RUNSTDBY_W::new(self) + } + #[doc = "Bit 7 - Operating Mode"] + #[inline(always)] + #[must_use] + pub fn mode(&mut self) -> MODE_W<7> { + MODE_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/usb/device/ctrlb.rs b/pac/atsaml22j/src/usb/device/ctrlb.rs new file mode 100644 index 000000000000..f899a4f6162d --- /dev/null +++ b/pac/atsaml22j/src/usb/device/ctrlb.rs @@ -0,0 +1,365 @@ +#[doc = "Register `CTRLB` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLB` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DETACH` reader - Detach"] +pub type DETACH_R = crate::BitReader; +#[doc = "Field `DETACH` writer - Detach"] +pub type DETACH_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRLB_SPEC, bool, O>; +#[doc = "Field `UPRSM` reader - Upstream Resume"] +pub type UPRSM_R = crate::BitReader; +#[doc = "Field `UPRSM` writer - Upstream Resume"] +pub type UPRSM_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRLB_SPEC, bool, O>; +#[doc = "Field `SPDCONF` reader - Speed Configuration"] +pub type SPDCONF_R = crate::FieldReader; +#[doc = "Speed Configuration\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SPDCONFSELECT_A { + #[doc = "0: FS : Full Speed"] + FS = 0, + #[doc = "1: LS : Low Speed"] + LS = 1, + #[doc = "2: HS : High Speed capable"] + HS = 2, + #[doc = "3: HSTM: High Speed Test Mode (force high-speed mode for test mode)"] + HSTM = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SPDCONFSELECT_A) -> Self { + variant as _ + } +} +impl SPDCONF_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> SPDCONFSELECT_A { + match self.bits { + 0 => SPDCONFSELECT_A::FS, + 1 => SPDCONFSELECT_A::LS, + 2 => SPDCONFSELECT_A::HS, + 3 => SPDCONFSELECT_A::HSTM, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `FS`"] + #[inline(always)] + pub fn is_fs(&self) -> bool { + *self == SPDCONFSELECT_A::FS + } + #[doc = "Checks if the value of the field is `LS`"] + #[inline(always)] + pub fn is_ls(&self) -> bool { + *self == SPDCONFSELECT_A::LS + } + #[doc = "Checks if the value of the field is `HS`"] + #[inline(always)] + pub fn is_hs(&self) -> bool { + *self == SPDCONFSELECT_A::HS + } + #[doc = "Checks if the value of the field is `HSTM`"] + #[inline(always)] + pub fn is_hstm(&self) -> bool { + *self == SPDCONFSELECT_A::HSTM + } +} +#[doc = "Field `SPDCONF` writer - Speed Configuration"] +pub type SPDCONF_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u16, CTRLB_SPEC, u8, SPDCONFSELECT_A, 2, O>; +impl<'a, const O: u8> SPDCONF_W<'a, O> { + #[doc = "FS : Full Speed"] + #[inline(always)] + pub fn fs(self) -> &'a mut W { + self.variant(SPDCONFSELECT_A::FS) + } + #[doc = "LS : Low Speed"] + #[inline(always)] + pub fn ls(self) -> &'a mut W { + self.variant(SPDCONFSELECT_A::LS) + } + #[doc = "HS : High Speed capable"] + #[inline(always)] + pub fn hs(self) -> &'a mut W { + self.variant(SPDCONFSELECT_A::HS) + } + #[doc = "HSTM: High Speed Test Mode (force high-speed mode for test mode)"] + #[inline(always)] + pub fn hstm(self) -> &'a mut W { + self.variant(SPDCONFSELECT_A::HSTM) + } +} +#[doc = "Field `NREPLY` reader - No Reply"] +pub type NREPLY_R = crate::BitReader; +#[doc = "Field `NREPLY` writer - No Reply"] +pub type NREPLY_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRLB_SPEC, bool, O>; +#[doc = "Field `TSTJ` reader - Test mode J"] +pub type TSTJ_R = crate::BitReader; +#[doc = "Field `TSTJ` writer - Test mode J"] +pub type TSTJ_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRLB_SPEC, bool, O>; +#[doc = "Field `TSTK` reader - Test mode K"] +pub type TSTK_R = crate::BitReader; +#[doc = "Field `TSTK` writer - Test mode K"] +pub type TSTK_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRLB_SPEC, bool, O>; +#[doc = "Field `TSTPCKT` reader - Test packet mode"] +pub type TSTPCKT_R = crate::BitReader; +#[doc = "Field `TSTPCKT` writer - Test packet mode"] +pub type TSTPCKT_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRLB_SPEC, bool, O>; +#[doc = "Field `OPMODE2` reader - Specific Operational Mode"] +pub type OPMODE2_R = crate::BitReader; +#[doc = "Field `OPMODE2` writer - Specific Operational Mode"] +pub type OPMODE2_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRLB_SPEC, bool, O>; +#[doc = "Field `GNAK` reader - Global NAK"] +pub type GNAK_R = crate::BitReader; +#[doc = "Field `GNAK` writer - Global NAK"] +pub type GNAK_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRLB_SPEC, bool, O>; +#[doc = "Field `LPMHDSK` reader - Link Power Management Handshake"] +pub type LPMHDSK_R = crate::FieldReader; +#[doc = "Link Power Management Handshake\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LPMHDSKSELECT_A { + #[doc = "0: No handshake. LPM is not supported"] + NO = 0, + #[doc = "1: ACK"] + ACK = 1, + #[doc = "2: NYET"] + NYET = 2, + #[doc = "3: STALL"] + STALL = 3, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LPMHDSKSELECT_A) -> Self { + variant as _ + } +} +impl LPMHDSK_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> LPMHDSKSELECT_A { + match self.bits { + 0 => LPMHDSKSELECT_A::NO, + 1 => LPMHDSKSELECT_A::ACK, + 2 => LPMHDSKSELECT_A::NYET, + 3 => LPMHDSKSELECT_A::STALL, + _ => unreachable!(), + } + } + #[doc = "Checks if the value of the field is `NO`"] + #[inline(always)] + pub fn is_no(&self) -> bool { + *self == LPMHDSKSELECT_A::NO + } + #[doc = "Checks if the value of the field is `ACK`"] + #[inline(always)] + pub fn is_ack(&self) -> bool { + *self == LPMHDSKSELECT_A::ACK + } + #[doc = "Checks if the value of the field is `NYET`"] + #[inline(always)] + pub fn is_nyet(&self) -> bool { + *self == LPMHDSKSELECT_A::NYET + } + #[doc = "Checks if the value of the field is `STALL`"] + #[inline(always)] + pub fn is_stall(&self) -> bool { + *self == LPMHDSKSELECT_A::STALL + } +} +#[doc = "Field `LPMHDSK` writer - Link Power Management Handshake"] +pub type LPMHDSK_W<'a, const O: u8> = + crate::FieldWriterSafe<'a, u16, CTRLB_SPEC, u8, LPMHDSKSELECT_A, 2, O>; +impl<'a, const O: u8> LPMHDSK_W<'a, O> { + #[doc = "No handshake. LPM is not supported"] + #[inline(always)] + pub fn no(self) -> &'a mut W { + self.variant(LPMHDSKSELECT_A::NO) + } + #[doc = "ACK"] + #[inline(always)] + pub fn ack(self) -> &'a mut W { + self.variant(LPMHDSKSELECT_A::ACK) + } + #[doc = "NYET"] + #[inline(always)] + pub fn nyet(self) -> &'a mut W { + self.variant(LPMHDSKSELECT_A::NYET) + } + #[doc = "STALL"] + #[inline(always)] + pub fn stall(self) -> &'a mut W { + self.variant(LPMHDSKSELECT_A::STALL) + } +} +impl R { + #[doc = "Bit 0 - Detach"] + #[inline(always)] + pub fn detach(&self) -> DETACH_R { + DETACH_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Upstream Resume"] + #[inline(always)] + pub fn uprsm(&self) -> UPRSM_R { + UPRSM_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bits 2:3 - Speed Configuration"] + #[inline(always)] + pub fn spdconf(&self) -> SPDCONF_R { + SPDCONF_R::new(((self.bits >> 2) & 3) as u8) + } + #[doc = "Bit 4 - No Reply"] + #[inline(always)] + pub fn nreply(&self) -> NREPLY_R { + NREPLY_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Test mode J"] + #[inline(always)] + pub fn tstj(&self) -> TSTJ_R { + TSTJ_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Test mode K"] + #[inline(always)] + pub fn tstk(&self) -> TSTK_R { + TSTK_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Test packet mode"] + #[inline(always)] + pub fn tstpckt(&self) -> TSTPCKT_R { + TSTPCKT_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Specific Operational Mode"] + #[inline(always)] + pub fn opmode2(&self) -> OPMODE2_R { + OPMODE2_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Global NAK"] + #[inline(always)] + pub fn gnak(&self) -> GNAK_R { + GNAK_R::new(((self.bits >> 9) & 1) != 0) + } + #[doc = "Bits 10:11 - Link Power Management Handshake"] + #[inline(always)] + pub fn lpmhdsk(&self) -> LPMHDSK_R { + LPMHDSK_R::new(((self.bits >> 10) & 3) as u8) + } +} +impl W { + #[doc = "Bit 0 - Detach"] + #[inline(always)] + #[must_use] + pub fn detach(&mut self) -> DETACH_W<0> { + DETACH_W::new(self) + } + #[doc = "Bit 1 - Upstream Resume"] + #[inline(always)] + #[must_use] + pub fn uprsm(&mut self) -> UPRSM_W<1> { + UPRSM_W::new(self) + } + #[doc = "Bits 2:3 - Speed Configuration"] + #[inline(always)] + #[must_use] + pub fn spdconf(&mut self) -> SPDCONF_W<2> { + SPDCONF_W::new(self) + } + #[doc = "Bit 4 - No Reply"] + #[inline(always)] + #[must_use] + pub fn nreply(&mut self) -> NREPLY_W<4> { + NREPLY_W::new(self) + } + #[doc = "Bit 5 - Test mode J"] + #[inline(always)] + #[must_use] + pub fn tstj(&mut self) -> TSTJ_W<5> { + TSTJ_W::new(self) + } + #[doc = "Bit 6 - Test mode K"] + #[inline(always)] + #[must_use] + pub fn tstk(&mut self) -> TSTK_W<6> { + TSTK_W::new(self) + } + #[doc = "Bit 7 - Test packet mode"] + #[inline(always)] + #[must_use] + pub fn tstpckt(&mut self) -> TSTPCKT_W<7> { + TSTPCKT_W::new(self) + } + #[doc = "Bit 8 - Specific Operational Mode"] + #[inline(always)] + #[must_use] + pub fn opmode2(&mut self) -> OPMODE2_W<8> { + OPMODE2_W::new(self) + } + #[doc = "Bit 9 - Global NAK"] + #[inline(always)] + #[must_use] + pub fn gnak(&mut self) -> GNAK_W<9> { + GNAK_W::new(self) + } + #[doc = "Bits 10:11 - Link Power Management Handshake"] + #[inline(always)] + #[must_use] + pub fn lpmhdsk(&mut self) -> LPMHDSK_W<10> { + LPMHDSK_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DEVICE Control B\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrlb](index.html) module"] +pub struct CTRLB_SPEC; +impl crate::RegisterSpec for CTRLB_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [ctrlb::R](R) reader structure"] +impl crate::Readable for CTRLB_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrlb::W](W) writer structure"] +impl crate::Writable for CTRLB_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRLB to value 0x01"] +impl crate::Resettable for CTRLB_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/pac/atsaml22j/src/usb/device/dadd.rs b/pac/atsaml22j/src/usb/device/dadd.rs new file mode 100644 index 000000000000..fd0ddf884cbb --- /dev/null +++ b/pac/atsaml22j/src/usb/device/dadd.rs @@ -0,0 +1,95 @@ +#[doc = "Register `DADD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DADD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DADD` reader - Device Address"] +pub type DADD_R = crate::FieldReader; +#[doc = "Field `DADD` writer - Device Address"] +pub type DADD_W<'a, const O: u8> = crate::FieldWriter<'a, u8, DADD_SPEC, u8, u8, 7, O>; +#[doc = "Field `ADDEN` reader - Device Address Enable"] +pub type ADDEN_R = crate::BitReader; +#[doc = "Field `ADDEN` writer - Device Address Enable"] +pub type ADDEN_W<'a, const O: u8> = crate::BitWriter<'a, u8, DADD_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:6 - Device Address"] + #[inline(always)] + pub fn dadd(&self) -> DADD_R { + DADD_R::new(self.bits & 0x7f) + } + #[doc = "Bit 7 - Device Address Enable"] + #[inline(always)] + pub fn adden(&self) -> ADDEN_R { + ADDEN_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:6 - Device Address"] + #[inline(always)] + #[must_use] + pub fn dadd(&mut self) -> DADD_W<0> { + DADD_W::new(self) + } + #[doc = "Bit 7 - Device Address Enable"] + #[inline(always)] + #[must_use] + pub fn adden(&mut self) -> ADDEN_W<7> { + ADDEN_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DEVICE Device Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dadd](index.html) module"] +pub struct DADD_SPEC; +impl crate::RegisterSpec for DADD_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [dadd::R](R) reader structure"] +impl crate::Readable for DADD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [dadd::W](W) writer structure"] +impl crate::Writable for DADD_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DADD to value 0"] +impl crate::Resettable for DADD_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/usb/device/descadd.rs b/pac/atsaml22j/src/usb/device/descadd.rs new file mode 100644 index 000000000000..e78eca076260 --- /dev/null +++ b/pac/atsaml22j/src/usb/device/descadd.rs @@ -0,0 +1,80 @@ +#[doc = "Register `DESCADD` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `DESCADD` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DESCADD` reader - Descriptor Address Value"] +pub type DESCADD_R = crate::FieldReader; +#[doc = "Field `DESCADD` writer - Descriptor Address Value"] +pub type DESCADD_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DESCADD_SPEC, u32, u32, 32, O>; +impl R { + #[doc = "Bits 0:31 - Descriptor Address Value"] + #[inline(always)] + pub fn descadd(&self) -> DESCADD_R { + DESCADD_R::new(self.bits) + } +} +impl W { + #[doc = "Bits 0:31 - Descriptor Address Value"] + #[inline(always)] + #[must_use] + pub fn descadd(&mut self) -> DESCADD_W<0> { + DESCADD_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Descriptor Address\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [descadd](index.html) module"] +pub struct DESCADD_SPEC; +impl crate::RegisterSpec for DESCADD_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [descadd::R](R) reader structure"] +impl crate::Readable for DESCADD_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [descadd::W](W) writer structure"] +impl crate::Writable for DESCADD_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets DESCADD to value 0"] +impl crate::Resettable for DESCADD_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/usb/device/epcfg.rs b/pac/atsaml22j/src/usb/device/epcfg.rs new file mode 100644 index 000000000000..881da9d466f7 --- /dev/null +++ b/pac/atsaml22j/src/usb/device/epcfg.rs @@ -0,0 +1,110 @@ +#[doc = "Register `EPCFG%s` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EPCFG%s` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EPTYPE0` reader - End Point Type0"] +pub type EPTYPE0_R = crate::FieldReader; +#[doc = "Field `EPTYPE0` writer - End Point Type0"] +pub type EPTYPE0_W<'a, const O: u8> = crate::FieldWriter<'a, u8, EPCFG_SPEC, u8, u8, 3, O>; +#[doc = "Field `EPTYPE1` reader - End Point Type1"] +pub type EPTYPE1_R = crate::FieldReader; +#[doc = "Field `EPTYPE1` writer - End Point Type1"] +pub type EPTYPE1_W<'a, const O: u8> = crate::FieldWriter<'a, u8, EPCFG_SPEC, u8, u8, 3, O>; +#[doc = "Field `NYETDIS` reader - NYET Token Disable"] +pub type NYETDIS_R = crate::BitReader; +#[doc = "Field `NYETDIS` writer - NYET Token Disable"] +pub type NYETDIS_W<'a, const O: u8> = crate::BitWriter<'a, u8, EPCFG_SPEC, bool, O>; +impl R { + #[doc = "Bits 0:2 - End Point Type0"] + #[inline(always)] + pub fn eptype0(&self) -> EPTYPE0_R { + EPTYPE0_R::new(self.bits & 7) + } + #[doc = "Bits 4:6 - End Point Type1"] + #[inline(always)] + pub fn eptype1(&self) -> EPTYPE1_R { + EPTYPE1_R::new((self.bits >> 4) & 7) + } + #[doc = "Bit 7 - NYET Token Disable"] + #[inline(always)] + pub fn nyetdis(&self) -> NYETDIS_R { + NYETDIS_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bits 0:2 - End Point Type0"] + #[inline(always)] + #[must_use] + pub fn eptype0(&mut self) -> EPTYPE0_W<0> { + EPTYPE0_W::new(self) + } + #[doc = "Bits 4:6 - End Point Type1"] + #[inline(always)] + #[must_use] + pub fn eptype1(&mut self) -> EPTYPE1_W<4> { + EPTYPE1_W::new(self) + } + #[doc = "Bit 7 - NYET Token Disable"] + #[inline(always)] + #[must_use] + pub fn nyetdis(&mut self) -> NYETDIS_W<7> { + NYETDIS_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DEVICE End Point Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [epcfg](index.html) module"] +pub struct EPCFG_SPEC; +impl crate::RegisterSpec for EPCFG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [epcfg::R](R) reader structure"] +impl crate::Readable for EPCFG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [epcfg::W](W) writer structure"] +impl crate::Writable for EPCFG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EPCFG%s to value 0"] +impl crate::Resettable for EPCFG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/usb/device/epintenclr.rs b/pac/atsaml22j/src/usb/device/epintenclr.rs new file mode 100644 index 000000000000..112b3d133eb0 --- /dev/null +++ b/pac/atsaml22j/src/usb/device/epintenclr.rs @@ -0,0 +1,170 @@ +#[doc = "Register `EPINTENCLR%s` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EPINTENCLR%s` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TRCPT0` reader - Transfer Complete 0 Interrupt Disable"] +pub type TRCPT0_R = crate::BitReader; +#[doc = "Field `TRCPT0` writer - Transfer Complete 0 Interrupt Disable"] +pub type TRCPT0_W<'a, const O: u8> = crate::BitWriter<'a, u8, EPINTENCLR_SPEC, bool, O>; +#[doc = "Field `TRCPT1` reader - Transfer Complete 1 Interrupt Disable"] +pub type TRCPT1_R = crate::BitReader; +#[doc = "Field `TRCPT1` writer - Transfer Complete 1 Interrupt Disable"] +pub type TRCPT1_W<'a, const O: u8> = crate::BitWriter<'a, u8, EPINTENCLR_SPEC, bool, O>; +#[doc = "Field `TRFAIL0` reader - Error Flow 0 Interrupt Disable"] +pub type TRFAIL0_R = crate::BitReader; +#[doc = "Field `TRFAIL0` writer - Error Flow 0 Interrupt Disable"] +pub type TRFAIL0_W<'a, const O: u8> = crate::BitWriter<'a, u8, EPINTENCLR_SPEC, bool, O>; +#[doc = "Field `TRFAIL1` reader - Error Flow 1 Interrupt Disable"] +pub type TRFAIL1_R = crate::BitReader; +#[doc = "Field `TRFAIL1` writer - Error Flow 1 Interrupt Disable"] +pub type TRFAIL1_W<'a, const O: u8> = crate::BitWriter<'a, u8, EPINTENCLR_SPEC, bool, O>; +#[doc = "Field `RXSTP` reader - Received Setup Interrupt Disable"] +pub type RXSTP_R = crate::BitReader; +#[doc = "Field `RXSTP` writer - Received Setup Interrupt Disable"] +pub type RXSTP_W<'a, const O: u8> = crate::BitWriter<'a, u8, EPINTENCLR_SPEC, bool, O>; +#[doc = "Field `STALL0` reader - Stall 0 In/Out Interrupt Disable"] +pub type STALL0_R = crate::BitReader; +#[doc = "Field `STALL0` writer - Stall 0 In/Out Interrupt Disable"] +pub type STALL0_W<'a, const O: u8> = crate::BitWriter<'a, u8, EPINTENCLR_SPEC, bool, O>; +#[doc = "Field `STALL1` reader - Stall 1 In/Out Interrupt Disable"] +pub type STALL1_R = crate::BitReader; +#[doc = "Field `STALL1` writer - Stall 1 In/Out Interrupt Disable"] +pub type STALL1_W<'a, const O: u8> = crate::BitWriter<'a, u8, EPINTENCLR_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Transfer Complete 0 Interrupt Disable"] + #[inline(always)] + pub fn trcpt0(&self) -> TRCPT0_R { + TRCPT0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transfer Complete 1 Interrupt Disable"] + #[inline(always)] + pub fn trcpt1(&self) -> TRCPT1_R { + TRCPT1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Error Flow 0 Interrupt Disable"] + #[inline(always)] + pub fn trfail0(&self) -> TRFAIL0_R { + TRFAIL0_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Error Flow 1 Interrupt Disable"] + #[inline(always)] + pub fn trfail1(&self) -> TRFAIL1_R { + TRFAIL1_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Received Setup Interrupt Disable"] + #[inline(always)] + pub fn rxstp(&self) -> RXSTP_R { + RXSTP_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Stall 0 In/Out Interrupt Disable"] + #[inline(always)] + pub fn stall0(&self) -> STALL0_R { + STALL0_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Stall 1 In/Out Interrupt Disable"] + #[inline(always)] + pub fn stall1(&self) -> STALL1_R { + STALL1_R::new(((self.bits >> 6) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transfer Complete 0 Interrupt Disable"] + #[inline(always)] + #[must_use] + pub fn trcpt0(&mut self) -> TRCPT0_W<0> { + TRCPT0_W::new(self) + } + #[doc = "Bit 1 - Transfer Complete 1 Interrupt Disable"] + #[inline(always)] + #[must_use] + pub fn trcpt1(&mut self) -> TRCPT1_W<1> { + TRCPT1_W::new(self) + } + #[doc = "Bit 2 - Error Flow 0 Interrupt Disable"] + #[inline(always)] + #[must_use] + pub fn trfail0(&mut self) -> TRFAIL0_W<2> { + TRFAIL0_W::new(self) + } + #[doc = "Bit 3 - Error Flow 1 Interrupt Disable"] + #[inline(always)] + #[must_use] + pub fn trfail1(&mut self) -> TRFAIL1_W<3> { + TRFAIL1_W::new(self) + } + #[doc = "Bit 4 - Received Setup Interrupt Disable"] + #[inline(always)] + #[must_use] + pub fn rxstp(&mut self) -> RXSTP_W<4> { + RXSTP_W::new(self) + } + #[doc = "Bit 5 - Stall 0 In/Out Interrupt Disable"] + #[inline(always)] + #[must_use] + pub fn stall0(&mut self) -> STALL0_W<5> { + STALL0_W::new(self) + } + #[doc = "Bit 6 - Stall 1 In/Out Interrupt Disable"] + #[inline(always)] + #[must_use] + pub fn stall1(&mut self) -> STALL1_W<6> { + STALL1_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DEVICE End Point Interrupt Clear Flag\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [epintenclr](index.html) module"] +pub struct EPINTENCLR_SPEC; +impl crate::RegisterSpec for EPINTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [epintenclr::R](R) reader structure"] +impl crate::Readable for EPINTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [epintenclr::W](W) writer structure"] +impl crate::Writable for EPINTENCLR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EPINTENCLR%s to value 0"] +impl crate::Resettable for EPINTENCLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/usb/device/epintenset.rs b/pac/atsaml22j/src/usb/device/epintenset.rs new file mode 100644 index 000000000000..220b17c24629 --- /dev/null +++ b/pac/atsaml22j/src/usb/device/epintenset.rs @@ -0,0 +1,170 @@ +#[doc = "Register `EPINTENSET%s` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EPINTENSET%s` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TRCPT0` reader - Transfer Complete 0 Interrupt Enable"] +pub type TRCPT0_R = crate::BitReader; +#[doc = "Field `TRCPT0` writer - Transfer Complete 0 Interrupt Enable"] +pub type TRCPT0_W<'a, const O: u8> = crate::BitWriter<'a, u8, EPINTENSET_SPEC, bool, O>; +#[doc = "Field `TRCPT1` reader - Transfer Complete 1 Interrupt Enable"] +pub type TRCPT1_R = crate::BitReader; +#[doc = "Field `TRCPT1` writer - Transfer Complete 1 Interrupt Enable"] +pub type TRCPT1_W<'a, const O: u8> = crate::BitWriter<'a, u8, EPINTENSET_SPEC, bool, O>; +#[doc = "Field `TRFAIL0` reader - Error Flow 0 Interrupt Enable"] +pub type TRFAIL0_R = crate::BitReader; +#[doc = "Field `TRFAIL0` writer - Error Flow 0 Interrupt Enable"] +pub type TRFAIL0_W<'a, const O: u8> = crate::BitWriter<'a, u8, EPINTENSET_SPEC, bool, O>; +#[doc = "Field `TRFAIL1` reader - Error Flow 1 Interrupt Enable"] +pub type TRFAIL1_R = crate::BitReader; +#[doc = "Field `TRFAIL1` writer - Error Flow 1 Interrupt Enable"] +pub type TRFAIL1_W<'a, const O: u8> = crate::BitWriter<'a, u8, EPINTENSET_SPEC, bool, O>; +#[doc = "Field `RXSTP` reader - Received Setup Interrupt Enable"] +pub type RXSTP_R = crate::BitReader; +#[doc = "Field `RXSTP` writer - Received Setup Interrupt Enable"] +pub type RXSTP_W<'a, const O: u8> = crate::BitWriter<'a, u8, EPINTENSET_SPEC, bool, O>; +#[doc = "Field `STALL0` reader - Stall 0 In/out Interrupt enable"] +pub type STALL0_R = crate::BitReader; +#[doc = "Field `STALL0` writer - Stall 0 In/out Interrupt enable"] +pub type STALL0_W<'a, const O: u8> = crate::BitWriter<'a, u8, EPINTENSET_SPEC, bool, O>; +#[doc = "Field `STALL1` reader - Stall 1 In/out Interrupt enable"] +pub type STALL1_R = crate::BitReader; +#[doc = "Field `STALL1` writer - Stall 1 In/out Interrupt enable"] +pub type STALL1_W<'a, const O: u8> = crate::BitWriter<'a, u8, EPINTENSET_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Transfer Complete 0 Interrupt Enable"] + #[inline(always)] + pub fn trcpt0(&self) -> TRCPT0_R { + TRCPT0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transfer Complete 1 Interrupt Enable"] + #[inline(always)] + pub fn trcpt1(&self) -> TRCPT1_R { + TRCPT1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Error Flow 0 Interrupt Enable"] + #[inline(always)] + pub fn trfail0(&self) -> TRFAIL0_R { + TRFAIL0_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Error Flow 1 Interrupt Enable"] + #[inline(always)] + pub fn trfail1(&self) -> TRFAIL1_R { + TRFAIL1_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Received Setup Interrupt Enable"] + #[inline(always)] + pub fn rxstp(&self) -> RXSTP_R { + RXSTP_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Stall 0 In/out Interrupt enable"] + #[inline(always)] + pub fn stall0(&self) -> STALL0_R { + STALL0_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Stall 1 In/out Interrupt enable"] + #[inline(always)] + pub fn stall1(&self) -> STALL1_R { + STALL1_R::new(((self.bits >> 6) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transfer Complete 0 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn trcpt0(&mut self) -> TRCPT0_W<0> { + TRCPT0_W::new(self) + } + #[doc = "Bit 1 - Transfer Complete 1 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn trcpt1(&mut self) -> TRCPT1_W<1> { + TRCPT1_W::new(self) + } + #[doc = "Bit 2 - Error Flow 0 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn trfail0(&mut self) -> TRFAIL0_W<2> { + TRFAIL0_W::new(self) + } + #[doc = "Bit 3 - Error Flow 1 Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn trfail1(&mut self) -> TRFAIL1_W<3> { + TRFAIL1_W::new(self) + } + #[doc = "Bit 4 - Received Setup Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn rxstp(&mut self) -> RXSTP_W<4> { + RXSTP_W::new(self) + } + #[doc = "Bit 5 - Stall 0 In/out Interrupt enable"] + #[inline(always)] + #[must_use] + pub fn stall0(&mut self) -> STALL0_W<5> { + STALL0_W::new(self) + } + #[doc = "Bit 6 - Stall 1 In/out Interrupt enable"] + #[inline(always)] + #[must_use] + pub fn stall1(&mut self) -> STALL1_W<6> { + STALL1_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DEVICE End Point Interrupt Set Flag\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [epintenset](index.html) module"] +pub struct EPINTENSET_SPEC; +impl crate::RegisterSpec for EPINTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [epintenset::R](R) reader structure"] +impl crate::Readable for EPINTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [epintenset::W](W) writer structure"] +impl crate::Writable for EPINTENSET_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EPINTENSET%s to value 0"] +impl crate::Resettable for EPINTENSET_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/usb/device/epintflag.rs b/pac/atsaml22j/src/usb/device/epintflag.rs new file mode 100644 index 000000000000..7c87c5694dbd --- /dev/null +++ b/pac/atsaml22j/src/usb/device/epintflag.rs @@ -0,0 +1,170 @@ +#[doc = "Register `EPINTFLAG%s` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EPINTFLAG%s` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TRCPT0` reader - Transfer Complete 0"] +pub type TRCPT0_R = crate::BitReader; +#[doc = "Field `TRCPT0` writer - Transfer Complete 0"] +pub type TRCPT0_W<'a, const O: u8> = crate::BitWriter<'a, u8, EPINTFLAG_SPEC, bool, O>; +#[doc = "Field `TRCPT1` reader - Transfer Complete 1"] +pub type TRCPT1_R = crate::BitReader; +#[doc = "Field `TRCPT1` writer - Transfer Complete 1"] +pub type TRCPT1_W<'a, const O: u8> = crate::BitWriter<'a, u8, EPINTFLAG_SPEC, bool, O>; +#[doc = "Field `TRFAIL0` reader - Error Flow 0"] +pub type TRFAIL0_R = crate::BitReader; +#[doc = "Field `TRFAIL0` writer - Error Flow 0"] +pub type TRFAIL0_W<'a, const O: u8> = crate::BitWriter<'a, u8, EPINTFLAG_SPEC, bool, O>; +#[doc = "Field `TRFAIL1` reader - Error Flow 1"] +pub type TRFAIL1_R = crate::BitReader; +#[doc = "Field `TRFAIL1` writer - Error Flow 1"] +pub type TRFAIL1_W<'a, const O: u8> = crate::BitWriter<'a, u8, EPINTFLAG_SPEC, bool, O>; +#[doc = "Field `RXSTP` reader - Received Setup"] +pub type RXSTP_R = crate::BitReader; +#[doc = "Field `RXSTP` writer - Received Setup"] +pub type RXSTP_W<'a, const O: u8> = crate::BitWriter<'a, u8, EPINTFLAG_SPEC, bool, O>; +#[doc = "Field `STALL0` reader - Stall 0 In/out"] +pub type STALL0_R = crate::BitReader; +#[doc = "Field `STALL0` writer - Stall 0 In/out"] +pub type STALL0_W<'a, const O: u8> = crate::BitWriter<'a, u8, EPINTFLAG_SPEC, bool, O>; +#[doc = "Field `STALL1` reader - Stall 1 In/out"] +pub type STALL1_R = crate::BitReader; +#[doc = "Field `STALL1` writer - Stall 1 In/out"] +pub type STALL1_W<'a, const O: u8> = crate::BitWriter<'a, u8, EPINTFLAG_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Transfer Complete 0"] + #[inline(always)] + pub fn trcpt0(&self) -> TRCPT0_R { + TRCPT0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Transfer Complete 1"] + #[inline(always)] + pub fn trcpt1(&self) -> TRCPT1_R { + TRCPT1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Error Flow 0"] + #[inline(always)] + pub fn trfail0(&self) -> TRFAIL0_R { + TRFAIL0_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Error Flow 1"] + #[inline(always)] + pub fn trfail1(&self) -> TRFAIL1_R { + TRFAIL1_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Received Setup"] + #[inline(always)] + pub fn rxstp(&self) -> RXSTP_R { + RXSTP_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Stall 0 In/out"] + #[inline(always)] + pub fn stall0(&self) -> STALL0_R { + STALL0_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Stall 1 In/out"] + #[inline(always)] + pub fn stall1(&self) -> STALL1_R { + STALL1_R::new(((self.bits >> 6) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Transfer Complete 0"] + #[inline(always)] + #[must_use] + pub fn trcpt0(&mut self) -> TRCPT0_W<0> { + TRCPT0_W::new(self) + } + #[doc = "Bit 1 - Transfer Complete 1"] + #[inline(always)] + #[must_use] + pub fn trcpt1(&mut self) -> TRCPT1_W<1> { + TRCPT1_W::new(self) + } + #[doc = "Bit 2 - Error Flow 0"] + #[inline(always)] + #[must_use] + pub fn trfail0(&mut self) -> TRFAIL0_W<2> { + TRFAIL0_W::new(self) + } + #[doc = "Bit 3 - Error Flow 1"] + #[inline(always)] + #[must_use] + pub fn trfail1(&mut self) -> TRFAIL1_W<3> { + TRFAIL1_W::new(self) + } + #[doc = "Bit 4 - Received Setup"] + #[inline(always)] + #[must_use] + pub fn rxstp(&mut self) -> RXSTP_W<4> { + RXSTP_W::new(self) + } + #[doc = "Bit 5 - Stall 0 In/out"] + #[inline(always)] + #[must_use] + pub fn stall0(&mut self) -> STALL0_W<5> { + STALL0_W::new(self) + } + #[doc = "Bit 6 - Stall 1 In/out"] + #[inline(always)] + #[must_use] + pub fn stall1(&mut self) -> STALL1_W<6> { + STALL1_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DEVICE End Point Interrupt Flag\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [epintflag](index.html) module"] +pub struct EPINTFLAG_SPEC; +impl crate::RegisterSpec for EPINTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [epintflag::R](R) reader structure"] +impl crate::Readable for EPINTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [epintflag::W](W) writer structure"] +impl crate::Writable for EPINTFLAG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EPINTFLAG%s to value 0"] +impl crate::Resettable for EPINTFLAG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/usb/device/epintsmry.rs b/pac/atsaml22j/src/usb/device/epintsmry.rs new file mode 100644 index 000000000000..c38ed0e3a72f --- /dev/null +++ b/pac/atsaml22j/src/usb/device/epintsmry.rs @@ -0,0 +1,86 @@ +#[doc = "Register `EPINTSMRY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `EPINT0` reader - End Point 0 Interrupt"] +pub type EPINT0_R = crate::BitReader; +#[doc = "Field `EPINT1` reader - End Point 1 Interrupt"] +pub type EPINT1_R = crate::BitReader; +#[doc = "Field `EPINT2` reader - End Point 2 Interrupt"] +pub type EPINT2_R = crate::BitReader; +#[doc = "Field `EPINT3` reader - End Point 3 Interrupt"] +pub type EPINT3_R = crate::BitReader; +#[doc = "Field `EPINT4` reader - End Point 4 Interrupt"] +pub type EPINT4_R = crate::BitReader; +#[doc = "Field `EPINT5` reader - End Point 5 Interrupt"] +pub type EPINT5_R = crate::BitReader; +#[doc = "Field `EPINT6` reader - End Point 6 Interrupt"] +pub type EPINT6_R = crate::BitReader; +#[doc = "Field `EPINT7` reader - End Point 7 Interrupt"] +pub type EPINT7_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - End Point 0 Interrupt"] + #[inline(always)] + pub fn epint0(&self) -> EPINT0_R { + EPINT0_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - End Point 1 Interrupt"] + #[inline(always)] + pub fn epint1(&self) -> EPINT1_R { + EPINT1_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - End Point 2 Interrupt"] + #[inline(always)] + pub fn epint2(&self) -> EPINT2_R { + EPINT2_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - End Point 3 Interrupt"] + #[inline(always)] + pub fn epint3(&self) -> EPINT3_R { + EPINT3_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - End Point 4 Interrupt"] + #[inline(always)] + pub fn epint4(&self) -> EPINT4_R { + EPINT4_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - End Point 5 Interrupt"] + #[inline(always)] + pub fn epint5(&self) -> EPINT5_R { + EPINT5_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - End Point 6 Interrupt"] + #[inline(always)] + pub fn epint6(&self) -> EPINT6_R { + EPINT6_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - End Point 7 Interrupt"] + #[inline(always)] + pub fn epint7(&self) -> EPINT7_R { + EPINT7_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[doc = "DEVICE End Point Interrupt Summary\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [epintsmry](index.html) module"] +pub struct EPINTSMRY_SPEC; +impl crate::RegisterSpec for EPINTSMRY_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [epintsmry::R](R) reader structure"] +impl crate::Readable for EPINTSMRY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets EPINTSMRY to value 0"] +impl crate::Resettable for EPINTSMRY_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/usb/device/epstatus.rs b/pac/atsaml22j/src/usb/device/epstatus.rs new file mode 100644 index 000000000000..33cd8f9085ce --- /dev/null +++ b/pac/atsaml22j/src/usb/device/epstatus.rs @@ -0,0 +1,79 @@ +#[doc = "Register `EPSTATUS%s` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `DTGLOUT` reader - Data Toggle Out"] +pub type DTGLOUT_R = crate::BitReader; +#[doc = "Field `DTGLIN` reader - Data Toggle In"] +pub type DTGLIN_R = crate::BitReader; +#[doc = "Field `CURBK` reader - Current Bank"] +pub type CURBK_R = crate::BitReader; +#[doc = "Field `STALLRQ0` reader - Stall 0 Request"] +pub type STALLRQ0_R = crate::BitReader; +#[doc = "Field `STALLRQ1` reader - Stall 1 Request"] +pub type STALLRQ1_R = crate::BitReader; +#[doc = "Field `BK0RDY` reader - Bank 0 ready"] +pub type BK0RDY_R = crate::BitReader; +#[doc = "Field `BK1RDY` reader - Bank 1 ready"] +pub type BK1RDY_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Data Toggle Out"] + #[inline(always)] + pub fn dtglout(&self) -> DTGLOUT_R { + DTGLOUT_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Data Toggle In"] + #[inline(always)] + pub fn dtglin(&self) -> DTGLIN_R { + DTGLIN_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Current Bank"] + #[inline(always)] + pub fn curbk(&self) -> CURBK_R { + CURBK_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 4 - Stall 0 Request"] + #[inline(always)] + pub fn stallrq0(&self) -> STALLRQ0_R { + STALLRQ0_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - Stall 1 Request"] + #[inline(always)] + pub fn stallrq1(&self) -> STALLRQ1_R { + STALLRQ1_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Bank 0 ready"] + #[inline(always)] + pub fn bk0rdy(&self) -> BK0RDY_R { + BK0RDY_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Bank 1 ready"] + #[inline(always)] + pub fn bk1rdy(&self) -> BK1RDY_R { + BK1RDY_R::new(((self.bits >> 7) & 1) != 0) + } +} +#[doc = "DEVICE End Point Pipe Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [epstatus](index.html) module"] +pub struct EPSTATUS_SPEC; +impl crate::RegisterSpec for EPSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [epstatus::R](R) reader structure"] +impl crate::Readable for EPSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets EPSTATUS%s to value 0"] +impl crate::Resettable for EPSTATUS_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/usb/device/epstatusclr.rs b/pac/atsaml22j/src/usb/device/epstatusclr.rs new file mode 100644 index 000000000000..0452f8ff295b --- /dev/null +++ b/pac/atsaml22j/src/usb/device/epstatusclr.rs @@ -0,0 +1,100 @@ +#[doc = "Register `EPSTATUSCLR%s` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DTGLOUT` writer - Data Toggle OUT Clear"] +pub type DTGLOUT_W<'a, const O: u8> = crate::BitWriter<'a, u8, EPSTATUSCLR_SPEC, bool, O>; +#[doc = "Field `DTGLIN` writer - Data Toggle IN Clear"] +pub type DTGLIN_W<'a, const O: u8> = crate::BitWriter<'a, u8, EPSTATUSCLR_SPEC, bool, O>; +#[doc = "Field `CURBK` writer - Current Bank Clear"] +pub type CURBK_W<'a, const O: u8> = crate::BitWriter<'a, u8, EPSTATUSCLR_SPEC, bool, O>; +#[doc = "Field `STALLRQ0` writer - Stall 0 Request Clear"] +pub type STALLRQ0_W<'a, const O: u8> = crate::BitWriter<'a, u8, EPSTATUSCLR_SPEC, bool, O>; +#[doc = "Field `STALLRQ1` writer - Stall 1 Request Clear"] +pub type STALLRQ1_W<'a, const O: u8> = crate::BitWriter<'a, u8, EPSTATUSCLR_SPEC, bool, O>; +#[doc = "Field `BK0RDY` writer - Bank 0 Ready Clear"] +pub type BK0RDY_W<'a, const O: u8> = crate::BitWriter<'a, u8, EPSTATUSCLR_SPEC, bool, O>; +#[doc = "Field `BK1RDY` writer - Bank 1 Ready Clear"] +pub type BK1RDY_W<'a, const O: u8> = crate::BitWriter<'a, u8, EPSTATUSCLR_SPEC, bool, O>; +impl W { + #[doc = "Bit 0 - Data Toggle OUT Clear"] + #[inline(always)] + #[must_use] + pub fn dtglout(&mut self) -> DTGLOUT_W<0> { + DTGLOUT_W::new(self) + } + #[doc = "Bit 1 - Data Toggle IN Clear"] + #[inline(always)] + #[must_use] + pub fn dtglin(&mut self) -> DTGLIN_W<1> { + DTGLIN_W::new(self) + } + #[doc = "Bit 2 - Current Bank Clear"] + #[inline(always)] + #[must_use] + pub fn curbk(&mut self) -> CURBK_W<2> { + CURBK_W::new(self) + } + #[doc = "Bit 4 - Stall 0 Request Clear"] + #[inline(always)] + #[must_use] + pub fn stallrq0(&mut self) -> STALLRQ0_W<4> { + STALLRQ0_W::new(self) + } + #[doc = "Bit 5 - Stall 1 Request Clear"] + #[inline(always)] + #[must_use] + pub fn stallrq1(&mut self) -> STALLRQ1_W<5> { + STALLRQ1_W::new(self) + } + #[doc = "Bit 6 - Bank 0 Ready Clear"] + #[inline(always)] + #[must_use] + pub fn bk0rdy(&mut self) -> BK0RDY_W<6> { + BK0RDY_W::new(self) + } + #[doc = "Bit 7 - Bank 1 Ready Clear"] + #[inline(always)] + #[must_use] + pub fn bk1rdy(&mut self) -> BK1RDY_W<7> { + BK1RDY_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DEVICE End Point Pipe Status Clear\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [epstatusclr](index.html) module"] +pub struct EPSTATUSCLR_SPEC; +impl crate::RegisterSpec for EPSTATUSCLR_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [epstatusclr::W](W) writer structure"] +impl crate::Writable for EPSTATUSCLR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EPSTATUSCLR%s to value 0"] +impl crate::Resettable for EPSTATUSCLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/usb/device/epstatusset.rs b/pac/atsaml22j/src/usb/device/epstatusset.rs new file mode 100644 index 000000000000..130a32c8d7e1 --- /dev/null +++ b/pac/atsaml22j/src/usb/device/epstatusset.rs @@ -0,0 +1,100 @@ +#[doc = "Register `EPSTATUSSET%s` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `DTGLOUT` writer - Data Toggle OUT Set"] +pub type DTGLOUT_W<'a, const O: u8> = crate::BitWriter<'a, u8, EPSTATUSSET_SPEC, bool, O>; +#[doc = "Field `DTGLIN` writer - Data Toggle IN Set"] +pub type DTGLIN_W<'a, const O: u8> = crate::BitWriter<'a, u8, EPSTATUSSET_SPEC, bool, O>; +#[doc = "Field `CURBK` writer - Current Bank Set"] +pub type CURBK_W<'a, const O: u8> = crate::BitWriter<'a, u8, EPSTATUSSET_SPEC, bool, O>; +#[doc = "Field `STALLRQ0` writer - Stall 0 Request Set"] +pub type STALLRQ0_W<'a, const O: u8> = crate::BitWriter<'a, u8, EPSTATUSSET_SPEC, bool, O>; +#[doc = "Field `STALLRQ1` writer - Stall 1 Request Set"] +pub type STALLRQ1_W<'a, const O: u8> = crate::BitWriter<'a, u8, EPSTATUSSET_SPEC, bool, O>; +#[doc = "Field `BK0RDY` writer - Bank 0 Ready Set"] +pub type BK0RDY_W<'a, const O: u8> = crate::BitWriter<'a, u8, EPSTATUSSET_SPEC, bool, O>; +#[doc = "Field `BK1RDY` writer - Bank 1 Ready Set"] +pub type BK1RDY_W<'a, const O: u8> = crate::BitWriter<'a, u8, EPSTATUSSET_SPEC, bool, O>; +impl W { + #[doc = "Bit 0 - Data Toggle OUT Set"] + #[inline(always)] + #[must_use] + pub fn dtglout(&mut self) -> DTGLOUT_W<0> { + DTGLOUT_W::new(self) + } + #[doc = "Bit 1 - Data Toggle IN Set"] + #[inline(always)] + #[must_use] + pub fn dtglin(&mut self) -> DTGLIN_W<1> { + DTGLIN_W::new(self) + } + #[doc = "Bit 2 - Current Bank Set"] + #[inline(always)] + #[must_use] + pub fn curbk(&mut self) -> CURBK_W<2> { + CURBK_W::new(self) + } + #[doc = "Bit 4 - Stall 0 Request Set"] + #[inline(always)] + #[must_use] + pub fn stallrq0(&mut self) -> STALLRQ0_W<4> { + STALLRQ0_W::new(self) + } + #[doc = "Bit 5 - Stall 1 Request Set"] + #[inline(always)] + #[must_use] + pub fn stallrq1(&mut self) -> STALLRQ1_W<5> { + STALLRQ1_W::new(self) + } + #[doc = "Bit 6 - Bank 0 Ready Set"] + #[inline(always)] + #[must_use] + pub fn bk0rdy(&mut self) -> BK0RDY_W<6> { + BK0RDY_W::new(self) + } + #[doc = "Bit 7 - Bank 1 Ready Set"] + #[inline(always)] + #[must_use] + pub fn bk1rdy(&mut self) -> BK1RDY_W<7> { + BK1RDY_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DEVICE End Point Pipe Status Set\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [epstatusset](index.html) module"] +pub struct EPSTATUSSET_SPEC; +impl crate::RegisterSpec for EPSTATUSSET_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [epstatusset::W](W) writer structure"] +impl crate::Writable for EPSTATUSSET_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EPSTATUSSET%s to value 0"] +impl crate::Resettable for EPSTATUSSET_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/usb/device/fnum.rs b/pac/atsaml22j/src/usb/device/fnum.rs new file mode 100644 index 000000000000..39573946e000 --- /dev/null +++ b/pac/atsaml22j/src/usb/device/fnum.rs @@ -0,0 +1,51 @@ +#[doc = "Register `FNUM` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `MFNUM` reader - Micro Frame Number"] +pub type MFNUM_R = crate::FieldReader; +#[doc = "Field `FNUM` reader - Frame Number"] +pub type FNUM_R = crate::FieldReader; +#[doc = "Field `FNCERR` reader - Frame Number CRC Error"] +pub type FNCERR_R = crate::BitReader; +impl R { + #[doc = "Bits 0:2 - Micro Frame Number"] + #[inline(always)] + pub fn mfnum(&self) -> MFNUM_R { + MFNUM_R::new((self.bits & 7) as u8) + } + #[doc = "Bits 3:13 - Frame Number"] + #[inline(always)] + pub fn fnum(&self) -> FNUM_R { + FNUM_R::new((self.bits >> 3) & 0x07ff) + } + #[doc = "Bit 15 - Frame Number CRC Error"] + #[inline(always)] + pub fn fncerr(&self) -> FNCERR_R { + FNCERR_R::new(((self.bits >> 15) & 1) != 0) + } +} +#[doc = "DEVICE Device Frame Number\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fnum](index.html) module"] +pub struct FNUM_SPEC; +impl crate::RegisterSpec for FNUM_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [fnum::R](R) reader structure"] +impl crate::Readable for FNUM_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets FNUM to value 0"] +impl crate::Resettable for FNUM_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/usb/device/fsmstatus.rs b/pac/atsaml22j/src/usb/device/fsmstatus.rs new file mode 100644 index 000000000000..24fcae054af5 --- /dev/null +++ b/pac/atsaml22j/src/usb/device/fsmstatus.rs @@ -0,0 +1,113 @@ +#[doc = "Register `FSMSTATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `FSMSTATE` reader - Fine State Machine Status"] +pub type FSMSTATE_R = crate::FieldReader; +#[doc = "Fine State Machine Status\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum FSMSTATESELECT_A { + #[doc = "1: OFF (L3). It corresponds to the powered-off, disconnected, and disabled state"] + OFF = 1, + #[doc = "2: ON (L0). It corresponds to the Idle and Active states"] + ON = 2, + #[doc = "4: SUSPEND (L2)"] + SUSPEND = 4, + #[doc = "8: SLEEP (L1)"] + SLEEP = 8, + #[doc = "16: DNRESUME. Down Stream Resume."] + DNRESUME = 16, + #[doc = "32: UPRESUME. Up Stream Resume."] + UPRESUME = 32, + #[doc = "64: RESET. USB lines Reset."] + RESET = 64, +} +impl From for u8 { + #[inline(always)] + fn from(variant: FSMSTATESELECT_A) -> Self { + variant as _ + } +} +impl FSMSTATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 1 => Some(FSMSTATESELECT_A::OFF), + 2 => Some(FSMSTATESELECT_A::ON), + 4 => Some(FSMSTATESELECT_A::SUSPEND), + 8 => Some(FSMSTATESELECT_A::SLEEP), + 16 => Some(FSMSTATESELECT_A::DNRESUME), + 32 => Some(FSMSTATESELECT_A::UPRESUME), + 64 => Some(FSMSTATESELECT_A::RESET), + _ => None, + } + } + #[doc = "Checks if the value of the field is `OFF`"] + #[inline(always)] + pub fn is_off(&self) -> bool { + *self == FSMSTATESELECT_A::OFF + } + #[doc = "Checks if the value of the field is `ON`"] + #[inline(always)] + pub fn is_on(&self) -> bool { + *self == FSMSTATESELECT_A::ON + } + #[doc = "Checks if the value of the field is `SUSPEND`"] + #[inline(always)] + pub fn is_suspend(&self) -> bool { + *self == FSMSTATESELECT_A::SUSPEND + } + #[doc = "Checks if the value of the field is `SLEEP`"] + #[inline(always)] + pub fn is_sleep(&self) -> bool { + *self == FSMSTATESELECT_A::SLEEP + } + #[doc = "Checks if the value of the field is `DNRESUME`"] + #[inline(always)] + pub fn is_dnresume(&self) -> bool { + *self == FSMSTATESELECT_A::DNRESUME + } + #[doc = "Checks if the value of the field is `UPRESUME`"] + #[inline(always)] + pub fn is_upresume(&self) -> bool { + *self == FSMSTATESELECT_A::UPRESUME + } + #[doc = "Checks if the value of the field is `RESET`"] + #[inline(always)] + pub fn is_reset(&self) -> bool { + *self == FSMSTATESELECT_A::RESET + } +} +impl R { + #[doc = "Bits 0:6 - Fine State Machine Status"] + #[inline(always)] + pub fn fsmstate(&self) -> FSMSTATE_R { + FSMSTATE_R::new(self.bits & 0x7f) + } +} +#[doc = "Finite State Machine Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fsmstatus](index.html) module"] +pub struct FSMSTATUS_SPEC; +impl crate::RegisterSpec for FSMSTATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [fsmstatus::R](R) reader structure"] +impl crate::Readable for FSMSTATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets FSMSTATUS to value 0x01"] +impl crate::Resettable for FSMSTATUS_SPEC { + const RESET_VALUE: Self::Ux = 0x01; +} diff --git a/pac/atsaml22j/src/usb/device/intenclr.rs b/pac/atsaml22j/src/usb/device/intenclr.rs new file mode 100644 index 000000000000..2cfc94e08d31 --- /dev/null +++ b/pac/atsaml22j/src/usb/device/intenclr.rs @@ -0,0 +1,215 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SUSPEND` reader - Suspend Interrupt Enable"] +pub type SUSPEND_R = crate::BitReader; +#[doc = "Field `SUSPEND` writer - Suspend Interrupt Enable"] +pub type SUSPEND_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENCLR_SPEC, bool, O>; +#[doc = "Field `MSOF` reader - Micro Start of Frame Interrupt Enable in High Speed Mode"] +pub type MSOF_R = crate::BitReader; +#[doc = "Field `MSOF` writer - Micro Start of Frame Interrupt Enable in High Speed Mode"] +pub type MSOF_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENCLR_SPEC, bool, O>; +#[doc = "Field `SOF` reader - Start Of Frame Interrupt Enable"] +pub type SOF_R = crate::BitReader; +#[doc = "Field `SOF` writer - Start Of Frame Interrupt Enable"] +pub type SOF_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENCLR_SPEC, bool, O>; +#[doc = "Field `EORST` reader - End of Reset Interrupt Enable"] +pub type EORST_R = crate::BitReader; +#[doc = "Field `EORST` writer - End of Reset Interrupt Enable"] +pub type EORST_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENCLR_SPEC, bool, O>; +#[doc = "Field `WAKEUP` reader - Wake Up Interrupt Enable"] +pub type WAKEUP_R = crate::BitReader; +#[doc = "Field `WAKEUP` writer - Wake Up Interrupt Enable"] +pub type WAKEUP_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENCLR_SPEC, bool, O>; +#[doc = "Field `EORSM` reader - End Of Resume Interrupt Enable"] +pub type EORSM_R = crate::BitReader; +#[doc = "Field `EORSM` writer - End Of Resume Interrupt Enable"] +pub type EORSM_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENCLR_SPEC, bool, O>; +#[doc = "Field `UPRSM` reader - Upstream Resume Interrupt Enable"] +pub type UPRSM_R = crate::BitReader; +#[doc = "Field `UPRSM` writer - Upstream Resume Interrupt Enable"] +pub type UPRSM_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENCLR_SPEC, bool, O>; +#[doc = "Field `RAMACER` reader - Ram Access Interrupt Enable"] +pub type RAMACER_R = crate::BitReader; +#[doc = "Field `RAMACER` writer - Ram Access Interrupt Enable"] +pub type RAMACER_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENCLR_SPEC, bool, O>; +#[doc = "Field `LPMNYET` reader - Link Power Management Not Yet Interrupt Enable"] +pub type LPMNYET_R = crate::BitReader; +#[doc = "Field `LPMNYET` writer - Link Power Management Not Yet Interrupt Enable"] +pub type LPMNYET_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENCLR_SPEC, bool, O>; +#[doc = "Field `LPMSUSP` reader - Link Power Management Suspend Interrupt Enable"] +pub type LPMSUSP_R = crate::BitReader; +#[doc = "Field `LPMSUSP` writer - Link Power Management Suspend Interrupt Enable"] +pub type LPMSUSP_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENCLR_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Suspend Interrupt Enable"] + #[inline(always)] + pub fn suspend(&self) -> SUSPEND_R { + SUSPEND_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Micro Start of Frame Interrupt Enable in High Speed Mode"] + #[inline(always)] + pub fn msof(&self) -> MSOF_R { + MSOF_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Start Of Frame Interrupt Enable"] + #[inline(always)] + pub fn sof(&self) -> SOF_R { + SOF_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - End of Reset Interrupt Enable"] + #[inline(always)] + pub fn eorst(&self) -> EORST_R { + EORST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Wake Up Interrupt Enable"] + #[inline(always)] + pub fn wakeup(&self) -> WAKEUP_R { + WAKEUP_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - End Of Resume Interrupt Enable"] + #[inline(always)] + pub fn eorsm(&self) -> EORSM_R { + EORSM_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Upstream Resume Interrupt Enable"] + #[inline(always)] + pub fn uprsm(&self) -> UPRSM_R { + UPRSM_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Ram Access Interrupt Enable"] + #[inline(always)] + pub fn ramacer(&self) -> RAMACER_R { + RAMACER_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Link Power Management Not Yet Interrupt Enable"] + #[inline(always)] + pub fn lpmnyet(&self) -> LPMNYET_R { + LPMNYET_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Link Power Management Suspend Interrupt Enable"] + #[inline(always)] + pub fn lpmsusp(&self) -> LPMSUSP_R { + LPMSUSP_R::new(((self.bits >> 9) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Suspend Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn suspend(&mut self) -> SUSPEND_W<0> { + SUSPEND_W::new(self) + } + #[doc = "Bit 1 - Micro Start of Frame Interrupt Enable in High Speed Mode"] + #[inline(always)] + #[must_use] + pub fn msof(&mut self) -> MSOF_W<1> { + MSOF_W::new(self) + } + #[doc = "Bit 2 - Start Of Frame Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn sof(&mut self) -> SOF_W<2> { + SOF_W::new(self) + } + #[doc = "Bit 3 - End of Reset Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn eorst(&mut self) -> EORST_W<3> { + EORST_W::new(self) + } + #[doc = "Bit 4 - Wake Up Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn wakeup(&mut self) -> WAKEUP_W<4> { + WAKEUP_W::new(self) + } + #[doc = "Bit 5 - End Of Resume Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn eorsm(&mut self) -> EORSM_W<5> { + EORSM_W::new(self) + } + #[doc = "Bit 6 - Upstream Resume Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn uprsm(&mut self) -> UPRSM_W<6> { + UPRSM_W::new(self) + } + #[doc = "Bit 7 - Ram Access Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn ramacer(&mut self) -> RAMACER_W<7> { + RAMACER_W::new(self) + } + #[doc = "Bit 8 - Link Power Management Not Yet Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn lpmnyet(&mut self) -> LPMNYET_W<8> { + LPMNYET_W::new(self) + } + #[doc = "Bit 9 - Link Power Management Suspend Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn lpmsusp(&mut self) -> LPMSUSP_W<9> { + LPMSUSP_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DEVICE Device Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/usb/device/intenset.rs b/pac/atsaml22j/src/usb/device/intenset.rs new file mode 100644 index 000000000000..9e719529fcd6 --- /dev/null +++ b/pac/atsaml22j/src/usb/device/intenset.rs @@ -0,0 +1,215 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SUSPEND` reader - Suspend Interrupt Enable"] +pub type SUSPEND_R = crate::BitReader; +#[doc = "Field `SUSPEND` writer - Suspend Interrupt Enable"] +pub type SUSPEND_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENSET_SPEC, bool, O>; +#[doc = "Field `MSOF` reader - Micro Start of Frame Interrupt Enable in High Speed Mode"] +pub type MSOF_R = crate::BitReader; +#[doc = "Field `MSOF` writer - Micro Start of Frame Interrupt Enable in High Speed Mode"] +pub type MSOF_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENSET_SPEC, bool, O>; +#[doc = "Field `SOF` reader - Start Of Frame Interrupt Enable"] +pub type SOF_R = crate::BitReader; +#[doc = "Field `SOF` writer - Start Of Frame Interrupt Enable"] +pub type SOF_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENSET_SPEC, bool, O>; +#[doc = "Field `EORST` reader - End of Reset Interrupt Enable"] +pub type EORST_R = crate::BitReader; +#[doc = "Field `EORST` writer - End of Reset Interrupt Enable"] +pub type EORST_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENSET_SPEC, bool, O>; +#[doc = "Field `WAKEUP` reader - Wake Up Interrupt Enable"] +pub type WAKEUP_R = crate::BitReader; +#[doc = "Field `WAKEUP` writer - Wake Up Interrupt Enable"] +pub type WAKEUP_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENSET_SPEC, bool, O>; +#[doc = "Field `EORSM` reader - End Of Resume Interrupt Enable"] +pub type EORSM_R = crate::BitReader; +#[doc = "Field `EORSM` writer - End Of Resume Interrupt Enable"] +pub type EORSM_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENSET_SPEC, bool, O>; +#[doc = "Field `UPRSM` reader - Upstream Resume Interrupt Enable"] +pub type UPRSM_R = crate::BitReader; +#[doc = "Field `UPRSM` writer - Upstream Resume Interrupt Enable"] +pub type UPRSM_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENSET_SPEC, bool, O>; +#[doc = "Field `RAMACER` reader - Ram Access Interrupt Enable"] +pub type RAMACER_R = crate::BitReader; +#[doc = "Field `RAMACER` writer - Ram Access Interrupt Enable"] +pub type RAMACER_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENSET_SPEC, bool, O>; +#[doc = "Field `LPMNYET` reader - Link Power Management Not Yet Interrupt Enable"] +pub type LPMNYET_R = crate::BitReader; +#[doc = "Field `LPMNYET` writer - Link Power Management Not Yet Interrupt Enable"] +pub type LPMNYET_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENSET_SPEC, bool, O>; +#[doc = "Field `LPMSUSP` reader - Link Power Management Suspend Interrupt Enable"] +pub type LPMSUSP_R = crate::BitReader; +#[doc = "Field `LPMSUSP` writer - Link Power Management Suspend Interrupt Enable"] +pub type LPMSUSP_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTENSET_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Suspend Interrupt Enable"] + #[inline(always)] + pub fn suspend(&self) -> SUSPEND_R { + SUSPEND_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Micro Start of Frame Interrupt Enable in High Speed Mode"] + #[inline(always)] + pub fn msof(&self) -> MSOF_R { + MSOF_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Start Of Frame Interrupt Enable"] + #[inline(always)] + pub fn sof(&self) -> SOF_R { + SOF_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - End of Reset Interrupt Enable"] + #[inline(always)] + pub fn eorst(&self) -> EORST_R { + EORST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Wake Up Interrupt Enable"] + #[inline(always)] + pub fn wakeup(&self) -> WAKEUP_R { + WAKEUP_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - End Of Resume Interrupt Enable"] + #[inline(always)] + pub fn eorsm(&self) -> EORSM_R { + EORSM_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Upstream Resume Interrupt Enable"] + #[inline(always)] + pub fn uprsm(&self) -> UPRSM_R { + UPRSM_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Ram Access Interrupt Enable"] + #[inline(always)] + pub fn ramacer(&self) -> RAMACER_R { + RAMACER_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Link Power Management Not Yet Interrupt Enable"] + #[inline(always)] + pub fn lpmnyet(&self) -> LPMNYET_R { + LPMNYET_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Link Power Management Suspend Interrupt Enable"] + #[inline(always)] + pub fn lpmsusp(&self) -> LPMSUSP_R { + LPMSUSP_R::new(((self.bits >> 9) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Suspend Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn suspend(&mut self) -> SUSPEND_W<0> { + SUSPEND_W::new(self) + } + #[doc = "Bit 1 - Micro Start of Frame Interrupt Enable in High Speed Mode"] + #[inline(always)] + #[must_use] + pub fn msof(&mut self) -> MSOF_W<1> { + MSOF_W::new(self) + } + #[doc = "Bit 2 - Start Of Frame Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn sof(&mut self) -> SOF_W<2> { + SOF_W::new(self) + } + #[doc = "Bit 3 - End of Reset Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn eorst(&mut self) -> EORST_W<3> { + EORST_W::new(self) + } + #[doc = "Bit 4 - Wake Up Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn wakeup(&mut self) -> WAKEUP_W<4> { + WAKEUP_W::new(self) + } + #[doc = "Bit 5 - End Of Resume Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn eorsm(&mut self) -> EORSM_W<5> { + EORSM_W::new(self) + } + #[doc = "Bit 6 - Upstream Resume Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn uprsm(&mut self) -> UPRSM_W<6> { + UPRSM_W::new(self) + } + #[doc = "Bit 7 - Ram Access Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn ramacer(&mut self) -> RAMACER_W<7> { + RAMACER_W::new(self) + } + #[doc = "Bit 8 - Link Power Management Not Yet Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn lpmnyet(&mut self) -> LPMNYET_W<8> { + LPMNYET_W::new(self) + } + #[doc = "Bit 9 - Link Power Management Suspend Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn lpmsusp(&mut self) -> LPMSUSP_W<9> { + LPMSUSP_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DEVICE Device Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/usb/device/intflag.rs b/pac/atsaml22j/src/usb/device/intflag.rs new file mode 100644 index 000000000000..e0a97fb5747c --- /dev/null +++ b/pac/atsaml22j/src/usb/device/intflag.rs @@ -0,0 +1,215 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `SUSPEND` reader - Suspend"] +pub type SUSPEND_R = crate::BitReader; +#[doc = "Field `SUSPEND` writer - Suspend"] +pub type SUSPEND_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTFLAG_SPEC, bool, O>; +#[doc = "Field `MSOF` reader - Micro Start of Frame in High Speed Mode"] +pub type MSOF_R = crate::BitReader; +#[doc = "Field `MSOF` writer - Micro Start of Frame in High Speed Mode"] +pub type MSOF_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTFLAG_SPEC, bool, O>; +#[doc = "Field `SOF` reader - Start Of Frame"] +pub type SOF_R = crate::BitReader; +#[doc = "Field `SOF` writer - Start Of Frame"] +pub type SOF_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTFLAG_SPEC, bool, O>; +#[doc = "Field `EORST` reader - End of Reset"] +pub type EORST_R = crate::BitReader; +#[doc = "Field `EORST` writer - End of Reset"] +pub type EORST_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTFLAG_SPEC, bool, O>; +#[doc = "Field `WAKEUP` reader - Wake Up"] +pub type WAKEUP_R = crate::BitReader; +#[doc = "Field `WAKEUP` writer - Wake Up"] +pub type WAKEUP_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTFLAG_SPEC, bool, O>; +#[doc = "Field `EORSM` reader - End Of Resume"] +pub type EORSM_R = crate::BitReader; +#[doc = "Field `EORSM` writer - End Of Resume"] +pub type EORSM_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTFLAG_SPEC, bool, O>; +#[doc = "Field `UPRSM` reader - Upstream Resume"] +pub type UPRSM_R = crate::BitReader; +#[doc = "Field `UPRSM` writer - Upstream Resume"] +pub type UPRSM_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTFLAG_SPEC, bool, O>; +#[doc = "Field `RAMACER` reader - Ram Access"] +pub type RAMACER_R = crate::BitReader; +#[doc = "Field `RAMACER` writer - Ram Access"] +pub type RAMACER_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTFLAG_SPEC, bool, O>; +#[doc = "Field `LPMNYET` reader - Link Power Management Not Yet"] +pub type LPMNYET_R = crate::BitReader; +#[doc = "Field `LPMNYET` writer - Link Power Management Not Yet"] +pub type LPMNYET_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTFLAG_SPEC, bool, O>; +#[doc = "Field `LPMSUSP` reader - Link Power Management Suspend"] +pub type LPMSUSP_R = crate::BitReader; +#[doc = "Field `LPMSUSP` writer - Link Power Management Suspend"] +pub type LPMSUSP_W<'a, const O: u8> = crate::BitWriter<'a, u16, INTFLAG_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Suspend"] + #[inline(always)] + pub fn suspend(&self) -> SUSPEND_R { + SUSPEND_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Micro Start of Frame in High Speed Mode"] + #[inline(always)] + pub fn msof(&self) -> MSOF_R { + MSOF_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Start Of Frame"] + #[inline(always)] + pub fn sof(&self) -> SOF_R { + SOF_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - End of Reset"] + #[inline(always)] + pub fn eorst(&self) -> EORST_R { + EORST_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Wake Up"] + #[inline(always)] + pub fn wakeup(&self) -> WAKEUP_R { + WAKEUP_R::new(((self.bits >> 4) & 1) != 0) + } + #[doc = "Bit 5 - End Of Resume"] + #[inline(always)] + pub fn eorsm(&self) -> EORSM_R { + EORSM_R::new(((self.bits >> 5) & 1) != 0) + } + #[doc = "Bit 6 - Upstream Resume"] + #[inline(always)] + pub fn uprsm(&self) -> UPRSM_R { + UPRSM_R::new(((self.bits >> 6) & 1) != 0) + } + #[doc = "Bit 7 - Ram Access"] + #[inline(always)] + pub fn ramacer(&self) -> RAMACER_R { + RAMACER_R::new(((self.bits >> 7) & 1) != 0) + } + #[doc = "Bit 8 - Link Power Management Not Yet"] + #[inline(always)] + pub fn lpmnyet(&self) -> LPMNYET_R { + LPMNYET_R::new(((self.bits >> 8) & 1) != 0) + } + #[doc = "Bit 9 - Link Power Management Suspend"] + #[inline(always)] + pub fn lpmsusp(&self) -> LPMSUSP_R { + LPMSUSP_R::new(((self.bits >> 9) & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Suspend"] + #[inline(always)] + #[must_use] + pub fn suspend(&mut self) -> SUSPEND_W<0> { + SUSPEND_W::new(self) + } + #[doc = "Bit 1 - Micro Start of Frame in High Speed Mode"] + #[inline(always)] + #[must_use] + pub fn msof(&mut self) -> MSOF_W<1> { + MSOF_W::new(self) + } + #[doc = "Bit 2 - Start Of Frame"] + #[inline(always)] + #[must_use] + pub fn sof(&mut self) -> SOF_W<2> { + SOF_W::new(self) + } + #[doc = "Bit 3 - End of Reset"] + #[inline(always)] + #[must_use] + pub fn eorst(&mut self) -> EORST_W<3> { + EORST_W::new(self) + } + #[doc = "Bit 4 - Wake Up"] + #[inline(always)] + #[must_use] + pub fn wakeup(&mut self) -> WAKEUP_W<4> { + WAKEUP_W::new(self) + } + #[doc = "Bit 5 - End Of Resume"] + #[inline(always)] + #[must_use] + pub fn eorsm(&mut self) -> EORSM_W<5> { + EORSM_W::new(self) + } + #[doc = "Bit 6 - Upstream Resume"] + #[inline(always)] + #[must_use] + pub fn uprsm(&mut self) -> UPRSM_W<6> { + UPRSM_W::new(self) + } + #[doc = "Bit 7 - Ram Access"] + #[inline(always)] + #[must_use] + pub fn ramacer(&mut self) -> RAMACER_W<7> { + RAMACER_W::new(self) + } + #[doc = "Bit 8 - Link Power Management Not Yet"] + #[inline(always)] + #[must_use] + pub fn lpmnyet(&mut self) -> LPMNYET_W<8> { + LPMNYET_W::new(self) + } + #[doc = "Bit 9 - Link Power Management Suspend"] + #[inline(always)] + #[must_use] + pub fn lpmsusp(&mut self) -> LPMSUSP_W<9> { + LPMSUSP_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "DEVICE Device Interrupt Flag\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/usb/device/padcal.rs b/pac/atsaml22j/src/usb/device/padcal.rs new file mode 100644 index 000000000000..fbe53d521be9 --- /dev/null +++ b/pac/atsaml22j/src/usb/device/padcal.rs @@ -0,0 +1,110 @@ +#[doc = "Register `PADCAL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `PADCAL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `TRANSP` reader - USB Pad Transp calibration"] +pub type TRANSP_R = crate::FieldReader; +#[doc = "Field `TRANSP` writer - USB Pad Transp calibration"] +pub type TRANSP_W<'a, const O: u8> = crate::FieldWriter<'a, u16, PADCAL_SPEC, u8, u8, 5, O>; +#[doc = "Field `TRANSN` reader - USB Pad Transn calibration"] +pub type TRANSN_R = crate::FieldReader; +#[doc = "Field `TRANSN` writer - USB Pad Transn calibration"] +pub type TRANSN_W<'a, const O: u8> = crate::FieldWriter<'a, u16, PADCAL_SPEC, u8, u8, 5, O>; +#[doc = "Field `TRIM` reader - USB Pad Trim calibration"] +pub type TRIM_R = crate::FieldReader; +#[doc = "Field `TRIM` writer - USB Pad Trim calibration"] +pub type TRIM_W<'a, const O: u8> = crate::FieldWriter<'a, u16, PADCAL_SPEC, u8, u8, 3, O>; +impl R { + #[doc = "Bits 0:4 - USB Pad Transp calibration"] + #[inline(always)] + pub fn transp(&self) -> TRANSP_R { + TRANSP_R::new((self.bits & 0x1f) as u8) + } + #[doc = "Bits 6:10 - USB Pad Transn calibration"] + #[inline(always)] + pub fn transn(&self) -> TRANSN_R { + TRANSN_R::new(((self.bits >> 6) & 0x1f) as u8) + } + #[doc = "Bits 12:14 - USB Pad Trim calibration"] + #[inline(always)] + pub fn trim(&self) -> TRIM_R { + TRIM_R::new(((self.bits >> 12) & 7) as u8) + } +} +impl W { + #[doc = "Bits 0:4 - USB Pad Transp calibration"] + #[inline(always)] + #[must_use] + pub fn transp(&mut self) -> TRANSP_W<0> { + TRANSP_W::new(self) + } + #[doc = "Bits 6:10 - USB Pad Transn calibration"] + #[inline(always)] + #[must_use] + pub fn transn(&mut self) -> TRANSN_W<6> { + TRANSN_W::new(self) + } + #[doc = "Bits 12:14 - USB Pad Trim calibration"] + #[inline(always)] + #[must_use] + pub fn trim(&mut self) -> TRIM_W<12> { + TRIM_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u16) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USB PAD Calibration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [padcal](index.html) module"] +pub struct PADCAL_SPEC; +impl crate::RegisterSpec for PADCAL_SPEC { + type Ux = u16; +} +#[doc = "`read()` method returns [padcal::R](R) reader structure"] +impl crate::Readable for PADCAL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [padcal::W](W) writer structure"] +impl crate::Writable for PADCAL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets PADCAL to value 0"] +impl crate::Resettable for PADCAL_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/usb/device/qosctrl.rs b/pac/atsaml22j/src/usb/device/qosctrl.rs new file mode 100644 index 000000000000..0e00f7c10098 --- /dev/null +++ b/pac/atsaml22j/src/usb/device/qosctrl.rs @@ -0,0 +1,95 @@ +#[doc = "Register `QOSCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `QOSCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `CQOS` reader - Configuration Quality of Service"] +pub type CQOS_R = crate::FieldReader; +#[doc = "Field `CQOS` writer - Configuration Quality of Service"] +pub type CQOS_W<'a, const O: u8> = crate::FieldWriter<'a, u8, QOSCTRL_SPEC, u8, u8, 2, O>; +#[doc = "Field `DQOS` reader - Data Quality of Service"] +pub type DQOS_R = crate::FieldReader; +#[doc = "Field `DQOS` writer - Data Quality of Service"] +pub type DQOS_W<'a, const O: u8> = crate::FieldWriter<'a, u8, QOSCTRL_SPEC, u8, u8, 2, O>; +impl R { + #[doc = "Bits 0:1 - Configuration Quality of Service"] + #[inline(always)] + pub fn cqos(&self) -> CQOS_R { + CQOS_R::new(self.bits & 3) + } + #[doc = "Bits 2:3 - Data Quality of Service"] + #[inline(always)] + pub fn dqos(&self) -> DQOS_R { + DQOS_R::new((self.bits >> 2) & 3) + } +} +impl W { + #[doc = "Bits 0:1 - Configuration Quality of Service"] + #[inline(always)] + #[must_use] + pub fn cqos(&mut self) -> CQOS_W<0> { + CQOS_W::new(self) + } + #[doc = "Bits 2:3 - Data Quality of Service"] + #[inline(always)] + #[must_use] + pub fn dqos(&mut self) -> DQOS_W<2> { + DQOS_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "USB Quality Of Service\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [qosctrl](index.html) module"] +pub struct QOSCTRL_SPEC; +impl crate::RegisterSpec for QOSCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [qosctrl::R](R) reader structure"] +impl crate::Readable for QOSCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [qosctrl::W](W) writer structure"] +impl crate::Writable for QOSCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets QOSCTRL to value 0x0f"] +impl crate::Resettable for QOSCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x0f; +} diff --git a/pac/atsaml22j/src/usb/device/status.rs b/pac/atsaml22j/src/usb/device/status.rs new file mode 100644 index 000000000000..f67bf9431c22 --- /dev/null +++ b/pac/atsaml22j/src/usb/device/status.rs @@ -0,0 +1,132 @@ +#[doc = "Register `STATUS` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SPEED` reader - Speed Status"] +pub type SPEED_R = crate::FieldReader; +#[doc = "Speed Status\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum SPEEDSELECT_A { + #[doc = "0: Full-speed mode"] + FS = 0, + #[doc = "1: High-speed mode"] + HS = 1, + #[doc = "2: Low-speed mode"] + LS = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: SPEEDSELECT_A) -> Self { + variant as _ + } +} +impl SPEED_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(SPEEDSELECT_A::FS), + 1 => Some(SPEEDSELECT_A::HS), + 2 => Some(SPEEDSELECT_A::LS), + _ => None, + } + } + #[doc = "Checks if the value of the field is `FS`"] + #[inline(always)] + pub fn is_fs(&self) -> bool { + *self == SPEEDSELECT_A::FS + } + #[doc = "Checks if the value of the field is `HS`"] + #[inline(always)] + pub fn is_hs(&self) -> bool { + *self == SPEEDSELECT_A::HS + } + #[doc = "Checks if the value of the field is `LS`"] + #[inline(always)] + pub fn is_ls(&self) -> bool { + *self == SPEEDSELECT_A::LS + } +} +#[doc = "Field `LINESTATE` reader - USB Line State Status"] +pub type LINESTATE_R = crate::FieldReader; +#[doc = "USB Line State Status\n\nValue on reset: 1"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum LINESTATESELECT_A { + #[doc = "0: SE0/RESET"] + _0 = 0, + #[doc = "1: FS-J or LS-K State"] + _1 = 1, + #[doc = "2: FS-K or LS-J State"] + _2 = 2, +} +impl From for u8 { + #[inline(always)] + fn from(variant: LINESTATESELECT_A) -> Self { + variant as _ + } +} +impl LINESTATE_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(LINESTATESELECT_A::_0), + 1 => Some(LINESTATESELECT_A::_1), + 2 => Some(LINESTATESELECT_A::_2), + _ => None, + } + } + #[doc = "Checks if the value of the field is `_0`"] + #[inline(always)] + pub fn is_0(&self) -> bool { + *self == LINESTATESELECT_A::_0 + } + #[doc = "Checks if the value of the field is `_1`"] + #[inline(always)] + pub fn is_1(&self) -> bool { + *self == LINESTATESELECT_A::_1 + } + #[doc = "Checks if the value of the field is `_2`"] + #[inline(always)] + pub fn is_2(&self) -> bool { + *self == LINESTATESELECT_A::_2 + } +} +impl R { + #[doc = "Bits 2:3 - Speed Status"] + #[inline(always)] + pub fn speed(&self) -> SPEED_R { + SPEED_R::new((self.bits >> 2) & 3) + } + #[doc = "Bits 6:7 - USB Line State Status"] + #[inline(always)] + pub fn linestate(&self) -> LINESTATE_R { + LINESTATE_R::new((self.bits >> 6) & 3) + } +} +#[doc = "DEVICE Status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"] +pub struct STATUS_SPEC; +impl crate::RegisterSpec for STATUS_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [status::R](R) reader structure"] +impl crate::Readable for STATUS_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets STATUS to value 0x40"] +impl crate::Resettable for STATUS_SPEC { + const RESET_VALUE: Self::Ux = 0x40; +} diff --git a/pac/atsaml22j/src/usb/device/syncbusy.rs b/pac/atsaml22j/src/usb/device/syncbusy.rs new file mode 100644 index 000000000000..26d172145964 --- /dev/null +++ b/pac/atsaml22j/src/usb/device/syncbusy.rs @@ -0,0 +1,44 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `SWRST` reader - Software Reset Synchronization Busy"] +pub type SWRST_R = crate::BitReader; +#[doc = "Field `ENABLE` reader - Enable Synchronization Busy"] +pub type ENABLE_R = crate::BitReader; +impl R { + #[doc = "Bit 0 - Software Reset Synchronization Busy"] + #[inline(always)] + pub fn swrst(&self) -> SWRST_R { + SWRST_R::new((self.bits & 1) != 0) + } + #[doc = "Bit 1 - Enable Synchronization Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 1) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/wdt.rs b/pac/atsaml22j/src/wdt.rs new file mode 100644 index 000000000000..7346b5f3076f --- /dev/null +++ b/pac/atsaml22j/src/wdt.rs @@ -0,0 +1,54 @@ +#[doc = r"Register block"] +#[repr(C)] +pub struct RegisterBlock { + #[doc = "0x00 - Control"] + pub ctrla: CTRLA, + #[doc = "0x01 - Configuration"] + pub config: CONFIG, + #[doc = "0x02 - Early Warning Interrupt Control"] + pub ewctrl: EWCTRL, + _reserved3: [u8; 0x01], + #[doc = "0x04 - Interrupt Enable Clear"] + pub intenclr: INTENCLR, + #[doc = "0x05 - Interrupt Enable Set"] + pub intenset: INTENSET, + #[doc = "0x06 - Interrupt Flag Status and Clear"] + pub intflag: INTFLAG, + _reserved6: [u8; 0x01], + #[doc = "0x08 - Synchronization Busy"] + pub syncbusy: SYNCBUSY, + #[doc = "0x0c - Clear"] + pub clear: CLEAR, +} +#[doc = "CTRLA (rw) register accessor: an alias for `Reg`"] +pub type CTRLA = crate::Reg; +#[doc = "Control"] +pub mod ctrla; +#[doc = "CONFIG (rw) register accessor: an alias for `Reg`"] +pub type CONFIG = crate::Reg; +#[doc = "Configuration"] +pub mod config; +#[doc = "EWCTRL (rw) register accessor: an alias for `Reg`"] +pub type EWCTRL = crate::Reg; +#[doc = "Early Warning Interrupt Control"] +pub mod ewctrl; +#[doc = "INTENCLR (rw) register accessor: an alias for `Reg`"] +pub type INTENCLR = crate::Reg; +#[doc = "Interrupt Enable Clear"] +pub mod intenclr; +#[doc = "INTENSET (rw) register accessor: an alias for `Reg`"] +pub type INTENSET = crate::Reg; +#[doc = "Interrupt Enable Set"] +pub mod intenset; +#[doc = "INTFLAG (rw) register accessor: an alias for `Reg`"] +pub type INTFLAG = crate::Reg; +#[doc = "Interrupt Flag Status and Clear"] +pub mod intflag; +#[doc = "SYNCBUSY (r) register accessor: an alias for `Reg`"] +pub type SYNCBUSY = crate::Reg; +#[doc = "Synchronization Busy"] +pub mod syncbusy; +#[doc = "CLEAR (w) register accessor: an alias for `Reg`"] +pub type CLEAR = crate::Reg; +#[doc = "Clear"] +pub mod clear; diff --git a/pac/atsaml22j/src/wdt/clear.rs b/pac/atsaml22j/src/wdt/clear.rs new file mode 100644 index 000000000000..5075840d1b24 --- /dev/null +++ b/pac/atsaml22j/src/wdt/clear.rs @@ -0,0 +1,73 @@ +#[doc = "Register `CLEAR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Watchdog Clear\n\nValue on reset: 0"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum CLEARSELECT_AW { + #[doc = "165: Clear Key"] + KEY = 165, +} +impl From for u8 { + #[inline(always)] + fn from(variant: CLEARSELECT_AW) -> Self { + variant as _ + } +} +#[doc = "Field `CLEAR` writer - Watchdog Clear"] +pub type CLEAR_W<'a, const O: u8> = + crate::FieldWriter<'a, u8, CLEAR_SPEC, u8, CLEARSELECT_AW, 8, O>; +impl<'a, const O: u8> CLEAR_W<'a, O> { + #[doc = "Clear Key"] + #[inline(always)] + pub fn key(self) -> &'a mut W { + self.variant(CLEARSELECT_AW::KEY) + } +} +impl W { + #[doc = "Bits 0:7 - Watchdog Clear"] + #[inline(always)] + #[must_use] + pub fn clear(&mut self) -> CLEAR_W<0> { + CLEAR_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Clear\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [clear](index.html) module"] +pub struct CLEAR_SPEC; +impl crate::RegisterSpec for CLEAR_SPEC { + type Ux = u8; +} +#[doc = "`write(|w| ..)` method takes [clear::W](W) writer structure"] +impl crate::Writable for CLEAR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CLEAR to value 0"] +impl crate::Resettable for CLEAR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/wdt/config.rs b/pac/atsaml22j/src/wdt/config.rs new file mode 100644 index 000000000000..27da6c937e3b --- /dev/null +++ b/pac/atsaml22j/src/wdt/config.rs @@ -0,0 +1,452 @@ +#[doc = "Register `CONFIG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CONFIG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `PER` reader - Time-Out Period"] +pub type PER_R = crate::FieldReader; +#[doc = "Time-Out Period\n\nValue on reset: 11"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum PERSELECT_A { + #[doc = "0: 8 clock cycles"] + CYC8 = 0, + #[doc = "1: 16 clock cycles"] + CYC16 = 1, + #[doc = "2: 32 clock cycles"] + CYC32 = 2, + #[doc = "3: 64 clock cycles"] + CYC64 = 3, + #[doc = "4: 128 clock cycles"] + CYC128 = 4, + #[doc = "5: 256 clock cycles"] + CYC256 = 5, + #[doc = "6: 512 clock cycles"] + CYC512 = 6, + #[doc = "7: 1024 clock cycles"] + CYC1024 = 7, + #[doc = "8: 2048 clock cycles"] + CYC2048 = 8, + #[doc = "9: 4096 clock cycles"] + CYC4096 = 9, + #[doc = "10: 8192 clock cycles"] + CYC8192 = 10, + #[doc = "11: 16384 clock cycles"] + CYC16384 = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: PERSELECT_A) -> Self { + variant as _ + } +} +impl PER_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(PERSELECT_A::CYC8), + 1 => Some(PERSELECT_A::CYC16), + 2 => Some(PERSELECT_A::CYC32), + 3 => Some(PERSELECT_A::CYC64), + 4 => Some(PERSELECT_A::CYC128), + 5 => Some(PERSELECT_A::CYC256), + 6 => Some(PERSELECT_A::CYC512), + 7 => Some(PERSELECT_A::CYC1024), + 8 => Some(PERSELECT_A::CYC2048), + 9 => Some(PERSELECT_A::CYC4096), + 10 => Some(PERSELECT_A::CYC8192), + 11 => Some(PERSELECT_A::CYC16384), + _ => None, + } + } + #[doc = "Checks if the value of the field is `CYC8`"] + #[inline(always)] + pub fn is_cyc8(&self) -> bool { + *self == PERSELECT_A::CYC8 + } + #[doc = "Checks if the value of the field is `CYC16`"] + #[inline(always)] + pub fn is_cyc16(&self) -> bool { + *self == PERSELECT_A::CYC16 + } + #[doc = "Checks if the value of the field is `CYC32`"] + #[inline(always)] + pub fn is_cyc32(&self) -> bool { + *self == PERSELECT_A::CYC32 + } + #[doc = "Checks if the value of the field is `CYC64`"] + #[inline(always)] + pub fn is_cyc64(&self) -> bool { + *self == PERSELECT_A::CYC64 + } + #[doc = "Checks if the value of the field is `CYC128`"] + #[inline(always)] + pub fn is_cyc128(&self) -> bool { + *self == PERSELECT_A::CYC128 + } + #[doc = "Checks if the value of the field is `CYC256`"] + #[inline(always)] + pub fn is_cyc256(&self) -> bool { + *self == PERSELECT_A::CYC256 + } + #[doc = "Checks if the value of the field is `CYC512`"] + #[inline(always)] + pub fn is_cyc512(&self) -> bool { + *self == PERSELECT_A::CYC512 + } + #[doc = "Checks if the value of the field is `CYC1024`"] + #[inline(always)] + pub fn is_cyc1024(&self) -> bool { + *self == PERSELECT_A::CYC1024 + } + #[doc = "Checks if the value of the field is `CYC2048`"] + #[inline(always)] + pub fn is_cyc2048(&self) -> bool { + *self == PERSELECT_A::CYC2048 + } + #[doc = "Checks if the value of the field is `CYC4096`"] + #[inline(always)] + pub fn is_cyc4096(&self) -> bool { + *self == PERSELECT_A::CYC4096 + } + #[doc = "Checks if the value of the field is `CYC8192`"] + #[inline(always)] + pub fn is_cyc8192(&self) -> bool { + *self == PERSELECT_A::CYC8192 + } + #[doc = "Checks if the value of the field is `CYC16384`"] + #[inline(always)] + pub fn is_cyc16384(&self) -> bool { + *self == PERSELECT_A::CYC16384 + } +} +#[doc = "Field `PER` writer - Time-Out Period"] +pub type PER_W<'a, const O: u8> = crate::FieldWriter<'a, u8, CONFIG_SPEC, u8, PERSELECT_A, 4, O>; +impl<'a, const O: u8> PER_W<'a, O> { + #[doc = "8 clock cycles"] + #[inline(always)] + pub fn cyc8(self) -> &'a mut W { + self.variant(PERSELECT_A::CYC8) + } + #[doc = "16 clock cycles"] + #[inline(always)] + pub fn cyc16(self) -> &'a mut W { + self.variant(PERSELECT_A::CYC16) + } + #[doc = "32 clock cycles"] + #[inline(always)] + pub fn cyc32(self) -> &'a mut W { + self.variant(PERSELECT_A::CYC32) + } + #[doc = "64 clock cycles"] + #[inline(always)] + pub fn cyc64(self) -> &'a mut W { + self.variant(PERSELECT_A::CYC64) + } + #[doc = "128 clock cycles"] + #[inline(always)] + pub fn cyc128(self) -> &'a mut W { + self.variant(PERSELECT_A::CYC128) + } + #[doc = "256 clock cycles"] + #[inline(always)] + pub fn cyc256(self) -> &'a mut W { + self.variant(PERSELECT_A::CYC256) + } + #[doc = "512 clock cycles"] + #[inline(always)] + pub fn cyc512(self) -> &'a mut W { + self.variant(PERSELECT_A::CYC512) + } + #[doc = "1024 clock cycles"] + #[inline(always)] + pub fn cyc1024(self) -> &'a mut W { + self.variant(PERSELECT_A::CYC1024) + } + #[doc = "2048 clock cycles"] + #[inline(always)] + pub fn cyc2048(self) -> &'a mut W { + self.variant(PERSELECT_A::CYC2048) + } + #[doc = "4096 clock cycles"] + #[inline(always)] + pub fn cyc4096(self) -> &'a mut W { + self.variant(PERSELECT_A::CYC4096) + } + #[doc = "8192 clock cycles"] + #[inline(always)] + pub fn cyc8192(self) -> &'a mut W { + self.variant(PERSELECT_A::CYC8192) + } + #[doc = "16384 clock cycles"] + #[inline(always)] + pub fn cyc16384(self) -> &'a mut W { + self.variant(PERSELECT_A::CYC16384) + } +} +#[doc = "Field `WINDOW` reader - Window Mode Time-Out Period"] +pub type WINDOW_R = crate::FieldReader; +#[doc = "Window Mode Time-Out Period\n\nValue on reset: 11"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum WINDOWSELECT_A { + #[doc = "0: 8 clock cycles"] + CYC8 = 0, + #[doc = "1: 16 clock cycles"] + CYC16 = 1, + #[doc = "2: 32 clock cycles"] + CYC32 = 2, + #[doc = "3: 64 clock cycles"] + CYC64 = 3, + #[doc = "4: 128 clock cycles"] + CYC128 = 4, + #[doc = "5: 256 clock cycles"] + CYC256 = 5, + #[doc = "6: 512 clock cycles"] + CYC512 = 6, + #[doc = "7: 1024 clock cycles"] + CYC1024 = 7, + #[doc = "8: 2048 clock cycles"] + CYC2048 = 8, + #[doc = "9: 4096 clock cycles"] + CYC4096 = 9, + #[doc = "10: 8192 clock cycles"] + CYC8192 = 10, + #[doc = "11: 16384 clock cycles"] + CYC16384 = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: WINDOWSELECT_A) -> Self { + variant as _ + } +} +impl WINDOW_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(WINDOWSELECT_A::CYC8), + 1 => Some(WINDOWSELECT_A::CYC16), + 2 => Some(WINDOWSELECT_A::CYC32), + 3 => Some(WINDOWSELECT_A::CYC64), + 4 => Some(WINDOWSELECT_A::CYC128), + 5 => Some(WINDOWSELECT_A::CYC256), + 6 => Some(WINDOWSELECT_A::CYC512), + 7 => Some(WINDOWSELECT_A::CYC1024), + 8 => Some(WINDOWSELECT_A::CYC2048), + 9 => Some(WINDOWSELECT_A::CYC4096), + 10 => Some(WINDOWSELECT_A::CYC8192), + 11 => Some(WINDOWSELECT_A::CYC16384), + _ => None, + } + } + #[doc = "Checks if the value of the field is `CYC8`"] + #[inline(always)] + pub fn is_cyc8(&self) -> bool { + *self == WINDOWSELECT_A::CYC8 + } + #[doc = "Checks if the value of the field is `CYC16`"] + #[inline(always)] + pub fn is_cyc16(&self) -> bool { + *self == WINDOWSELECT_A::CYC16 + } + #[doc = "Checks if the value of the field is `CYC32`"] + #[inline(always)] + pub fn is_cyc32(&self) -> bool { + *self == WINDOWSELECT_A::CYC32 + } + #[doc = "Checks if the value of the field is `CYC64`"] + #[inline(always)] + pub fn is_cyc64(&self) -> bool { + *self == WINDOWSELECT_A::CYC64 + } + #[doc = "Checks if the value of the field is `CYC128`"] + #[inline(always)] + pub fn is_cyc128(&self) -> bool { + *self == WINDOWSELECT_A::CYC128 + } + #[doc = "Checks if the value of the field is `CYC256`"] + #[inline(always)] + pub fn is_cyc256(&self) -> bool { + *self == WINDOWSELECT_A::CYC256 + } + #[doc = "Checks if the value of the field is `CYC512`"] + #[inline(always)] + pub fn is_cyc512(&self) -> bool { + *self == WINDOWSELECT_A::CYC512 + } + #[doc = "Checks if the value of the field is `CYC1024`"] + #[inline(always)] + pub fn is_cyc1024(&self) -> bool { + *self == WINDOWSELECT_A::CYC1024 + } + #[doc = "Checks if the value of the field is `CYC2048`"] + #[inline(always)] + pub fn is_cyc2048(&self) -> bool { + *self == WINDOWSELECT_A::CYC2048 + } + #[doc = "Checks if the value of the field is `CYC4096`"] + #[inline(always)] + pub fn is_cyc4096(&self) -> bool { + *self == WINDOWSELECT_A::CYC4096 + } + #[doc = "Checks if the value of the field is `CYC8192`"] + #[inline(always)] + pub fn is_cyc8192(&self) -> bool { + *self == WINDOWSELECT_A::CYC8192 + } + #[doc = "Checks if the value of the field is `CYC16384`"] + #[inline(always)] + pub fn is_cyc16384(&self) -> bool { + *self == WINDOWSELECT_A::CYC16384 + } +} +#[doc = "Field `WINDOW` writer - Window Mode Time-Out Period"] +pub type WINDOW_W<'a, const O: u8> = + crate::FieldWriter<'a, u8, CONFIG_SPEC, u8, WINDOWSELECT_A, 4, O>; +impl<'a, const O: u8> WINDOW_W<'a, O> { + #[doc = "8 clock cycles"] + #[inline(always)] + pub fn cyc8(self) -> &'a mut W { + self.variant(WINDOWSELECT_A::CYC8) + } + #[doc = "16 clock cycles"] + #[inline(always)] + pub fn cyc16(self) -> &'a mut W { + self.variant(WINDOWSELECT_A::CYC16) + } + #[doc = "32 clock cycles"] + #[inline(always)] + pub fn cyc32(self) -> &'a mut W { + self.variant(WINDOWSELECT_A::CYC32) + } + #[doc = "64 clock cycles"] + #[inline(always)] + pub fn cyc64(self) -> &'a mut W { + self.variant(WINDOWSELECT_A::CYC64) + } + #[doc = "128 clock cycles"] + #[inline(always)] + pub fn cyc128(self) -> &'a mut W { + self.variant(WINDOWSELECT_A::CYC128) + } + #[doc = "256 clock cycles"] + #[inline(always)] + pub fn cyc256(self) -> &'a mut W { + self.variant(WINDOWSELECT_A::CYC256) + } + #[doc = "512 clock cycles"] + #[inline(always)] + pub fn cyc512(self) -> &'a mut W { + self.variant(WINDOWSELECT_A::CYC512) + } + #[doc = "1024 clock cycles"] + #[inline(always)] + pub fn cyc1024(self) -> &'a mut W { + self.variant(WINDOWSELECT_A::CYC1024) + } + #[doc = "2048 clock cycles"] + #[inline(always)] + pub fn cyc2048(self) -> &'a mut W { + self.variant(WINDOWSELECT_A::CYC2048) + } + #[doc = "4096 clock cycles"] + #[inline(always)] + pub fn cyc4096(self) -> &'a mut W { + self.variant(WINDOWSELECT_A::CYC4096) + } + #[doc = "8192 clock cycles"] + #[inline(always)] + pub fn cyc8192(self) -> &'a mut W { + self.variant(WINDOWSELECT_A::CYC8192) + } + #[doc = "16384 clock cycles"] + #[inline(always)] + pub fn cyc16384(self) -> &'a mut W { + self.variant(WINDOWSELECT_A::CYC16384) + } +} +impl R { + #[doc = "Bits 0:3 - Time-Out Period"] + #[inline(always)] + pub fn per(&self) -> PER_R { + PER_R::new(self.bits & 0x0f) + } + #[doc = "Bits 4:7 - Window Mode Time-Out Period"] + #[inline(always)] + pub fn window(&self) -> WINDOW_R { + WINDOW_R::new((self.bits >> 4) & 0x0f) + } +} +impl W { + #[doc = "Bits 0:3 - Time-Out Period"] + #[inline(always)] + #[must_use] + pub fn per(&mut self) -> PER_W<0> { + PER_W::new(self) + } + #[doc = "Bits 4:7 - Window Mode Time-Out Period"] + #[inline(always)] + #[must_use] + pub fn window(&mut self) -> WINDOW_W<4> { + WINDOW_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Configuration\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [config](index.html) module"] +pub struct CONFIG_SPEC; +impl crate::RegisterSpec for CONFIG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [config::R](R) reader structure"] +impl crate::Readable for CONFIG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [config::W](W) writer structure"] +impl crate::Writable for CONFIG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CONFIG to value 0xbb"] +impl crate::Resettable for CONFIG_SPEC { + const RESET_VALUE: Self::Ux = 0xbb; +} diff --git a/pac/atsaml22j/src/wdt/ctrla.rs b/pac/atsaml22j/src/wdt/ctrla.rs new file mode 100644 index 000000000000..28f8a5144357 --- /dev/null +++ b/pac/atsaml22j/src/wdt/ctrla.rs @@ -0,0 +1,110 @@ +#[doc = "Register `CTRLA` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `CTRLA` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `ENABLE` reader - Enable"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `ENABLE` writer - Enable"] +pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLA_SPEC, bool, O>; +#[doc = "Field `WEN` reader - Watchdog Timer Window Mode Enable"] +pub type WEN_R = crate::BitReader; +#[doc = "Field `WEN` writer - Watchdog Timer Window Mode Enable"] +pub type WEN_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLA_SPEC, bool, O>; +#[doc = "Field `ALWAYSON` reader - Always-On"] +pub type ALWAYSON_R = crate::BitReader; +#[doc = "Field `ALWAYSON` writer - Always-On"] +pub type ALWAYSON_W<'a, const O: u8> = crate::BitWriter<'a, u8, CTRLA_SPEC, bool, O>; +impl R { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Watchdog Timer Window Mode Enable"] + #[inline(always)] + pub fn wen(&self) -> WEN_R { + WEN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 7 - Always-On"] + #[inline(always)] + pub fn alwayson(&self) -> ALWAYSON_R { + ALWAYSON_R::new(((self.bits >> 7) & 1) != 0) + } +} +impl W { + #[doc = "Bit 1 - Enable"] + #[inline(always)] + #[must_use] + pub fn enable(&mut self) -> ENABLE_W<1> { + ENABLE_W::new(self) + } + #[doc = "Bit 2 - Watchdog Timer Window Mode Enable"] + #[inline(always)] + #[must_use] + pub fn wen(&mut self) -> WEN_W<2> { + WEN_W::new(self) + } + #[doc = "Bit 7 - Always-On"] + #[inline(always)] + #[must_use] + pub fn alwayson(&mut self) -> ALWAYSON_W<7> { + ALWAYSON_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"] +pub struct CTRLA_SPEC; +impl crate::RegisterSpec for CTRLA_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ctrla::R](R) reader structure"] +impl crate::Readable for CTRLA_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"] +impl crate::Writable for CTRLA_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets CTRLA to value 0"] +impl crate::Resettable for CTRLA_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/wdt/ewctrl.rs b/pac/atsaml22j/src/wdt/ewctrl.rs new file mode 100644 index 000000000000..9620782c9cb5 --- /dev/null +++ b/pac/atsaml22j/src/wdt/ewctrl.rs @@ -0,0 +1,259 @@ +#[doc = "Register `EWCTRL` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `EWCTRL` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EWOFFSET` reader - Early Warning Interrupt Time Offset"] +pub type EWOFFSET_R = crate::FieldReader; +#[doc = "Early Warning Interrupt Time Offset\n\nValue on reset: 11"] +#[derive(Clone, Copy, Debug, PartialEq, Eq)] +#[repr(u8)] +pub enum EWOFFSETSELECT_A { + #[doc = "0: 8 clock cycles"] + CYC8 = 0, + #[doc = "1: 16 clock cycles"] + CYC16 = 1, + #[doc = "2: 32 clock cycles"] + CYC32 = 2, + #[doc = "3: 64 clock cycles"] + CYC64 = 3, + #[doc = "4: 128 clock cycles"] + CYC128 = 4, + #[doc = "5: 256 clock cycles"] + CYC256 = 5, + #[doc = "6: 512 clock cycles"] + CYC512 = 6, + #[doc = "7: 1024 clock cycles"] + CYC1024 = 7, + #[doc = "8: 2048 clock cycles"] + CYC2048 = 8, + #[doc = "9: 4096 clock cycles"] + CYC4096 = 9, + #[doc = "10: 8192 clock cycles"] + CYC8192 = 10, + #[doc = "11: 16384 clock cycles"] + CYC16384 = 11, +} +impl From for u8 { + #[inline(always)] + fn from(variant: EWOFFSETSELECT_A) -> Self { + variant as _ + } +} +impl EWOFFSET_R { + #[doc = "Get enumerated values variant"] + #[inline(always)] + pub fn variant(&self) -> Option { + match self.bits { + 0 => Some(EWOFFSETSELECT_A::CYC8), + 1 => Some(EWOFFSETSELECT_A::CYC16), + 2 => Some(EWOFFSETSELECT_A::CYC32), + 3 => Some(EWOFFSETSELECT_A::CYC64), + 4 => Some(EWOFFSETSELECT_A::CYC128), + 5 => Some(EWOFFSETSELECT_A::CYC256), + 6 => Some(EWOFFSETSELECT_A::CYC512), + 7 => Some(EWOFFSETSELECT_A::CYC1024), + 8 => Some(EWOFFSETSELECT_A::CYC2048), + 9 => Some(EWOFFSETSELECT_A::CYC4096), + 10 => Some(EWOFFSETSELECT_A::CYC8192), + 11 => Some(EWOFFSETSELECT_A::CYC16384), + _ => None, + } + } + #[doc = "Checks if the value of the field is `CYC8`"] + #[inline(always)] + pub fn is_cyc8(&self) -> bool { + *self == EWOFFSETSELECT_A::CYC8 + } + #[doc = "Checks if the value of the field is `CYC16`"] + #[inline(always)] + pub fn is_cyc16(&self) -> bool { + *self == EWOFFSETSELECT_A::CYC16 + } + #[doc = "Checks if the value of the field is `CYC32`"] + #[inline(always)] + pub fn is_cyc32(&self) -> bool { + *self == EWOFFSETSELECT_A::CYC32 + } + #[doc = "Checks if the value of the field is `CYC64`"] + #[inline(always)] + pub fn is_cyc64(&self) -> bool { + *self == EWOFFSETSELECT_A::CYC64 + } + #[doc = "Checks if the value of the field is `CYC128`"] + #[inline(always)] + pub fn is_cyc128(&self) -> bool { + *self == EWOFFSETSELECT_A::CYC128 + } + #[doc = "Checks if the value of the field is `CYC256`"] + #[inline(always)] + pub fn is_cyc256(&self) -> bool { + *self == EWOFFSETSELECT_A::CYC256 + } + #[doc = "Checks if the value of the field is `CYC512`"] + #[inline(always)] + pub fn is_cyc512(&self) -> bool { + *self == EWOFFSETSELECT_A::CYC512 + } + #[doc = "Checks if the value of the field is `CYC1024`"] + #[inline(always)] + pub fn is_cyc1024(&self) -> bool { + *self == EWOFFSETSELECT_A::CYC1024 + } + #[doc = "Checks if the value of the field is `CYC2048`"] + #[inline(always)] + pub fn is_cyc2048(&self) -> bool { + *self == EWOFFSETSELECT_A::CYC2048 + } + #[doc = "Checks if the value of the field is `CYC4096`"] + #[inline(always)] + pub fn is_cyc4096(&self) -> bool { + *self == EWOFFSETSELECT_A::CYC4096 + } + #[doc = "Checks if the value of the field is `CYC8192`"] + #[inline(always)] + pub fn is_cyc8192(&self) -> bool { + *self == EWOFFSETSELECT_A::CYC8192 + } + #[doc = "Checks if the value of the field is `CYC16384`"] + #[inline(always)] + pub fn is_cyc16384(&self) -> bool { + *self == EWOFFSETSELECT_A::CYC16384 + } +} +#[doc = "Field `EWOFFSET` writer - Early Warning Interrupt Time Offset"] +pub type EWOFFSET_W<'a, const O: u8> = + crate::FieldWriter<'a, u8, EWCTRL_SPEC, u8, EWOFFSETSELECT_A, 4, O>; +impl<'a, const O: u8> EWOFFSET_W<'a, O> { + #[doc = "8 clock cycles"] + #[inline(always)] + pub fn cyc8(self) -> &'a mut W { + self.variant(EWOFFSETSELECT_A::CYC8) + } + #[doc = "16 clock cycles"] + #[inline(always)] + pub fn cyc16(self) -> &'a mut W { + self.variant(EWOFFSETSELECT_A::CYC16) + } + #[doc = "32 clock cycles"] + #[inline(always)] + pub fn cyc32(self) -> &'a mut W { + self.variant(EWOFFSETSELECT_A::CYC32) + } + #[doc = "64 clock cycles"] + #[inline(always)] + pub fn cyc64(self) -> &'a mut W { + self.variant(EWOFFSETSELECT_A::CYC64) + } + #[doc = "128 clock cycles"] + #[inline(always)] + pub fn cyc128(self) -> &'a mut W { + self.variant(EWOFFSETSELECT_A::CYC128) + } + #[doc = "256 clock cycles"] + #[inline(always)] + pub fn cyc256(self) -> &'a mut W { + self.variant(EWOFFSETSELECT_A::CYC256) + } + #[doc = "512 clock cycles"] + #[inline(always)] + pub fn cyc512(self) -> &'a mut W { + self.variant(EWOFFSETSELECT_A::CYC512) + } + #[doc = "1024 clock cycles"] + #[inline(always)] + pub fn cyc1024(self) -> &'a mut W { + self.variant(EWOFFSETSELECT_A::CYC1024) + } + #[doc = "2048 clock cycles"] + #[inline(always)] + pub fn cyc2048(self) -> &'a mut W { + self.variant(EWOFFSETSELECT_A::CYC2048) + } + #[doc = "4096 clock cycles"] + #[inline(always)] + pub fn cyc4096(self) -> &'a mut W { + self.variant(EWOFFSETSELECT_A::CYC4096) + } + #[doc = "8192 clock cycles"] + #[inline(always)] + pub fn cyc8192(self) -> &'a mut W { + self.variant(EWOFFSETSELECT_A::CYC8192) + } + #[doc = "16384 clock cycles"] + #[inline(always)] + pub fn cyc16384(self) -> &'a mut W { + self.variant(EWOFFSETSELECT_A::CYC16384) + } +} +impl R { + #[doc = "Bits 0:3 - Early Warning Interrupt Time Offset"] + #[inline(always)] + pub fn ewoffset(&self) -> EWOFFSET_R { + EWOFFSET_R::new(self.bits & 0x0f) + } +} +impl W { + #[doc = "Bits 0:3 - Early Warning Interrupt Time Offset"] + #[inline(always)] + #[must_use] + pub fn ewoffset(&mut self) -> EWOFFSET_W<0> { + EWOFFSET_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Early Warning Interrupt Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ewctrl](index.html) module"] +pub struct EWCTRL_SPEC; +impl crate::RegisterSpec for EWCTRL_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [ewctrl::R](R) reader structure"] +impl crate::Readable for EWCTRL_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [ewctrl::W](W) writer structure"] +impl crate::Writable for EWCTRL_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets EWCTRL to value 0x0b"] +impl crate::Resettable for EWCTRL_SPEC { + const RESET_VALUE: Self::Ux = 0x0b; +} diff --git a/pac/atsaml22j/src/wdt/intenclr.rs b/pac/atsaml22j/src/wdt/intenclr.rs new file mode 100644 index 000000000000..988c4f5f2e46 --- /dev/null +++ b/pac/atsaml22j/src/wdt/intenclr.rs @@ -0,0 +1,80 @@ +#[doc = "Register `INTENCLR` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENCLR` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EW` reader - Early Warning Interrupt Enable"] +pub type EW_R = crate::BitReader; +#[doc = "Field `EW` writer - Early Warning Interrupt Enable"] +pub type EW_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENCLR_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Early Warning Interrupt Enable"] + #[inline(always)] + pub fn ew(&self) -> EW_R { + EW_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Early Warning Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn ew(&mut self) -> EW_W<0> { + EW_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenclr](index.html) module"] +pub struct INTENCLR_SPEC; +impl crate::RegisterSpec for INTENCLR_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenclr::R](R) reader structure"] +impl crate::Readable for INTENCLR_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenclr::W](W) writer structure"] +impl crate::Writable for INTENCLR_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTENCLR to value 0"] +impl crate::Resettable for INTENCLR_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/wdt/intenset.rs b/pac/atsaml22j/src/wdt/intenset.rs new file mode 100644 index 000000000000..7bcd4b5f8a4c --- /dev/null +++ b/pac/atsaml22j/src/wdt/intenset.rs @@ -0,0 +1,80 @@ +#[doc = "Register `INTENSET` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTENSET` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EW` reader - Early Warning Interrupt Enable"] +pub type EW_R = crate::BitReader; +#[doc = "Field `EW` writer - Early Warning Interrupt Enable"] +pub type EW_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTENSET_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Early Warning Interrupt Enable"] + #[inline(always)] + pub fn ew(&self) -> EW_R { + EW_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Early Warning Interrupt Enable"] + #[inline(always)] + #[must_use] + pub fn ew(&mut self) -> EW_W<0> { + EW_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Enable Set\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intenset](index.html) module"] +pub struct INTENSET_SPEC; +impl crate::RegisterSpec for INTENSET_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intenset::R](R) reader structure"] +impl crate::Readable for INTENSET_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intenset::W](W) writer structure"] +impl crate::Writable for INTENSET_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTENSET to value 0"] +impl crate::Resettable for INTENSET_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/wdt/intflag.rs b/pac/atsaml22j/src/wdt/intflag.rs new file mode 100644 index 000000000000..1006a060bab1 --- /dev/null +++ b/pac/atsaml22j/src/wdt/intflag.rs @@ -0,0 +1,80 @@ +#[doc = "Register `INTFLAG` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Register `INTFLAG` writer"] +pub struct W(crate::W); +impl core::ops::Deref for W { + type Target = crate::W; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl core::ops::DerefMut for W { + #[inline(always)] + fn deref_mut(&mut self) -> &mut Self::Target { + &mut self.0 + } +} +impl From> for W { + #[inline(always)] + fn from(writer: crate::W) -> Self { + W(writer) + } +} +#[doc = "Field `EW` reader - Early Warning"] +pub type EW_R = crate::BitReader; +#[doc = "Field `EW` writer - Early Warning"] +pub type EW_W<'a, const O: u8> = crate::BitWriter<'a, u8, INTFLAG_SPEC, bool, O>; +impl R { + #[doc = "Bit 0 - Early Warning"] + #[inline(always)] + pub fn ew(&self) -> EW_R { + EW_R::new((self.bits & 1) != 0) + } +} +impl W { + #[doc = "Bit 0 - Early Warning"] + #[inline(always)] + #[must_use] + pub fn ew(&mut self) -> EW_W<0> { + EW_W::new(self) + } + #[doc = "Writes raw bits to the register."] + #[inline(always)] + pub unsafe fn bits(&mut self, bits: u8) -> &mut Self { + self.0.bits(bits); + self + } +} +#[doc = "Interrupt Flag Status and Clear\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [intflag](index.html) module"] +pub struct INTFLAG_SPEC; +impl crate::RegisterSpec for INTFLAG_SPEC { + type Ux = u8; +} +#[doc = "`read()` method returns [intflag::R](R) reader structure"] +impl crate::Readable for INTFLAG_SPEC { + type Reader = R; +} +#[doc = "`write(|w| ..)` method takes [intflag::W](W) writer structure"] +impl crate::Writable for INTFLAG_SPEC { + type Writer = W; + const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; + const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0; +} +#[doc = "`reset()` method sets INTFLAG to value 0"] +impl crate::Resettable for INTFLAG_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/pac/atsaml22j/src/wdt/syncbusy.rs b/pac/atsaml22j/src/wdt/syncbusy.rs new file mode 100644 index 000000000000..7a4d939eef18 --- /dev/null +++ b/pac/atsaml22j/src/wdt/syncbusy.rs @@ -0,0 +1,58 @@ +#[doc = "Register `SYNCBUSY` reader"] +pub struct R(crate::R); +impl core::ops::Deref for R { + type Target = crate::R; + #[inline(always)] + fn deref(&self) -> &Self::Target { + &self.0 + } +} +impl From> for R { + #[inline(always)] + fn from(reader: crate::R) -> Self { + R(reader) + } +} +#[doc = "Field `ENABLE` reader - Enable Busy"] +pub type ENABLE_R = crate::BitReader; +#[doc = "Field `WEN` reader - Window Enable Busy"] +pub type WEN_R = crate::BitReader; +#[doc = "Field `ALWAYSON` reader - Always-On Busy"] +pub type ALWAYSON_R = crate::BitReader; +#[doc = "Field `CLEAR` reader - Clear Busy"] +pub type CLEAR_R = crate::BitReader; +impl R { + #[doc = "Bit 1 - Enable Busy"] + #[inline(always)] + pub fn enable(&self) -> ENABLE_R { + ENABLE_R::new(((self.bits >> 1) & 1) != 0) + } + #[doc = "Bit 2 - Window Enable Busy"] + #[inline(always)] + pub fn wen(&self) -> WEN_R { + WEN_R::new(((self.bits >> 2) & 1) != 0) + } + #[doc = "Bit 3 - Always-On Busy"] + #[inline(always)] + pub fn alwayson(&self) -> ALWAYSON_R { + ALWAYSON_R::new(((self.bits >> 3) & 1) != 0) + } + #[doc = "Bit 4 - Clear Busy"] + #[inline(always)] + pub fn clear(&self) -> CLEAR_R { + CLEAR_R::new(((self.bits >> 4) & 1) != 0) + } +} +#[doc = "Synchronization Busy\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [syncbusy](index.html) module"] +pub struct SYNCBUSY_SPEC; +impl crate::RegisterSpec for SYNCBUSY_SPEC { + type Ux = u32; +} +#[doc = "`read()` method returns [syncbusy::R](R) reader structure"] +impl crate::Readable for SYNCBUSY_SPEC { + type Reader = R; +} +#[doc = "`reset()` method sets SYNCBUSY to value 0"] +impl crate::Resettable for SYNCBUSY_SPEC { + const RESET_VALUE: Self::Ux = 0; +} diff --git a/svd/ATSAML22J18A.svd b/svd/ATSAML22J18A.svd new file mode 100644 index 000000000000..d01a5d820998 --- /dev/null +++ b/svd/ATSAML22J18A.svd @@ -0,0 +1,22553 @@ + + + Microchip Technology Inc. + MICROCHIP + ATSAML22J18A + SAML22 + B + Microchip ATSAML22J18A device: Cortex-M0+ Microcontroller with 256KB Flash, 32KB SRAM, 64-pin package + + Copyright (c) 2018 Microchip Technology Inc.\n +\n + SPDX-License-Identifier: Apache-2.0\n +\n + Licensed under the Apache License, Version 2.0 (the "License");\n + you may not use this file except in compliance with the License.\n + You may obtain a copy of the License at\n +\n + http://www.apache.org/licenses/LICENSE-2.0\n +\n + Unless required by applicable law or agreed to in writing, software\n + distributed under the License is distributed on an "AS IS" BASIS,\n + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n + See the License for the specific language governing permissions and\n + limitations under the License. + + + CM0+ + r0p1 + little + true + false + true + 2 + false + 26 + + system_saml22 + 8 + 32 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + AC + 1.0.1 + Analog Comparators + AC + AC_ + 0x42003400 + + 0 + 0x40 + registers + + + AC + 21 + + + + CTRLA + Control A + 0x00 + 8 + + + SWRST + Software Reset + 0 + 1 + write-only + + + ENABLE + Enable + 1 + 1 + + + + + CTRLB + Control B + 0x01 + 8 + write-only + + + START0 + Comparator 0 Start Comparison + 0 + 1 + + + START1 + Comparator 1 Start Comparison + 1 + 1 + + + + + EVCTRL + Event Control + 0x02 + 16 + + + COMPEO0 + Comparator 0 Event Output Enable + 0 + 1 + + + COMPEO1 + Comparator 1 Event Output Enable + 1 + 1 + + + WINEO0 + Window 0 Event Output Enable + 4 + 1 + + + COMPEI0 + Comparator 0 Event Input Enable + 8 + 1 + + + COMPEI1 + Comparator 1 Event Input Enable + 9 + 1 + + + INVEI0 + Comparator 0 Input Event Invert Enable + 12 + 1 + + + INVEI1 + Comparator 1 Input Event Invert Enable + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x04 + 8 + + + COMP0 + Comparator 0 Interrupt Enable + 0 + 1 + + + COMP1 + Comparator 1 Interrupt Enable + 1 + 1 + + + WIN0 + Window 0 Interrupt Enable + 4 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x05 + 8 + + + COMP0 + Comparator 0 Interrupt Enable + 0 + 1 + + + COMP1 + Comparator 1 Interrupt Enable + 1 + 1 + + + WIN0 + Window 0 Interrupt Enable + 4 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x06 + 8 + + + COMP0 + Comparator 0 + 0 + 1 + + + COMP1 + Comparator 1 + 1 + 1 + + + WIN0 + Window 0 + 4 + 1 + + + + + STATUSA + Status A + 0x07 + 8 + read-only + + + STATE0 + Comparator 0 Current State + 0 + 1 + read-only + + + STATE1 + Comparator 1 Current State + 1 + 1 + read-only + + + WSTATE0 + Window 0 Current State + 4 + 2 + read-only + + WSTATE0Select + + ABOVE + Signal is above window + 0x0 + + + INSIDE + Signal is inside window + 0x1 + + + BELOW + Signal is below window + 0x2 + + + + + + + STATUSB + Status B + 0x08 + 8 + read-only + + + READY0 + Comparator 0 Ready + 0 + 1 + read-only + + + READY1 + Comparator 1 Ready + 1 + 1 + read-only + + + + + DBGCTRL + Debug Control + 0x09 + 8 + + + DBGRUN + Debug Run + 0 + 1 + + + + + WINCTRL + Window Control + 0x0A + 8 + + + WEN0 + Window 0 Mode Enable + 0 + 1 + + + WINTSEL0 + Window 0 Interrupt Selection + 1 + 2 + + WINTSEL0Select + + ABOVE + Interrupt on signal above window + 0x0 + + + INSIDE + Interrupt on signal inside window + 0x1 + + + BELOW + Interrupt on signal below window + 0x2 + + + OUTSIDE + Interrupt on signal outside window + 0x3 + + + + + + + 2 + 0x1 + SCALER%s + Scaler n + 0x0C + 8 + + + VALUE + Scaler Value + 0 + 6 + + + + + 2 + 0x4 + COMPCTRL%s + Comparator Control n + 0x10 + 32 + + + ENABLE + Enable + 1 + 1 + + + SINGLE + Single-Shot Mode + 2 + 1 + + + INTSEL + Interrupt Selection + 3 + 2 + + INTSELSelect + + TOGGLE + Interrupt on comparator output toggle + 0x0 + + + RISING + Interrupt on comparator output rising + 0x1 + + + FALLING + Interrupt on comparator output falling + 0x2 + + + EOC + Interrupt on end of comparison (single-shot mode only) + 0x3 + + + + + RUNSTDBY + Run in Standby + 6 + 1 + + + MUXNEG + Negative Input Mux Selection + 8 + 3 + + MUXNEGSelect + + PIN0 + I/O pin 0 + 0x0 + + + PIN1 + I/O pin 1 + 0x1 + + + PIN2 + I/O pin 2 + 0x2 + + + PIN3 + I/O pin 3 + 0x3 + + + GND + Ground + 0x4 + + + VSCALE + VDD scaler + 0x5 + + + BANDGAP + Internal bandgap voltage + 0x6 + + + DAC + DAC output + 0x7 + + + + + MUXPOS + Positive Input Mux Selection + 12 + 3 + + MUXPOSSelect + + PIN0 + I/O pin 0 + 0x0 + + + PIN1 + I/O pin 1 + 0x1 + + + PIN2 + I/O pin 2 + 0x2 + + + PIN3 + I/O pin 3 + 0x3 + + + VSCALE + VDD Scaler + 0x4 + + + + + SWAP + Swap Inputs and Invert + 15 + 1 + + + SPEED + Speed Selection + 16 + 2 + + SPEEDSelect + + LOW + Low speed + 0x0 + + + MEDLOW + Medium low speed + 0x1 + + + MEDHIGH + Medium high speed + 0x2 + + + HIGH + High speed + 0x3 + + + + + HYSTEN + Hysteresis Enable + 19 + 1 + + + HYST + Hysteresis Level + 20 + 2 + + HYSTSelect + + HYST50 + 50mV + 0x0 + + + HYST70 + 70mV + 0x1 + + + HYST90 + 90mV + 0x2 + + + HYST110 + 110mV + 0x3 + + + + + FLEN + Filter Length + 24 + 3 + + FLENSelect + + OFF + No filtering + 0x0 + + + MAJ3 + 3-bit majority function (2 of 3) + 0x1 + + + MAJ5 + 5-bit majority function (3 of 5) + 0x2 + + + + + OUT + Output + 28 + 2 + + OUTSelect + + OFF + The output of COMPn is not routed to the COMPn I/O port + 0x0 + + + ASYNC + The asynchronous output of COMPn is routed to the COMPn I/O port + 0x1 + + + SYNC + The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port + 0x2 + + + + + + + SYNCBUSY + Synchronization Busy + 0x20 + 32 + read-only + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + read-only + + + ENABLE + Enable Synchronization Busy + 1 + 1 + read-only + + + WINCTRL + WINCTRL Synchronization Busy + 2 + 1 + read-only + + + COMPCTRL0 + COMPCTRL 0 Synchronization Busy + 3 + 1 + read-only + + + COMPCTRL1 + COMPCTRL 1 Synchronization Busy + 4 + 1 + read-only + + + + + + + ADC + 2.1.0 + Analog Digital Converter + ADC + ADC_ + 0x42003000 + + 0 + 0x80 + registers + + + ADC + 20 + + + + CTRLA + Control A + 0x00 + 8 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run During Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + + + CTRLB + Control B + 0x01 + 8 + + + PRESCALER + Prescaler Configuration + 0 + 3 + + PRESCALERSelect + + DIV2 + Peripheral clock divided by 2 + 0x0 + + + DIV4 + Peripheral clock divided by 4 + 0x1 + + + DIV8 + Peripheral clock divided by 8 + 0x2 + + + DIV16 + Peripheral clock divided by 16 + 0x3 + + + DIV32 + Peripheral clock divided by 32 + 0x4 + + + DIV64 + Peripheral clock divided by 64 + 0x5 + + + DIV128 + Peripheral clock divided by 128 + 0x6 + + + DIV256 + Peripheral clock divided by 256 + 0x7 + + + + + + + REFCTRL + Reference Control + 0x02 + 8 + + + REFSEL + Reference Selection + 0 + 4 + + REFSELSelect + + INTREF + Internal Bandgap Reference + 0x0 + + + INTVCC0 + 1/1.6 VDDANA + 0x1 + + + INTVCC1 + 1/2 VDDANA + 0x2 + + + AREFA + External Reference + 0x3 + + + AREFB + External Reference + 0x4 + + + INTVCC2 + VCCANA + 0x5 + + + + + REFCOMP + Reference Buffer Offset Compensation Enable + 7 + 1 + + + + + EVCTRL + Event Control + 0x03 + 8 + + + FLUSHEI + Flush Event Input Enable + 0 + 1 + + + STARTEI + Start Conversion Event Input Enable + 1 + 1 + + + FLUSHINV + Flush Event Invert Enable + 2 + 1 + + + STARTINV + Satrt Event Invert Enable + 3 + 1 + + + RESRDYEO + Result Ready Event Out + 4 + 1 + + + WINMONEO + Window Monitor Event Out + 5 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x04 + 8 + + + RESRDY + Result Ready Interrupt Disable + 0 + 1 + + + OVERRUN + Overrun Interrupt Disable + 1 + 1 + + + WINMON + Window Monitor Interrupt Disable + 2 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x05 + 8 + + + RESRDY + Result Ready Interrupt Enable + 0 + 1 + + + OVERRUN + Overrun Interrupt Enable + 1 + 1 + + + WINMON + Window Monitor Interrupt Enable + 2 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x06 + 8 + + + RESRDY + Result Ready Interrupt Flag + 0 + 1 + + + OVERRUN + Overrun Interrupt Flag + 1 + 1 + + + WINMON + Window Monitor Interrupt Flag + 2 + 1 + + + + + SEQSTATUS + Sequence Status + 0x07 + 8 + read-only + + + SEQSTATE + Sequence State + 0 + 5 + read-only + + + SEQBUSY + Sequence Busy + 7 + 1 + read-only + + + + + INPUTCTRL + Input Control + 0x08 + 16 + + + MUXPOS + Positive Mux Input Selection + 0 + 5 + + MUXPOSSelect + + AIN0 + ADC AIN0 Pin + 0x0 + + + AIN1 + ADC AIN1 Pin + 0x1 + + + AIN2 + ADC AIN2 Pin + 0x2 + + + AIN3 + ADC AIN3 Pin + 0x3 + + + AIN4 + ADC AIN4 Pin + 0x4 + + + AIN5 + ADC AIN5 Pin + 0x5 + + + AIN6 + ADC AIN6 Pin + 0x6 + + + AIN7 + ADC AIN7 Pin + 0x7 + + + AIN8 + ADC AIN8 Pin + 0x8 + + + AIN9 + ADC AIN9 Pin + 0x9 + + + AIN10 + ADC AIN10 Pin + 0xa + + + AIN11 + ADC AIN11 Pin + 0xb + + + AIN12 + ADC AIN12 Pin + 0xc + + + AIN13 + ADC AIN13 Pin + 0xd + + + AIN14 + ADC AIN14 Pin + 0xe + + + AIN15 + ADC AIN15 Pin + 0xf + + + AIN16 + ADC AIN16 Pin + 0x10 + + + AIN17 + ADC AIN17 Pin + 0x11 + + + AIN18 + ADC AIN18 Pin + 0x12 + + + AIN19 + ADC AIN19 Pin + 0x13 + + + TEMP + Temperature Sensor + 0x18 + + + BANDGAP + Bandgap Voltage + 0x19 + + + SCALEDCOREVCC + 1/4 Scaled Core Supply + 0x1a + + + SCALEDIOVCC + 1/4 Scaled I/O Supply + 0x1b + + + SCALEDVBAT + 1/4 Scaled VBAT Supply + 0x1d + + + CTAT + CTAT output + 0x1e + + + + + MUXNEG + Negative Mux Input Selection + 8 + 5 + + MUXNEGSelect + + AIN0 + ADC AIN0 Pin + 0x0 + + + AIN1 + ADC AIN1 Pin + 0x1 + + + AIN2 + ADC AIN2 Pin + 0x2 + + + AIN3 + ADC AIN3 Pin + 0x3 + + + AIN4 + ADC AIN4 Pin + 0x4 + + + AIN5 + ADC AIN5 Pin + 0x5 + + + AIN6 + ADC AIN6 Pin + 0x6 + + + AIN7 + ADC AIN7 Pin + 0x7 + + + + + + + CTRLC + Control C + 0x0A + 16 + + + DIFFMODE + Differential Mode + 0 + 1 + + + LEFTADJ + Left-Adjusted Result + 1 + 1 + + + FREERUN + Free Running Mode + 2 + 1 + + + CORREN + Digital Correction Logic Enable + 3 + 1 + + + RESSEL + Conversion Result Resolution + 4 + 2 + + RESSELSelect + + 12BIT + 12-bit result + 0x0 + + + 16BIT + For averaging mode output + 0x1 + + + 10BIT + 10-bit result + 0x2 + + + 8BIT + 8-bit result + 0x3 + + + + + R2R + Rail-to-Rail mode enable + 7 + 1 + + + WINMODE + Window Monitor Mode + 8 + 3 + + WINMODESelect + + DISABLE + No window mode (default) + 0x0 + + + MODE1 + RESULT > WINLT + 0x1 + + + MODE2 + RESULT < WINUT + 0x2 + + + MODE3 + WINLT < RESULT < WINUT + 0x3 + + + MODE4 + !(WINLT < RESULT < WINUT) + 0x4 + + + + + DUALSEL + Dual Mode Trigger Selection + 12 + 2 + + DUALSELSelect + + BOTH + Start event or software trigger will start a conversion on both ADCs + 0x0 + + + INTERLEAVE + START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 + 0x1 + + + + + + + AVGCTRL + Average Control + 0x0C + 8 + + + SAMPLENUM + Number of Samples to be Collected + 0 + 4 + + SAMPLENUMSelect + + 1 + 1 sample + 0x0 + + + 2 + 2 samples + 0x1 + + + 4 + 4 samples + 0x2 + + + 8 + 8 samples + 0x3 + + + 16 + 16 samples + 0x4 + + + 32 + 32 samples + 0x5 + + + 64 + 64 samples + 0x6 + + + 128 + 128 samples + 0x7 + + + 256 + 256 samples + 0x8 + + + 512 + 512 samples + 0x9 + + + 1024 + 1024 samples + 0xa + + + + + ADJRES + Adjusting Result / Division Coefficient + 4 + 3 + + + + + SAMPCTRL + Sample Time Control + 0x0D + 8 + + + SAMPLEN + Sampling Time Length + 0 + 6 + + + OFFCOMP + Comparator Offset Compensation Enable + 7 + 1 + + + + + WINLT + Window Monitor Lower Threshold + 0x0E + 16 + + + WINLT + Window Lower Threshold + 0 + 16 + + + + + WINUT + Window Monitor Upper Threshold + 0x10 + 16 + + + WINUT + Window Upper Threshold + 0 + 16 + + + + + GAINCORR + Gain Correction + 0x12 + 16 + + + GAINCORR + Gain Correction Value + 0 + 12 + + + + + OFFSETCORR + Offset Correction + 0x14 + 16 + + + OFFSETCORR + Offset Correction Value + 0 + 12 + + + + + SWTRIG + Software Trigger + 0x18 + 8 + + + FLUSH + ADC Flush + 0 + 1 + + + START + Start ADC Conversion + 1 + 1 + + + + + DBGCTRL + Debug Control + 0x1C + 8 + + + DBGRUN + Debug Run + 0 + 1 + + + + + SYNCBUSY + Synchronization Busy + 0x20 + 16 + read-only + + + SWRST + SWRST Synchronization Busy + 0 + 1 + read-only + + + ENABLE + ENABLE Synchronization Busy + 1 + 1 + read-only + + + INPUTCTRL + INPUTCTRL Synchronization Busy + 2 + 1 + read-only + + + CTRLC + CTRLC Synchronization Busy + 3 + 1 + read-only + + + AVGCTRL + AVGCTRL Synchronization Busy + 4 + 1 + read-only + + + SAMPCTRL + SAMPCTRL Synchronization Busy + 5 + 1 + read-only + + + WINLT + WINLT Synchronization Busy + 6 + 1 + read-only + + + WINUT + WINUT Synchronization Busy + 7 + 1 + read-only + + + GAINCORR + GAINCORR Synchronization Busy + 8 + 1 + read-only + + + OFFSETCORR + OFFSETCTRL Synchronization Busy + 9 + 1 + read-only + + + SWTRIG + SWTRG Synchronization Busy + 10 + 1 + read-only + + + + + RESULT + Result + 0x24 + 16 + read-only + + + RESULT + Result Value + 0 + 16 + read-only + + + + + SEQCTRL + Sequence Control + 0x28 + 32 + + + SEQEN + Enable Positive Input in the Sequence + 0 + 32 + + + + + CALIB + Calibration + 0x2C + 16 + + + BIASCOMP + Bias Comparator Scaling + 0 + 3 + + + BIASREFBUF + Bias Reference Buffer Scaling + 8 + 3 + + + + + + + AES + 2.1.0 + Advanced Encryption Standard + AES + AES_ + 0x42004000 + + 0 + 0x100 + registers + + + AES + 24 + + + + CTRLA + Control A + 0x00 + 32 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + AESMODE + AES Modes of operation + 2 + 3 + + + CFBS + CFB Types + 5 + 3 + + + KEYSIZE + Keysize + 8 + 2 + + + CIPHER + Cipher mode + 10 + 1 + + + STARTMODE + Start mode + 11 + 1 + + + LOD + LOD Enable + 12 + 1 + + + KEYGEN + Last key generation + 13 + 1 + + + XORKEY + Xor Key operation + 14 + 1 + + + CTYPE + Counter measure types + 16 + 4 + + + + + CTRLB + Control B + 0x04 + 8 + + + START + Manual Start + 0 + 1 + + + NEWMSG + New message + 1 + 1 + + + EOM + End of message + 2 + 1 + + + GFMUL + GF Multiplication + 3 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x05 + 8 + + + ENCCMP + Encryption Complete + 0 + 1 + + + GFMCMP + GF Multiplication Complete + 1 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x06 + 8 + + + ENCCMP + Encryption Complete + 0 + 1 + + + GFMCMP + GF Multiplication Complete + 1 + 1 + + + + + INTFLAG + Interrupt Flag Status + 0x07 + 8 + + + ENCCMP + Encryption Complete + 0 + 1 + + + GFMCMP + GF Multiplication Complete + 1 + 1 + + + + + DATABUFPTR + Data buffer pointer + 0x08 + 8 + + + INDATAPTR + Input Data Pointer + 0 + 2 + + + + + DBGCTRL + Debug control + 0x09 + 8 + write-only + + + DBGRUN + Debug Run + 0 + 1 + + + + + 8 + 0x4 + KEYWORD%s + Keyword n + 0x0C + 32 + write-only + + + INDATA + Indata + 0x38 + 32 + + + 4 + 0x4 + INTVECTV%s + Initialisation Vector n + 0x3C + 32 + write-only + + + 4 + 0x4 + HASHKEY%s + Hash key n + 0x5C + 32 + + + 4 + 0x4 + GHASH%s + Galois Hash n + 0x6C + 32 + + + CIPLEN + Cipher Length + 0x80 + 32 + + + RANDSEED + Random Seed + 0x84 + 32 + + + + + CCL + 1.0.1 + Configurable Custom Logic + CCL + CCL_ + 0x42004800 + + 0 + 0x40 + registers + + + + CTRL + Control + 0x0 + 8 + + + SWRST + Software Reset + 0 + 1 + write-only + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run during Standby + 6 + 1 + + + + + 2 + 0x1 + SEQCTRL%s + SEQ Control x + 0x4 + 8 + + + SEQSEL + Sequential Selection + 0 + 4 + + SEQSELSelect + + DISABLE + Sequential logic is disabled + 0x0 + + + DFF + D flip flop + 0x1 + + + JK + JK flip flop + 0x2 + + + LATCH + D latch + 0x3 + + + RS + RS latch + 0x4 + + + + + + + 4 + 0x4 + LUTCTRL%s + LUT Control x + 0x8 + 32 + + + ENABLE + LUT Enable + 1 + 1 + + + FILTSEL + Filter Selection + 4 + 2 + + FILTSELSelect + + DISABLE + Filter disabled + 0x0 + + + SYNCH + Synchronizer enabled + 0x1 + + + FILTER + Filter enabled + 0x2 + + + + + EDGESEL + Edge Selection + 7 + 1 + + + INSEL0 + Input Selection 0 + 8 + 4 + + INSEL0Select + + MASK + Masked input + 0x0 + + + FEEDBACK + Feedback input source + 0x1 + + + LINK + Linked LUT input source + 0x2 + + + EVENT + Event in put source + 0x3 + + + IO + I/O pin input source + 0x4 + + + AC + AC input source + 0x5 + + + TC + TC input source + 0x6 + + + ALTTC + Alternate TC input source + 0x7 + + + TCC + TCC input source + 0x8 + + + SERCOM + SERCOM inout source + 0x9 + + + + + INSEL1 + Input Selection 1 + 12 + 4 + + + INSEL2 + Input Selection 2 + 16 + 4 + + + INVEI + Input Event Invert + 20 + 1 + + + LUTEI + Event Input Enable + 21 + 1 + + + LUTEO + Event Output Enable + 22 + 1 + + + TRUTH + Truth Value + 24 + 8 + + + + + + + DMAC + 2.2.2 + Direct Memory Access Controller + DMAC + DMAC_ + 0x41008000 + + 0 + 0x80 + registers + + + DMAC + 7 + + + + CTRL + Control + 0x00 + 16 + + + SWRST + Software Reset + 0 + 1 + + + DMAENABLE + DMA Enable + 1 + 1 + + + CRCENABLE + CRC Enable + 2 + 1 + + + LVLEN0 + Priority Level 0 Enable + 8 + 1 + + + LVLEN1 + Priority Level 1 Enable + 9 + 1 + + + LVLEN2 + Priority Level 2 Enable + 10 + 1 + + + LVLEN3 + Priority Level 3 Enable + 11 + 1 + + + + + CRCCTRL + CRC Control + 0x02 + 16 + + + CRCBEATSIZE + CRC Beat Size + 0 + 2 + + CRCBEATSIZESelect + + BYTE + 8-bit bus transfer + 0x0 + + + HWORD + 16-bit bus transfer + 0x1 + + + WORD + 32-bit bus transfer + 0x2 + + + + + CRCPOLY + CRC Polynomial Type + 2 + 2 + + CRCPOLYSelect + + CRC16 + CRC-16 (CRC-CCITT) + 0x0 + + + CRC32 + CRC32 (IEEE 802.3) + 0x1 + + + + + CRCSRC + CRC Input Source + 8 + 6 + + CRCSRCSelect + + NOACT + No action + 0x0 + + + IO + I/O interface + 0x1 + + + + + + + CRCDATAIN + CRC Data Input + 0x04 + 32 + + + CRCDATAIN + CRC Data Input + 0 + 32 + + + + + CRCCHKSUM + CRC Checksum + 0x08 + 32 + + + CRCCHKSUM + CRC Checksum + 0 + 32 + + + + + CRCSTATUS + CRC Status + 0x0C + 8 + + + CRCBUSY + CRC Module Busy + 0 + 1 + + + CRCZERO + CRC Zero + 1 + 1 + read-only + + + + + DBGCTRL + Debug Control + 0x0D + 8 + + + DBGRUN + Debug Run + 0 + 1 + + + + + QOSCTRL + QOS Control + 0x0E + 8 + 0x2A + + + WRBQOS + Write-Back Quality of Service + 0 + 2 + + WRBQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + FQOS + Fetch Quality of Service + 2 + 2 + + FQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + DQOS + Data Transfer Quality of Service + 4 + 2 + + DQOSSelect + + DISABLE + Background (no sensitive operation) + 0x0 + + + LOW + Sensitive Bandwidth + 0x1 + + + MEDIUM + Sensitive Latency + 0x2 + + + HIGH + Critical Latency + 0x3 + + + + + + + SWTRIGCTRL + Software Trigger Control + 0x10 + 32 + + + SWTRIG0 + Channel 0 Software Trigger + 0 + 1 + + + SWTRIG1 + Channel 1 Software Trigger + 1 + 1 + + + SWTRIG2 + Channel 2 Software Trigger + 2 + 1 + + + SWTRIG3 + Channel 3 Software Trigger + 3 + 1 + + + SWTRIG4 + Channel 4 Software Trigger + 4 + 1 + + + SWTRIG5 + Channel 5 Software Trigger + 5 + 1 + + + SWTRIG6 + Channel 6 Software Trigger + 6 + 1 + + + SWTRIG7 + Channel 7 Software Trigger + 7 + 1 + + + SWTRIG8 + Channel 8 Software Trigger + 8 + 1 + + + SWTRIG9 + Channel 9 Software Trigger + 9 + 1 + + + SWTRIG10 + Channel 10 Software Trigger + 10 + 1 + + + SWTRIG11 + Channel 11 Software Trigger + 11 + 1 + + + SWTRIG12 + Channel 12 Software Trigger + 12 + 1 + + + SWTRIG13 + Channel 13 Software Trigger + 13 + 1 + + + SWTRIG14 + Channel 14 Software Trigger + 14 + 1 + + + SWTRIG15 + Channel 15 Software Trigger + 15 + 1 + + + + + PRICTRL0 + Priority Control 0 + 0x14 + 32 + + + LVLPRI0 + Level 0 Channel Priority Number + 0 + 4 + + + RRLVLEN0 + Level 0 Round-Robin Scheduling Enable + 7 + 1 + + + LVLPRI1 + Level 1 Channel Priority Number + 8 + 4 + + + RRLVLEN1 + Level 1 Round-Robin Scheduling Enable + 15 + 1 + + + LVLPRI2 + Level 2 Channel Priority Number + 16 + 4 + + + RRLVLEN2 + Level 2 Round-Robin Scheduling Enable + 23 + 1 + + + LVLPRI3 + Level 3 Channel Priority Number + 24 + 4 + + + RRLVLEN3 + Level 3 Round-Robin Scheduling Enable + 31 + 1 + + + + + INTPEND + Interrupt Pending + 0x20 + 16 + + + ID + Channel ID + 0 + 4 + + + TERR + Transfer Error + 8 + 1 + + + TCMPL + Transfer Complete + 9 + 1 + + + SUSP + Channel Suspend + 10 + 1 + + + FERR + Fetch Error + 13 + 1 + read-only + + + BUSY + Busy + 14 + 1 + read-only + + + PEND + Pending + 15 + 1 + read-only + + + + + INTSTATUS + Interrupt Status + 0x24 + 32 + read-only + + + CHINT0 + Channel 0 Pending Interrupt + 0 + 1 + read-only + + + CHINT1 + Channel 1 Pending Interrupt + 1 + 1 + read-only + + + CHINT2 + Channel 2 Pending Interrupt + 2 + 1 + read-only + + + CHINT3 + Channel 3 Pending Interrupt + 3 + 1 + read-only + + + CHINT4 + Channel 4 Pending Interrupt + 4 + 1 + read-only + + + CHINT5 + Channel 5 Pending Interrupt + 5 + 1 + read-only + + + CHINT6 + Channel 6 Pending Interrupt + 6 + 1 + read-only + + + CHINT7 + Channel 7 Pending Interrupt + 7 + 1 + read-only + + + CHINT8 + Channel 8 Pending Interrupt + 8 + 1 + read-only + + + CHINT9 + Channel 9 Pending Interrupt + 9 + 1 + read-only + + + CHINT10 + Channel 10 Pending Interrupt + 10 + 1 + read-only + + + CHINT11 + Channel 11 Pending Interrupt + 11 + 1 + read-only + + + CHINT12 + Channel 12 Pending Interrupt + 12 + 1 + read-only + + + CHINT13 + Channel 13 Pending Interrupt + 13 + 1 + read-only + + + CHINT14 + Channel 14 Pending Interrupt + 14 + 1 + read-only + + + CHINT15 + Channel 15 Pending Interrupt + 15 + 1 + read-only + + + + + BUSYCH + Busy Channels + 0x28 + 32 + read-only + + + BUSYCH0 + Busy Channel 0 + 0 + 1 + read-only + + + BUSYCH1 + Busy Channel 1 + 1 + 1 + read-only + + + BUSYCH2 + Busy Channel 2 + 2 + 1 + read-only + + + BUSYCH3 + Busy Channel 3 + 3 + 1 + read-only + + + BUSYCH4 + Busy Channel 4 + 4 + 1 + read-only + + + BUSYCH5 + Busy Channel 5 + 5 + 1 + read-only + + + BUSYCH6 + Busy Channel 6 + 6 + 1 + read-only + + + BUSYCH7 + Busy Channel 7 + 7 + 1 + read-only + + + BUSYCH8 + Busy Channel 8 + 8 + 1 + read-only + + + BUSYCH9 + Busy Channel 9 + 9 + 1 + read-only + + + BUSYCH10 + Busy Channel 10 + 10 + 1 + read-only + + + BUSYCH11 + Busy Channel 11 + 11 + 1 + read-only + + + BUSYCH12 + Busy Channel 12 + 12 + 1 + read-only + + + BUSYCH13 + Busy Channel 13 + 13 + 1 + read-only + + + BUSYCH14 + Busy Channel 14 + 14 + 1 + read-only + + + BUSYCH15 + Busy Channel 15 + 15 + 1 + read-only + + + + + PENDCH + Pending Channels + 0x2C + 32 + read-only + + + PENDCH0 + Pending Channel 0 + 0 + 1 + read-only + + + PENDCH1 + Pending Channel 1 + 1 + 1 + read-only + + + PENDCH2 + Pending Channel 2 + 2 + 1 + read-only + + + PENDCH3 + Pending Channel 3 + 3 + 1 + read-only + + + PENDCH4 + Pending Channel 4 + 4 + 1 + read-only + + + PENDCH5 + Pending Channel 5 + 5 + 1 + read-only + + + PENDCH6 + Pending Channel 6 + 6 + 1 + read-only + + + PENDCH7 + Pending Channel 7 + 7 + 1 + read-only + + + PENDCH8 + Pending Channel 8 + 8 + 1 + read-only + + + PENDCH9 + Pending Channel 9 + 9 + 1 + read-only + + + PENDCH10 + Pending Channel 10 + 10 + 1 + read-only + + + PENDCH11 + Pending Channel 11 + 11 + 1 + read-only + + + PENDCH12 + Pending Channel 12 + 12 + 1 + read-only + + + PENDCH13 + Pending Channel 13 + 13 + 1 + read-only + + + PENDCH14 + Pending Channel 14 + 14 + 1 + read-only + + + PENDCH15 + Pending Channel 15 + 15 + 1 + read-only + + + + + ACTIVE + Active Channel and Levels + 0x30 + 32 + read-only + + + LVLEX0 + Level 0 Channel Trigger Request Executing + 0 + 1 + read-only + + + LVLEX1 + Level 1 Channel Trigger Request Executing + 1 + 1 + read-only + + + LVLEX2 + Level 2 Channel Trigger Request Executing + 2 + 1 + read-only + + + LVLEX3 + Level 3 Channel Trigger Request Executing + 3 + 1 + read-only + + + ID + Active Channel ID + 8 + 5 + read-only + + + ABUSY + Active Channel Busy + 15 + 1 + read-only + + + BTCNT + Active Channel Block Transfer Count + 16 + 16 + read-only + + + + + BASEADDR + Descriptor Memory Section Base Address + 0x34 + 32 + + + BASEADDR + Descriptor Memory Base Address + 0 + 32 + + + + + WRBADDR + Write-Back Memory Section Base Address + 0x38 + 32 + + + WRBADDR + Write-Back Memory Base Address + 0 + 32 + + + + + CHID + Channel ID + 0x3F + 8 + + + ID + Channel ID + 0 + 4 + + + + + CHCTRLA + Channel Control A + 0x40 + 8 + + + SWRST + Channel Software Reset + 0 + 1 + + + ENABLE + Channel Enable + 1 + 1 + + + RUNSTDBY + Channel run in standby + 6 + 1 + + + + + CHCTRLB + Channel Control B + 0x44 + 32 + + + EVACT + Event Input Action + 0 + 3 + + EVACTSelect + + NOACT + No action + 0x0 + + + TRIG + Transfer and periodic transfer trigger + 0x1 + + + CTRIG + Conditional transfer trigger + 0x2 + + + CBLOCK + Conditional block transfer + 0x3 + + + SUSPEND + Channel suspend operation + 0x4 + + + RESUME + Channel resume operation + 0x5 + + + SSKIP + Skip next block suspend action + 0x6 + + + + + EVIE + Channel Event Input Enable + 3 + 1 + + + EVOE + Channel Event Output Enable + 4 + 1 + + + LVL + Channel Arbitration Level + 5 + 2 + + + TRIGSRC + Trigger Source + 8 + 6 + + TRIGSRCSelect + + DISABLE + Only software/event triggers + 0x0 + + + + + TRIGACT + Trigger Action + 22 + 2 + + TRIGACTSelect + + BLOCK + One trigger required for each block transfer + 0x0 + + + BEAT + One trigger required for each beat transfer + 0x2 + + + TRANSACTION + One trigger required for each transaction + 0x3 + + + + + CMD + Software Command + 24 + 2 + + CMDSelect + + NOACT + No action + 0x0 + + + SUSPEND + Channel suspend operation + 0x1 + + + RESUME + Channel resume operation + 0x2 + + + + + + + CHINTENCLR + Channel Interrupt Enable Clear + 0x4C + 8 + + + TERR + Channel Transfer Error Interrupt Enable + 0 + 1 + + + TCMPL + Channel Transfer Complete Interrupt Enable + 1 + 1 + + + SUSP + Channel Suspend Interrupt Enable + 2 + 1 + + + + + CHINTENSET + Channel Interrupt Enable Set + 0x4D + 8 + + + TERR + Channel Transfer Error Interrupt Enable + 0 + 1 + + + TCMPL + Channel Transfer Complete Interrupt Enable + 1 + 1 + + + SUSP + Channel Suspend Interrupt Enable + 2 + 1 + + + + + CHINTFLAG + Channel Interrupt Flag Status and Clear + 0x4E + 8 + + + TERR + Channel Transfer Error + 0 + 1 + + + TCMPL + Channel Transfer Complete + 1 + 1 + + + SUSP + Channel Suspend + 2 + 1 + + + + + CHSTATUS + Channel Status + 0x4F + 8 + read-only + + + PEND + Channel Pending + 0 + 1 + read-only + + + BUSY + Channel Busy + 1 + 1 + read-only + + + FERR + Channel Fetch Error + 2 + 1 + read-only + + + + + + + DSU + 2.5.0.1 + Device Service Unit + DSU + DSU_ + 0x41002000 + + 0 + 0x2000 + registers + + + + CTRL + Control + 0x0000 + 8 + write-only + + + SWRST + Software Reset + 0 + 1 + write-only + + + CRC + 32-bit Cyclic Redundancy Code + 2 + 1 + write-only + + + MBIST + Memory built-in self-test + 3 + 1 + write-only + + + CE + Chip-Erase + 4 + 1 + write-only + + + ARR + Auxiliary Row Read + 6 + 1 + write-only + + + SMSA + Start Memory Stream Access + 7 + 1 + write-only + + + + + STATUSA + Status A + 0x0001 + 8 + + + DONE + Done + 0 + 1 + + + CRSTEXT + CPU Reset Phase Extension + 1 + 1 + + + BERR + Bus Error + 2 + 1 + + + FAIL + Failure + 3 + 1 + + + PERR + Protection Error + 4 + 1 + + + + + STATUSB + Status B + 0x0002 + 8 + read-only + + + PROT + Protected + 0 + 1 + + + DBGPRES + Debugger Present + 1 + 1 + + + DCCD0 + Debug Communication Channel 0 Dirty + 2 + 1 + + + DCCD1 + Debug Communication Channel 1 Dirty + 3 + 1 + + + HPE + Hot-Plugging Enable + 4 + 1 + + + + + ADDR + Address + 0x0004 + 32 + + + AMOD + Access Mode + 0 + 2 + + + ADDR + Address + 2 + 30 + + + + + LENGTH + Length + 0x0008 + 32 + + + LENGTH + Length + 2 + 30 + + + + + DATA + Data + 0x000C + 32 + + + DATA + Data + 0 + 32 + + + + + 2 + 0x4 + DCC%s + Debug Communication Channel n + 0x0010 + 32 + + + DATA + Data + 0 + 32 + + + + + DID + Device Identification + 0x0018 + 32 + read-only + 0x10820105 + + + DEVSEL + Device Select + 0 + 8 + read-only + + + REVISION + Revision Number + 8 + 4 + read-only + + + DIE + Die Number + 12 + 4 + read-only + + + SERIES + Series + 16 + 6 + read-only + + SERIESSelect + + 0 + Cortex-M0+ processor, basic feature set + 0x0 + + + 1 + Cortex-M0+ processor, USB + 0x1 + + + + + FAMILY + Family + 23 + 5 + read-only + + FAMILYSelect + + 0 + General purpose microcontroller + 0x0 + + + 1 + PicoPower + 0x1 + + + + + PROCESSOR + Processor + 28 + 4 + read-only + + PROCESSORSelect + + 0 + Cortex-M0 + 0x0 + + + 1 + Cortex-M0+ + 0x1 + + + 2 + Cortex-M3 + 0x2 + + + 3 + Cortex-M4 + 0x3 + + + + + + + 2 + 0x4 + DCFG%s + Device Configuration + 0x00F0 + 32 + + + DCFG + Device Configuration + 0 + 32 + + + + + ENTRY0 + CoreSight ROM Table Entry 0 + 0x1000 + 32 + read-only + 0x9F0FC002 + + + EPRES + Entry Present + 0 + 1 + + + FMT + Format + 1 + 1 + read-only + + + ADDOFF + Address Offset + 12 + 20 + read-only + + + + + ENTRY1 + CoreSight ROM Table Entry 1 + 0x1004 + 32 + read-only + 0x00007002 + + + END + CoreSight ROM Table End + 0x1008 + 32 + read-only + + + END + End Marker + 0 + 32 + + + + + MEMTYPE + CoreSight ROM Table Memory Type + 0x1FCC + 32 + read-only + + + SMEMP + System Memory Present + 0 + 1 + + + + + PID4 + Peripheral Identification 4 + 0x1FD0 + 32 + read-only + + + JEPCC + JEP-106 Continuation Code + 0 + 4 + + + FKBC + 4KB count + 4 + 4 + read-only + + + + + PID5 + Peripheral Identification 5 + 0x1FD4 + 32 + read-only + + + PID6 + Peripheral Identification 6 + 0x1FD8 + 32 + read-only + + + PID7 + Peripheral Identification 7 + 0x1FDC + 32 + read-only + + + PID0 + Peripheral Identification 0 + 0x1FE0 + 32 + read-only + 0x000000D0 + + + PARTNBL + Part Number Low + 0 + 8 + + + + + PID1 + Peripheral Identification 1 + 0x1FE4 + 32 + read-only + 0x000000FC + + + PARTNBH + Part Number High + 0 + 4 + + + JEPIDCL + Low part of the JEP-106 Identity Code + 4 + 4 + read-only + + + + + PID2 + Peripheral Identification 2 + 0x1FE8 + 32 + read-only + 0x00000009 + + + JEPIDCH + JEP-106 Identity Code High + 0 + 3 + + + JEPU + JEP-106 Identity Code is used + 3 + 1 + read-only + + + REVISION + Revision Number + 4 + 4 + read-only + + + + + PID3 + Peripheral Identification 3 + 0x1FEC + 32 + read-only + + + CUSMOD + ARM CUSMOD + 0 + 4 + + + REVAND + Revision Number + 4 + 4 + read-only + + + + + CID0 + Component Identification 0 + 0x1FF0 + 32 + read-only + 0x0000000D + + + PREAMBLEB0 + Preamble Byte 0 + 0 + 8 + read-only + + + + + CID1 + Component Identification 1 + 0x1FF4 + 32 + read-only + 0x00000010 + + + PREAMBLE + Preamble + 0 + 4 + read-only + + + CCLASS + Component Class + 4 + 4 + read-only + + + + + CID2 + Component Identification 2 + 0x1FF8 + 32 + read-only + 0x00000005 + + + PREAMBLEB2 + Preamble Byte 2 + 0 + 8 + read-only + + + + + CID3 + Component Identification 3 + 0x1FFC + 32 + read-only + 0x000000B1 + + + PREAMBLEB3 + Preamble Byte 3 + 0 + 8 + + + + + + + EIC + 2.0.2 + External Interrupt Controller + EIC + EIC_ + 0x40002800 + + 0 + 0x40 + registers + + + EIC + 3 + + + + CTRLA + Control + 0x00 + 8 + + + SWRST + Software Reset + 0 + 1 + write-only + + + ENABLE + Enable + 1 + 1 + + + CKSEL + Clock Selection + 4 + 1 + + + + + NMICTRL + NMI Control + 0x01 + 8 + + + NMISENSE + NMI Input Sense Configuration + 0 + 3 + + NMISENSESelect + + NONE + No detection + 0x0 + + + RISE + Rising edge detection + 0x1 + + + FALL + Falling edge detection + 0x2 + + + BOTH + Both edges detection + 0x3 + + + HIGH + High level detection + 0x4 + + + LOW + Low level detection + 0x5 + + + + + NMIFILTEN + NMI Filter Enable + 3 + 1 + + + NMIASYNCH + NMI Asynchronous edge Detection Enable + 4 + 1 + + + + + NMIFLAG + NMI Interrupt Flag + 0x02 + 16 + + + NMI + NMI Interrupt Flag + 0 + 1 + + + + + SYNCBUSY + Syncbusy register + 0x04 + 32 + read-only + + + SWRST + Software reset synchronisation + 0 + 1 + read-only + + + ENABLE + Enable synchronisation + 1 + 1 + read-only + + + + + EVCTRL + Event Control + 0x08 + 32 + + + EXTINTEO + External Interrupt Event Output Enable + 0 + 16 + + + + + INTENCLR + Interrupt Enable Clear + 0x0C + 32 + + + EXTINT + External Interrupt Disable + 0 + 16 + + + + + INTENSET + Interrupt Enable Set + 0x10 + 32 + + + EXTINT + External Interrupt Disable + 0 + 16 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x14 + 32 + + + EXTINT + External Interrupt Flag + 0 + 16 + + + + + ASYNCH + EIC Asynchronous edge Detection Enable + 0x18 + 32 + + + ASYNCH + EIC Asynchronous edge Detection Enable + 0 + 16 + + + + + 2 + 0x4 + CONFIG%s + Configuration n + 0x1C + 32 + + + SENSE0 + Input Sense Configuration 0 + 0 + 3 + + SENSE0Select + + NONE + No detection + 0x0 + + + RISE + Rising edge detection + 0x1 + + + FALL + Falling edge detection + 0x2 + + + BOTH + Both edges detection + 0x3 + + + HIGH + High level detection + 0x4 + + + LOW + Low level detection + 0x5 + + + + + FILTEN0 + Filter Enable 0 + 3 + 1 + + + SENSE1 + Input Sense Configuration 1 + 4 + 3 + + SENSE1Select + + NONE + No detection + 0x0 + + + RISE + Rising edge detection + 0x1 + + + FALL + Falling edge detection + 0x2 + + + BOTH + Both edges detection + 0x3 + + + HIGH + High level detection + 0x4 + + + LOW + Low level detection + 0x5 + + + + + FILTEN1 + Filter Enable 1 + 7 + 1 + + + SENSE2 + Input Sense Configuration 2 + 8 + 3 + + SENSE2Select + + NONE + No detection + 0x0 + + + RISE + Rising edge detection + 0x1 + + + FALL + Falling edge detection + 0x2 + + + BOTH + Both edges detection + 0x3 + + + HIGH + High level detection + 0x4 + + + LOW + Low level detection + 0x5 + + + + + FILTEN2 + Filter Enable 2 + 11 + 1 + + + SENSE3 + Input Sense Configuration 3 + 12 + 3 + + SENSE3Select + + NONE + No detection + 0x0 + + + RISE + Rising edge detection + 0x1 + + + FALL + Falling edge detection + 0x2 + + + BOTH + Both edges detection + 0x3 + + + HIGH + High level detection + 0x4 + + + LOW + Low level detection + 0x5 + + + + + FILTEN3 + Filter Enable 3 + 15 + 1 + + + SENSE4 + Input Sense Configuration 4 + 16 + 3 + + SENSE4Select + + NONE + No detection + 0x0 + + + RISE + Rising edge detection + 0x1 + + + FALL + Falling edge detection + 0x2 + + + BOTH + Both edges detection + 0x3 + + + HIGH + High level detection + 0x4 + + + LOW + Low level detection + 0x5 + + + + + FILTEN4 + Filter Enable 4 + 19 + 1 + + + SENSE5 + Input Sense Configuration 5 + 20 + 3 + + SENSE5Select + + NONE + No detection + 0x0 + + + RISE + Rising edge detection + 0x1 + + + FALL + Falling edge detection + 0x2 + + + BOTH + Both edges detection + 0x3 + + + HIGH + High level detection + 0x4 + + + LOW + Low level detection + 0x5 + + + + + FILTEN5 + Filter Enable 5 + 23 + 1 + + + SENSE6 + Input Sense Configuration 6 + 24 + 3 + + SENSE6Select + + NONE + No detection + 0x0 + + + RISE + Rising edge detection + 0x1 + + + FALL + Falling edge detection + 0x2 + + + BOTH + Both edges detection + 0x3 + + + HIGH + High level detection + 0x4 + + + LOW + Low level detection + 0x5 + + + + + FILTEN6 + Filter Enable 6 + 27 + 1 + + + SENSE7 + Input Sense Configuration 7 + 28 + 3 + + SENSE7Select + + NONE + No detection + 0x0 + + + RISE + Rising edge detection + 0x1 + + + FALL + Falling edge detection + 0x2 + + + BOTH + Both edges detection + 0x3 + + + HIGH + High level detection + 0x4 + + + LOW + Low level detection + 0x5 + + + + + FILTEN7 + Filter Enable 7 + 31 + 1 + + + + + + + EVSYS + 1.0.1 + Event System Interface + EVSYS + EVSYS_ + 0x42000000 + + 0 + 0x400 + registers + + + EVSYS + 8 + + + + CTRLA + Control + 0x00 + 8 + + + SWRST + Software Reset + 0 + 1 + write-only + + + + + CHSTATUS + Channel Status + 0x0C + 32 + read-only + + + USRRDY0 + Channel 0 User Ready + 0 + 1 + read-only + + + USRRDY1 + Channel 1 User Ready + 1 + 1 + read-only + + + USRRDY2 + Channel 2 User Ready + 2 + 1 + read-only + + + USRRDY3 + Channel 3 User Ready + 3 + 1 + read-only + + + USRRDY4 + Channel 4 User Ready + 4 + 1 + read-only + + + USRRDY5 + Channel 5 User Ready + 5 + 1 + read-only + + + USRRDY6 + Channel 6 User Ready + 6 + 1 + read-only + + + USRRDY7 + Channel 7 User Ready + 7 + 1 + read-only + + + CHBUSY0 + Channel 0 Busy + 16 + 1 + read-only + + + CHBUSY1 + Channel 1 Busy + 17 + 1 + read-only + + + CHBUSY2 + Channel 2 Busy + 18 + 1 + read-only + + + CHBUSY3 + Channel 3 Busy + 19 + 1 + read-only + + + CHBUSY4 + Channel 4 Busy + 20 + 1 + read-only + + + CHBUSY5 + Channel 5 Busy + 21 + 1 + read-only + + + CHBUSY6 + Channel 6 Busy + 22 + 1 + read-only + + + CHBUSY7 + Channel 7 Busy + 23 + 1 + read-only + + + + + INTENCLR + Interrupt Enable Clear + 0x10 + 32 + + + OVR0 + Channel 0 Overrun Interrupt Enable + 0 + 1 + + + OVR1 + Channel 1 Overrun Interrupt Enable + 1 + 1 + + + OVR2 + Channel 2 Overrun Interrupt Enable + 2 + 1 + + + OVR3 + Channel 3 Overrun Interrupt Enable + 3 + 1 + + + OVR4 + Channel 4 Overrun Interrupt Enable + 4 + 1 + + + OVR5 + Channel 5 Overrun Interrupt Enable + 5 + 1 + + + OVR6 + Channel 6 Overrun Interrupt Enable + 6 + 1 + + + OVR7 + Channel 7 Overrun Interrupt Enable + 7 + 1 + + + EVD0 + Channel 0 Event Detection Interrupt Enable + 16 + 1 + + + EVD1 + Channel 1 Event Detection Interrupt Enable + 17 + 1 + + + EVD2 + Channel 2 Event Detection Interrupt Enable + 18 + 1 + + + EVD3 + Channel 3 Event Detection Interrupt Enable + 19 + 1 + + + EVD4 + Channel 4 Event Detection Interrupt Enable + 20 + 1 + + + EVD5 + Channel 5 Event Detection Interrupt Enable + 21 + 1 + + + EVD6 + Channel 6 Event Detection Interrupt Enable + 22 + 1 + + + EVD7 + Channel 7 Event Detection Interrupt Enable + 23 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x14 + 32 + + + OVR0 + Channel 0 Overrun Interrupt Enable + 0 + 1 + + + OVR1 + Channel 1 Overrun Interrupt Enable + 1 + 1 + + + OVR2 + Channel 2 Overrun Interrupt Enable + 2 + 1 + + + OVR3 + Channel 3 Overrun Interrupt Enable + 3 + 1 + + + OVR4 + Channel 4 Overrun Interrupt Enable + 4 + 1 + + + OVR5 + Channel 5 Overrun Interrupt Enable + 5 + 1 + + + OVR6 + Channel 6 Overrun Interrupt Enable + 6 + 1 + + + OVR7 + Channel 7 Overrun Interrupt Enable + 7 + 1 + + + EVD0 + Channel 0 Event Detection Interrupt Enable + 16 + 1 + + + EVD1 + Channel 1 Event Detection Interrupt Enable + 17 + 1 + + + EVD2 + Channel 2 Event Detection Interrupt Enable + 18 + 1 + + + EVD3 + Channel 3 Event Detection Interrupt Enable + 19 + 1 + + + EVD4 + Channel 4 Event Detection Interrupt Enable + 20 + 1 + + + EVD5 + Channel 5 Event Detection Interrupt Enable + 21 + 1 + + + EVD6 + Channel 6 Event Detection Interrupt Enable + 22 + 1 + + + EVD7 + Channel 7 Event Detection Interrupt Enable + 23 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x18 + 32 + + + OVR0 + Channel 0 Overrun + 0 + 1 + + + OVR1 + Channel 1 Overrun + 1 + 1 + + + OVR2 + Channel 2 Overrun + 2 + 1 + + + OVR3 + Channel 3 Overrun + 3 + 1 + + + OVR4 + Channel 4 Overrun + 4 + 1 + + + OVR5 + Channel 5 Overrun + 5 + 1 + + + OVR6 + Channel 6 Overrun + 6 + 1 + + + OVR7 + Channel 7 Overrun + 7 + 1 + + + EVD0 + Channel 0 Event Detection + 16 + 1 + + + EVD1 + Channel 1 Event Detection + 17 + 1 + + + EVD2 + Channel 2 Event Detection + 18 + 1 + + + EVD3 + Channel 3 Event Detection + 19 + 1 + + + EVD4 + Channel 4 Event Detection + 20 + 1 + + + EVD5 + Channel 5 Event Detection + 21 + 1 + + + EVD6 + Channel 6 Event Detection + 22 + 1 + + + EVD7 + Channel 7 Event Detection + 23 + 1 + + + + + SWEVT + Software Event + 0x1C + 32 + write-only + + + CHANNEL0 + Channel 0 Software Selection + 0 + 1 + + + CHANNEL1 + Channel 1 Software Selection + 1 + 1 + + + CHANNEL2 + Channel 2 Software Selection + 2 + 1 + + + CHANNEL3 + Channel 3 Software Selection + 3 + 1 + + + CHANNEL4 + Channel 4 Software Selection + 4 + 1 + + + CHANNEL5 + Channel 5 Software Selection + 5 + 1 + + + CHANNEL6 + Channel 6 Software Selection + 6 + 1 + + + CHANNEL7 + Channel 7 Software Selection + 7 + 1 + + + + + 8 + 0x4 + CHANNEL%s + Channel n + 0x20 + 32 + 0x00008000 + + + EVGEN + Event Generator Selection + 0 + 7 + + + PATH + Path Selection + 8 + 2 + + PATHSelect + + SYNCHRONOUS + Synchronous path + 0x0 + + + RESYNCHRONIZED + Resynchronized path + 0x1 + + + ASYNCHRONOUS + Asynchronous path + 0x2 + + + + + EDGSEL + Edge Detection Selection + 10 + 2 + + EDGSELSelect + + NO_EVT_OUTPUT + No event output when using the resynchronized or synchronous path + 0x0 + + + RISING_EDGE + Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path + 0x1 + + + FALLING_EDGE + Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path + 0x2 + + + BOTH_EDGES + Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path + 0x3 + + + + + RUNSTDBY + Run in standby + 14 + 1 + + + ONDEMAND + Generic Clock On Demand + 15 + 1 + + + + + 31 + 0x4 + USER%s + User Multiplexer n + 0x80 + 32 + + + CHANNEL + Channel Event Selection + 0 + 4 + + + + + + + FREQM + 1.0.1 + Frequency Meter + FREQM + FREQM_ + 0x40002C00 + + 0 + 0x20 + registers + + + FREQM + 4 + + + + CTRLA + Control A Register + 0x00 + 8 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + + + CTRLB + Control B Register + 0x01 + 8 + write-only + + + START + Start Measurement + 0 + 1 + write-only + + + + + CFGA + Config A register + 0x02 + 16 + + + REFNUM + Number of Reference Clock Cycles + 0 + 8 + + + + + INTENCLR + Interrupt Enable Clear Register + 0x08 + 8 + + + DONE + Measurement Done Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set Register + 0x09 + 8 + + + DONE + Measurement Done Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Register + 0x0A + 8 + + + DONE + Measurement Done + 0 + 1 + + + + + STATUS + Status Register + 0x0B + 8 + + + BUSY + FREQM Status + 0 + 1 + read-only + + + OVF + Sticky Count Value Overflow + 1 + 1 + + + + + SYNCBUSY + Synchronization Busy Register + 0x0C + 32 + read-only + + + SWRST + Software Reset + 0 + 1 + read-only + + + ENABLE + Enable + 1 + 1 + read-only + + + + + VALUE + Count Value Register + 0x10 + 32 + read-only + + + VALUE + Measurement Value + 0 + 24 + read-only + + + + + + + GCLK + 1.1.1 + Generic Clock Generator + GCLK + GCLK_ + 0x40001C00 + + 0 + 0x200 + registers + + + + CTRLA + Control + 0x00 + 8 + + + SWRST + Software Reset + 0 + 1 + + + + + SYNCBUSY + Synchronization Busy + 0x04 + 32 + read-only + + + SWRST + Software Reset Synchroniation Busy bit + 0 + 1 + read-only + + + GENCTRL0 + Generic Clock Generator Control 0 Synchronization Busy bits + 2 + 1 + read-only + + GENCTRL0Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + + + GENCTRL1 + Generic Clock Generator Control 1 Synchronization Busy bits + 3 + 1 + read-only + + GENCTRL1Select + + GCLK1 + Generic clock generator 1 + 0x1 + + + + + GENCTRL2 + Generic Clock Generator Control 2 Synchronization Busy bits + 4 + 1 + read-only + + GENCTRL2Select + + GCLK2 + Generic clock generator 2 + 0x1 + + + + + GENCTRL3 + Generic Clock Generator Control 3 Synchronization Busy bits + 5 + 1 + read-only + + GENCTRL3Select + + GCLK3 + Generic clock generator 3 + 0x1 + + + + + GENCTRL4 + Generic Clock Generator Control 4 Synchronization Busy bits + 6 + 1 + read-only + + GENCTRL4Select + + GCLK4 + Generic clock generator 4 + 0x1 + + + + + + + 5 + 0x4 + GENCTRL%s + Generic Clock Generator Control + 0x20 + 32 + + + SRC + Source Select + 0 + 3 + + SRCSelect + + XOSC + XOSC oscillator output + 0x0 + + + GCLKIN + Generator input pad + 0x1 + + + GCLKGEN1 + Generic clock generator 1 output + 0x2 + + + OSCULP32K + OSCULP32K oscillator output + 0x3 + + + XOSC32K + XOSC32K oscillator output + 0x4 + + + OSC16M + OSC16M oscillator output + 0x5 + + + DFLL48M + DFLL48M output + 0x6 + + + DPLL96M + DPLL96M output + 0x7 + + + + + GENEN + Generic Clock Generator Enable + 8 + 1 + + + IDC + Improve Duty Cycle + 9 + 1 + + + OOV + Output Off Value + 10 + 1 + + + OE + Output Enable + 11 + 1 + + + DIVSEL + Divide Selection + 12 + 1 + + + RUNSTDBY + Run in Standby + 13 + 1 + + + DIV + Division Factor + 16 + 16 + + + + + 30 + 0x4 + PCHCTRL%s + Peripheral Clock Control + 0x80 + 32 + + + GEN + Generic Clock Generator + 0 + 3 + + GENSelect + + GCLK0 + Generic clock generator 0 + 0x0 + + + GCLK1 + Generic clock generator 1 + 0x1 + + + GCLK2 + Generic clock generator 2 + 0x2 + + + GCLK3 + Generic clock generator 3 + 0x3 + + + GCLK4 + Generic clock generator 4 + 0x4 + + + + + CHEN + Channel Enable + 6 + 1 + + + WRTLOCK + Write Lock + 7 + 1 + + + + + + + MCLK + 2.1.0 + Main Clock + MCLK + MCLK_ + 0x40000800 + + 0 + 0x80 + registers + + + SYSTEM + 0 + + + + INTENCLR + Interrupt Enable Clear + 0x01 + 8 + + + CKRDY + Clock Ready Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x02 + 8 + + + CKRDY + Clock Ready Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x03 + 8 + 0x01 + + + CKRDY + Clock Ready + 0 + 1 + + + + + CPUDIV + CPU Clock Division + 0x04 + 8 + 0x01 + + + CPUDIV + CPU Clock Division Factor + 0 + 8 + + CPUDIVSelect + + DIV1 + Divide by 1 + 0x1 + + + DIV2 + Divide by 2 + 0x2 + + + DIV4 + Divide by 4 + 0x4 + + + DIV8 + Divide by 8 + 0x8 + + + DIV16 + Divide by 16 + 0x10 + + + DIV32 + Divide by 32 + 0x20 + + + DIV64 + Divide by 64 + 0x40 + + + DIV128 + Divide by 128 + 0x80 + + + + + + + BUPDIV + Backup Clock Division + 0x06 + 8 + 0x01 + + + BUPDIV + Backup Clock Division Factor + 0 + 8 + + BUPDIVSelect + + DIV1 + Divide by 1 + 0x1 + + + DIV2 + Divide by 2 + 0x2 + + + DIV4 + Divide by 4 + 0x4 + + + DIV8 + Divide by 8 + 0x8 + + + DIV16 + Divide by 16 + 0x10 + + + DIV32 + Divide by 32 + 0x20 + + + DIV64 + Divide by 64 + 0x40 + + + DIV128 + Divide by 128 + 0x80 + + + + + + + AHBMASK + AHB Mask + 0x10 + 32 + 0x000007FF + + + HPB0_ + HPB0 AHB Clock Mask + 0 + 1 + + + HPB1_ + HPB1 AHB Clock Mask + 1 + 1 + + + HPB2_ + HPB2 AHB Clock Mask + 2 + 1 + + + DMAC_ + DMAC AHB Clock Mask + 3 + 1 + + + USB_ + USB AHB Clock Mask + 4 + 1 + + + DSU_ + DSU AHB Clock Mask + 5 + 1 + + + PAC_ + PAC AHB Clock Mask + 7 + 1 + + + NVMCTRL_ + NVMCTRL AHB Clock Mask + 8 + 1 + + + HSRAM_ + HSRAM AHB Clock Mask + 9 + 1 + + + NVMCTRL_PICACHU_ + NVMCTRL_PICACHU AHB Clock Mask + 10 + 1 + + + + + APBAMASK + APBA Mask + 0x14 + 32 + 0x00001FFF + + + PAC_ + PAC APB Clock Enable + 0 + 1 + + + PM_ + PM APB Clock Enable + 1 + 1 + + + MCLK_ + MCLK APB Clock Enable + 2 + 1 + + + RSTC_ + RSTC APB Clock Enable + 3 + 1 + + + OSCCTRL_ + OSCCTRL APB Clock Enable + 4 + 1 + + + OSC32KCTRL_ + OSC32KCTRL APB Clock Enable + 5 + 1 + + + SUPC_ + SUPC APB Clock Enable + 6 + 1 + + + GCLK_ + GCLK APB Clock Enable + 7 + 1 + + + WDT_ + WDT APB Clock Enable + 8 + 1 + + + RTC_ + RTC APB Clock Enable + 9 + 1 + + + EIC_ + EIC APB Clock Enable + 10 + 1 + + + FREQM_ + FREQM APB Clock Enable + 11 + 1 + + + + + APBBMASK + APBB Mask + 0x18 + 32 + 0x0000004F + + + USB_ + USB APB Clock Enable + 0 + 1 + + + DSU_ + DSU APB Clock Enable + 1 + 1 + + + NVMCTRL_ + NVMCTRL APB Clock Enable + 2 + 1 + + + PORT_ + PORT APB Clock Enable + 3 + 1 + + + + + APBCMASK + APBC Mask + 0x1C + 32 + 0x0007FFFF + + + EVSYS_ + EVSYS APB Clock Enable + 0 + 1 + + + SERCOM0_ + SERCOM0 APB Clock Enable + 1 + 1 + + + SERCOM1_ + SERCOM1 APB Clock Enable + 2 + 1 + + + SERCOM2_ + SERCOM2 APB Clock Enable + 3 + 1 + + + SERCOM3_ + SERCOM3 APB Clock Enable + 4 + 1 + + + TCC0_ + TCC0 APB Clock Enable + 7 + 1 + + + TC0_ + TC0 APB Clock Enable + 8 + 1 + + + TC1_ + TC1 APB Clock Enable + 9 + 1 + + + TC2_ + TC2 APB Clock Enable + 10 + 1 + + + TC3_ + TC3 APB Clock Enable + 11 + 1 + + + ADC_ + ADC APB Clock Enable + 12 + 1 + + + AC_ + AC APB Clock Enable + 13 + 1 + + + PTC_ + PTC APB Clock Enable + 14 + 1 + + + SLCD_ + SLCD APB Clock Enable + 15 + 1 + + + AES_ + AES APB Clock Enable + 16 + 1 + + + TRNG_ + TRNG APB Clock Enable + 17 + 1 + + + CCL_ + CCL APB Clock Enable + 18 + 1 + + + + + + + MTB + 1.0.0 + Cortex-M0+ Micro-Trace Buffer + MTB + MTB_ + 0x4100A000 + + 0 + 0x1000 + registers + + + + POSITION + MTB Position + 0x000 + 32 + + + WRAP + Pointer Value Wraps + 2 + 1 + + + POINTER + Trace Packet Location Pointer + 3 + 29 + + + + + MASTER + MTB Master + 0x004 + 32 + + + MASK + Maximum Value of the Trace Buffer in SRAM + 0 + 5 + + + TSTARTEN + Trace Start Input Enable + 5 + 1 + + + TSTOPEN + Trace Stop Input Enable + 6 + 1 + + + SFRWPRIV + Special Function Register Write Privilege + 7 + 1 + + + RAMPRIV + SRAM Privilege + 8 + 1 + + + HALTREQ + Halt Request + 9 + 1 + + + EN + Main Trace Enable + 31 + 1 + + + + + FLOW + MTB Flow + 0x008 + 32 + + + AUTOSTOP + Auto Stop Tracing + 0 + 1 + + + AUTOHALT + Auto Halt Request + 1 + 1 + + + WATERMARK + Watermark value + 3 + 29 + + + + + BASE + MTB Base + 0x00C + 32 + read-only + + + ITCTRL + MTB Integration Mode Control + 0xF00 + 32 + + + CLAIMSET + MTB Claim Set + 0xFA0 + 32 + + + CLAIMCLR + MTB Claim Clear + 0xFA4 + 32 + + + LOCKACCESS + MTB Lock Access + 0xFB0 + 32 + + + LOCKSTATUS + MTB Lock Status + 0xFB4 + 32 + read-only + + + AUTHSTATUS + MTB Authentication Status + 0xFB8 + 32 + read-only + + + DEVARCH + MTB Device Architecture + 0xFBC + 32 + read-only + + + DEVID + MTB Device Configuration + 0xFC8 + 32 + read-only + + + DEVTYPE + MTB Device Type + 0xFCC + 32 + read-only + + + PID4 + Peripheral Identification 4 + 0xFD0 + 32 + read-only + + + PID5 + Peripheral Identification 5 + 0xFD4 + 32 + read-only + + + PID6 + Peripheral Identification 6 + 0xFD8 + 32 + read-only + + + PID7 + Peripheral Identification 7 + 0xFDC + 32 + read-only + + + PID0 + Peripheral Identification 0 + 0xFE0 + 32 + read-only + + + PID1 + Peripheral Identification 1 + 0xFE4 + 32 + read-only + + + PID2 + Peripheral Identification 2 + 0xFE8 + 32 + read-only + + + PID3 + Peripheral Identification 3 + 0xFEC + 32 + read-only + + + CID0 + Component Identification 0 + 0xFF0 + 32 + read-only + + + CID1 + Component Identification 1 + 0xFF4 + 32 + read-only + + + CID2 + Component Identification 2 + 0xFF8 + 32 + read-only + + + CID3 + Component Identification 3 + 0xFFC + 32 + read-only + + + + + NVMCTRL + 3.0.2 + Non-Volatile Memory Controller + NVMCTRL + NVMCTRL_ + 0x41004000 + + 0 + 0x80 + registers + + + NVMCTRL + 6 + + + + CTRLA + Control A + 0x00 + 16 + + + CMD + Command + 0 + 7 + + CMDSelect + + ER + Erase Row - Erases the row addressed by the ADDR register. + 0x2 + + + WP + Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. + 0x4 + + + EAR + Erase Auxiliary Row - Erases the auxiliary row addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. + 0x5 + + + WAP + Write Auxiliary Page - Writes the contents of the page buffer to the page addressed by the ADDR register. This command can be given only when the security bit is not set and only to the user configuration row. + 0x6 + + + SF + Security Flow Command + 0xa + + + WL + Write lockbits + 0xf + + + RWWEEER + RWW EEPROM area Erase Row - Erases the row addressed by the ADDR register. + 0x1a + + + RWWEEWP + RWW EEPROM Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register. + 0x1c + + + LR + Lock Region - Locks the region containing the address location in the ADDR register. + 0x40 + + + UR + Unlock Region - Unlocks the region containing the address location in the ADDR register. + 0x41 + + + SPRM + Sets the power reduction mode. + 0x42 + + + CPRM + Clears the power reduction mode. + 0x43 + + + PBC + Page Buffer Clear - Clears the page buffer. + 0x44 + + + SSB + Set Security Bit - Sets the security bit by writing 0x00 to the first byte in the lockbit row. + 0x45 + + + INVALL + Invalidate all cache lines. + 0x46 + + + + + CMDEX + Command Execution + 8 + 8 + + CMDEXSelect + + KEY + Execution Key + 0xa5 + + + + + + + CTRLB + Control B + 0x04 + 32 + 0x00000080 + + + RWS + NVM Read Wait States + 1 + 4 + + RWSSelect + + SINGLE + Single Auto Wait State + 0x0 + + + HALF + Half Auto Wait State + 0x1 + + + DUAL + Dual Auto Wait State + 0x2 + + + + + MANW + Manual Write + 7 + 1 + + + SLEEPPRM + Power Reduction Mode during Sleep + 8 + 2 + + SLEEPPRMSelect + + WAKEONACCESS + NVM block enters low-power mode when entering sleep.NVM block exits low-power mode upon first access. + 0x0 + + + WAKEUPINSTANT + NVM block enters low-power mode when entering sleep.NVM block exits low-power mode when exiting sleep. + 0x1 + + + DISABLED + Auto power reduction disabled. + 0x3 + + + + + FWUP + fast wake-up + 11 + 1 + + + READMODE + NVMCTRL Read Mode + 16 + 2 + + READMODESelect + + NO_MISS_PENALTY + The NVM Controller (cache system) does not insert wait states on a cache miss. Gives the best system performance. + 0x0 + + + LOW_POWER + Reduces power consumption of the cache system, but inserts a wait state each time there is a cache miss. This mode may not be relevant if CPU performance is required, as the application will be stalled and may lead to increase run time. + 0x1 + + + DETERMINISTIC + The cache system ensures that a cache hit or miss takes the same amount of time, determined by the number of programmed flash wait states. This mode can be used for real-time applications that require deterministic execution timings. + 0x2 + + + + + CACHEDIS + Cache Disable + 18 + 1 + + + + + PARAM + NVM Parameter + 0x08 + 32 + + + NVMP + NVM Pages + 0 + 16 + read-only + + + PSZ + Page Size + 16 + 3 + read-only + + PSZSelect + + 8 + 8 bytes + 0x0 + + + 16 + 16 bytes + 0x1 + + + 32 + 32 bytes + 0x2 + + + 64 + 64 bytes + 0x3 + + + 128 + 128 bytes + 0x4 + + + 256 + 256 bytes + 0x5 + + + 512 + 512 bytes + 0x6 + + + 1024 + 1024 bytes + 0x7 + + + + + RWWEEP + RWW EEPROM Pages + 20 + 12 + read-only + + + + + INTENCLR + Interrupt Enable Clear + 0x0C + 8 + + + READY + NVM Ready Interrupt Enable + 0 + 1 + + + ERROR + Error Interrupt Enable + 1 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x10 + 8 + + + READY + NVM Ready Interrupt Enable + 0 + 1 + + + ERROR + Error Interrupt Enable + 1 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x14 + 8 + + + READY + NVM Ready + 0 + 1 + + + ERROR + Error + 1 + 1 + + + + + STATUS + Status + 0x18 + 16 + + + PRM + Power Reduction Mode + 0 + 1 + read-only + + + LOAD + NVM Page Buffer Active Loading + 1 + 1 + + + PROGE + Programming Error Status + 2 + 1 + + + LOCKE + Lock Error Status + 3 + 1 + + + NVME + NVM Error + 4 + 1 + + + SB + Security Bit Status + 8 + 1 + read-only + + + + + ADDR + Address + 0x1C + 32 + + + ADDR + NVM Address + 0 + 22 + + + + + LOCK + Lock Section + 0x20 + 16 + + + LOCK + Region Lock Bits + 0 + 16 + read-only + + + + + + + OSCCTRL + 3.0.0 + Oscillators Control + OSCCTRL + OSCCTRL_ + 0x40001000 + + 0 + 0x80 + registers + + + SYSTEM + 0 + + + + INTENCLR + Interrupt Enable Clear + 0x00 + 32 + + + XOSCRDY + XOSC Ready Interrupt Enable + 0 + 1 + + + XOSCFAIL + XOSC Clock Failure Detector Interrupt Enable + 1 + 1 + + + OSC16MRDY + OSC16M Ready Interrupt Enable + 4 + 1 + + + DFLLRDY + DFLL Ready Interrupt Enable + 8 + 1 + + + DFLLOOB + DFLL Out Of Bounds Interrupt Enable + 9 + 1 + + + DFLLLCKF + DFLL Lock Fine Interrupt Enable + 10 + 1 + + + DFLLLCKC + DFLL Lock Coarse Interrupt Enable + 11 + 1 + + + DFLLRCS + DFLL Reference Clock Stopped Interrupt Enable + 12 + 1 + + + DPLLLCKR + DPLL Lock Rise Interrupt Enable + 16 + 1 + + + DPLLLCKF + DPLL Lock Fall Interrupt Enable + 17 + 1 + + + DPLLLTO + DPLL Time Out Interrupt Enable + 18 + 1 + + + DPLLLDRTO + DPLL Ratio Ready Interrupt Enable + 19 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x04 + 32 + + + XOSCRDY + XOSC Ready Interrupt Enable + 0 + 1 + + + XOSCFAIL + XOSC Clock Failure Detector Interrupt Enable + 1 + 1 + + + OSC16MRDY + OSC16M Ready Interrupt Enable + 4 + 1 + + + DFLLRDY + DFLL Ready Interrupt Enable + 8 + 1 + + + DFLLOOB + DFLL Out Of Bounds Interrupt Enable + 9 + 1 + + + DFLLLCKF + DFLL Lock Fine Interrupt Enable + 10 + 1 + + + DFLLLCKC + DFLL Lock Coarse Interrupt Enable + 11 + 1 + + + DFLLRCS + DFLL Reference Clock Stopped Interrupt Enable + 12 + 1 + + + DPLLLCKR + DPLL Lock Rise Interrupt Enable + 16 + 1 + + + DPLLLCKF + DPLL Lock Fall Interrupt Enable + 17 + 1 + + + DPLLLTO + DPLL Time Out Interrupt Enable + 18 + 1 + + + DPLLLDRTO + DPLL Ratio Ready Interrupt Enable + 19 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x08 + 32 + + + XOSCRDY + XOSC Ready + 0 + 1 + + + XOSCFAIL + XOSC Clock Failure Detector + 1 + 1 + + + OSC16MRDY + OSC16M Ready + 4 + 1 + + + DFLLRDY + DFLL Ready + 8 + 1 + + + DFLLOOB + DFLL Out Of Bounds + 9 + 1 + + + DFLLLCKF + DFLL Lock Fine + 10 + 1 + + + DFLLLCKC + DFLL Lock Coarse + 11 + 1 + + + DFLLRCS + DFLL Reference Clock Stopped + 12 + 1 + + + DPLLLCKR + DPLL Lock Rise + 16 + 1 + + + DPLLLCKF + DPLL Lock Fall + 17 + 1 + + + DPLLLTO + DPLL Timeout + 18 + 1 + + + DPLLLDRTO + DPLL Ratio Ready + 19 + 1 + + + + + STATUS + Power and Clocks Status + 0x0C + 32 + read-only + + + XOSCRDY + XOSC Ready + 0 + 1 + read-only + + + XOSCFAIL + XOSC Clock Failure Detector + 1 + 1 + read-only + + + XOSCCKSW + XOSC Clock Switch + 2 + 1 + read-only + + + OSC16MRDY + OSC16M Ready + 4 + 1 + read-only + + + DFLLRDY + DFLL Ready + 8 + 1 + read-only + + + DFLLOOB + DFLL Out Of Bounds + 9 + 1 + read-only + + + DFLLLCKF + DFLL Lock Fine + 10 + 1 + read-only + + + DFLLLCKC + DFLL Lock Coarse + 11 + 1 + read-only + + + DFLLRCS + DFLL Reference Clock Stopped + 12 + 1 + read-only + + + DPLLLCKR + DPLL Lock Rise + 16 + 1 + read-only + + + DPLLLCKF + DPLL Lock Fall + 17 + 1 + read-only + + + DPLLTO + DPLL Timeout + 18 + 1 + read-only + + + DPLLLDRTO + DPLL Ratio Ready + 19 + 1 + read-only + + + + + XOSCCTRL + External Multipurpose Crystal Oscillator (XOSC) Control + 0x10 + 16 + 0x0080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + XTALEN + Crystal Oscillator Enable + 2 + 1 + + + CFDEN + Xosc Clock Failure Detecteor Enable + 3 + 1 + + + SWBEN + Xosc Clock Switch Enable + 4 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + GAIN + Oscillator Gain + 8 + 3 + + + AMPGC + Automatic Amplitude Gain Control + 11 + 1 + + + STARTUP + Start-Up Time + 12 + 4 + + + + + CFDPRESC + Cloc Failure Detector Prescaler + 0x12 + 8 + + + CFDPRESC + Clock Failure Detector Prescaler + 0 + 3 + + + + + EVCTRL + Event Control + 0x13 + 8 + + + CFDEO + Clock Failure Detector Event Output Enable + 0 + 1 + + + + + OSC16MCTRL + 16MHz Internal Oscillator (OSC16M) Control + 0x14 + 8 + 0x82 + + + ENABLE + Oscillator Enable + 1 + 1 + + + FSEL + Oscillator Frequency Select + 2 + 2 + + FSELSelect + + 4 + 4MHz + 0x0 + + + 8 + 8MHz + 0x1 + + + 12 + 12MHz + 0x2 + + + 16 + 16MHz + 0x3 + + + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + + + DFLLCTRL + DFLL48M Control + 0x18 + 16 + 0x0080 + + + ENABLE + DFLL Enable + 1 + 1 + + + MODE + Operating Mode Selection + 2 + 1 + + + STABLE + Stable DFLL Frequency + 3 + 1 + + + LLAW + Lose Lock After Wake + 4 + 1 + + + USBCRM + USB Clock Recovery Mode + 5 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + CCDIS + Chill Cycle Disable + 8 + 1 + + + QLDIS + Quick Lock Disable + 9 + 1 + + + BPLCKC + Bypass Coarse Lock + 10 + 1 + + + WAITLOCK + Wait Lock + 11 + 1 + + + + + DFLLVAL + DFLL48M Value + 0x1C + 32 + + + FINE + Fine Value + 0 + 10 + + + COARSE + Coarse Value + 10 + 6 + + + DIFF + Multiplication Ratio Difference + 16 + 16 + read-only + + + + + DFLLMUL + DFLL48M Multiplier + 0x20 + 32 + + + MUL + DFLL Multiply Factor + 0 + 16 + + + FSTEP + Fine Maximum Step + 16 + 10 + + + CSTEP + Coarse Maximum Step + 26 + 6 + + + + + DFLLSYNC + DFLL48M Synchronization + 0x24 + 8 + + + READREQ + Read Request + 7 + 1 + write-only + + + + + DPLLCTRLA + DPLL Control + 0x28 + 8 + 0x80 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand + 7 + 1 + + + + + DPLLRATIO + DPLL Ratio Control + 0x2C + 32 + + + LDR + Loop Divider Ratio + 0 + 12 + + + LDRFRAC + Loop Divider Ratio Fractional Part + 16 + 4 + + + + + DPLLCTRLB + Digital Core Configuration + 0x30 + 32 + + + FILTER + Proportional Integral Filter Selection + 0 + 2 + + + LPEN + Low-Power Enable + 2 + 1 + + + WUF + Wake Up Fast + 3 + 1 + + + REFCLK + Reference Clock Selection + 4 + 2 + + + LTIME + Lock Time + 8 + 3 + + + LBYPASS + Lock Bypass + 12 + 1 + + + DIV + Clock Divider + 16 + 11 + + + + + DPLLPRESC + DPLL Prescaler + 0x34 + 8 + + + PRESC + Output Clock Prescaler + 0 + 2 + + PRESCSelect + + DIV1 + DPLL output is divided by 1 + 0x0 + + + DIV2 + DPLL output is divided by 2 + 0x1 + + + DIV4 + DPLL output is divided by 4 + 0x2 + + + + + + + DPLLSYNCBUSY + DPLL Synchronization Busy + 0x38 + 8 + read-only + + + ENABLE + DPLL Enable Synchronization Status + 1 + 1 + read-only + + + DPLLRATIO + DPLL Ratio Synchronization Status + 2 + 1 + read-only + + + DPLLPRESC + DPLL Prescaler Synchronization Status + 3 + 1 + read-only + + + + + DPLLSTATUS + DPLL Status + 0x3C + 8 + read-only + + + LOCK + DPLL Lock Status + 0 + 1 + read-only + + + CLKRDY + DPLL Clock Ready + 1 + 1 + read-only + + + + + + + OSC32KCTRL + 3.0.0 + 32k Oscillators Control + OSC32KCTRL + OSC32KCTRL_ + 0x40001400 + + 0 + 0x80 + registers + + + SYSTEM + 0 + + + + INTENCLR + Interrupt Enable Clear + 0x00 + 32 + + + XOSC32KRDY + XOSC32K Ready Interrupt Enable + 0 + 1 + + + CLKFAIL + XOSC32K Clock Failure Detector Interrupt Enable + 2 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x04 + 32 + + + XOSC32KRDY + XOSC32K Ready Interrupt Enable + 0 + 1 + + + CLKFAIL + XOSC32K Clock Failure Detector Interrupt Enable + 2 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x08 + 32 + + + XOSC32KRDY + XOSC32K Ready + 0 + 1 + + + CLKFAIL + XOSC32K Clock Failure Detector + 2 + 1 + + + + + STATUS + Power and Clocks Status + 0x0C + 32 + read-only + + + XOSC32KRDY + XOSC32K Ready + 0 + 1 + read-only + + + CLKFAIL + XOSC32K Clock Failure Detector + 2 + 1 + read-only + + + CLKSW + XOSC32K Clock switch + 3 + 1 + read-only + + + + + RTCCTRL + RTC Clock Selection + 0x10 + 8 + + + RTCSEL + RTC Clock Selection + 0 + 3 + + RTCSELSelect + + ULP1K + 1.024kHz from 32kHz internal ULP oscillator + 0x0 + + + ULP32K + 32.768kHz from 32kHz internal ULP oscillator + 0x1 + + + XOSC1K + 1.024kHz from 32.768kHz external oscillator + 0x4 + + + XOSC32K + 32.768kHz from 32.768kHz external crystal oscillator + 0x5 + + + + + + + SLCDCTRL + SLCD Clock Selection + 0x11 + 8 + + + SLCDSEL + SLCD Clock Selection + 0 + 1 + + + + + XOSC32K + 32kHz External Crystal Oscillator (XOSC32K) Control + 0x14 + 16 + 0x0080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + XTALEN + Crystal Oscillator Enable + 2 + 1 + + + EN32K + 32kHz Output Enable + 3 + 1 + + + EN1K + 1kHz Output Enable + 4 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + STARTUP + Oscillator Start-Up Time + 8 + 3 + + + WRTLOCK + Write Lock + 12 + 1 + + + + + CFDCTRL + Clock Failure Detector Control + 0x16 + 8 + + + CFDEN + Clock Failure Detector Enable + 0 + 1 + + + SWBACK + Clock Switch Back + 1 + 1 + + + CFDPRESC + Clock Failure Detector Prescaler + 2 + 1 + + + + + EVCTRL + Event Control + 0x17 + 8 + + + CFDEO + Clock Failure Detector Event Output Enable + 0 + 1 + + + + + OSCULP32K + 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control + 0x1C + 32 + + + EN32K + Enable Out 32k + 1 + 1 + + + EN1K + Enable Out 1k + 2 + 1 + + + CALIB + Oscillator Calibration + 8 + 5 + + + WRTLOCK + Write Lock + 15 + 1 + + + + + + + PAC + 1.1.0 + Peripheral Access Controller + PAC + PAC_ + 0x40000000 + + 0 + 0x80 + registers + + + SYSTEM + 0 + + + + WRCTRL + Write control + 0x00 + 32 + + + PERID + Peripheral identifier + 0 + 16 + + + KEY + Peripheral access control key + 16 + 8 + + KEYSelect + + OFF + No action + 0x0 + + + CLR + Clear protection + 0x1 + + + SET + Set protection + 0x2 + + + SETLCK + Set and lock protection + 0x3 + + + + + + + EVCTRL + Event control + 0x04 + 8 + + + ERREO + Peripheral acess error event output + 0 + 1 + + + + + INTENCLR + Interrupt enable clear + 0x08 + 8 + + + ERR + Peripheral access error interrupt disable + 0 + 1 + + + + + INTENSET + Interrupt enable set + 0x09 + 8 + + + ERR + Peripheral access error interrupt enable + 0 + 1 + + + + + INTFLAGAHB + Bridge interrupt flag status + 0x10 + 32 + + + FLASH_ + FLASH + 0 + 1 + + + HSRAMCM0P_ + HSRAMCM0P + 1 + 1 + + + HSRAMDSU_ + HSRAMDSU + 2 + 1 + + + HPB1_ + HPB1 + 3 + 1 + + + HPB0_ + HPB0 + 4 + 1 + + + HPB2_ + HPB2 + 5 + 1 + + + HSRAMDMAC_ + HSRAMDMAC + 6 + 1 + + + + + INTFLAGA + Peripheral interrupt flag status - Bridge A + 0x14 + 32 + + + PAC_ + PAC + 0 + 1 + + + PM_ + PM + 1 + 1 + + + MCLK_ + MCLK + 2 + 1 + + + RSTC_ + RSTC + 3 + 1 + + + OSCCTRL_ + OSCCTRL + 4 + 1 + + + OSC32KCTRL_ + OSC32KCTRL + 5 + 1 + + + SUPC_ + SUPC + 6 + 1 + + + GCLK_ + GCLK + 7 + 1 + + + WDT_ + WDT + 8 + 1 + + + RTC_ + RTC + 9 + 1 + + + EIC_ + EIC + 10 + 1 + + + FREQM_ + FREQM + 11 + 1 + + + + + INTFLAGB + Peripheral interrupt flag status - Bridge B + 0x18 + 32 + + + USB_ + USB + 0 + 1 + + + DSU_ + DSU + 1 + 1 + + + NVMCTRL_ + NVMCTRL + 2 + 1 + + + PORT_ + PORT + 3 + 1 + + + DMAC_ + DMAC + 4 + 1 + + + MTB_ + MTB + 5 + 1 + + + + + INTFLAGC + Peripheral interrupt flag status - Bridge C + 0x1C + 32 + + + EVSYS_ + EVSYS + 0 + 1 + + + SERCOM0_ + SERCOM0 + 1 + 1 + + + SERCOM1_ + SERCOM1 + 2 + 1 + + + SERCOM2_ + SERCOM2 + 3 + 1 + + + SERCOM3_ + SERCOM3 + 4 + 1 + + + TCC0_ + TCC0 + 7 + 1 + + + TC0_ + TC0 + 8 + 1 + + + TC1_ + TC1 + 9 + 1 + + + TC2_ + TC2 + 10 + 1 + + + TC3_ + TC3 + 11 + 1 + + + ADC_ + ADC + 12 + 1 + + + AC_ + AC + 13 + 1 + + + PTC_ + PTC + 14 + 1 + + + SLCD_ + SLCD + 15 + 1 + + + AES_ + AES + 16 + 1 + + + TRNG_ + TRNG + 17 + 1 + + + CCL_ + CCL + 18 + 1 + + + + + STATUSA + Peripheral write protection status - Bridge A + 0x34 + 32 + read-only + + + PAC_ + PAC APB Protect Enable + 0 + 1 + + + PM_ + PM APB Protect Enable + 1 + 1 + + + MCLK_ + MCLK APB Protect Enable + 2 + 1 + + + RSTC_ + RSTC APB Protect Enable + 3 + 1 + + + OSCCTRL_ + OSCCTRL APB Protect Enable + 4 + 1 + + + OSC32KCTRL_ + OSC32KCTRL APB Protect Enable + 5 + 1 + + + SUPC_ + SUPC APB Protect Enable + 6 + 1 + + + GCLK_ + GCLK APB Protect Enable + 7 + 1 + + + WDT_ + WDT APB Protect Enable + 8 + 1 + + + RTC_ + RTC APB Protect Enable + 9 + 1 + + + EIC_ + EIC APB Protect Enable + 10 + 1 + + + FREQM_ + FREQM APB Protect Enable + 11 + 1 + + + + + STATUSB + Peripheral write protection status - Bridge B + 0x38 + 32 + read-only + 0x00000002 + + + USB_ + USB APB Protect Enable + 0 + 1 + + + DSU_ + DSU APB Protect Enable + 1 + 1 + + + NVMCTRL_ + NVMCTRL APB Protect Enable + 2 + 1 + + + PORT_ + PORT APB Protect Enable + 3 + 1 + + + DMAC_ + DMAC APB Protect Enable + 4 + 1 + + + MTB_ + MTB APB Protect Enable + 5 + 1 + + + + + STATUSC + Peripheral write protection status - Bridge C + 0x3C + 32 + read-only + 0x00080000 + + + EVSYS_ + EVSYS APB Protect Enable + 0 + 1 + + + SERCOM0_ + SERCOM0 APB Protect Enable + 1 + 1 + + + SERCOM1_ + SERCOM1 APB Protect Enable + 2 + 1 + + + SERCOM2_ + SERCOM2 APB Protect Enable + 3 + 1 + + + SERCOM3_ + SERCOM3 APB Protect Enable + 4 + 1 + + + TCC0_ + TCC0 APB Protect Enable + 7 + 1 + + + TC0_ + TC0 APB Protect Enable + 8 + 1 + + + TC1_ + TC1 APB Protect Enable + 9 + 1 + + + TC2_ + TC2 APB Protect Enable + 10 + 1 + + + TC3_ + TC3 APB Protect Enable + 11 + 1 + + + ADC_ + ADC APB Protect Enable + 12 + 1 + + + AC_ + AC APB Protect Enable + 13 + 1 + + + PTC_ + PTC APB Protect Enable + 14 + 1 + + + SLCD_ + SLCD APB Protect Enable + 15 + 1 + + + AES_ + AES APB Protect Enable + 16 + 1 + + + TRNG_ + TRNG APB Protect Enable + 17 + 1 + + + CCL_ + CCL APB Protect Enable + 18 + 1 + + + + + + + PM + 2.1.1 + Power Manager + PM + PM_ + 0x40000400 + + 0 + 0x80 + registers + + + SYSTEM + 0 + + + + CTRLA + Control A + 0x00 + 8 + + + IORET + I/O Retention + 2 + 1 + + + + + SLEEPCFG + Sleep Configuration + 0x01 + 8 + 0x02 + + + SLEEPMODE + Sleep Mode + 0 + 3 + + SLEEPMODESelect + + IDLE0 + CPU clock is OFF + 0x0 + + + IDLE1 + AHB clock is OFF + 0x1 + + + IDLE2 + APB clock are OFF + 0x2 + + + STANDBY + All Clocks are OFF + 0x4 + + + BACKUP + Only Backup domain is powered ON + 0x5 + + + OFF + All power domains are powered OFF + 0x6 + + + + + + + PLCFG + Performance Level Configuration + 0x02 + 8 + + + PLSEL + Performance Level Select + 0 + 2 + + PLSELSelect + + PL0 + Performance Level 0 + 0x0 + + + PL1 + Performance Level 1 + 0x1 + + + PL2 + Performance Level 2 + 0x2 + + + + + PLDIS + Performance Level Disable + 7 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x04 + 8 + + + PLRDY + Performance Level Interrupt Enable + 0 + 1 + write-only + + + + + INTENSET + Interrupt Enable Set + 0x05 + 8 + + + PLRDY + Performance Level Ready interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x06 + 8 + + + PLRDY + Performance Level Ready + 0 + 1 + + + + + STDBYCFG + Standby Configuration + 0x08 + 16 + 0x0400 + + + VREGSMOD + Voltage Regulator Standby mode + 6 + 2 + + VREGSMODSelect + + AUTO + Automatic mode + 0x0 + + + PERFORMANCE + Performance oriented + 0x1 + + + LP + Low Power oriented + 0x2 + + + + + BBIASHS + Back Bias for HMCRAMCHS + 10 + 2 + + + + + + + PORT + 2.1.1 + Port Module + PORT + PORT_ + 0x41006000 + + 0 + 0x200 + registers + + + + 2 + 0x80 + DIR%s + Data Direction + 0x00 + 32 + + + 2 + 0x80 + DIRCLR%s + Data Direction Clear + 0x04 + 32 + + + 2 + 0x80 + DIRSET%s + Data Direction Set + 0x08 + 32 + + + 2 + 0x80 + DIRTGL%s + Data Direction Toggle + 0x0C + 32 + + + 2 + 0x80 + OUT%s + Data Output Value + 0x10 + 32 + + + 2 + 0x80 + OUTCLR%s + Data Output Value Clear + 0x14 + 32 + + + 2 + 0x80 + OUTSET%s + Data Output Value Set + 0x18 + 32 + + + 2 + 0x80 + OUTTGL%s + Data Output Value Toggle + 0x1C + 32 + + + 2 + 0x80 + IN%s + Data Input Value + 0x20 + 32 + read-only + + + 2 + 0x80 + CTRL%s + Control + 0x24 + 32 + + + SAMPLING + Input Sampling Mode + 0 + 32 + write-only + + + + + 2 + 0x80 + WRCONFIG%s + Write Configuration + 0x28 + 32 + write-only + + + PINMASK + Pin Mask for Multiple Pin Configuration + 0 + 16 + + + PMUXEN + Select Peripheral Multiplexer + 16 + 1 + + + INEN + Input Enable + 17 + 1 + + + PULLEN + Pull Enable + 18 + 1 + + + DRVSTR + Output Driver Strength Selection + 22 + 1 + + + PMUX + Peripheral Multiplexing Template + 24 + 4 + + + WRPMUX + Write PMUX Registers + 28 + 1 + + + WRPINCFG + Write PINCFG Registers + 30 + 1 + + + HWSEL + Half-Word Select + 31 + 1 + + + + + 2 + 0x80 + EVCTRL%s + Event Input Control + 0x2C + 32 + + + PID0 + Port Event Pin Identifier 0 + 0 + 5 + + + EVACT0 + Port Event Action 0 + 5 + 2 + + + PORTEI0 + Port Event Enable Input 0 + 7 + 1 + + + PID1 + Port Event Pin Identifier 1 + 8 + 5 + + + EVACT1 + Port Event Action 1 + 13 + 2 + + + PORTEI1 + Port Event Enable Input 1 + 15 + 1 + + + PID2 + Port Event Pin Identifier 2 + 16 + 5 + + + EVACT2 + Port Event Action 2 + 21 + 2 + + + PORTEI2 + Port Event Enable Input 2 + 23 + 1 + + + PID3 + Port Event Pin Identifier 3 + 24 + 5 + + + EVACT3 + Port Event Action 3 + 29 + 2 + + + PORTEI3 + Port Event Enable Input 3 + 31 + 1 + + + + + 16 + 0x1 + PMUX0_%s + Peripheral Multiplexing n - Group 0 + 0x30 + 8 + + + PMUXE + Peripheral Multiplexing for Even-Numbered Pin + 0 + 4 + + + PMUXO + Peripheral Multiplexing for Odd-Numbered Pin + 4 + 4 + + + + + 16 + 0x1 + PMUX1_%s + Peripheral Multiplexing n - Group 1 + 0xb0 + + + 32 + 0x1 + PINCFG0_%s + Pin Configuration n - Group 0 + 0x40 + 8 + + + PMUXEN + Select Peripheral Multiplexer + 0 + 1 + + + INEN + Input Enable + 1 + 1 + + + PULLEN + Pull Enable + 2 + 1 + + + DRVSTR + Output Driver Strength Selection + 6 + 1 + write-only + + + + + 32 + 0x1 + PINCFG1_%s + Pin Configuration n - Group 1 + 0xc0 + + + + + PORT_IOBUS + Port Module (IOBUS) + PORT_IOBUS + PORT_IOBUS_ + 0x60000000 + + + RSTC + 3.0.0 + Reset Controller + RSTC + RSTC_ + 0x40000C00 + + 0 + 0x20 + registers + + + + RCAUSE + Reset Cause + 0x00 + 8 + read-only + + + POR + Power On Reset + 0 + 1 + + + BODCORE + Brown Out CORE Detector Reset + 1 + 1 + + + BODVDD + Brown Out VDD Detector Reset + 2 + 1 + + + EXT + External Reset + 4 + 1 + + + WDT + Watchdog Reset + 5 + 1 + + + SYST + System Reset Request + 6 + 1 + + + BACKUP + Backup Reset + 7 + 1 + + + + + BKUPEXIT + Backup Exit Source + 0x02 + 8 + read-only + + + RTC + Real Timer Counter Interrupt + 1 + 1 + read-only + + + BBPS + Battery Backup Power Switch + 2 + 1 + read-only + + + + + + + RTC + 2.0.1 + Real-Time Counter + RTC + RTC_ + 0x40002400 + + 0 + 0x100 + registers + + + RTC + 2 + + + + MODE0 + 32-bit Counter with Single 32-bit Compare + RtcMode0 + 0x0 + + CTRLA + MODE0 Control A + 0x00 + 16 + + + SWRST + Software Reset + 0 + 1 + write-only + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0x0 + + + COUNT16 + Mode 1: 16-bit Counter + 0x1 + + + CLOCK + Mode 2: Clock/Calendar + 0x2 + + + + + MATCHCLR + Clear on Match + 7 + 1 + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + OFF + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x1 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x2 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x3 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x4 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x5 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x6 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x7 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x8 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x9 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0xa + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xb + + + + + BKTRST + BKUP Registers Reset On Tamper Enable + 13 + 1 + + + GPTRST + GP Registers Reset On Tamper Enable + 14 + 1 + + + COUNTSYNC + Count Read Synchronization Enable + 15 + 1 + + + + + CTRLB + MODE0 Control B + 0x02 + 16 + + + GP0EN + General Purpose 0 Enable + 0 + 1 + + + DEBMAJ + Debouncer Majority Enable + 4 + 1 + + + DEBASYNC + Debouncer Asynchronous Enable + 5 + 1 + + + RTCOUT + RTC Output Enable + 6 + 1 + + + DMAEN + DMA Enable + 7 + 1 + + + DEBF + Debounce Freqnuency + 8 + 3 + + DEBFSelect + + DIV2 + CLK_RTC_DEB = CLK_RTC/2 + 0x0 + + + DIV4 + CLK_RTC_DEB = CLK_RTC/4 + 0x1 + + + DIV8 + CLK_RTC_DEB = CLK_RTC/8 + 0x2 + + + DIV16 + CLK_RTC_DEB = CLK_RTC/16 + 0x3 + + + DIV32 + CLK_RTC_DEB = CLK_RTC/32 + 0x4 + + + DIV64 + CLK_RTC_DEB = CLK_RTC/64 + 0x5 + + + DIV128 + CLK_RTC_DEB = CLK_RTC/128 + 0x6 + + + DIV256 + CLK_RTC_DEB = CLK_RTC/256 + 0x7 + + + + + ACTF + Active Layer Freqnuency + 12 + 3 + + ACTFSelect + + DIV2 + CLK_RTC_OUT = CLK_RTC/2 + 0x0 + + + DIV4 + CLK_RTC_OUT = CLK_RTC/4 + 0x1 + + + DIV8 + CLK_RTC_OUT = CLK_RTC/8 + 0x2 + + + DIV16 + CLK_RTC_OUT = CLK_RTC/16 + 0x3 + + + DIV32 + CLK_RTC_OUT = CLK_RTC/32 + 0x4 + + + DIV64 + CLK_RTC_OUT = CLK_RTC/64 + 0x5 + + + DIV128 + CLK_RTC_OUT = CLK_RTC/128 + 0x6 + + + DIV256 + CLK_RTC_OUT = CLK_RTC/256 + 0x7 + + + + + + + EVCTRL + MODE0 Event Control + 0x04 + 32 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + CMPEO0 + Compare 0 Event Output Enable + 8 + 1 + + + TAMPEREO + Tamper Event Output Enable + 14 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + TAMPEVEI + Tamper Event Input Enable + 16 + 1 + + + + + INTENCLR + MODE0 Interrupt Enable Clear + 0x08 + 16 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + write-only + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + write-only + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + write-only + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + write-only + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + write-only + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + write-only + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + write-only + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + write-only + + + CMP0 + Compare 0 Interrupt Enable + 8 + 1 + + + TAMPER + Tamper Enable + 14 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTENSET + MODE0 Interrupt Enable Set + 0x0A + 16 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + CMP0 + Compare 0 Interrupt Enable + 8 + 1 + + + TAMPER + Tamper Enable + 14 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTFLAG + MODE0 Interrupt Flag Status and Clear + 0x0C + 16 + + + PER0 + Periodic Interval 0 + 0 + 1 + + + PER1 + Periodic Interval 1 + 1 + 1 + + + PER2 + Periodic Interval 2 + 2 + 1 + + + PER3 + Periodic Interval 3 + 3 + 1 + + + PER4 + Periodic Interval 4 + 4 + 1 + + + PER5 + Periodic Interval 5 + 5 + 1 + + + PER6 + Periodic Interval 6 + 6 + 1 + + + PER7 + Periodic Interval 7 + 7 + 1 + + + CMP0 + Compare 0 + 8 + 1 + + + TAMPER + Tamper + 14 + 1 + + + OVF + Overflow + 15 + 1 + + + + + DBGCTRL + Debug Control + 0x0E + 8 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + MODE0 Synchronization Busy Status + 0x10 + 32 + read-only + + + SWRST + Software Reset Busy + 0 + 1 + read-only + + + ENABLE + Enable Bit Busy + 1 + 1 + read-only + + + FREQCORR + FREQCORR Register Busy + 2 + 1 + read-only + + + COUNT + COUNT Register Busy + 3 + 1 + read-only + + + COMP0 + COMP 0 Register Busy + 5 + 1 + read-only + + + COUNTSYNC + Count Synchronization Enable Bit Busy + 15 + 1 + read-only + + + GP0 + General Purpose 0 Register Busy + 16 + 1 + read-only + + + GP1 + General Purpose 1 Register Busy + 17 + 1 + read-only + + + + + FREQCORR + Frequency Correction + 0x14 + 8 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + COUNT + MODE0 Counter Value + 0x18 + 32 + + + COUNT + Counter Value + 0 + 32 + + + + + 1 + 0x4 + COMP%s + MODE0 Compare n Value + 0x20 + 32 + + + COMP + Compare Value + 0 + 32 + + + + + 2 + 0x4 + GP%s + General Purpose + 0x40 + 32 + + + GP + General Purpose + 0 + 32 + + + + + TAMPCTRL + Tamper Control + 0x60 + 32 + + + IN0ACT + Tamper Input 0 Action + 0 + 2 + + IN0ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN0 to OUT + 0x3 + + + + + IN1ACT + Tamper Input 1 Action + 2 + 2 + + IN1ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN1 to OUT + 0x3 + + + + + IN2ACT + Tamper Input 2 Action + 4 + 2 + + IN2ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN2 to OUT + 0x3 + + + + + IN3ACT + Tamper Input 3 Action + 6 + 2 + + IN3ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN3 to OUT + 0x3 + + + + + IN4ACT + Tamper Input 4 Action + 8 + 2 + + IN4ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN4 to OUT + 0x3 + + + + + TAMLVL0 + Tamper Level Select 0 + 16 + 1 + + + TAMLVL1 + Tamper Level Select 1 + 17 + 1 + + + TAMLVL2 + Tamper Level Select 2 + 18 + 1 + + + TAMLVL3 + Tamper Level Select 3 + 19 + 1 + + + TAMLVL4 + Tamper Level Select 4 + 20 + 1 + + + DEBNC0 + Debouncer Enable 0 + 24 + 1 + + + DEBNC1 + Debouncer Enable 1 + 25 + 1 + + + DEBNC2 + Debouncer Enable 2 + 26 + 1 + + + DEBNC3 + Debouncer Enable 3 + 27 + 1 + + + DEBNC4 + Debouncer Enable 4 + 28 + 1 + + + + + TIMESTAMP + MODE0 Timestamp + 0x64 + 32 + read-only + + + COUNT + Count Timestamp Value + 0 + 32 + read-only + + + + + TAMPID + Tamper ID + 0x68 + 32 + + + TAMPID0 + Tamper Input 0 Detected + 0 + 1 + + + TAMPID1 + Tamper Input 1 Detected + 1 + 1 + + + TAMPID2 + Tamper Input 2 Detected + 2 + 1 + + + TAMPID3 + Tamper Input 3 Detected + 3 + 1 + + + TAMPID4 + Tamper Input 4 Detected + 4 + 1 + + + TAMPEVT + Tamper Event Detected + 31 + 1 + + + + + 8 + 0x4 + BKUP%s + Backup + 0x80 + 32 + + + BKUP + Backup + 0 + 32 + + + + + + MODE1 + 16-bit Counter with Two 16-bit Compares + MODE0 + RtcMode1 + 0x0 + + CTRLA + MODE1 Control A + 0x00 + 16 + + + SWRST + Software Reset + 0 + 1 + write-only + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0x0 + + + COUNT16 + Mode 1: 16-bit Counter + 0x1 + + + CLOCK + Mode 2: Clock/Calendar + 0x2 + + + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + OFF + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x1 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x2 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x3 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x4 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x5 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x6 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x7 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x8 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x9 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0xa + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xb + + + + + BKTRST + BKUP Registers Reset On Tamper Enable + 13 + 1 + + + GPTRST + GP Registers Reset On Tamper Enable + 14 + 1 + + + COUNTSYNC + Count Read Synchronization Enable + 15 + 1 + + + + + CTRLB + MODE1 Control B + 0x02 + 16 + + + GP0EN + General Purpose 0 Enable + 0 + 1 + + + DEBMAJ + Debouncer Majority Enable + 4 + 1 + + + DEBASYNC + Debouncer Asynchronous Enable + 5 + 1 + + + RTCOUT + RTC Output Enable + 6 + 1 + + + DMAEN + DMA Enable + 7 + 1 + + + DEBF + Debounce Freqnuency + 8 + 3 + + DEBFSelect + + DIV2 + CLK_RTC_DEB = CLK_RTC/2 + 0x0 + + + DIV4 + CLK_RTC_DEB = CLK_RTC/4 + 0x1 + + + DIV8 + CLK_RTC_DEB = CLK_RTC/8 + 0x2 + + + DIV16 + CLK_RTC_DEB = CLK_RTC/16 + 0x3 + + + DIV32 + CLK_RTC_DEB = CLK_RTC/32 + 0x4 + + + DIV64 + CLK_RTC_DEB = CLK_RTC/64 + 0x5 + + + DIV128 + CLK_RTC_DEB = CLK_RTC/128 + 0x6 + + + DIV256 + CLK_RTC_DEB = CLK_RTC/256 + 0x7 + + + + + ACTF + Active Layer Freqnuency + 12 + 3 + + ACTFSelect + + DIV2 + CLK_RTC_OUT = CLK_RTC/2 + 0x0 + + + DIV4 + CLK_RTC_OUT = CLK_RTC/4 + 0x1 + + + DIV8 + CLK_RTC_OUT = CLK_RTC/8 + 0x2 + + + DIV16 + CLK_RTC_OUT = CLK_RTC/16 + 0x3 + + + DIV32 + CLK_RTC_OUT = CLK_RTC/32 + 0x4 + + + DIV64 + CLK_RTC_OUT = CLK_RTC/64 + 0x5 + + + DIV128 + CLK_RTC_OUT = CLK_RTC/128 + 0x6 + + + DIV256 + CLK_RTC_OUT = CLK_RTC/256 + 0x7 + + + + + + + EVCTRL + MODE1 Event Control + 0x04 + 32 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + CMPEO0 + Compare 0 Event Output Enable + 8 + 1 + + + CMPEO1 + Compare 1 Event Output Enable + 9 + 1 + + + TAMPEREO + Tamper Event Output Enable + 14 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + TAMPEVEI + Tamper Event Input Enable + 16 + 1 + + + + + INTENCLR + MODE1 Interrupt Enable Clear + 0x08 + 16 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + CMP0 + Compare 0 Interrupt Enable + 8 + 1 + + + CMP1 + Compare 1 Interrupt Enable + 9 + 1 + + + TAMPER + Tamper Enable + 14 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTENSET + MODE1 Interrupt Enable Set + 0x0A + 16 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + CMP0 + Compare 0 Interrupt Enable + 8 + 1 + + + CMP1 + Compare 1 Interrupt Enable + 9 + 1 + + + TAMPER + Tamper Enable + 14 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTFLAG + MODE1 Interrupt Flag Status and Clear + 0x0C + 16 + + + PER0 + Periodic Interval 0 + 0 + 1 + + + PER1 + Periodic Interval 1 + 1 + 1 + + + PER2 + Periodic Interval 2 + 2 + 1 + + + PER3 + Periodic Interval 3 + 3 + 1 + + + PER4 + Periodic Interval 4 + 4 + 1 + + + PER5 + Periodic Interval 5 + 5 + 1 + + + PER6 + Periodic Interval 6 + 6 + 1 + + + PER7 + Periodic Interval 7 + 7 + 1 + + + CMP0 + Compare 0 + 8 + 1 + + + CMP1 + Compare 1 + 9 + 1 + + + TAMPER + Tamper + 14 + 1 + + + OVF + Overflow + 15 + 1 + + + + + DBGCTRL + Debug Control + 0x0E + 8 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + MODE1 Synchronization Busy Status + 0x10 + 32 + read-only + + + SWRST + Software Reset Bit Busy + 0 + 1 + read-only + + + ENABLE + Enable Bit Busy + 1 + 1 + read-only + + + FREQCORR + FREQCORR Register Busy + 2 + 1 + read-only + + + COUNT + COUNT Register Busy + 3 + 1 + read-only + + + PER + PER Register Busy + 4 + 1 + read-only + + + COMP0 + COMP 0 Register Busy + 5 + 1 + read-only + + + COMP1 + COMP 1 Register Busy + 6 + 1 + read-only + + + COUNTSYNC + Count Synchronization Enable Bit Busy + 15 + 1 + read-only + + + GP0 + General Purpose 0 Register Busy + 16 + 1 + read-only + + + GP1 + General Purpose 1 Register Busy + 17 + 1 + read-only + + + + + FREQCORR + Frequency Correction + 0x14 + 8 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + COUNT + MODE1 Counter Value + 0x18 + 16 + + + COUNT + Counter Value + 0 + 16 + + + + + PER + MODE1 Counter Period + 0x1C + 16 + + + PER + Counter Period + 0 + 16 + + + + + 2 + 0x2 + COMP%s + MODE1 Compare n Value + 0x20 + 16 + + + COMP + Compare Value + 0 + 16 + + + + + 2 + 0x4 + GP%s + General Purpose + 0x40 + 32 + + + GP + General Purpose + 0 + 32 + + + + + TAMPCTRL + Tamper Control + 0x60 + 32 + + + IN0ACT + Tamper Input 0 Action + 0 + 2 + + IN0ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN0 to OUT + 0x3 + + + + + IN1ACT + Tamper Input 1 Action + 2 + 2 + + IN1ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN1 to OUT + 0x3 + + + + + IN2ACT + Tamper Input 2 Action + 4 + 2 + + IN2ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN2 to OUT + 0x3 + + + + + IN3ACT + Tamper Input 3 Action + 6 + 2 + + IN3ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN3 to OUT + 0x3 + + + + + IN4ACT + Tamper Input 4 Action + 8 + 2 + + IN4ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN4 to OUT + 0x3 + + + + + TAMLVL0 + Tamper Level Select 0 + 16 + 1 + + + TAMLVL1 + Tamper Level Select 1 + 17 + 1 + + + TAMLVL2 + Tamper Level Select 2 + 18 + 1 + + + TAMLVL3 + Tamper Level Select 3 + 19 + 1 + + + TAMLVL4 + Tamper Level Select 4 + 20 + 1 + + + DEBNC0 + Debouncer Enable 0 + 24 + 1 + + + DEBNC1 + Debouncer Enable 1 + 25 + 1 + + + DEBNC2 + Debouncer Enable 2 + 26 + 1 + + + DEBNC3 + Debouncer Enable 3 + 27 + 1 + + + DEBNC4 + Debouncer Enable 4 + 28 + 1 + + + + + TIMESTAMP + MODE1 Timestamp + 0x64 + 32 + read-only + + + COUNT + Count Timestamp Value + 0 + 16 + read-only + + + + + TAMPID + Tamper ID + 0x68 + 32 + + + TAMPID0 + Tamper Input 0 Detected + 0 + 1 + + + TAMPID1 + Tamper Input 1 Detected + 1 + 1 + + + TAMPID2 + Tamper Input 2 Detected + 2 + 1 + + + TAMPID3 + Tamper Input 3 Detected + 3 + 1 + + + TAMPID4 + Tamper Input 4 Detected + 4 + 1 + + + TAMPEVT + Tamper Event Detected + 31 + 1 + + + + + 8 + 0x4 + BKUP%s + Backup + 0x80 + 32 + + + BKUP + Backup + 0 + 32 + + + + + + MODE2 + Clock/Calendar with Alarm + MODE0 + RtcMode2 + 0x0 + + CTRLA + MODE2 Control A + 0x00 + 16 + + + SWRST + Software Reset + 0 + 1 + write-only + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0x0 + + + COUNT16 + Mode 1: 16-bit Counter + 0x1 + + + CLOCK + Mode 2: Clock/Calendar + 0x2 + + + + + CLKREP + Clock Representation + 6 + 1 + + + MATCHCLR + Clear on Match + 7 + 1 + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + OFF + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x1 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x2 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x3 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x4 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x5 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x6 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x7 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x8 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x9 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0xa + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xb + + + + + BKTRST + BKUP Registers Reset On Tamper Enable + 13 + 1 + + + GPTRST + GP Registers Reset On Tamper Enable + 14 + 1 + + + CLOCKSYNC + Clock Read Synchronization Enable + 15 + 1 + + + + + CTRLB + MODE2 Control B + 0x02 + 16 + + + GP0EN + General Purpose 0 Enable + 0 + 1 + + + DEBMAJ + Debouncer Majority Enable + 4 + 1 + + + DEBASYNC + Debouncer Asynchronous Enable + 5 + 1 + + + RTCOUT + RTC Output Enable + 6 + 1 + + + DMAEN + DMA Enable + 7 + 1 + + + DEBF + Debounce Freqnuency + 8 + 3 + + DEBFSelect + + DIV2 + CLK_RTC_DEB = CLK_RTC/2 + 0x0 + + + DIV4 + CLK_RTC_DEB = CLK_RTC/4 + 0x1 + + + DIV8 + CLK_RTC_DEB = CLK_RTC/8 + 0x2 + + + DIV16 + CLK_RTC_DEB = CLK_RTC/16 + 0x3 + + + DIV32 + CLK_RTC_DEB = CLK_RTC/32 + 0x4 + + + DIV64 + CLK_RTC_DEB = CLK_RTC/64 + 0x5 + + + DIV128 + CLK_RTC_DEB = CLK_RTC/128 + 0x6 + + + DIV256 + CLK_RTC_DEB = CLK_RTC/256 + 0x7 + + + + + ACTF + Active Layer Freqnuency + 12 + 3 + + ACTFSelect + + DIV2 + CLK_RTC_OUT = CLK_RTC/2 + 0x0 + + + DIV4 + CLK_RTC_OUT = CLK_RTC/4 + 0x1 + + + DIV8 + CLK_RTC_OUT = CLK_RTC/8 + 0x2 + + + DIV16 + CLK_RTC_OUT = CLK_RTC/16 + 0x3 + + + DIV32 + CLK_RTC_OUT = CLK_RTC/32 + 0x4 + + + DIV64 + CLK_RTC_OUT = CLK_RTC/64 + 0x5 + + + DIV128 + CLK_RTC_OUT = CLK_RTC/128 + 0x6 + + + DIV256 + CLK_RTC_OUT = CLK_RTC/256 + 0x7 + + + + + + + EVCTRL + MODE2 Event Control + 0x04 + 32 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + ALARMEO0 + Alarm 0 Event Output Enable + 8 + 1 + + + TAMPEREO + Tamper Event Output Enable + 14 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + TAMPEVEI + Tamper Event Input Enable + 16 + 1 + + + + + INTENCLR + MODE2 Interrupt Enable Clear + 0x08 + 16 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + ALARM0 + Alarm 0 Interrupt Enable + 8 + 1 + + + TAMPER + Tamper Enable + 14 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTENSET + MODE2 Interrupt Enable Set + 0x0A + 16 + + + PER0 + Periodic Interval 0 Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Enable + 7 + 1 + + + ALARM0 + Alarm 0 Interrupt Enable + 8 + 1 + + + TAMPER + Tamper Enable + 14 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTFLAG + MODE2 Interrupt Flag Status and Clear + 0x0C + 16 + + + PER0 + Periodic Interval 0 + 0 + 1 + + + PER1 + Periodic Interval 1 + 1 + 1 + + + PER2 + Periodic Interval 2 + 2 + 1 + + + PER3 + Periodic Interval 3 + 3 + 1 + + + PER4 + Periodic Interval 4 + 4 + 1 + + + PER5 + Periodic Interval 5 + 5 + 1 + + + PER6 + Periodic Interval 6 + 6 + 1 + + + PER7 + Periodic Interval 7 + 7 + 1 + + + ALARM0 + Alarm 0 + 8 + 1 + + + TAMPER + Tamper + 14 + 1 + + + OVF + Overflow + 15 + 1 + + + + + DBGCTRL + Debug Control + 0x0E + 8 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + MODE2 Synchronization Busy Status + 0x10 + 32 + read-only + + + SWRST + Software Reset Bit Busy + 0 + 1 + read-only + + + ENABLE + Enable Bit Busy + 1 + 1 + read-only + + + FREQCORR + FREQCORR Register Busy + 2 + 1 + read-only + + + CLOCK + CLOCK Register Busy + 3 + 1 + read-only + + + ALARM0 + ALARM 0 Register Busy + 5 + 1 + read-only + + + MASK0 + MASK 0 Register Busy + 11 + 1 + read-only + + + CLOCKSYNC + Clock Synchronization Enable Bit Busy + 15 + 1 + read-only + + + GP0 + General Purpose 0 Register Busy + 16 + 1 + read-only + + + GP1 + General Purpose 1 Register Busy + 17 + 1 + read-only + + + + + FREQCORR + Frequency Correction + 0x14 + 8 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + CLOCK + MODE2 Clock Value + 0x18 + 32 + + + SECOND + Second + 0 + 6 + + + MINUTE + Minute + 6 + 6 + + + HOUR + Hour + 12 + 5 + + HOURSelect + + AM + AM when CLKREP in 12-hour + 0x0 + + + PM + PM when CLKREP in 12-hour + 0x10 + + + + + DAY + Day + 17 + 5 + + + MONTH + Month + 22 + 4 + + + YEAR + Year + 26 + 6 + + + + + 1 + 0x8 + ALARM%s + MODE2 Alarm n Value + 0x20 + 32 + + + SECOND + Second + 0 + 6 + + + MINUTE + Minute + 6 + 6 + + + HOUR + Hour + 12 + 5 + + HOURSelect + + AM + Morning hour + 0x0 + + + PM + Afternoon hour + 0x10 + + + + + DAY + Day + 17 + 5 + + + MONTH + Month + 22 + 4 + + + YEAR + Year + 26 + 6 + + + + + 1 + 0x8 + MASK%s + MODE2 Alarm n Mask + 0x24 + 8 + + + SEL + Alarm Mask Selection + 0 + 3 + + SELSelect + + OFF + Alarm Disabled + 0x0 + + + SS + Match seconds only + 0x1 + + + MMSS + Match seconds and minutes only + 0x2 + + + HHMMSS + Match seconds, minutes, and hours only + 0x3 + + + DDHHMMSS + Match seconds, minutes, hours, and days only + 0x4 + + + MMDDHHMMSS + Match seconds, minutes, hours, days, and months only + 0x5 + + + YYMMDDHHMMSS + Match seconds, minutes, hours, days, months, and years + 0x6 + + + + + + + 2 + 0x4 + GP%s + General Purpose + 0x40 + 32 + + + GP + General Purpose + 0 + 32 + + + + + TAMPCTRL + Tamper Control + 0x60 + 32 + + + IN0ACT + Tamper Input 0 Action + 0 + 2 + + IN0ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN0 to OUT + 0x3 + + + + + IN1ACT + Tamper Input 1 Action + 2 + 2 + + IN1ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN1 to OUT + 0x3 + + + + + IN2ACT + Tamper Input 2 Action + 4 + 2 + + IN2ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN2 to OUT + 0x3 + + + + + IN3ACT + Tamper Input 3 Action + 6 + 2 + + IN3ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN3 to OUT + 0x3 + + + + + IN4ACT + Tamper Input 4 Action + 8 + 2 + + IN4ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN4 to OUT + 0x3 + + + + + TAMLVL0 + Tamper Level Select 0 + 16 + 1 + + + TAMLVL1 + Tamper Level Select 1 + 17 + 1 + + + TAMLVL2 + Tamper Level Select 2 + 18 + 1 + + + TAMLVL3 + Tamper Level Select 3 + 19 + 1 + + + TAMLVL4 + Tamper Level Select 4 + 20 + 1 + + + DEBNC0 + Debouncer Enable 0 + 24 + 1 + + + DEBNC1 + Debouncer Enable 1 + 25 + 1 + + + DEBNC2 + Debouncer Enable 2 + 26 + 1 + + + DEBNC3 + Debouncer Enable 3 + 27 + 1 + + + DEBNC4 + Debouncer Enable 4 + 28 + 1 + + + + + TIMESTAMP + MODE2 Timestamp + 0x64 + 32 + read-only + + + SECOND + Second Timestamp Value + 0 + 6 + read-only + + + MINUTE + Minute Timestamp Value + 6 + 6 + read-only + + + HOUR + Hour Timestamp Value + 12 + 5 + read-only + + HOURSelect + + AM + AM when CLKREP in 12-hour + 0x0 + + + PM + PM when CLKREP in 12-hour + 0x10 + + + + + DAY + Day Timestamp Value + 17 + 5 + read-only + + + MONTH + Month Timestamp Value + 22 + 4 + read-only + + + YEAR + Year Timestamp Value + 26 + 6 + read-only + + + + + TAMPID + Tamper ID + 0x68 + 32 + + + TAMPID0 + Tamper Input 0 Detected + 0 + 1 + + + TAMPID1 + Tamper Input 1 Detected + 1 + 1 + + + TAMPID2 + Tamper Input 2 Detected + 2 + 1 + + + TAMPID3 + Tamper Input 3 Detected + 3 + 1 + + + TAMPID4 + Tamper Input 4 Detected + 4 + 1 + + + TAMPEVT + Tamper Event Detected + 31 + 1 + + + + + 8 + 0x4 + BKUP%s + Backup + 0x80 + 32 + + + BKUP + Backup + 0 + 32 + + + + + + + + SERCOM0 + 4.0.0 + Serial Communication Interface 0 + SERCOM + SERCOM_ + 0x42000400 + + 0 + 0x40 + registers + + + SERCOM0 + 9 + + + + I2CM + I2C Master Mode + SercomI2cm + 0x0 + + CTRLA + I2CM Control A + 0x00 + 32 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + + RUNSTDBY + Run in Standby + 7 + 1 + + + PINOUT + Pin Usage + 16 + 1 + + + SDAHOLD + SDA Hold Time + 20 + 2 + + + MEXTTOEN + Master SCL Low Extend Timeout + 22 + 1 + + + SEXTTOEN + Slave SCL Low Extend Timeout + 23 + 1 + + + SPEED + Transfer Speed + 24 + 2 + + + SCLSM + SCL Clock Stretch Mode + 27 + 1 + + + INACTOUT + Inactive Time-Out + 28 + 2 + + + LOWTOUTEN + SCL Low Timeout Enable + 30 + 1 + + + + + CTRLB + I2CM Control B + 0x04 + 32 + + + SMEN + Smart Mode Enable + 8 + 1 + + + QCEN + Quick Command Enable + 9 + 1 + + + CMD + Command + 16 + 2 + write-only + + + ACKACT + Acknowledge Action + 18 + 1 + + + + + BAUD + I2CM Baud Rate + 0x0C + 32 + + + BAUD + Baud Rate Value + 0 + 8 + + + BAUDLOW + Baud Rate Value Low + 8 + 8 + + + HSBAUD + High Speed Baud Rate Value + 16 + 8 + + + HSBAUDLOW + High Speed Baud Rate Value Low + 24 + 8 + + + + + INTENCLR + I2CM Interrupt Enable Clear + 0x14 + 8 + + + MB + Master On Bus Interrupt Disable + 0 + 1 + + + SB + Slave On Bus Interrupt Disable + 1 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + I2CM Interrupt Enable Set + 0x16 + 8 + + + MB + Master On Bus Interrupt Enable + 0 + 1 + + + SB + Slave On Bus Interrupt Enable + 1 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + I2CM Interrupt Flag Status and Clear + 0x18 + 8 + + + MB + Master On Bus Interrupt + 0 + 1 + + + SB + Slave On Bus Interrupt + 1 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + I2CM Status + 0x1A + 16 + + + BUSERR + Bus Error + 0 + 1 + + + ARBLOST + Arbitration Lost + 1 + 1 + + + RXNACK + Received Not Acknowledge + 2 + 1 + read-only + + + BUSSTATE + Bus State + 4 + 2 + + + LOWTOUT + SCL Low Timeout + 6 + 1 + + + CLKHOLD + Clock Hold + 7 + 1 + read-only + + + MEXTTOUT + Master SCL Low Extend Timeout + 8 + 1 + + + SEXTTOUT + Slave SCL Low Extend Timeout + 9 + 1 + + + LENERR + Length Error + 10 + 1 + + + + + SYNCBUSY + I2CM Synchronization Busy + 0x1C + 32 + read-only + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + read-only + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + read-only + + + SYSOP + System Operation Synchronization Busy + 2 + 1 + read-only + + + + + ADDR + I2CM Address + 0x24 + 32 + + + ADDR + Address Value + 0 + 11 + + + LENEN + Length Enable + 13 + 1 + + + HS + High Speed Mode + 14 + 1 + + + TENBITEN + Ten Bit Addressing Enable + 15 + 1 + + + LEN + Length + 16 + 8 + + + + + DATA + I2CM Data + 0x28 + 8 + + + DATA + Data Value + 0 + 8 + + + + + DBGCTRL + I2CM Debug Control + 0x30 + 8 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + I2CS + I2C Slave Mode + I2CM + SercomI2cs + 0x0 + + CTRLA + I2CS Control A + 0x00 + 32 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + + RUNSTDBY + Run during Standby + 7 + 1 + + + PINOUT + Pin Usage + 16 + 1 + + + SDAHOLD + SDA Hold Time + 20 + 2 + + + SEXTTOEN + Slave SCL Low Extend Timeout + 23 + 1 + + + SPEED + Transfer Speed + 24 + 2 + + + SCLSM + SCL Clock Stretch Mode + 27 + 1 + + + LOWTOUTEN + SCL Low Timeout Enable + 30 + 1 + + + + + CTRLB + I2CS Control B + 0x04 + 32 + + + SMEN + Smart Mode Enable + 8 + 1 + + + GCMD + PMBus Group Command + 9 + 1 + + + AACKEN + Automatic Address Acknowledge + 10 + 1 + + + AMODE + Address Mode + 14 + 2 + + + CMD + Command + 16 + 2 + write-only + + + ACKACT + Acknowledge Action + 18 + 1 + + + + + INTENCLR + I2CS Interrupt Enable Clear + 0x14 + 8 + + + PREC + Stop Received Interrupt Disable + 0 + 1 + + + AMATCH + Address Match Interrupt Disable + 1 + 1 + + + DRDY + Data Interrupt Disable + 2 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + I2CS Interrupt Enable Set + 0x16 + 8 + + + PREC + Stop Received Interrupt Enable + 0 + 1 + + + AMATCH + Address Match Interrupt Enable + 1 + 1 + + + DRDY + Data Interrupt Enable + 2 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + I2CS Interrupt Flag Status and Clear + 0x18 + 8 + + + PREC + Stop Received Interrupt + 0 + 1 + + + AMATCH + Address Match Interrupt + 1 + 1 + + + DRDY + Data Interrupt + 2 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + I2CS Status + 0x1A + 16 + + + BUSERR + Bus Error + 0 + 1 + + + COLL + Transmit Collision + 1 + 1 + + + RXNACK + Received Not Acknowledge + 2 + 1 + read-only + + + DIR + Read/Write Direction + 3 + 1 + read-only + + + SR + Repeated Start + 4 + 1 + read-only + + + LOWTOUT + SCL Low Timeout + 6 + 1 + + + CLKHOLD + Clock Hold + 7 + 1 + read-only + + + SEXTTOUT + Slave SCL Low Extend Timeout + 9 + 1 + + + HS + High Speed + 10 + 1 + + + + + SYNCBUSY + I2CS Synchronization Busy + 0x1C + 32 + read-only + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + read-only + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + read-only + + + + + ADDR + I2CS Address + 0x24 + 32 + + + GENCEN + General Call Address Enable + 0 + 1 + + + ADDR + Address Value + 1 + 10 + + + TENBITEN + Ten Bit Addressing Enable + 15 + 1 + + + ADDRMASK + Address Mask + 17 + 10 + + + + + DATA + I2CS Data + 0x28 + 8 + + + DATA + Data Value + 0 + 8 + + + + + + SPI + SPI Mode + I2CM + SercomSpi + 0x0 + + CTRLA + SPI Control A + 0x00 + 32 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + DOPO + Data Out Pinout + 16 + 2 + + + DIPO + Data In Pinout + 20 + 2 + + + FORM + Frame Format + 24 + 4 + + + CPHA + Clock Phase + 28 + 1 + + + CPOL + Clock Polarity + 29 + 1 + + + DORD + Data Order + 30 + 1 + + + + + CTRLB + SPI Control B + 0x04 + 32 + + + CHSIZE + Character Size + 0 + 3 + + + PLOADEN + Data Preload Enable + 6 + 1 + + + SSDE + Slave Select Low Detect Enable + 9 + 1 + + + MSSEN + Master Slave Select Enable + 13 + 1 + + + AMODE + Address Mode + 14 + 2 + + + RXEN + Receiver Enable + 17 + 1 + + + + + BAUD + SPI Baud Rate + 0x0C + 8 + + + BAUD + Baud Rate Value + 0 + 8 + + + + + INTENCLR + SPI Interrupt Enable Clear + 0x14 + 8 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + SSL + Slave Select Low Interrupt Disable + 3 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + SPI Interrupt Enable Set + 0x16 + 8 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + SSL + Slave Select Low Interrupt Enable + 3 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + SPI Interrupt Flag Status and Clear + 0x18 + 8 + + + DRE + Data Register Empty Interrupt + 0 + 1 + read-only + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + read-only + + + SSL + Slave Select Low Interrupt Flag + 3 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + SPI Status + 0x1A + 16 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + + + SYNCBUSY + SPI Synchronization Busy + 0x1C + 32 + read-only + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + read-only + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + read-only + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + read-only + + + + + ADDR + SPI Address + 0x24 + 32 + + + ADDR + Address Value + 0 + 8 + + + ADDRMASK + Address Mask + 16 + 8 + + + + + DATA + SPI Data + 0x28 + 32 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + SPI Debug Control + 0x30 + 8 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + USART + USART Mode + I2CM + SercomUsart + 0x0 + + CTRLA + USART Control A + 0x00 + 32 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + TXINV + Transmit Data Invert + 9 + 1 + + + RXINV + Receive Data Invert + 10 + 1 + + + SAMPR + Sample + 13 + 3 + + + TXPO + Transmit Data Pinout + 16 + 2 + + + RXPO + Receive Data Pinout + 20 + 2 + + + SAMPA + Sample Adjustment + 22 + 2 + + + FORM + Frame Format + 24 + 4 + + + CMODE + Communication Mode + 28 + 1 + + + CPOL + Clock Polarity + 29 + 1 + + + DORD + Data Order + 30 + 1 + + + + + CTRLB + USART Control B + 0x04 + 32 + + + CHSIZE + Character Size + 0 + 3 + + + SBMODE + Stop Bit Mode + 6 + 1 + + + COLDEN + Collision Detection Enable + 8 + 1 + + + SFDE + Start of Frame Detection Enable + 9 + 1 + + + ENC + Encoding Format + 10 + 1 + + + PMODE + Parity Mode + 13 + 1 + + + TXEN + Transmitter Enable + 16 + 1 + + + RXEN + Receiver Enable + 17 + 1 + + + + + CTRLC + USART Control C + 0x08 + 32 + + + GTIME + Guard Time + 0 + 3 + + + INACK + Inhibit Not Acknowledge + 16 + 1 + + + DSNACK + Disable Successive NACK + 17 + 1 + + + MAXITER + Maximum Iterations + 20 + 3 + + + + + BAUD + USART Baud Rate + 0x0C + 16 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + BAUD_FRAC_MODE + USART Baud Rate + BAUD + 0x0C + 16 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_FRACFP_MODE + USART Baud Rate + BAUD + 0x0C + 16 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_USARTFP_MODE + USART Baud Rate + BAUD + 0x0C + 16 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + RXPL + USART Receive Pulse Length + 0x0E + 8 + + + RXPL + Receive Pulse Length + 0 + 8 + + + + + INTENCLR + USART Interrupt Enable Clear + 0x14 + 8 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + RXS + Receive Start Interrupt Disable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Disable + 4 + 1 + + + RXBRK + Break Received Interrupt Disable + 5 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + USART Interrupt Enable Set + 0x16 + 8 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + RXS + Receive Start Interrupt Enable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Enable + 4 + 1 + + + RXBRK + Break Received Interrupt Enable + 5 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + USART Interrupt Flag Status and Clear + 0x18 + 8 + + + DRE + Data Register Empty Interrupt + 0 + 1 + read-only + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + read-only + + + RXS + Receive Start Interrupt + 3 + 1 + write-only + + + CTSIC + Clear To Send Input Change Interrupt + 4 + 1 + + + RXBRK + Break Received Interrupt + 5 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + USART Status + 0x1A + 16 + + + PERR + Parity Error + 0 + 1 + + + FERR + Frame Error + 1 + 1 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + CTS + Clear To Send + 3 + 1 + read-only + + + ISF + Inconsistent Sync Field + 4 + 1 + + + COLL + Collision Detected + 5 + 1 + + + TXE + Transmitter Empty + 6 + 1 + read-only + + + ITER + Maximum Number of Repetitions Reached + 7 + 1 + + + + + SYNCBUSY + USART Synchronization Busy + 0x1C + 32 + read-only + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + read-only + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + read-only + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + read-only + + + + + RXERRCNT + USART Receive Error Count + 0x20 + 8 + read-only + + + DATA + USART Data + 0x28 + 16 + + + DATA + Data Value + 0 + 9 + + + + + DBGCTRL + USART Debug Control + 0x30 + 8 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + + + SERCOM1 + Serial Communication Interface 1 + 0x42000800 + + SERCOM1 + 10 + + + + SERCOM2 + Serial Communication Interface 2 + 0x42000C00 + + SERCOM2 + 11 + + + + SERCOM3 + Serial Communication Interface 3 + 0x42001000 + + SERCOM3 + 12 + + + + SLCD + 1.0.0 + Segment Liquid Crystal Display Controller + SLCD + SLCD_ + 0x42003C00 + + 0 + 0x100 + registers + + + SLCD + 23 + + + + CTRLA + Control A + 0x00 + 32 + 0x03D80000 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + DUTY + Duty Ratio + 2 + 3 + + DUTYSelect + + STATIC + Static duty + 0x0 + + + HALF + 1/2 duty + 0x1 + + + THIRD + 1/3 duty + 0x2 + + + FOURTH + 1/4 duty + 0x3 + + + SIXTH + 1/6 duty + 0x4 + + + EIGHT + 1/8 duty + 0x5 + + + + + WMOD + Waveform Mode + 5 + 1 + + WMODSelect + + LP + Low Power Waveform Mode + 0x0 + + + STD + Standard Waveform Mode + 0x1 + + + + + RUNSTDBY + Run in Standby + 6 + 1 + + + PRESC + Clock Prescaler + 8 + 2 + + PRESCSelect + + PRESC16 + 16 + 0x0 + + + PRESC32 + 32 + 0x1 + + + PRESC64 + 64 + 0x2 + + + PRESC128 + 128 + 0x3 + + + + + CKDIV + Clock Divider + 12 + 3 + + + BIAS + Bias Setting + 16 + 2 + + BIASSelect + + STATIC + Static + 0x0 + + + HALF + 1/2 bias + 0x1 + + + THIRD + 1/3 bias + 0x2 + + + FOURTH + 1/4 bias + 0x3 + + + + + XVLCD + External VLCD + 19 + 1 + + + PRF + Power Refresh Frequency + 20 + 2 + + PRFSelect + + PR2000 + 2kHz + 0x0 + + + PR1000 + 1kHz + 0x1 + + + PR500 + 500Hz + 0x2 + + + PR250 + 250Hz + 0x3 + + + + + DMFCS + Display Memory Update Frame Counter Selection + 22 + 2 + + DMFCSSelect + + FC0 + Frame Counter 0 + 0x0 + + + FC1 + Frame Counter 1 + 0x1 + + + FC2 + Frame Counter 2 + 0x2 + + + NFC + Frame Counter event to DMU is forced to 0 + 0x3 + + + + + RRF + Reference Refresh Frequency + 24 + 3 + + RRFSelect + + RR2000 + 2kHz + 0x0 + + + RR1000 + 1kHz + 0x1 + + + RR500 + 500Hz + 0x2 + + + RR250 + 250Hz + 0x3 + + + RR125 + 125Hz + 0x4 + + + RR62 + 62.5Hz + 0x5 + + + + + + + CTRLB + Control B + 0x04 + 16 + + + BBD + Bias Buffer Enable Duration + 0 + 4 + + + BBEN + Bias Buffer Enable + 7 + 1 + + + LRD + Low Resistance Enable Duration + 8 + 4 + + + LREN + Low Resistance Enable + 15 + 1 + + + + + CTRLC + Control C + 0x06 + 16 + + + CLEAR + Clear Display Memory + 0 + 1 + + + LOCK + Lock Shadow Memory + 1 + 1 + + + ABMEN + Automated Bit Mapping Enable + 2 + 1 + + + ACMEN + Automated Character Mapping Enable + 3 + 1 + + + CTST + Contrast Adjustment + 4 + 4 + + + LPPM + LCD Power Macro Power mode + 8 + 2 + + LPPMSelect + + AUTO + LCD power automatically select regualation mode or pump mode + 0x0 + + + STEPUP + LCD power use step-up pump loop only + 0x1 + + + STEPDOWN + LCD power use step-down drop-out regulation loop only + 0x2 + + + + + + + CTRLD + Control D + 0x08 + 8 + 0x80 + + + BLANK + Blank LCD + 0 + 1 + + + BLINK + Blinking Enable + 1 + 1 + + + CSREN + Circular Shift Register Enable + 2 + 1 + + + FC0EN + Frame Counter 0 Enable + 4 + 1 + + + FC1EN + Frame Counter 1 Enable + 5 + 1 + + + FC2EN + Frame Counter 2 Enable + 6 + 1 + + + DISPEN + Display enable + 7 + 1 + + + + + EVCTRL + Event Control + 0x0C + 8 + + + FC0OEO + Frame Counter 0 Overflow Event Output Enable + 0 + 1 + + + FC1OEO + Frame Counter 1 Overflow Event Output Enable + 1 + 1 + + + FC2OEO + Frame Counter 2 Overflow Event Output Enable + 2 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x0D + 8 + + + FC0O + Frame Counter 0 Overflow Interrupt Disable + 0 + 1 + + + FC1O + Frame Counter 1 Overflow Interrupt Disable + 1 + 1 + + + FC2O + Frame Counter 2 Overflow Interrupt Disable + 2 + 1 + + + VLCDRT + VLCD Ready Toggle Interrupt Disable + 3 + 1 + + + VLCDST + VLCD Status Toggle Interrupt Disable + 4 + 1 + + + PRST + Pump Run Status Toggle Interrupt Disable + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x0E + 8 + + + FC0O + Frame Counter 0 Overflow Interrupt Enable + 0 + 1 + + + FC1O + Frame Counter 1 Overflow Interrupt Enable + 1 + 1 + + + FC2O + Frame Counter 2 Overflow Interrupt Enable + 2 + 1 + + + VLCDRT + VLCD Ready Toggle Interrupt Enable + 3 + 1 + + + VLCDST + VLCD Status Toggle Interrupt Enable + 4 + 1 + + + PRST + Pump Run Status Toggle Interrupt Enable + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x0F + 8 + + + FC0O + Frame Counter 0 Overflow + 0 + 1 + + + FC1O + Frame Counter 1 Overflow + 1 + 1 + + + FC2O + Frame Counter 2 Overflow + 2 + 1 + + + VLCDRT + VLCD Ready Toggle + 3 + 1 + + + VLCDST + VLCD Status Toggle + 4 + 1 + + + PRST + Pump Run Status Toggle + 5 + 1 + + + + + STATUS + Status + 0x10 + 8 + read-only + + + VLCDR + VLCD Ready + 0 + 1 + read-only + + + PRUN + LCD Charge Pump is Running + 1 + 1 + read-only + + + VLCDS + VLCD Status + 2 + 1 + read-only + + + CMWRBUSY + Character mapping write busy + 3 + 1 + read-only + + + ACMBUSY + ACM state machine busy + 4 + 1 + read-only + + + ABMBUSY + ABM state machine busy + 5 + 1 + read-only + + + + + SYNCBUSY + Synchronization Busy + 0x14 + 32 + read-only + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + CTRLD + Control D + 2 + 1 + + + + + FC0 + Frame Counter 0 Configuration + 0x18 + 8 + + + OVF + Frame Counter Overflow Value + 0 + 5 + + + PB + Prescaler Bypass + 7 + 1 + + + + + FC1 + Frame Counter 1 Configuration + 0x19 + 8 + + + OVF + Frame Counter Overflow Value + 0 + 5 + + + PB + Prescaler Bypass + 7 + 1 + + + + + FC2 + Frame Counter 2 Configuration + 0x1A + 8 + + + OVF + Frame Counter Overflow Value + 0 + 5 + + + PB + Prescaler Bypass + 7 + 1 + + + + + LPENL + LCD Pin Enable Low + 0x1C + 32 + + + LPEN + LCD Pin Enable + 0 + 32 + + + + + LPENH + LCD Pin Enable High + 0x20 + 32 + + + LPEN + LCD Pin Enable + 0 + 20 + + + + + SDATAL0 + Segments Data Low for COM0 Line + 0x24 + 32 + + + SDATA + Segments Data + 0 + 32 + + + + + SDATAH0 + Segments Data High for COM0 Line + 0x28 + 32 + + + SDATA + Segments Data + 0 + 12 + + + + + SDATAL1 + Segments Data Low for COM1 Line + 0x2C + 32 + + + SDATA + Segments Data + 0 + 32 + + + + + SDATAH1 + Segments Data High for COM1 Line + 0x30 + 32 + + + SDATA + Segments Data + 0 + 12 + + + + + SDATAL2 + Segments Data Low for COM2 Line + 0x34 + 32 + + + SDATA + Segments Data + 0 + 32 + + + + + SDATAH2 + Segments Data High for COM2 Line + 0x38 + 32 + + + SDATA + Segments Data + 0 + 12 + + + + + SDATAL3 + Segments Data Low for COM3 Line + 0x3C + 32 + + + SDATA + Segments Data + 0 + 32 + + + + + SDATAH3 + Segments Data High for COM3 Line + 0x40 + 32 + + + SDATA + Segments Data + 0 + 12 + + + + + SDATAL4 + Segments Data Low for COM4 Line + 0x44 + 32 + + + SDATA + Segments Data + 0 + 32 + + + + + SDATAH4 + Segments Data High for COM4 Line + 0x48 + 32 + + + SDATA + Segments Data + 0 + 10 + + + + + SDATAL5 + Segments Data Low for COM5 Line + 0x4C + 32 + + + SDATA + Segments Data + 0 + 32 + + + + + SDATAH5 + Segments Data High for COM5 Line + 0x50 + 32 + + + SDATA + Segments Data + 0 + 10 + + + + + SDATAL6 + Segments Data Low for COM6 Line + 0x54 + 32 + + + SDATA + Segments Data + 0 + 32 + + + + + SDATAH6 + Segments Data High for COM6 Line + 0x58 + 32 + + + SDATA + Segments Data + 0 + 8 + + + + + SDATAL7 + Segments Data Low for COM7 Line + 0x5C + 32 + + + SDATA + Segments Data + 0 + 32 + + + + + SDATAH7 + Segments Data High for COM7 Line + 0x60 + 32 + + + SDATA + Segments Data + 0 + 8 + + + + + ISDATA + Indirect Segments Data Access + 0x64 + 32 + write-only + + + SDATA + Segments Data + 0 + 8 + + + SDMASK + Segments Data Mask + 8 + 8 + + + OFF + Byte Offset + 16 + 6 + + + + + BCFG + Blink Configuration + 0x68 + 32 + + + MODE + Blinking Mode + 0 + 1 + + MODESelect + + BLINKALL + Blink all segments + 0x0 + + + BLINKSEL + Blink selected segments + 0x1 + + + + + FCS + Frame Counter Selection + 1 + 2 + + FCSSelect + + FC0 + Frame Counter 0 + 0x0 + + + FC1 + Frame Counter 1 + 0x1 + + + FC2 + Frame Counter 2 + 0x2 + + + + + BSS0 + Blink Segment Selection 0 + 8 + 8 + + + BSS1 + Blink Segment Selection 1 + 16 + 8 + + + + + CSRCFG + Circular Shift Register Configuration + 0x6C + 32 + + + DIR + Direction + 0 + 1 + + + FCS + Frame Counter Selection + 1 + 2 + + FCSSelect + + FC0 + Frame Counter 0 + 0x0 + + + FC1 + Frame Counter 1 + 0x1 + + + FC2 + Frame Counter 2 + 0x2 + + + + + SIZE + Circular Shift Register Size + 4 + 4 + + + DATA + Circular Shift Register Value + 8 + 16 + + + + + CMCFG + Character Mapping Configuration + 0x70 + 8 + + + NSEG + Number of SEG lines + 0 + 3 + + + DEC + Decrement SEG Line Index + 3 + 1 + + + + + ACMCFG + Automated Character Mapping Configuration + 0x74 + 32 + + + NCOM + COM Lines per Row + 0 + 3 + + + NDIG + Number of Digit + 4 + 4 + + + STEPS + Scrolling Steps + 8 + 8 + + + NDROW + Number of Digit per Row + 16 + 6 + + + MODE + Mode + 23 + 1 + + MODESelect + + SEQ + Sequential Display Mode + 0x0 + + + SCROLL + Scrolling Display Mode + 0x1 + + + + + STSEG + Start SEG Line + 24 + 6 + + + FCS + Frame Counter Selection + 30 + 2 + + FCSSelect + + FC0 + Frame Counter 0 + 0x0 + + + FC1 + Frame Counter 1 + 0x1 + + + FC2 + Frame Counter 2 + 0x2 + + + + + + + ABMCFG + Automated Bit Mapping Configuration + 0x78 + 8 + + + FCS + Frame Counter Selection + 0 + 2 + + FCSSelect + + FC0 + Frame Counter 0 + 0x0 + + + FC1 + Frame Counter 1 + 0x1 + + + FC2 + Frame Counter 2 + 0x2 + + + + + SIZE + Size + 2 + 6 + + + + + CMDATA + Character Mapping Segments Data + 0x7C + 32 + write-only + + + SDATA + Segments Data + 0 + 24 + + + + + CMDMASK + Character Mapping Segments Data Mask + 0x80 + 32 + + + SDMASK + Segments Data Mask + 0 + 24 + + + + + CMINDEX + Character Mapping SEG/COM Index + 0x84 + 16 + + + SINDEX + SEG Line Index + 0 + 6 + + + CINDEX + COM Line Index + 8 + 3 + + + + + + + SUPC + 3.0.0 + Supply Controller + SUPC + SUPC_ + 0x40001800 + + 0 + 0x80 + registers + + + SYSTEM + 0 + + + + INTENCLR + Interrupt Enable Clear + 0x00 + 32 + + + BOD33RDY + BOD33 Ready + 0 + 1 + + + BOD33DET + BOD33 Detection + 1 + 1 + + + B33SRDY + BOD33 Synchronization Ready + 2 + 1 + + + BOD12RDY + BOD12 Ready + 3 + 1 + + + BOD12DET + BOD12 Detection + 4 + 1 + + + B12SRDY + BOD12 Synchronization Ready + 5 + 1 + + + VREGRDY + Voltage Regulator Ready + 8 + 1 + + + APWSRDY + Automatic Power Switch Ready + 9 + 1 + + + VCORERDY + VDDCORE Ready + 10 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x04 + 32 + + + BOD33RDY + BOD33 Ready + 0 + 1 + + + BOD33DET + BOD33 Detection + 1 + 1 + + + B33SRDY + BOD33 Synchronization Ready + 2 + 1 + + + BOD12RDY + BOD12 Ready + 3 + 1 + + + BOD12DET + BOD12 Detection + 4 + 1 + + + B12SRDY + BOD12 Synchronization Ready + 5 + 1 + + + VREGRDY + Voltage Regulator Ready + 8 + 1 + + + APWSRDY + Automatic Power Switch Ready + 9 + 1 + + + VCORERDY + VDDCORE Ready + 10 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x08 + 32 + + + BOD33RDY + BOD33 Ready + 0 + 1 + + + BOD33DET + BOD33 Detection + 1 + 1 + + + B33SRDY + BOD33 Synchronization Ready + 2 + 1 + + + BOD12RDY + BOD12 Ready + 3 + 1 + + + BOD12DET + BOD12 Detection + 4 + 1 + + + B12SRDY + BOD12 Synchronization Ready + 5 + 1 + + + VREGRDY + Voltage Regulator Ready + 8 + 1 + + + APWSRDY + Automatic Power Switch Ready + 9 + 1 + + + VCORERDY + VDDCORE Ready + 10 + 1 + + + + + STATUS + Power and Clocks Status + 0x0C + 32 + read-only + + + BOD33RDY + BOD33 Ready + 0 + 1 + read-only + + + BOD33DET + BOD33 Detection + 1 + 1 + read-only + + + B33SRDY + BOD33 Synchronization Ready + 2 + 1 + read-only + + + BOD12RDY + BOD12 Ready + 3 + 1 + read-only + + + BOD12DET + BOD12 Detection + 4 + 1 + read-only + + + B12SRDY + BOD12 Synchronization Ready + 5 + 1 + read-only + + + VREGRDY + Voltage Regulator Ready + 8 + 1 + read-only + + + APWSRDY + Automatic Power Switch Ready + 9 + 1 + read-only + + + VCORERDY + VDDCORE Ready + 10 + 1 + read-only + + + BBPS + Battery Backup Power Switch + 11 + 1 + read-only + + + + + BOD33 + BOD33 Control + 0x10 + 32 + + + ENABLE + Enable + 1 + 1 + + + HYST + Hysteresis Enable + 2 + 1 + + + ACTION + Action when Threshold Crossed + 3 + 2 + + ACTIONSelect + + NONE + No action + 0x0 + + + RESET + The BOD33 generates a reset + 0x1 + + + INT + The BOD33 generates an interrupt + 0x2 + + + BKUP + The BOD33 puts the device in backup sleep mode if VMON=0 + 0x3 + + + + + STDBYCFG + Configuration in Standby mode + 5 + 1 + + + RUNSTDBY + Run during Standby + 6 + 1 + + + RUNBKUP + Configuration in Backup mode + 7 + 1 + + + ACTCFG + Configuration in Active mode + 8 + 1 + + + VMON + Voltage Monitored in active and standby mode + 10 + 1 + + + PSEL + Prescaler Select + 12 + 4 + + PSELSelect + + DIV2 + Divide clock by 2 + 0x0 + + + DIV4 + Divide clock by 4 + 0x1 + + + DIV8 + Divide clock by 8 + 0x2 + + + DIV16 + Divide clock by 16 + 0x3 + + + DIV32 + Divide clock by 32 + 0x4 + + + DIV64 + Divide clock by 64 + 0x5 + + + DIV128 + Divide clock by 128 + 0x6 + + + DIV256 + Divide clock by 256 + 0x7 + + + DIV512 + Divide clock by 512 + 0x8 + + + DIV1024 + Divide clock by 1024 + 0x9 + + + DIV2048 + Divide clock by 2048 + 0xa + + + DIV4096 + Divide clock by 4096 + 0xb + + + DIV8192 + Divide clock by 8192 + 0xc + + + DIV16384 + Divide clock by 16384 + 0xd + + + DIV32768 + Divide clock by 32768 + 0xe + + + DIV65536 + Divide clock by 65536 + 0xf + + + + + LEVEL + Threshold Level for VDD + 16 + 6 + + + BKUPLEVEL + Threshold Level in backup sleep mode or for VBAT + 24 + 6 + + + + + BOD12 + BOD12 Control + 0x14 + 32 + + + ENABLE + Enable + 1 + 1 + + + HYST + Hysteresis Enable + 2 + 1 + + + ACTION + Action when Threshold Crossed + 3 + 2 + + ACTIONSelect + + NONE + No action + 0x0 + + + RESET + The BOD12 generates a reset + 0x1 + + + INT + The BOD12 generates an interrupt + 0x2 + + + + + STDBYCFG + Configuration in Standby mode + 5 + 1 + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ACTCFG + Configuration in Active mode + 8 + 1 + + + PSEL + Prescaler Select + 12 + 4 + + PSELSelect + + DIV2 + Divide clock by 2 + 0x0 + + + DIV4 + Divide clock by 4 + 0x1 + + + DIV8 + Divide clock by 8 + 0x2 + + + DIV16 + Divide clock by 16 + 0x3 + + + DIV32 + Divide clock by 32 + 0x4 + + + DIV64 + Divide clock by 64 + 0x5 + + + DIV128 + Divide clock by 128 + 0x6 + + + DIV256 + Divide clock by 256 + 0x7 + + + DIV512 + Divide clock by 512 + 0x8 + + + DIV1024 + Divide clock by 1024 + 0x9 + + + DIV2048 + Divide clock by 2048 + 0xa + + + DIV4096 + Divide clock by 4096 + 0xb + + + DIV8192 + Divide clock by 8192 + 0xc + + + DIV16384 + Divide clock by 16384 + 0xd + + + DIV32768 + Divide clock by 32768 + 0xe + + + DIV65536 + Divide clock by 65536 + 0xf + + + + + LEVEL + Threshold Level + 16 + 6 + + + + + VREG + VREG Control + 0x18 + 32 + + + ENABLE + Enable + 1 + 1 + + + SEL + Voltage Regulator Selection in active mode + 2 + 2 + + SELSelect + + LDO + LDO selection + 0x0 + + + BUCK + Buck selection + 0x1 + + + SCVREG + Switched Cap selection + 0x2 + + + + + STDBYPL0 + Standby in PL0 + 5 + 1 + + + RUNSTDBY + Run during Standby + 6 + 1 + + + LPEFF + Low Power efficiency + 8 + 1 + + + VSVSTEP + Voltage Scaling Voltage Step + 16 + 4 + + + VSPER + Voltage Scaling Period + 24 + 8 + + + + + VREF + VREF Control + 0x1C + 32 + + + TSEN + Temperature Sensor Output Enable + 1 + 1 + + + VREFOE + Voltage Reference Output Enable + 2 + 1 + + + TSSEL + Temperature Sensor Selection + 3 + 1 + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + On Demand Contrl + 7 + 1 + + + SEL + Voltage Reference Selection + 16 + 4 + + SELSelect + + 1V0 + 1.0V voltage reference typical value + 0x0 + + + 1V1 + 1.1V voltage reference typical value + 0x1 + + + 1V2 + 1.2V voltage reference typical value + 0x2 + + + 1V25 + 1.25V voltage reference typical value + 0x3 + + + 2V0 + 2.0V voltage reference typical value + 0x4 + + + 2V2 + 2.2V voltage reference typical value + 0x5 + + + 2V4 + 2.4V voltage reference typical value + 0x6 + + + 2V5 + 2.5V voltage reference typical value + 0x7 + + + + + + + BBPS + Battery Backup Power Switch + 0x20 + 32 + + + CONF + Battery Backup Configuration + 0 + 2 + + CONFSelect + + NONE + The backup domain is always supplied by main power + 0x0 + + + APWS + The power switch is handled by the automatic power switch + 0x1 + + + FORCED + The backup domain is always supplied by battery backup power + 0x2 + + + BOD33 + The power switch is handled by the BOD33 + 0x3 + + + + + WAKEEN + Wake Enable + 2 + 1 + + + PSOKEN + Power Supply OK Enable + 3 + 1 + + + + + BKOUT + Backup Output Control + 0x24 + 32 + + + EN + Enable Output + 0 + 2 + + + CLR + Clear Output + 8 + 2 + write-only + + + SET + Set Output + 16 + 2 + write-only + + + RTCTGL + RTC Toggle Output + 24 + 2 + + + + + BKIN + Backup Input Control + 0x28 + 32 + read-only + + + BKIN + Backup Input Value + 0 + 8 + read-only + + + + + + + TC0 + 2.0.0 + Basic Timer Counter 0 + TC + TC_ + 0x42002000 + + 0 + 0x40 + registers + + + TC0 + 16 + + + + COUNT8 + 8-bit Counter Mode + TcCount8 + 0x0 + + CTRLA + Control A + 0x00 + 32 + + + SWRST + Software Reset + 0 + 1 + write-only + + + ENABLE + Enable + 1 + 1 + + + MODE + Timer Counter Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0x0 + + + COUNT8 + Counter in 8-bit mode + 0x1 + + + COUNT32 + Counter in 32-bit mode + 0x2 + + + + + PRESCSYNC + Prescaler and Counter Synchronization + 4 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0x0 + + + PRESC + Reload or reset the counter on next prescaler clock + 0x1 + + + RESYNC + Reload or reset the counter on next generic clock and reset the prescaler counter + 0x2 + + + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + Clock On Demand + 7 + 1 + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0x0 + + + DIV2 + Prescaler: GCLK_TC/2 + 0x1 + + + DIV4 + Prescaler: GCLK_TC/4 + 0x2 + + + DIV8 + Prescaler: GCLK_TC/8 + 0x3 + + + DIV16 + Prescaler: GCLK_TC/16 + 0x4 + + + DIV64 + Prescaler: GCLK_TC/64 + 0x5 + + + DIV256 + Prescaler: GCLK_TC/256 + 0x6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 0x7 + + + + + ALOCK + Auto Lock + 11 + 1 + + + CAPTEN0 + Capture Channel 0 Enable + 16 + 1 + + + CAPTEN1 + Capture Channel 1 Enable + 17 + 1 + + + COPEN0 + Capture On Pin 0 Enable + 20 + 1 + + + COPEN1 + Capture On Pin 1 Enable + 21 + 1 + + + + + CTRLBCLR + Control B Clear + 0x04 + 8 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0x0 + + + RETRIGGER + Force a start, restart or retrigger + 0x1 + + + STOP + Force a stop + 0x2 + + + UPDATE + Force update of double-buffered register + 0x3 + + + READSYNC + Force a read synchronization of COUNT + 0x4 + + + DMAOS + One-shot DMA trigger + 0x5 + + + + + + + CTRLBSET + Control B Set + 0x05 + 8 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0x0 + + + RETRIGGER + Force a start, restart or retrigger + 0x1 + + + STOP + Force a stop + 0x2 + + + UPDATE + Force update of double-buffered register + 0x3 + + + READSYNC + Force a read synchronization of COUNT + 0x4 + + + DMAOS + One-shot DMA trigger + 0x5 + + + + + + + EVCTRL + Event Control + 0x06 + 16 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0x0 + + + RETRIGGER + Start, restart or retrigger TC on event + 0x1 + + + COUNT + Count on event + 0x2 + + + START + Start TC on event + 0x3 + + + STAMP + Time stamp capture + 0x4 + + + PPW + Period catured in CC0, pulse width in CC1 + 0x5 + + + PWP + Period catured in CC1, pulse width in CC0 + 0x6 + + + PW + Pulse width capture + 0x7 + + + + + TCINV + TC Event Input Polarity + 4 + 1 + + + TCEI + TC Event Enable + 5 + 1 + + + OVFEO + Event Output Enable + 8 + 1 + + + MCEO0 + MC Event Output Enable 0 + 12 + 1 + + + MCEO1 + MC Event Output Enable 1 + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x08 + 8 + + + OVF + OVF Interrupt Disable + 0 + 1 + + + ERR + ERR Interrupt Disable + 1 + 1 + + + MC0 + MC Interrupt Disable 0 + 4 + 1 + + + MC1 + MC Interrupt Disable 1 + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x09 + 8 + + + OVF + OVF Interrupt Enable + 0 + 1 + + + ERR + ERR Interrupt Enable + 1 + 1 + + + MC0 + MC Interrupt Enable 0 + 4 + 1 + + + MC1 + MC Interrupt Enable 1 + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x0A + 8 + + + OVF + OVF Interrupt Flag + 0 + 1 + + + ERR + ERR Interrupt Flag + 1 + 1 + + + MC0 + MC Interrupt Flag 0 + 4 + 1 + + + MC1 + MC Interrupt Flag 1 + 5 + 1 + + + + + STATUS + Status + 0x0B + 8 + 0x01 + + + STOP + Stop Status Flag + 0 + 1 + read-only + + + SLAVE + Slave Status Flag + 1 + 1 + read-only + + + PERBUFV + Synchronization Busy Status + 3 + 1 + + + CCBUFV0 + Compare channel buffer 0 valid + 4 + 1 + + + CCBUFV1 + Compare channel buffer 1 valid + 5 + 1 + + + + + WAVE + Waveform Generation Control + 0x0C + 8 + + + WAVEGEN + Waveform Generation Mode + 0 + 2 + + WAVEGENSelect + + NFRQ + Normal frequency + 0x0 + + + MFRQ + Match frequency + 0x1 + + + NPWM + Normal PWM + 0x2 + + + MPWM + Match PWM + 0x3 + + + + + + + DRVCTRL + Control C + 0x0D + 8 + + + INVEN0 + Output Waveform Invert Enable 0 + 0 + 1 + + + INVEN1 + Output Waveform Invert Enable 1 + 1 + 1 + + + + + DBGCTRL + Debug Control + 0x0F + 8 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + Synchronization Status + 0x10 + 32 + read-only + + + SWRST + swrst + 0 + 1 + + + ENABLE + enable + 1 + 1 + + + CTRLB + CTRLB + 2 + 1 + + + STATUS + STATUS + 3 + 1 + + + COUNT + Counter + 4 + 1 + + + PER + Period + 5 + 1 + + + CC0 + Compare Channel 0 + 6 + 1 + + + CC1 + Compare Channel 1 + 7 + 1 + + + + + COUNT + COUNT8 Count + 0x14 + 8 + + + COUNT + Counter Value + 0 + 8 + + + + + PER + COUNT8 Period + 0x1B + 8 + 0xFF + + + PER + Period Value + 0 + 8 + + + + + 2 + 0x1 + CC%s + COUNT8 Compare and Capture + 0x1C + 8 + + + CC + Counter/Compare Value + 0 + 8 + + + + + PERBUF + COUNT8 Period Buffer + 0x2F + 8 + 0xFF + + + PERBUF + Period Buffer Value + 0 + 8 + + + + + 2 + 0x1 + CCBUF%s + COUNT8 Compare and Capture Buffer + 0x30 + 8 + + + CCBUF + Counter/Compare Buffer Value + 0 + 8 + + + + + + COUNT16 + 16-bit Counter Mode + COUNT8 + TcCount16 + 0x0 + + CTRLA + Control A + 0x00 + 32 + + + SWRST + Software Reset + 0 + 1 + write-only + + + ENABLE + Enable + 1 + 1 + + + MODE + Timer Counter Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0x0 + + + COUNT8 + Counter in 8-bit mode + 0x1 + + + COUNT32 + Counter in 32-bit mode + 0x2 + + + + + PRESCSYNC + Prescaler and Counter Synchronization + 4 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0x0 + + + PRESC + Reload or reset the counter on next prescaler clock + 0x1 + + + RESYNC + Reload or reset the counter on next generic clock and reset the prescaler counter + 0x2 + + + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + Clock On Demand + 7 + 1 + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0x0 + + + DIV2 + Prescaler: GCLK_TC/2 + 0x1 + + + DIV4 + Prescaler: GCLK_TC/4 + 0x2 + + + DIV8 + Prescaler: GCLK_TC/8 + 0x3 + + + DIV16 + Prescaler: GCLK_TC/16 + 0x4 + + + DIV64 + Prescaler: GCLK_TC/64 + 0x5 + + + DIV256 + Prescaler: GCLK_TC/256 + 0x6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 0x7 + + + + + ALOCK + Auto Lock + 11 + 1 + + + CAPTEN0 + Capture Channel 0 Enable + 16 + 1 + + + CAPTEN1 + Capture Channel 1 Enable + 17 + 1 + + + COPEN0 + Capture On Pin 0 Enable + 20 + 1 + + + COPEN1 + Capture On Pin 1 Enable + 21 + 1 + + + + + CTRLBCLR + Control B Clear + 0x04 + 8 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0x0 + + + RETRIGGER + Force a start, restart or retrigger + 0x1 + + + STOP + Force a stop + 0x2 + + + UPDATE + Force update of double-buffered register + 0x3 + + + READSYNC + Force a read synchronization of COUNT + 0x4 + + + DMAOS + One-shot DMA trigger + 0x5 + + + + + + + CTRLBSET + Control B Set + 0x05 + 8 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0x0 + + + RETRIGGER + Force a start, restart or retrigger + 0x1 + + + STOP + Force a stop + 0x2 + + + UPDATE + Force update of double-buffered register + 0x3 + + + READSYNC + Force a read synchronization of COUNT + 0x4 + + + DMAOS + One-shot DMA trigger + 0x5 + + + + + + + EVCTRL + Event Control + 0x06 + 16 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0x0 + + + RETRIGGER + Start, restart or retrigger TC on event + 0x1 + + + COUNT + Count on event + 0x2 + + + START + Start TC on event + 0x3 + + + STAMP + Time stamp capture + 0x4 + + + PPW + Period catured in CC0, pulse width in CC1 + 0x5 + + + PWP + Period catured in CC1, pulse width in CC0 + 0x6 + + + PW + Pulse width capture + 0x7 + + + + + TCINV + TC Event Input Polarity + 4 + 1 + + + TCEI + TC Event Enable + 5 + 1 + + + OVFEO + Event Output Enable + 8 + 1 + + + MCEO0 + MC Event Output Enable 0 + 12 + 1 + + + MCEO1 + MC Event Output Enable 1 + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x08 + 8 + + + OVF + OVF Interrupt Disable + 0 + 1 + + + ERR + ERR Interrupt Disable + 1 + 1 + + + MC0 + MC Interrupt Disable 0 + 4 + 1 + + + MC1 + MC Interrupt Disable 1 + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x09 + 8 + + + OVF + OVF Interrupt Enable + 0 + 1 + + + ERR + ERR Interrupt Enable + 1 + 1 + + + MC0 + MC Interrupt Enable 0 + 4 + 1 + + + MC1 + MC Interrupt Enable 1 + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x0A + 8 + + + OVF + OVF Interrupt Flag + 0 + 1 + + + ERR + ERR Interrupt Flag + 1 + 1 + + + MC0 + MC Interrupt Flag 0 + 4 + 1 + + + MC1 + MC Interrupt Flag 1 + 5 + 1 + + + + + STATUS + Status + 0x0B + 8 + 0x01 + + + STOP + Stop Status Flag + 0 + 1 + read-only + + + SLAVE + Slave Status Flag + 1 + 1 + read-only + + + PERBUFV + Synchronization Busy Status + 3 + 1 + + + CCBUFV0 + Compare channel buffer 0 valid + 4 + 1 + + + CCBUFV1 + Compare channel buffer 1 valid + 5 + 1 + + + + + WAVE + Waveform Generation Control + 0x0C + 8 + + + WAVEGEN + Waveform Generation Mode + 0 + 2 + + WAVEGENSelect + + NFRQ + Normal frequency + 0x0 + + + MFRQ + Match frequency + 0x1 + + + NPWM + Normal PWM + 0x2 + + + MPWM + Match PWM + 0x3 + + + + + + + DRVCTRL + Control C + 0x0D + 8 + + + INVEN0 + Output Waveform Invert Enable 0 + 0 + 1 + + + INVEN1 + Output Waveform Invert Enable 1 + 1 + 1 + + + + + DBGCTRL + Debug Control + 0x0F + 8 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + Synchronization Status + 0x10 + 32 + read-only + + + SWRST + swrst + 0 + 1 + + + ENABLE + enable + 1 + 1 + + + CTRLB + CTRLB + 2 + 1 + + + STATUS + STATUS + 3 + 1 + + + COUNT + Counter + 4 + 1 + + + PER + Period + 5 + 1 + + + CC0 + Compare Channel 0 + 6 + 1 + + + CC1 + Compare Channel 1 + 7 + 1 + + + + + COUNT + COUNT16 Count + 0x14 + 16 + + + COUNT + Counter Value + 0 + 16 + + + + + 2 + 0x2 + CC%s + COUNT16 Compare and Capture + 0x1C + 16 + + + CC + Counter/Compare Value + 0 + 16 + + + + + 2 + 0x2 + CCBUF%s + COUNT16 Compare and Capture Buffer + 0x30 + 16 + + + CCBUF + Counter/Compare Buffer Value + 0 + 16 + + + + + + COUNT32 + 32-bit Counter Mode + COUNT8 + TcCount32 + 0x0 + + CTRLA + Control A + 0x00 + 32 + + + SWRST + Software Reset + 0 + 1 + write-only + + + ENABLE + Enable + 1 + 1 + + + MODE + Timer Counter Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0x0 + + + COUNT8 + Counter in 8-bit mode + 0x1 + + + COUNT32 + Counter in 32-bit mode + 0x2 + + + + + PRESCSYNC + Prescaler and Counter Synchronization + 4 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0x0 + + + PRESC + Reload or reset the counter on next prescaler clock + 0x1 + + + RESYNC + Reload or reset the counter on next generic clock and reset the prescaler counter + 0x2 + + + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + Clock On Demand + 7 + 1 + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0x0 + + + DIV2 + Prescaler: GCLK_TC/2 + 0x1 + + + DIV4 + Prescaler: GCLK_TC/4 + 0x2 + + + DIV8 + Prescaler: GCLK_TC/8 + 0x3 + + + DIV16 + Prescaler: GCLK_TC/16 + 0x4 + + + DIV64 + Prescaler: GCLK_TC/64 + 0x5 + + + DIV256 + Prescaler: GCLK_TC/256 + 0x6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 0x7 + + + + + ALOCK + Auto Lock + 11 + 1 + + + CAPTEN0 + Capture Channel 0 Enable + 16 + 1 + + + CAPTEN1 + Capture Channel 1 Enable + 17 + 1 + + + COPEN0 + Capture On Pin 0 Enable + 20 + 1 + + + COPEN1 + Capture On Pin 1 Enable + 21 + 1 + + + + + CTRLBCLR + Control B Clear + 0x04 + 8 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0x0 + + + RETRIGGER + Force a start, restart or retrigger + 0x1 + + + STOP + Force a stop + 0x2 + + + UPDATE + Force update of double-buffered register + 0x3 + + + READSYNC + Force a read synchronization of COUNT + 0x4 + + + DMAOS + One-shot DMA trigger + 0x5 + + + + + + + CTRLBSET + Control B Set + 0x05 + 8 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0x0 + + + RETRIGGER + Force a start, restart or retrigger + 0x1 + + + STOP + Force a stop + 0x2 + + + UPDATE + Force update of double-buffered register + 0x3 + + + READSYNC + Force a read synchronization of COUNT + 0x4 + + + DMAOS + One-shot DMA trigger + 0x5 + + + + + + + EVCTRL + Event Control + 0x06 + 16 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0x0 + + + RETRIGGER + Start, restart or retrigger TC on event + 0x1 + + + COUNT + Count on event + 0x2 + + + START + Start TC on event + 0x3 + + + STAMP + Time stamp capture + 0x4 + + + PPW + Period catured in CC0, pulse width in CC1 + 0x5 + + + PWP + Period catured in CC1, pulse width in CC0 + 0x6 + + + PW + Pulse width capture + 0x7 + + + + + TCINV + TC Event Input Polarity + 4 + 1 + + + TCEI + TC Event Enable + 5 + 1 + + + OVFEO + Event Output Enable + 8 + 1 + + + MCEO0 + MC Event Output Enable 0 + 12 + 1 + + + MCEO1 + MC Event Output Enable 1 + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x08 + 8 + + + OVF + OVF Interrupt Disable + 0 + 1 + + + ERR + ERR Interrupt Disable + 1 + 1 + + + MC0 + MC Interrupt Disable 0 + 4 + 1 + + + MC1 + MC Interrupt Disable 1 + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x09 + 8 + + + OVF + OVF Interrupt Enable + 0 + 1 + + + ERR + ERR Interrupt Enable + 1 + 1 + + + MC0 + MC Interrupt Enable 0 + 4 + 1 + + + MC1 + MC Interrupt Enable 1 + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x0A + 8 + + + OVF + OVF Interrupt Flag + 0 + 1 + + + ERR + ERR Interrupt Flag + 1 + 1 + + + MC0 + MC Interrupt Flag 0 + 4 + 1 + + + MC1 + MC Interrupt Flag 1 + 5 + 1 + + + + + STATUS + Status + 0x0B + 8 + 0x01 + + + STOP + Stop Status Flag + 0 + 1 + read-only + + + SLAVE + Slave Status Flag + 1 + 1 + read-only + + + PERBUFV + Synchronization Busy Status + 3 + 1 + + + CCBUFV0 + Compare channel buffer 0 valid + 4 + 1 + + + CCBUFV1 + Compare channel buffer 1 valid + 5 + 1 + + + + + WAVE + Waveform Generation Control + 0x0C + 8 + + + WAVEGEN + Waveform Generation Mode + 0 + 2 + + WAVEGENSelect + + NFRQ + Normal frequency + 0x0 + + + MFRQ + Match frequency + 0x1 + + + NPWM + Normal PWM + 0x2 + + + MPWM + Match PWM + 0x3 + + + + + + + DRVCTRL + Control C + 0x0D + 8 + + + INVEN0 + Output Waveform Invert Enable 0 + 0 + 1 + + + INVEN1 + Output Waveform Invert Enable 1 + 1 + 1 + + + + + DBGCTRL + Debug Control + 0x0F + 8 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + Synchronization Status + 0x10 + 32 + read-only + + + SWRST + swrst + 0 + 1 + + + ENABLE + enable + 1 + 1 + + + CTRLB + CTRLB + 2 + 1 + + + STATUS + STATUS + 3 + 1 + + + COUNT + Counter + 4 + 1 + + + PER + Period + 5 + 1 + + + CC0 + Compare Channel 0 + 6 + 1 + + + CC1 + Compare Channel 1 + 7 + 1 + + + + + COUNT + COUNT32 Count + 0x14 + 32 + + + COUNT + Counter Value + 0 + 32 + + + + + 2 + 0x4 + CC%s + COUNT32 Compare and Capture + 0x1C + 32 + + + CC + Counter/Compare Value + 0 + 32 + + + + + 2 + 0x4 + CCBUF%s + COUNT32 Compare and Capture Buffer + 0x30 + 32 + + + CCBUF + Counter/Compare Buffer Value + 0 + 32 + + + + + + + + TC1 + Basic Timer Counter 1 + 0x42002400 + + TC1 + 17 + + + + TC2 + Basic Timer Counter 2 + 0x42002800 + + TC2 + 18 + + + + TC3 + Basic Timer Counter 3 + 0x42002C00 + + TC3 + 19 + + + + TCC0 + 3.0.0 + Timer Counter Control + TCC + TCC_ + 0x42001C00 + + 0 + 0x090 + registers + + + TCC0 + 15 + + + + CTRLA + Control A + 0x00 + 32 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RESOLUTION + Enhanced Resolution + 5 + 2 + + RESOLUTIONSelect + + NONE + Dithering is disabled + 0x0 + + + DITH4 + Dithering is done every 16 PWM frames + 0x1 + + + DITH5 + Dithering is done every 32 PWM frames + 0x2 + + + DITH6 + Dithering is done every 64 PWM frames + 0x3 + + + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + No division + 0x0 + + + DIV2 + Divide by 2 + 0x1 + + + DIV4 + Divide by 4 + 0x2 + + + DIV8 + Divide by 8 + 0x3 + + + DIV16 + Divide by 16 + 0x4 + + + DIV64 + Divide by 64 + 0x5 + + + DIV256 + Divide by 256 + 0x6 + + + DIV1024 + Divide by 1024 + 0x7 + + + + + RUNSTDBY + Run in Standby + 11 + 1 + + + PRESCSYNC + Prescaler and Counter Synchronization Selection + 12 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset counter on next GCLK + 0x0 + + + PRESC + Reload or reset counter on next prescaler clock + 0x1 + + + RESYNC + Reload or reset counter on next GCLK and reset prescaler counter + 0x2 + + + + + ALOCK + Auto Lock + 14 + 1 + + + MSYNC + Master Synchronization (only for TCC Slave Instance) + 15 + 1 + + + DMAOS + DMA One-shot Trigger Mode + 23 + 1 + + + CPTEN0 + Capture Channel 0 Enable + 24 + 1 + + + CPTEN1 + Capture Channel 1 Enable + 25 + 1 + + + CPTEN2 + Capture Channel 2 Enable + 26 + 1 + + + CPTEN3 + Capture Channel 3 Enable + 27 + 1 + + + + + CTRLBCLR + Control B Clear + 0x04 + 8 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + IDXCMD + Ramp Index Command + 3 + 2 + + IDXCMDSelect + + DISABLE + Command disabled: Index toggles between cycles A and B + 0x0 + + + SET + Set index: cycle B will be forced in the next cycle + 0x1 + + + CLEAR + Clear index: cycle A will be forced in the next cycle + 0x2 + + + HOLD + Hold index: the next cycle will be the same as the current cycle + 0x3 + + + + + CMD + TCC Command + 5 + 3 + + CMDSelect + + NONE + No action + 0x0 + + + RETRIGGER + Clear start, restart or retrigger + 0x1 + + + STOP + Force stop + 0x2 + + + UPDATE + Force update or double buffered registers + 0x3 + + + READSYNC + Force COUNT read synchronization + 0x4 + + + DMAOS + One-shot DMA trigger + 0x5 + + + + + + + CTRLBSET + Control B Set + 0x05 + 8 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + IDXCMD + Ramp Index Command + 3 + 2 + + IDXCMDSelect + + DISABLE + Command disabled: Index toggles between cycles A and B + 0x0 + + + SET + Set index: cycle B will be forced in the next cycle + 0x1 + + + CLEAR + Clear index: cycle A will be forced in the next cycle + 0x2 + + + HOLD + Hold index: the next cycle will be the same as the current cycle + 0x3 + + + + + CMD + TCC Command + 5 + 3 + + CMDSelect + + NONE + No action + 0x0 + + + RETRIGGER + Clear start, restart or retrigger + 0x1 + + + STOP + Force stop + 0x2 + + + UPDATE + Force update or double buffered registers + 0x3 + + + READSYNC + Force COUNT read synchronization + 0x4 + + + DMAOS + One-shot DMA trigger + 0x5 + + + + + + + SYNCBUSY + Synchronization Busy + 0x08 + 32 + read-only + + + SWRST + Swrst Busy + 0 + 1 + + + ENABLE + Enable Busy + 1 + 1 + + + CTRLB + Ctrlb Busy + 2 + 1 + + + STATUS + Status Busy + 3 + 1 + + + COUNT + Count Busy + 4 + 1 + + + PATT + Pattern Busy + 5 + 1 + + + WAVE + Wave Busy + 6 + 1 + + + PER + Period Busy + 7 + 1 + + + CC0 + Compare Channel 0 Busy + 8 + 1 + + + CC1 + Compare Channel 1 Busy + 9 + 1 + + + CC2 + Compare Channel 2 Busy + 10 + 1 + + + CC3 + Compare Channel 3 Busy + 11 + 1 + + + + + FCTRLA + Recoverable Fault A Configuration + 0x0C + 32 + + + SRC + Fault A Source + 0 + 2 + + SRCSelect + + DISABLE + Fault input disabled + 0x0 + + + ENABLE + MCEx (x=0,1) event input + 0x1 + + + INVERT + Inverted MCEx (x=0,1) event input + 0x2 + + + ALTFAULT + Alternate fault (A or B) state at the end of the previous period + 0x3 + + + + + KEEP + Fault A Keeper + 3 + 1 + + + QUAL + Fault A Qualification + 4 + 1 + + + BLANK + Fault A Blanking Mode + 5 + 2 + + BLANKSelect + + START + Blanking applied from start of the ramp + 0x0 + + + RISE + Blanking applied from rising edge of the output waveform + 0x1 + + + FALL + Blanking applied from falling edge of the output waveform + 0x2 + + + BOTH + Blanking applied from each toggle of the output waveform + 0x3 + + + + + RESTART + Fault A Restart + 7 + 1 + + + HALT + Fault A Halt Mode + 8 + 2 + + HALTSelect + + DISABLE + Halt action disabled + 0x0 + + + HW + Hardware halt action + 0x1 + + + SW + Software halt action + 0x2 + + + NR + Non-recoverable fault + 0x3 + + + + + CHSEL + Fault A Capture Channel + 10 + 2 + + CHSELSelect + + CC0 + Capture value stored in channel 0 + 0x0 + + + CC1 + Capture value stored in channel 1 + 0x1 + + + CC2 + Capture value stored in channel 2 + 0x2 + + + CC3 + Capture value stored in channel 3 + 0x3 + + + + + CAPTURE + Fault A Capture Action + 12 + 3 + + CAPTURESelect + + DISABLE + No capture + 0x0 + + + CAPT + Capture on fault + 0x1 + + + CAPTMIN + Minimum capture + 0x2 + + + CAPTMAX + Maximum capture + 0x3 + + + LOCMIN + Minimum local detection + 0x4 + + + LOCMAX + Maximum local detection + 0x5 + + + DERIV0 + Minimum and maximum local detection + 0x6 + + + CAPTMARK + Capture with ramp index as MSB value + 0x7 + + + + + BLANKPRESC + Fault A Blanking Prescaler + 15 + 1 + + + BLANKVAL + Fault A Blanking Time + 16 + 8 + + + FILTERVAL + Fault A Filter Value + 24 + 4 + + + + + FCTRLB + Recoverable Fault B Configuration + 0x10 + 32 + + + SRC + Fault B Source + 0 + 2 + + SRCSelect + + DISABLE + Fault input disabled + 0x0 + + + ENABLE + MCEx (x=0,1) event input + 0x1 + + + INVERT + Inverted MCEx (x=0,1) event input + 0x2 + + + ALTFAULT + Alternate fault (A or B) state at the end of the previous period + 0x3 + + + + + KEEP + Fault B Keeper + 3 + 1 + + + QUAL + Fault B Qualification + 4 + 1 + + + BLANK + Fault B Blanking Mode + 5 + 2 + + BLANKSelect + + START + Blanking applied from start of the ramp + 0x0 + + + RISE + Blanking applied from rising edge of the output waveform + 0x1 + + + FALL + Blanking applied from falling edge of the output waveform + 0x2 + + + BOTH + Blanking applied from each toggle of the output waveform + 0x3 + + + + + RESTART + Fault B Restart + 7 + 1 + + + HALT + Fault B Halt Mode + 8 + 2 + + HALTSelect + + DISABLE + Halt action disabled + 0x0 + + + HW + Hardware halt action + 0x1 + + + SW + Software halt action + 0x2 + + + NR + Non-recoverable fault + 0x3 + + + + + CHSEL + Fault B Capture Channel + 10 + 2 + + CHSELSelect + + CC0 + Capture value stored in channel 0 + 0x0 + + + CC1 + Capture value stored in channel 1 + 0x1 + + + CC2 + Capture value stored in channel 2 + 0x2 + + + CC3 + Capture value stored in channel 3 + 0x3 + + + + + CAPTURE + Fault B Capture Action + 12 + 3 + + CAPTURESelect + + DISABLE + No capture + 0x0 + + + CAPT + Capture on fault + 0x1 + + + CAPTMIN + Minimum capture + 0x2 + + + CAPTMAX + Maximum capture + 0x3 + + + LOCMIN + Minimum local detection + 0x4 + + + LOCMAX + Maximum local detection + 0x5 + + + DERIV0 + Minimum and maximum local detection + 0x6 + + + CAPTMARK + Capture with ramp index as MSB value + 0x7 + + + + + BLANKPRESC + Fault B Blanking Prescaler + 15 + 1 + + + BLANKVAL + Fault B Blanking Time + 16 + 8 + + + FILTERVAL + Fault B Filter Value + 24 + 4 + + + + + WEXCTRL + Waveform Extension Configuration + 0x14 + 32 + + + OTMX + Output Matrix + 0 + 2 + + + DTIEN0 + Dead-time Insertion Generator 0 Enable + 8 + 1 + + + DTIEN1 + Dead-time Insertion Generator 1 Enable + 9 + 1 + + + DTIEN2 + Dead-time Insertion Generator 2 Enable + 10 + 1 + + + DTIEN3 + Dead-time Insertion Generator 3 Enable + 11 + 1 + + + DTLS + Dead-time Low Side Outputs Value + 16 + 8 + + + DTHS + Dead-time High Side Outputs Value + 24 + 8 + + + + + DRVCTRL + Driver Control + 0x18 + 32 + + + NRE0 + Non-Recoverable State 0 Output Enable + 0 + 1 + + + NRE1 + Non-Recoverable State 1 Output Enable + 1 + 1 + + + NRE2 + Non-Recoverable State 2 Output Enable + 2 + 1 + + + NRE3 + Non-Recoverable State 3 Output Enable + 3 + 1 + + + NRE4 + Non-Recoverable State 4 Output Enable + 4 + 1 + + + NRE5 + Non-Recoverable State 5 Output Enable + 5 + 1 + + + NRE6 + Non-Recoverable State 6 Output Enable + 6 + 1 + + + NRE7 + Non-Recoverable State 7 Output Enable + 7 + 1 + + + NRV0 + Non-Recoverable State 0 Output Value + 8 + 1 + + + NRV1 + Non-Recoverable State 1 Output Value + 9 + 1 + + + NRV2 + Non-Recoverable State 2 Output Value + 10 + 1 + + + NRV3 + Non-Recoverable State 3 Output Value + 11 + 1 + + + NRV4 + Non-Recoverable State 4 Output Value + 12 + 1 + + + NRV5 + Non-Recoverable State 5 Output Value + 13 + 1 + + + NRV6 + Non-Recoverable State 6 Output Value + 14 + 1 + + + NRV7 + Non-Recoverable State 7 Output Value + 15 + 1 + + + INVEN0 + Output Waveform 0 Inversion + 16 + 1 + + + INVEN1 + Output Waveform 1 Inversion + 17 + 1 + + + INVEN2 + Output Waveform 2 Inversion + 18 + 1 + + + INVEN3 + Output Waveform 3 Inversion + 19 + 1 + + + INVEN4 + Output Waveform 4 Inversion + 20 + 1 + + + INVEN5 + Output Waveform 5 Inversion + 21 + 1 + + + INVEN6 + Output Waveform 6 Inversion + 22 + 1 + + + INVEN7 + Output Waveform 7 Inversion + 23 + 1 + + + FILTERVAL0 + Non-Recoverable Fault Input 0 Filter Value + 24 + 4 + + + FILTERVAL1 + Non-Recoverable Fault Input 1 Filter Value + 28 + 4 + + + + + DBGCTRL + Debug Control + 0x1E + 8 + + + DBGRUN + Debug Running Mode + 0 + 1 + + + FDDBD + Fault Detection on Debug Break Detection + 2 + 1 + + + + + EVCTRL + Event Control + 0x20 + 32 + + + EVACT0 + Timer/counter Input Event0 Action + 0 + 3 + + EVACT0Select + + OFF + Event action disabled + 0x0 + + + RETRIGGER + Start, restart or re-trigger counter on event + 0x1 + + + COUNTEV + Count on event + 0x2 + + + START + Start counter on event + 0x3 + + + INC + Increment counter on event + 0x4 + + + COUNT + Count on active state of asynchronous event + 0x5 + + + STAMP + Stamp capture + 0x6 + + + FAULT + Non-recoverable fault + 0x7 + + + + + EVACT1 + Timer/counter Input Event1 Action + 3 + 3 + + EVACT1Select + + OFF + Event action disabled + 0x0 + + + RETRIGGER + Re-trigger counter on event + 0x1 + + + DIR + Direction control + 0x2 + + + STOP + Stop counter on event + 0x3 + + + DEC + Decrement counter on event + 0x4 + + + PPW + Period capture value in CC0 register, pulse width capture value in CC1 register + 0x5 + + + PWP + Period capture value in CC1 register, pulse width capture value in CC0 register + 0x6 + + + FAULT + Non-recoverable fault + 0x7 + + + + + CNTSEL + Timer/counter Output Event Mode + 6 + 2 + + CNTSELSelect + + START + An interrupt/event is generated when a new counter cycle starts + 0x0 + + + END + An interrupt/event is generated when a counter cycle ends + 0x1 + + + BETWEEN + An interrupt/event is generated when a counter cycle ends, except for the first and last cycles + 0x2 + + + BOUNDARY + An interrupt/event is generated when a new counter cycle starts or a counter cycle ends + 0x3 + + + + + OVFEO + Overflow/Underflow Output Event Enable + 8 + 1 + + + TRGEO + Retrigger Output Event Enable + 9 + 1 + + + CNTEO + Timer/counter Output Event Enable + 10 + 1 + + + TCINV0 + Inverted Event 0 Input Enable + 12 + 1 + + + TCINV1 + Inverted Event 1 Input Enable + 13 + 1 + + + TCEI0 + Timer/counter Event 0 Input Enable + 14 + 1 + + + TCEI1 + Timer/counter Event 1 Input Enable + 15 + 1 + + + MCEI0 + Match or Capture Channel 0 Event Input Enable + 16 + 1 + + + MCEI1 + Match or Capture Channel 1 Event Input Enable + 17 + 1 + + + MCEI2 + Match or Capture Channel 2 Event Input Enable + 18 + 1 + + + MCEI3 + Match or Capture Channel 3 Event Input Enable + 19 + 1 + + + MCEO0 + Match or Capture Channel 0 Event Output Enable + 24 + 1 + + + MCEO1 + Match or Capture Channel 1 Event Output Enable + 25 + 1 + + + MCEO2 + Match or Capture Channel 2 Event Output Enable + 26 + 1 + + + MCEO3 + Match or Capture Channel 3 Event Output Enable + 27 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x24 + 32 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + TRG + Retrigger Interrupt Enable + 1 + 1 + + + CNT + Counter Interrupt Enable + 2 + 1 + + + ERR + Error Interrupt Enable + 3 + 1 + + + UFS + Non-Recoverable Update Fault Interrupt Enable + 10 + 1 + + + DFS + Non-Recoverable Debug Fault Interrupt Enable + 11 + 1 + + + FAULTA + Recoverable Fault A Interrupt Enable + 12 + 1 + + + FAULTB + Recoverable Fault B Interrupt Enable + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 Interrupt Enable + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 Interrupt Enable + 15 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 16 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 17 + 1 + + + MC2 + Match or Capture Channel 2 Interrupt Enable + 18 + 1 + + + MC3 + Match or Capture Channel 3 Interrupt Enable + 19 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x28 + 32 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + TRG + Retrigger Interrupt Enable + 1 + 1 + + + CNT + Counter Interrupt Enable + 2 + 1 + + + ERR + Error Interrupt Enable + 3 + 1 + + + UFS + Non-Recoverable Update Fault Interrupt Enable + 10 + 1 + + + DFS + Non-Recoverable Debug Fault Interrupt Enable + 11 + 1 + + + FAULTA + Recoverable Fault A Interrupt Enable + 12 + 1 + + + FAULTB + Recoverable Fault B Interrupt Enable + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 Interrupt Enable + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 Interrupt Enable + 15 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 16 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 17 + 1 + + + MC2 + Match or Capture Channel 2 Interrupt Enable + 18 + 1 + + + MC3 + Match or Capture Channel 3 Interrupt Enable + 19 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x2C + 32 + + + OVF + Overflow + 0 + 1 + + + TRG + Retrigger + 1 + 1 + + + CNT + Counter + 2 + 1 + + + ERR + Error + 3 + 1 + + + UFS + Non-Recoverable Update Fault + 10 + 1 + + + DFS + Non-Recoverable Debug Fault + 11 + 1 + + + FAULTA + Recoverable Fault A + 12 + 1 + + + FAULTB + Recoverable Fault B + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 + 15 + 1 + + + MC0 + Match or Capture 0 + 16 + 1 + + + MC1 + Match or Capture 1 + 17 + 1 + + + MC2 + Match or Capture 2 + 18 + 1 + + + MC3 + Match or Capture 3 + 19 + 1 + + + + + STATUS + Status + 0x30 + 32 + 0x00000001 + + + STOP + Stop + 0 + 1 + read-only + + + IDX + Ramp + 1 + 1 + read-only + + + UFS + Non-recoverable Update Fault State + 2 + 1 + + + DFS + Non-Recoverable Debug Fault State + 3 + 1 + + + SLAVE + Slave + 4 + 1 + read-only + + + PATTBUFV + Pattern Buffer Valid + 5 + 1 + + + PERBUFV + Period Buffer Valid + 7 + 1 + + + FAULTAIN + Recoverable Fault A Input + 8 + 1 + read-only + + + FAULTBIN + Recoverable Fault B Input + 9 + 1 + read-only + + + FAULT0IN + Non-Recoverable Fault0 Input + 10 + 1 + read-only + + + FAULT1IN + Non-Recoverable Fault1 Input + 11 + 1 + read-only + + + FAULTA + Recoverable Fault A State + 12 + 1 + + + FAULTB + Recoverable Fault B State + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 State + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 State + 15 + 1 + + + CCBUFV0 + Compare Channel 0 Buffer Valid + 16 + 1 + + + CCBUFV1 + Compare Channel 1 Buffer Valid + 17 + 1 + + + CCBUFV2 + Compare Channel 2 Buffer Valid + 18 + 1 + + + CCBUFV3 + Compare Channel 3 Buffer Valid + 19 + 1 + + + CMP0 + Compare Channel 0 Value + 24 + 1 + read-only + + + CMP1 + Compare Channel 1 Value + 25 + 1 + read-only + + + CMP2 + Compare Channel 2 Value + 26 + 1 + read-only + + + CMP3 + Compare Channel 3 Value + 27 + 1 + read-only + + + + + COUNT + Count + 0x34 + 32 + + + COUNT + Counter Value + 0 + 24 + + + + + COUNT_DITH4 + Count + COUNT + 0x34 + 32 + + + COUNT + Counter Value + 4 + 20 + + + + + COUNT_DITH5 + Count + COUNT + 0x34 + 32 + + + COUNT + Counter Value + 5 + 19 + + + + + COUNT_DITH6 + Count + COUNT + 0x34 + 32 + + + COUNT + Counter Value + 6 + 18 + + + + + PATT + Pattern + 0x38 + 16 + + + PGE0 + Pattern Generator 0 Output Enable + 0 + 1 + + + PGE1 + Pattern Generator 1 Output Enable + 1 + 1 + + + PGE2 + Pattern Generator 2 Output Enable + 2 + 1 + + + PGE3 + Pattern Generator 3 Output Enable + 3 + 1 + + + PGE4 + Pattern Generator 4 Output Enable + 4 + 1 + + + PGE5 + Pattern Generator 5 Output Enable + 5 + 1 + + + PGE6 + Pattern Generator 6 Output Enable + 6 + 1 + + + PGE7 + Pattern Generator 7 Output Enable + 7 + 1 + + + PGV0 + Pattern Generator 0 Output Value + 8 + 1 + + + PGV1 + Pattern Generator 1 Output Value + 9 + 1 + + + PGV2 + Pattern Generator 2 Output Value + 10 + 1 + + + PGV3 + Pattern Generator 3 Output Value + 11 + 1 + + + PGV4 + Pattern Generator 4 Output Value + 12 + 1 + + + PGV5 + Pattern Generator 5 Output Value + 13 + 1 + + + PGV6 + Pattern Generator 6 Output Value + 14 + 1 + + + PGV7 + Pattern Generator 7 Output Value + 15 + 1 + + + + + WAVE + Waveform Control + 0x3C + 32 + + + WAVEGEN + Waveform Generation + 0 + 3 + + WAVEGENSelect + + NFRQ + Normal frequency + 0x0 + + + MFRQ + Match frequency + 0x1 + + + NPWM + Normal PWM + 0x2 + + + DSCRITICAL + Dual-slope critical + 0x4 + + + DSBOTTOM + Dual-slope with interrupt/event condition when COUNT reaches ZERO + 0x5 + + + DSBOTH + Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP + 0x6 + + + DSTOP + Dual-slope with interrupt/event condition when COUNT reaches TOP + 0x7 + + + + + RAMP + Ramp Mode + 4 + 2 + + RAMPSelect + + RAMP1 + RAMP1 operation + 0x0 + + + RAMP2A + Alternative RAMP2 operation + 0x1 + + + RAMP2 + RAMP2 operation + 0x2 + + + RAMP2C + Critical RAMP2 operation + 0x3 + + + + + CIPEREN + Circular period Enable + 7 + 1 + + + CICCEN0 + Circular Channel 0 Enable + 8 + 1 + + + CICCEN1 + Circular Channel 1 Enable + 9 + 1 + + + CICCEN2 + Circular Channel 2 Enable + 10 + 1 + + + CICCEN3 + Circular Channel 3 Enable + 11 + 1 + + + POL0 + Channel 0 Polarity + 16 + 1 + + + POL1 + Channel 1 Polarity + 17 + 1 + + + POL2 + Channel 2 Polarity + 18 + 1 + + + POL3 + Channel 3 Polarity + 19 + 1 + + + SWAP0 + Swap DTI Output Pair 0 + 24 + 1 + + + SWAP1 + Swap DTI Output Pair 1 + 25 + 1 + + + SWAP2 + Swap DTI Output Pair 2 + 26 + 1 + + + SWAP3 + Swap DTI Output Pair 3 + 27 + 1 + + + + + PER + Period + 0x40 + 32 + 0xFFFFFFFF + + + PER + Period Value + 0 + 24 + + + + + PER_DITH4 + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHER + Dithering Cycle Number + 0 + 4 + + + PER + Period Value + 4 + 20 + + + + + PER_DITH5 + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHER + Dithering Cycle Number + 0 + 5 + + + PER + Period Value + 5 + 19 + + + + + PER_DITH6 + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHER + Dithering Cycle Number + 0 + 6 + + + PER + Period Value + 6 + 18 + + + + + 4 + 0x4 + CC%s + Compare and Capture + 0x44 + 32 + + + CC + Channel Compare/Capture Value + 0 + 24 + + + + + 4 + 0x4 + CC%s_DITH4 + Compare and Capture + CC%s + 0x44 + 32 + + + DITHER + Dithering Cycle Number + 0 + 4 + + + CC + Channel Compare/Capture Value + 4 + 20 + + + + + 4 + 0x4 + CC%s_DITH5 + Compare and Capture + CC%s + 0x44 + 32 + + + DITHER + Dithering Cycle Number + 0 + 5 + + + CC + Channel Compare/Capture Value + 5 + 19 + + + + + 4 + 0x4 + CC%s_DITH6 + Compare and Capture + CC%s + 0x44 + 32 + + + DITHER + Dithering Cycle Number + 0 + 6 + + + CC + Channel Compare/Capture Value + 6 + 18 + + + + + PATTBUF + Pattern Buffer + 0x64 + 16 + + + PGEB0 + Pattern Generator 0 Output Enable Buffer + 0 + 1 + + + PGEB1 + Pattern Generator 1 Output Enable Buffer + 1 + 1 + + + PGEB2 + Pattern Generator 2 Output Enable Buffer + 2 + 1 + + + PGEB3 + Pattern Generator 3 Output Enable Buffer + 3 + 1 + + + PGEB4 + Pattern Generator 4 Output Enable Buffer + 4 + 1 + + + PGEB5 + Pattern Generator 5 Output Enable Buffer + 5 + 1 + + + PGEB6 + Pattern Generator 6 Output Enable Buffer + 6 + 1 + + + PGEB7 + Pattern Generator 7 Output Enable Buffer + 7 + 1 + + + PGVB0 + Pattern Generator 0 Output Enable + 8 + 1 + + + PGVB1 + Pattern Generator 1 Output Enable + 9 + 1 + + + PGVB2 + Pattern Generator 2 Output Enable + 10 + 1 + + + PGVB3 + Pattern Generator 3 Output Enable + 11 + 1 + + + PGVB4 + Pattern Generator 4 Output Enable + 12 + 1 + + + PGVB5 + Pattern Generator 5 Output Enable + 13 + 1 + + + PGVB6 + Pattern Generator 6 Output Enable + 14 + 1 + + + PGVB7 + Pattern Generator 7 Output Enable + 15 + 1 + + + + + PERBUF + Period Buffer + 0x6C + 32 + 0xFFFFFFFF + + + PERBUF + Period Buffer Value + 0 + 24 + + + + + PERBUF_DITH4 + Period Buffer + PERBUF + 0x6C + 32 + 0xFFFFFFFF + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 4 + + + PERBUF + Period Buffer Value + 4 + 20 + + + + + PERBUF_DITH5 + Period Buffer + PERBUF + 0x6C + 32 + 0xFFFFFFFF + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 5 + + + PERBUF + Period Buffer Value + 5 + 19 + + + + + PERBUF_DITH6 + Period Buffer + PERBUF + 0x6C + 32 + 0xFFFFFFFF + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 6 + + + PERBUF + Period Buffer Value + 6 + 18 + + + + + 4 + 0x4 + CCBUF%s + Compare and Capture Buffer + 0x70 + 32 + + + CCBUF + Channel Compare/Capture Buffer Value + 0 + 24 + + + + + 4 + 0x4 + CCBUF%s_DITH4 + Compare and Capture Buffer + CCBUF%s + 0x70 + 32 + + + CCBUF + Channel Compare/Capture Buffer Value + 0 + 4 + + + DITHERBUF + Dithering Buffer Cycle Number + 4 + 20 + + + + + 4 + 0x4 + CCBUF%s_DITH5 + Compare and Capture Buffer + CCBUF%s + 0x70 + 32 + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 5 + + + CCBUF + Channel Compare/Capture Buffer Value + 5 + 19 + + + + + 4 + 0x4 + CCBUF%s_DITH6 + Compare and Capture Buffer + CCBUF%s + 0x70 + 32 + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 6 + + + CCBUF + Channel Compare/Capture Buffer Value + 6 + 18 + + + + + + + TRNG + 1.0.1 + True Random Generator + TRNG + TRNG_ + 0x42004400 + + 0 + 0x100 + registers + + + TRNG + 25 + + + + CTRLA + Control A + 0x00 + 8 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + + + EVCTRL + Event Control + 0x04 + 8 + + + DATARDYEO + Data Ready Event Output + 0 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x08 + 8 + + + DATARDY + Data Ready Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x09 + 8 + + + DATARDY + Data Ready Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x0A + 8 + + + DATARDY + Data Ready Interrupt Flag + 0 + 1 + + + + + DATA + Output Data + 0x20 + 32 + read-only + + + DATA + Output Data + 0 + 32 + + + + + + + USB + 1.1.1 + Universal Serial Bus + USB + USB_ + 0x41000000 + + 0 + 0x400 + registers + + + USB + 5 + + + + DEVICE + USB is Device + UsbDevice + 0x0 + + CTRLA + Control A + 0x000 + 8 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby Mode + 2 + 1 + + + MODE + Operating Mode + 7 + 1 + + MODESelect + + DEVICE + Device Mode + 0x0 + + + + + + + SYNCBUSY + Synchronization Busy + 0x002 + 8 + read-only + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + read-only + + + ENABLE + Enable Synchronization Busy + 1 + 1 + read-only + + + + + QOSCTRL + USB Quality Of Service + 0x003 + 8 + 0x0F + + + CQOS + Configuration Quality of Service + 0 + 2 + + + DQOS + Data Quality of Service + 2 + 2 + + + + + CTRLB + DEVICE Control B + 0x008 + 16 + 0x0001 + + + DETACH + Detach + 0 + 1 + + + UPRSM + Upstream Resume + 1 + 1 + + + SPDCONF + Speed Configuration + 2 + 2 + + SPDCONFSelect + + FS + FS : Full Speed + 0x0 + + + LS + LS : Low Speed + 0x1 + + + HS + HS : High Speed capable + 0x2 + + + HSTM + HSTM: High Speed Test Mode (force high-speed mode for test mode) + 0x3 + + + + + NREPLY + No Reply + 4 + 1 + + + TSTJ + Test mode J + 5 + 1 + + + TSTK + Test mode K + 6 + 1 + + + TSTPCKT + Test packet mode + 7 + 1 + + + OPMODE2 + Specific Operational Mode + 8 + 1 + + + GNAK + Global NAK + 9 + 1 + + + LPMHDSK + Link Power Management Handshake + 10 + 2 + + LPMHDSKSelect + + NO + No handshake. LPM is not supported + 0x0 + + + ACK + ACK + 0x1 + + + NYET + NYET + 0x2 + + + STALL + STALL + 0x3 + + + + + + + DADD + DEVICE Device Address + 0x00A + 8 + + + DADD + Device Address + 0 + 7 + + + ADDEN + Device Address Enable + 7 + 1 + + + + + STATUS + DEVICE Status + 0x00C + 8 + read-only + 0x40 + + + SPEED + Speed Status + 2 + 2 + read-only + + SPEEDSelect + + FS + Full-speed mode + 0x0 + + + HS + High-speed mode + 0x1 + + + LS + Low-speed mode + 0x2 + + + + + LINESTATE + USB Line State Status + 6 + 2 + read-only + + LINESTATESelect + + 0 + SE0/RESET + 0x0 + + + 1 + FS-J or LS-K State + 0x1 + + + 2 + FS-K or LS-J State + 0x2 + + + + + + + FSMSTATUS + Finite State Machine Status + 0x00D + 8 + read-only + 0x01 + + + FSMSTATE + Fine State Machine Status + 0 + 7 + read-only + + FSMSTATESelect + + OFF + OFF (L3). It corresponds to the powered-off, disconnected, and disabled state + 0x1 + + + ON + ON (L0). It corresponds to the Idle and Active states + 0x2 + + + SUSPEND + SUSPEND (L2) + 0x4 + + + SLEEP + SLEEP (L1) + 0x8 + + + DNRESUME + DNRESUME. Down Stream Resume. + 0x10 + + + UPRESUME + UPRESUME. Up Stream Resume. + 0x20 + + + RESET + RESET. USB lines Reset. + 0x40 + + + + + + + FNUM + DEVICE Device Frame Number + 0x010 + 16 + read-only + + + MFNUM + Micro Frame Number + 0 + 3 + read-only + + + FNUM + Frame Number + 3 + 11 + read-only + + + FNCERR + Frame Number CRC Error + 15 + 1 + read-only + + + + + INTENCLR + DEVICE Device Interrupt Enable Clear + 0x014 + 16 + + + SUSPEND + Suspend Interrupt Enable + 0 + 1 + + + MSOF + Micro Start of Frame Interrupt Enable in High Speed Mode + 1 + 1 + + + SOF + Start Of Frame Interrupt Enable + 2 + 1 + + + EORST + End of Reset Interrupt Enable + 3 + 1 + + + WAKEUP + Wake Up Interrupt Enable + 4 + 1 + + + EORSM + End Of Resume Interrupt Enable + 5 + 1 + + + UPRSM + Upstream Resume Interrupt Enable + 6 + 1 + + + RAMACER + Ram Access Interrupt Enable + 7 + 1 + + + LPMNYET + Link Power Management Not Yet Interrupt Enable + 8 + 1 + + + LPMSUSP + Link Power Management Suspend Interrupt Enable + 9 + 1 + + + + + INTENSET + DEVICE Device Interrupt Enable Set + 0x018 + 16 + + + SUSPEND + Suspend Interrupt Enable + 0 + 1 + + + MSOF + Micro Start of Frame Interrupt Enable in High Speed Mode + 1 + 1 + + + SOF + Start Of Frame Interrupt Enable + 2 + 1 + + + EORST + End of Reset Interrupt Enable + 3 + 1 + + + WAKEUP + Wake Up Interrupt Enable + 4 + 1 + + + EORSM + End Of Resume Interrupt Enable + 5 + 1 + + + UPRSM + Upstream Resume Interrupt Enable + 6 + 1 + + + RAMACER + Ram Access Interrupt Enable + 7 + 1 + + + LPMNYET + Link Power Management Not Yet Interrupt Enable + 8 + 1 + + + LPMSUSP + Link Power Management Suspend Interrupt Enable + 9 + 1 + + + + + INTFLAG + DEVICE Device Interrupt Flag + 0x01C + 16 + + + SUSPEND + Suspend + 0 + 1 + + + MSOF + Micro Start of Frame in High Speed Mode + 1 + 1 + + + SOF + Start Of Frame + 2 + 1 + + + EORST + End of Reset + 3 + 1 + + + WAKEUP + Wake Up + 4 + 1 + + + EORSM + End Of Resume + 5 + 1 + + + UPRSM + Upstream Resume + 6 + 1 + + + RAMACER + Ram Access + 7 + 1 + + + LPMNYET + Link Power Management Not Yet + 8 + 1 + + + LPMSUSP + Link Power Management Suspend + 9 + 1 + + + + + EPINTSMRY + DEVICE End Point Interrupt Summary + 0x020 + 16 + read-only + + + EPINT0 + End Point 0 Interrupt + 0 + 1 + read-only + + + EPINT1 + End Point 1 Interrupt + 1 + 1 + read-only + + + EPINT2 + End Point 2 Interrupt + 2 + 1 + read-only + + + EPINT3 + End Point 3 Interrupt + 3 + 1 + read-only + + + EPINT4 + End Point 4 Interrupt + 4 + 1 + read-only + + + EPINT5 + End Point 5 Interrupt + 5 + 1 + read-only + + + EPINT6 + End Point 6 Interrupt + 6 + 1 + read-only + + + EPINT7 + End Point 7 Interrupt + 7 + 1 + read-only + + + + + DESCADD + Descriptor Address + 0x024 + 32 + + + DESCADD + Descriptor Address Value + 0 + 32 + + + + + PADCAL + USB PAD Calibration + 0x028 + 16 + + + TRANSP + USB Pad Transp calibration + 0 + 5 + + + TRANSN + USB Pad Transn calibration + 6 + 5 + + + TRIM + USB Pad Trim calibration + 12 + 3 + + + + + 8 + 0x20 + EPCFG%s + DEVICE End Point Configuration + 0x100 + 8 + + + EPTYPE0 + End Point Type0 + 0 + 3 + + + EPTYPE1 + End Point Type1 + 4 + 3 + + + NYETDIS + NYET Token Disable + 7 + 1 + + + + + 8 + 0x20 + EPSTATUSCLR%s + DEVICE End Point Pipe Status Clear + 0x104 + 8 + write-only + + + DTGLOUT + Data Toggle OUT Clear + 0 + 1 + write-only + + + DTGLIN + Data Toggle IN Clear + 1 + 1 + write-only + + + CURBK + Current Bank Clear + 2 + 1 + write-only + + + STALLRQ0 + Stall 0 Request Clear + 4 + 1 + write-only + + + STALLRQ1 + Stall 1 Request Clear + 5 + 1 + write-only + + + BK0RDY + Bank 0 Ready Clear + 6 + 1 + write-only + + + BK1RDY + Bank 1 Ready Clear + 7 + 1 + write-only + + + + + 8 + 0x20 + EPSTATUSSET%s + DEVICE End Point Pipe Status Set + 0x105 + 8 + write-only + + + DTGLOUT + Data Toggle OUT Set + 0 + 1 + write-only + + + DTGLIN + Data Toggle IN Set + 1 + 1 + write-only + + + CURBK + Current Bank Set + 2 + 1 + write-only + + + STALLRQ0 + Stall 0 Request Set + 4 + 1 + write-only + + + STALLRQ1 + Stall 1 Request Set + 5 + 1 + write-only + + + BK0RDY + Bank 0 Ready Set + 6 + 1 + write-only + + + BK1RDY + Bank 1 Ready Set + 7 + 1 + write-only + + + + + 8 + 0x20 + EPSTATUS%s + DEVICE End Point Pipe Status + 0x106 + 8 + read-only + + + DTGLOUT + Data Toggle Out + 0 + 1 + read-only + + + DTGLIN + Data Toggle In + 1 + 1 + read-only + + + CURBK + Current Bank + 2 + 1 + read-only + + + STALLRQ0 + Stall 0 Request + 4 + 1 + read-only + + + STALLRQ1 + Stall 1 Request + 5 + 1 + read-only + + + BK0RDY + Bank 0 ready + 6 + 1 + read-only + + + BK1RDY + Bank 1 ready + 7 + 1 + read-only + + + + + 8 + 0x20 + EPINTFLAG%s + DEVICE End Point Interrupt Flag + 0x107 + 8 + + + TRCPT0 + Transfer Complete 0 + 0 + 1 + + + TRCPT1 + Transfer Complete 1 + 1 + 1 + + + TRFAIL0 + Error Flow 0 + 2 + 1 + + + TRFAIL1 + Error Flow 1 + 3 + 1 + + + RXSTP + Received Setup + 4 + 1 + + + STALL0 + Stall 0 In/out + 5 + 1 + + + STALL1 + Stall 1 In/out + 6 + 1 + + + + + 8 + 0x20 + EPINTENCLR%s + DEVICE End Point Interrupt Clear Flag + 0x108 + 8 + + + TRCPT0 + Transfer Complete 0 Interrupt Disable + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Interrupt Disable + 1 + 1 + + + TRFAIL0 + Error Flow 0 Interrupt Disable + 2 + 1 + + + TRFAIL1 + Error Flow 1 Interrupt Disable + 3 + 1 + + + RXSTP + Received Setup Interrupt Disable + 4 + 1 + + + STALL0 + Stall 0 In/Out Interrupt Disable + 5 + 1 + + + STALL1 + Stall 1 In/Out Interrupt Disable + 6 + 1 + + + + + 8 + 0x20 + EPINTENSET%s + DEVICE End Point Interrupt Set Flag + 0x109 + 8 + + + TRCPT0 + Transfer Complete 0 Interrupt Enable + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Interrupt Enable + 1 + 1 + + + TRFAIL0 + Error Flow 0 Interrupt Enable + 2 + 1 + + + TRFAIL1 + Error Flow 1 Interrupt Enable + 3 + 1 + + + RXSTP + Received Setup Interrupt Enable + 4 + 1 + + + STALL0 + Stall 0 In/out Interrupt enable + 5 + 1 + + + STALL1 + Stall 1 In/out Interrupt enable + 6 + 1 + + + + + + + + WDT + 1.0.1 + Watchdog Timer + WDT + WDT_ + 0x40002000 + + 0 + 0x10 + registers + + + WDT + 1 + + + + CTRLA + Control + 0x0 + 8 + + + ENABLE + Enable + 1 + 1 + + + WEN + Watchdog Timer Window Mode Enable + 2 + 1 + + + ALWAYSON + Always-On + 7 + 1 + + + + + CONFIG + Configuration + 0x1 + 8 + 0xBB + + + PER + Time-Out Period + 0 + 4 + + PERSelect + + CYC8 + 8 clock cycles + 0x0 + + + CYC16 + 16 clock cycles + 0x1 + + + CYC32 + 32 clock cycles + 0x2 + + + CYC64 + 64 clock cycles + 0x3 + + + CYC128 + 128 clock cycles + 0x4 + + + CYC256 + 256 clock cycles + 0x5 + + + CYC512 + 512 clock cycles + 0x6 + + + CYC1024 + 1024 clock cycles + 0x7 + + + CYC2048 + 2048 clock cycles + 0x8 + + + CYC4096 + 4096 clock cycles + 0x9 + + + CYC8192 + 8192 clock cycles + 0xa + + + CYC16384 + 16384 clock cycles + 0xb + + + + + WINDOW + Window Mode Time-Out Period + 4 + 4 + + WINDOWSelect + + CYC8 + 8 clock cycles + 0x0 + + + CYC16 + 16 clock cycles + 0x1 + + + CYC32 + 32 clock cycles + 0x2 + + + CYC64 + 64 clock cycles + 0x3 + + + CYC128 + 128 clock cycles + 0x4 + + + CYC256 + 256 clock cycles + 0x5 + + + CYC512 + 512 clock cycles + 0x6 + + + CYC1024 + 1024 clock cycles + 0x7 + + + CYC2048 + 2048 clock cycles + 0x8 + + + CYC4096 + 4096 clock cycles + 0x9 + + + CYC8192 + 8192 clock cycles + 0xa + + + CYC16384 + 16384 clock cycles + 0xb + + + + + + + EWCTRL + Early Warning Interrupt Control + 0x2 + 8 + 0x0B + + + EWOFFSET + Early Warning Interrupt Time Offset + 0 + 4 + + EWOFFSETSelect + + CYC8 + 8 clock cycles + 0x0 + + + CYC16 + 16 clock cycles + 0x1 + + + CYC32 + 32 clock cycles + 0x2 + + + CYC64 + 64 clock cycles + 0x3 + + + CYC128 + 128 clock cycles + 0x4 + + + CYC256 + 256 clock cycles + 0x5 + + + CYC512 + 512 clock cycles + 0x6 + + + CYC1024 + 1024 clock cycles + 0x7 + + + CYC2048 + 2048 clock cycles + 0x8 + + + CYC4096 + 4096 clock cycles + 0x9 + + + CYC8192 + 8192 clock cycles + 0xa + + + CYC16384 + 16384 clock cycles + 0xb + + + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + + + EW + Early Warning Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + + + EW + Early Warning Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + + + EW + Early Warning + 0 + 1 + + + + + SYNCBUSY + Synchronization Busy + 0x8 + 32 + read-only + + + ENABLE + Enable Busy + 1 + 1 + read-only + + + WEN + Window Enable Busy + 2 + 1 + read-only + + + ALWAYSON + Always-On Busy + 3 + 1 + read-only + + + CLEAR + Clear Busy + 4 + 1 + read-only + + + + + CLEAR + Clear + 0xC + 8 + write-only + + + CLEAR + Watchdog Clear + 0 + 8 + write-only + + CLEARSelect + + KEY + Clear Key + 0xa5 + + + + + + + + +