benchmark: add cycle counter reading for x86

This adds the physical TSC reading for CPU utilisation
measurement.

Signed-off-by: Terry Bai <tianyi.bai@unsw.edu.au>

Author: terryzbai

benchmark/idle.c

@@ -20,13 +20,16 @@ struct bench *b;
 
 static inline uint64_t read_cycle_count()
 {
-    uint64_t cycle_count;
+    uint64_t cycle_count = 0;
 #if defined(CONFIG_ARCH_ARM)
     SEL4BENCH_READ_CCNT(cycle_count);
 #elif defined(CONFIG_ARCH_RISCV)
     asm volatile("rdcycle %0" : "=r"(cycle_count));
 #elif defined(CONFIG_ARCH_X86_64)
-    // Do nothing only for build atm
+    uint32_t lo, hi, unused;
+    __asm__ __volatile__("rdtscp" : "=a"(lo), "=d"(hi), "=c"(unused));
+    __asm__ __volatile__("lfence" ::: "memory");
+    cycle_count = ((uint64_t)hi << 32) | lo;
 #else
 #error "read_cycle_count: unsupported architecture"
 #endif

include/sddf/benchmark/config.h

@@ -15,7 +15,7 @@
  * on non-benchmarking configurations.
  * This defines whether we actually try to benchmark, setup the PMU etc.
  */
-#if defined(CONFIG_ENABLE_BENCHMARKS) && (defined(CONFIG_ARCH_ARM) || defined(CONFIG_ARCH_RISCV))
+#if defined(CONFIG_ENABLE_BENCHMARKS) && (defined(CONFIG_ARCH_ARM) || defined(CONFIG_ARCH_RISCV) || defined(CONFIG_ARCH_X86_64))
 #define ENABLE_BENCHMARKING 1
 #else
 #define ENABLE_BENCHMARKING 0