@@ -20,7 +20,7 @@ mod lut;
2020pub mod registers;
2121mod waitloop;
2222
23- use std:: { sync:: Arc , u8 } ;
23+ use std:: sync:: Arc ;
2424
2525use access:: { CODE , NONSEQ , SEQ } ;
2626use common:: { components:: debugger:: Severity , numutil:: NumExt } ;
@@ -76,17 +76,17 @@ impl<S: ArmSystem> Cpu<S> {
7676 return ;
7777 }
7878
79- let mut gg = SysWrapper :: new ( gg) ;
79+ let gg = SysWrapper :: new ( gg) ;
8080 if gg. cpu ( ) . cache . enabled {
8181 if let Some ( cache) = gg. cpu ( ) . cache . get ( pc) {
82- Cpu :: run_cache ( & mut gg, cache) ;
82+ Cpu :: run_cache ( gg, cache) ;
8383 return ;
8484 } else if S :: can_cache_at ( pc) {
85- Cpu :: try_make_cache ( & mut gg) ;
85+ Cpu :: try_make_cache ( gg) ;
8686 return ;
8787 }
8888 }
89- Self :: execute_next_inst ( & mut gg) ;
89+ Self :: execute_next_inst ( gg) ;
9090 }
9191
9292 /// Execute the next instruction and advance the scheduler.
@@ -266,8 +266,7 @@ impl<S: ArmSystem> Cpu<S> {
266266 pub fn check_if_interrupt ( gg : & mut S ) {
267267 if gg. cpur ( ) . is_interrupt_pending ( ) {
268268 gg. cpu ( ) . inc_pc_by ( 4 ) ;
269- let mut wrapper = SysWrapper :: new ( gg) ;
270- Cpu :: exception_occurred ( & mut wrapper, Exception :: Irq ) ;
269+ Cpu :: exception_occurred ( SysWrapper :: new ( gg) , Exception :: Irq ) ;
271270 }
272271 }
273272
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