55# r8125 is the Linux device driver released for Realtek 2.5Gigabit Ethernet
66# controllers with PCI-Express interface.
77#
8- # Copyright(c) 2021 Realtek Semiconductor Corp. All rights reserved.
8+ # Copyright(c) 2022 Realtek Semiconductor Corp. All rights reserved.
99#
1010# This program is free software; you can redistribute it and/or modify it
1111# under the terms of the GNU General Public License as published by the Free
@@ -363,12 +363,12 @@ do { \
363363#define RSS_SUFFIX ""
364364#endif
365365
366- #define RTL8125_VERSION "9.007.01 " NAPI_SUFFIX DASH_SUFFIX REALWOW_SUFFIX PTP_SUFFIX RSS_SUFFIX
366+ #define RTL8125_VERSION "9.008.00 " NAPI_SUFFIX DASH_SUFFIX REALWOW_SUFFIX PTP_SUFFIX RSS_SUFFIX
367367#define MODULENAME "r8125"
368368#define PFX MODULENAME ": "
369369
370370#define GPL_CLAIM "\
371- r8125 Copyright (C) 2021 Realtek NIC software team <nicfae@realtek.com> \n \
371+ r8125 Copyright (C) 2022 Realtek NIC software team <nicfae@realtek.com> \n \
372372This program comes with ABSOLUTELY NO WARRANTY; for details, please see <http://www.gnu.org/licenses/>. \n \
373373This is free software, and you are welcome to redistribute it under certain conditions; see <http://www.gnu.org/licenses/>. \n"
374374
@@ -413,7 +413,7 @@ This is free software, and you are welcome to redistribute it under certain cond
413413#endif
414414
415415#define Reserved2_data 7
416- #define RX_DMA_BURST 7 /* Maximum PCI burst, '6 ' is 1024 */
416+ #define RX_DMA_BURST 7 /* Maximum PCI burst, '7 ' is unlimited */
417417#define TX_DMA_BURST_unlimited 7
418418#define TX_DMA_BURST_1024 6
419419#define TX_DMA_BURST_512 5
@@ -456,12 +456,17 @@ This is free software, and you are welcome to redistribute it under certain cond
456456#define RTL8125_LINK_TIMEOUT (1 * HZ)
457457#define RTL8125_ESD_TIMEOUT (2 * HZ)
458458
459- #define NUM_TX_DESC 1024 /* Number of Tx descriptor registers */
460- #define NUM_RX_DESC 1024 /* Number of Rx descriptor registers */
459+ #define MAX_NUM_TX_DESC 1024 /* Maximum number of Tx descriptor registers */
460+ #define MAX_NUM_RX_DESC 1024 /* Maximum number of Rx descriptor registers */
461+
462+ #define MIN_NUM_TX_DESC 256 /* Minimum number of Tx descriptor registers */
463+ #define MIN_NUM_RX_DESC 256 /* Minimum number of Rx descriptor registers */
464+
465+ #define NUM_TX_DESC MAX_NUM_TX_DESC /* Number of Tx descriptor registers */
466+ #define NUM_RX_DESC MAX_NUM_RX_DESC /* Number of Rx descriptor registers */
461467
462468#define RX_BUF_SIZE 0x05F3 /* 0x05F3 = 1522bye + 1 */
463- #define R8125_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
464- #define R8125_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
469+
465470#define R8125_MAX_TX_QUEUES (2)
466471#define R8125_MAX_RX_QUEUES (4)
467472#define R8125_MAX_QUEUES R8125_MAX_RX_QUEUES
@@ -545,6 +550,9 @@ This is free software, and you are welcome to redistribute it under certain cond
545550#define RTK_LPA_ADVERTISE_5000FULL 0x40
546551#define RTK_LPA_ADVERTISE_10000FULL 0x800
547552
553+ #define RTK_EEE_ADVERTISE_2500FULL 0x01
554+ #define RTK_LPA_EEE_ADVERTISE_2500FULL 0x01
555+
548556/* Tx NO CLOSE */
549557#define MAX_TX_NO_CLOSE_DESC_PTR_V2 0x10000
550558#define TX_NO_CLOSE_SW_PTR_MASK_V2 0x1FFFF
@@ -1745,9 +1753,10 @@ struct rtl8125_tx_ring {
17451753 u32 index ;
17461754 u32 cur_tx ; /* Index into the Tx descriptor buffer of next Rx pkt. */
17471755 u32 dirty_tx ;
1756+ u32 num_tx_desc ; /* Number of Tx descriptor registers */
17481757 struct TxDesc * TxDescArray ; /* 256-aligned Tx descriptor ring */
17491758 dma_addr_t TxPhyAddr ;
1750- struct ring_info tx_skb [NUM_TX_DESC ]; /* Tx data buffers */
1759+ struct ring_info tx_skb [MAX_NUM_TX_DESC ]; /* Tx data buffers */
17511760
17521761 u32 NextHwDesCloPtr ;
17531762 u32 BeginHwDesCloPtr ;
@@ -1763,10 +1772,11 @@ struct rtl8125_rx_ring {
17631772 u32 index ;
17641773 u32 cur_rx ; /* Index into the Rx descriptor buffer of next Rx pkt. */
17651774 u32 dirty_rx ;
1775+ u32 num_rx_desc ; /* Number of Rx descriptor registers */
17661776 struct RxDesc * RxDescArray ; /* 256-aligned Rx descriptor ring */
1767- u64 RxDescPhyAddr [NUM_RX_DESC ]; /* Rx desc physical address*/
1777+ u64 RxDescPhyAddr [MAX_NUM_RX_DESC ]; /* Rx desc physical address*/
17681778 dma_addr_t RxPhyAddr ;
1769- struct sk_buff * Rx_skbuff [NUM_RX_DESC ]; /* Rx data buffers */
1779+ struct sk_buff * Rx_skbuff [MAX_NUM_RX_DESC ]; /* Rx data buffers */
17701780
17711781 u16 rdsar_reg ; /* Receive Descriptor Start Address */
17721782};
@@ -2031,8 +2041,8 @@ struct rtl8125_private {
20312041 //struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
20322042 //dma_addr_t TxPhyAddr;
20332043 //dma_addr_t RxPhyAddr;
2034- //struct sk_buff *Rx_skbuff[NUM_RX_DESC ]; /* Rx data buffers */
2035- //struct ring_info tx_skb[NUM_TX_DESC ]; /* Tx data buffers */
2044+ //struct sk_buff *Rx_skbuff[MAX_NUM_RX_DESC ]; /* Rx data buffers */
2045+ //struct ring_info tx_skb[MAX_NUM_TX_DESC ]; /* Tx data buffers */
20362046 unsigned rx_buf_sz ;
20372047 u16 HwSuppNumTxQueues ;
20382048 u16 HwSuppNumRxQueues ;
@@ -2118,12 +2128,17 @@ struct rtl8125_private {
21182128 u16 sw_ram_code_ver ;
21192129 u16 hw_ram_code_ver ;
21202130
2131+ u8 RequireRduNonStopPatch ;
2132+
21212133 u8 rtk_enable_diag ;
21222134
21232135 u8 ShortPacketSwChecksum ;
21242136
21252137 u8 UseSwPaddingShortPkt ;
21262138
2139+ void * ShortPacketEmptyBuffer ;
2140+ dma_addr_t ShortPacketEmptyBufferPhy ;
2141+
21272142 u8 RequireAdcBiasPatch ;
21282143 u16 AdcBiasPatchIoffset ;
21292144
@@ -2278,7 +2293,6 @@ struct rtl8125_private {
22782293#endif
22792294 u8 InitRxDescType ;
22802295 u16 RxDescLength ; //V1 16 Byte V2 32 Bytes
2281- u32 RxDescRingLength ;
22822296
22832297 u8 HwSuppPtpVer ;
22842298 u8 EnablePtp ;
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