Open
Description
Hello,
I synthesized a Verilog/SystemVerilog project designed for U200 using the xilinx_aws-vu9p-f1_shell-v04261818_201920_3.xpfm platform to generate an xclbin file. I then used /home/centos/aws-fpga/Vitis/tools/create_vitis_afi.sh to create an AFI from the xclbin file. Will this work without issues on an F1 instance with the vu9p platform?
So far, I’ve successfully created the AFI and uploaded it to the F1 instance. Currently, I’m testing to confirm if it operates as expected.
Additionally, I’d like to know if there are any potential issues when using XRT APIs, such as xrtKernelWriteRegister, on the FPGA.
Thank you.
Metadata
Metadata
Assignees
Labels
No labels