|
| 1 | +/** |
| 2 | + * SPDX-License-Identifier: Apache-2.0 |
| 3 | + * Copyright (c) Bao Project and Contributors. All rights reserved. |
| 4 | + */ |
| 5 | + |
| 6 | +#include <config.h> |
| 7 | + |
| 8 | + |
| 9 | +#define E3650_UART_BASE 0xF8D60000 |
| 10 | + |
| 11 | + |
| 12 | +#define E3650_GICD_BASE 0xF4000000 |
| 13 | +#define E3650_GICR_BASE 0xF4100000 |
| 14 | + |
| 15 | + |
| 16 | +#define VM0_IRAM_BASE 0x00B00000 |
| 17 | +#define VM0_IRAM_SIZE 0x00100000 |
| 18 | + |
| 19 | +#define VM1_IRAM_BASE 0x00C00000 |
| 20 | +#define VM1_IRAM_SIZE 0x00100000 |
| 21 | + |
| 22 | + |
| 23 | +VM_IMAGE(guest_image0, XSTR(BAO_DEMOS_WRKDIR_IMGS/baremetal_vm0.bin)) |
| 24 | +VM_IMAGE(guest_image1, XSTR(BAO_DEMOS_WRKDIR_IMGS/baremetal_vm1.bin)) |
| 25 | + |
| 26 | +struct config config = { |
| 27 | + |
| 28 | + .vmlist_size = 2, |
| 29 | + .vmlist = (struct vm_config[]) { |
| 30 | + { |
| 31 | + .image = VM_IMAGE_BUILTIN(guest_image0, VM0_IRAM_BASE), |
| 32 | + |
| 33 | + .entry = VM0_IRAM_BASE, |
| 34 | + |
| 35 | + .cpu_affinity = 0x3, // Cores 0 and 1 (0011) |
| 36 | + |
| 37 | + .platform = { |
| 38 | + .cpu_num = 2, |
| 39 | + |
| 40 | + .region_num = 1, |
| 41 | + .regions = (struct vm_mem_region[]) { |
| 42 | + { |
| 43 | + .base = VM0_IRAM_BASE, |
| 44 | + .size = VM0_IRAM_SIZE, |
| 45 | + }, |
| 46 | + }, |
| 47 | + |
| 48 | + .dev_num = 1, |
| 49 | + .devs = (struct vm_dev_region[]) { |
| 50 | + { |
| 51 | + |
| 52 | + .pa = E3650_UART_BASE, |
| 53 | + .va = E3650_UART_BASE, |
| 54 | + .size = 0x10000, |
| 55 | + .interrupt_num = 1, |
| 56 | + .interrupts = (unsigned[]) { 114 }, |
| 57 | + }, |
| 58 | + }, |
| 59 | + |
| 60 | + .arch = { |
| 61 | + .gic = { |
| 62 | + .gicd_addr = E3650_GICD_BASE, |
| 63 | + .gicr_addr = E3650_GICR_BASE, |
| 64 | + }, |
| 65 | + }, |
| 66 | + }, |
| 67 | + }, |
| 68 | + { |
| 69 | + .image = VM_IMAGE_BUILTIN(guest_image1, VM1_IRAM_BASE), |
| 70 | + |
| 71 | + .entry = VM1_IRAM_BASE, |
| 72 | + |
| 73 | + .cpu_affinity = 0xC, // Cores 2 and 3 (1100) |
| 74 | + |
| 75 | + .platform = { |
| 76 | + .cpu_num = 2, |
| 77 | + |
| 78 | + .region_num = 1, |
| 79 | + .regions = (struct vm_mem_region[]) { |
| 80 | + { |
| 81 | + .base = VM1_IRAM_BASE, |
| 82 | + .size = VM1_IRAM_SIZE, |
| 83 | + }, |
| 84 | + }, |
| 85 | + |
| 86 | + .dev_num = 1, |
| 87 | + .devs = (struct vm_dev_region[]) { |
| 88 | + { |
| 89 | + .pa = E3650_UART_BASE, |
| 90 | + .va = E3650_UART_BASE, |
| 91 | + .size = 0x10000, |
| 92 | + .interrupt_num = 0, |
| 93 | + }, |
| 94 | + }, |
| 95 | + |
| 96 | + .arch = { |
| 97 | + .gic = { |
| 98 | + .gicd_addr = E3650_GICD_BASE, |
| 99 | + .gicr_addr = E3650_GICR_BASE, |
| 100 | + }, |
| 101 | + }, |
| 102 | + }, |
| 103 | + } |
| 104 | + } |
| 105 | +}; |
0 commit comments