1 parent 99b857f commit c9061b2Copy full SHA for c9061b2
1 file changed
src/inference/riscv64_no_seed_default.c
@@ -38,7 +38,7 @@
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// additional trigger can be added for the all-zero case.
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//
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// Phase: PRE_COLLECTION — access() checks need no component results.
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-// Applicable: riscv64 only. See riscv64 H8.
+// Applicable: riscv64 only.
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// ---
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// <bcoles@gmail.com>
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@@ -82,6 +82,10 @@ static void riscv64_no_seed_default_run(struct kasld_analysis_ctx *ctx) {
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if (link_addr < ctx->text_base_min || link_addr > ctx->text_base_max)
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return;
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+ /* Already pinned at this value — no-op. */
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+ if (ctx->text_base_min == link_addr && ctx->text_base_max == link_addr)
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+ return;
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+
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if (verbose && !quiet)
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fprintf(stdout,
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"[infer] text_base pinned by riscv64_no_seed_default:"
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