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sarnoldsarnold
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fix: dev: rename conflicting Win32 symbol, cleanup whitespace
Signed-off-by: Stephen L Arnold <[email protected]>
1 parent 8431e39 commit aea93e2

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3 files changed

+44
-44
lines changed

3 files changed

+44
-44
lines changed

‎src/opt/eslim/eSLIMMan.tpp‎

Lines changed: 18 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@
99
Synopsis [eSLIM manager.]
1010
1111
Author [Franz-Xaver Reichl]
12-
12+
1313
Affiliation [University of Freiburg]
1414
1515
Date [Ver. 1.0. Started - March 2025.]
@@ -55,16 +55,16 @@ namespace eSLIM {
5555
}
5656

5757
template <typename Y, typename R, typename S>
58-
eSLIM_Man<Y, R, S>::eSLIM_Man(Gia_Man_t * pGia, const eSLIMConfig& cfg, eSLIMLog& log)
59-
: gia_man(pGia), cfg(cfg), log(log),
58+
eSLIM_Man<Y, R, S>::eSLIM_Man(Gia_Man_t * pGia, const eSLIMConfig& cfg, eSLIMLog& log)
59+
: gia_man(pGia), cfg(cfg), log(log),
6060
subcircuit_selection(gia_man, cfg, log) {
6161
if (cfg.fix_seed) {
6262
subcircuit_selection.setSeed(cfg.seed);
6363
}
6464
relation_generation_time = log.relation_generation_time;
6565
synthesis_time = log.synthesis_time;
6666
}
67-
67+
6868
template <typename Y, typename R, typename S>
6969
void eSLIM_Man<Y, R, S>::minimize() {
7070
abctime clkStart = Abc_Clock();
@@ -96,7 +96,7 @@ namespace eSLIM {
9696
template <typename Y, typename R, typename S>
9797
Abc_RData_t* eSLIM_Man<Y, R, S>::generateRelation(const Subcircuit& subcir) {
9898
int nof_outputs = Vec_IntSize(subcir.io) - subcir.nof_inputs;
99-
assert(Vec_IntSize(subcir.io) <= 32);
99+
assert(Vec_IntSize(subcir.io) <= 32);
100100
abctime relation_generation_start = Abc_Clock();
101101
Vec_Int_t* relation_patterns_masks = generateRelationPatterns(subcir);
102102
log.relation_generation_time += (double)1.0*(Abc_Clock() - relation_generation_start)/CLOCKS_PER_SEC;
@@ -121,13 +121,13 @@ namespace eSLIM {
121121
Abc_RData_t* p = Abc_RDataStart( nof_inputs, nof_outputs, Vec_IntSize(patterns) );
122122
Vec_IntForEachEntry( patterns, mask, i ) {
123123
for ( int k = 0; k < nof_vars; k++ ) {
124-
if ( (mask >> (nof_vars-1-k)) & 1 ) {
124+
if ( (mask >> (nof_vars-1-k)) & 1 ) {
125125
if ( k < nof_inputs ) {
126126
Abc_RDataSetIn( p, k, i );
127127
} else {
128128
Abc_RDataSetOut( p, 2*(k-nof_inputs)+1, i );
129-
}
130-
} else {
129+
}
130+
} else {
131131
if ( k >= nof_inputs ) {
132132
Abc_RDataSetOut( p, 2*(k-nof_inputs), i );
133133
}
@@ -152,7 +152,7 @@ namespace eSLIM {
152152
}
153153
return vSimsDiv;
154154
}
155-
155+
156156
template <typename Y, typename R, typename S>
157157
Vec_Wrd_t* eSLIM_Man<Y, R, S>::getSimsOut(Abc_RData_t* relation) {
158158
Vec_Wrd_t* vSimsOut = Vec_WrdStart(relation->nPats);
@@ -180,7 +180,7 @@ namespace eSLIM {
180180
insertReplacement(replacement, subcir);
181181
Mini_AigStop(replacement);
182182
}
183-
subcir.free();
183+
subcir._free();
184184
}
185185

186186
// Based on Exa_ManExactSynthesis6Int and Exa_ManExactSynthesis6
@@ -223,11 +223,11 @@ namespace eSLIM {
223223
log.nof_reduced_circuits_per_size.resize(original_size + 1, 0);
224224
}
225225
log.nof_analyzed_circuits_per_size[original_size]++;
226-
226+
227227
abctime synthesis_start = Abc_Clock();
228228
std::tie(size, pMini) = reduce(vSimsDiv2, vSimsOut2, subcir.forbidden_pairs, nVars, nDivs, nOuts, size);
229229
log.synthesis_time += (double)1.0*(Abc_Clock() - synthesis_start)/CLOCKS_PER_SEC;
230-
230+
231231
if (size > original_size) {
232232
// Could not find a replacement. This can be caused by a timeout.
233233
Abc_RDataStop(relation);
@@ -264,7 +264,7 @@ namespace eSLIM {
264264
if (pMini != nullptr) {
265265
Mini_Aig_t* pTemp = pMini;
266266
pMini = Mini_AigDupCompl(pTemp, DivCompl, OutCompl);
267-
Mini_AigStop(pTemp);
267+
Mini_AigStop(pTemp);
268268

269269
log.nof_replaced_circuits_per_size[original_size]++;
270270
if (size < original_size) {
@@ -304,7 +304,7 @@ namespace eSLIM {
304304
} else {
305305
valuefanin0 = false;
306306
}
307-
valuefanin0 = valuefanin0 != pObj->fCompl0;
307+
valuefanin0 = valuefanin0 != pObj->fCompl0;
308308
if (Gia_ObjIsTravIdCurrent(gia_man, Gia_ObjFanin1(pObj))) {
309309
valuefanin1 = getAllFalseBehaviourRec(Gia_ObjFanin1(pObj));
310310
} else {
@@ -320,7 +320,7 @@ namespace eSLIM {
320320
bool fanin_negated = Abc_LitIsCompl(fanin_lit);
321321
int fanin_value;
322322
if (fanin_idx == 0) { // constant fanin
323-
fanin_value = 0;
323+
fanin_value = 0;
324324
} else if (fanin_idx <= subcir.nof_inputs) {
325325
Gia_Obj_t* pObj = Gia_ManObj(gia_man, Vec_IntEntry(subcir.io, fanin_idx - 1));
326326
if (Gia_ObjIsTravIdCurrent(gia_man, pObj)) { //the node has already been added
@@ -464,7 +464,7 @@ namespace eSLIM {
464464
}
465465
po_idx++;
466466
}
467-
467+
468468
Gia_ManForEachPo( gia_man, pObj, i ) {
469469
assert(Gia_ObjIsTravIdCurrent(gia_man, Gia_ObjFanin0(pObj)));
470470
bool fanin_negated = Gia_ObjFaninC0(pObj) ^ Gia_ObjFanin0(pObj)->fMark0;
@@ -476,7 +476,7 @@ namespace eSLIM {
476476
}
477477

478478
template <typename Y, typename R, typename S>
479-
std::pair<int, Mini_Aig_t*> eSLIM_Man<Y, R, S>::reduce(Vec_Wrd_t* vSimsDiv, Vec_Wrd_t* vSimsOut, const std::unordered_map<int, std::unordered_set<int>>& forbidden_pairs,
479+
std::pair<int, Mini_Aig_t*> eSLIM_Man<Y, R, S>::reduce(Vec_Wrd_t* vSimsDiv, Vec_Wrd_t* vSimsOut, const std::unordered_map<int, std::unordered_set<int>>& forbidden_pairs,
480480
int nVars, int nDivs, int nOuts, int size) {
481481
Y synth_man(vSimsDiv,vSimsOut,nVars,1+nVars+nDivs,nOuts,size, forbidden_pairs, log, cfg);
482482
Mini_Aig_t* result = nullptr;
@@ -511,4 +511,4 @@ namespace eSLIM {
511511

512512
}
513513

514-
ABC_NAMESPACE_CXX_HEADER_END
514+
ABC_NAMESPACE_CXX_HEADER_END

‎src/opt/eslim/selectionStrategy.tpp‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@
99
Synopsis [Procedures for selecting subcircuits.]
1010
1111
Author [Franz-Xaver Reichl]
12-
12+
1313
Affiliation [University of Freiburg]
1414
1515
Date [Ver. 1.0. Started - March 2025.]
@@ -35,7 +35,7 @@ namespace eSLIM {
3535
if (filterSubcircuit(subcir)) {
3636
return subcir;
3737
} else {
38-
subcir.free();
38+
subcir._free();
3939
}
4040
}
4141
status = false;
@@ -74,12 +74,12 @@ namespace eSLIM {
7474
if (!Gia_ObjIsTravIdPrevious(gia_man, Gia_ObjFanin0(pObj)) && !Gia_ObjIsTravIdCurrent(gia_man, Gia_ObjFanin0(pObj))) {
7575
Gia_ObjSetTravIdCurrent(gia_man, Gia_ObjFanin0(pObj));
7676
Vec_IntPush(io, Gia_ObjId(gia_man, Gia_ObjFanin0(pObj)));
77-
}
77+
}
7878
// fanin1 is not in the subcircuit and was not considered yet
7979
if (!Gia_ObjIsTravIdPrevious(gia_man, Gia_ObjFanin1(pObj)) && !Gia_ObjIsTravIdCurrent(gia_man, Gia_ObjFanin1(pObj))) {
8080
Gia_ObjSetTravIdCurrent(gia_man, Gia_ObjFanin1(pObj));
8181
Vec_IntPush(io, Gia_ObjId(gia_man, Gia_ObjFanin1(pObj)));
82-
}
82+
}
8383
}
8484
int nof_inputs = Vec_IntSize(io);
8585

@@ -88,19 +88,19 @@ namespace eSLIM {
8888
// If there is an object that is not contained in the subcircuit that has a fanin in the subcircuit then this fanin is an output
8989
if (!Gia_ObjIsTravIdPrevious(gia_man, pObj)) {
9090
if (Gia_ObjIsTravIdPrevious(gia_man, Gia_ObjFanin0(pObj))) {
91-
Gia_ObjSetTravIdCurrent(gia_man, Gia_ObjFanin0(pObj));
91+
Gia_ObjSetTravIdCurrent(gia_man, Gia_ObjFanin0(pObj));
9292
Vec_IntPush(io, Gia_ObjId(gia_man, Gia_ObjFanin0(pObj)));
9393
}
9494
if (Gia_ObjIsTravIdPrevious(gia_man, Gia_ObjFanin1(pObj))) {
95-
Gia_ObjSetTravIdCurrent(gia_man, Gia_ObjFanin1(pObj));
95+
Gia_ObjSetTravIdCurrent(gia_man, Gia_ObjFanin1(pObj));
9696
Vec_IntPush(io, Gia_ObjId(gia_man, Gia_ObjFanin1(pObj)));
9797
}
9898
}
9999
}
100100

101101
Gia_ManForEachPo( gia_man, pObj, i ) {
102102
if (Gia_ObjIsTravIdPrevious(gia_man, Gia_ObjFanin0(pObj))) {
103-
Gia_ObjSetTravIdCurrent(gia_man, Gia_ObjFanin0(pObj));
103+
Gia_ObjSetTravIdCurrent(gia_man, Gia_ObjFanin0(pObj));
104104
Vec_IntPush(io, Gia_ObjId(gia_man, Gia_ObjFanin0(pObj)));
105105
}
106106
}
@@ -129,7 +129,7 @@ namespace eSLIM {
129129

130130
template <typename T>
131131
void SelectionStrategy<T>::forbiddenPairsRec(Gia_Obj_t * pObj, int input, int min_level, std::unordered_map<int, std::unordered_set<int>>& pairs, const std::unordered_map<int,int>& out_id) {
132-
if (Gia_ObjIsTravIdCurrent(gia_man, pObj)) {
132+
if (Gia_ObjIsTravIdCurrent(gia_man, pObj)) {
133133
auto id = Gia_ObjId(gia_man, pObj);
134134
pairs[out_id.at(id)].insert(input);
135135
return;
@@ -228,4 +228,4 @@ namespace eSLIM {
228228
}
229229
}
230230

231-
ABC_NAMESPACE_CXX_HEADER_END
231+
ABC_NAMESPACE_CXX_HEADER_END

‎src/opt/eslim/utils.hpp‎

Lines changed: 17 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@
99
Synopsis [Utilities for the eSLIM package.]
1010
1111
Author [Franz-Xaver Reichl]
12-
12+
1313
Affiliation [University of Freiburg]
1414
1515
Date [Ver. 1.0. Started - March 2025.]
@@ -33,21 +33,21 @@ ABC_NAMESPACE_CXX_HEADER_START
3333

3434
namespace eSLIM {
3535

36-
struct eSLIMConfig {
37-
bool extended_normality_processing = false;
38-
bool apply_strash = true;
39-
bool fix_seed = false;
40-
bool fill_subcircuits = false;
36+
struct eSLIMConfig {
37+
bool extended_normality_processing = false;
38+
bool apply_strash = true;
39+
bool fix_seed = false;
40+
bool fill_subcircuits = false;
4141
bool trial_limit_active = true;
42-
bool allow_xors = false;
42+
bool allow_xors = false;
4343

44-
unsigned int timeout = 3600;
45-
unsigned int iterations = 0;
46-
unsigned int subcircuit_size_bound = 6;
47-
unsigned int strash_intervall = 100;
44+
unsigned int timeout = 3600;
45+
unsigned int iterations = 0;
46+
unsigned int subcircuit_size_bound = 6;
47+
unsigned int strash_intervall = 100;
4848
int seed = 0;
4949
unsigned int nselection_trials = 100;
50-
double expansion_probability = 0.6;
50+
double expansion_probability = 0.6;
5151

5252
// times given in sec
5353
int minimum_sat_timeout = 1;
@@ -81,23 +81,23 @@ namespace eSLIM {
8181
Vec_Int_t* io;
8282
unsigned int nof_inputs;
8383
std::unordered_map<int, std::unordered_set<int>> forbidden_pairs;
84-
void free();
84+
void _free();
8585
};
8686

87-
inline void Subcircuit::free() {
87+
inline void Subcircuit::_free() {
8888
Vec_IntFree(nodes);
8989
Vec_IntFree(io);
9090
}
9191

92-
inline eSLIMLog::eSLIMLog(int size)
92+
inline eSLIMLog::eSLIMLog(int size)
9393
: nof_analyzed_circuits_per_size(size + 1, 0), nof_replaced_circuits_per_size(size + 1, 0),
9494
nof_reduced_circuits_per_size(size + 1, 0), cummulative_sat_runtimes_per_size(size + 1, 0),
95-
nof_sat_calls_per_size(size + 1, 0), cummulative_unsat_runtimes_per_size(size + 1, 0),
95+
nof_sat_calls_per_size(size + 1, 0), cummulative_unsat_runtimes_per_size(size + 1, 0),
9696
nof_unsat_calls_per_size(size + 1, 0) {
9797
}
9898

9999
}
100100

101101
ABC_NAMESPACE_CXX_HEADER_END
102102

103-
#endif
103+
#endif

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