move flwadd to flw opcode space

Author: tommydcjung

v/vanilla_bean/bsg_vanilla_pkg.v

@@ -540,8 +540,10 @@ typedef struct packed {
 `define RV32_FSQRT_S  {7'b0101100, 5'b00000, 5'b?????, 3'b???, 5'b?????, 7'b1010011}
 
 
+//                                    //
+//  NON-STANDARD RISC-V Instructions  //
+//                                    //
 
-// NON-STANDARD RISC-V Instructions
 
 //  [FLWADD]
 //
@@ -554,8 +556,7 @@ typedef struct packed {
 //  Machine Format:
 //          rs1   rs2       rd    opcode
 //  0000000_?????_?????_111_?????_0000111
-`define RV32_FLWADD_OP     7'b0000100
-`define RV32_FLWADD {7'b0000000, 5'b?????, 5'b?????, 3'b111, 5'b?????, `RV32_FLWADD_OP}
+`define RV32_FLWADD {7'b0000000, 5'b?????, 5'b?????, 3'b111, 5'b?????, `RV32_LOAD_FP}
 
 
 

v/vanilla_bean/cl_decode.v

@@ -32,7 +32,7 @@ always_comb begin
       `RV32_LUI_OP, `RV32_AUIPC_OP,
       `RV32_JAL_OP, `RV32_JALR_OP,
       `RV32_LOAD, `RV32_OP,
-      `RV32_OP_IMM, `RV32_AMO_OP, `RV32_FLWADD_OP: begin
+      `RV32_OP_IMM, `RV32_AMO_OP: begin
         decode_o.write_rd = 1'b1;
       end
       `RV32_OP_FP: begin
@@ -41,6 +41,10 @@ always_comb begin
           | ((instruction_i.funct7 == `RV32_FCLASS_S_FUN7) & (instruction_i.rs2 == 5'b00000)) // FCLASS, FMV.X.W
           | ((instruction_i.funct7 == `RV32_FCVT_S_F2I_FUN7)); // FCVT.W.S, FCVT.WU.S
       end
+      `RV32_LOAD_FP: begin
+        // flwadd
+        decode_o.write_rd = (instruction_i.funct7 == 7'b0000000) & (instruction_i.funct3 == 3'b111);
+      end
       `RV32_SYSTEM: begin
         decode_o.write_rd = 1'b1; // CSRRW, CSRRS
       end
@@ -57,15 +61,15 @@ always_comb begin
     `RV32_JALR_OP, `RV32_BRANCH,
     `RV32_LOAD, `RV32_STORE,
     `RV32_OP, `RV32_OP_IMM,
-    `RV32_AMO_OP, `RV32_FLWADD_OP: begin
+    `RV32_AMO_OP: begin
       decode_o.read_rs1 = 1'b1;
     end
    `RV32_OP_FP: begin
      decode_o.read_rs1 = 
        (instruction_i.funct7 == `RV32_FCVT_S_I2F_FUN7) // FCVT.S.W, FCVT.S.WU
        | (instruction_i.funct7 == `RV32_FMV_W_X_FUN7); // FMV.W.X
     end
-    `RV32_LOAD_FP, `RV32_STORE_FP: begin // FLW, FSW
+    `RV32_LOAD_FP, `RV32_STORE_FP: begin // FLW, FSW, FLWADD
       decode_o.read_rs1 = 1'b1;
      end
     `RV32_SYSTEM: begin
@@ -87,9 +91,13 @@ end
 // declares if Op reads from second port of integer register file
 always_comb begin
   unique casez (instruction_i.op)
-    `RV32_BRANCH, `RV32_STORE, `RV32_OP, `RV32_FLWADD_OP: begin
+    `RV32_BRANCH, `RV32_STORE, `RV32_OP: begin
       decode_o.read_rs2 = 1'b1;
     end
+    `RV32_LOAD_FP: begin
+      // flwadd
+      decode_o.read_rs2 = (instruction_i.funct7 == 7'b0000000) & (instruction_i.funct3 == 3'b111);
+    end
     `RV32_AMO_OP: begin
       // According the ISA, LR instruction don't read rs2
       decode_o.read_rs2 = (instruction_i.funct7 ==? 7'b00001??)   // amoswap
@@ -103,7 +111,7 @@ always_comb begin
 end
 
 // Load & Store
-assign decode_o.is_flwadd_op = (instruction_i.op == `RV32_FLWADD_OP);
+assign decode_o.is_flwadd_op = (instruction_i ==? `RV32_FLWADD);
 assign decode_o.is_load_op = (instruction_i.op == `RV32_LOAD) | (instruction_i.op == `RV32_LOAD_FP);
 assign decode_o.is_store_op = (instruction_i.op == `RV32_STORE) | (instruction_i.op == `RV32_STORE_FP);