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Use array for regular operand types
1 parent 9fb3c9c commit 7bb18ff

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+147
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‎bddisasm/bdx86_decoder.c

+147-184
Original file line numberDiff line numberDiff line change
@@ -1491,6 +1491,134 @@ static const ND_OPERAND_SIZE operandSizes[] =
14911491
};
14921492

14931493

1494+
static const ND_OPERAND operandTypes[] = {
1495+
{ }, // ND_OPT_A,
1496+
{ }, // ND_OPT_B,
1497+
{ }, // ND_OPT_C,
1498+
{ }, // ND_OPT_D,
1499+
{ }, // ND_OPT_E,
1500+
{ }, // ND_OPT_F,
1501+
{ }, // ND_OPT_G,
1502+
{ }, // ND_OPT_H,
1503+
{ }, // ND_OPT_I,
1504+
{ }, // ND_OPT_J,
1505+
{ }, // ND_OPT_K,
1506+
{ }, // ND_OPT_L,
1507+
{ }, // ND_OPT_M,
1508+
{ }, // ND_OPT_N,
1509+
{ }, // ND_OPT_O,
1510+
{ }, // ND_OPT_P,
1511+
{ }, // ND_OPT_Q,
1512+
{ }, // ND_OPT_R,
1513+
{ }, // ND_OPT_S,
1514+
{ }, // ND_OPT_T,
1515+
{ }, // ND_OPT_U,
1516+
{ }, // ND_OPT_V,
1517+
{ }, // ND_OPT_W,
1518+
{ }, // ND_OPT_X,
1519+
{ }, // ND_OPT_Y,
1520+
{ }, // ND_OPT_Z,
1521+
{ }, // ND_OPT_rB,
1522+
{ }, // ND_OPT_mB,
1523+
{ }, // ND_OPT_rK,
1524+
{ }, // ND_OPT_vK,
1525+
{ }, // ND_OPT_mK,
1526+
{ }, // ND_OPT_aK,
1527+
{ }, // ND_OPT_rM,
1528+
{ }, // ND_OPT_mM,
1529+
{ }, // ND_OPT_rT,
1530+
{ }, // ND_OPT_mT,
1531+
{ }, // ND_OPT_vT,
1532+
{ }, // ND_OPT_dfv,
1533+
{ .Type = ND_OP_CONST, .Encoding = ND_OPE_1, .Info = { .Constant = { .Const = 1 } } }, // ND_OPT_1 operand is an implicit constant (used by shift/rotate instruction).
1534+
1535+
// These are implicit arguments inside instructions.
1536+
1537+
// Special registers.
1538+
{ }, // ND_OPT_rIP,
1539+
{ .Type = ND_OP_REG, .Encoding = ND_OPE_S, .Info = { .Register = { .Type = ND_REG_MXCSR, .Size = ND_SIZE_32BIT, .Reg = 0 } } }, // ND_OPT_MXCSR The operand is implicit and is the MXCSR.
1540+
{ .Type = ND_OP_REG, .Encoding = ND_OPE_S, .Info = { .Register = { .Type = ND_REG_PKRU, .Size = ND_SIZE_32BIT, .Reg = 0 } } }, // ND_OPT_PKRU The operand is the PKRU register.
1541+
{ }, // ND_OPT_SSP,
1542+
{ .Type = ND_OP_REG, .Encoding = ND_OPE_S, .Info = { .Register = { .Type = ND_REG_UIF, .Size = ND_SIZE_8BIT, .Reg = 0 } } }, // ND_OPT_UIF The operand is the User Interrupt Flag.
1543+
1544+
1545+
// General Purpose Registers.
1546+
{ .Type = ND_OP_REG, .Encoding = ND_OPE_S, .Info = { .Register = { .Type = ND_REG_GPR, .Size = ND_SIZE_8BIT, .Reg = NDR_AH, .IsHigh8 = ND_TRUE } } }, // ND_OPT_AH Operand is the accumulator.
1547+
{ }, // ND_OPT_rAX,
1548+
{ }, // ND_OPT_rCX,
1549+
{ }, // ND_OPT_rDX,
1550+
{ }, // ND_OPT_rBX,
1551+
{ }, // ND_OPT_rSP,
1552+
{ }, // ND_OPT_rBP,
1553+
{ }, // ND_OPT_rSI,
1554+
{ }, // ND_OPT_rDI,
1555+
{ }, // ND_OPT_rR8,
1556+
{ }, // ND_OPT_rR9,
1557+
{ }, // ND_OPT_rR11,
1558+
1559+
// Segment registers.
1560+
{ }, // ND_OPT_CS,
1561+
{ }, // ND_OPT_SS,
1562+
{ }, // ND_OPT_DS,
1563+
{ }, // ND_OPT_ES,
1564+
{ }, // ND_OPT_FS,
1565+
{ }, // ND_OPT_GS,
1566+
1567+
// FPU registers.
1568+
{ .Type = ND_OP_REG, .Encoding = ND_OPE_S, .Info = { .Register = { .Type = ND_REG_FPU, .Size = ND_SIZE_80BIT, .Reg = 0 } } }, // ND_OPT_ST0 Operand is the ST(0) register.
1569+
{ }, // ND_OPT_STi,
1570+
1571+
// SSE registers.
1572+
{ .Type = ND_OP_REG, .Encoding = ND_OPE_S, .Info = { .Register = { .Type = ND_REG_SSE, .Size = ND_SIZE_128BIT, .Reg = 0 } } }, // ND_OPT_XMM0 Operand is a hard-coded XMM register.
1573+
{ .Type = ND_OP_REG, .Encoding = ND_OPE_S, .Info = { .Register = { .Type = ND_REG_SSE, .Size = ND_SIZE_128BIT, .Reg = 1 } } }, // ND_OPT_XMM1
1574+
{ .Type = ND_OP_REG, .Encoding = ND_OPE_S, .Info = { .Register = { .Type = ND_REG_SSE, .Size = ND_SIZE_128BIT, .Reg = 2 } } }, // ND_OPT_XMM2
1575+
{ .Type = ND_OP_REG, .Encoding = ND_OPE_S, .Info = { .Register = { .Type = ND_REG_SSE, .Size = ND_SIZE_128BIT, .Reg = 3 } } }, // ND_OPT_XMM3
1576+
{ .Type = ND_OP_REG, .Encoding = ND_OPE_S, .Info = { .Register = { .Type = ND_REG_SSE, .Size = ND_SIZE_128BIT, .Reg = 4 } } }, // ND_OPT_XMM4
1577+
{ .Type = ND_OP_REG, .Encoding = ND_OPE_S, .Info = { .Register = { .Type = ND_REG_SSE, .Size = ND_SIZE_128BIT, .Reg = 5 } } }, // ND_OPT_XMM5
1578+
{ .Type = ND_OP_REG, .Encoding = ND_OPE_S, .Info = { .Register = { .Type = ND_REG_SSE, .Size = ND_SIZE_128BIT, .Reg = 6 } } }, // ND_OPT_XMM6
1579+
{ .Type = ND_OP_REG, .Encoding = ND_OPE_S, .Info = { .Register = { .Type = ND_REG_SSE, .Size = ND_SIZE_128BIT, .Reg = 7 } } }, // ND_OPT_XMM7
1580+
1581+
// Implicit memory operands.
1582+
{ }, // ND_OPT_pAX, // [rAX]
1583+
{ }, // ND_OPT_pCX, // [rCX]
1584+
{ }, // ND_OPT_pBXAL, // [rBX + AL]
1585+
{ }, // ND_OPT_pDI, // [rDI]
1586+
{ }, // ND_OPT_SHS, // Shadow stack.
1587+
{ }, // ND_OPT_SHSP, // Shadow stack pointed by the SSP.
1588+
{ }, // ND_OPT_SHS0, // Shadow stack pointed by the SSP.
1589+
{ }, // ND_OPT_SMT, // Source MSR table, encoded in [RSI].
1590+
{ }, // ND_OPT_DMT, // Destination MSR table, encoded in [RDI].
1591+
1592+
// Special immediates.
1593+
{ }, // ND_OPT_m2zI,
1594+
1595+
// Misc CR/XCR/MSR/SYS registers.
1596+
{ }, // ND_OPT_CR0,
1597+
{ }, // ND_OPT_IDTR,
1598+
{ }, // ND_OPT_GDTR,
1599+
{ }, // ND_OPT_LDTR,
1600+
{ }, // ND_OPT_TR,
1601+
{ .Type = ND_OP_REG, .Encoding = ND_OPE_S, .Info = { .Register = { .Type = ND_REG_SYS, .Size = ND_SIZE_16BIT, .Reg = NDR_X87_CONTROL } } }, // ND_OPT_X87CONTROL The operand is implicit and is the x87 control word.
1602+
{ .Type = ND_OP_REG, .Encoding = ND_OPE_S, .Info = { .Register = { .Type = ND_REG_SYS, .Size = ND_SIZE_16BIT, .Reg = NDR_X87_TAG } } }, // ND_OPT_X87TAG The operand is implicit and is the x87 tag word.
1603+
{ .Type = ND_OP_REG, .Encoding = ND_OPE_S, .Info = { .Register = { .Type = ND_REG_SYS, .Size = ND_SIZE_16BIT, .Reg = NDR_X87_STATUS } } }, // ND_OPT_X87STATUS The operand is implicit and is the x87 status word.
1604+
{ .Type = ND_OP_REG, .Encoding = ND_OPE_E, .Info = { .Register = { .Type = ND_REG_MSR, .Size = ND_SIZE_64BIT, .Reg = 0xFFFFFFFF } } }, // ND_OPT_MSR The operand is implicit and is a MSR (usually selected by the ECX register).
1605+
{ .Type = ND_OP_REG, .Encoding = ND_OPE_E, .Info = { .Register = { .Type = ND_REG_XCR, .Size = ND_SIZE_64BIT, .Reg = 0xFF } } }, // ND_OPT_XCR,
1606+
{ .Type = ND_OP_REG, .Encoding = ND_OPE_S, .Info = { .Register = { .Type = ND_REG_MSR, .Size = ND_SIZE_64BIT, .Reg = NDR_IA32_TSC } } }, // ND_OPT_TSC The operand is implicit and is the IA32_TSC.
1607+
{ .Type = ND_OP_REG, .Encoding = ND_OPE_S, .Info = { .Register = { .Type = ND_REG_MSR, .Size = ND_SIZE_64BIT, .Reg = NDR_IA32_TSC_AUX } } }, // ND_OPT_TSCAUX The operand is implicit and is the IA32_TSCAUX.
1608+
{ .Type = ND_OP_REG, .Encoding = ND_OPE_S, .Info = { .Register = { .Type = ND_REG_MSR, .Size = ND_SIZE_64BIT, .Reg = NDR_IA32_SYSENTER_EIP } } }, // ND_OPT_SEIP The operand is implicit and is the IA32_SYSENTER_EIP.
1609+
{ .Type = ND_OP_REG, .Encoding = ND_OPE_S, .Info = { .Register = { .Type = ND_REG_MSR, .Size = ND_SIZE_64BIT, .Reg = NDR_IA32_SYSENTER_ESP } } }, // ND_OPT_SESP The operand is implicit and is the IA32_SYSENTER_ESP.
1610+
{ .Type = ND_OP_REG, .Encoding = ND_OPE_S, .Info = { .Register = { .Type = ND_REG_MSR, .Size = ND_SIZE_64BIT, .Reg = NDR_IA32_SYSENTER_CS } } }, // ND_OPT_SCS,
1611+
{ .Type = ND_OP_REG, .Encoding = ND_OPE_S, .Info = { .Register = { .Type = ND_REG_MSR, .Size = ND_SIZE_64BIT, .Reg = NDR_IA32_STAR } } }, // ND_OPT_STAR The operand is implicit and is the IA32_STAR.
1612+
{ .Type = ND_OP_REG, .Encoding = ND_OPE_S, .Info = { .Register = { .Type = ND_REG_MSR, .Size = ND_SIZE_64BIT, .Reg = NDR_IA32_LSTAR } } }, // ND_OPT_LSTAR The operand is implicit and is the IA32_LSTAR.
1613+
{ .Type = ND_OP_REG, .Encoding = ND_OPE_S, .Info = { .Register = { .Type = ND_REG_MSR, .Size = ND_SIZE_64BIT, .Reg = NDR_IA32_FMASK } } }, // ND_OPT_FMASK The operand is implicit and is the IA32_FMASK.
1614+
{ .Type = ND_OP_REG, .Encoding = ND_OPE_S, .Info = { .Register = { .Type = ND_REG_MSR, .Size = ND_SIZE_64BIT, .Reg = NDR_IA32_FS_BASE } } }, // ND_OPT_FSBASE The operand is implicit and is the IA32_FS_BASE MSR.
1615+
{ .Type = ND_OP_REG, .Encoding = ND_OPE_S, .Info = { .Register = { .Type = ND_REG_MSR, .Size = ND_SIZE_64BIT, .Reg = NDR_IA32_GS_BASE } } }, // ND_OPT_GSBASE The operand is implicit and is the IA32_GS_BASE MSR.
1616+
{ .Type = ND_OP_REG, .Encoding = ND_OPE_S, .Info = { .Register = { .Type = ND_REG_MSR, .Size = ND_SIZE_64BIT, .Reg = NDR_IA32_KERNEL_GS_BASE } } }, // ND_OPT_KGSBASE,
1617+
{ .Type = ND_OP_REG, .Encoding = ND_OPE_S, .Info = { .Register = { .Type = ND_REG_XCR, .Size = ND_SIZE_64BIT, .Reg = 0 } } }, // ND_OPT_XCR0 The operand is implicit and is XCR0.
1618+
{ } // ND_OPT_BANK,
1619+
};
1620+
1621+
14941622
//
14951623
// NdParseOperand
14961624
//
@@ -1855,13 +1983,6 @@ NdParseOperand(
18551983
//
18561984
switch (opt)
18571985
{
1858-
case ND_OPT_1:
1859-
// operand is an implicit constant (used by shift/rotate instruction).
1860-
operand->Type = ND_OP_CONST;
1861-
operand->Encoding = ND_OPE_1;
1862-
operand->Info.Constant.Const = 1;
1863-
break;
1864-
18651986
case ND_OPT_rIP:
18661987
// The operand is the instruction pointer.
18671988
operand->Type = ND_OP_REG;
@@ -1888,15 +2009,6 @@ NdParseOperand(
18882009
operand->Info.Register.Reg = NDR_RAX;
18892010
break;
18902011

1891-
case ND_OPT_AH:
1892-
// Operand is the accumulator.
1893-
operand->Type = ND_OP_REG;
1894-
operand->Info.Register.Type = ND_REG_GPR;
1895-
operand->Info.Register.Size = ND_SIZE_8BIT;
1896-
operand->Info.Register.Reg = NDR_AH;
1897-
operand->Info.Register.IsHigh8 = ND_TRUE;
1898-
break;
1899-
19002012
case ND_OPT_rCX:
19012013
// Operand is the counter register.
19022014
operand->Type = ND_OP_REG;
@@ -2026,14 +2138,6 @@ NdParseOperand(
20262138
operand->Info.Register.Reg = NDR_GS;
20272139
break;
20282140

2029-
case ND_OPT_ST0:
2030-
// Operand is the ST(0) register.
2031-
operand->Type = ND_OP_REG;
2032-
operand->Info.Register.Type = ND_REG_FPU;
2033-
operand->Info.Register.Size = ND_SIZE_80BIT;
2034-
operand->Info.Register.Reg = 0;
2035-
break;
2036-
20372141
case ND_OPT_STi:
20382142
// Operand is the ST(i) register.
20392143
operand->Type = ND_OP_REG;
@@ -2043,21 +2147,6 @@ NdParseOperand(
20432147
operand->Info.Register.Reg = Instrux->ModRm.rm;
20442148
break;
20452149

2046-
case ND_OPT_XMM0:
2047-
case ND_OPT_XMM1:
2048-
case ND_OPT_XMM2:
2049-
case ND_OPT_XMM3:
2050-
case ND_OPT_XMM4:
2051-
case ND_OPT_XMM5:
2052-
case ND_OPT_XMM6:
2053-
case ND_OPT_XMM7:
2054-
// Operand is a hard-coded XMM register.
2055-
operand->Type = ND_OP_REG;
2056-
operand->Info.Register.Type = ND_REG_SSE;
2057-
operand->Info.Register.Size = ND_SIZE_128BIT;
2058-
operand->Info.Register.Reg = opt - ND_OPT_XMM0;
2059-
break;
2060-
20612150
// Special operands. These are always implicit, and can't be encoded inside the instruction.
20622151
case ND_OPT_CR0:
20632152
// The operand is implicit and is control register 0.
@@ -2099,46 +2188,6 @@ NdParseOperand(
20992188
operand->Info.Register.Reg = NDR_TR;
21002189
break;
21012190

2102-
case ND_OPT_X87CONTROL:
2103-
// The operand is implicit and is the x87 control word.
2104-
operand->Type = ND_OP_REG;
2105-
operand->Info.Register.Type = ND_REG_SYS;
2106-
operand->Info.Register.Size = ND_SIZE_16BIT;
2107-
operand->Info.Register.Reg = NDR_X87_CONTROL;
2108-
break;
2109-
2110-
case ND_OPT_X87TAG:
2111-
// The operand is implicit and is the x87 tag word.
2112-
operand->Type = ND_OP_REG;
2113-
operand->Info.Register.Type = ND_REG_SYS;
2114-
operand->Info.Register.Size = ND_SIZE_16BIT;
2115-
operand->Info.Register.Reg = NDR_X87_TAG;
2116-
break;
2117-
2118-
case ND_OPT_X87STATUS:
2119-
// The operand is implicit and is the x87 status word.
2120-
operand->Type = ND_OP_REG;
2121-
operand->Info.Register.Type = ND_REG_SYS;
2122-
operand->Info.Register.Size = ND_SIZE_16BIT;
2123-
operand->Info.Register.Reg = NDR_X87_STATUS;
2124-
break;
2125-
2126-
case ND_OPT_MXCSR:
2127-
// The operand is implicit and is the MXCSR.
2128-
operand->Type = ND_OP_REG;
2129-
operand->Info.Register.Type = ND_REG_MXCSR;
2130-
operand->Info.Register.Size = ND_SIZE_32BIT;
2131-
operand->Info.Register.Reg = 0;
2132-
break;
2133-
2134-
case ND_OPT_PKRU:
2135-
// The operand is the PKRU register.
2136-
operand->Type = ND_OP_REG;
2137-
operand->Info.Register.Type = ND_REG_PKRU;
2138-
operand->Info.Register.Size = ND_SIZE_32BIT;
2139-
operand->Info.Register.Reg = 0;
2140-
break;
2141-
21422191
case ND_OPT_SSP:
21432192
// The operand is the SSP register.
21442193
operand->Type = ND_OP_REG;
@@ -2147,126 +2196,40 @@ NdParseOperand(
21472196
operand->Info.Register.Reg = 0;
21482197
break;
21492198

2199+
case ND_OPT_1:
2200+
case ND_OPT_AH:
2201+
case ND_OPT_ST0:
2202+
case ND_OPT_XMM0:
2203+
case ND_OPT_XMM1:
2204+
case ND_OPT_XMM2:
2205+
case ND_OPT_XMM3:
2206+
case ND_OPT_XMM4:
2207+
case ND_OPT_XMM5:
2208+
case ND_OPT_XMM6:
2209+
case ND_OPT_XMM7:
2210+
case ND_OPT_X87CONTROL:
2211+
case ND_OPT_X87TAG:
2212+
case ND_OPT_X87STATUS:
2213+
case ND_OPT_MXCSR:
2214+
case ND_OPT_PKRU:
21502215
case ND_OPT_UIF:
2151-
// The operand is the User Interrupt Flag.
2152-
operand->Type = ND_OP_REG;
2153-
operand->Info.Register.Type = ND_REG_UIF;
2154-
operand->Info.Register.Size = ND_SIZE_8BIT; // 1 bit, in fact, but there is no size defined for one bit.
2155-
operand->Info.Register.Reg = 0;
2156-
break;
2157-
21582216
case ND_OPT_MSR:
2159-
// The operand is implicit and is a MSR (usually selected by the ECX register).
2160-
operand->Type = ND_OP_REG;
2161-
operand->Encoding = ND_OPE_E;
2162-
operand->Info.Register.Type = ND_REG_MSR;
2163-
operand->Info.Register.Size = ND_SIZE_64BIT;
2164-
operand->Info.Register.Reg = 0xFFFFFFFF;
2165-
break;
2166-
21672217
case ND_OPT_TSC:
2168-
// The operand is implicit and is the IA32_TSC.
2169-
operand->Type = ND_OP_REG;
2170-
operand->Info.Register.Type = ND_REG_MSR;
2171-
operand->Info.Register.Size = ND_SIZE_64BIT;
2172-
operand->Info.Register.Reg = NDR_IA32_TSC;
2173-
break;
2174-
21752218
case ND_OPT_TSCAUX:
2176-
// The operand is implicit and is the IA32_TSCAUX.
2177-
operand->Type = ND_OP_REG;
2178-
operand->Info.Register.Type = ND_REG_MSR;
2179-
operand->Info.Register.Size = ND_SIZE_64BIT;
2180-
operand->Info.Register.Reg = NDR_IA32_TSC_AUX;
2181-
break;
2182-
21832219
case ND_OPT_SCS:
2184-
// The operand is implicit and is the IA32_SYSENTER_CS.
2185-
operand->Type = ND_OP_REG;
2186-
operand->Info.Register.Type = ND_REG_MSR;
2187-
operand->Info.Register.Size = ND_SIZE_64BIT;
2188-
operand->Info.Register.Reg = NDR_IA32_SYSENTER_CS;
2189-
break;
2190-
21912220
case ND_OPT_SESP:
2192-
// The operand is implicit and is the IA32_SYSENTER_ESP.
2193-
operand->Type = ND_OP_REG;
2194-
operand->Info.Register.Type = ND_REG_MSR;
2195-
operand->Info.Register.Size = ND_SIZE_64BIT;
2196-
operand->Info.Register.Reg = NDR_IA32_SYSENTER_ESP;
2197-
break;
2198-
21992221
case ND_OPT_SEIP:
2200-
// The operand is implicit and is the IA32_SYSENTER_EIP.
2201-
operand->Type = ND_OP_REG;
2202-
operand->Info.Register.Type = ND_REG_MSR;
2203-
operand->Info.Register.Size = ND_SIZE_64BIT;
2204-
operand->Info.Register.Reg = NDR_IA32_SYSENTER_EIP;
2205-
break;
2206-
22072222
case ND_OPT_STAR:
2208-
// The operand is implicit and is the IA32_STAR.
2209-
operand->Type = ND_OP_REG;
2210-
operand->Info.Register.Type = ND_REG_MSR;
2211-
operand->Info.Register.Size = ND_SIZE_64BIT;
2212-
operand->Info.Register.Reg = NDR_IA32_STAR;
2213-
break;
2214-
22152223
case ND_OPT_LSTAR:
2216-
// The operand is implicit and is the IA32_LSTAR.
2217-
operand->Type = ND_OP_REG;
2218-
operand->Info.Register.Type = ND_REG_MSR;
2219-
operand->Info.Register.Size = ND_SIZE_64BIT;
2220-
operand->Info.Register.Reg = NDR_IA32_LSTAR;
2221-
break;
2222-
22232224
case ND_OPT_FMASK:
2224-
// The operand is implicit and is the IA32_FMASK.
2225-
operand->Type = ND_OP_REG;
2226-
operand->Info.Register.Type = ND_REG_MSR;
2227-
operand->Info.Register.Size = ND_SIZE_64BIT;
2228-
operand->Info.Register.Reg = NDR_IA32_FMASK;
2229-
break;
2230-
22312225
case ND_OPT_FSBASE:
2232-
// The operand is implicit and is the IA32_FS_BASE MSR.
2233-
operand->Type = ND_OP_REG;
2234-
operand->Info.Register.Type = ND_REG_MSR;
2235-
operand->Info.Register.Size = ND_SIZE_64BIT;
2236-
operand->Info.Register.Reg = NDR_IA32_FS_BASE;
2237-
break;
2238-
22392226
case ND_OPT_GSBASE:
2240-
// The operand is implicit and is the IA32_GS_BASE MSR.
2241-
operand->Type = ND_OP_REG;
2242-
operand->Info.Register.Type = ND_REG_MSR;
2243-
operand->Info.Register.Size = ND_SIZE_64BIT;
2244-
operand->Info.Register.Reg = NDR_IA32_GS_BASE;
2245-
break;
2246-
22472227
case ND_OPT_KGSBASE:
2248-
// The operand is implicit and is the IA32_KERNEL_GS_BASE MSR.
2249-
operand->Type = ND_OP_REG;
2250-
operand->Info.Register.Type = ND_REG_MSR;
2251-
operand->Info.Register.Size = ND_SIZE_64BIT;
2252-
operand->Info.Register.Reg = NDR_IA32_KERNEL_GS_BASE;
2253-
break;
2254-
22552228
case ND_OPT_XCR:
2256-
// The operand is implicit and is an extended control register (usually selected by ECX register).
2257-
operand->Type = ND_OP_REG;
2258-
operand->Encoding = ND_OPE_E;
2259-
operand->Info.Register.Type = ND_REG_XCR;
2260-
operand->Info.Register.Size = ND_SIZE_64BIT;
2261-
operand->Info.Register.Reg = 0xFF;
2262-
break;
2263-
22642229
case ND_OPT_XCR0:
2265-
// The operand is implicit and is XCR0.
2266-
operand->Type = ND_OP_REG;
2267-
operand->Info.Register.Type = ND_REG_XCR;
2268-
operand->Info.Register.Size = ND_SIZE_64BIT;
2269-
operand->Info.Register.Reg = 0;
2230+
operand->Type = operandTypes[opt].Type;
2231+
operand->Encoding = operandTypes[opt].Encoding;
2232+
operand->Info = operandTypes[opt].Info;
22702233
break;
22712234

22722235
case ND_OPT_BANK:

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