sequencer.sch

v 20130925 2
C 40000 40000 0 0 0 title-B.sym
N 44500 48100 44400 48100 4
N 44500 48500 44100 48500 4
N 44400 49200 44400 48500 4
C 45700 49200 1 270 1 resistor-1.sym
{
T 46100 49500 5 10 0 0 90 2 1
device=RESISTOR
T 45700 49200 5 10 0 0 0 6 1
footprint=1206
T 45600 49700 5 10 1 1 0 6 1
refdes=R2
T 45600 49600 5 10 1 1 0 8 1
value=1k
}
N 45800 49200 45800 48300 4
N 45900 48300 45500 48300 4
C 46800 48400 1 180 0 resistor-1.sym
{
T 46500 48000 5 10 0 0 180 0 1
device=RESISTOR
T 46800 48400 5 10 0 0 90 0 1
footprint=1206
T 46200 48500 5 10 1 1 0 6 1
refdes=R3
T 46300 48500 5 10 1 1 0 0 1
value=100k
}
C 47100 47000 1 90 0 capacitor-1.sym
{
T 46400 47200 5 10 0 0 90 0 1
device=CAPACITOR
T 46200 47200 5 10 0 0 90 0 1
symversion=0.1
T 47100 47000 5 10 0 0 0 0 1
footprint=1206
T 46600 47500 5 10 1 1 0 6 1
refdes=C2
T 46600 47400 5 10 1 1 0 8 1
value=100n
}
N 46900 47900 46900 48300 4
N 46800 48300 48700 48300 4
C 47700 49200 1 270 1 resistor-1.sym
{
T 48100 49500 5 10 0 0 90 2 1
device=RESISTOR
T 47700 49200 5 10 0 0 0 6 1
footprint=1206
T 47600 49700 5 10 1 1 0 6 1
refdes=R4
T 47600 49600 5 10 1 1 0 8 1
value=10k
}
C 47700 45300 1 270 1 resistor-1.sym
{
T 48100 45600 5 10 0 0 90 2 1
device=RESISTOR
T 47700 45300 5 10 0 0 0 6 1
footprint=1206
T 47600 45800 5 10 1 1 0 6 1
refdes=R6
T 47600 45700 5 10 1 1 0 8 1
value=4.7k
}
C 47700 43800 1 270 1 resistor-1.sym
{
T 48100 44100 5 10 0 0 90 2 1
device=RESISTOR
T 47700 43800 5 10 0 0 0 6 1
footprint=1206
T 47600 44300 5 10 1 1 0 6 1
refdes=R7
T 47600 44200 5 10 1 1 0 8 1
value=10k
}
N 47800 47900 47800 49200 4
N 47800 44700 47800 45300 4
N 48700 47900 47800 47900 4
N 47800 44900 48700 44900 4
N 48300 45300 48300 48300 4
N 48700 45300 48300 45300 4
C 44300 49200 1 270 1 resistor-1.sym
{
T 44700 49500 5 10 0 0 90 2 1
device=RESISTOR
T 44300 49200 5 10 0 0 0 6 1
footprint=1206
T 44100 49700 5 10 1 1 0 6 1
refdes=R1
T 44100 49600 5 10 1 1 0 8 1
value=10k
}
C 47600 50200 1 0 0 12V-plus-1.sym
C 46800 46700 1 0 0 gnd-1.sym
C 47700 43500 1 0 0 gnd-1.sym
C 44200 50200 1 0 0 12V-plus-1.sym
C 45600 50200 1 0 0 12V-plus-1.sym
N 49700 45100 51100 45100 4
{
T 49900 45200 5 10 1 1 0 0 1
netname=tx_bias
}
N 45800 50200 45800 50100 4
N 44400 50200 44400 50100 4
N 47800 50100 47800 50200 4
C 47700 47000 1 270 1 resistor-1.sym
{
T 48100 47300 5 10 0 0 90 2 1
device=RESISTOR
T 47700 47000 5 10 0 0 0 6 1
footprint=1206
T 47600 47500 5 10 1 1 0 6 1
refdes=R5
T 47600 47400 5 10 1 1 0 8 1
value=4.7k
}
N 44400 48100 44400 46400 4
N 44400 46400 47800 46400 4
N 47800 46200 47800 47000 4
C 48700 44700 1 0 0 lm339-1.sym
{
T 49525 44850 5 8 0 0 0 0 1
device=LM339
T 49600 46525 5 8 0 0 0 0 1
symversion=1.0
T 48700 44700 5 10 0 0 0 0 1
slot=1
T 48700 44700 5 10 0 1 0 0 1
footprint=DIP14
T 49500 44900 5 10 1 1 0 2 1
refdes=U1
}
C 44500 47900 1 0 0 lm339-1.sym
{
T 45325 48050 5 8 0 0 0 0 1
device=LM339
T 45400 49725 5 8 0 0 0 0 1
symversion=1.0
T 44500 47900 5 10 0 0 0 0 1
slot=2
T 44500 47900 5 10 0 1 0 0 1
footprint=DIP14
T 45300 48100 5 10 1 1 0 2 1
refdes=U1
}
C 48700 47700 1 0 0 lm339-1.sym
{
T 49525 47850 5 8 0 0 0 0 1
device=LM339
T 49600 49525 5 8 0 0 0 0 1
symversion=1.0
T 48700 47700 5 10 0 0 0 0 1
slot=4
T 48700 47700 5 10 0 1 0 0 1
footprint=DIP14
T 49500 47900 5 10 1 1 0 2 1
refdes=U1
}
C 49400 45500 1 0 1 12V-plus-1.sym
C 45200 48700 1 0 1 12V-plus-1.sym
C 49400 48500 1 0 1 12V-plus-1.sym
C 49100 44400 1 0 0 gnd-1.sym
C 49100 47400 1 0 0 gnd-1.sym
C 44900 47600 1 0 0 gnd-1.sym
C 44200 47800 1 0 1 gnd-1.sym
C 44100 47900 1 0 1 header-2-1.sym
{
T 43100 48150 5 10 0 0 0 6 1
device=HEADER3
T 44100 47900 5 10 0 0 0 6 1
footprint=SIP2
T 43700 48800 5 10 1 1 0 6 1
refdes=J2
}
C 44700 41500 1 90 0 capacitor-1.sym
{
T 44000 41700 5 10 0 0 90 0 1
device=CAPACITOR
T 43800 41700 5 10 0 0 90 0 1
symversion=0.1
T 44700 41500 5 10 0 0 0 0 1
footprint=1206
T 44200 42000 5 10 1 1 0 6 1
refdes=C1
T 44200 41900 5 10 1 1 0 8 1
value=100n
}
N 44500 42400 44500 42700 4
C 44600 40800 1 0 1 gnd-1.sym
C 45200 41500 1 0 0 lm339-1.sym
{
T 46025 41650 5 8 0 0 0 0 1
device=LM339
T 46100 43325 5 8 0 0 0 0 1
symversion=1.0
T 45200 41500 5 10 0 0 0 0 1
slot=3
T 45200 41500 5 10 0 1 0 0 1
footprint=DIP14
T 46000 41700 5 10 1 1 0 2 1
refdes=U1
}
C 45500 42700 1 0 0 12V-plus-1.sym
C 45600 40800 1 0 0 gnd-1.sym
C 44900 40800 1 0 0 gnd-1.sym
N 45000 41100 45000 42100 4
N 45000 42100 45200 42100 4
N 45200 41700 45000 41700 4
C 46200 41800 1 0 0 nc-right-1.sym
{
T 46300 42300 5 10 0 0 0 0 1
value=NoConnection
T 46300 42500 5 10 0 0 0 0 1
device=DRC_Directive
}
N 45700 42700 45700 42300 4
N 45700 41100 45700 41500 4
N 44500 41100 44500 41500 4
N 49700 48100 51100 48100 4
{
T 49900 48200 5 10 1 1 0 0 1
netname=tx_relays
}
N 51100 48100 51100 46900 4
N 51100 45100 51100 46500 4
C 43500 41600 1 0 1 header-2-1.sym
{
T 42500 41850 5 10 0 0 0 6 1
device=HEADER3
T 43500 41600 5 10 0 0 0 6 1
footprint=SIP2
T 43100 42500 5 10 1 1 0 6 1
refdes=J1
}
C 44300 42700 1 0 0 12V-plus-1.sym
C 43300 42700 1 0 0 12V-plus-1.sym
C 43600 40800 1 0 1 gnd-1.sym
N 43500 41800 43500 41100 4
N 43500 42200 43500 42700 4
C 51100 45900 1 0 0 header-4-1.sym
{
T 51100 47500 5 10 0 1 0 0 1
device=HEADER4
T 51500 47600 5 10 1 1 0 0 1
refdes=J3
T 51100 45900 5 10 0 0 0 6 1
footprint=SIP4
}