lpsdr/t_filter.sch at master · bitglue/lpsdr · GitHub

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
v 20130925 2
C 40000 40000 0 0 0 title-B.sym
N 44600 45000 51700 45000 4
C 44600 44800 1 0 1 header-4-1.sym
{
T 44600 46400 5 10 0 1 0 6 1
device=HEADER4
T 44600 44800 5 10 0 0 0 0 1
footprint=SIP4
T 44200 46500 5 10 1 1 0 6 1
refdes=J1
}
C 51700 44800 1 0 0 header-4-1.sym
{
T 51700 46400 5 10 0 1 0 0 1
device=HEADER4
T 51700 44800 5 10 0 0 0 0 1
footprint=SIP4
T 52100 46500 5 10 1 1 0 0 1
refdes=J2
}
N 47400 45100 47400 45000 4
N 47900 45100 47900 45000 4
N 47900 46000 47900 46200 4
N 47400 46000 47400 46200 4
N 44600 45400 44700 45400 4
N 44700 45400 44700 45000 4
N 44600 45800 44700 45800 4
N 44700 45800 44700 48900 4
N 51700 45800 51600 45800 4
N 51600 45800 51600 48900 4
N 51700 45400 51600 45400 4
N 51600 45400 51600 45000 4
N 48900 46000 48900 46200 4
N 48400 46000 48400 46200 4
N 47600 47400 48700 47400 4
N 47400 46200 48900 46200 4
N 48400 45100 48400 45000 4
N 48900 45100 48900 45000 4
C 50250 46300 1 90 0 inductor-1.sym
{
T 50250 46800 5 10 1 1 0 1 1
refdes=L3
T 49750 46500 5 10 0 0 90 0 1
device=INDUCTOR
T 49550 46500 5 10 0 1 90 0 1
symversion=0.1
T 50250 46300 5 10 0 0 90 0 1
footprint=ACY200
}
N 49400 45100 49400 45000 4
N 49900 45100 49900 45000 4
N 49900 46000 49900 46200 4
N 49400 46000 49400 46200 4
N 50900 46000 50900 46200 4
N 50400 46000 50400 46200 4
N 49400 46200 50900 46200 4
N 50150 46300 50150 46200 4
N 50400 45100 50400 45000 4
N 50900 45100 50900 45000 4
N 50150 47200 50150 47400 4
C 45600 45100 1 90 0 capacitor-1.sym
{
T 44900 45300 5 10 0 0 90 0 1
device=CAPACITOR
T 44700 45300 5 10 0 1 90 0 1
symversion=0.1
T 45600 45100 5 10 0 0 0 0 1
footprint=1206
T 45400 44800 5 10 1 1 0 5 1
refdes=C5
}
N 45400 45100 45400 45000 4
N 45900 45100 45900 45000 4
N 45900 46000 45900 46200 4
N 45400 46000 45400 46200 4
N 46900 46000 46900 46200 4
N 46400 46000 46400 46200 4
N 45400 46200 46900 46200 4
N 46400 45100 46400 45000 4
N 46900 45100 46900 45000 4
N 45600 47400 45600 48900 4
N 45600 47400 46700 47400 4
N 49600 47400 50700 47400 4
C 48250 46300 1 90 0 inductor-1.sym
{
T 47750 46500 5 10 0 0 90 0 1
device=INDUCTOR
T 47550 46500 5 10 0 1 90 0 1
symversion=0.1
T 48250 46300 5 10 0 0 90 0 1
footprint=ACY200
T 48250 46800 5 10 1 1 0 1 1
refdes=L2
}
N 48150 46300 48150 46200 4
N 48150 47200 48150 47400 4
C 46250 46300 1 90 0 inductor-1.sym
{
T 45750 46500 5 10 0 0 90 0 1
device=INDUCTOR
T 45550 46500 5 10 0 1 90 0 1
symversion=0.1
T 46250 46300 5 10 0 0 90 0 1
footprint=ACY200
T 46250 46800 5 10 1 1 0 1 1
refdes=L1
}
N 46150 46300 46150 46200 4
N 46150 47200 46150 47400 4
N 44700 46200 44600 46200 4
N 51700 46200 51600 46200 4
C 45600 49100 1 180 0 capacitor-1.sym
{
T 45400 48400 5 10 0 0 180 6 1
device=CAPACITOR
T 45400 48200 5 10 0 1 180 6 1
symversion=0.1
T 45600 49100 5 10 0 0 0 6 1
footprint=1206
T 45000 49000 5 10 1 1 0 6 1
refdes=C1
}
C 45600 48600 1 180 0 capacitor-1.sym
{
T 45400 47900 5 10 0 0 180 6 1
device=CAPACITOR
T 45400 47700 5 10 0 1 180 6 1
symversion=0.1
T 45600 48600 5 10 0 0 0 6 1
footprint=1206
T 45000 48500 5 10 1 1 0 6 1
refdes=C2
}
C 45600 47600 1 180 0 capacitor-1.sym
{
T 45400 46900 5 10 0 0 180 6 1
device=CAPACITOR
T 45400 46700 5 10 0 1 180 6 1
symversion=0.1
T 45600 47600 5 10 0 0 0 6 1
footprint=1206
T 45000 47500 5 10 1 1 0 6 1
refdes=C4
}
C 45600 48100 1 180 0 capacitor-1.sym
{
T 45400 47400 5 10 0 0 180 6 1
device=CAPACITOR
T 45400 47200 5 10 0 1 180 6 1
symversion=0.1
T 45600 48100 5 10 0 0 0 6 1
footprint=1206
T 45000 48000 5 10 1 1 0 6 1
refdes=C3
}
N 47600 47400 47600 48900 4
C 47600 49100 1 180 0 capacitor-1.sym
{
T 47400 48400 5 10 0 0 180 6 1
device=CAPACITOR
T 47400 48200 5 10 0 1 180 6 1
symversion=0.1
T 47600 49100 5 10 0 0 0 6 1
footprint=1206
T 47000 49000 5 10 1 1 0 6 1
refdes=C9
}
C 47600 48600 1 180 0 capacitor-1.sym
{
T 47400 47900 5 10 0 0 180 6 1
device=CAPACITOR
T 47400 47700 5 10 0 1 180 6 1
symversion=0.1
T 47600 48600 5 10 0 0 0 6 1
footprint=1206
T 47000 48500 5 10 1 1 0 6 1
refdes=C10
}
C 47600 47600 1 180 0 capacitor-1.sym
{
T 47400 46900 5 10 0 0 180 6 1
device=CAPACITOR
T 47400 46700 5 10 0 1 180 6 1
symversion=0.1
T 47600 47600 5 10 0 0 0 6 1
footprint=1206
T 47000 47500 5 10 1 1 0 6 1
refdes=C12
}
C 47600 48100 1 180 0 capacitor-1.sym
{
T 47400 47400 5 10 0 0 180 6 1
device=CAPACITOR
T 47400 47200 5 10 0 1 180 6 1
symversion=0.1
T 47600 48100 5 10 0 0 0 6 1
footprint=1206
T 47000 48000 5 10 1 1 0 6 1
refdes=C11
}
N 46700 47400 46700 48900 4
N 49600 47400 49600 48900 4
C 49600 49100 1 180 0 capacitor-1.sym
{
T 49400 48400 5 10 0 0 180 6 1
device=CAPACITOR
T 49400 48200 5 10 0 1 180 6 1
symversion=0.1
T 49600 49100 5 10 0 0 0 6 1
footprint=1206
T 49000 49000 5 10 1 1 0 6 1
refdes=C17
}
C 49600 48600 1 180 0 capacitor-1.sym
{
T 49400 47900 5 10 0 0 180 6 1
device=CAPACITOR
T 49400 47700 5 10 0 1 180 6 1
symversion=0.1
T 49600 48600 5 10 0 0 0 6 1
footprint=1206
T 49000 48500 5 10 1 1 0 6 1
refdes=C18
}
C 49600 47600 1 180 0 capacitor-1.sym
{
T 49400 46900 5 10 0 0 180 6 1
device=CAPACITOR
T 49400 46700 5 10 0 1 180 6 1
symversion=0.1
T 49600 47600 5 10 0 0 0 6 1
footprint=1206
T 49000 47500 5 10 1 1 0 6 1
refdes=C20
}
C 49600 48100 1 180 0 capacitor-1.sym
{
T 49400 47400 5 10 0 0 180 6 1
device=CAPACITOR
T 49400 47200 5 10 0 1 180 6 1
symversion=0.1
T 49600 48100 5 10 0 0 0 6 1
footprint=1206
T 49000 48000 5 10 1 1 0 6 1
refdes=C19
}
N 48700 47400 48700 48900 4
C 51600 49100 1 180 0 capacitor-1.sym
{
T 51400 48400 5 10 0 0 180 6 1
device=CAPACITOR
T 51400 48200 5 10 0 1 180 6 1
symversion=0.1
T 51600 49100 5 10 0 0 0 6 1
footprint=1206
T 51000 49000 5 10 1 1 0 6 1
refdes=C25
}
C 51600 48600 1 180 0 capacitor-1.sym
{
T 51400 47900 5 10 0 0 180 6 1
device=CAPACITOR
T 51400 47700 5 10 0 1 180 6 1
symversion=0.1
T 51600 48600 5 10 0 0 0 6 1
footprint=1206
T 51000 48500 5 10 1 1 0 6 1
refdes=C26
}
C 51600 47600 1 180 0 capacitor-1.sym
{
T 51400 46900 5 10 0 0 180 6 1
device=CAPACITOR
T 51400 46700 5 10 0 1 180 6 1
symversion=0.1
T 51600 47600 5 10 0 0 0 6 1
footprint=1206
T 51000 47500 5 10 1 1 0 6 1
refdes=C28
}
C 51600 48100 1 180 0 capacitor-1.sym
{
T 51400 47400 5 10 0 0 180 6 1
device=CAPACITOR
T 51400 47200 5 10 0 1 180 6 1
symversion=0.1
T 51600 48100 5 10 0 0 0 6 1
footprint=1206
T 51000 48000 5 10 1 1 0 6 1
refdes=C27
}
N 50700 47400 50700 48900 4
C 46100 45100 1 90 0 capacitor-1.sym
{
T 45400 45300 5 10 0 0 90 0 1
device=CAPACITOR
T 45200 45300 5 10 0 1 90 0 1
symversion=0.1
T 46100 45100 5 10 0 0 0 0 1
footprint=1206
T 45900 44800 5 10 1 1 0 5 1
refdes=C6
}
C 46600 45100 1 90 0 capacitor-1.sym
{
T 45900 45300 5 10 0 0 90 0 1
device=CAPACITOR
T 45700 45300 5 10 0 1 90 0 1
symversion=0.1
T 46600 45100 5 10 0 0 0 0 1
footprint=1206
T 46400 44800 5 10 1 1 0 5 1
refdes=C7
}
C 47100 45100 1 90 0 capacitor-1.sym
{
T 46400 45300 5 10 0 0 90 0 1
device=CAPACITOR
T 46200 45300 5 10 0 1 90 0 1
symversion=0.1
T 47100 45100 5 10 0 0 0 0 1
footprint=1206
T 46900 44800 5 10 1 1 0 5 1
refdes=C8
}
C 47600 45100 1 90 0 capacitor-1.sym
{
T 46900 45300 5 10 0 0 90 0 1
device=CAPACITOR
T 46700 45300 5 10 0 1 90 0 1
symversion=0.1
T 47600 45100 5 10 0 0 0 0 1
footprint=1206
T 47400 44800 5 10 1 1 0 5 1
refdes=C13
}
C 48100 45100 1 90 0 capacitor-1.sym
{
T 47400 45300 5 10 0 0 90 0 1
device=CAPACITOR
T 47200 45300 5 10 0 1 90 0 1
symversion=0.1
T 48100 45100 5 10 0 0 0 0 1
footprint=1206
T 47900 44800 5 10 1 1 0 5 1
refdes=C14
}
C 48600 45100 1 90 0 capacitor-1.sym
{
T 47900 45300 5 10 0 0 90 0 1
device=CAPACITOR
T 47700 45300 5 10 0 1 90 0 1
symversion=0.1
T 48600 45100 5 10 0 0 0 0 1
footprint=1206
T 48400 44800 5 10 1 1 0 5 1
refdes=C15
}
C 49100 45100 1 90 0 capacitor-1.sym
{
T 48400 45300 5 10 0 0 90 0 1
device=CAPACITOR
T 48200 45300 5 10 0 1 90 0 1
symversion=0.1
T 49100 45100 5 10 0 0 0 0 1
footprint=1206
T 48900 44800 5 10 1 1 0 5 1
refdes=C16
}
C 49600 45100 1 90 0 capacitor-1.sym
{
T 48900 45300 5 10 0 0 90 0 1
device=CAPACITOR
T 48700 45300 5 10 0 1 90 0 1
symversion=0.1
T 49600 45100 5 10 0 0 0 0 1
footprint=1206
T 49400 44800 5 10 1 1 0 5 1
refdes=C21
}
C 50100 45100 1 90 0 capacitor-1.sym
{
T 49400 45300 5 10 0 0 90 0 1
device=CAPACITOR
T 49200 45300 5 10 0 1 90 0 1
symversion=0.1
T 50100 45100 5 10 0 0 0 0 1
footprint=1206
T 49900 44800 5 10 1 1 0 5 1
refdes=C22
}
C 50600 45100 1 90 0 capacitor-1.sym
{
T 49900 45300 5 10 0 0 90 0 1
device=CAPACITOR
T 49700 45300 5 10 0 1 90 0 1
symversion=0.1
T 50600 45100 5 10 0 0 0 0 1
footprint=1206
T 50400 44800 5 10 1 1 0 5 1
refdes=C23
}
C 51100 45100 1 90 0 capacitor-1.sym
{
T 50400 45300 5 10 0 0 90 0 1
device=CAPACITOR
T 50200 45300 5 10 0 1 90 0 1
symversion=0.1
T 51100 45100 5 10 0 0 0 0 1
footprint=1206
T 50900 44800 5 10 1 1 0 5 1
refdes=C24
}