riscv32: Add very basic support for Hazard3 SoC on Icebreaker SPRAM

Author: ALTracer

src/target/riscv32.c

@@ -71,6 +71,13 @@ static void riscv32_regs_write(target_s *target, const void *data);
 static int riscv32_breakwatch_set(target_s *target, breakwatch_s *breakwatch);
 static int riscv32_breakwatch_clear(target_s *target, breakwatch_s *breakwatch);
 
+bool hazard3_probe(target_s *const target)
+{
+	target->driver = "Hazard3";
+	target_add_ram32(target, 0x0, 131072);
+	return true;
+}
+
 bool riscv32_probe(target_s *const target)
 {
 	/* 'E' base ISA has 16 GPRs + PC, 'I' base ISA has 32 GPRs + PC */
@@ -102,6 +109,9 @@ bool riscv32_probe(target_s *const target)
 		PROBE(ch32v003x_probe);
 		PROBE(ch32vx_probe);
 		break;
+	case 0xe77:
+		PROBE(hazard3_probe);
+		break;
 	default:
 		break;
 	}