Concurrency compatibility

[avonwyss]

I'm looking forward to use AceRoutine on some ESP32 project. Since performance is important I'd like to actually use both cores of the ESP32 in parallel. Using the second core is not hard per se, e.g. a call to xTaskCreatePinnedToCore with a task performing an infinite loop should do the trick. But this of course brings us all the nastiness of concurrent execution, synchronization requirements etc.

So I was wondering how you see the chances of getting both cores to work on running coroutine code simultaneously. Obviously the scheduler would need to be different and take care of some synchronization. Also, channels would need to be extended for communication to work across cores and their guarantees to remain valid. Do you see any conceptional or general issues which would prevent this from working?

[bxparks]

Do you have any documentation of how the ESP32 handles parallelism? What's the memory model between the 2 processors? What sort of mutexes or semaphores are provided? The nice thing about AceRoutine's implementation of coroutines is that you never have to worry about simultaneous mutations, because everything is single threaded. But with 2 processors, all of those assumptions go out the window.

This is a very interesting problem, and I would love to work on this... but realistically, I have zero time to work on it, too many things on my plate right now. But I would very much appreciate being informed of your progress.

[avonwyss]

Thank you for your reply. I'm not completely sure about the details of the memory model, but it should be documented in the Xtensa Instruction Set Architecture (ISA).

However, FreeRTOS does have both synchronization primitives support (queues/semaphore/mutex) and also task notifications, so these may be the way to go instead of trying to manually get concurrency and the memory model right in code.

That being said, while browsing the FreeRTOS docs I've noticed that there is some co-routine support built in. From the specified limitations it seems that these do use a variant of Duff's Device, and it is also currently not clear to me how these would work in a multicore environment.

I'll try to remember to post my progress when I'll work on it (won't be in the next weeks through...).