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| 1 | +test run |
| 2 | +; target s390x TODO: Not yet implemented on s390x |
| 3 | +set enable_simd |
| 4 | +target x86_64 machinst skylake |
| 5 | + |
| 6 | +function %fmin_pseudo_f32(f32, f32) -> f32 { |
| 7 | +block0(v0:f32, v1:f32): |
| 8 | + v2 = fmin_pseudo v0, v1 |
| 9 | + return v2 |
| 10 | +} |
| 11 | +; run: %fmin_pseudo_f32(0x1.0, 0x2.0) == 0x1.0 |
| 12 | +; run: %fmin_pseudo_f32(NaN, 0x2.0) == NaN |
| 13 | +; run: %fmin_pseudo_f32(0x0.1, NaN) == 0x0.1 |
| 14 | +; run: %fmin_pseudo_f32(0x0.0, -0x0.0) == 0x0.0 |
| 15 | +; run: %fmin_pseudo_f32(-0x0.0, 0x0.0) == -0x0.0 |
| 16 | + |
| 17 | +function %fmax_pseudo_f32(f32, f32) -> f32 { |
| 18 | +block0(v0:f32, v1:f32): |
| 19 | + v2 = fmax_pseudo v0, v1 |
| 20 | + return v2 |
| 21 | +} |
| 22 | +; run: %fmax_pseudo_f32(0x1.0, 0x2.0) == 0x2.0 |
| 23 | +; run: %fmax_pseudo_f32(NaN, 0x2.0) == NaN |
| 24 | +; run: %fmax_pseudo_f32(0x0.1, NaN) == 0x0.1 |
| 25 | +; run: %fmax_pseudo_f32(0x0.0, 0x0.0) == 0x0.0 |
| 26 | +; run: %fmax_pseudo_f32(-0x0.0, 0x0.0) == -0x0.0 |
| 27 | + |
| 28 | +function %fmin_pseudo_f64(f64, f64) -> f64 { |
| 29 | +block0(v0:f64, v1:f64): |
| 30 | + v2 = fmin_pseudo v0, v1 |
| 31 | + return v2 |
| 32 | +} |
| 33 | +; run: %fmin_pseudo_f64(0x1.0, 0x2.0) == 0x1.0 |
| 34 | +; run: %fmin_pseudo_f64(NaN, 0x2.0) == NaN |
| 35 | +; run: %fmin_pseudo_f64(0x0.1, NaN) == 0x0.1 |
| 36 | +; run: %fmin_pseudo_f64(0x0.0, -0x0.0) == 0x0.0 |
| 37 | +; run: %fmin_pseudo_f64(-0x0.0, 0x0.0) == -0x0.0 |
| 38 | + |
| 39 | +function %fmax_pseudo_f64(f64, f64) -> f64 { |
| 40 | +block0(v0:f64, v1:f64): |
| 41 | + v2 = fmax_pseudo v0, v1 |
| 42 | + return v2 |
| 43 | +} |
| 44 | +; run: %fmax_pseudo_f64(0x1.0, 0x2.0) == 0x2.0 |
| 45 | +; run: %fmax_pseudo_f64(NaN, 0x2.0) == NaN |
| 46 | +; run: %fmax_pseudo_f64(0x0.1, NaN) == 0x0.1 |
| 47 | +; run: %fmax_pseudo_f64(0x0.0, 0x0.0) == 0x0.0 |
| 48 | +; run: %fmax_pseudo_f64(-0x0.0, 0x0.0) == -0x0.0 |
| 49 | + |
| 50 | +target aarch64 ; TODO scalar fmin_pseudo and fmax_pseudo are unimplemented for AArch64 |
| 51 | + |
| 52 | +function %fmin_pseudo_f32x4(f32x4, f32x4) -> f32x4 { |
| 53 | +block0(v0:f32x4, v1:f32x4): |
| 54 | + v2 = fmin_pseudo v0, v1 |
| 55 | + return v2 |
| 56 | +} |
| 57 | +; run: %fmin_pseudo_f32x4([0x1.0 NaN 0x0.1 -0x0.0], [0x2.0 0x2.0 NaN 0x0.0]) == [0x1.0 NaN 0x0.1 -0x0.0] |
| 58 | + |
| 59 | +function %fmax_pseudo_f32x4(f32x4, f32x4) -> f32x4 { |
| 60 | +block0(v0:f32x4, v1:f32x4): |
| 61 | + v2 = fmax_pseudo v0, v1 |
| 62 | + return v2 |
| 63 | +} |
| 64 | +; run: %fmax_pseudo_f32x4([0x1.0 NaN 0x0.1 -0x0.0], [0x2.0 0x2.0 NaN 0x0.0]) == [0x2.0 NaN 0x0.1 -0x0.0] |
| 65 | + |
| 66 | +function %fmin_pseudo_f64x2(f64x2, f64x2) -> f64x2 { |
| 67 | +block0(v0:f64x2, v1:f64x2): |
| 68 | + v2 = fmin_pseudo v0, v1 |
| 69 | + return v2 |
| 70 | +} |
| 71 | +; run: %fmin_pseudo_f64x2([0x1.0 NaN], [0x2.0 0x2.0]) == [0x1.0 NaN] |
| 72 | +; run: %fmin_pseudo_f64x2([0x0.1 -0x0.0], [NaN 0x0.0]) == [0x0.1 -0x0.0] |
| 73 | + |
| 74 | +function %fmax_pseudo_f64x2(f64x2, f64x2) -> f64x2 { |
| 75 | +block0(v0:f64x2, v1:f64x2): |
| 76 | + v2 = fmax_pseudo v0, v1 |
| 77 | + return v2 |
| 78 | +} |
| 79 | +; run: %fmax_pseudo_f64x2([0x1.0 NaN], [0x2.0 0x2.0]) == [0x2.0 NaN] |
| 80 | +; run: %fmax_pseudo_f64x2([0x0.1 -0x0.0], [NaN 0x0.0]) == [0x0.1 -0x0.0] |
| 81 | + |
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