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Issues list

Cranelift: RISCV frame pointer position differs from LLVM bug Incorrect behavior in the current implementation that needs fixing cranelift:area:debug cranelift:area:riscv64 Issues related to the RISC-V 64 backend. cranelift Issues related to the Cranelift code generator wasmtime:debugging Issues related to debugging of JIT'ed code
#10281 opened Feb 24, 2025 by JonasKruckenberg
cranelift: Disable NaN Canonicalization for RISC-V cranelift:area:riscv64 Issues related to the RISC-V 64 backend.
#7322 opened Oct 21, 2023 by afonso360
riscv64: Add Support For Linker Relaxation cranelift:area:riscv64 Issues related to the RISC-V 64 backend.
#7191 opened Oct 8, 2023 by afonso360
riscv64: Improve Clobber Save/Restore Sequence cranelift:area:riscv64 Issues related to the RISC-V 64 backend.
#7190 opened Oct 8, 2023 by afonso360
riscv64: Improve codegen for operations that use vslideup cranelift:area:riscv64 Issues related to the RISC-V 64 backend.
#7188 opened Oct 8, 2023 by afonso360
riscv64: Implement Zvbb - Vector Basic Bit-manipulation Extension cranelift:area:riscv64 Issues related to the RISC-V 64 backend.
#7187 opened Oct 8, 2023 by afonso360
riscv64: Implement Remaining Vector Instructions cranelift:area:riscv64 Issues related to the RISC-V 64 backend.
#7186 opened Oct 8, 2023 by afonso360
1 of 20 tasks
riscv64: Suboptimal register allocation for short function cranelift:area:regalloc Issues related to register allocation. cranelift:area:riscv64 Issues related to the RISC-V 64 backend. cranelift Issues related to the Cranelift code generator
#7147 opened Oct 4, 2023 by afonso360
3
riscv64: Refactor Inst::generate_imm cranelift:area:riscv64 Issues related to the RISC-V 64 backend.
#6922 opened Aug 29, 2023 by afonso360
riscv64: Add matchers for splat or vconst in SIMD lowering rules. cranelift:area:riscv64 Issues related to the RISC-V 64 backend. cranelift Issues related to the Cranelift code generator
#6826 opened Aug 9, 2023 by afonso360
riscv64: Improve SIMD icmp with immediates cranelift:area:riscv64 Issues related to the RISC-V 64 backend. cranelift Issues related to the Cranelift code generator
#6623 opened Jun 22, 2023 by afonso360
riscv64: Improve SIMD ExtAddPairwise Instruction Codegen cranelift:area:riscv64 Issues related to the RISC-V 64 backend. cranelift Issues related to the Cranelift code generator
#6600 opened Jun 17, 2023 by afonso360
riscv64: Merge vector mask generation rules with vector constant generation rules cranelift:area:riscv64 Issues related to the RISC-V 64 backend.
#6571 opened Jun 13, 2023 by afonso360
Support bitcasting between scalar and vector types cranelift:area:aarch64 Issues related to AArch64 backend. cranelift:area:riscv64 Issues related to the RISC-V 64 backend. cranelift:area:s390x Issues related to Cranelift's s390x backend cranelift:area:x64 Issues related to x64 codegen cranelift:E-compiler-easy Beginner–Intermediate compiler issues. cranelift Issues related to the Cranelift code generator
#6104 opened Mar 27, 2023 by bjorn3
8
Cranelift: bus error with unaligned atomics on RISC-V backend bug Incorrect behavior in the current implementation that needs fixing cranelift:area:riscv64 Issues related to the RISC-V 64 backend. cranelift Issues related to the Cranelift code generator
#5882 opened Feb 25, 2023 by afonso360
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