Fix verification generation for event driven simulators (#2455)

Event driven simulators (such as vivado xsim and synopsys vcs) behave
fundamentally differently than cycle based simulators like icarus and
verilator. Rather than taking a full cycle step at a time, individual
values within a cycle can be updated independently of each other, which
makes the current way of combinationally checking disjoint guards
invalid. We can fix this issue by only performing disjoint checks at the
positive edge of the clock, which is fine because it's the only time
that we truly care about the guards being disjoint. Without these fixes
you have to turn off verification to run calyx verilog through
commercial simulators.

Author: andrewb1999

calyx/backend/src/verilog.rs

@@ -647,7 +647,7 @@ fn emit_component<F: io::Write>(
                 if let Some(check) =
                     emit_guard_disjoint_check(dst, asgns, &pool, true)
                 {
-                    writeln!(f, "always_comb begin")?;
+                    writeln!(f, "always_ff @(posedge clk) begin")?;
                     writeln!(f, "  {check}")?;
                     writeln!(f, "end")?;
                 }

tests/backend/verilog/data-instance.expect

@@ -145,7 +145,7 @@ assign data_add_multi_left =
   _guard1 ? 2'd2 :
   _guard3 ? 2'd3 :
   'x;
-always_comb begin
+always_ff @(posedge clk) begin
   if(~$onehot0({_guard3, _guard1})) begin
     $fatal(2, "Multiple assignment to port `data_add_multi.left'.");
 end

tests/errors/runtime/multiple-drivers.expect

@@ -1,2 +1,2 @@
-[70] %Error: Assertion failed in TOP.toplevel.main: Multiple assignment to port `r.in'.
+[90] %Error: Assertion failed in TOP.toplevel.main: Multiple assignment to port `r.in'.
 %Error: Verilog $stop