[yxi] Rename calyx-axi-wrapper clock signal to ap_clk (#2386)

Another PR whittling down the changes present in #2267.
This PR changes the toplevel clock signal from `clk` to `ap_clk`. This
should allow us to reuse the existing
[`gen_xo.tcl`](https://github.com/calyxir/calyx/blob/main/fud2/rsrc/gen_xo.tcl#L34-L37)
and maintain backwards compatibility with the old verilog-axi-wrapper,
without requiring a distinction between the two in the `gen_xo.tcl`
file.

Also fixes a bsd vs gnu `sed` syntax error. The new command should work
on both.
(bsd sed require terminating commands to end with a `;`, gnu does not)

I'll also note that this PR touches a bunch of runt cocotb tests in
`tests/axi`. I'm aware that there is a desire to get rid of large
snapshots as they tend to get ignored. For now this setup is the best
thing I have to make sure breaking changes aren't introduced to either
axi-wrapper, so choosing to update them for now.

Author: nathanielnrn

fud2/scripts/cocotb-axi.rhai

@@ -26,7 +26,7 @@ fn cocotb_setup(e) {
     e.rule("copy", "cp $in $out");
     // This cleans up the extra `make` cruft, leaving what is in between `{` and `}.`
     e.rule(
-      "cleanup-cocotb", `sed -n '/Output:/,/make\[1\]/{/Output:/d;/make\[1\]/d;p}' $in > $out`
+      "cleanup-cocotb", `sed -n '/Output:/,/make\[1\]/{/Output:/d;/make\[1\]/d;p;}' $in > $out`
     );
 }
 
@@ -49,6 +49,8 @@ op(
     c::verilog_noverify,
     cocotb_axi,
     |e, input, output| {
+        // Cocotb wants files relative to the location of the makefile.
+        // This is annoying to calculate on the fly, so we just copy necessary files to the build directory
         e.build_cmd(
             ["Makefile"],
             "copy",

fud2/tests/snapshots/tests__test@plan_calyx-to-cocotb-axi.snap

@@ -26,7 +26,7 @@ rule make-cocotb
 rule copy
   command = cp $in $out
 rule cleanup-cocotb
-  command = sed -n '/Output:/,/make\[1\]/{/Output:/d;/make\[1\]/d;p}' $in > $out
+  command = sed -n '/Output:/,/make\[1\]/{/Output:/d;/make\[1\]/d;p;}' $in > $out
 
 build Makefile: copy $cocotb-makefile-dir/Makefile
 build axi_test.py: copy $cocotb-makefile-dir/axi_test.py

yxi/axi-calyx/axi_generator.py

@@ -459,6 +459,8 @@ def add_main_comp(prog, mems):
     main_compute = wrapper_comp.comp_instance(
         "main_compute", "main", check_undeclared=False
     )
+    # Naming the clock signal `ap_clk` ensures Xilinx tool compatability
+    wrapper_comp.input("ap_clk", 1, ["clk"])
 
     for mem in mems:
         mem_name = mem[name_key]

yxi/axi-calyx/cocotb/axi_test.py

@@ -32,12 +32,9 @@ async def setup_rams(self, data: Mapping[str, Any]):
             # i.e m0_axi_RDATA.
             # These prefixes have to match verilog code. See kernel.xml <args>
             # and ports assigned within that for guidance.
-            # In general, the index of `m<idx>_axi` just
-            # increments by 1 in fud axi generation
-            #print(f"mem is: {mem}")
             rams[mem] = AxiRam(
                 AxiBus.from_prefix(self.toplevel, f"{mem}"),
-                self.toplevel.clk,
+                self.toplevel.ap_clk,
                 reset = self.toplevel.reset,
                 # self.toplevel.ap_rst_n,
                 size=size,
@@ -56,7 +53,7 @@ def get_rams(self):
     async def init_toplevel(self):
         await Timer(50, "ns")
         self.toplevel.reset.value = 1
-        await ClockCycles(self.toplevel.clk, 5)
+        await ClockCycles(self.toplevel.ap_clk, 5)
         self.toplevel.reset.value = 0
         self.toplevel.go.value = 1
 
@@ -73,10 +70,10 @@ async def run_kernel_test(toplevel, data_path: str):
 
 
     # set up clock of 2ns period, simulator default timestep is 1ps
-    cocotb.start_soon(Clock(toplevel.clk, 2, units="ns").start())
+    cocotb.start_soon(Clock(toplevel.ap_clk, 2, units="ns").start())
     await tb.init_toplevel()
     await Timer(100, "ns")
-    await FallingEdge(toplevel.clk)
+    await FallingEdge(toplevel.ap_clk)
 
 
     # Finish when ap_done is high or 100 us of simulation have passed.

yxi/axi-calyx/dynamic_axi_generator.py

@@ -626,6 +626,8 @@ def add_main_comp(prog, mems):
     main_compute = wrapper_comp.comp_instance(
         "main_compute", "main", check_undeclared=False
     )
+    # Naming the clock signal `ap_clk` ensures Xilinx tool compatability
+    wrapper_comp.input("ap_clk", 1, ["clk"])
 
     for mem in mems:
         mem_name = mem[name_key]

yxi/tests/axi/dynamic/dyn-mem-vec-add-axi-wrapped.expect

@@ -9105,6 +9105,7 @@ assign invoke1_done_in = read_controller_Sum0_done;
 // COMPONENT END: axi_dyn_mem_Sum0
 endmodule
 module wrapper(
+  input logic ap_clk,
   input logic A0_ARESETn,
   input logic A0_ARREADY,
   input logic A0_RVALID,
@@ -9199,7 +9200,6 @@ module wrapper(
   output logic Sum0_WID,
   output logic Sum0_BID,
   input logic go,
-  input logic clk,
   input logic reset,
   output logic done
 );
@@ -9507,7 +9507,7 @@ assign axi_dyn_mem_A0_write_en =
   _guard1 ? main_compute_A0_write_en :
   1'd0;
 assign axi_dyn_mem_A0_RDATA = A0_RDATA;
-assign axi_dyn_mem_A0_clk = clk;
+assign axi_dyn_mem_A0_clk = ap_clk;
 assign axi_dyn_mem_A0_addr0 =
   _guard2 ? main_compute_A0_addr0 :
   3'd0;
@@ -9527,7 +9527,7 @@ assign axi_dyn_mem_Sum0_write_en =
   _guard4 ? main_compute_Sum0_write_en :
   1'd0;
 assign axi_dyn_mem_Sum0_RDATA = Sum0_RDATA;
-assign axi_dyn_mem_Sum0_clk = clk;
+assign axi_dyn_mem_Sum0_clk = ap_clk;
 assign axi_dyn_mem_Sum0_addr0 =
   _guard5 ? main_compute_Sum0_addr0 :
   3'd0;
@@ -9613,7 +9613,7 @@ assign main_compute_B0_read_data =
 assign main_compute_Sum0_done =
   _guard11 ? axi_dyn_mem_Sum0_done :
   1'd0;
-assign main_compute_clk = clk;
+assign main_compute_clk = ap_clk;
 assign main_compute_B0_done =
   _guard12 ? axi_dyn_mem_B0_done :
   1'd0;
@@ -9631,7 +9631,7 @@ assign axi_dyn_mem_B0_write_en =
   _guard15 ? main_compute_B0_write_en :
   1'd0;
 assign axi_dyn_mem_B0_RDATA = B0_RDATA;
-assign axi_dyn_mem_B0_clk = clk;
+assign axi_dyn_mem_B0_clk = ap_clk;
 assign axi_dyn_mem_B0_addr0 =
   _guard16 ? main_compute_B0_addr0 :
   3'd0;

yxi/tests/axi/dynamic/dyn-mem-vec-add-axi-wrapped.futil

@@ -670,7 +670,7 @@ component axi_dyn_mem_Sum0(@write_together(1) @data addr0: 3, @write_together(1)
     }
   }
 }
-component wrapper<"toplevel"=1>(A0_ARESETn: 1, A0_ARREADY: 1, A0_RVALID: 1, A0_RLAST: 1, A0_RDATA: 32, A0_RRESP: 2, A0_AWREADY: 1, A0_WREADY: 1, A0_BVALID: 1, A0_BRESP: 2, A0_RID: 1, B0_ARESETn: 1, B0_ARREADY: 1, B0_RVALID: 1, B0_RLAST: 1, B0_RDATA: 32, B0_RRESP: 2, B0_AWREADY: 1, B0_WREADY: 1, B0_BVALID: 1, B0_BRESP: 2, B0_RID: 1, Sum0_ARESETn: 1, Sum0_ARREADY: 1, Sum0_RVALID: 1, Sum0_RLAST: 1, Sum0_RDATA: 32, Sum0_RRESP: 2, Sum0_AWREADY: 1, Sum0_WREADY: 1, Sum0_BVALID: 1, Sum0_BRESP: 2, Sum0_RID: 1) -> (A0_ARVALID: 1, A0_ARADDR: 64, A0_ARSIZE: 3, A0_ARLEN: 8, A0_ARBURST: 2, A0_RREADY: 1, A0_AWVALID: 1, A0_AWADDR: 64, A0_AWSIZE: 3, A0_AWLEN: 8, A0_AWBURST: 2, A0_AWPROT: 3, A0_WVALID: 1, A0_WLAST: 1, A0_WDATA: 32, A0_BREADY: 1, A0_ARID: 1, A0_AWID: 1, A0_WID: 1, A0_BID: 1, B0_ARVALID: 1, B0_ARADDR: 64, B0_ARSIZE: 3, B0_ARLEN: 8, B0_ARBURST: 2, B0_RREADY: 1, B0_AWVALID: 1, B0_AWADDR: 64, B0_AWSIZE: 3, B0_AWLEN: 8, B0_AWBURST: 2, B0_AWPROT: 3, B0_WVALID: 1, B0_WLAST: 1, B0_WDATA: 32, B0_BREADY: 1, B0_ARID: 1, B0_AWID: 1, B0_WID: 1, B0_BID: 1, Sum0_ARVALID: 1, Sum0_ARADDR: 64, Sum0_ARSIZE: 3, Sum0_ARLEN: 8, Sum0_ARBURST: 2, Sum0_RREADY: 1, Sum0_AWVALID: 1, Sum0_AWADDR: 64, Sum0_AWSIZE: 3, Sum0_AWLEN: 8, Sum0_AWBURST: 2, Sum0_AWPROT: 3, Sum0_WVALID: 1, Sum0_WLAST: 1, Sum0_WDATA: 32, Sum0_BREADY: 1, Sum0_ARID: 1, Sum0_AWID: 1, Sum0_WID: 1, Sum0_BID: 1) {
+component wrapper<"toplevel"=1>(@clk ap_clk: 1, A0_ARESETn: 1, A0_ARREADY: 1, A0_RVALID: 1, A0_RLAST: 1, A0_RDATA: 32, A0_RRESP: 2, A0_AWREADY: 1, A0_WREADY: 1, A0_BVALID: 1, A0_BRESP: 2, A0_RID: 1, B0_ARESETn: 1, B0_ARREADY: 1, B0_RVALID: 1, B0_RLAST: 1, B0_RDATA: 32, B0_RRESP: 2, B0_AWREADY: 1, B0_WREADY: 1, B0_BVALID: 1, B0_BRESP: 2, B0_RID: 1, Sum0_ARESETn: 1, Sum0_ARREADY: 1, Sum0_RVALID: 1, Sum0_RLAST: 1, Sum0_RDATA: 32, Sum0_RRESP: 2, Sum0_AWREADY: 1, Sum0_WREADY: 1, Sum0_BVALID: 1, Sum0_BRESP: 2, Sum0_RID: 1) -> (A0_ARVALID: 1, A0_ARADDR: 64, A0_ARSIZE: 3, A0_ARLEN: 8, A0_ARBURST: 2, A0_RREADY: 1, A0_AWVALID: 1, A0_AWADDR: 64, A0_AWSIZE: 3, A0_AWLEN: 8, A0_AWBURST: 2, A0_AWPROT: 3, A0_WVALID: 1, A0_WLAST: 1, A0_WDATA: 32, A0_BREADY: 1, A0_ARID: 1, A0_AWID: 1, A0_WID: 1, A0_BID: 1, B0_ARVALID: 1, B0_ARADDR: 64, B0_ARSIZE: 3, B0_ARLEN: 8, B0_ARBURST: 2, B0_RREADY: 1, B0_AWVALID: 1, B0_AWADDR: 64, B0_AWSIZE: 3, B0_AWLEN: 8, B0_AWBURST: 2, B0_AWPROT: 3, B0_WVALID: 1, B0_WLAST: 1, B0_WDATA: 32, B0_BREADY: 1, B0_ARID: 1, B0_AWID: 1, B0_WID: 1, B0_BID: 1, Sum0_ARVALID: 1, Sum0_ARADDR: 64, Sum0_ARSIZE: 3, Sum0_ARLEN: 8, Sum0_ARBURST: 2, Sum0_RREADY: 1, Sum0_AWVALID: 1, Sum0_AWADDR: 64, Sum0_AWSIZE: 3, Sum0_AWLEN: 8, Sum0_AWBURST: 2, Sum0_AWPROT: 3, Sum0_WVALID: 1, Sum0_WLAST: 1, Sum0_WDATA: 32, Sum0_BREADY: 1, Sum0_ARID: 1, Sum0_AWID: 1, Sum0_WID: 1, Sum0_BID: 1) {
   cells {
     main_compute = main();
     axi_dyn_mem_A0 = axi_dyn_mem_A0();