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upgrade baa, fst-writer and fraction dependencies (#2382)
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8 files changed

+116
-123
lines changed

8 files changed

+116
-123
lines changed

Cargo.lock

Lines changed: 82 additions & 88 deletions
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Cargo.toml

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -58,6 +58,7 @@ calyx-ir = { path = "calyx-ir", version = "0.7.1" }
5858
calyx-frontend = { path = "calyx-frontend", version = "0.7.1" }
5959
calyx-opt = { path = "calyx-opt", version = "0.7.1" }
6060
calyx-backend = { path = "calyx-backend", version = "0.7.1" }
61+
baa = { version = "0.16.0", features = ["bigint", "serde1", "fraction1"] }
6162

6263
[workspace.dependencies.petgraph]
6364
version = "0.6"

cider-dap/Cargo.toml

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,7 @@ argh = "0.1"
1515
slog = "2.7.0"
1616
slog-term = "2.8.0"
1717
slog-async = "2.7.0"
18-
baa = "0.14"
18+
baa.workspace = true
1919

2020
cider = { path = "../cider" }
2121

cider/Cargo.toml

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -21,10 +21,9 @@ pest_derive.workspace = true
2121
pest_consume.workspace = true
2222
argh.workspace = true
2323
owo-colors = "^3.5"
24-
bitvec = "1.0"
2524
serde_json = "1.0"
2625
rustyline = "=10.0.0"
27-
fraction = { version = "0.11.0", features = ["with-serde-support"] }
26+
fraction = { version = "0.15.3", features = ["with-serde-support"] }
2827
thiserror = "1.0.26"
2928
slog = "2.7.0"
3029
slog-term = "2.8.0"
@@ -33,7 +32,6 @@ ahash = "0.8.3"
3332
num-bigint = "0.4.6"
3433
num-traits = "0.2.19"
3534

36-
once_cell = "1.9.0"
3735
petgraph = "0.6.3"
3836

3937
calyx-ir = { path = "../calyx-ir" }
@@ -42,8 +40,8 @@ calyx-opt = { path = "../calyx-opt" }
4240
calyx-frontend = { path = "../calyx-frontend" }
4341

4442
ciborium = "0.2.2"
45-
baa = { version = "0.14.0", features = ["bigint", "serde1", "fraction1"] }
46-
fst-writer = "0.2.1"
43+
baa.workspace = true
44+
fst-writer = "0.2.3"
4745
bon = "2.3"
4846

4947
[dev-dependencies]

cider/src/flatten/flat_ir/base.rs

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -565,7 +565,7 @@ impl AssignedValue {
565565
/// A utility constructor which returns a new implicitly assigned value with
566566
/// a one bit high value
567567
pub fn implicit_bit_high() -> Self {
568-
Self::new(BitVecValue::tru(), AssignmentWinner::Implicit)
568+
Self::new(BitVecValue::new_true(), AssignmentWinner::Implicit)
569569
}
570570

571571
/// A utility constructor which returns an [`AssignedValue`] with the given
@@ -586,13 +586,13 @@ impl AssignedValue {
586586
/// high value and a [`AssignmentWinner::Cell`] as the winner
587587
#[inline]
588588
pub fn cell_b_high() -> Self {
589-
Self::cell_value(BitVecValue::tru())
589+
Self::cell_value(BitVecValue::new_true())
590590
}
591591
/// A utility constructor which returns an [`AssignedValue`] with a one bit
592592
/// low value and a [`AssignmentWinner::Cell`] as the winner
593593
#[inline]
594594
pub fn cell_b_low() -> Self {
595-
Self::cell_value(BitVecValue::fals())
595+
Self::cell_value(BitVecValue::new_false())
596596
}
597597

598598
pub fn thread(&self) -> Option<ThreadIdx> {

cider/src/flatten/primitives/stateful/math.rs

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -49,9 +49,9 @@ impl<const DEPTH: usize> Primitive for StdMultPipe<DEPTH> {
4949
let done_signal = port_map.insert_val_general(
5050
done,
5151
AssignedValue::cell_value(if self.done_is_high {
52-
BitVecValue::tru()
52+
BitVecValue::new_true()
5353
} else {
54-
BitVecValue::fals()
54+
BitVecValue::new_false()
5555
}),
5656
)?;
5757

@@ -101,9 +101,9 @@ impl<const DEPTH: usize> Primitive for StdMultPipe<DEPTH> {
101101
port_map.insert_val_general(
102102
done,
103103
AssignedValue::cell_value(if self.done_is_high {
104-
BitVecValue::tru()
104+
BitVecValue::new_true()
105105
} else {
106-
BitVecValue::fals()
106+
BitVecValue::new_false()
107107
}),
108108
)?;
109109

@@ -378,9 +378,9 @@ impl<const DEPTH: usize> Primitive for FxpMultPipe<DEPTH> {
378378
let done_signal = port_map.insert_val_general(
379379
done,
380380
AssignedValue::cell_value(if self.done_is_high {
381-
BitVecValue::tru()
381+
BitVecValue::new_true()
382382
} else {
383-
BitVecValue::fals()
383+
BitVecValue::new_false()
384384
}),
385385
)?;
386386

@@ -439,9 +439,9 @@ impl<const DEPTH: usize> Primitive for FxpMultPipe<DEPTH> {
439439
port_map.insert_val_general(
440440
done,
441441
AssignedValue::cell_value(if self.done_is_high {
442-
BitVecValue::tru()
442+
BitVecValue::new_true()
443443
} else {
444-
BitVecValue::fals()
444+
BitVecValue::new_false()
445445
}),
446446
)?;
447447
port_map.write_exact_unchecked(out, self.current_output.clone());

cider/src/flatten/primitives/stateful/memories.rs

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -76,7 +76,7 @@ impl Primitive for StdReg {
7676
BitVecValue::zero(self.internal_state.value.width());
7777
port_map.insert_val_general(
7878
done,
79-
AssignedValue::cell_value(BitVecValue::fals()),
79+
AssignedValue::cell_value(BitVecValue::new_false()),
8080
)?
8181
} else if port_map[write_en].as_bool().unwrap_or_default() {
8282
self.internal_state.value = port_map[input]
@@ -89,13 +89,13 @@ impl Primitive for StdReg {
8989

9090
port_map.insert_val_general(
9191
done,
92-
AssignedValue::cell_value(BitVecValue::tru()),
92+
AssignedValue::cell_value(BitVecValue::new_true()),
9393
)?
9494
} else {
9595
self.done_is_high = false;
9696
port_map.insert_val_general(
9797
done,
98-
AssignedValue::cell_value(BitVecValue::fals()),
98+
AssignedValue::cell_value(BitVecValue::new_false()),
9999
)?
100100
};
101101

@@ -120,9 +120,9 @@ impl Primitive for StdReg {
120120
let done_signal = port_map.insert_val_general(
121121
done,
122122
AssignedValue::cell_value(if self.done_is_high {
123-
BitVecValue::tru()
123+
BitVecValue::new_true()
124124
} else {
125-
BitVecValue::fals()
125+
BitVecValue::new_false()
126126
}),
127127
)?;
128128

@@ -566,9 +566,9 @@ impl Primitive for CombMem {
566566
let done_signal = port_map.insert_val_general(
567567
self.done(),
568568
AssignedValue::cell_value(if self.done_is_high {
569-
BitVecValue::tru()
569+
BitVecValue::new_true()
570570
} else {
571-
BitVecValue::fals()
571+
BitVecValue::new_false()
572572
}),
573573
)?;
574574
Ok(done_signal | read)
@@ -902,9 +902,9 @@ impl Primitive for SeqMem {
902902
let done_signal = port_map.insert_val_general(
903903
self.done(),
904904
AssignedValue::cell_value(if self.done_is_high {
905-
BitVecValue::tru()
905+
BitVecValue::new_true()
906906
} else {
907-
BitVecValue::fals()
907+
BitVecValue::new_false()
908908
}),
909909
)?;
910910

@@ -962,9 +962,9 @@ impl Primitive for SeqMem {
962962
port_map.insert_val_general(
963963
self.done(),
964964
AssignedValue::cell_value(if self.done_is_high {
965-
BitVecValue::tru()
965+
BitVecValue::new_true()
966966
} else {
967-
BitVecValue::fals()
967+
BitVecValue::new_false()
968968
}),
969969
)?;
970970
port_map.write_exact_unchecked(

cider/src/flatten/structures/environment/env.rs

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -151,9 +151,9 @@ impl PortMap {
151151
self.insert_val(
152152
target,
153153
AssignedValue::cell_value(if done_bool {
154-
BitVecValue::tru()
154+
BitVecValue::new_true()
155155
} else {
156-
BitVecValue::fals()
156+
BitVecValue::new_false()
157157
}),
158158
)
159159
.map_err(|e| RuntimeError::ConflictingAssignments(e).into())
@@ -1687,7 +1687,7 @@ impl<C: AsRef<Context> + Clone> BaseSimulator<C> {
16871687
+ self.env.ctx.as_ref().primary[ledger.comp_id]
16881688
.unwrap_standard()
16891689
.go;
1690-
self.env.ports[go] = PortValue::new_implicit(BitVecValue::tru());
1690+
self.env.ports[go] = PortValue::new_implicit(BitVecValue::new_true());
16911691
}
16921692

16931693
// may want to make this iterate directly if it turns out that the vec
@@ -1867,7 +1867,7 @@ impl<C: AsRef<Context> + Clone> BaseSimulator<C> {
18671867

18681868
for (comp, id) in self.env.pc.finished_comps() {
18691869
let done_port = self.env.unwrap_comp_done(*comp);
1870-
let v = PortValue::new_implicit(BitVecValue::tru());
1870+
let v = PortValue::new_implicit(BitVecValue::new_true());
18711871
self.env.ports[done_port] = if self.conf.check_data_race {
18721872
v.with_thread(id.expect("finished comps should have a thread"))
18731873
} else {
@@ -1902,7 +1902,7 @@ impl<C: AsRef<Context> + Clone> BaseSimulator<C> {
19021902
// if the done is not high & defined, we need to set it to low
19031903
if !self.env.ports[comp_done].as_bool().unwrap_or_default() {
19041904
self.env.ports[comp_done] =
1905-
PortValue::new_implicit(BitVecValue::fals());
1905+
PortValue::new_implicit(BitVecValue::new_false());
19061906
}
19071907

19081908
match &ctx_ref.primary[node.control_node_idx] {
@@ -1917,7 +1917,7 @@ impl<C: AsRef<Context> + Clone> BaseSimulator<C> {
19171917
// set go high
19181918
let go_idx = index_bases + go_local;
19191919
self.env.ports[go_idx] =
1920-
PortValue::new_implicit(BitVecValue::tru());
1920+
PortValue::new_implicit(BitVecValue::new_true());
19211921
}
19221922
ControlNode::Invoke(invoke) => {
19231923
if invoke.comb_group.is_some()
@@ -1931,7 +1931,7 @@ impl<C: AsRef<Context> + Clone> BaseSimulator<C> {
19311931

19321932
let go = self.get_global_port_idx(&invoke.go, node.comp);
19331933
self.env.ports[go] =
1934-
PortValue::new_implicit(BitVecValue::tru())
1934+
PortValue::new_implicit(BitVecValue::new_true())
19351935
.with_thread_optional(
19361936
if self.conf.check_data_race {
19371937
assert!(thread.is_some(), "Invoke is running but has no thread. This shouldn't happen. In {}", node.comp.get_full_name(&self.env));

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