Replace blocking assignment in divider implementation

[rachitnigam]

The divider implementation currently uses a bunch of blocking assignments in its core loop. These can sometimes be problematic; I ran into trouble with simulation designs in Icarus verilog with blocking assignments. We should replace them with continuous assignments.

Specifically, here is code:https://github.com/cucapra/calyx/blob/480b08a0348c94507a60416ff217ac373b66be84/primitives/binary_operators.sv#L151-L158

And these are the changes that we need to make:

  logic [16:0] c;
  logic [8:0] right_ext, sub;
  logic check;

  assign right_ext = {1'b0, right};
  assign check = acc >= right_ext;

  // True branch
  assign sub = acc - right;
  assign c = check ? {sub[7:0], quotient, 1'b1} : ({acc, quotient} << 1);

  assign quotient_next = c[7:0];
  assign acc_next = c[16:8];