|
22 | 22 | * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
23 | 23 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
24 | 24 | */ |
| 25 | +#include "board_common.h" |
| 26 | +#include <kendryte/k230_platform.h> |
25 | 27 |
|
26 | 28 | #include <asm/asm.h> |
| 29 | +#include <asm/global_data.h> |
27 | 30 | #include <asm/io.h> |
28 | 31 | #include <asm/spl.h> |
29 | 32 | #include <asm/types.h> |
|
37 | 40 | #include <lmb.h> |
38 | 41 | #include <malloc.h> |
39 | 42 | #include <memalign.h> |
40 | | -#include <stdio.h> |
41 | 43 | #include <u-boot/crc.h> |
42 | | -#include <asm/global_data.h> |
43 | 44 |
|
44 | | -#include <kendryte/k230_platform.h> |
| 45 | +#include <stdio.h> |
45 | 46 |
|
46 | | -#include "board_common.h" |
47 | 47 | DECLARE_GLOBAL_DATA_PTR; |
48 | | -int mmc_get_env_dev(void) { |
49 | | - return (BOOT_MEDIUM_SDIO1 == g_boot_medium) ? 1 : 0; |
50 | | -} |
51 | 48 |
|
52 | | -enum env_location arch_env_get_location(enum env_operation op, int prio) { |
53 | | - if (0 != prio) { |
54 | | - return ENVL_UNKNOWN; |
55 | | - } |
| 49 | +uint64_t g_dram_base = CONFIG_MEM_BASE_ADDR; |
| 50 | +uint64_t g_dram_size = 128 * 1024 * 1024; |
| 51 | + |
| 52 | +int mmc_get_env_dev(void) { return (BOOT_MEDIUM_SDIO1 == g_boot_medium) ? 1 : 0; } |
| 53 | + |
| 54 | +enum env_location arch_env_get_location(enum env_operation op, int prio) |
| 55 | +{ |
| 56 | + if (0 != prio) { |
| 57 | + return ENVL_UNKNOWN; |
| 58 | + } |
56 | 59 |
|
57 | 60 | #ifdef CONFIG_ENV_IS_NOWHERE |
58 | | - return ENVL_NOWHERE; |
| 61 | + return ENVL_NOWHERE; |
59 | 62 | #endif |
60 | 63 |
|
61 | | - if (g_boot_medium == BOOT_MEDIUM_NORFLASH) { |
62 | | - return ENVL_SPI_FLASH; |
63 | | - } |
| 64 | + if (g_boot_medium == BOOT_MEDIUM_NORFLASH) { |
| 65 | + return ENVL_SPI_FLASH; |
| 66 | + } |
64 | 67 |
|
65 | | - if (g_boot_medium == BOOT_MEDIUM_NANDFLASH) { |
66 | | - return ENVL_SPINAND; |
67 | | - } |
| 68 | + if (g_boot_medium == BOOT_MEDIUM_NANDFLASH) { |
| 69 | + return ENVL_SPINAND; |
| 70 | + } |
68 | 71 |
|
69 | | - return ENVL_MMC; |
| 72 | + return ENVL_MMC; |
70 | 73 | } |
71 | 74 |
|
72 | 75 | #ifndef CONFIG_SPL_BUILD |
73 | | -int __weak kd_board_init(void) |
74 | | -{ |
75 | | - return 0; |
76 | | -} |
| 76 | +int __weak kd_board_init(void) { return 0; } |
77 | 77 |
|
78 | | -int board_init(void) { |
79 | | - if ((BOOT_MEDIUM_SDIO0 == g_boot_medium) || |
80 | | - (BOOT_MEDIUM_SDIO1 == g_boot_medium)) { |
| 78 | +int board_init(void) |
| 79 | +{ |
| 80 | + if ((BOOT_MEDIUM_SDIO0 == g_boot_medium) || (BOOT_MEDIUM_SDIO1 == g_boot_medium)) { |
81 | 81 | #define SD_HOST_REG_VOL_STABLE (1 << 4) |
82 | | -#define SD_CARD_WRITE_PROT (1 << 6) |
| 82 | +#define SD_CARD_WRITE_PROT (1 << 6) |
83 | 83 |
|
84 | | - u32 sd0_ctrl = readl((void *)SD0_CTRL); |
85 | | - sd0_ctrl |= SD_HOST_REG_VOL_STABLE | SD_CARD_WRITE_PROT; |
86 | | - writel(sd0_ctrl, (void *)SD0_CTRL); |
87 | | - } |
| 84 | + u32 sd0_ctrl = readl((void*)SD0_CTRL); |
| 85 | + sd0_ctrl |= SD_HOST_REG_VOL_STABLE | SD_CARD_WRITE_PROT; |
| 86 | + writel(sd0_ctrl, (void*)SD0_CTRL); |
| 87 | + } |
88 | 88 |
|
89 | | - return kd_board_init(); |
| 89 | + return kd_board_init(); |
90 | 90 | } |
91 | 91 | #endif |
92 | 92 |
|
93 | | -u32 detect_ddr_size(void) |
| 93 | +uint64_t detect_ddr_size(void) |
94 | 94 | { |
95 | | - u64 ddr_size = 0; |
96 | | - u64 readv0,readv1 = 0; |
97 | | - ulong ddr_detect_pattern[]={0x1234567887654321, 0x1122334455667788}; |
98 | | - |
99 | | - |
100 | | - gd->ram_base = CONFIG_MEM_BASE_ADDR; |
101 | | - gd->ram_size = 0x8000000; |
102 | | - |
103 | | - writeq(ddr_detect_pattern[0], CONFIG_MEM_BASE_ADDR); |
104 | | - writeq(ddr_detect_pattern[0], CONFIG_MEM_BASE_ADDR+8); |
105 | | - flush_dcache_range(CONFIG_MEM_BASE_ADDR, CONFIG_MEM_BASE_ADDR+CONFIG_SYS_CACHELINE_SIZE); |
106 | | - |
107 | | - for(ddr_size = 128*1024*1024; ddr_size <= (u64)(1*1024*1024*1024); ddr_size=ddr_size<<1 ){ |
108 | | - invalidate_dcache_range(ddr_size, ddr_size + CONFIG_SYS_CACHELINE_SIZE); |
109 | | - readv0 = readq(ddr_size); |
110 | | - |
111 | | - if(readv0 == ddr_detect_pattern[0]){//再次确认下 |
112 | | - writeq(ddr_detect_pattern[1], ddr_size+8); |
113 | | - flush_dcache_range(ddr_size, ddr_size+CONFIG_SYS_CACHELINE_SIZE); |
114 | | - invalidate_dcache_range(CONFIG_MEM_BASE_ADDR, CONFIG_MEM_BASE_ADDR + CONFIG_SYS_CACHELINE_SIZE); |
115 | | - |
116 | | - readv1 = readq(CONFIG_MEM_BASE_ADDR+8); |
117 | | - if(readv1 == ddr_detect_pattern[1]){ |
118 | | - //printf("get ddr size=%lx\n", ddr_size); |
119 | | - break; |
120 | | - } |
121 | | - } |
122 | | - //printf("ddr size=%lx %lx,%lx \n", ddr_size,readv0,readv1); |
123 | | - } |
124 | | - gd->ram_size = ddr_size; |
125 | | - //printf("ddr detect error %x\n\n", ddr_size); |
126 | | - return ddr_size; |
| 95 | + uint64_t ddr_size = 0; |
| 96 | + uint64_t readv0, readv1 = 0; |
| 97 | + uint64_t ddr_detect_pattern[] = { 0x1234567887654321, 0x1122334455667788 }; |
| 98 | + |
| 99 | + gd->ram_base = CONFIG_MEM_BASE_ADDR; |
| 100 | + gd->ram_size = 0x8000000; |
| 101 | + |
| 102 | + g_dram_base = CONFIG_MEM_BASE_ADDR; |
| 103 | + g_dram_size = 128 * 1024 * 1024; |
| 104 | + |
| 105 | + writeq(ddr_detect_pattern[0], CONFIG_MEM_BASE_ADDR); |
| 106 | + writeq(ddr_detect_pattern[0], CONFIG_MEM_BASE_ADDR + 8); |
| 107 | + flush_dcache_range(CONFIG_MEM_BASE_ADDR, CONFIG_MEM_BASE_ADDR + CONFIG_SYS_CACHELINE_SIZE); |
| 108 | + |
| 109 | + for (ddr_size = 128 * 1024 * 1024; ddr_size <= (u64)(1 * 1024 * 1024 * 1024); ddr_size = ddr_size << 1) { |
| 110 | + invalidate_dcache_range(ddr_size, ddr_size + CONFIG_SYS_CACHELINE_SIZE); |
| 111 | + readv0 = readq(ddr_size); |
| 112 | + if (readv0 == ddr_detect_pattern[0]) { |
| 113 | + writeq(ddr_detect_pattern[1], ddr_size + 8); |
| 114 | + flush_dcache_range(ddr_size, ddr_size + CONFIG_SYS_CACHELINE_SIZE); |
| 115 | + invalidate_dcache_range(CONFIG_MEM_BASE_ADDR, CONFIG_MEM_BASE_ADDR + CONFIG_SYS_CACHELINE_SIZE); |
| 116 | + readv1 = readq(CONFIG_MEM_BASE_ADDR + 8); |
| 117 | + if (readv1 == ddr_detect_pattern[1]) { |
| 118 | + break; |
| 119 | + } |
| 120 | + } |
| 121 | + } |
| 122 | + |
| 123 | + gd->ram_size = ddr_size; |
| 124 | + g_dram_size = ddr_size; |
| 125 | + |
| 126 | + return ddr_size; |
127 | 127 | } |
128 | 128 |
|
129 | | -#ifdef CONFIG_AUTO_DETECT_DDR_SIZE |
130 | | -int dram_init(void) |
131 | | -{ |
132 | | - detect_ddr_size(); |
133 | | - return 0; |
134 | | -} |
135 | | -#else |
136 | 129 | int dram_init(void) |
137 | 130 | { |
138 | | - return fdtdec_setup_mem_size_base(); |
139 | | -} |
| 131 | + detect_ddr_size(); |
140 | 132 |
|
141 | | -int dram_init_banksize(void) |
142 | | -{ |
143 | | - return fdtdec_setup_memory_banksize(); |
| 133 | + return 0; |
144 | 134 | } |
145 | | -#endif |
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