rs: add TriCore support from capstone 5.0.6

Author: jiegec

capstone-rs/src/arch/mod.rs

@@ -328,6 +328,21 @@ macro_rules! arch_info_base {
                 ( syntax: )
                 ( both_endian: true )
             ]
+            [
+                ( tricore, TriCore )
+                ( mode:
+                    TriCore110,
+                    TriCore120,
+                    TriCore130,
+                    TriCore131,
+                    TriCore160,
+                    TriCore161,
+                    TriCore162,
+                    )
+                ( extra_modes: )
+                ( syntax: )
+                ( both_endian: true )
+            ]
             [
                 ( x86, X86 )
                 ( mode:
@@ -530,6 +545,13 @@ macro_rules! detail_arch_base {
                 /// Returns the Tms320c64x details, if any
                 => arch_name = tms320c64x,
             ]
+            [
+                detail = TriCoreDetail,
+                insn_detail = TriCoreInsnDetail<'a>,
+                op = TriCoreOperand,
+                /// Returns the TriCore details, if any
+                => arch_name = tricore,
+            ]
             [
                 detail = X86Detail,
                 insn_detail = X86InsnDetail<'a>,

capstone-rs/src/arch/tricore.rs

@@ -0,0 +1,91 @@
+//! Contains tricore-specific types
+
+use core::convert::From;
+use core::{cmp, fmt, slice};
+
+pub use capstone_sys::tricore_insn as TriCoreInsn;
+pub use capstone_sys::tricore_insn_group as TriCoreInsnGroup;
+pub use capstone_sys::tricore_reg as TriCoreReg;
+use capstone_sys::{cs_tricore, cs_tricore_op, tricore_op_mem, tricore_op_type};
+
+pub use crate::arch::arch_builder::tricore::*;
+use crate::arch::DetailsArchInsn;
+use crate::instruction::{RegId, RegIdInt};
+
+/// Contains tricore-specific details for an instruction
+pub struct TriCoreInsnDetail<'a>(pub(crate) &'a cs_tricore);
+
+impl_PartialEq_repr_fields!(TriCoreInsnDetail<'a> [ 'a ];
+    operands
+);
+
+/// tricore operand
+#[derive(Clone, Debug, Eq, PartialEq)]
+pub enum TriCoreOperand {
+    /// Register
+    Reg(RegId),
+
+    /// Immediate
+    Imm(i32),
+
+    /// Memory
+    Mem(TriCoreOpMem),
+
+    /// Invalid
+    Invalid,
+}
+
+impl Default for TriCoreOperand {
+    fn default() -> Self {
+        TriCoreOperand::Invalid
+    }
+}
+
+/// tricore memory operand
+#[derive(Debug, Copy, Clone)]
+pub struct TriCoreOpMem(pub(crate) tricore_op_mem);
+
+impl TriCoreOpMem {
+    /// Base register
+    pub fn base(&self) -> RegId {
+        RegId(RegIdInt::from(self.0.base))
+    }
+
+    /// Disp value
+    pub fn disp(&self) -> i32 {
+        self.0.disp
+    }
+}
+
+impl_PartialEq_repr_fields!(TriCoreOpMem;
+    base, disp
+);
+
+impl cmp::Eq for TriCoreOpMem {}
+
+impl From<&cs_tricore_op> for TriCoreOperand {
+    fn from(insn: &cs_tricore_op) -> TriCoreOperand {
+        match insn.type_ {
+            tricore_op_type::TRICORE_OP_REG => {
+                TriCoreOperand::Reg(RegId(unsafe { insn.__bindgen_anon_1.reg } as RegIdInt))
+            }
+            tricore_op_type::TRICORE_OP_IMM => {
+                TriCoreOperand::Imm(unsafe { insn.__bindgen_anon_1.imm })
+            }
+            tricore_op_type::TRICORE_OP_MEM => {
+                TriCoreOperand::Mem(TriCoreOpMem(unsafe { insn.__bindgen_anon_1.mem }))
+            }
+            tricore_op_type::TRICORE_OP_INVALID => TriCoreOperand::Invalid,
+        }
+    }
+}
+
+def_arch_details_struct!(
+    InsnDetail = TriCoreInsnDetail;
+    Operand = TriCoreOperand;
+    OperandIterator = TriCoreOperandIterator;
+    OperandIteratorLife = TriCoreOperandIterator<'a>;
+    [ pub struct TriCoreOperandIterator<'a>(slice::Iter<'a, cs_tricore_op>); ]
+    cs_arch_op = cs_tricore_op;
+    cs_arch = cs_tricore;
+);

capstone-rs/src/constants.rs

@@ -216,6 +216,8 @@ define_cs_enum_wrapper!(
     => M68K = CS_ARCH_M68K;
     /// Texas Instruments TMS320C64x
     => TMS320C64X = CS_ARCH_TMS320C64X;
+    /// TriCore
+    => TriCore = CS_ARCH_TRICORE;
     /// Motorola 68000
     => M680X = CS_ARCH_M680X;
     /// EVM
@@ -293,6 +295,20 @@ define_cs_enum_wrapper!(
     => Cbpf = { cs_mode::CS_MODE_BPF_CLASSIC };
     /// Extended BPF mode
     => Ebpf = { cs_mode::CS_MODE_BPF_EXTENDED };
+    /// TriCore 1.1
+    => TriCore110 = { cs_mode::CS_MODE_TRICORE_110 };
+    /// TriCore 1.2
+    => TriCore120 = { cs_mode::CS_MODE_TRICORE_120 };
+    /// TriCore 1.3
+    => TriCore130 = { cs_mode::CS_MODE_TRICORE_130 };
+    /// TriCore 1.3.1
+    => TriCore131 = { cs_mode::CS_MODE_TRICORE_131 };
+    /// TriCore 1.6
+    => TriCore160 = { cs_mode::CS_MODE_TRICORE_160 };
+    /// TriCore 1.6.1
+    => TriCore161 = { cs_mode::CS_MODE_TRICORE_161 };
+    /// TriCore 1.6.2
+    => TriCore162 = { cs_mode::CS_MODE_TRICORE_162 };
     /// Default mode for little-endian
     => Default = { cs_mode::CS_MODE_LITTLE_ENDIAN };
 );

capstone-rs/src/instruction.rs

@@ -495,6 +495,7 @@ impl InsnDetail<'_> {
             [RISCV, RiscVDetail, RiscVInsnDetail, riscv]
             [SPARC, SparcDetail, SparcInsnDetail, sparc]
             [TMS320C64X, Tms320c64xDetail, Tms320c64xInsnDetail, tms320c64x]
+            [TriCore, TriCoreDetail, TriCoreInsnDetail, tricore]
             [X86, X86Detail, X86InsnDetail, x86]
             [XCORE, XcoreDetail, XcoreInsnDetail, xcore]
             [BPF, BpfDetail, BpfInsnDetail, bpf]

capstone-rs/src/test.rs

@@ -3717,3 +3717,53 @@ fn test_regs_tms320c64x() {
         CsResult::Err(Error::UnsupportedArch),
     );
 }
+
+#[test]
+fn test_arch_tricore() {
+    test_arch_mode_endian_insns(
+        &mut Capstone::new()
+            .tricore()
+            .mode(tricore::ArchMode::TriCore162)
+            .build()
+            .unwrap(),
+        Arch::TriCore,
+        Mode::TriCore162,
+        None,
+        &[],
+        &[("ld.a", b"\x09\xcf\xbc\xf5")],
+    );
+}
+
+#[test]
+fn test_arch_tricore_detail() {
+    use crate::arch::tricore::TriCoreOpMem;
+    use crate::arch::tricore::TriCoreOperand;
+    use capstone_sys::tricore_op_mem;
+    use capstone_sys::tricore_reg::*;
+
+    test_arch_mode_endian_insns_detail(
+        &mut Capstone::new()
+            .tricore()
+            .mode(tricore::ArchMode::TriCore162)
+            .build()
+            .unwrap(),
+        Arch::TriCore,
+        Mode::TriCore162,
+        None,
+        &[],
+        &[
+            // ld.a a15, [+a12]#-4
+            DII::new(
+                "ld.a",
+                b"\x09\xcf\xbc\xf5",
+                &[
+                    TriCoreOperand::Reg(RegId(TRICORE_REG_A15 as RegIdInt)),
+                    TriCoreOperand::Mem(TriCoreOpMem(tricore_op_mem {
+                        base: TRICORE_REG_A12 as u8,
+                        disp: -4,
+                    })),
+                ],
+            ),
+        ],
+    );
+}

capstone-sys/build.rs

@@ -130,6 +130,7 @@ fn build_capstone_cc() {
         .define("CAPSTONE_HAS_SPARC", None)
         .define("CAPSTONE_HAS_SYSZ", None)
         .define("CAPSTONE_HAS_TMS320C64X", None)
+        .define("CAPSTONE_HAS_TRICORE", None)
         .define("CAPSTONE_HAS_WASM", None)
         .define("CAPSTONE_HAS_X86", None)
         .define("CAPSTONE_HAS_XCORE", None)

capstone-sys/common.rs

@@ -69,6 +69,10 @@ pub static ARCH_INCLUDES: &[CapstoneArchInfo<'static>] = &[
         header_name: "tms320c64x.h",
         cs_name: "tms320c64x",
     },
+    CapstoneArchInfo {
+        header_name: "tricore.h",
+        cs_name: "tricore",
+    },
     CapstoneArchInfo {
         header_name: "x86.h",
         cs_name: "x86",