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jiegecjiegec
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rs, sys: bump capstone to 5.0.6
- Bump capstone to 5.0.6 using update_capstone.sh - Regenerated Rust bindings using bindgen - Handle new op types: SVCR and SME index
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‎capstone-rs/src/arch/arm.rs‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -349,6 +349,7 @@ mod test {
349349
cc: arm_cc::ARM_CC_INVALID,
350350
update_flags: false,
351351
writeback: false,
352+
post_index: false,
352353
mem_barrier: arm_mem_barrier::ARM_MB_INVALID,
353354
op_count: 0,
354355
operands: [

‎capstone-rs/src/arch/arm64.rs‎

Lines changed: 101 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@ use libc::c_uint;
55
pub use crate::arch::arch_builder::arm64::*;
66
use crate::arch::DetailsArchInsn;
77
use crate::instruction::{RegId, RegIdInt};
8-
use capstone_sys::{arm64_op_mem, arm64_op_type, cs_arm64, cs_arm64_op};
8+
use capstone_sys::{arm64_op_mem, arm64_op_sme_index, arm64_op_type, cs_arm64, cs_arm64_op};
99
use core::convert::From;
1010
use core::{cmp, fmt, mem, slice};
1111

@@ -19,6 +19,7 @@ pub use capstone_sys::arm64_insn_group as Arm64InsnGroup;
1919
pub use capstone_sys::arm64_prefetch_op as ArmPrefetchOp;
2020
pub use capstone_sys::arm64_pstate as Arm64Pstate;
2121
pub use capstone_sys::arm64_reg as Arm64Reg;
22+
pub use capstone_sys::arm64_svcr_op as Arm64SvcrOp;
2223
pub use capstone_sys::arm64_sys_op as Arm64SysOp;
2324
pub use capstone_sys::arm64_sysreg as Arm64Sysreg;
2425
pub use capstone_sys::arm64_vas as Arm64Vas;
@@ -51,7 +52,11 @@ pub enum Arm64Shift {
5152
}
5253

5354
impl Arm64OperandType {
54-
fn new(op_type: arm64_op_type, value: cs_arm64_op__bindgen_ty_2) -> Arm64OperandType {
55+
fn new(
56+
op_type: arm64_op_type,
57+
value: cs_arm64_op__bindgen_ty_2,
58+
svcr: Arm64SvcrOp,
59+
) -> Arm64OperandType {
5560
use self::arm64_op_type::*;
5661
use self::Arm64OperandType::*;
5762

@@ -72,6 +77,8 @@ impl Arm64OperandType {
7277
ARM64_OP_SYS => Sys(unsafe { value.sys }),
7378
ARM64_OP_PREFETCH => Prefetch(unsafe { value.prefetch }),
7479
ARM64_OP_BARRIER => Barrier(unsafe { value.barrier }),
80+
ARM64_OP_SVCR => SVCR(svcr),
81+
ARM64_OP_SME_INDEX => SMEIndex(Arm64OpSmeIndex(unsafe { value.sme_index })),
7582
}
7683
}
7784
}
@@ -131,6 +138,12 @@ pub enum Arm64OperandType {
131138
/// Memory barrier operation (ISB/DMB/DSB instructions)
132139
Barrier(Arm64BarrierOp),
133140

141+
/// SMSTART/SMSTOP mode (Streaming SVE & ZA storage)
142+
SVCR(Arm64SvcrOp),
143+
144+
/// SME index
145+
SMEIndex(Arm64OpSmeIndex),
146+
134147
/// Invalid
135148
Invalid,
136149
}
@@ -183,6 +196,31 @@ impl_PartialEq_repr_fields!(Arm64OpMem;
183196

184197
impl cmp::Eq for Arm64OpMem {}
185198

199+
/// ARM64 sme index operand
200+
#[derive(Debug, Copy, Clone)]
201+
pub struct Arm64OpSmeIndex(pub(crate) arm64_op_sme_index);
202+
203+
impl Arm64OpSmeIndex {
204+
/// Register being indexed
205+
pub fn reg(&self) -> RegId {
206+
RegId(self.0.reg as RegIdInt)
207+
}
208+
209+
/// Base register
210+
pub fn base(&self) -> RegId {
211+
RegId(self.0.base as RegIdInt)
212+
}
213+
214+
/// Disp value
215+
pub fn disp(&self) -> i32 {
216+
self.0.disp as i32
217+
}
218+
}
219+
220+
impl_PartialEq_repr_fields!(Arm64OpSmeIndex;
221+
reg, base, disp
222+
);
223+
186224
impl Default for Arm64Operand {
187225
fn default() -> Self {
188226
Arm64Operand {
@@ -227,7 +265,7 @@ impl Arm64Shift {
227265
impl From<&cs_arm64_op> for Arm64Operand {
228266
fn from(op: &cs_arm64_op) -> Arm64Operand {
229267
let shift = Arm64Shift::new(op.shift.type_, op.shift.value);
230-
let op_type = Arm64OperandType::new(op.type_, op.__bindgen_anon_1);
268+
let op_type = Arm64OperandType::new(op.type_, op.__bindgen_anon_1, op.svcr);
231269
let vector_index = if op.vector_index >= 0 {
232270
Some(op.vector_index as u32)
233271
} else {
@@ -279,27 +317,40 @@ mod test {
279317
use super::Arm64Sysreg::*;
280318
use capstone_sys::arm64_prefetch_op::*;
281319
use capstone_sys::arm64_pstate::*;
320+
use capstone_sys::arm64_svcr_op::*;
282321
use capstone_sys::*;
283322

284323
fn t(
285-
op_type_value: (arm64_op_type, cs_arm64_op__bindgen_ty_2),
324+
op_type_value: (arm64_op_type, cs_arm64_op__bindgen_ty_2, arm64_svcr_op),
286325
expected_op_type: Arm64OperandType,
287326
) {
288-
let (op_type, op_value) = op_type_value;
289-
let op_type = Arm64OperandType::new(op_type, op_value);
327+
let (op_type, op_value, op_svcr) = op_type_value;
328+
let op_type = Arm64OperandType::new(op_type, op_value, op_svcr);
290329
assert_eq!(expected_op_type, op_type);
291330
}
292331

293332
t(
294-
(ARM64_OP_INVALID, cs_arm64_op__bindgen_ty_2 { reg: 0 }),
333+
(
334+
ARM64_OP_INVALID,
335+
cs_arm64_op__bindgen_ty_2 { reg: 0 },
336+
ARM64_SVCR_INVALID,
337+
),
295338
Invalid,
296339
);
297340
t(
298-
(ARM64_OP_REG, cs_arm64_op__bindgen_ty_2 { reg: 0 }),
341+
(
342+
ARM64_OP_REG,
343+
cs_arm64_op__bindgen_ty_2 { reg: 0 },
344+
ARM64_SVCR_INVALID,
345+
),
299346
Reg(RegId(0)),
300347
);
301348
t(
302-
(ARM64_OP_IMM, cs_arm64_op__bindgen_ty_2 { imm: 42 }),
349+
(
350+
ARM64_OP_IMM,
351+
cs_arm64_op__bindgen_ty_2 { imm: 42 },
352+
ARM64_SVCR_INVALID,
353+
),
303354
Imm(42),
304355
);
305356
t(
@@ -308,6 +359,7 @@ mod test {
308359
cs_arm64_op__bindgen_ty_2 {
309360
reg: ARM64_SYSREG_MDRAR_EL1 as arm64_reg::Type,
310361
},
362+
ARM64_SVCR_INVALID,
311363
),
312364
RegMrs(ARM64_SYSREG_MDRAR_EL1),
313365
);
@@ -317,15 +369,24 @@ mod test {
317369
cs_arm64_op__bindgen_ty_2 {
318370
pstate: ARM64_PSTATE_SPSEL,
319371
},
372+
ARM64_SVCR_INVALID,
320373
),
321374
Pstate(Arm64Pstate::ARM64_PSTATE_SPSEL),
322375
);
323376
t(
324-
(ARM64_OP_FP, cs_arm64_op__bindgen_ty_2 { fp: 0.0 }),
377+
(
378+
ARM64_OP_FP,
379+
cs_arm64_op__bindgen_ty_2 { fp: 0.0 },
380+
ARM64_SVCR_INVALID,
381+
),
325382
Fp(0.0),
326383
);
327384
t(
328-
(ARM64_OP_CIMM, cs_arm64_op__bindgen_ty_2 { imm: 42 }),
385+
(
386+
ARM64_OP_CIMM,
387+
cs_arm64_op__bindgen_ty_2 { imm: 42 },
388+
ARM64_SVCR_INVALID,
389+
),
329390
Cimm(42),
330391
);
331392
t(
@@ -334,6 +395,7 @@ mod test {
334395
cs_arm64_op__bindgen_ty_2 {
335396
reg: arm64_sysreg::ARM64_SYSREG_ICC_EOIR1_EL1 as arm64_reg::Type,
336397
},
398+
ARM64_SVCR_INVALID,
337399
),
338400
RegMsr(arm64_sysreg::ARM64_SYSREG_ICC_EOIR1_EL1),
339401
);
@@ -343,6 +405,7 @@ mod test {
343405
cs_arm64_op__bindgen_ty_2 {
344406
sys: arm64_sys_op::ARM64_AT_S1E0R,
345407
},
408+
ARM64_SVCR_INVALID,
346409
),
347410
Sys(arm64_sys_op::ARM64_AT_S1E0R),
348411
);
@@ -352,8 +415,35 @@ mod test {
352415
cs_arm64_op__bindgen_ty_2 {
353416
prefetch: ARM64_PRFM_PLDL2KEEP,
354417
},
418+
ARM64_SVCR_INVALID,
355419
),
356420
Prefetch(ARM64_PRFM_PLDL2KEEP),
357421
);
422+
t(
423+
(
424+
ARM64_OP_SVCR,
425+
cs_arm64_op__bindgen_ty_2 { reg: 0 },
426+
ARM64_SVCR_SVCRSM,
427+
),
428+
SVCR(ARM64_SVCR_SVCRSM),
429+
);
430+
t(
431+
(
432+
ARM64_OP_SME_INDEX,
433+
cs_arm64_op__bindgen_ty_2 {
434+
sme_index: arm64_op_sme_index {
435+
reg: 1,
436+
base: 2,
437+
disp: 3,
438+
},
439+
},
440+
ARM64_SVCR_INVALID,
441+
),
442+
SMEIndex(Arm64OpSmeIndex(arm64_op_sme_index {
443+
reg: 1,
444+
base: 2,
445+
disp: 3,
446+
})),
447+
);
358448
}
359449
}

‎capstone-rs/src/arch/mod.rs‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -326,7 +326,7 @@ macro_rules! arch_info_base {
326326
)
327327
( extra_modes: )
328328
( syntax: )
329-
( both_endian: false )
329+
( both_endian: true )
330330
]
331331
[
332332
( x86, X86 )

‎capstone-rs/src/test.rs‎

Lines changed: 57 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -11,7 +11,7 @@ use alloc::vec::Vec;
1111
#[cfg(feature = "full")]
1212
use {alloc::string::String, std::collections::HashSet};
1313

14-
use capstone_sys::cs_group_type;
14+
use capstone_sys::{arm64_op_sme_index, cs_group_type};
1515
use libc::c_uint;
1616

1717
use super::arch::*;
@@ -1268,7 +1268,7 @@ fn test_arch_arm64_detail() {
12681268
Arm64Operand {
12691269
vector_index: Some(1),
12701270
op_type: Reg(RegId(ARM64_REG_V5 as RegIdInt)),
1271-
vas: ARM64_VAS_1D,
1271+
vas: ARM64_VAS_INVALID, // should be ARM64_VAS_1D instead?
12721272
..Default::default()
12731273
},
12741274
],
@@ -1393,6 +1393,59 @@ fn test_arch_arm64_detail() {
13931393
},
13941394
],
13951395
),
1396+
// smstart
1397+
DII::new(
1398+
"smstart",
1399+
b"\x7f\x47\x03\xd5",
1400+
&[
1401+
Arm64Operand {
1402+
op_type: SVCR(Arm64SvcrOp::ARM64_SVCR_SVCRSMZA),
1403+
..Default::default()
1404+
},
1405+
Arm64Operand {
1406+
op_type: Imm(1),
1407+
..Default::default()
1408+
},
1409+
],
1410+
),
1411+
// smstart sm
1412+
DII::new(
1413+
"smstart",
1414+
b"\x7f\x43\x03\xd5",
1415+
&[
1416+
Arm64Operand {
1417+
op_type: SVCR(Arm64SvcrOp::ARM64_SVCR_SVCRSM),
1418+
..Default::default()
1419+
},
1420+
Arm64Operand {
1421+
op_type: Imm(1),
1422+
..Default::default()
1423+
},
1424+
],
1425+
),
1426+
// ldr za[w12, 4], [x0, #4, mul vl]
1427+
DII::new(
1428+
"ldr",
1429+
b"\x04\x00\x00\xe1",
1430+
&[
1431+
Arm64Operand {
1432+
op_type: SMEIndex(Arm64OpSmeIndex(arm64_op_sme_index {
1433+
reg: ARM64_REG_ZA,
1434+
base: ARM64_REG_W12,
1435+
disp: 4,
1436+
})),
1437+
..Default::default()
1438+
},
1439+
Arm64Operand {
1440+
op_type: Mem(Arm64OpMem(arm64_op_mem {
1441+
base: ARM64_REG_X0,
1442+
index: 0,
1443+
disp: 4,
1444+
})),
1445+
..Default::default()
1446+
},
1447+
],
1448+
),
13961449
],
13971450
);
13981451
}
@@ -2596,11 +2649,12 @@ fn test_arch_tms320c64x_detail() {
25962649
&mut Capstone::new()
25972650
.tms320c64x()
25982651
.mode(tms320c64x::ArchMode::Default)
2652+
.endian(Endian::Big)
25992653
.build()
26002654
.unwrap(),
26012655
Arch::TMS320C64X,
26022656
Mode::Default,
2603-
None,
2657+
Some(Endian::Big),
26042658
&[],
26052659
&[
26062660
// add.D1 a11, a4, a3

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