rs: minor fix-ups regs_access; add tests

Author: tmfink

capstone-rs/src/capstone.rs

@@ -14,7 +14,7 @@ use crate::instruction::{Insn, InsnDetail, InsnGroupId, InsnId, Instructions, Re
 
 use {crate::ffi::str_from_cstr_ptr, alloc::string::ToString, libc::c_uint};
 
-/// This is taken from the [python bindings](https://github.com/capstone-engine/capstone/blob/5fb8a423d4455cade99b12912142fd3a0c10d957/bindings/python/capstone/__init__.py#L929)
+/// taken from the [python bindings](https://github.com/capstone-engine/capstone/blob/5fb8a423d4455cade99b12912142fd3a0c10d957/bindings/python/capstone/__init__.py#L929)
 const MAX_NUM_REGISTERS: usize = 64;
 
 /// An instance of the capstone disassembler
@@ -103,11 +103,20 @@ impl Iterator for EmptyExtraModeIter {
     }
 }
 
+#[derive(Clone, Debug, PartialEq, Eq, Hash)]
 pub struct RegAccess {
     pub read: Vec<RegId>,
     pub write: Vec<RegId>,
 }
 
+impl RegAccess {
+    /// Sort read and write fields
+    pub fn sort(&mut self) {
+        self.read.sort_unstable();
+        self.write.sort_unstable();
+    }
+}
+
 impl Capstone {
     /// Create a new instance of the decompiler using the builder pattern interface.
     /// This is the recommended interface to `Capstone`.
@@ -373,19 +382,20 @@ impl Capstone {
         }
     }
 
-    /// Get the registers are which are read to and written to
-    pub fn regs_access_buf(&self, insn: &Insn) -> CsResult<RegAccess> {
+    // todo(tmfink): integrate into regs_read()/regs_write() methods to avoid the need to call
+    /// Get the registers which are read and written
+    pub fn regs_access(&self, insn: &Insn) -> CsResult<RegAccess> {
         let mut read = Vec::new();
         let mut write = Vec::new();
 
-        self.regs_access(insn, &mut read, &mut write)?;
+        self.regs_access_buf(insn, &mut read, &mut write)?;
 
         Ok(RegAccess { read, write })
     }
 
-    /// Get the registers are which are read to and written to\
-    /// the registers are pushed to the back of the provided buffers
-    pub fn regs_access(
+    /// Get the registers are which are read and written.
+    /// The registers are pushed to the back of the provided buffers
+    pub(crate) fn regs_access_buf(
         &self,
         insn: &Insn,
         read: &mut Vec<RegId>,

capstone-rs/src/test.rs

@@ -3510,3 +3510,97 @@ fn test_arch_bpf_detail() {
         ],
     );
 }
+
+#[cfg(feature = "full")]
+fn assert_regs_access_matches(
+    cs: &mut Capstone,
+    bytes: &[u8],
+    expected_regs_access: CsResult<&[RegAccess]>,
+) {
+    let expected_regs_access = expected_regs_access.clone().map(|accesses: &[RegAccess]| {
+        accesses
+            .iter()
+            .map(|regs| {
+                let mut regs = regs.clone();
+                regs.sort();
+                regs
+            })
+            .collect::<Vec<RegAccess>>()
+    });
+    let insns = cs.disasm_all(bytes, 0x1000).unwrap();
+    let reg_access: CsResult<Vec<RegAccess>> = insns
+        .iter()
+        .map(|insn| {
+            cs.regs_access(insn).map(|mut regs| {
+                regs.sort();
+                regs
+            })
+        })
+        .collect();
+    let reg_access = reg_access.as_ref().map(|access| access.as_slice());
+    assert_eq!(reg_access, expected_regs_access.as_deref());
+}
+
+fn as_reg_access<T: TryInto<RegIdInt> + Copy + Debug>(read: &[T], write: &[T]) -> RegAccess {
+    let as_reg_access = |input: &[T]| -> Vec<RegId> {
+        input
+            .iter()
+            .copied()
+            .map(|reg| {
+                RegId(
+                    reg.try_into()
+                        .unwrap_or_else(|_| panic!("Failed to create RegInt")),
+                )
+            })
+            .collect()
+    };
+    RegAccess {
+        read: as_reg_access(read),
+        write: as_reg_access(write),
+    }
+}
+
+#[cfg(feature = "full")]
+fn test_regs_access(mut cs: Capstone, code: &[u8], expected_regs_access: CsResult<&[RegAccess]>) {
+    // should always fail when not in debug mode
+    assert_regs_access_matches(&mut cs, code, CsResult::Err(Error::DetailOff));
+
+    // now detail is enabled, check for expected outcome
+    cs.set_detail(true).expect("failed to set detail");
+    assert_regs_access_matches(&mut cs, code, expected_regs_access);
+}
+
+#[cfg(feature = "full")]
+#[test]
+fn test_regs_access_arm() {
+    use crate::arch::arm::ArmReg::*;
+
+    test_regs_access(
+        Capstone::new()
+            .arm()
+            .mode(arm::ArchMode::Thumb)
+            .build()
+            .unwrap(),
+        b"\xf0\xbd",
+        CsResult::Ok(&[as_reg_access(
+            &[ARM_REG_SP],
+            &[
+                ARM_REG_SP, ARM_REG_R4, ARM_REG_R5, ARM_REG_R6, ARM_REG_R7, ARM_REG_PC,
+            ],
+        )]),
+    );
+}
+
+#[cfg(feature = "full")]
+#[test]
+fn test_regs_tms320c64x() {
+    test_regs_access(
+        Capstone::new()
+            .tms320c64x()
+            .mode(tms320c64x::ArchMode::Default)
+            .build()
+            .unwrap(),
+        b"\x01\xac\x88\x40",
+        CsResult::Err(Error::UnsupportedArch),
+    );
+}