[Bug] Vivado syntax error on vhdl generated by xml2vhdl for deferred const init

[carobers]

The following is my test design.

This is Vivado 2021.1 running on Ubuntu 20.04 in a virtual machine.
mlib_devel commit casper-astro/mlib_devel@883e094

Vivado exits synthesis due to syntax errors.

ERROR: [Synth 8-2772] type t_axi4lite_mmap_addr_arr does not match with a string literal 
[xml2vhdl_hdl_output/axi4lite_axi4lite_top_mmap_pkg.vhd:95] 
ERROR: [Synth 8-2772] type t_axi4lite_mmap_addr_arr does not match with a string literal [xml2vhdl_hdl_output/axi4lite_axi4lite_top_mmap_pkg.vhd:94] 

For xml2vhdl commit 180f5fd

It seems that it's unhappy with the following vhdl code:

constant c_axi4lite_mmap_baddr: t_axi4lite_mmap_addr_arr := (X"00000000");
constant c_axi4lite_mmap_mask: t_axi4lite_mmap_addr_arr := (X"00000000");

when the array length of type t_axi4lite_mmap_addr_arr is one.

---

I solved this issue by modifying xml2ic to generate an explicit array mapping such that it's now the following:

constant c_axi4lite_mmap_baddr: t_axi4lite_mmap_addr_arr := (
        0 => X"00000000");
constant c_axi4lite_mmap_mask: t_axi4lite_mmap_addr_arr := (
        0 => X"00000000");

Following the RFSOC-Casper tutorial here, multiple software registers were added. The following code was generated:

constant c_axi4lite_mmap_baddr: t_axi4lite_mmap_addr_arr := (
        0 => X"00000000",
        1 => X"00000020");
constant c_axi4lite_mmap_mask: t_axi4lite_mmap_addr_arr := (
        0 => X"00000020",
        1 => X"00000020");

These modifications worked in terms of generating a bitstream and an FPG file.

The new code can be found here:

https://github.com/asu-rdl/xml2vhdl/blob/2548874261ba725f638630e1c3b0bb1b77170bd5/scripts/python/xml2vhdl-ox/xml2vhdl/xml2ic.py#L712

Thoughts?