Updated README

Author: ccattuto

README.md

@@ -1,20 +1,18 @@
 # 🐍 RISC-V Emulator in Python (RV32IMAC, machine mode, Newlib support)
 
-This is a simple and readable **RISC-V RV32IMAC emulator** written in pure Python. It supports machine mode, atomic instructions (A extension), compressed instructions (RVC extension), multiply/divide instructions (M extension), and can run programs compiled with **Newlib** or **Newlib-nano**. It is designed for educational use, experimentation, and portability — not for high performance or full system emulation.
+This is a simple and readable **RISC-V RV32IMAC emulator** written in pure Python. It supports machine mode, multiply/divide instructions (M extension), atomic instructions (A extension), compressed instructions (C extension), and can run programs compiled with **Newlib** or **Newlib-nano**. It is designed for educational use, experimentation, and portability — not for high performance or full system emulation.
 
 ## ✅ Features
 
-- **Implements the full RV32I base integer ISA**
-- **Implements the M extension** with multiply (`MUL`, `MULH`, `MULHSU`, `MULHU`) and divide (`DIV`, `DIVU`, `REM`, `REMU`) instructions
-- **Implements the A extension** with all 11 atomic memory operations (`LR.W`, `SC.W`, `AMOSWAP.W`, `AMOADD.W`, `AMOXOR.W`, `AMOAND.W`, `AMOOR.W`, `AMOMIN.W`, `AMOMAX.W`, `AMOMINU.W`, `AMOMAXU.W`) and proper LR/SC reservation tracking
-- **Implements the RVC (Compressed) extension** with full support for 16-bit compressed instructions, achieving 25-30% code density improvement
+- **Implements the full RV32I base integer ISA** with the **M extension** (multiply and divide instructions) and the **A extension** (atomic memory operations)
+- **Implements the C extension** (compressed instructions), switchable at run time
 - **Implements all RV32MI machine-mode instructions and trap mechanisms**, including synchronous traps (`ecall`, `ebreak`, illegal instruction trap), asynchronous traps (machine timer interrupt), `mret`, and the **Zicsr (Control Status Registers) extension** and registers (`mstatus`, `mepc`, `mtvec`, `mcause`, `mscratch`, ...)
 - **Supports loading ELF and flat binary formats**
 - **Supports terminal I/O**, both "cooked" and raw
 - **Provides most of the system calls needed by [Newlib](https://en.wikipedia.org/wiki/Newlib)**: `_write`, `_read`, `_exit`, **dynamic memory allocation** (`_sbrk`), **file I/O** (`_open`, `_close`, `_fstat`, `_lseek`, ...)
 - **Supports argc/argv program arguments**
 - **Supports memory-mapped IO** and provides a **UART peripheral** using a pseudo-terminal, and a **memory-mapped block device** backed by an image file
-- **Passes all `rv32ui`, `rv32mi`, `rv32uc`, `rv32um`, and `rv32ua` unit tests** (60 tests total) provided by [RISC-V International](https://github.com/riscv-software-src/riscv-tests)
+- **Passes all `rv32ui`, `rv32mi`, `rv32um`, `rv32ua`, and `rv32uc` unit tests** provided by [RISC-V International](https://github.com/riscv-software-src/riscv-tests)
 - **Supports logging** of register values, function calls, system calls, traps, invalid memory accesses, and violations of invariants
 - Runs [MicroPython](https://micropython.org/), [CircuitPython](https://circuitpython.org/) with emulated peripherals, and [FreeRTOS](https://www.freertos.org/) with preemptive multitasking
 - Self-contained, modular, extensible codebase. Provides a **Python API** enabling users to control execution, inspect state, and script complex tests directly in Python.
@@ -34,6 +32,7 @@ pip install -r requirements.txt
 ```
 ├── riscv-emu.py               # Emulator
 ├── cpu.py                     # CPU emulation logic
+├── rvc.py                     # RVC logic
 ├── ram.py                     # RAM emulation logic
 ├── machine.py                 # Host logic (executable loading, invariants check)
 ├── peripherals.py             # Peripherals (UART, block device)
@@ -53,7 +52,7 @@ pip install -r requirements.txt
 ├── tests/test_api*.py         # Examples of programmatic control of the emulator in Python
 ├── build/                     # Executable and binaries
 ├── prebuilt/                  # Pre-built examples
-├── run_unit_tests.py          # Runs RISC-V unit tests (RV32UI, RV32MI, RV32UC, RV32UM, and RV32UA)
+├── run_unit_tests.py          # Runs RISC-V unit tests (RV32UI, RV32MI, RV32UM, RV32UA, and RV32UC)
 ├── riscv-tests/               # Git submodule with RISC-V unit tests
 ├── advanced/freertos/         # FreeRTOS port
 ├── advanced/micropython/      # MicroPython port
@@ -70,6 +69,7 @@ pip install -r requirements.txt
 
 | Option                  | Description                                                                 |
 |-------------------------|-----------------------------------------------------------------------------|
+| `--rvc`                 | Enable RVC support (compressed instructions)                                |
 | `--regs REGS`           | Print selected registers at each instruction                                |
 | `--trace`               | Log the names of functions traversed during execution                       |
 | `--syscalls`            | Log Newlib syscalls                                                         |
@@ -86,7 +86,6 @@ pip install -r requirements.txt
 | `--uart`                | Enable PTY UART                                                             |
 | `--blkdev PATH`         | Enable MMIO block device                                                    |
 | `--blkdev-size NUM`     | Block device size in 512-byte blocks (default 1024)                         |
-| `--rvc`                 | Enable RVC (compressed instructions) support for 16-bit instructions        |
 | `--raw-tty`             | Enable raw terminal mode                                                    |
 | `--no-color`            | Remove ANSI colors in debugging output                                      |
 | `--log LOG_FILE`        | Log debug information to file `LOG_FILE`                                    |
@@ -99,7 +98,7 @@ make all
 
 The Makefile supports building with different RISC-V extensions, e.g., to build with rv32iac_zicsr (RV32IMAC):
 ```
-make RVC=1 MUL=1 RVA=1 all
+make RVM=1 RVA=1 RVC=1 all
 ```
 
 If you just want to **test the emulator without installing a RISC-V compiler**, you will find pre-built binaries in `prebuilt/`.
@@ -207,7 +206,7 @@ and connect to the console using your favorite terminal program, e.g., `screen /
 
 ### Using the Python API
 
-The emulator provides a Python API that allows users to control execution, set and inspect state, and run complex tests directly from Python programs. Here is an example of how you can load and run a simple program:
+The emulator provides a Python API that allows users to control execution, set and inspect state, and run complex tests directly from Python programs. Here is an example of how you can load and run a simple RV32I program:
 ```python
 from cpu import CPU
 from ram import RAM
@@ -250,7 +249,7 @@ make
 cd -
 ```
 
-The script automatically runs all RV32UI, RV32MI, RV32UC, and RV32UM [RISC-V unit tests](https://github.com/riscv-software-src/riscv-tests) in `riscv-tests/`. The emulator passes all of them.
+The script automatically runs all RV32UI, RV32MI, RV32UM, RV32UA, and RV32UC [RISC-V unit tests](https://github.com/riscv-software-src/riscv-tests) in `riscv-tests/`. The emulator passes all of them.
 ```
 ./run_unit_tests.py
 Test rv32ui-p-bltu                 : PASS
@@ -354,27 +353,19 @@ Test rv32uc-p-rvc                  : PASS
 The emulator achieves **over 2 MIPS** (million instructions per second) using Python 3.12 (Anaconda distribution) on a Macbook Pro (M1, 2020) running macOS Sequoia. Execution times for some binaries in `prebuilt/`:
 ```
 time ./riscv-emu.py prebuilt/test_newlib2.elf
-./riscv-emu.py prebuilt/test_newlib2.elf  11.43s user 0.05s system 99% cpu 11.506 total
+./riscv-emu.py prebuilt/test_newlib2.elf  1.71s user 0.03s system 98% cpu 1.772 total
 ```
 ```
 time ./riscv-emu.py prebuilt/test_newlib4.elf
-./riscv-emu.py prebuilt/test_newlib4.elf  4.90s user 0.03s system 99% cpu 4.973 total
+./riscv-emu.py prebuilt/test_newlib4.elf  0.37s user 0.03s system 94% cpu 0.416 total
 ```
 ```
 time ./riscv-emu.py prebuilt/test_newlib6.elf
-./riscv-emu.py prebuilt/test_newlib6.elf  75.85s user 0.24s system 99% cpu 1:16.37 total
+./riscv-emu.py prebuilt/test_newlib6.elf  76.19s user 0.29s system 99% cpu 1:16.56 total
 ```
 
 Running the emulator with [PyPy](https://pypy.org/) yields a speedup of almost 4x over CPython, achieving **over 9 MIPS**.
 ```
-time pypy3 ./riscv-emu.py prebuilt/test_newlib2.elf
-pypy3 ./riscv-emu.py prebuilt/test_newlib2.elf  2.76s user 0.06s system 97% cpu 2.891 total
-```
-```
-time pypy3 ./riscv-emu.py prebuilt/test_newlib4.elf
-pypy3 ./riscv-emu.py prebuilt/test_newlib4.elf  1.24s user 0.03s system 99% cpu 1.276 total
-```
-```
 time pypy3 ./riscv-emu.py prebuilt/test_newlib6.elf
-pypy3 ./riscv-emu.py prebuilt/test_newlib6.elf  19.82s user 0.15s system 99% cpu 20.046 total
+pypy3 ./riscv-emu.py prebuilt/test_newlib6.elf  19.77s user 0.11s system 99% cpu 20.009 total
 ```