Replaced direct all to __sinit() with call to __libc_init_array() in startup_*.S , for all projects. Use t0,t1 regs instead of a0,a1. Updated binaries.

Author: ccattuto

advanced/circuitpython/riscv-emu.py/Makefile

@@ -85,7 +85,7 @@ $(BUILD)/%.o: %.S
 
 SRC_QSTR += $(SRC_C) $(SRC_SUPERVISOR) $(SRC_COMMON_HAL_EXPANDED) $(SRC_SHARED_MODULE_EXPANDED) $(SRC_CIRCUITPY_COMMON)
 
-all: $(BUILD)/firmware.elf $(BUILD)/circuitpy.img
+all: $(BUILD)/firmware.elf $(BUILD)/firmware.bin $(BUILD)/circuitpy.img
 
 BOARD_LD := $(wildcard boards/$(BOARD)/link.ld)
 

advanced/circuitpython/riscv-emu.py/link.ld

@@ -7,6 +7,8 @@ MEMORY
 
 SECTIONS
 {
+  . = 0x00000000;
+
   .text : ALIGN(4)
   {
     KEEP(*(.init))

advanced/circuitpython/riscv-emu.py/start.S

@@ -1,4 +1,4 @@
-    .section .text
+    .section .init
     .globl _start
 
 _start:
@@ -13,25 +13,23 @@ _start:
     mv s1, a1
 
     # initialize .bss
-    la   a0, __bss_start
-    la   a1, __bss_end
+    la   t0, __bss_start
+    la   t1, __bss_end
 z_bss:
-    sw   zero, 0(a0)
-    addi a0, a0, 4
-    blt  a0, a1, z_bss
+    sw   zero, 0(t0)
+    addi t0, t0, 4
+    blt  t0, t1, z_bss
 
     # initialize .sbss
-    la   a0, __sbss_start
-    la   a1, __sbss_end
+    la   t0, __sbss_start
+    la   t1, __sbss_end
 z_sbss:
-    sw   zero, 0(a0)
-    addi a0, a0, 4
-    blt  a0, a1, z_sbss
+    sw   zero, 0(t0)
+    addi t0, t0, 4
+    blt  t0, t1, z_sbss
 
     # initialize Newlib
-    la   a0, _impure_ptr
-    lw   a0, 0(a0)
-    call __sinit
+    call __libc_init_array
 
     # restore a0 and a1
     mv a0, s0

advanced/coremark/README.md

@@ -16,17 +16,17 @@ Inspect the results in `run1.log` and `run2.log`:
 ```
 2K performance run parameters for coremark.
 CoreMark Size    : 666
-Total ticks      : 14828555
-Total time (secs): 14
-Iterations/Sec   : 1
-Iterations       : 20
+Total ticks      : 12326926
+Total time (secs): 12
+Iterations/Sec   : 3
+Iterations       : 40
 Compiler version : GCC12.2.0
-Compiler flags   : -march=rv32i_zicsr -mabi=ilp32 -O2 -D_REENT_SMALL -DPERFORMANCE_RUN=1  
+Compiler flags   : -march=rv32im_zicsr -mabi=ilp32 -O2 -D_REENT_SMALL -DPERFORMANCE_RUN=1
 Memory location  : heap
 seedcrc          : 0xe9f5
 [0]crclist       : 0xe714
 [0]crcmatrix     : 0x1fd7
 [0]crcstate      : 0x8e3a
-[0]crcfinal      : 0x4983
+[0]crcfinal      : 0x65c5
 Correct operation validated. See README.md for run and reporting rules.
 ```

advanced/coremark/riscv-emu.py/start_newlib.S

@@ -1,4 +1,4 @@
-    .section .text
+    .section .init
     .globl _start
 
 _start:
@@ -13,25 +13,23 @@ _start:
     mv s1, a1
 
     # initialize .bss
-    la   a0, __bss_start
-    la   a1, __bss_end
+    la   t0, __bss_start
+    la   t1, __bss_end
 z_bss:
-    sw   zero, 0(a0)
-    addi a0, a0, 4
-    blt  a0, a1, z_bss
+    sw   zero, 0(t0)
+    addi t0, t0, 4
+    blt  t0, t1, z_bss
 
     # initialize .sbss
-    la   a0, __sbss_start
-    la   a1, __sbss_end
+    la   t0, __sbss_start
+    la   t1, __sbss_end
 z_sbss:
-    sw   zero, 0(a0)
-    addi a0, a0, 4
-    blt  a0, a1, z_sbss
+    sw   zero, 0(t0)
+    addi t0, t0, 4
+    blt  t0, t1, z_sbss
 
     # initialize Newlib
-    la   a0, _impure_ptr
-    lw   a0, 0(a0)
-    call __sinit
+    call __libc_init_array
 
     # restore a0 and a1
     mv a0, s0

advanced/freertos/port/start.S

@@ -1,4 +1,4 @@
-    .section .text
+    .section .init
     .globl _start
 
 _start:
@@ -13,33 +13,31 @@ _start:
     mv s1, a1
 
     # initialize .bss
-    la   a0, __bss_start
-    la   a1, __bss_end
+    la   t0, __bss_start
+    la   t1, __bss_end
 z_bss:
-    sw   zero, 0(a0)
-    addi a0, a0, 4
-    blt  a0, a1, z_bss
+    sw   zero, 0(t0)
+    addi t0, t0, 4
+    blt  t0, t1, z_bss
 
     # initialize .sbss
-    la   a0, __sbss_start
-    la   a1, __sbss_end
+    la   t0, __sbss_start
+    la   t1, __sbss_end
 z_sbss:
-    sw   zero, 0(a0)
-    addi a0, a0, 4
-    blt  a0, a1, z_sbss
+    sw   zero, 0(t0)
+    addi t0, t0, 4
+    blt  t0, t1, z_sbss
 
-    # initialize Newlib -- uncomment these if your FreeRTOS application needs Newlib-nano
-#    la   a0, _impure_ptr
-#    lw   a0, 0(a0)
-#    call __sinit
+    # initialize Newlib -- uncomment this if your FreeRTOS application needs Newlib-nano
+#    call __libc_init_array
 
     # install trap handler for FreeRTOS
 #if defined(MTIMER_MMIO) && MTIMER_MMIO == 1
-    la a0, freertos_risc_v_trap_handler
+    la t0, freertos_risc_v_trap_handler
 #else
-    la a0, freertos_risc_v_trap_handler_riscvpy
+    la t0, freertos_risc_v_trap_handler_riscvpy
 #endif
-    csrw mtvec, a0
+    csrw mtvec, t0
 
     # restore a0 and a1
     mv a0, s0

advanced/micropython/port-riscv-emu.py/start.S

@@ -13,26 +13,24 @@ _start:
     mv s1, a1
 
     # initialize .bss
-    la   a0, __bss_start
-    la   a1, __bss_end
+    la   t0, __bss_start
+    la   t1, __bss_end
 z_bss:
-    sw   zero, 0(a0)
-    addi a0, a0, 4
-    blt  a0, a1, z_bss
+    sw   zero, 0(t0)
+    addi t0, t0, 4
+    blt  t0, t1, z_bss
 
     # initialize .sbss
-    la   a0, __sbss_start
-    la   a1, __sbss_end
+    la   t0, __sbss_start
+    la   t1, __sbss_end
 z_sbss:
-    sw   zero, 0(a0)
-    addi a0, a0, 4
-    blt  a0, a1, z_sbss
+    sw   zero, 0(t0)
+    addi t0, t0, 4
+    blt  t0, t1, z_sbss
 
 #if (MICROPY_PORT_MODE == MODE_REPL_NEWLIB)
     # initialize Newlib
-    la   a0, _impure_ptr
-    lw   a0, 0(a0)
-    call __sinit
+    call __libc_init_array
 #endif
 
     # restore a0 and a1